./Ultimate.py --spec ../../sv-benchmarks/c/MemSafety.prp --file ../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-write.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for memory safety (deref-memtrack) Using default analysis Version 1dbac8bc Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/config/AutomizerMemDerefMemtrack.xml -i ../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-write.c -s /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/config/svcomp-DerefFreeMemtrack-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 68d161eb03bccd8280d2086bc4cdb7b46f7ee157 ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(valid-deref) --- Real Ultimate output --- This is Ultimate 0.1.23-1dbac8b [2018-11-10 09:58:26,362 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-10 09:58:26,363 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-10 09:58:26,369 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-10 09:58:26,370 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-10 09:58:26,370 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-10 09:58:26,371 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-10 09:58:26,372 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-10 09:58:26,373 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-10 09:58:26,374 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-10 09:58:26,375 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-10 09:58:26,375 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-10 09:58:26,375 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-10 09:58:26,376 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-10 09:58:26,376 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-10 09:58:26,377 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-10 09:58:26,377 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-10 09:58:26,378 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-10 09:58:26,379 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-10 09:58:26,380 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-10 09:58:26,381 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-10 09:58:26,382 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-10 09:58:26,384 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-10 09:58:26,384 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-10 09:58:26,384 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-10 09:58:26,385 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-10 09:58:26,385 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-10 09:58:26,385 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-10 09:58:26,386 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-10 09:58:26,386 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-10 09:58:26,386 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-10 09:58:26,387 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-10 09:58:26,387 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-10 09:58:26,387 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-10 09:58:26,387 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-10 09:58:26,388 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-10 09:58:26,388 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/config/svcomp-DerefFreeMemtrack-32bit-Automizer_Default.epf [2018-11-10 09:58:26,397 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-10 09:58:26,398 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-10 09:58:26,399 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-10 09:58:26,399 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-10 09:58:26,399 INFO L133 SettingsManager]: * Use SBE=true [2018-11-10 09:58:26,399 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-10 09:58:26,399 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-10 09:58:26,399 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-10 09:58:26,399 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-10 09:58:26,400 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-10 09:58:26,400 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-10 09:58:26,400 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-11-10 09:58:26,400 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-11-10 09:58:26,400 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-11-10 09:58:26,400 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-10 09:58:26,400 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-10 09:58:26,401 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-10 09:58:26,401 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-10 09:58:26,401 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-10 09:58:26,401 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-10 09:58:26,401 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-10 09:58:26,401 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-10 09:58:26,401 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-10 09:58:26,401 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-10 09:58:26,402 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-10 09:58:26,402 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 68d161eb03bccd8280d2086bc4cdb7b46f7ee157 [2018-11-10 09:58:26,427 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-10 09:58:26,436 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-10 09:58:26,438 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-10 09:58:26,439 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-10 09:58:26,440 INFO L276 PluginConnector]: CDTParser initialized [2018-11-10 09:58:26,440 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-write.c [2018-11-10 09:58:26,478 INFO L218 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/data/6a4fcc0dc/b637e9161ae64bd99b9438836e5473af/FLAG850bb6449 [2018-11-10 09:58:26,906 INFO L298 CDTParser]: Found 1 translation units. [2018-11-10 09:58:26,906 INFO L158 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-write.c [2018-11-10 09:58:26,911 INFO L346 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/data/6a4fcc0dc/b637e9161ae64bd99b9438836e5473af/FLAG850bb6449 [2018-11-10 09:58:26,923 INFO L354 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/data/6a4fcc0dc/b637e9161ae64bd99b9438836e5473af [2018-11-10 09:58:26,926 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-10 09:58:26,927 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-11-10 09:58:26,928 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-10 09:58:26,928 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-10 09:58:26,931 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-10 09:58:26,931 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.11 09:58:26" (1/1) ... [2018-11-10 09:58:26,933 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@23480a2c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 09:58:26, skipping insertion in model container [2018-11-10 09:58:26,934 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.11 09:58:26" (1/1) ... [2018-11-10 09:58:26,942 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-10 09:58:26,957 INFO L174 MainTranslator]: Built tables and reachable declarations [2018-11-10 09:58:27,067 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-11-10 09:58:27,072 INFO L189 MainTranslator]: Completed pre-run [2018-11-10 09:58:27,083 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-11-10 09:58:27,093 INFO L193 MainTranslator]: Completed translation [2018-11-10 09:58:27,093 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 09:58:27 WrapperNode [2018-11-10 09:58:27,093 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-10 09:58:27,094 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-10 09:58:27,094 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-10 09:58:27,094 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-10 09:58:27,101 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 09:58:27" (1/1) ... [2018-11-10 09:58:27,101 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 09:58:27" (1/1) ... [2018-11-10 09:58:27,106 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 09:58:27" (1/1) ... [2018-11-10 09:58:27,106 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 09:58:27" (1/1) ... [2018-11-10 09:58:27,110 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 09:58:27" (1/1) ... [2018-11-10 09:58:27,113 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 09:58:27" (1/1) ... [2018-11-10 09:58:27,114 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 09:58:27" (1/1) ... [2018-11-10 09:58:27,115 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-10 09:58:27,116 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-10 09:58:27,116 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-10 09:58:27,116 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-10 09:58:27,116 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 09:58:27" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-10 09:58:27,185 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-10 09:58:27,186 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-10 09:58:27,186 INFO L138 BoogieDeclarations]: Found implementation of procedure foo [2018-11-10 09:58:27,186 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-10 09:58:27,186 INFO L130 BoogieDeclarations]: Found specification of procedure foo [2018-11-10 09:58:27,186 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2018-11-10 09:58:27,186 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-10 09:58:27,186 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-10 09:58:27,186 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2018-11-10 09:58:27,187 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-10 09:58:27,187 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-10 09:58:27,187 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-10 09:58:27,187 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~int [2018-11-10 09:58:27,338 INFO L341 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-10 09:58:27,339 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.11 09:58:27 BoogieIcfgContainer [2018-11-10 09:58:27,339 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-10 09:58:27,340 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-10 09:58:27,340 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-10 09:58:27,342 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-10 09:58:27,342 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 10.11 09:58:26" (1/3) ... [2018-11-10 09:58:27,343 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3e18c069 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 10.11 09:58:27, skipping insertion in model container [2018-11-10 09:58:27,343 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 09:58:27" (2/3) ... [2018-11-10 09:58:27,343 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3e18c069 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 10.11 09:58:27, skipping insertion in model container [2018-11-10 09:58:27,344 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.11 09:58:27" (3/3) ... [2018-11-10 09:58:27,345 INFO L112 eAbstractionObserver]: Analyzing ICFG ArraysWithLenghtAtDeclaration_false-valid-deref-write.c [2018-11-10 09:58:27,353 INFO L136 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-10 09:58:27,358 INFO L148 ceAbstractionStarter]: Appying trace abstraction to program that has 8 error locations. [2018-11-10 09:58:27,367 INFO L257 AbstractCegarLoop]: Starting to check reachability of 8 error locations. [2018-11-10 09:58:27,386 INFO L135 ementStrategyFactory]: Using default assertion order modulation [2018-11-10 09:58:27,387 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-10 09:58:27,387 INFO L383 AbstractCegarLoop]: Hoare is false [2018-11-10 09:58:27,387 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-10 09:58:27,387 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-10 09:58:27,387 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-10 09:58:27,387 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-10 09:58:27,387 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-10 09:58:27,388 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-10 09:58:27,401 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states. [2018-11-10 09:58:27,408 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-11-10 09:58:27,408 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:58:27,409 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:58:27,410 INFO L424 AbstractCegarLoop]: === Iteration 1 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:58:27,413 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:58:27,413 INFO L82 PathProgramCache]: Analyzing trace with hash -1496656545, now seen corresponding path program 1 times [2018-11-10 09:58:27,414 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:58:27,415 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:58:27,449 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:27,449 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 09:58:27,450 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:27,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:27,498 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 09:58:27,499 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 09:58:27,499 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 09:58:27,501 INFO L460 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-11-10 09:58:27,509 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-11-10 09:58:27,510 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-11-10 09:58:27,511 INFO L87 Difference]: Start difference. First operand 54 states. Second operand 2 states. [2018-11-10 09:58:27,522 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:58:27,522 INFO L93 Difference]: Finished difference Result 54 states and 57 transitions. [2018-11-10 09:58:27,522 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-11-10 09:58:27,523 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 14 [2018-11-10 09:58:27,523 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:58:27,529 INFO L225 Difference]: With dead ends: 54 [2018-11-10 09:58:27,529 INFO L226 Difference]: Without dead ends: 51 [2018-11-10 09:58:27,530 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-11-10 09:58:27,540 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51 states. [2018-11-10 09:58:27,549 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51 to 51. [2018-11-10 09:58:27,550 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51 states. [2018-11-10 09:58:27,551 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 54 transitions. [2018-11-10 09:58:27,552 INFO L78 Accepts]: Start accepts. Automaton has 51 states and 54 transitions. Word has length 14 [2018-11-10 09:58:27,552 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:58:27,553 INFO L481 AbstractCegarLoop]: Abstraction has 51 states and 54 transitions. [2018-11-10 09:58:27,553 INFO L482 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-11-10 09:58:27,553 INFO L276 IsEmpty]: Start isEmpty. Operand 51 states and 54 transitions. [2018-11-10 09:58:27,553 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-11-10 09:58:27,553 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:58:27,553 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:58:27,554 INFO L424 AbstractCegarLoop]: === Iteration 2 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:58:27,554 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:58:27,554 INFO L82 PathProgramCache]: Analyzing trace with hash 405796804, now seen corresponding path program 1 times [2018-11-10 09:58:27,554 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:58:27,554 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:58:27,555 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:27,555 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 09:58:27,555 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:27,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:27,598 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 09:58:27,598 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 09:58:27,598 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 09:58:27,600 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-10 09:58:27,600 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 09:58:27,600 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 09:58:27,600 INFO L87 Difference]: Start difference. First operand 51 states and 54 transitions. Second operand 3 states. [2018-11-10 09:58:27,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:58:27,670 INFO L93 Difference]: Finished difference Result 74 states and 78 transitions. [2018-11-10 09:58:27,670 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 09:58:27,670 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 15 [2018-11-10 09:58:27,670 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:58:27,672 INFO L225 Difference]: With dead ends: 74 [2018-11-10 09:58:27,672 INFO L226 Difference]: Without dead ends: 74 [2018-11-10 09:58:27,672 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 09:58:27,673 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74 states. [2018-11-10 09:58:27,678 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74 to 55. [2018-11-10 09:58:27,678 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 55 states. [2018-11-10 09:58:27,679 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 58 transitions. [2018-11-10 09:58:27,679 INFO L78 Accepts]: Start accepts. Automaton has 55 states and 58 transitions. Word has length 15 [2018-11-10 09:58:27,679 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:58:27,679 INFO L481 AbstractCegarLoop]: Abstraction has 55 states and 58 transitions. [2018-11-10 09:58:27,679 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-10 09:58:27,679 INFO L276 IsEmpty]: Start isEmpty. Operand 55 states and 58 transitions. [2018-11-10 09:58:27,680 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-11-10 09:58:27,680 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:58:27,680 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:58:27,680 INFO L424 AbstractCegarLoop]: === Iteration 3 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:58:27,680 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:58:27,680 INFO L82 PathProgramCache]: Analyzing trace with hash -213588543, now seen corresponding path program 1 times [2018-11-10 09:58:27,680 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:58:27,681 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:58:27,681 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:27,681 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 09:58:27,681 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:27,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:27,710 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 09:58:27,710 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 09:58:27,710 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 09:58:27,710 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-10 09:58:27,711 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 09:58:27,711 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 09:58:27,711 INFO L87 Difference]: Start difference. First operand 55 states and 58 transitions. Second operand 3 states. [2018-11-10 09:58:27,755 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:58:27,755 INFO L93 Difference]: Finished difference Result 66 states and 70 transitions. [2018-11-10 09:58:27,756 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 09:58:27,756 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 16 [2018-11-10 09:58:27,756 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:58:27,758 INFO L225 Difference]: With dead ends: 66 [2018-11-10 09:58:27,758 INFO L226 Difference]: Without dead ends: 66 [2018-11-10 09:58:27,759 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 09:58:27,759 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66 states. [2018-11-10 09:58:27,762 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66 to 58. [2018-11-10 09:58:27,762 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 58 states. [2018-11-10 09:58:27,763 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 62 transitions. [2018-11-10 09:58:27,763 INFO L78 Accepts]: Start accepts. Automaton has 58 states and 62 transitions. Word has length 16 [2018-11-10 09:58:27,763 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:58:27,763 INFO L481 AbstractCegarLoop]: Abstraction has 58 states and 62 transitions. [2018-11-10 09:58:27,763 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-10 09:58:27,763 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states and 62 transitions. [2018-11-10 09:58:27,763 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-11-10 09:58:27,764 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:58:27,764 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:58:27,764 INFO L424 AbstractCegarLoop]: === Iteration 4 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:58:27,764 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:58:27,764 INFO L82 PathProgramCache]: Analyzing trace with hash 1968689806, now seen corresponding path program 1 times [2018-11-10 09:58:27,766 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:58:27,766 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:58:27,767 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:27,767 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 09:58:27,767 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:27,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:27,857 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 09:58:27,858 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 09:58:27,858 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 09:58:27,858 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-10 09:58:27,858 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-10 09:58:27,858 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-11-10 09:58:27,858 INFO L87 Difference]: Start difference. First operand 58 states and 62 transitions. Second operand 6 states. [2018-11-10 09:58:27,942 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:58:27,942 INFO L93 Difference]: Finished difference Result 60 states and 64 transitions. [2018-11-10 09:58:27,942 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-10 09:58:27,943 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 17 [2018-11-10 09:58:27,943 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:58:27,943 INFO L225 Difference]: With dead ends: 60 [2018-11-10 09:58:27,943 INFO L226 Difference]: Without dead ends: 60 [2018-11-10 09:58:27,944 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2018-11-10 09:58:27,944 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states. [2018-11-10 09:58:27,946 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 57. [2018-11-10 09:58:27,946 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 57 states. [2018-11-10 09:58:27,947 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 61 transitions. [2018-11-10 09:58:27,947 INFO L78 Accepts]: Start accepts. Automaton has 57 states and 61 transitions. Word has length 17 [2018-11-10 09:58:27,947 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:58:27,947 INFO L481 AbstractCegarLoop]: Abstraction has 57 states and 61 transitions. [2018-11-10 09:58:27,947 INFO L482 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-10 09:58:27,948 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 61 transitions. [2018-11-10 09:58:27,948 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-11-10 09:58:27,948 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:58:27,948 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:58:27,948 INFO L424 AbstractCegarLoop]: === Iteration 5 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:58:27,948 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:58:27,949 INFO L82 PathProgramCache]: Analyzing trace with hash 1968689805, now seen corresponding path program 1 times [2018-11-10 09:58:27,949 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:58:27,949 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:58:27,949 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:27,949 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 09:58:27,950 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:27,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:27,987 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 09:58:27,988 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 09:58:27,988 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-10 09:58:27,988 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-10 09:58:27,988 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 09:58:27,988 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 09:58:27,989 INFO L87 Difference]: Start difference. First operand 57 states and 61 transitions. Second operand 5 states. [2018-11-10 09:58:28,061 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:58:28,062 INFO L93 Difference]: Finished difference Result 56 states and 60 transitions. [2018-11-10 09:58:28,062 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-10 09:58:28,062 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 17 [2018-11-10 09:58:28,062 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:58:28,062 INFO L225 Difference]: With dead ends: 56 [2018-11-10 09:58:28,062 INFO L226 Difference]: Without dead ends: 56 [2018-11-10 09:58:28,063 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-10 09:58:28,063 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56 states. [2018-11-10 09:58:28,064 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56 to 56. [2018-11-10 09:58:28,064 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 56 states. [2018-11-10 09:58:28,065 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56 states to 56 states and 60 transitions. [2018-11-10 09:58:28,065 INFO L78 Accepts]: Start accepts. Automaton has 56 states and 60 transitions. Word has length 17 [2018-11-10 09:58:28,065 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:58:28,065 INFO L481 AbstractCegarLoop]: Abstraction has 56 states and 60 transitions. [2018-11-10 09:58:28,065 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-10 09:58:28,065 INFO L276 IsEmpty]: Start isEmpty. Operand 56 states and 60 transitions. [2018-11-10 09:58:28,065 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-11-10 09:58:28,065 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:58:28,066 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:58:28,066 INFO L424 AbstractCegarLoop]: === Iteration 6 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:58:28,066 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:58:28,066 INFO L82 PathProgramCache]: Analyzing trace with hash 1411888660, now seen corresponding path program 1 times [2018-11-10 09:58:28,066 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:58:28,066 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:58:28,066 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:28,067 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 09:58:28,067 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:28,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:28,110 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 09:58:28,110 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 09:58:28,110 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 09:58:28,110 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-10 09:58:28,111 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 09:58:28,111 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 09:58:28,111 INFO L87 Difference]: Start difference. First operand 56 states and 60 transitions. Second operand 3 states. [2018-11-10 09:58:28,126 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:58:28,126 INFO L93 Difference]: Finished difference Result 54 states and 58 transitions. [2018-11-10 09:58:28,126 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 09:58:28,126 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 20 [2018-11-10 09:58:28,127 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:58:28,127 INFO L225 Difference]: With dead ends: 54 [2018-11-10 09:58:28,127 INFO L226 Difference]: Without dead ends: 54 [2018-11-10 09:58:28,127 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 09:58:28,128 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2018-11-10 09:58:28,129 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 54. [2018-11-10 09:58:28,129 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2018-11-10 09:58:28,129 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 58 transitions. [2018-11-10 09:58:28,130 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 58 transitions. Word has length 20 [2018-11-10 09:58:28,130 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:58:28,130 INFO L481 AbstractCegarLoop]: Abstraction has 54 states and 58 transitions. [2018-11-10 09:58:28,130 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-10 09:58:28,130 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 58 transitions. [2018-11-10 09:58:28,130 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-11-10 09:58:28,130 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:58:28,130 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:58:28,131 INFO L424 AbstractCegarLoop]: === Iteration 7 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:58:28,131 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:58:28,131 INFO L82 PathProgramCache]: Analyzing trace with hash 1411888661, now seen corresponding path program 1 times [2018-11-10 09:58:28,131 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:58:28,131 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:58:28,132 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:28,132 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 09:58:28,132 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:28,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:28,187 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 09:58:28,188 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 09:58:28,188 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-10 09:58:28,188 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-10 09:58:28,188 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-10 09:58:28,188 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-11-10 09:58:28,188 INFO L87 Difference]: Start difference. First operand 54 states and 58 transitions. Second operand 6 states. [2018-11-10 09:58:28,284 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:58:28,284 INFO L93 Difference]: Finished difference Result 77 states and 82 transitions. [2018-11-10 09:58:28,284 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-10 09:58:28,284 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 20 [2018-11-10 09:58:28,285 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:58:28,285 INFO L225 Difference]: With dead ends: 77 [2018-11-10 09:58:28,285 INFO L226 Difference]: Without dead ends: 77 [2018-11-10 09:58:28,285 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-10 09:58:28,285 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77 states. [2018-11-10 09:58:28,287 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77 to 58. [2018-11-10 09:58:28,287 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 58 states. [2018-11-10 09:58:28,288 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 63 transitions. [2018-11-10 09:58:28,288 INFO L78 Accepts]: Start accepts. Automaton has 58 states and 63 transitions. Word has length 20 [2018-11-10 09:58:28,288 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:58:28,288 INFO L481 AbstractCegarLoop]: Abstraction has 58 states and 63 transitions. [2018-11-10 09:58:28,288 INFO L482 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-10 09:58:28,288 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states and 63 transitions. [2018-11-10 09:58:28,288 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-11-10 09:58:28,288 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:58:28,289 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:58:28,289 INFO L424 AbstractCegarLoop]: === Iteration 8 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:58:28,289 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:58:28,289 INFO L82 PathProgramCache]: Analyzing trace with hash -1835389063, now seen corresponding path program 1 times [2018-11-10 09:58:28,289 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:58:28,289 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:58:28,290 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:28,290 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 09:58:28,290 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:28,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:28,309 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 09:58:28,309 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:58:28,310 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:58:28,328 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 09:58:28,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:28,353 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:58:28,374 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 09:58:28,400 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:58:28,400 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3] total 3 [2018-11-10 09:58:28,400 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-10 09:58:28,400 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-10 09:58:28,401 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-10 09:58:28,401 INFO L87 Difference]: Start difference. First operand 58 states and 63 transitions. Second operand 4 states. [2018-11-10 09:58:28,432 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:58:28,432 INFO L93 Difference]: Finished difference Result 70 states and 77 transitions. [2018-11-10 09:58:28,433 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-10 09:58:28,433 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 22 [2018-11-10 09:58:28,433 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:58:28,434 INFO L225 Difference]: With dead ends: 70 [2018-11-10 09:58:28,434 INFO L226 Difference]: Without dead ends: 70 [2018-11-10 09:58:28,434 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 20 SyntacticMatches, 3 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-10 09:58:28,434 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70 states. [2018-11-10 09:58:28,438 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70 to 64. [2018-11-10 09:58:28,438 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 64 states. [2018-11-10 09:58:28,439 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64 states to 64 states and 70 transitions. [2018-11-10 09:58:28,439 INFO L78 Accepts]: Start accepts. Automaton has 64 states and 70 transitions. Word has length 22 [2018-11-10 09:58:28,439 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:58:28,440 INFO L481 AbstractCegarLoop]: Abstraction has 64 states and 70 transitions. [2018-11-10 09:58:28,440 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-10 09:58:28,440 INFO L276 IsEmpty]: Start isEmpty. Operand 64 states and 70 transitions. [2018-11-10 09:58:28,440 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-11-10 09:58:28,440 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:58:28,441 INFO L375 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:58:28,441 INFO L424 AbstractCegarLoop]: === Iteration 9 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:58:28,441 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:58:28,441 INFO L82 PathProgramCache]: Analyzing trace with hash 1339122637, now seen corresponding path program 1 times [2018-11-10 09:58:28,441 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:58:28,441 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:58:28,442 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:28,442 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 09:58:28,442 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:28,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:28,482 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 09:58:28,482 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:58:28,482 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:58:28,487 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 09:58:28,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:28,500 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:58:28,548 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 09:58:28,563 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:58:28,563 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 9 [2018-11-10 09:58:28,564 INFO L460 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-10 09:58:28,564 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-10 09:58:28,564 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=50, Unknown=0, NotChecked=0, Total=72 [2018-11-10 09:58:28,564 INFO L87 Difference]: Start difference. First operand 64 states and 70 transitions. Second operand 9 states. [2018-11-10 09:58:28,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:58:28,669 INFO L93 Difference]: Finished difference Result 86 states and 90 transitions. [2018-11-10 09:58:28,670 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-10 09:58:28,670 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 26 [2018-11-10 09:58:28,670 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:58:28,670 INFO L225 Difference]: With dead ends: 86 [2018-11-10 09:58:28,670 INFO L226 Difference]: Without dead ends: 80 [2018-11-10 09:58:28,671 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 23 SyntacticMatches, 1 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=35, Invalid=75, Unknown=0, NotChecked=0, Total=110 [2018-11-10 09:58:28,671 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states. [2018-11-10 09:58:28,673 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 60. [2018-11-10 09:58:28,673 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2018-11-10 09:58:28,673 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 63 transitions. [2018-11-10 09:58:28,673 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 63 transitions. Word has length 26 [2018-11-10 09:58:28,673 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:58:28,673 INFO L481 AbstractCegarLoop]: Abstraction has 60 states and 63 transitions. [2018-11-10 09:58:28,674 INFO L482 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-10 09:58:28,674 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 63 transitions. [2018-11-10 09:58:28,674 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-11-10 09:58:28,674 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:58:28,674 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:58:28,674 INFO L424 AbstractCegarLoop]: === Iteration 10 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:58:28,674 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:58:28,675 INFO L82 PathProgramCache]: Analyzing trace with hash 1250905905, now seen corresponding path program 2 times [2018-11-10 09:58:28,675 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:58:28,675 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:58:28,675 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:28,675 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 09:58:28,675 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:28,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:28,736 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 7 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 09:58:28,737 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:58:28,737 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:58:28,748 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-10 09:58:28,761 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-10 09:58:28,761 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 09:58:28,763 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:58:28,816 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 09:58:28,832 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-10 09:58:28,832 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [8] total 12 [2018-11-10 09:58:28,832 INFO L460 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-11-10 09:58:28,832 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-11-10 09:58:28,832 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=95, Unknown=0, NotChecked=0, Total=132 [2018-11-10 09:58:28,833 INFO L87 Difference]: Start difference. First operand 60 states and 63 transitions. Second operand 12 states. [2018-11-10 09:58:28,969 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:58:28,969 INFO L93 Difference]: Finished difference Result 95 states and 98 transitions. [2018-11-10 09:58:28,969 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-10 09:58:28,969 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 28 [2018-11-10 09:58:28,970 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:58:28,970 INFO L225 Difference]: With dead ends: 95 [2018-11-10 09:58:28,970 INFO L226 Difference]: Without dead ends: 95 [2018-11-10 09:58:28,971 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 24 SyntacticMatches, 1 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=64, Invalid=146, Unknown=0, NotChecked=0, Total=210 [2018-11-10 09:58:28,971 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95 states. [2018-11-10 09:58:28,973 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95 to 79. [2018-11-10 09:58:28,973 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 79 states. [2018-11-10 09:58:28,973 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79 states to 79 states and 82 transitions. [2018-11-10 09:58:28,974 INFO L78 Accepts]: Start accepts. Automaton has 79 states and 82 transitions. Word has length 28 [2018-11-10 09:58:28,974 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:58:28,974 INFO L481 AbstractCegarLoop]: Abstraction has 79 states and 82 transitions. [2018-11-10 09:58:28,974 INFO L482 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-11-10 09:58:28,974 INFO L276 IsEmpty]: Start isEmpty. Operand 79 states and 82 transitions. [2018-11-10 09:58:28,975 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-11-10 09:58:28,975 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:58:28,975 INFO L375 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:58:28,976 INFO L424 AbstractCegarLoop]: === Iteration 11 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:58:28,976 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:58:28,976 INFO L82 PathProgramCache]: Analyzing trace with hash -1002444923, now seen corresponding path program 2 times [2018-11-10 09:58:28,976 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:58:28,976 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:58:28,977 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:28,977 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 09:58:28,977 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:28,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:29,029 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-10 09:58:29,030 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 09:58:29,030 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 09:58:29,030 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-10 09:58:29,031 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-10 09:58:29,031 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-10 09:58:29,031 INFO L87 Difference]: Start difference. First operand 79 states and 82 transitions. Second operand 6 states. [2018-11-10 09:58:29,133 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:58:29,133 INFO L93 Difference]: Finished difference Result 89 states and 93 transitions. [2018-11-10 09:58:29,134 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-10 09:58:29,134 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 32 [2018-11-10 09:58:29,134 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:58:29,134 INFO L225 Difference]: With dead ends: 89 [2018-11-10 09:58:29,135 INFO L226 Difference]: Without dead ends: 89 [2018-11-10 09:58:29,135 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-11-10 09:58:29,135 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 89 states. [2018-11-10 09:58:29,137 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 89 to 82. [2018-11-10 09:58:29,137 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 82 states. [2018-11-10 09:58:29,138 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 85 transitions. [2018-11-10 09:58:29,138 INFO L78 Accepts]: Start accepts. Automaton has 82 states and 85 transitions. Word has length 32 [2018-11-10 09:58:29,138 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:58:29,138 INFO L481 AbstractCegarLoop]: Abstraction has 82 states and 85 transitions. [2018-11-10 09:58:29,138 INFO L482 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-10 09:58:29,138 INFO L276 IsEmpty]: Start isEmpty. Operand 82 states and 85 transitions. [2018-11-10 09:58:29,139 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-11-10 09:58:29,139 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:58:29,139 INFO L375 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:58:29,140 INFO L424 AbstractCegarLoop]: === Iteration 12 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:58:29,140 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:58:29,140 INFO L82 PathProgramCache]: Analyzing trace with hash -627429204, now seen corresponding path program 1 times [2018-11-10 09:58:29,140 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:58:29,140 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:58:29,141 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:29,141 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 09:58:29,141 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:29,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:29,185 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 2 proven. 7 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-11-10 09:58:29,186 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:58:29,186 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:58:29,193 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 09:58:29,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:29,209 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:58:29,257 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-11-10 09:58:29,274 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:58:29,274 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 4] total 10 [2018-11-10 09:58:29,275 INFO L460 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-10 09:58:29,275 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-10 09:58:29,275 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2018-11-10 09:58:29,275 INFO L87 Difference]: Start difference. First operand 82 states and 85 transitions. Second operand 10 states. [2018-11-10 09:58:29,356 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:58:29,356 INFO L93 Difference]: Finished difference Result 90 states and 94 transitions. [2018-11-10 09:58:29,356 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-10 09:58:29,356 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 45 [2018-11-10 09:58:29,357 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:58:29,357 INFO L225 Difference]: With dead ends: 90 [2018-11-10 09:58:29,357 INFO L226 Difference]: Without dead ends: 90 [2018-11-10 09:58:29,357 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 58 GetRequests, 46 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=49, Invalid=133, Unknown=0, NotChecked=0, Total=182 [2018-11-10 09:58:29,358 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90 states. [2018-11-10 09:58:29,359 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90 to 60. [2018-11-10 09:58:29,359 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2018-11-10 09:58:29,359 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 61 transitions. [2018-11-10 09:58:29,360 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 61 transitions. Word has length 45 [2018-11-10 09:58:29,360 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:58:29,360 INFO L481 AbstractCegarLoop]: Abstraction has 60 states and 61 transitions. [2018-11-10 09:58:29,360 INFO L482 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-10 09:58:29,360 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 61 transitions. [2018-11-10 09:58:29,361 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-11-10 09:58:29,361 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:58:29,361 INFO L375 BasicCegarLoop]: trace histogram [6, 5, 4, 4, 4, 4, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:58:29,361 INFO L424 AbstractCegarLoop]: === Iteration 13 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:58:29,361 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:58:29,361 INFO L82 PathProgramCache]: Analyzing trace with hash 921180166, now seen corresponding path program 1 times [2018-11-10 09:58:29,361 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:58:29,361 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:58:29,362 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:29,362 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 09:58:29,362 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:29,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:29,415 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 36 proven. 12 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-11-10 09:58:29,415 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:58:29,416 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:58:29,424 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 09:58:29,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:29,442 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:58:29,453 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 36 proven. 12 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-11-10 09:58:29,472 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:58:29,472 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 4 [2018-11-10 09:58:29,472 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-10 09:58:29,473 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 09:58:29,473 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 09:58:29,473 INFO L87 Difference]: Start difference. First operand 60 states and 61 transitions. Second operand 5 states. [2018-11-10 09:58:29,497 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:58:29,497 INFO L93 Difference]: Finished difference Result 72 states and 74 transitions. [2018-11-10 09:58:29,497 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-10 09:58:29,497 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 53 [2018-11-10 09:58:29,498 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:58:29,498 INFO L225 Difference]: With dead ends: 72 [2018-11-10 09:58:29,498 INFO L226 Difference]: Without dead ends: 72 [2018-11-10 09:58:29,498 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 57 GetRequests, 51 SyntacticMatches, 3 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 09:58:29,498 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72 states. [2018-11-10 09:58:29,500 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72 to 66. [2018-11-10 09:58:29,500 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 66 states. [2018-11-10 09:58:29,501 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 68 transitions. [2018-11-10 09:58:29,501 INFO L78 Accepts]: Start accepts. Automaton has 66 states and 68 transitions. Word has length 53 [2018-11-10 09:58:29,501 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:58:29,501 INFO L481 AbstractCegarLoop]: Abstraction has 66 states and 68 transitions. [2018-11-10 09:58:29,501 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-10 09:58:29,501 INFO L276 IsEmpty]: Start isEmpty. Operand 66 states and 68 transitions. [2018-11-10 09:58:29,502 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-11-10 09:58:29,502 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:58:29,502 INFO L375 BasicCegarLoop]: trace histogram [6, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:58:29,502 INFO L424 AbstractCegarLoop]: === Iteration 14 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:58:29,502 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:58:29,502 INFO L82 PathProgramCache]: Analyzing trace with hash -760332838, now seen corresponding path program 1 times [2018-11-10 09:58:29,502 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:58:29,502 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:58:29,503 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:29,503 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 09:58:29,503 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:29,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:29,618 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 5 proven. 57 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-11-10 09:58:29,618 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:58:29,618 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:58:29,624 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 09:58:29,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:29,642 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:58:29,689 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 42 proven. 10 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-11-10 09:58:29,706 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:58:29,706 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 8] total 15 [2018-11-10 09:58:29,707 INFO L460 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-11-10 09:58:29,707 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-11-10 09:58:29,707 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=43, Invalid=167, Unknown=0, NotChecked=0, Total=210 [2018-11-10 09:58:29,707 INFO L87 Difference]: Start difference. First operand 66 states and 68 transitions. Second operand 15 states. [2018-11-10 09:58:29,835 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:58:29,836 INFO L93 Difference]: Finished difference Result 74 states and 75 transitions. [2018-11-10 09:58:29,836 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-10 09:58:29,836 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 57 [2018-11-10 09:58:29,836 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:58:29,837 INFO L225 Difference]: With dead ends: 74 [2018-11-10 09:58:29,837 INFO L226 Difference]: Without dead ends: 71 [2018-11-10 09:58:29,837 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 74 GetRequests, 56 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 48 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=92, Invalid=288, Unknown=0, NotChecked=0, Total=380 [2018-11-10 09:58:29,837 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71 states. [2018-11-10 09:58:29,838 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71 to 66. [2018-11-10 09:58:29,838 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 66 states. [2018-11-10 09:58:29,839 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 67 transitions. [2018-11-10 09:58:29,839 INFO L78 Accepts]: Start accepts. Automaton has 66 states and 67 transitions. Word has length 57 [2018-11-10 09:58:29,839 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:58:29,839 INFO L481 AbstractCegarLoop]: Abstraction has 66 states and 67 transitions. [2018-11-10 09:58:29,839 INFO L482 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-11-10 09:58:29,839 INFO L276 IsEmpty]: Start isEmpty. Operand 66 states and 67 transitions. [2018-11-10 09:58:29,840 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-11-10 09:58:29,841 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:58:29,841 INFO L375 BasicCegarLoop]: trace histogram [7, 6, 5, 5, 5, 5, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:58:29,841 INFO L424 AbstractCegarLoop]: === Iteration 15 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:58:29,841 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:58:29,841 INFO L82 PathProgramCache]: Analyzing trace with hash -1986143746, now seen corresponding path program 2 times [2018-11-10 09:58:29,841 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:58:29,842 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:58:29,842 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:29,842 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 09:58:29,842 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:29,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:29,902 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 70 proven. 11 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-10 09:58:29,902 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:58:29,902 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:58:29,907 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-10 09:58:29,923 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-10 09:58:29,923 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 09:58:29,925 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:58:29,983 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 78 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-10 09:58:29,999 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:58:29,999 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9] total 15 [2018-11-10 09:58:30,000 INFO L460 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-11-10 09:58:30,000 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-11-10 09:58:30,000 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=56, Invalid=154, Unknown=0, NotChecked=0, Total=210 [2018-11-10 09:58:30,000 INFO L87 Difference]: Start difference. First operand 66 states and 67 transitions. Second operand 15 states. [2018-11-10 09:58:30,123 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:58:30,123 INFO L93 Difference]: Finished difference Result 100 states and 101 transitions. [2018-11-10 09:58:30,124 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-10 09:58:30,124 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 59 [2018-11-10 09:58:30,124 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:58:30,124 INFO L225 Difference]: With dead ends: 100 [2018-11-10 09:58:30,125 INFO L226 Difference]: Without dead ends: 100 [2018-11-10 09:58:30,125 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 73 GetRequests, 55 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 38 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=113, Invalid=267, Unknown=0, NotChecked=0, Total=380 [2018-11-10 09:58:30,125 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states. [2018-11-10 09:58:30,127 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 95. [2018-11-10 09:58:30,127 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 95 states. [2018-11-10 09:58:30,127 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 96 transitions. [2018-11-10 09:58:30,128 INFO L78 Accepts]: Start accepts. Automaton has 95 states and 96 transitions. Word has length 59 [2018-11-10 09:58:30,128 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:58:30,128 INFO L481 AbstractCegarLoop]: Abstraction has 95 states and 96 transitions. [2018-11-10 09:58:30,128 INFO L482 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-11-10 09:58:30,128 INFO L276 IsEmpty]: Start isEmpty. Operand 95 states and 96 transitions. [2018-11-10 09:58:30,129 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2018-11-10 09:58:30,130 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:58:30,130 INFO L375 BasicCegarLoop]: trace histogram [7, 5, 5, 5, 5, 5, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:58:30,130 INFO L424 AbstractCegarLoop]: === Iteration 16 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:58:30,130 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:58:30,130 INFO L82 PathProgramCache]: Analyzing trace with hash 1883390930, now seen corresponding path program 2 times [2018-11-10 09:58:30,130 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:58:30,130 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:58:30,131 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:30,131 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 09:58:30,131 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:30,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:30,263 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 46 trivial. 0 not checked. [2018-11-10 09:58:30,264 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:58:30,264 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:58:30,278 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-10 09:58:30,295 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-10 09:58:30,295 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 09:58:30,297 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:58:30,317 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-10 09:58:30,318 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-10 09:58:30,323 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-10 09:58:30,323 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-10 09:58:30,326 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-10 09:58:30,327 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:16, output treesize:14 [2018-11-10 09:58:30,336 INFO L700 Elim1Store]: detected not equals via solver [2018-11-10 09:58:30,337 INFO L700 Elim1Store]: detected not equals via solver [2018-11-10 09:58:30,337 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-11-10 09:58:30,338 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-10 09:58:30,344 INFO L700 Elim1Store]: detected not equals via solver [2018-11-10 09:58:30,345 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 21 [2018-11-10 09:58:30,345 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-10 09:58:30,350 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-10 09:58:30,351 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:25, output treesize:14 [2018-11-10 09:58:30,494 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 86 trivial. 0 not checked. [2018-11-10 09:58:30,511 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:58:30,511 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 12 [2018-11-10 09:58:30,511 INFO L460 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-10 09:58:30,511 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-10 09:58:30,511 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=117, Unknown=0, NotChecked=0, Total=156 [2018-11-10 09:58:30,512 INFO L87 Difference]: Start difference. First operand 95 states and 96 transitions. Second operand 13 states. [2018-11-10 09:58:30,595 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:58:30,595 INFO L93 Difference]: Finished difference Result 99 states and 100 transitions. [2018-11-10 09:58:30,597 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-10 09:58:30,597 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 63 [2018-11-10 09:58:30,597 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:58:30,597 INFO L225 Difference]: With dead ends: 99 [2018-11-10 09:58:30,597 INFO L226 Difference]: Without dead ends: 99 [2018-11-10 09:58:30,598 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 76 GetRequests, 59 SyntacticMatches, 2 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 48 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=69, Invalid=203, Unknown=0, NotChecked=0, Total=272 [2018-11-10 09:58:30,598 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states. [2018-11-10 09:58:30,600 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 97. [2018-11-10 09:58:30,600 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 97 states. [2018-11-10 09:58:30,600 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 98 transitions. [2018-11-10 09:58:30,601 INFO L78 Accepts]: Start accepts. Automaton has 97 states and 98 transitions. Word has length 63 [2018-11-10 09:58:30,601 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:58:30,601 INFO L481 AbstractCegarLoop]: Abstraction has 97 states and 98 transitions. [2018-11-10 09:58:30,601 INFO L482 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-10 09:58:30,601 INFO L276 IsEmpty]: Start isEmpty. Operand 97 states and 98 transitions. [2018-11-10 09:58:30,602 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-11-10 09:58:30,602 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:58:30,602 INFO L375 BasicCegarLoop]: trace histogram [11, 9, 8, 8, 8, 8, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:58:30,602 INFO L424 AbstractCegarLoop]: === Iteration 17 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:58:30,602 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:58:30,602 INFO L82 PathProgramCache]: Analyzing trace with hash -102681199, now seen corresponding path program 3 times [2018-11-10 09:58:30,602 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:58:30,603 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:58:30,603 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:30,603 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 09:58:30,603 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:30,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:30,678 INFO L134 CoverageAnalysis]: Checked inductivity of 249 backedges. 135 proven. 16 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-11-10 09:58:30,678 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:58:30,678 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:58:30,685 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-10 09:58:30,728 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2018-11-10 09:58:30,728 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 09:58:30,732 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:58:30,752 INFO L134 CoverageAnalysis]: Checked inductivity of 249 backedges. 135 proven. 16 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-11-10 09:58:30,769 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:58:30,769 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 10 [2018-11-10 09:58:30,769 INFO L460 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-10 09:58:30,770 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-10 09:58:30,770 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=82, Unknown=0, NotChecked=0, Total=110 [2018-11-10 09:58:30,770 INFO L87 Difference]: Start difference. First operand 97 states and 98 transitions. Second operand 11 states. [2018-11-10 09:58:30,866 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:58:30,866 INFO L93 Difference]: Finished difference Result 132 states and 134 transitions. [2018-11-10 09:58:30,867 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-10 09:58:30,867 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 90 [2018-11-10 09:58:30,867 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:58:30,868 INFO L225 Difference]: With dead ends: 132 [2018-11-10 09:58:30,868 INFO L226 Difference]: Without dead ends: 132 [2018-11-10 09:58:30,868 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 101 GetRequests, 89 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=49, Invalid=133, Unknown=0, NotChecked=0, Total=182 [2018-11-10 09:58:30,868 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states. [2018-11-10 09:58:30,870 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 126. [2018-11-10 09:58:30,870 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 126 states. [2018-11-10 09:58:30,871 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 126 states to 126 states and 128 transitions. [2018-11-10 09:58:30,871 INFO L78 Accepts]: Start accepts. Automaton has 126 states and 128 transitions. Word has length 90 [2018-11-10 09:58:30,871 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:58:30,871 INFO L481 AbstractCegarLoop]: Abstraction has 126 states and 128 transitions. [2018-11-10 09:58:30,871 INFO L482 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-10 09:58:30,871 INFO L276 IsEmpty]: Start isEmpty. Operand 126 states and 128 transitions. [2018-11-10 09:58:30,872 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-11-10 09:58:30,872 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:58:30,872 INFO L375 BasicCegarLoop]: trace histogram [11, 8, 8, 8, 8, 8, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:58:30,872 INFO L424 AbstractCegarLoop]: === Iteration 18 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:58:30,873 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:58:30,873 INFO L82 PathProgramCache]: Analyzing trace with hash 293051877, now seen corresponding path program 3 times [2018-11-10 09:58:30,873 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:58:30,873 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:58:30,873 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:30,873 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 09:58:30,874 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:30,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:30,991 INFO L134 CoverageAnalysis]: Checked inductivity of 251 backedges. 88 proven. 136 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-11-10 09:58:30,992 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:58:30,992 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:58:31,002 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-10 09:58:31,015 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2018-11-10 09:58:31,015 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 09:58:31,018 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:58:31,020 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-10 09:58:31,021 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-10 09:58:31,028 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-10 09:58:31,028 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-10 09:58:31,032 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-10 09:58:31,032 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:16, output treesize:14 [2018-11-10 09:58:31,065 INFO L700 Elim1Store]: detected not equals via solver [2018-11-10 09:58:31,065 INFO L700 Elim1Store]: detected not equals via solver [2018-11-10 09:58:31,066 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 21 [2018-11-10 09:58:31,066 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-10 09:58:31,074 INFO L700 Elim1Store]: detected not equals via solver [2018-11-10 09:58:31,075 INFO L700 Elim1Store]: detected not equals via solver [2018-11-10 09:58:31,076 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-11-10 09:58:31,076 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-10 09:58:31,080 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-10 09:58:31,080 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:25, output treesize:14 [2018-11-10 09:58:31,339 INFO L134 CoverageAnalysis]: Checked inductivity of 251 backedges. 8 proven. 4 refuted. 0 times theorem prover too weak. 239 trivial. 0 not checked. [2018-11-10 09:58:31,356 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:58:31,356 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 8] total 21 [2018-11-10 09:58:31,357 INFO L460 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-10 09:58:31,357 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-10 09:58:31,357 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=68, Invalid=352, Unknown=0, NotChecked=0, Total=420 [2018-11-10 09:58:31,357 INFO L87 Difference]: Start difference. First operand 126 states and 128 transitions. Second operand 21 states. [2018-11-10 09:58:31,716 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:58:31,716 INFO L93 Difference]: Finished difference Result 151 states and 153 transitions. [2018-11-10 09:58:31,717 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-11-10 09:58:31,717 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 94 [2018-11-10 09:58:31,717 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:58:31,718 INFO L225 Difference]: With dead ends: 151 [2018-11-10 09:58:31,718 INFO L226 Difference]: Without dead ends: 145 [2018-11-10 09:58:31,719 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 129 GetRequests, 91 SyntacticMatches, 4 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 248 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=234, Invalid=1026, Unknown=0, NotChecked=0, Total=1260 [2018-11-10 09:58:31,719 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 145 states. [2018-11-10 09:58:31,721 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 145 to 136. [2018-11-10 09:58:31,721 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 136 states. [2018-11-10 09:58:31,722 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 136 states to 136 states and 138 transitions. [2018-11-10 09:58:31,722 INFO L78 Accepts]: Start accepts. Automaton has 136 states and 138 transitions. Word has length 94 [2018-11-10 09:58:31,722 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:58:31,722 INFO L481 AbstractCegarLoop]: Abstraction has 136 states and 138 transitions. [2018-11-10 09:58:31,722 INFO L482 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-10 09:58:31,722 INFO L276 IsEmpty]: Start isEmpty. Operand 136 states and 138 transitions. [2018-11-10 09:58:31,723 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2018-11-10 09:58:31,723 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:58:31,723 INFO L375 BasicCegarLoop]: trace histogram [16, 13, 12, 12, 12, 12, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:58:31,724 INFO L424 AbstractCegarLoop]: === Iteration 19 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:58:31,724 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:58:31,724 INFO L82 PathProgramCache]: Analyzing trace with hash 35734246, now seen corresponding path program 4 times [2018-11-10 09:58:31,724 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:58:31,724 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:58:31,724 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:31,725 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 09:58:31,725 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:31,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:31,765 INFO L134 CoverageAnalysis]: Checked inductivity of 561 backedges. 213 proven. 27 refuted. 0 times theorem prover too weak. 321 trivial. 0 not checked. [2018-11-10 09:58:31,765 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:58:31,765 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:58:31,777 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-10 09:58:31,808 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-10 09:58:31,808 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 09:58:31,811 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:58:31,840 INFO L134 CoverageAnalysis]: Checked inductivity of 561 backedges. 213 proven. 27 refuted. 0 times theorem prover too weak. 321 trivial. 0 not checked. [2018-11-10 09:58:31,857 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:58:31,858 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 5] total 9 [2018-11-10 09:58:31,858 INFO L460 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-10 09:58:31,858 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-10 09:58:31,858 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2018-11-10 09:58:31,859 INFO L87 Difference]: Start difference. First operand 136 states and 138 transitions. Second operand 10 states. [2018-11-10 09:58:31,903 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:58:31,903 INFO L93 Difference]: Finished difference Result 144 states and 146 transitions. [2018-11-10 09:58:31,904 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-10 09:58:31,904 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 127 [2018-11-10 09:58:31,904 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:58:31,905 INFO L225 Difference]: With dead ends: 144 [2018-11-10 09:58:31,905 INFO L226 Difference]: Without dead ends: 144 [2018-11-10 09:58:31,905 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 132 GetRequests, 123 SyntacticMatches, 1 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2018-11-10 09:58:31,905 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states. [2018-11-10 09:58:31,907 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 137. [2018-11-10 09:58:31,907 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 137 states. [2018-11-10 09:58:31,908 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 137 states to 137 states and 139 transitions. [2018-11-10 09:58:31,908 INFO L78 Accepts]: Start accepts. Automaton has 137 states and 139 transitions. Word has length 127 [2018-11-10 09:58:31,908 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:58:31,908 INFO L481 AbstractCegarLoop]: Abstraction has 137 states and 139 transitions. [2018-11-10 09:58:31,908 INFO L482 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-10 09:58:31,908 INFO L276 IsEmpty]: Start isEmpty. Operand 137 states and 139 transitions. [2018-11-10 09:58:31,909 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 134 [2018-11-10 09:58:31,909 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:58:31,909 INFO L375 BasicCegarLoop]: trace histogram [17, 14, 13, 13, 13, 13, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:58:31,910 INFO L424 AbstractCegarLoop]: === Iteration 20 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:58:31,910 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:58:31,910 INFO L82 PathProgramCache]: Analyzing trace with hash 1430478046, now seen corresponding path program 5 times [2018-11-10 09:58:31,910 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:58:31,910 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:58:31,910 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:31,911 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 09:58:31,911 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:31,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:31,998 INFO L134 CoverageAnalysis]: Checked inductivity of 642 backedges. 320 proven. 34 refuted. 0 times theorem prover too weak. 288 trivial. 0 not checked. [2018-11-10 09:58:31,998 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:58:31,998 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:58:32,005 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-10 09:58:32,049 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2018-11-10 09:58:32,049 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 09:58:32,051 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:58:32,115 INFO L134 CoverageAnalysis]: Checked inductivity of 642 backedges. 273 proven. 48 refuted. 0 times theorem prover too weak. 321 trivial. 0 not checked. [2018-11-10 09:58:32,132 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:58:32,132 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 7] total 18 [2018-11-10 09:58:32,132 INFO L460 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-11-10 09:58:32,133 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-11-10 09:58:32,133 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=285, Unknown=0, NotChecked=0, Total=342 [2018-11-10 09:58:32,133 INFO L87 Difference]: Start difference. First operand 137 states and 139 transitions. Second operand 19 states. [2018-11-10 09:58:32,352 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:58:32,352 INFO L93 Difference]: Finished difference Result 208 states and 214 transitions. [2018-11-10 09:58:32,352 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-11-10 09:58:32,352 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 133 [2018-11-10 09:58:32,352 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:58:32,353 INFO L225 Difference]: With dead ends: 208 [2018-11-10 09:58:32,353 INFO L226 Difference]: Without dead ends: 208 [2018-11-10 09:58:32,354 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 152 GetRequests, 128 SyntacticMatches, 0 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 105 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=118, Invalid=532, Unknown=0, NotChecked=0, Total=650 [2018-11-10 09:58:32,354 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 208 states. [2018-11-10 09:58:32,356 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 208 to 180. [2018-11-10 09:58:32,356 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 180 states. [2018-11-10 09:58:32,356 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 180 states to 180 states and 184 transitions. [2018-11-10 09:58:32,356 INFO L78 Accepts]: Start accepts. Automaton has 180 states and 184 transitions. Word has length 133 [2018-11-10 09:58:32,357 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:58:32,357 INFO L481 AbstractCegarLoop]: Abstraction has 180 states and 184 transitions. [2018-11-10 09:58:32,357 INFO L482 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-11-10 09:58:32,357 INFO L276 IsEmpty]: Start isEmpty. Operand 180 states and 184 transitions. [2018-11-10 09:58:32,358 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 177 [2018-11-10 09:58:32,358 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:58:32,358 INFO L375 BasicCegarLoop]: trace histogram [23, 19, 18, 18, 18, 18, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:58:32,358 INFO L424 AbstractCegarLoop]: === Iteration 21 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:58:32,359 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:58:32,359 INFO L82 PathProgramCache]: Analyzing trace with hash 1547425825, now seen corresponding path program 6 times [2018-11-10 09:58:32,359 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:58:32,359 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:58:32,359 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:32,360 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 09:58:32,360 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:32,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:32,493 INFO L134 CoverageAnalysis]: Checked inductivity of 1218 backedges. 699 proven. 198 refuted. 0 times theorem prover too weak. 321 trivial. 0 not checked. [2018-11-10 09:58:32,493 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:58:32,493 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:58:32,498 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-10 09:58:32,541 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2018-11-10 09:58:32,541 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 09:58:32,544 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:58:32,630 INFO L134 CoverageAnalysis]: Checked inductivity of 1218 backedges. 503 proven. 59 refuted. 0 times theorem prover too weak. 656 trivial. 0 not checked. [2018-11-10 09:58:32,646 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:58:32,646 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 11] total 26 [2018-11-10 09:58:32,647 INFO L460 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-11-10 09:58:32,647 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-11-10 09:58:32,647 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=92, Invalid=558, Unknown=0, NotChecked=0, Total=650 [2018-11-10 09:58:32,647 INFO L87 Difference]: Start difference. First operand 180 states and 184 transitions. Second operand 26 states. [2018-11-10 09:58:33,302 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:58:33,302 INFO L93 Difference]: Finished difference Result 297 states and 303 transitions. [2018-11-10 09:58:33,303 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-11-10 09:58:33,303 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 176 [2018-11-10 09:58:33,304 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:58:33,304 INFO L225 Difference]: With dead ends: 297 [2018-11-10 09:58:33,304 INFO L226 Difference]: Without dead ends: 297 [2018-11-10 09:58:33,305 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 225 GetRequests, 169 SyntacticMatches, 0 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 803 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=644, Invalid=2662, Unknown=0, NotChecked=0, Total=3306 [2018-11-10 09:58:33,305 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 297 states. [2018-11-10 09:58:33,309 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 297 to 244. [2018-11-10 09:58:33,309 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 244 states. [2018-11-10 09:58:33,309 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 244 states to 244 states and 249 transitions. [2018-11-10 09:58:33,310 INFO L78 Accepts]: Start accepts. Automaton has 244 states and 249 transitions. Word has length 176 [2018-11-10 09:58:33,310 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:58:33,310 INFO L481 AbstractCegarLoop]: Abstraction has 244 states and 249 transitions. [2018-11-10 09:58:33,310 INFO L482 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-11-10 09:58:33,310 INFO L276 IsEmpty]: Start isEmpty. Operand 244 states and 249 transitions. [2018-11-10 09:58:33,311 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 226 [2018-11-10 09:58:33,311 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:58:33,311 INFO L375 BasicCegarLoop]: trace histogram [30, 25, 24, 24, 24, 24, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:58:33,311 INFO L424 AbstractCegarLoop]: === Iteration 22 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:58:33,311 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:58:33,312 INFO L82 PathProgramCache]: Analyzing trace with hash -1695529226, now seen corresponding path program 7 times [2018-11-10 09:58:33,312 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:58:33,312 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:58:33,315 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:33,316 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 09:58:33,316 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:33,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:33,471 INFO L134 CoverageAnalysis]: Checked inductivity of 2128 backedges. 1206 proven. 354 refuted. 0 times theorem prover too weak. 568 trivial. 0 not checked. [2018-11-10 09:58:33,471 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:58:33,471 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:58:33,492 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 09:58:33,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:33,536 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:58:33,652 INFO L134 CoverageAnalysis]: Checked inductivity of 2128 backedges. 1285 proven. 70 refuted. 0 times theorem prover too weak. 773 trivial. 0 not checked. [2018-11-10 09:58:33,668 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:58:33,668 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 14] total 24 [2018-11-10 09:58:33,668 INFO L460 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-11-10 09:58:33,669 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-11-10 09:58:33,669 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=112, Invalid=440, Unknown=0, NotChecked=0, Total=552 [2018-11-10 09:58:33,669 INFO L87 Difference]: Start difference. First operand 244 states and 249 transitions. Second operand 24 states. [2018-11-10 09:58:33,894 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:58:33,894 INFO L93 Difference]: Finished difference Result 266 states and 268 transitions. [2018-11-10 09:58:33,894 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-11-10 09:58:33,895 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 225 [2018-11-10 09:58:33,895 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:58:33,896 INFO L225 Difference]: With dead ends: 266 [2018-11-10 09:58:33,896 INFO L226 Difference]: Without dead ends: 244 [2018-11-10 09:58:33,896 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 254 GetRequests, 221 SyntacticMatches, 0 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 267 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=278, Invalid=912, Unknown=0, NotChecked=0, Total=1190 [2018-11-10 09:58:33,897 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 244 states. [2018-11-10 09:58:33,900 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 244 to 241. [2018-11-10 09:58:33,900 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 241 states. [2018-11-10 09:58:33,902 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 241 states to 241 states and 242 transitions. [2018-11-10 09:58:33,902 INFO L78 Accepts]: Start accepts. Automaton has 241 states and 242 transitions. Word has length 225 [2018-11-10 09:58:33,902 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:58:33,903 INFO L481 AbstractCegarLoop]: Abstraction has 241 states and 242 transitions. [2018-11-10 09:58:33,903 INFO L482 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-11-10 09:58:33,903 INFO L276 IsEmpty]: Start isEmpty. Operand 241 states and 242 transitions. [2018-11-10 09:58:33,904 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 238 [2018-11-10 09:58:33,904 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:58:33,904 INFO L375 BasicCegarLoop]: trace histogram [32, 27, 26, 26, 26, 26, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:58:33,904 INFO L424 AbstractCegarLoop]: === Iteration 23 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:58:33,904 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:58:33,904 INFO L82 PathProgramCache]: Analyzing trace with hash -1086078922, now seen corresponding path program 8 times [2018-11-10 09:58:33,905 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:58:33,905 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:58:33,905 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:33,905 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 09:58:33,905 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:33,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:34,072 INFO L134 CoverageAnalysis]: Checked inductivity of 2448 backedges. 909 proven. 91 refuted. 0 times theorem prover too weak. 1448 trivial. 0 not checked. [2018-11-10 09:58:34,072 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:58:34,072 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:58:34,080 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-10 09:58:34,137 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-10 09:58:34,137 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 09:58:34,140 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:58:34,213 INFO L134 CoverageAnalysis]: Checked inductivity of 2448 backedges. 850 proven. 108 refuted. 0 times theorem prover too weak. 1490 trivial. 0 not checked. [2018-11-10 09:58:34,228 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:58:34,229 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 8] total 20 [2018-11-10 09:58:34,229 INFO L460 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-10 09:58:34,229 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-10 09:58:34,229 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=65, Invalid=355, Unknown=0, NotChecked=0, Total=420 [2018-11-10 09:58:34,229 INFO L87 Difference]: Start difference. First operand 241 states and 242 transitions. Second operand 21 states. [2018-11-10 09:58:34,555 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:58:34,555 INFO L93 Difference]: Finished difference Result 319 states and 323 transitions. [2018-11-10 09:58:34,555 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-11-10 09:58:34,555 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 237 [2018-11-10 09:58:34,555 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:58:34,556 INFO L225 Difference]: With dead ends: 319 [2018-11-10 09:58:34,556 INFO L226 Difference]: Without dead ends: 319 [2018-11-10 09:58:34,556 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 259 GetRequests, 230 SyntacticMatches, 0 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 149 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=158, Invalid=772, Unknown=0, NotChecked=0, Total=930 [2018-11-10 09:58:34,556 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 319 states. [2018-11-10 09:58:34,561 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 319 to 296. [2018-11-10 09:58:34,561 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 296 states. [2018-11-10 09:58:34,562 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 296 states to 296 states and 299 transitions. [2018-11-10 09:58:34,562 INFO L78 Accepts]: Start accepts. Automaton has 296 states and 299 transitions. Word has length 237 [2018-11-10 09:58:34,562 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:58:34,563 INFO L481 AbstractCegarLoop]: Abstraction has 296 states and 299 transitions. [2018-11-10 09:58:34,563 INFO L482 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-10 09:58:34,563 INFO L276 IsEmpty]: Start isEmpty. Operand 296 states and 299 transitions. [2018-11-10 09:58:34,564 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 293 [2018-11-10 09:58:34,564 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:58:34,564 INFO L375 BasicCegarLoop]: trace histogram [40, 34, 33, 33, 33, 33, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:58:34,564 INFO L424 AbstractCegarLoop]: === Iteration 24 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:58:34,565 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:58:34,565 INFO L82 PathProgramCache]: Analyzing trace with hash 42363705, now seen corresponding path program 9 times [2018-11-10 09:58:34,565 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:58:34,565 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:58:34,565 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:34,566 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 09:58:34,566 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:34,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:34,799 INFO L134 CoverageAnalysis]: Checked inductivity of 3894 backedges. 2002 proven. 402 refuted. 0 times theorem prover too weak. 1490 trivial. 0 not checked. [2018-11-10 09:58:34,799 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:58:34,799 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:58:34,804 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-10 09:58:34,867 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 8 check-sat command(s) [2018-11-10 09:58:34,867 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 09:58:34,870 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:58:34,981 INFO L134 CoverageAnalysis]: Checked inductivity of 3894 backedges. 1266 proven. 147 refuted. 0 times theorem prover too weak. 2481 trivial. 0 not checked. [2018-11-10 09:58:34,998 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:58:34,998 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 10] total 31 [2018-11-10 09:58:34,998 INFO L460 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-11-10 09:58:34,999 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-11-10 09:58:34,999 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=140, Invalid=790, Unknown=0, NotChecked=0, Total=930 [2018-11-10 09:58:34,999 INFO L87 Difference]: Start difference. First operand 296 states and 299 transitions. Second operand 31 states. [2018-11-10 09:58:35,518 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:58:35,518 INFO L93 Difference]: Finished difference Result 379 states and 385 transitions. [2018-11-10 09:58:35,519 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-11-10 09:58:35,519 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 292 [2018-11-10 09:58:35,519 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:58:35,520 INFO L225 Difference]: With dead ends: 379 [2018-11-10 09:58:35,521 INFO L226 Difference]: Without dead ends: 379 [2018-11-10 09:58:35,521 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 336 GetRequests, 284 SyntacticMatches, 0 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 581 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=630, Invalid=2232, Unknown=0, NotChecked=0, Total=2862 [2018-11-10 09:58:35,522 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 379 states. [2018-11-10 09:58:35,527 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 379 to 369. [2018-11-10 09:58:35,527 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 369 states. [2018-11-10 09:58:35,528 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 369 states to 369 states and 375 transitions. [2018-11-10 09:58:35,529 INFO L78 Accepts]: Start accepts. Automaton has 369 states and 375 transitions. Word has length 292 [2018-11-10 09:58:35,529 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:58:35,529 INFO L481 AbstractCegarLoop]: Abstraction has 369 states and 375 transitions. [2018-11-10 09:58:35,529 INFO L482 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-11-10 09:58:35,529 INFO L276 IsEmpty]: Start isEmpty. Operand 369 states and 375 transitions. [2018-11-10 09:58:35,530 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 305 [2018-11-10 09:58:35,531 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:58:35,531 INFO L375 BasicCegarLoop]: trace histogram [42, 36, 35, 35, 35, 35, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:58:35,531 INFO L424 AbstractCegarLoop]: === Iteration 25 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:58:35,531 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:58:35,531 INFO L82 PathProgramCache]: Analyzing trace with hash 593895417, now seen corresponding path program 10 times [2018-11-10 09:58:35,531 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:58:35,531 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:58:35,532 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:35,532 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 09:58:35,532 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:35,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:35,772 INFO L134 CoverageAnalysis]: Checked inductivity of 4326 backedges. 1660 proven. 146 refuted. 0 times theorem prover too weak. 2520 trivial. 0 not checked. [2018-11-10 09:58:35,772 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:58:35,772 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:58:35,781 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-10 09:58:35,838 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-10 09:58:35,838 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 09:58:35,843 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:58:36,054 INFO L134 CoverageAnalysis]: Checked inductivity of 4326 backedges. 1683 proven. 123 refuted. 0 times theorem prover too weak. 2520 trivial. 0 not checked. [2018-11-10 09:58:36,070 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:58:36,070 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 19] total 30 [2018-11-10 09:58:36,070 INFO L460 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-11-10 09:58:36,071 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-11-10 09:58:36,071 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=211, Invalid=659, Unknown=0, NotChecked=0, Total=870 [2018-11-10 09:58:36,071 INFO L87 Difference]: Start difference. First operand 369 states and 375 transitions. Second operand 30 states. [2018-11-10 09:58:36,327 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:58:36,327 INFO L93 Difference]: Finished difference Result 499 states and 509 transitions. [2018-11-10 09:58:36,327 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-11-10 09:58:36,327 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 304 [2018-11-10 09:58:36,328 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:58:36,329 INFO L225 Difference]: With dead ends: 499 [2018-11-10 09:58:36,329 INFO L226 Difference]: Without dead ends: 499 [2018-11-10 09:58:36,330 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 338 GetRequests, 295 SyntacticMatches, 0 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 293 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=538, Invalid=1442, Unknown=0, NotChecked=0, Total=1980 [2018-11-10 09:58:36,330 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 499 states. [2018-11-10 09:58:36,339 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 499 to 488. [2018-11-10 09:58:36,339 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 488 states. [2018-11-10 09:58:36,341 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 488 states to 488 states and 498 transitions. [2018-11-10 09:58:36,341 INFO L78 Accepts]: Start accepts. Automaton has 488 states and 498 transitions. Word has length 304 [2018-11-10 09:58:36,341 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:58:36,341 INFO L481 AbstractCegarLoop]: Abstraction has 488 states and 498 transitions. [2018-11-10 09:58:36,342 INFO L482 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-11-10 09:58:36,342 INFO L276 IsEmpty]: Start isEmpty. Operand 488 states and 498 transitions. [2018-11-10 09:58:36,344 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 354 [2018-11-10 09:58:36,344 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:58:36,345 INFO L375 BasicCegarLoop]: trace histogram [49, 42, 41, 41, 41, 41, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:58:36,345 INFO L424 AbstractCegarLoop]: === Iteration 26 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:58:36,345 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:58:36,345 INFO L82 PathProgramCache]: Analyzing trace with hash -1424474418, now seen corresponding path program 11 times [2018-11-10 09:58:36,345 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:58:36,345 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:58:36,346 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:36,346 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 09:58:36,346 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:36,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:36,660 INFO L134 CoverageAnalysis]: Checked inductivity of 5932 backedges. 2588 proven. 733 refuted. 0 times theorem prover too weak. 2611 trivial. 0 not checked. [2018-11-10 09:58:36,660 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:58:36,660 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:58:36,666 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-10 09:58:36,792 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 20 check-sat command(s) [2018-11-10 09:58:36,793 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 09:58:36,797 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:58:37,067 INFO L134 CoverageAnalysis]: Checked inductivity of 5932 backedges. 3637 proven. 580 refuted. 0 times theorem prover too weak. 1715 trivial. 0 not checked. [2018-11-10 09:58:37,093 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:58:37,093 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 20] total 41 [2018-11-10 09:58:37,093 INFO L460 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-11-10 09:58:37,093 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-11-10 09:58:37,094 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=211, Invalid=1429, Unknown=0, NotChecked=0, Total=1640 [2018-11-10 09:58:37,094 INFO L87 Difference]: Start difference. First operand 488 states and 498 transitions. Second operand 41 states. [2018-11-10 09:58:38,013 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:58:38,013 INFO L93 Difference]: Finished difference Result 382 states and 385 transitions. [2018-11-10 09:58:38,014 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-11-10 09:58:38,014 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 353 [2018-11-10 09:58:38,014 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:58:38,015 INFO L225 Difference]: With dead ends: 382 [2018-11-10 09:58:38,015 INFO L226 Difference]: Without dead ends: 373 [2018-11-10 09:58:38,016 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 416 GetRequests, 338 SyntacticMatches, 0 SemanticMatches, 78 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1758 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=970, Invalid=5350, Unknown=0, NotChecked=0, Total=6320 [2018-11-10 09:58:38,016 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 373 states. [2018-11-10 09:58:38,021 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 373 to 369. [2018-11-10 09:58:38,021 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 369 states. [2018-11-10 09:58:38,022 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 369 states to 369 states and 372 transitions. [2018-11-10 09:58:38,022 INFO L78 Accepts]: Start accepts. Automaton has 369 states and 372 transitions. Word has length 353 [2018-11-10 09:58:38,022 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:58:38,022 INFO L481 AbstractCegarLoop]: Abstraction has 369 states and 372 transitions. [2018-11-10 09:58:38,022 INFO L482 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-11-10 09:58:38,023 INFO L276 IsEmpty]: Start isEmpty. Operand 369 states and 372 transitions. [2018-11-10 09:58:38,024 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 360 [2018-11-10 09:58:38,024 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:58:38,024 INFO L375 BasicCegarLoop]: trace histogram [50, 43, 42, 42, 42, 42, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:58:38,025 INFO L424 AbstractCegarLoop]: === Iteration 27 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:58:38,025 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:58:38,025 INFO L82 PathProgramCache]: Analyzing trace with hash -987311930, now seen corresponding path program 12 times [2018-11-10 09:58:38,025 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:58:38,025 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:58:38,026 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:38,026 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 09:58:38,026 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:38,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:38,370 INFO L134 CoverageAnalysis]: Checked inductivity of 6195 backedges. 3015 proven. 531 refuted. 0 times theorem prover too weak. 2649 trivial. 0 not checked. [2018-11-10 09:58:38,370 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:58:38,370 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:58:38,386 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-10 09:58:38,525 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 17 check-sat command(s) [2018-11-10 09:58:38,525 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 09:58:38,529 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:58:38,725 INFO L134 CoverageAnalysis]: Checked inductivity of 6195 backedges. 2876 proven. 523 refuted. 0 times theorem prover too weak. 2796 trivial. 0 not checked. [2018-11-10 09:58:38,741 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:58:38,742 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 17] total 35 [2018-11-10 09:58:38,742 INFO L460 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-11-10 09:58:38,742 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-11-10 09:58:38,743 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=210, Invalid=980, Unknown=0, NotChecked=0, Total=1190 [2018-11-10 09:58:38,743 INFO L87 Difference]: Start difference. First operand 369 states and 372 transitions. Second operand 35 states. [2018-11-10 09:58:39,386 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:58:39,386 INFO L93 Difference]: Finished difference Result 443 states and 448 transitions. [2018-11-10 09:58:39,386 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-11-10 09:58:39,386 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 359 [2018-11-10 09:58:39,387 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:58:39,388 INFO L225 Difference]: With dead ends: 443 [2018-11-10 09:58:39,388 INFO L226 Difference]: Without dead ends: 443 [2018-11-10 09:58:39,389 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 407 GetRequests, 349 SyntacticMatches, 0 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 921 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=812, Invalid=2728, Unknown=0, NotChecked=0, Total=3540 [2018-11-10 09:58:39,389 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 443 states. [2018-11-10 09:58:39,392 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 443 to 436. [2018-11-10 09:58:39,392 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 436 states. [2018-11-10 09:58:39,393 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 436 states to 436 states and 441 transitions. [2018-11-10 09:58:39,393 INFO L78 Accepts]: Start accepts. Automaton has 436 states and 441 transitions. Word has length 359 [2018-11-10 09:58:39,394 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:58:39,394 INFO L481 AbstractCegarLoop]: Abstraction has 436 states and 441 transitions. [2018-11-10 09:58:39,394 INFO L482 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-11-10 09:58:39,394 INFO L276 IsEmpty]: Start isEmpty. Operand 436 states and 441 transitions. [2018-11-10 09:58:39,395 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 366 [2018-11-10 09:58:39,395 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:58:39,396 INFO L375 BasicCegarLoop]: trace histogram [51, 44, 43, 43, 43, 43, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:58:39,396 INFO L424 AbstractCegarLoop]: === Iteration 28 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:58:39,396 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:58:39,396 INFO L82 PathProgramCache]: Analyzing trace with hash -605502962, now seen corresponding path program 13 times [2018-11-10 09:58:39,396 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:58:39,396 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:58:39,398 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:39,398 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 09:58:39,398 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:39,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:39,618 INFO L134 CoverageAnalysis]: Checked inductivity of 6464 backedges. 2102 proven. 176 refuted. 0 times theorem prover too weak. 4186 trivial. 0 not checked. [2018-11-10 09:58:39,618 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:58:39,619 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:58:39,626 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 09:58:39,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:39,699 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:58:39,836 INFO L134 CoverageAnalysis]: Checked inductivity of 6464 backedges. 1911 proven. 192 refuted. 0 times theorem prover too weak. 4361 trivial. 0 not checked. [2018-11-10 09:58:39,853 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:58:39,853 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 10] total 29 [2018-11-10 09:58:39,854 INFO L460 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-11-10 09:58:39,854 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-11-10 09:58:39,854 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=130, Invalid=740, Unknown=0, NotChecked=0, Total=870 [2018-11-10 09:58:39,854 INFO L87 Difference]: Start difference. First operand 436 states and 441 transitions. Second operand 30 states. [2018-11-10 09:58:40,365 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:58:40,365 INFO L93 Difference]: Finished difference Result 590 states and 601 transitions. [2018-11-10 09:58:40,365 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-11-10 09:58:40,365 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 365 [2018-11-10 09:58:40,366 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:58:40,367 INFO L225 Difference]: With dead ends: 590 [2018-11-10 09:58:40,367 INFO L226 Difference]: Without dead ends: 590 [2018-11-10 09:58:40,367 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 397 GetRequests, 356 SyntacticMatches, 1 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 331 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=261, Invalid=1461, Unknown=0, NotChecked=0, Total=1722 [2018-11-10 09:58:40,368 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 590 states. [2018-11-10 09:58:40,374 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 590 to 567. [2018-11-10 09:58:40,375 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 567 states. [2018-11-10 09:58:40,376 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 567 states to 567 states and 577 transitions. [2018-11-10 09:58:40,376 INFO L78 Accepts]: Start accepts. Automaton has 567 states and 577 transitions. Word has length 365 [2018-11-10 09:58:40,376 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:58:40,377 INFO L481 AbstractCegarLoop]: Abstraction has 567 states and 577 transitions. [2018-11-10 09:58:40,377 INFO L482 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-11-10 09:58:40,377 INFO L276 IsEmpty]: Start isEmpty. Operand 567 states and 577 transitions. [2018-11-10 09:58:40,379 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 427 [2018-11-10 09:58:40,379 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:58:40,379 INFO L375 BasicCegarLoop]: trace histogram [60, 52, 51, 51, 51, 51, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:58:40,379 INFO L424 AbstractCegarLoop]: === Iteration 29 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:58:40,380 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:58:40,380 INFO L82 PathProgramCache]: Analyzing trace with hash -520272359, now seen corresponding path program 14 times [2018-11-10 09:58:40,380 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:58:40,380 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:58:40,380 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:40,381 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 09:58:40,381 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:40,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:40,850 INFO L134 CoverageAnalysis]: Checked inductivity of 9031 backedges. 3759 proven. 956 refuted. 0 times theorem prover too weak. 4316 trivial. 0 not checked. [2018-11-10 09:58:40,850 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:58:40,850 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:58:40,862 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-10 09:58:40,957 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-10 09:58:40,957 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 09:58:40,963 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:58:41,492 INFO L134 CoverageAnalysis]: Checked inductivity of 9031 backedges. 5454 proven. 140 refuted. 0 times theorem prover too weak. 3437 trivial. 0 not checked. [2018-11-10 09:58:41,518 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:58:41,518 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 18] total 41 [2018-11-10 09:58:41,519 INFO L460 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-11-10 09:58:41,519 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-11-10 09:58:41,519 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=248, Invalid=1392, Unknown=0, NotChecked=0, Total=1640 [2018-11-10 09:58:41,519 INFO L87 Difference]: Start difference. First operand 567 states and 577 transitions. Second operand 41 states. [2018-11-10 09:58:42,258 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:58:42,258 INFO L93 Difference]: Finished difference Result 455 states and 458 transitions. [2018-11-10 09:58:42,258 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2018-11-10 09:58:42,258 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 426 [2018-11-10 09:58:42,259 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:58:42,260 INFO L225 Difference]: With dead ends: 455 [2018-11-10 09:58:42,260 INFO L226 Difference]: Without dead ends: 446 [2018-11-10 09:58:42,261 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 483 GetRequests, 412 SyntacticMatches, 0 SemanticMatches, 71 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1456 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=833, Invalid=4423, Unknown=0, NotChecked=0, Total=5256 [2018-11-10 09:58:42,261 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 446 states. [2018-11-10 09:58:42,266 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 446 to 442. [2018-11-10 09:58:42,267 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 442 states. [2018-11-10 09:58:42,268 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 442 states to 442 states and 445 transitions. [2018-11-10 09:58:42,268 INFO L78 Accepts]: Start accepts. Automaton has 442 states and 445 transitions. Word has length 426 [2018-11-10 09:58:42,268 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:58:42,268 INFO L481 AbstractCegarLoop]: Abstraction has 442 states and 445 transitions. [2018-11-10 09:58:42,268 INFO L482 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-11-10 09:58:42,268 INFO L276 IsEmpty]: Start isEmpty. Operand 442 states and 445 transitions. [2018-11-10 09:58:42,270 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 433 [2018-11-10 09:58:42,270 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:58:42,270 INFO L375 BasicCegarLoop]: trace histogram [61, 53, 52, 52, 52, 52, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:58:42,271 INFO L424 AbstractCegarLoop]: === Iteration 30 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:58:42,271 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:58:42,271 INFO L82 PathProgramCache]: Analyzing trace with hash -668946479, now seen corresponding path program 15 times [2018-11-10 09:58:42,271 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:58:42,271 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:58:42,271 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:42,272 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 09:58:42,272 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:42,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:42,553 INFO L134 CoverageAnalysis]: Checked inductivity of 9356 backedges. 4317 proven. 678 refuted. 0 times theorem prover too weak. 4361 trivial. 0 not checked. [2018-11-10 09:58:42,553 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:58:42,553 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:58:42,562 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-10 09:58:42,681 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2018-11-10 09:58:42,682 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 09:58:42,685 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:58:42,901 INFO L134 CoverageAnalysis]: Checked inductivity of 9356 backedges. 2611 proven. 243 refuted. 0 times theorem prover too weak. 6502 trivial. 0 not checked. [2018-11-10 09:58:42,928 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:58:42,928 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 12] total 37 [2018-11-10 09:58:42,929 INFO L460 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-11-10 09:58:42,929 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-11-10 09:58:42,930 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=201, Invalid=1131, Unknown=0, NotChecked=0, Total=1332 [2018-11-10 09:58:42,930 INFO L87 Difference]: Start difference. First operand 442 states and 445 transitions. Second operand 37 states. [2018-11-10 09:58:43,671 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:58:43,671 INFO L93 Difference]: Finished difference Result 531 states and 537 transitions. [2018-11-10 09:58:43,672 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-11-10 09:58:43,672 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 432 [2018-11-10 09:58:43,672 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:58:43,673 INFO L225 Difference]: With dead ends: 531 [2018-11-10 09:58:43,674 INFO L226 Difference]: Without dead ends: 531 [2018-11-10 09:58:43,675 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 486 GetRequests, 422 SyntacticMatches, 0 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 918 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=951, Invalid=3339, Unknown=0, NotChecked=0, Total=4290 [2018-11-10 09:58:43,675 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 531 states. [2018-11-10 09:58:43,681 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 531 to 521. [2018-11-10 09:58:43,681 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 521 states. [2018-11-10 09:58:43,682 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 521 states to 521 states and 527 transitions. [2018-11-10 09:58:43,682 INFO L78 Accepts]: Start accepts. Automaton has 521 states and 527 transitions. Word has length 432 [2018-11-10 09:58:43,682 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:58:43,683 INFO L481 AbstractCegarLoop]: Abstraction has 521 states and 527 transitions. [2018-11-10 09:58:43,683 INFO L482 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-11-10 09:58:43,683 INFO L276 IsEmpty]: Start isEmpty. Operand 521 states and 527 transitions. [2018-11-10 09:58:43,685 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 445 [2018-11-10 09:58:43,685 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:58:43,685 INFO L375 BasicCegarLoop]: trace histogram [63, 55, 54, 54, 54, 54, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:58:43,686 INFO L424 AbstractCegarLoop]: === Iteration 31 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:58:43,686 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:58:43,686 INFO L82 PathProgramCache]: Analyzing trace with hash 1926350993, now seen corresponding path program 16 times [2018-11-10 09:58:43,686 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:58:43,686 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:58:43,687 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:43,687 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 09:58:43,687 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:43,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:43,998 INFO L134 CoverageAnalysis]: Checked inductivity of 10024 backedges. 3227 proven. 249 refuted. 0 times theorem prover too weak. 6548 trivial. 0 not checked. [2018-11-10 09:58:43,998 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:58:43,999 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:58:44,016 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-10 09:58:44,083 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-10 09:58:44,083 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 09:58:44,087 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:58:44,325 INFO L134 CoverageAnalysis]: Checked inductivity of 10024 backedges. 3256 proven. 220 refuted. 0 times theorem prover too weak. 6548 trivial. 0 not checked. [2018-11-10 09:58:44,343 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:58:44,343 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 23] total 36 [2018-11-10 09:58:44,343 INFO L460 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-11-10 09:58:44,344 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-11-10 09:58:44,344 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=301, Invalid=959, Unknown=0, NotChecked=0, Total=1260 [2018-11-10 09:58:44,344 INFO L87 Difference]: Start difference. First operand 521 states and 527 transitions. Second operand 36 states. [2018-11-10 09:58:44,907 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:58:44,907 INFO L93 Difference]: Finished difference Result 675 states and 685 transitions. [2018-11-10 09:58:44,907 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-11-10 09:58:44,907 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 444 [2018-11-10 09:58:44,907 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:58:44,908 INFO L225 Difference]: With dead ends: 675 [2018-11-10 09:58:44,908 INFO L226 Difference]: Without dead ends: 675 [2018-11-10 09:58:44,909 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 486 GetRequests, 433 SyntacticMatches, 0 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 458 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=792, Invalid=2178, Unknown=0, NotChecked=0, Total=2970 [2018-11-10 09:58:44,909 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 675 states. [2018-11-10 09:58:44,916 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 675 to 664. [2018-11-10 09:58:44,916 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 664 states. [2018-11-10 09:58:44,918 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 664 states to 664 states and 674 transitions. [2018-11-10 09:58:44,918 INFO L78 Accepts]: Start accepts. Automaton has 664 states and 674 transitions. Word has length 444 [2018-11-10 09:58:44,918 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:58:44,918 INFO L481 AbstractCegarLoop]: Abstraction has 664 states and 674 transitions. [2018-11-10 09:58:44,918 INFO L482 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-11-10 09:58:44,918 INFO L276 IsEmpty]: Start isEmpty. Operand 664 states and 674 transitions. [2018-11-10 09:58:44,921 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 506 [2018-11-10 09:58:44,921 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:58:44,922 INFO L375 BasicCegarLoop]: trace histogram [72, 63, 62, 62, 62, 62, 10, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:58:44,922 INFO L424 AbstractCegarLoop]: === Iteration 32 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:58:44,922 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:58:44,922 INFO L82 PathProgramCache]: Analyzing trace with hash -458054874, now seen corresponding path program 17 times [2018-11-10 09:58:44,922 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:58:44,922 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:58:44,923 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:44,923 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 09:58:44,923 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:44,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:45,345 INFO L134 CoverageAnalysis]: Checked inductivity of 13170 backedges. 5237 proven. 1209 refuted. 0 times theorem prover too weak. 6724 trivial. 0 not checked. [2018-11-10 09:58:45,345 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:58:45,346 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:58:45,352 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-10 09:58:45,581 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 23 check-sat command(s) [2018-11-10 09:58:45,581 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 09:58:45,589 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:58:46,277 INFO L134 CoverageAnalysis]: Checked inductivity of 13170 backedges. 7549 proven. 1024 refuted. 0 times theorem prover too weak. 4597 trivial. 0 not checked. [2018-11-10 09:58:46,304 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:58:46,304 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 24] total 49 [2018-11-10 09:58:46,305 INFO L460 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-11-10 09:58:46,305 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-11-10 09:58:46,306 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=306, Invalid=2046, Unknown=0, NotChecked=0, Total=2352 [2018-11-10 09:58:46,306 INFO L87 Difference]: Start difference. First operand 664 states and 674 transitions. Second operand 49 states. [2018-11-10 09:58:47,637 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:58:47,637 INFO L93 Difference]: Finished difference Result 534 states and 537 transitions. [2018-11-10 09:58:47,638 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2018-11-10 09:58:47,638 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 505 [2018-11-10 09:58:47,638 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:58:47,639 INFO L225 Difference]: With dead ends: 534 [2018-11-10 09:58:47,639 INFO L226 Difference]: Without dead ends: 525 [2018-11-10 09:58:47,641 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 582 GetRequests, 486 SyntacticMatches, 0 SemanticMatches, 96 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2801 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=1432, Invalid=8074, Unknown=0, NotChecked=0, Total=9506 [2018-11-10 09:58:47,641 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 525 states. [2018-11-10 09:58:47,646 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 525 to 521. [2018-11-10 09:58:47,646 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 521 states. [2018-11-10 09:58:47,647 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 521 states to 521 states and 524 transitions. [2018-11-10 09:58:47,647 INFO L78 Accepts]: Start accepts. Automaton has 521 states and 524 transitions. Word has length 505 [2018-11-10 09:58:47,647 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:58:47,648 INFO L481 AbstractCegarLoop]: Abstraction has 521 states and 524 transitions. [2018-11-10 09:58:47,648 INFO L482 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-11-10 09:58:47,648 INFO L276 IsEmpty]: Start isEmpty. Operand 521 states and 524 transitions. [2018-11-10 09:58:47,650 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 512 [2018-11-10 09:58:47,650 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:58:47,651 INFO L375 BasicCegarLoop]: trace histogram [73, 64, 63, 63, 63, 63, 10, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:58:47,651 INFO L424 AbstractCegarLoop]: === Iteration 33 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:58:47,651 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:58:47,651 INFO L82 PathProgramCache]: Analyzing trace with hash 504957726, now seen corresponding path program 18 times [2018-11-10 09:58:47,651 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:58:47,651 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:58:47,652 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:47,652 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 09:58:47,652 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:47,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:48,064 INFO L134 CoverageAnalysis]: Checked inductivity of 13563 backedges. 5944 proven. 843 refuted. 0 times theorem prover too weak. 6776 trivial. 0 not checked. [2018-11-10 09:58:48,064 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:58:48,064 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:58:48,070 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-10 09:58:48,294 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 21 check-sat command(s) [2018-11-10 09:58:48,294 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 09:58:48,299 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:58:48,640 INFO L134 CoverageAnalysis]: Checked inductivity of 13563 backedges. 5711 proven. 833 refuted. 0 times theorem prover too weak. 7019 trivial. 0 not checked. [2018-11-10 09:58:48,666 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:58:48,667 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 19] total 41 [2018-11-10 09:58:48,667 INFO L460 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-11-10 09:58:48,667 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-11-10 09:58:48,668 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=296, Invalid=1344, Unknown=0, NotChecked=0, Total=1640 [2018-11-10 09:58:48,668 INFO L87 Difference]: Start difference. First operand 521 states and 524 transitions. Second operand 41 states. [2018-11-10 09:58:49,287 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:58:49,287 INFO L93 Difference]: Finished difference Result 607 states and 612 transitions. [2018-11-10 09:58:49,288 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-11-10 09:58:49,288 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 511 [2018-11-10 09:58:49,288 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:58:49,289 INFO L225 Difference]: With dead ends: 607 [2018-11-10 09:58:49,289 INFO L226 Difference]: Without dead ends: 607 [2018-11-10 09:58:49,290 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 569 GetRequests, 499 SyntacticMatches, 0 SemanticMatches, 70 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1393 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=1184, Invalid=3928, Unknown=0, NotChecked=0, Total=5112 [2018-11-10 09:58:49,290 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 607 states. [2018-11-10 09:58:49,296 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 607 to 600. [2018-11-10 09:58:49,296 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 600 states. [2018-11-10 09:58:49,297 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 600 states to 600 states and 605 transitions. [2018-11-10 09:58:49,297 INFO L78 Accepts]: Start accepts. Automaton has 600 states and 605 transitions. Word has length 511 [2018-11-10 09:58:49,298 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:58:49,298 INFO L481 AbstractCegarLoop]: Abstraction has 600 states and 605 transitions. [2018-11-10 09:58:49,298 INFO L482 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-11-10 09:58:49,298 INFO L276 IsEmpty]: Start isEmpty. Operand 600 states and 605 transitions. [2018-11-10 09:58:49,301 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 518 [2018-11-10 09:58:49,301 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:58:49,301 INFO L375 BasicCegarLoop]: trace histogram [74, 65, 64, 64, 64, 64, 10, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:58:49,301 INFO L424 AbstractCegarLoop]: === Iteration 34 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:58:49,301 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:58:49,302 INFO L82 PathProgramCache]: Analyzing trace with hash 892822118, now seen corresponding path program 19 times [2018-11-10 09:58:49,302 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:58:49,302 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:58:49,302 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:49,302 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 09:58:49,302 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:49,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:49,609 INFO L134 CoverageAnalysis]: Checked inductivity of 13962 backedges. 3707 proven. 289 refuted. 0 times theorem prover too weak. 9966 trivial. 0 not checked. [2018-11-10 09:58:49,610 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:58:49,610 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:58:49,616 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 09:58:49,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:49,710 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:58:49,915 INFO L134 CoverageAnalysis]: Checked inductivity of 13962 backedges. 3600 proven. 300 refuted. 0 times theorem prover too weak. 10062 trivial. 0 not checked. [2018-11-10 09:58:49,931 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:58:49,931 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 12] total 28 [2018-11-10 09:58:49,931 INFO L460 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-11-10 09:58:49,931 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-11-10 09:58:49,932 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=115, Invalid=697, Unknown=0, NotChecked=0, Total=812 [2018-11-10 09:58:49,932 INFO L87 Difference]: Start difference. First operand 600 states and 605 transitions. Second operand 29 states. [2018-11-10 09:58:50,549 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:58:50,549 INFO L93 Difference]: Finished difference Result 782 states and 793 transitions. [2018-11-10 09:58:50,549 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-11-10 09:58:50,549 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 517 [2018-11-10 09:58:50,550 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:58:50,551 INFO L225 Difference]: With dead ends: 782 [2018-11-10 09:58:50,552 INFO L226 Difference]: Without dead ends: 782 [2018-11-10 09:58:50,552 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 548 GetRequests, 506 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 321 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=261, Invalid=1631, Unknown=0, NotChecked=0, Total=1892 [2018-11-10 09:58:50,552 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 782 states. [2018-11-10 09:58:50,560 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 782 to 755. [2018-11-10 09:58:50,560 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 755 states. [2018-11-10 09:58:50,562 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 755 states to 755 states and 765 transitions. [2018-11-10 09:58:50,562 INFO L78 Accepts]: Start accepts. Automaton has 755 states and 765 transitions. Word has length 517 [2018-11-10 09:58:50,562 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:58:50,562 INFO L481 AbstractCegarLoop]: Abstraction has 755 states and 765 transitions. [2018-11-10 09:58:50,562 INFO L482 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-11-10 09:58:50,562 INFO L276 IsEmpty]: Start isEmpty. Operand 755 states and 765 transitions. [2018-11-10 09:58:50,566 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 591 [2018-11-10 09:58:50,566 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:58:50,566 INFO L375 BasicCegarLoop]: trace histogram [85, 75, 74, 74, 74, 74, 11, 11, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:58:50,566 INFO L424 AbstractCegarLoop]: === Iteration 35 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:58:50,567 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:58:50,567 INFO L82 PathProgramCache]: Analyzing trace with hash -380668367, now seen corresponding path program 20 times [2018-11-10 09:58:50,567 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:58:50,567 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:58:50,567 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:50,567 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 09:58:50,568 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:50,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:51,166 INFO L134 CoverageAnalysis]: Checked inductivity of 18553 backedges. 7058 proven. 1492 refuted. 0 times theorem prover too weak. 10003 trivial. 0 not checked. [2018-11-10 09:58:51,166 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:58:51,166 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:58:51,172 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-10 09:58:51,257 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-10 09:58:51,257 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 09:58:51,262 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:58:51,650 INFO L134 CoverageAnalysis]: Checked inductivity of 18553 backedges. 10388 proven. 234 refuted. 0 times theorem prover too weak. 7931 trivial. 0 not checked. [2018-11-10 09:58:51,667 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:58:51,667 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 22] total 49 [2018-11-10 09:58:51,667 INFO L460 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-11-10 09:58:51,667 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-11-10 09:58:51,668 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=355, Invalid=1997, Unknown=0, NotChecked=0, Total=2352 [2018-11-10 09:58:51,668 INFO L87 Difference]: Start difference. First operand 755 states and 765 transitions. Second operand 49 states. [2018-11-10 09:58:52,497 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:58:52,497 INFO L93 Difference]: Finished difference Result 619 states and 622 transitions. [2018-11-10 09:58:52,497 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2018-11-10 09:58:52,497 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 590 [2018-11-10 09:58:52,497 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:58:52,498 INFO L225 Difference]: With dead ends: 619 [2018-11-10 09:58:52,498 INFO L226 Difference]: Without dead ends: 610 [2018-11-10 09:58:52,499 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 659 GetRequests, 572 SyntacticMatches, 0 SemanticMatches, 87 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2264 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=1220, Invalid=6612, Unknown=0, NotChecked=0, Total=7832 [2018-11-10 09:58:52,499 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 610 states. [2018-11-10 09:58:52,502 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 610 to 606. [2018-11-10 09:58:52,502 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 606 states. [2018-11-10 09:58:52,503 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 606 states to 606 states and 609 transitions. [2018-11-10 09:58:52,504 INFO L78 Accepts]: Start accepts. Automaton has 606 states and 609 transitions. Word has length 590 [2018-11-10 09:58:52,504 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:58:52,504 INFO L481 AbstractCegarLoop]: Abstraction has 606 states and 609 transitions. [2018-11-10 09:58:52,504 INFO L482 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-11-10 09:58:52,504 INFO L276 IsEmpty]: Start isEmpty. Operand 606 states and 609 transitions. [2018-11-10 09:58:52,507 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 597 [2018-11-10 09:58:52,507 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:58:52,507 INFO L375 BasicCegarLoop]: trace histogram [86, 76, 75, 75, 75, 75, 11, 11, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:58:52,507 INFO L424 AbstractCegarLoop]: === Iteration 36 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:58:52,507 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:58:52,508 INFO L82 PathProgramCache]: Analyzing trace with hash 109372905, now seen corresponding path program 21 times [2018-11-10 09:58:52,508 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:58:52,508 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:58:52,508 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:52,508 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 09:58:52,509 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:52,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:52,910 INFO L134 CoverageAnalysis]: Checked inductivity of 19020 backedges. 7932 proven. 1026 refuted. 0 times theorem prover too weak. 10062 trivial. 0 not checked. [2018-11-10 09:58:52,910 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:58:52,910 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:58:52,916 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-10 09:58:53,042 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2018-11-10 09:58:53,043 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 09:58:53,046 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:58:53,328 INFO L134 CoverageAnalysis]: Checked inductivity of 19020 backedges. 7643 proven. 1015 refuted. 0 times theorem prover too weak. 10362 trivial. 0 not checked. [2018-11-10 09:58:53,344 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:58:53,344 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 20] total 44 [2018-11-10 09:58:53,345 INFO L460 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-11-10 09:58:53,345 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-11-10 09:58:53,345 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=345, Invalid=1547, Unknown=0, NotChecked=0, Total=1892 [2018-11-10 09:58:53,345 INFO L87 Difference]: Start difference. First operand 606 states and 609 transitions. Second operand 44 states. [2018-11-10 09:58:54,250 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:58:54,250 INFO L93 Difference]: Finished difference Result 698 states and 703 transitions. [2018-11-10 09:58:54,251 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2018-11-10 09:58:54,252 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 596 [2018-11-10 09:58:54,252 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:58:54,253 INFO L225 Difference]: With dead ends: 698 [2018-11-10 09:58:54,254 INFO L226 Difference]: Without dead ends: 698 [2018-11-10 09:58:54,254 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 659 GetRequests, 583 SyntacticMatches, 0 SemanticMatches, 76 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1665 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=1397, Invalid=4609, Unknown=0, NotChecked=0, Total=6006 [2018-11-10 09:58:54,255 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 698 states. [2018-11-10 09:58:54,260 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 698 to 691. [2018-11-10 09:58:54,260 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 691 states. [2018-11-10 09:58:54,262 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 691 states to 691 states and 696 transitions. [2018-11-10 09:58:54,262 INFO L78 Accepts]: Start accepts. Automaton has 691 states and 696 transitions. Word has length 596 [2018-11-10 09:58:54,262 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:58:54,262 INFO L481 AbstractCegarLoop]: Abstraction has 691 states and 696 transitions. [2018-11-10 09:58:54,262 INFO L482 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-11-10 09:58:54,262 INFO L276 IsEmpty]: Start isEmpty. Operand 691 states and 696 transitions. [2018-11-10 09:58:54,265 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 603 [2018-11-10 09:58:54,266 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:58:54,266 INFO L375 BasicCegarLoop]: trace histogram [87, 77, 76, 76, 76, 76, 11, 11, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:58:54,266 INFO L424 AbstractCegarLoop]: === Iteration 37 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:58:54,266 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:58:54,266 INFO L82 PathProgramCache]: Analyzing trace with hash -1056310031, now seen corresponding path program 22 times [2018-11-10 09:58:54,266 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:58:54,267 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:58:54,267 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:54,267 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 09:58:54,267 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:54,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:54,623 INFO L134 CoverageAnalysis]: Checked inductivity of 19493 backedges. 4787 proven. 356 refuted. 0 times theorem prover too weak. 14350 trivial. 0 not checked. [2018-11-10 09:58:54,623 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:58:54,623 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:58:54,629 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-10 09:58:54,782 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-10 09:58:54,782 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 09:58:54,788 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:58:54,978 INFO L134 CoverageAnalysis]: Checked inductivity of 19493 backedges. 4725 proven. 363 refuted. 0 times theorem prover too weak. 14405 trivial. 0 not checked. [2018-11-10 09:58:54,995 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:58:54,995 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 13] total 29 [2018-11-10 09:58:54,996 INFO L460 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-11-10 09:58:54,996 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-11-10 09:58:54,996 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=126, Invalid=744, Unknown=0, NotChecked=0, Total=870 [2018-11-10 09:58:54,996 INFO L87 Difference]: Start difference. First operand 691 states and 696 transitions. Second operand 30 states. [2018-11-10 09:58:55,806 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:58:55,806 INFO L93 Difference]: Finished difference Result 885 states and 896 transitions. [2018-11-10 09:58:55,807 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2018-11-10 09:58:55,807 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 602 [2018-11-10 09:58:55,807 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:58:55,809 INFO L225 Difference]: With dead ends: 885 [2018-11-10 09:58:55,809 INFO L226 Difference]: Without dead ends: 885 [2018-11-10 09:58:55,809 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 634 GetRequests, 590 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 337 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=272, Invalid=1798, Unknown=0, NotChecked=0, Total=2070 [2018-11-10 09:58:55,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 885 states. [2018-11-10 09:58:55,814 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 885 to 858. [2018-11-10 09:58:55,814 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 858 states. [2018-11-10 09:58:55,815 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 858 states to 858 states and 868 transitions. [2018-11-10 09:58:55,816 INFO L78 Accepts]: Start accepts. Automaton has 858 states and 868 transitions. Word has length 602 [2018-11-10 09:58:55,816 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:58:55,816 INFO L481 AbstractCegarLoop]: Abstraction has 858 states and 868 transitions. [2018-11-10 09:58:55,816 INFO L482 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-11-10 09:58:55,816 INFO L276 IsEmpty]: Start isEmpty. Operand 858 states and 868 transitions. [2018-11-10 09:58:55,819 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 682 [2018-11-10 09:58:55,819 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:58:55,819 INFO L375 BasicCegarLoop]: trace histogram [99, 88, 87, 87, 87, 87, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:58:55,819 INFO L424 AbstractCegarLoop]: === Iteration 38 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:58:55,819 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:58:55,819 INFO L82 PathProgramCache]: Analyzing trace with hash 2034427390, now seen corresponding path program 23 times [2018-11-10 09:58:55,820 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:58:55,820 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:58:55,820 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:55,820 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 09:58:55,820 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:55,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:56,269 INFO L134 CoverageAnalysis]: Checked inductivity of 25402 backedges. 9258 proven. 1805 refuted. 0 times theorem prover too weak. 14339 trivial. 0 not checked. [2018-11-10 09:58:56,269 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:58:56,269 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:58:56,274 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-10 09:58:56,559 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 25 check-sat command(s) [2018-11-10 09:58:56,560 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 09:58:56,566 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:58:57,076 INFO L134 CoverageAnalysis]: Checked inductivity of 25402 backedges. 13533 proven. 1572 refuted. 0 times theorem prover too weak. 10297 trivial. 0 not checked. [2018-11-10 09:58:57,093 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:58:57,094 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 28] total 57 [2018-11-10 09:58:57,094 INFO L460 AbstractCegarLoop]: Interpolant automaton has 57 states [2018-11-10 09:58:57,094 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2018-11-10 09:58:57,094 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=421, Invalid=2771, Unknown=0, NotChecked=0, Total=3192 [2018-11-10 09:58:57,094 INFO L87 Difference]: Start difference. First operand 858 states and 868 transitions. Second operand 57 states. [2018-11-10 09:58:58,607 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:58:58,607 INFO L93 Difference]: Finished difference Result 710 states and 713 transitions. [2018-11-10 09:58:58,608 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 67 states. [2018-11-10 09:58:58,608 INFO L78 Accepts]: Start accepts. Automaton has 57 states. Word has length 681 [2018-11-10 09:58:58,608 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:58:58,610 INFO L225 Difference]: With dead ends: 710 [2018-11-10 09:58:58,610 INFO L226 Difference]: Without dead ends: 701 [2018-11-10 09:58:58,611 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 772 GetRequests, 658 SyntacticMatches, 0 SemanticMatches, 114 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4080 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=1990, Invalid=11350, Unknown=0, NotChecked=0, Total=13340 [2018-11-10 09:58:58,612 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 701 states. [2018-11-10 09:58:58,616 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 701 to 697. [2018-11-10 09:58:58,617 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 697 states. [2018-11-10 09:58:58,618 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 697 states to 697 states and 700 transitions. [2018-11-10 09:58:58,618 INFO L78 Accepts]: Start accepts. Automaton has 697 states and 700 transitions. Word has length 681 [2018-11-10 09:58:58,618 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:58:58,618 INFO L481 AbstractCegarLoop]: Abstraction has 697 states and 700 transitions. [2018-11-10 09:58:58,618 INFO L482 AbstractCegarLoop]: Interpolant automaton has 57 states. [2018-11-10 09:58:58,618 INFO L276 IsEmpty]: Start isEmpty. Operand 697 states and 700 transitions. [2018-11-10 09:58:58,631 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 688 [2018-11-10 09:58:58,631 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:58:58,631 INFO L375 BasicCegarLoop]: trace histogram [100, 89, 88, 88, 88, 88, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:58:58,631 INFO L424 AbstractCegarLoop]: === Iteration 39 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:58:58,632 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:58:58,632 INFO L82 PathProgramCache]: Analyzing trace with hash 1172587510, now seen corresponding path program 24 times [2018-11-10 09:58:58,632 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:58:58,632 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:58:58,632 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:58,632 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 09:58:58,633 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:58:58,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:58:59,169 INFO L134 CoverageAnalysis]: Checked inductivity of 25949 backedges. 10317 proven. 1227 refuted. 0 times theorem prover too weak. 14405 trivial. 0 not checked. [2018-11-10 09:58:59,169 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:58:59,170 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:58:59,177 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-10 09:58:59,607 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 22 check-sat command(s) [2018-11-10 09:58:59,607 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 09:58:59,613 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:58:59,930 INFO L134 CoverageAnalysis]: Checked inductivity of 25949 backedges. 6054 proven. 430 refuted. 0 times theorem prover too weak. 19465 trivial. 0 not checked. [2018-11-10 09:58:59,947 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:58:59,947 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 18] total 47 [2018-11-10 09:58:59,948 INFO L460 AbstractCegarLoop]: Interpolant automaton has 47 states [2018-11-10 09:58:59,948 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2018-11-10 09:58:59,948 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=309, Invalid=1853, Unknown=0, NotChecked=0, Total=2162 [2018-11-10 09:58:59,948 INFO L87 Difference]: Start difference. First operand 697 states and 700 transitions. Second operand 47 states. [2018-11-10 09:59:01,499 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:59:01,499 INFO L93 Difference]: Finished difference Result 892 states and 898 transitions. [2018-11-10 09:59:01,499 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 110 states. [2018-11-10 09:59:01,499 INFO L78 Accepts]: Start accepts. Automaton has 47 states. Word has length 687 [2018-11-10 09:59:01,500 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:59:01,501 INFO L225 Difference]: With dead ends: 892 [2018-11-10 09:59:01,501 INFO L226 Difference]: Without dead ends: 892 [2018-11-10 09:59:01,502 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 799 GetRequests, 673 SyntacticMatches, 0 SemanticMatches, 126 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5115 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=2562, Invalid=13694, Unknown=0, NotChecked=0, Total=16256 [2018-11-10 09:59:01,502 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 892 states. [2018-11-10 09:59:01,506 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 892 to 797. [2018-11-10 09:59:01,506 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 797 states. [2018-11-10 09:59:01,507 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 797 states to 797 states and 802 transitions. [2018-11-10 09:59:01,507 INFO L78 Accepts]: Start accepts. Automaton has 797 states and 802 transitions. Word has length 687 [2018-11-10 09:59:01,508 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:59:01,508 INFO L481 AbstractCegarLoop]: Abstraction has 797 states and 802 transitions. [2018-11-10 09:59:01,508 INFO L482 AbstractCegarLoop]: Interpolant automaton has 47 states. [2018-11-10 09:59:01,508 INFO L276 IsEmpty]: Start isEmpty. Operand 797 states and 802 transitions. [2018-11-10 09:59:01,513 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 779 [2018-11-10 09:59:01,513 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:59:01,513 INFO L375 BasicCegarLoop]: trace histogram [114, 102, 101, 101, 101, 101, 13, 13, 13, 13, 12, 12, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:59:01,513 INFO L424 AbstractCegarLoop]: === Iteration 40 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:59:01,514 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:59:01,514 INFO L82 PathProgramCache]: Analyzing trace with hash -1013732919, now seen corresponding path program 25 times [2018-11-10 09:59:01,514 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:59:01,514 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:59:01,514 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:59:01,515 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 09:59:01,515 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:59:01,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:59:02,192 INFO L134 CoverageAnalysis]: Checked inductivity of 33957 backedges. 13337 proven. 1747 refuted. 0 times theorem prover too weak. 18873 trivial. 0 not checked. [2018-11-10 09:59:02,193 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:59:02,193 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:59:02,199 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 09:59:02,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:59:02,307 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:59:02,651 INFO L134 CoverageAnalysis]: Checked inductivity of 33957 backedges. 13514 proven. 420 refuted. 0 times theorem prover too weak. 20023 trivial. 0 not checked. [2018-11-10 09:59:02,667 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:59:02,667 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 28] total 45 [2018-11-10 09:59:02,667 INFO L460 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-11-10 09:59:02,668 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-11-10 09:59:02,668 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=413, Invalid=1567, Unknown=0, NotChecked=0, Total=1980 [2018-11-10 09:59:02,668 INFO L87 Difference]: Start difference. First operand 797 states and 802 transitions. Second operand 45 states. [2018-11-10 09:59:03,337 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:59:03,338 INFO L93 Difference]: Finished difference Result 819 states and 821 transitions. [2018-11-10 09:59:03,338 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2018-11-10 09:59:03,338 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 778 [2018-11-10 09:59:03,338 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:59:03,340 INFO L225 Difference]: With dead ends: 819 [2018-11-10 09:59:03,340 INFO L226 Difference]: Without dead ends: 797 [2018-11-10 09:59:03,340 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 835 GetRequests, 767 SyntacticMatches, 0 SemanticMatches, 68 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1443 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1097, Invalid=3733, Unknown=0, NotChecked=0, Total=4830 [2018-11-10 09:59:03,341 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 797 states. [2018-11-10 09:59:03,346 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 797 to 794. [2018-11-10 09:59:03,346 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 794 states. [2018-11-10 09:59:03,348 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 794 states to 794 states and 795 transitions. [2018-11-10 09:59:03,348 INFO L78 Accepts]: Start accepts. Automaton has 794 states and 795 transitions. Word has length 778 [2018-11-10 09:59:03,348 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:59:03,348 INFO L481 AbstractCegarLoop]: Abstraction has 794 states and 795 transitions. [2018-11-10 09:59:03,348 INFO L482 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-11-10 09:59:03,348 INFO L276 IsEmpty]: Start isEmpty. Operand 794 states and 795 transitions. [2018-11-10 09:59:03,357 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 791 [2018-11-10 09:59:03,357 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:59:03,357 INFO L375 BasicCegarLoop]: trace histogram [116, 104, 103, 103, 103, 103, 13, 13, 13, 13, 12, 12, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:59:03,357 INFO L424 AbstractCegarLoop]: === Iteration 41 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:59:03,357 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:59:03,358 INFO L82 PathProgramCache]: Analyzing trace with hash -1365222775, now seen corresponding path program 26 times [2018-11-10 09:59:03,358 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:59:03,358 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:59:03,358 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:59:03,358 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 09:59:03,358 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:59:03,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:59:03,715 INFO L134 CoverageAnalysis]: Checked inductivity of 35229 backedges. 7700 proven. 511 refuted. 0 times theorem prover too weak. 27018 trivial. 0 not checked. [2018-11-10 09:59:03,716 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:59:03,716 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:59:03,721 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-10 09:59:03,833 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-10 09:59:03,834 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 09:59:03,839 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:59:04,106 INFO L134 CoverageAnalysis]: Checked inductivity of 35229 backedges. 7626 proven. 507 refuted. 0 times theorem prover too weak. 27096 trivial. 0 not checked. [2018-11-10 09:59:04,122 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:59:04,122 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 15] total 33 [2018-11-10 09:59:04,123 INFO L460 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-11-10 09:59:04,123 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-11-10 09:59:04,123 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=159, Invalid=963, Unknown=0, NotChecked=0, Total=1122 [2018-11-10 09:59:04,123 INFO L87 Difference]: Start difference. First operand 794 states and 795 transitions. Second operand 34 states. [2018-11-10 09:59:04,951 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:59:04,951 INFO L93 Difference]: Finished difference Result 914 states and 918 transitions. [2018-11-10 09:59:04,951 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-11-10 09:59:04,951 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 790 [2018-11-10 09:59:04,952 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:59:04,953 INFO L225 Difference]: With dead ends: 914 [2018-11-10 09:59:04,953 INFO L226 Difference]: Without dead ends: 914 [2018-11-10 09:59:04,953 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 825 GetRequests, 776 SyntacticMatches, 0 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 419 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=317, Invalid=2233, Unknown=0, NotChecked=0, Total=2550 [2018-11-10 09:59:04,954 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 914 states. [2018-11-10 09:59:04,958 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 914 to 891. [2018-11-10 09:59:04,958 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 891 states. [2018-11-10 09:59:04,959 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 891 states to 891 states and 894 transitions. [2018-11-10 09:59:04,959 INFO L78 Accepts]: Start accepts. Automaton has 891 states and 894 transitions. Word has length 790 [2018-11-10 09:59:04,959 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:59:04,960 INFO L481 AbstractCegarLoop]: Abstraction has 891 states and 894 transitions. [2018-11-10 09:59:04,960 INFO L482 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-11-10 09:59:04,960 INFO L276 IsEmpty]: Start isEmpty. Operand 891 states and 894 transitions. [2018-11-10 09:59:04,964 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 888 [2018-11-10 09:59:04,964 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:59:04,964 INFO L375 BasicCegarLoop]: trace histogram [131, 118, 117, 117, 117, 117, 14, 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:59:04,964 INFO L424 AbstractCegarLoop]: === Iteration 42 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:59:04,964 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:59:04,964 INFO L82 PathProgramCache]: Analyzing trace with hash -468157618, now seen corresponding path program 27 times [2018-11-10 09:59:04,965 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:59:04,965 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:59:04,965 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:59:04,965 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 09:59:04,965 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:59:04,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:59:05,601 INFO L134 CoverageAnalysis]: Checked inductivity of 45201 backedges. 16422 proven. 1683 refuted. 0 times theorem prover too weak. 27096 trivial. 0 not checked. [2018-11-10 09:59:05,601 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:59:05,601 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:59:05,607 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-10 09:59:05,768 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2018-11-10 09:59:05,769 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 09:59:05,774 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:59:06,217 INFO L134 CoverageAnalysis]: Checked inductivity of 45201 backedges. 15929 proven. 1669 refuted. 0 times theorem prover too weak. 27603 trivial. 0 not checked. [2018-11-10 09:59:06,242 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:59:06,242 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 23] total 53 [2018-11-10 09:59:06,242 INFO L460 AbstractCegarLoop]: Interpolant automaton has 53 states [2018-11-10 09:59:06,243 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2018-11-10 09:59:06,243 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=516, Invalid=2240, Unknown=0, NotChecked=0, Total=2756 [2018-11-10 09:59:06,243 INFO L87 Difference]: Start difference. First operand 891 states and 894 transitions. Second operand 53 states. [2018-11-10 09:59:07,206 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:59:07,207 INFO L93 Difference]: Finished difference Result 1007 states and 1012 transitions. [2018-11-10 09:59:07,207 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-11-10 09:59:07,207 INFO L78 Accepts]: Start accepts. Automaton has 53 states. Word has length 887 [2018-11-10 09:59:07,208 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:59:07,209 INFO L225 Difference]: With dead ends: 1007 [2018-11-10 09:59:07,209 INFO L226 Difference]: Without dead ends: 1007 [2018-11-10 09:59:07,210 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 965 GetRequests, 871 SyntacticMatches, 0 SemanticMatches, 94 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2625 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=2144, Invalid=6976, Unknown=0, NotChecked=0, Total=9120 [2018-11-10 09:59:07,210 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1007 states. [2018-11-10 09:59:07,215 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1007 to 1000. [2018-11-10 09:59:07,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1000 states. [2018-11-10 09:59:07,216 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1000 states to 1000 states and 1005 transitions. [2018-11-10 09:59:07,216 INFO L78 Accepts]: Start accepts. Automaton has 1000 states and 1005 transitions. Word has length 887 [2018-11-10 09:59:07,217 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:59:07,217 INFO L481 AbstractCegarLoop]: Abstraction has 1000 states and 1005 transitions. [2018-11-10 09:59:07,217 INFO L482 AbstractCegarLoop]: Interpolant automaton has 53 states. [2018-11-10 09:59:07,217 INFO L276 IsEmpty]: Start isEmpty. Operand 1000 states and 1005 transitions. [2018-11-10 09:59:07,221 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 894 [2018-11-10 09:59:07,221 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:59:07,221 INFO L375 BasicCegarLoop]: trace histogram [132, 119, 118, 118, 118, 118, 14, 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:59:07,222 INFO L424 AbstractCegarLoop]: === Iteration 43 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:59:07,222 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:59:07,222 INFO L82 PathProgramCache]: Analyzing trace with hash 1786838678, now seen corresponding path program 28 times [2018-11-10 09:59:07,222 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:59:07,222 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:59:07,222 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:59:07,223 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 09:59:07,223 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:59:07,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:59:07,664 INFO L134 CoverageAnalysis]: Checked inductivity of 45932 backedges. 9593 proven. 599 refuted. 0 times theorem prover too weak. 35740 trivial. 0 not checked. [2018-11-10 09:59:07,664 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:59:07,664 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:59:07,670 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-10 09:59:07,866 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-10 09:59:07,866 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 09:59:07,875 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:59:08,221 INFO L134 CoverageAnalysis]: Checked inductivity of 45932 backedges. 9438 proven. 588 refuted. 0 times theorem prover too weak. 35906 trivial. 0 not checked. [2018-11-10 09:59:08,238 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:59:08,239 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 16] total 36 [2018-11-10 09:59:08,239 INFO L460 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-11-10 09:59:08,239 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-11-10 09:59:08,240 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=181, Invalid=1151, Unknown=0, NotChecked=0, Total=1332 [2018-11-10 09:59:08,240 INFO L87 Difference]: Start difference. First operand 1000 states and 1005 transitions. Second operand 37 states. [2018-11-10 09:59:09,231 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:59:09,231 INFO L93 Difference]: Finished difference Result 1230 states and 1241 transitions. [2018-11-10 09:59:09,232 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-11-10 09:59:09,232 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 893 [2018-11-10 09:59:09,232 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:59:09,234 INFO L225 Difference]: With dead ends: 1230 [2018-11-10 09:59:09,234 INFO L226 Difference]: Without dead ends: 1230 [2018-11-10 09:59:09,234 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 932 GetRequests, 878 SyntacticMatches, 0 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 531 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=371, Invalid=2709, Unknown=0, NotChecked=0, Total=3080 [2018-11-10 09:59:09,235 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1230 states. [2018-11-10 09:59:09,240 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1230 to 1203. [2018-11-10 09:59:09,240 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1203 states. [2018-11-10 09:59:09,242 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1203 states to 1203 states and 1213 transitions. [2018-11-10 09:59:09,242 INFO L78 Accepts]: Start accepts. Automaton has 1203 states and 1213 transitions. Word has length 893 [2018-11-10 09:59:09,243 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:59:09,243 INFO L481 AbstractCegarLoop]: Abstraction has 1203 states and 1213 transitions. [2018-11-10 09:59:09,243 INFO L482 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-11-10 09:59:09,243 INFO L276 IsEmpty]: Start isEmpty. Operand 1203 states and 1213 transitions. [2018-11-10 09:59:09,248 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 991 [2018-11-10 09:59:09,248 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:59:09,249 INFO L375 BasicCegarLoop]: trace histogram [147, 133, 132, 132, 132, 132, 15, 15, 15, 15, 14, 14, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:59:09,249 INFO L424 AbstractCegarLoop]: === Iteration 44 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:59:09,249 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:59:09,249 INFO L82 PathProgramCache]: Analyzing trace with hash 465341153, now seen corresponding path program 29 times [2018-11-10 09:59:09,249 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:59:09,249 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:59:09,250 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:59:09,250 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 09:59:09,250 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:59:09,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:59:09,999 INFO L134 CoverageAnalysis]: Checked inductivity of 57235 backedges. 18492 proven. 2924 refuted. 0 times theorem prover too weak. 35819 trivial. 0 not checked. [2018-11-10 09:59:09,999 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:59:09,999 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:59:10,005 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-10 09:59:10,611 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 29 check-sat command(s) [2018-11-10 09:59:10,611 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 09:59:10,621 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:59:11,427 INFO L134 CoverageAnalysis]: Checked inductivity of 57235 backedges. 27339 proven. 2589 refuted. 0 times theorem prover too weak. 27307 trivial. 0 not checked. [2018-11-10 09:59:11,445 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:59:11,445 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 34] total 69 [2018-11-10 09:59:11,446 INFO L460 AbstractCegarLoop]: Interpolant automaton has 69 states [2018-11-10 09:59:11,446 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2018-11-10 09:59:11,446 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=631, Invalid=4061, Unknown=0, NotChecked=0, Total=4692 [2018-11-10 09:59:11,446 INFO L87 Difference]: Start difference. First operand 1203 states and 1213 transitions. Second operand 69 states. [2018-11-10 09:59:13,286 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:59:13,287 INFO L93 Difference]: Finished difference Result 1019 states and 1022 transitions. [2018-11-10 09:59:13,287 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 82 states. [2018-11-10 09:59:13,287 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 990 [2018-11-10 09:59:13,287 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:59:13,288 INFO L225 Difference]: With dead ends: 1019 [2018-11-10 09:59:13,288 INFO L226 Difference]: Without dead ends: 1010 [2018-11-10 09:59:13,289 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1102 GetRequests, 961 SyntacticMatches, 0 SemanticMatches, 141 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6441 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=3007, Invalid=17299, Unknown=0, NotChecked=0, Total=20306 [2018-11-10 09:59:13,290 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1010 states. [2018-11-10 09:59:13,293 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1010 to 1006. [2018-11-10 09:59:13,293 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1006 states. [2018-11-10 09:59:13,294 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1006 states to 1006 states and 1009 transitions. [2018-11-10 09:59:13,295 INFO L78 Accepts]: Start accepts. Automaton has 1006 states and 1009 transitions. Word has length 990 [2018-11-10 09:59:13,295 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:59:13,295 INFO L481 AbstractCegarLoop]: Abstraction has 1006 states and 1009 transitions. [2018-11-10 09:59:13,295 INFO L482 AbstractCegarLoop]: Interpolant automaton has 69 states. [2018-11-10 09:59:13,295 INFO L276 IsEmpty]: Start isEmpty. Operand 1006 states and 1009 transitions. [2018-11-10 09:59:13,299 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 997 [2018-11-10 09:59:13,299 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:59:13,299 INFO L375 BasicCegarLoop]: trace histogram [148, 134, 133, 133, 133, 133, 15, 15, 15, 15, 14, 14, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:59:13,300 INFO L424 AbstractCegarLoop]: === Iteration 45 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:59:13,300 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:59:13,300 INFO L82 PathProgramCache]: Analyzing trace with hash -2008504679, now seen corresponding path program 30 times [2018-11-10 09:59:13,300 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:59:13,300 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:59:13,300 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:59:13,300 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 09:59:13,301 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:59:13,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:59:14,054 INFO L134 CoverageAnalysis]: Checked inductivity of 58058 backedges. 20214 proven. 1938 refuted. 0 times theorem prover too weak. 35906 trivial. 0 not checked. [2018-11-10 09:59:14,054 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:59:14,054 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:59:14,061 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-10 09:59:15,069 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 26 check-sat command(s) [2018-11-10 09:59:15,069 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 09:59:15,077 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:59:15,569 INFO L134 CoverageAnalysis]: Checked inductivity of 58058 backedges. 11508 proven. 694 refuted. 0 times theorem prover too weak. 45856 trivial. 0 not checked. [2018-11-10 09:59:15,587 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:59:15,587 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 21] total 56 [2018-11-10 09:59:15,588 INFO L460 AbstractCegarLoop]: Interpolant automaton has 56 states [2018-11-10 09:59:15,588 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 56 interpolants. [2018-11-10 09:59:15,588 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=447, Invalid=2633, Unknown=0, NotChecked=0, Total=3080 [2018-11-10 09:59:15,589 INFO L87 Difference]: Start difference. First operand 1006 states and 1009 transitions. Second operand 56 states. [2018-11-10 09:59:17,681 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:59:17,681 INFO L93 Difference]: Finished difference Result 1237 states and 1243 transitions. [2018-11-10 09:59:17,682 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 137 states. [2018-11-10 09:59:17,682 INFO L78 Accepts]: Start accepts. Automaton has 56 states. Word has length 996 [2018-11-10 09:59:17,682 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:59:17,684 INFO L225 Difference]: With dead ends: 1237 [2018-11-10 09:59:17,684 INFO L226 Difference]: Without dead ends: 1237 [2018-11-10 09:59:17,685 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1135 GetRequests, 979 SyntacticMatches, 0 SemanticMatches, 156 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8088 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=3714, Invalid=21092, Unknown=0, NotChecked=0, Total=24806 [2018-11-10 09:59:17,685 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1237 states. [2018-11-10 09:59:17,690 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1237 to 1124. [2018-11-10 09:59:17,690 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1124 states. [2018-11-10 09:59:17,691 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1124 states to 1124 states and 1129 transitions. [2018-11-10 09:59:17,691 INFO L78 Accepts]: Start accepts. Automaton has 1124 states and 1129 transitions. Word has length 996 [2018-11-10 09:59:17,691 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:59:17,691 INFO L481 AbstractCegarLoop]: Abstraction has 1124 states and 1129 transitions. [2018-11-10 09:59:17,691 INFO L482 AbstractCegarLoop]: Interpolant automaton has 56 states. [2018-11-10 09:59:17,691 INFO L276 IsEmpty]: Start isEmpty. Operand 1124 states and 1129 transitions. [2018-11-10 09:59:17,696 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1106 [2018-11-10 09:59:17,696 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:59:17,696 INFO L375 BasicCegarLoop]: trace histogram [165, 150, 149, 149, 149, 149, 16, 16, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:59:17,697 INFO L424 AbstractCegarLoop]: === Iteration 46 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:59:17,697 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:59:17,697 INFO L82 PathProgramCache]: Analyzing trace with hash 1227877678, now seen corresponding path program 31 times [2018-11-10 09:59:17,697 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:59:17,697 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:59:17,697 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:59:17,698 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 09:59:17,698 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:59:17,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:59:18,505 INFO L134 CoverageAnalysis]: Checked inductivity of 72528 backedges. 24956 proven. 2644 refuted. 0 times theorem prover too weak. 44928 trivial. 0 not checked. [2018-11-10 09:59:18,506 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:59:18,506 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:59:18,512 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 09:59:18,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:59:18,676 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:59:19,236 INFO L134 CoverageAnalysis]: Checked inductivity of 72528 backedges. 25175 proven. 660 refuted. 0 times theorem prover too weak. 46693 trivial. 0 not checked. [2018-11-10 09:59:19,253 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:59:19,253 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 34] total 54 [2018-11-10 09:59:19,254 INFO L460 AbstractCegarLoop]: Interpolant automaton has 54 states [2018-11-10 09:59:19,254 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2018-11-10 09:59:19,254 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=602, Invalid=2260, Unknown=0, NotChecked=0, Total=2862 [2018-11-10 09:59:19,254 INFO L87 Difference]: Start difference. First operand 1124 states and 1129 transitions. Second operand 54 states. [2018-11-10 09:59:20,111 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:59:20,111 INFO L93 Difference]: Finished difference Result 1146 states and 1148 transitions. [2018-11-10 09:59:20,112 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2018-11-10 09:59:20,112 INFO L78 Accepts]: Start accepts. Automaton has 54 states. Word has length 1105 [2018-11-10 09:59:20,112 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:59:20,114 INFO L225 Difference]: With dead ends: 1146 [2018-11-10 09:59:20,114 INFO L226 Difference]: Without dead ends: 1124 [2018-11-10 09:59:20,114 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1174 GetRequests, 1091 SyntacticMatches, 0 SemanticMatches, 83 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2232 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=1613, Invalid=5527, Unknown=0, NotChecked=0, Total=7140 [2018-11-10 09:59:20,115 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1124 states. [2018-11-10 09:59:20,119 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1124 to 1121. [2018-11-10 09:59:20,119 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1121 states. [2018-11-10 09:59:20,120 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1121 states to 1121 states and 1122 transitions. [2018-11-10 09:59:20,120 INFO L78 Accepts]: Start accepts. Automaton has 1121 states and 1122 transitions. Word has length 1105 [2018-11-10 09:59:20,120 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:59:20,120 INFO L481 AbstractCegarLoop]: Abstraction has 1121 states and 1122 transitions. [2018-11-10 09:59:20,120 INFO L482 AbstractCegarLoop]: Interpolant automaton has 54 states. [2018-11-10 09:59:20,120 INFO L276 IsEmpty]: Start isEmpty. Operand 1121 states and 1122 transitions. [2018-11-10 09:59:20,125 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1118 [2018-11-10 09:59:20,125 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:59:20,126 INFO L375 BasicCegarLoop]: trace histogram [167, 152, 151, 151, 151, 151, 16, 16, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:59:20,126 INFO L424 AbstractCegarLoop]: === Iteration 47 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:59:20,126 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:59:20,126 INFO L82 PathProgramCache]: Analyzing trace with hash 1830910574, now seen corresponding path program 32 times [2018-11-10 09:59:20,126 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:59:20,126 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:59:20,127 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:59:20,127 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 09:59:20,127 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:59:20,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:59:20,896 INFO L134 CoverageAnalysis]: Checked inductivity of 74388 backedges. 14642 proven. 796 refuted. 0 times theorem prover too weak. 58950 trivial. 0 not checked. [2018-11-10 09:59:20,896 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:59:20,896 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:59:20,901 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-10 09:59:21,066 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-10 09:59:21,066 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 09:59:21,074 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:59:21,614 INFO L134 CoverageAnalysis]: Checked inductivity of 74388 backedges. 13875 proven. 768 refuted. 0 times theorem prover too weak. 59745 trivial. 0 not checked. [2018-11-10 09:59:21,631 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:59:21,631 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 18] total 53 [2018-11-10 09:59:21,631 INFO L460 AbstractCegarLoop]: Interpolant automaton has 54 states [2018-11-10 09:59:21,632 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2018-11-10 09:59:21,632 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=378, Invalid=2484, Unknown=0, NotChecked=0, Total=2862 [2018-11-10 09:59:21,632 INFO L87 Difference]: Start difference. First operand 1121 states and 1122 transitions. Second operand 54 states. [2018-11-10 09:59:22,892 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:59:22,892 INFO L93 Difference]: Finished difference Result 1255 states and 1259 transitions. [2018-11-10 09:59:22,892 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 55 states. [2018-11-10 09:59:22,892 INFO L78 Accepts]: Start accepts. Automaton has 54 states. Word has length 1117 [2018-11-10 09:59:22,892 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:59:22,894 INFO L225 Difference]: With dead ends: 1255 [2018-11-10 09:59:22,894 INFO L226 Difference]: Without dead ends: 1255 [2018-11-10 09:59:22,894 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1172 GetRequests, 1100 SyntacticMatches, 1 SemanticMatches, 71 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1152 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=660, Invalid=4596, Unknown=0, NotChecked=0, Total=5256 [2018-11-10 09:59:22,895 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1255 states. [2018-11-10 09:59:22,900 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1255 to 1236. [2018-11-10 09:59:22,900 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1236 states. [2018-11-10 09:59:22,901 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1236 states to 1236 states and 1239 transitions. [2018-11-10 09:59:22,901 INFO L78 Accepts]: Start accepts. Automaton has 1236 states and 1239 transitions. Word has length 1117 [2018-11-10 09:59:22,902 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:59:22,902 INFO L481 AbstractCegarLoop]: Abstraction has 1236 states and 1239 transitions. [2018-11-10 09:59:22,902 INFO L482 AbstractCegarLoop]: Interpolant automaton has 54 states. [2018-11-10 09:59:22,902 INFO L276 IsEmpty]: Start isEmpty. Operand 1236 states and 1239 transitions. [2018-11-10 09:59:22,912 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1233 [2018-11-10 09:59:22,912 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:59:22,912 INFO L375 BasicCegarLoop]: trace histogram [185, 169, 168, 168, 168, 168, 17, 17, 17, 17, 16, 16, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:59:22,912 INFO L424 AbstractCegarLoop]: === Iteration 48 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:59:22,912 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:59:22,913 INFO L82 PathProgramCache]: Analyzing trace with hash 1964060977, now seen corresponding path program 33 times [2018-11-10 09:59:22,913 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:59:22,913 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:59:22,913 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:59:22,913 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 09:59:22,914 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:59:22,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:59:23,835 INFO L134 CoverageAnalysis]: Checked inductivity of 91704 backedges. 29457 proven. 2502 refuted. 0 times theorem prover too weak. 59745 trivial. 0 not checked. [2018-11-10 09:59:23,835 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:59:23,835 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:59:23,842 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-10 09:59:24,072 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2018-11-10 09:59:24,072 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 09:59:24,079 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:59:24,817 INFO L134 CoverageAnalysis]: Checked inductivity of 91704 backedges. 28706 proven. 2485 refuted. 0 times theorem prover too weak. 60513 trivial. 0 not checked. [2018-11-10 09:59:24,834 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:59:24,835 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 26] total 62 [2018-11-10 09:59:24,835 INFO L460 AbstractCegarLoop]: Interpolant automaton has 62 states [2018-11-10 09:59:24,835 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2018-11-10 09:59:24,836 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=723, Invalid=3059, Unknown=0, NotChecked=0, Total=3782 [2018-11-10 09:59:24,836 INFO L87 Difference]: Start difference. First operand 1236 states and 1239 transitions. Second operand 62 states. [2018-11-10 09:59:25,953 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:59:25,954 INFO L93 Difference]: Finished difference Result 1370 states and 1375 transitions. [2018-11-10 09:59:25,954 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2018-11-10 09:59:25,954 INFO L78 Accepts]: Start accepts. Automaton has 62 states. Word has length 1232 [2018-11-10 09:59:25,955 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:59:25,957 INFO L225 Difference]: With dead ends: 1370 [2018-11-10 09:59:25,957 INFO L226 Difference]: Without dead ends: 1370 [2018-11-10 09:59:25,958 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1325 GetRequests, 1213 SyntacticMatches, 0 SemanticMatches, 112 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3801 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=3053, Invalid=9829, Unknown=0, NotChecked=0, Total=12882 [2018-11-10 09:59:25,959 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1370 states. [2018-11-10 09:59:25,964 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1370 to 1363. [2018-11-10 09:59:25,964 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1363 states. [2018-11-10 09:59:25,966 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1363 states to 1363 states and 1368 transitions. [2018-11-10 09:59:25,966 INFO L78 Accepts]: Start accepts. Automaton has 1363 states and 1368 transitions. Word has length 1232 [2018-11-10 09:59:25,967 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:59:25,967 INFO L481 AbstractCegarLoop]: Abstraction has 1363 states and 1368 transitions. [2018-11-10 09:59:25,967 INFO L482 AbstractCegarLoop]: Interpolant automaton has 62 states. [2018-11-10 09:59:25,967 INFO L276 IsEmpty]: Start isEmpty. Operand 1363 states and 1368 transitions. [2018-11-10 09:59:25,974 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1239 [2018-11-10 09:59:25,974 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:59:25,974 INFO L375 BasicCegarLoop]: trace histogram [186, 170, 169, 169, 169, 169, 17, 17, 17, 17, 16, 16, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:59:25,974 INFO L424 AbstractCegarLoop]: === Iteration 49 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:59:25,974 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:59:25,975 INFO L82 PathProgramCache]: Analyzing trace with hash -872723911, now seen corresponding path program 34 times [2018-11-10 09:59:25,975 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:59:25,975 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:59:25,975 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:59:25,975 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 09:59:25,975 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:59:26,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:59:26,595 INFO L134 CoverageAnalysis]: Checked inductivity of 92747 backedges. 16634 proven. 905 refuted. 0 times theorem prover too weak. 75208 trivial. 0 not checked. [2018-11-10 09:59:26,595 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:59:26,595 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:59:26,601 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-10 09:59:27,468 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-10 09:59:27,468 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 09:59:27,479 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:59:28,012 INFO L134 CoverageAnalysis]: Checked inductivity of 92747 backedges. 16536 proven. 867 refuted. 0 times theorem prover too weak. 75344 trivial. 0 not checked. [2018-11-10 09:59:28,031 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:59:28,032 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 19] total 41 [2018-11-10 09:59:28,033 INFO L460 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-11-10 09:59:28,033 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-11-10 09:59:28,033 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=237, Invalid=1485, Unknown=0, NotChecked=0, Total=1722 [2018-11-10 09:59:28,033 INFO L87 Difference]: Start difference. First operand 1363 states and 1368 transitions. Second operand 42 states. [2018-11-10 09:59:29,270 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:59:29,270 INFO L93 Difference]: Finished difference Result 1629 states and 1640 transitions. [2018-11-10 09:59:29,271 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2018-11-10 09:59:29,271 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 1238 [2018-11-10 09:59:29,272 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:59:29,274 INFO L225 Difference]: With dead ends: 1629 [2018-11-10 09:59:29,274 INFO L226 Difference]: Without dead ends: 1629 [2018-11-10 09:59:29,274 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1282 GetRequests, 1220 SyntacticMatches, 0 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 670 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=443, Invalid=3589, Unknown=0, NotChecked=0, Total=4032 [2018-11-10 09:59:29,275 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1629 states. [2018-11-10 09:59:29,282 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1629 to 1602. [2018-11-10 09:59:29,282 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1602 states. [2018-11-10 09:59:29,284 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1602 states to 1602 states and 1612 transitions. [2018-11-10 09:59:29,284 INFO L78 Accepts]: Start accepts. Automaton has 1602 states and 1612 transitions. Word has length 1238 [2018-11-10 09:59:29,285 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:59:29,285 INFO L481 AbstractCegarLoop]: Abstraction has 1602 states and 1612 transitions. [2018-11-10 09:59:29,285 INFO L482 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-11-10 09:59:29,285 INFO L276 IsEmpty]: Start isEmpty. Operand 1602 states and 1612 transitions. [2018-11-10 09:59:29,292 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1354 [2018-11-10 09:59:29,292 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:59:29,293 INFO L375 BasicCegarLoop]: trace histogram [204, 187, 186, 186, 186, 186, 18, 18, 18, 18, 17, 17, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:59:29,293 INFO L424 AbstractCegarLoop]: === Iteration 50 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:59:29,293 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:59:29,293 INFO L82 PathProgramCache]: Analyzing trace with hash 129131910, now seen corresponding path program 35 times [2018-11-10 09:59:29,293 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:59:29,293 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:59:29,293 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:59:29,293 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 09:59:29,294 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:59:29,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:59:30,373 INFO L134 CoverageAnalysis]: Checked inductivity of 111982 backedges. 32433 proven. 4313 refuted. 0 times theorem prover too weak. 75236 trivial. 0 not checked. [2018-11-10 09:59:30,374 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:59:30,374 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:59:30,380 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-10 09:59:31,494 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 35 check-sat command(s) [2018-11-10 09:59:31,494 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 09:59:31,508 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:59:32,723 INFO L134 CoverageAnalysis]: Checked inductivity of 111982 backedges. 48237 proven. 3840 refuted. 0 times theorem prover too weak. 59905 trivial. 0 not checked. [2018-11-10 09:59:32,742 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:59:32,742 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 40] total 81 [2018-11-10 09:59:32,743 INFO L460 AbstractCegarLoop]: Interpolant automaton has 81 states [2018-11-10 09:59:32,743 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 81 interpolants. [2018-11-10 09:59:32,743 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=886, Invalid=5594, Unknown=0, NotChecked=0, Total=6480 [2018-11-10 09:59:32,743 INFO L87 Difference]: Start difference. First operand 1602 states and 1612 transitions. Second operand 81 states. [2018-11-10 09:59:35,116 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:59:35,116 INFO L93 Difference]: Finished difference Result 1382 states and 1385 transitions. [2018-11-10 09:59:35,117 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 97 states. [2018-11-10 09:59:35,117 INFO L78 Accepts]: Start accepts. Automaton has 81 states. Word has length 1353 [2018-11-10 09:59:35,117 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:59:35,119 INFO L225 Difference]: With dead ends: 1382 [2018-11-10 09:59:35,119 INFO L226 Difference]: Without dead ends: 1373 [2018-11-10 09:59:35,120 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1486 GetRequests, 1318 SyntacticMatches, 0 SemanticMatches, 168 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9333 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=4240, Invalid=24490, Unknown=0, NotChecked=0, Total=28730 [2018-11-10 09:59:35,121 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1373 states. [2018-11-10 09:59:35,126 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1373 to 1369. [2018-11-10 09:59:35,126 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1369 states. [2018-11-10 09:59:35,127 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1369 states to 1369 states and 1372 transitions. [2018-11-10 09:59:35,127 INFO L78 Accepts]: Start accepts. Automaton has 1369 states and 1372 transitions. Word has length 1353 [2018-11-10 09:59:35,128 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:59:35,128 INFO L481 AbstractCegarLoop]: Abstraction has 1369 states and 1372 transitions. [2018-11-10 09:59:35,128 INFO L482 AbstractCegarLoop]: Interpolant automaton has 81 states. [2018-11-10 09:59:35,128 INFO L276 IsEmpty]: Start isEmpty. Operand 1369 states and 1372 transitions. [2018-11-10 09:59:35,136 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1360 [2018-11-10 09:59:35,136 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:59:35,136 INFO L375 BasicCegarLoop]: trace histogram [205, 188, 187, 187, 187, 187, 18, 18, 18, 18, 17, 17, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:59:35,136 INFO L424 AbstractCegarLoop]: === Iteration 51 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:59:35,136 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:59:35,137 INFO L82 PathProgramCache]: Analyzing trace with hash 1320641918, now seen corresponding path program 36 times [2018-11-10 09:59:35,137 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:59:35,137 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:59:35,137 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:59:35,137 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 09:59:35,138 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:59:35,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:59:36,216 INFO L134 CoverageAnalysis]: Checked inductivity of 113135 backedges. 34980 proven. 2811 refuted. 0 times theorem prover too weak. 75344 trivial. 0 not checked. [2018-11-10 09:59:36,217 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:59:36,217 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:59:36,223 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-10 09:59:39,049 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 37 check-sat command(s) [2018-11-10 09:59:39,049 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 09:59:39,063 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:59:39,947 INFO L134 CoverageAnalysis]: Checked inductivity of 113135 backedges. 32425 proven. 4607 refuted. 0 times theorem prover too weak. 76103 trivial. 0 not checked. [2018-11-10 09:59:39,966 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:59:39,966 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 28] total 68 [2018-11-10 09:59:39,967 INFO L460 AbstractCegarLoop]: Interpolant automaton has 68 states [2018-11-10 09:59:39,967 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 68 interpolants. [2018-11-10 09:59:39,967 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=809, Invalid=3747, Unknown=0, NotChecked=0, Total=4556 [2018-11-10 09:59:39,967 INFO L87 Difference]: Start difference. First operand 1369 states and 1372 transitions. Second operand 68 states. [2018-11-10 09:59:41,807 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:59:41,807 INFO L93 Difference]: Finished difference Result 1642 states and 1651 transitions. [2018-11-10 09:59:41,807 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 88 states. [2018-11-10 09:59:41,808 INFO L78 Accepts]: Start accepts. Automaton has 68 states. Word has length 1359 [2018-11-10 09:59:41,809 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:59:41,812 INFO L225 Difference]: With dead ends: 1642 [2018-11-10 09:59:41,812 INFO L226 Difference]: Without dead ends: 1642 [2018-11-10 09:59:41,814 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1479 GetRequests, 1336 SyntacticMatches, 0 SemanticMatches, 143 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6340 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=4602, Invalid=16278, Unknown=0, NotChecked=0, Total=20880 [2018-11-10 09:59:41,815 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1642 states. [2018-11-10 09:59:41,828 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1642 to 1629. [2018-11-10 09:59:41,829 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1629 states. [2018-11-10 09:59:41,830 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1629 states to 1629 states and 1638 transitions. [2018-11-10 09:59:41,831 INFO L78 Accepts]: Start accepts. Automaton has 1629 states and 1638 transitions. Word has length 1359 [2018-11-10 09:59:41,831 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:59:41,831 INFO L481 AbstractCegarLoop]: Abstraction has 1629 states and 1638 transitions. [2018-11-10 09:59:41,832 INFO L482 AbstractCegarLoop]: Interpolant automaton has 68 states. [2018-11-10 09:59:41,832 INFO L276 IsEmpty]: Start isEmpty. Operand 1629 states and 1638 transitions. [2018-11-10 09:59:41,843 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1493 [2018-11-10 09:59:41,843 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:59:41,844 INFO L375 BasicCegarLoop]: trace histogram [226, 208, 207, 207, 207, 207, 19, 19, 19, 19, 18, 18, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:59:41,844 INFO L424 AbstractCegarLoop]: === Iteration 52 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:59:41,844 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:59:41,844 INFO L82 PathProgramCache]: Analyzing trace with hash -1670009527, now seen corresponding path program 37 times [2018-11-10 09:59:41,844 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:59:41,844 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:59:41,845 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:59:41,845 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 09:59:41,845 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:59:41,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:59:43,060 INFO L134 CoverageAnalysis]: Checked inductivity of 138096 backedges. 41152 proven. 3138 refuted. 0 times theorem prover too weak. 93806 trivial. 0 not checked. [2018-11-10 09:59:43,060 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:59:43,060 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:59:43,066 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 09:59:43,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:59:43,280 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:59:44,623 INFO L134 CoverageAnalysis]: Checked inductivity of 138096 backedges. 43256 proven. 954 refuted. 0 times theorem prover too weak. 93886 trivial. 0 not checked. [2018-11-10 09:59:44,639 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:59:44,640 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 40] total 83 [2018-11-10 09:59:44,641 INFO L460 AbstractCegarLoop]: Interpolant automaton has 83 states [2018-11-10 09:59:44,641 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 83 interpolants. [2018-11-10 09:59:44,642 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1058, Invalid=5748, Unknown=0, NotChecked=0, Total=6806 [2018-11-10 09:59:44,642 INFO L87 Difference]: Start difference. First operand 1629 states and 1638 transitions. Second operand 83 states. [2018-11-10 09:59:46,651 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:59:46,651 INFO L93 Difference]: Finished difference Result 1521 states and 1523 transitions. [2018-11-10 09:59:46,652 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 99 states. [2018-11-10 09:59:46,652 INFO L78 Accepts]: Start accepts. Automaton has 83 states. Word has length 1492 [2018-11-10 09:59:46,653 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:59:46,655 INFO L225 Difference]: With dead ends: 1521 [2018-11-10 09:59:46,655 INFO L226 Difference]: Without dead ends: 1509 [2018-11-10 09:59:46,657 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1611 GetRequests, 1456 SyntacticMatches, 0 SemanticMatches, 155 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7666 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=3754, Invalid=20738, Unknown=0, NotChecked=0, Total=24492 [2018-11-10 09:59:46,657 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1509 states. [2018-11-10 09:59:46,663 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1509 to 1502. [2018-11-10 09:59:46,663 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1502 states. [2018-11-10 09:59:46,665 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1502 states to 1502 states and 1503 transitions. [2018-11-10 09:59:46,665 INFO L78 Accepts]: Start accepts. Automaton has 1502 states and 1503 transitions. Word has length 1492 [2018-11-10 09:59:46,665 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:59:46,666 INFO L481 AbstractCegarLoop]: Abstraction has 1502 states and 1503 transitions. [2018-11-10 09:59:46,666 INFO L482 AbstractCegarLoop]: Interpolant automaton has 83 states. [2018-11-10 09:59:46,666 INFO L276 IsEmpty]: Start isEmpty. Operand 1502 states and 1503 transitions. [2018-11-10 09:59:46,675 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1499 [2018-11-10 09:59:46,675 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:59:46,675 INFO L375 BasicCegarLoop]: trace histogram [227, 209, 208, 208, 208, 208, 19, 19, 19, 19, 18, 18, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:59:46,676 INFO L424 AbstractCegarLoop]: === Iteration 53 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:59:46,676 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:59:46,676 INFO L82 PathProgramCache]: Analyzing trace with hash -16917423, now seen corresponding path program 38 times [2018-11-10 09:59:46,676 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:59:46,676 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:59:46,677 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:59:46,677 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 09:59:46,677 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:59:46,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:59:47,556 INFO L134 CoverageAnalysis]: Checked inductivity of 139377 backedges. 22943 proven. 1144 refuted. 0 times theorem prover too weak. 115290 trivial. 0 not checked. [2018-11-10 09:59:47,556 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:59:47,556 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:59:47,562 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-10 09:59:47,770 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-10 09:59:47,770 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 09:59:47,781 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:59:48,513 INFO L134 CoverageAnalysis]: Checked inductivity of 139377 backedges. 22833 proven. 1083 refuted. 0 times theorem prover too weak. 115461 trivial. 0 not checked. [2018-11-10 09:59:48,530 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:59:48,530 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 21] total 45 [2018-11-10 09:59:48,531 INFO L460 AbstractCegarLoop]: Interpolant automaton has 46 states [2018-11-10 09:59:48,531 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2018-11-10 09:59:48,531 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=282, Invalid=1788, Unknown=0, NotChecked=0, Total=2070 [2018-11-10 09:59:48,531 INFO L87 Difference]: Start difference. First operand 1502 states and 1503 transitions. Second operand 46 states. [2018-11-10 09:59:50,047 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:59:50,047 INFO L93 Difference]: Finished difference Result 1658 states and 1662 transitions. [2018-11-10 09:59:50,047 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2018-11-10 09:59:50,047 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 1498 [2018-11-10 09:59:50,048 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:59:50,050 INFO L225 Difference]: With dead ends: 1658 [2018-11-10 09:59:50,050 INFO L226 Difference]: Without dead ends: 1658 [2018-11-10 09:59:50,051 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1545 GetRequests, 1478 SyntacticMatches, 0 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 782 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=500, Invalid=4192, Unknown=0, NotChecked=0, Total=4692 [2018-11-10 09:59:50,051 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1658 states. [2018-11-10 09:59:50,058 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1658 to 1635. [2018-11-10 09:59:50,058 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1635 states. [2018-11-10 09:59:50,060 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1635 states to 1635 states and 1638 transitions. [2018-11-10 09:59:50,060 INFO L78 Accepts]: Start accepts. Automaton has 1635 states and 1638 transitions. Word has length 1498 [2018-11-10 09:59:50,061 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:59:50,061 INFO L481 AbstractCegarLoop]: Abstraction has 1635 states and 1638 transitions. [2018-11-10 09:59:50,061 INFO L482 AbstractCegarLoop]: Interpolant automaton has 46 states. [2018-11-10 09:59:50,062 INFO L276 IsEmpty]: Start isEmpty. Operand 1635 states and 1638 transitions. [2018-11-10 09:59:50,075 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1632 [2018-11-10 09:59:50,075 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:59:50,075 INFO L375 BasicCegarLoop]: trace histogram [248, 229, 228, 228, 228, 228, 20, 20, 20, 20, 19, 19, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:59:50,075 INFO L424 AbstractCegarLoop]: === Iteration 54 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:59:50,076 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:59:50,076 INFO L82 PathProgramCache]: Analyzing trace with hash 1711118422, now seen corresponding path program 39 times [2018-11-10 09:59:50,076 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:59:50,076 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:59:50,077 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:59:50,077 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 09:59:50,077 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:59:50,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:59:51,482 INFO L134 CoverageAnalysis]: Checked inductivity of 166953 backedges. 48009 proven. 3483 refuted. 0 times theorem prover too weak. 115461 trivial. 0 not checked. [2018-11-10 09:59:51,482 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:59:51,482 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:59:51,489 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-10 09:59:51,846 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) [2018-11-10 09:59:51,846 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 09:59:51,855 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:59:52,865 INFO L134 CoverageAnalysis]: Checked inductivity of 166953 backedges. 26382 proven. 1200 refuted. 0 times theorem prover too weak. 139371 trivial. 0 not checked. [2018-11-10 09:59:52,883 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:59:52,883 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 23] total 70 [2018-11-10 09:59:52,884 INFO L460 AbstractCegarLoop]: Interpolant automaton has 70 states [2018-11-10 09:59:52,884 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 70 interpolants. [2018-11-10 09:59:52,884 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=751, Invalid=4079, Unknown=0, NotChecked=0, Total=4830 [2018-11-10 09:59:52,884 INFO L87 Difference]: Start difference. First operand 1635 states and 1638 transitions. Second operand 70 states. [2018-11-10 09:59:54,698 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:59:54,698 INFO L93 Difference]: Finished difference Result 1796 states and 1802 transitions. [2018-11-10 09:59:54,698 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 71 states. [2018-11-10 09:59:54,698 INFO L78 Accepts]: Start accepts. Automaton has 70 states. Word has length 1631 [2018-11-10 09:59:54,699 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:59:54,702 INFO L225 Difference]: With dead ends: 1796 [2018-11-10 09:59:54,702 INFO L226 Difference]: Without dead ends: 1796 [2018-11-10 09:59:54,703 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1740 GetRequests, 1610 SyntacticMatches, 0 SemanticMatches, 130 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4130 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=3932, Invalid=13360, Unknown=0, NotChecked=0, Total=17292 [2018-11-10 09:59:54,704 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1796 states. [2018-11-10 09:59:54,713 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1796 to 1786. [2018-11-10 09:59:54,713 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1786 states. [2018-11-10 09:59:54,715 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1786 states to 1786 states and 1792 transitions. [2018-11-10 09:59:54,715 INFO L78 Accepts]: Start accepts. Automaton has 1786 states and 1792 transitions. Word has length 1631 [2018-11-10 09:59:54,716 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:59:54,716 INFO L481 AbstractCegarLoop]: Abstraction has 1786 states and 1792 transitions. [2018-11-10 09:59:54,716 INFO L482 AbstractCegarLoop]: Interpolant automaton has 70 states. [2018-11-10 09:59:54,716 INFO L276 IsEmpty]: Start isEmpty. Operand 1786 states and 1792 transitions. [2018-11-10 09:59:54,727 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1644 [2018-11-10 09:59:54,727 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:59:54,727 INFO L375 BasicCegarLoop]: trace histogram [250, 231, 230, 230, 230, 230, 20, 20, 20, 20, 19, 19, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:59:54,727 INFO L424 AbstractCegarLoop]: === Iteration 55 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:59:54,728 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:59:54,728 INFO L82 PathProgramCache]: Analyzing trace with hash 455998870, now seen corresponding path program 40 times [2018-11-10 09:59:54,728 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:59:54,728 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:59:54,729 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:59:54,729 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 09:59:54,729 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:59:54,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 09:59:56,033 INFO L134 CoverageAnalysis]: Checked inductivity of 169777 backedges. 29077 proven. 1316 refuted. 0 times theorem prover too weak. 139384 trivial. 0 not checked. [2018-11-10 09:59:56,033 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 09:59:56,034 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 09:59:56,053 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-10 09:59:56,246 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-10 09:59:56,246 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 09:59:56,257 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 09:59:57,499 INFO L134 CoverageAnalysis]: Checked inductivity of 169777 backedges. 29139 proven. 1254 refuted. 0 times theorem prover too weak. 139384 trivial. 0 not checked. [2018-11-10 09:59:57,517 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 09:59:57,517 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 45] total 69 [2018-11-10 09:59:57,518 INFO L460 AbstractCegarLoop]: Interpolant automaton has 69 states [2018-11-10 09:59:57,518 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2018-11-10 09:59:57,518 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1082, Invalid=3610, Unknown=0, NotChecked=0, Total=4692 [2018-11-10 09:59:57,518 INFO L87 Difference]: Start difference. First operand 1786 states and 1792 transitions. Second operand 69 states. [2018-11-10 09:59:58,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 09:59:58,727 INFO L93 Difference]: Finished difference Result 2072 states and 2082 transitions. [2018-11-10 09:59:58,727 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2018-11-10 09:59:58,727 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 1643 [2018-11-10 09:59:58,728 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 09:59:58,731 INFO L225 Difference]: With dead ends: 2072 [2018-11-10 09:59:58,731 INFO L226 Difference]: Without dead ends: 2072 [2018-11-10 09:59:58,732 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1729 GetRequests, 1621 SyntacticMatches, 0 SemanticMatches, 108 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2009 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=3047, Invalid=8943, Unknown=0, NotChecked=0, Total=11990 [2018-11-10 09:59:58,733 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2072 states. [2018-11-10 09:59:58,740 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2072 to 2061. [2018-11-10 09:59:58,741 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2061 states. [2018-11-10 09:59:58,742 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2061 states to 2061 states and 2071 transitions. [2018-11-10 09:59:58,743 INFO L78 Accepts]: Start accepts. Automaton has 2061 states and 2071 transitions. Word has length 1643 [2018-11-10 09:59:58,743 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 09:59:58,743 INFO L481 AbstractCegarLoop]: Abstraction has 2061 states and 2071 transitions. [2018-11-10 09:59:58,743 INFO L482 AbstractCegarLoop]: Interpolant automaton has 69 states. [2018-11-10 09:59:58,744 INFO L276 IsEmpty]: Start isEmpty. Operand 2061 states and 2071 transitions. [2018-11-10 09:59:58,756 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1771 [2018-11-10 09:59:58,756 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 09:59:58,756 INFO L375 BasicCegarLoop]: trace histogram [270, 250, 249, 249, 249, 249, 21, 21, 21, 21, 20, 20, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 09:59:58,757 INFO L424 AbstractCegarLoop]: === Iteration 56 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 09:59:58,757 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 09:59:58,757 INFO L82 PathProgramCache]: Analyzing trace with hash -796381911, now seen corresponding path program 41 times [2018-11-10 09:59:58,757 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 09:59:58,757 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 09:59:58,758 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:59:58,758 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 09:59:58,758 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 09:59:58,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 10:00:00,371 INFO L134 CoverageAnalysis]: Checked inductivity of 198553 backedges. 52053 proven. 5972 refuted. 0 times theorem prover too weak. 140528 trivial. 0 not checked. [2018-11-10 10:00:00,371 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 10:00:00,372 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 10:00:00,378 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-10 10:00:04,027 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 53 check-sat command(s) [2018-11-10 10:00:04,028 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 10:00:04,049 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 10:00:05,839 INFO L134 CoverageAnalysis]: Checked inductivity of 198553 backedges. 77678 proven. 6466 refuted. 0 times theorem prover too weak. 114409 trivial. 0 not checked. [2018-11-10 10:00:05,860 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 10:00:05,860 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 46] total 93 [2018-11-10 10:00:05,861 INFO L460 AbstractCegarLoop]: Interpolant automaton has 93 states [2018-11-10 10:00:05,861 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 93 interpolants. [2018-11-10 10:00:05,862 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1173, Invalid=7383, Unknown=0, NotChecked=0, Total=8556 [2018-11-10 10:00:05,862 INFO L87 Difference]: Start difference. First operand 2061 states and 2071 transitions. Second operand 93 states. [2018-11-10 10:00:08,672 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 10:00:08,672 INFO L93 Difference]: Finished difference Result 1799 states and 1802 transitions. [2018-11-10 10:00:08,672 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 111 states. [2018-11-10 10:00:08,673 INFO L78 Accepts]: Start accepts. Automaton has 93 states. Word has length 1770 [2018-11-10 10:00:08,673 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 10:00:08,675 INFO L225 Difference]: With dead ends: 1799 [2018-11-10 10:00:08,675 INFO L226 Difference]: Without dead ends: 1790 [2018-11-10 10:00:08,677 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1923 GetRequests, 1729 SyntacticMatches, 0 SemanticMatches, 194 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12588 ImplicationChecksByTransitivity, 2.8s TimeCoverageRelationStatistics Valid=5595, Invalid=32625, Unknown=0, NotChecked=0, Total=38220 [2018-11-10 10:00:08,678 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states. [2018-11-10 10:00:08,683 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1786. [2018-11-10 10:00:08,683 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1786 states. [2018-11-10 10:00:08,684 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1786 states to 1786 states and 1789 transitions. [2018-11-10 10:00:08,685 INFO L78 Accepts]: Start accepts. Automaton has 1786 states and 1789 transitions. Word has length 1770 [2018-11-10 10:00:08,685 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 10:00:08,685 INFO L481 AbstractCegarLoop]: Abstraction has 1786 states and 1789 transitions. [2018-11-10 10:00:08,685 INFO L482 AbstractCegarLoop]: Interpolant automaton has 93 states. [2018-11-10 10:00:08,685 INFO L276 IsEmpty]: Start isEmpty. Operand 1786 states and 1789 transitions. [2018-11-10 10:00:08,696 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1777 [2018-11-10 10:00:08,697 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 10:00:08,697 INFO L375 BasicCegarLoop]: trace histogram [271, 251, 250, 250, 250, 250, 21, 21, 21, 21, 20, 20, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 10:00:08,697 INFO L424 AbstractCegarLoop]: === Iteration 57 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 10:00:08,697 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 10:00:08,697 INFO L82 PathProgramCache]: Analyzing trace with hash 2070207201, now seen corresponding path program 42 times [2018-11-10 10:00:08,697 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 10:00:08,697 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 10:00:08,698 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:00:08,698 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 10:00:08,698 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:00:08,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 10:00:10,308 INFO L134 CoverageAnalysis]: Checked inductivity of 200090 backedges. 55587 proven. 3846 refuted. 0 times theorem prover too weak. 140657 trivial. 0 not checked. [2018-11-10 10:00:10,308 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 10:00:10,308 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 10:00:10,315 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-10 10:00:11,419 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 43 check-sat command(s) [2018-11-10 10:00:11,420 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 10:00:11,432 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 10:00:12,712 INFO L134 CoverageAnalysis]: Checked inductivity of 200090 backedges. 54408 proven. 3825 refuted. 0 times theorem prover too weak. 141857 trivial. 0 not checked. [2018-11-10 10:00:12,730 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 10:00:12,731 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 30] total 74 [2018-11-10 10:00:12,732 INFO L460 AbstractCegarLoop]: Interpolant automaton has 74 states [2018-11-10 10:00:12,732 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 74 interpolants. [2018-11-10 10:00:12,732 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1055, Invalid=4347, Unknown=0, NotChecked=0, Total=5402 [2018-11-10 10:00:12,732 INFO L87 Difference]: Start difference. First operand 1786 states and 1789 transitions. Second operand 74 states. [2018-11-10 10:00:14,197 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 10:00:14,197 INFO L93 Difference]: Finished difference Result 1938 states and 1943 transitions. [2018-11-10 10:00:14,197 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2018-11-10 10:00:14,197 INFO L78 Accepts]: Start accepts. Automaton has 74 states. Word has length 1776 [2018-11-10 10:00:14,198 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 10:00:14,200 INFO L225 Difference]: With dead ends: 1938 [2018-11-10 10:00:14,200 INFO L226 Difference]: Without dead ends: 1938 [2018-11-10 10:00:14,201 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1889 GetRequests, 1753 SyntacticMatches, 0 SemanticMatches, 136 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5705 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=4517, Invalid=14389, Unknown=0, NotChecked=0, Total=18906 [2018-11-10 10:00:14,201 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1938 states. [2018-11-10 10:00:14,208 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1938 to 1931. [2018-11-10 10:00:14,208 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1931 states. [2018-11-10 10:00:14,209 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1931 states to 1931 states and 1936 transitions. [2018-11-10 10:00:14,209 INFO L78 Accepts]: Start accepts. Automaton has 1931 states and 1936 transitions. Word has length 1776 [2018-11-10 10:00:14,210 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 10:00:14,210 INFO L481 AbstractCegarLoop]: Abstraction has 1931 states and 1936 transitions. [2018-11-10 10:00:14,210 INFO L482 AbstractCegarLoop]: Interpolant automaton has 74 states. [2018-11-10 10:00:14,210 INFO L276 IsEmpty]: Start isEmpty. Operand 1931 states and 1936 transitions. [2018-11-10 10:00:14,221 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1783 [2018-11-10 10:00:14,222 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 10:00:14,222 INFO L375 BasicCegarLoop]: trace histogram [272, 252, 251, 251, 251, 251, 21, 21, 21, 21, 20, 20, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 10:00:14,222 INFO L424 AbstractCegarLoop]: === Iteration 58 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 10:00:14,222 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 10:00:14,222 INFO L82 PathProgramCache]: Analyzing trace with hash 1310697, now seen corresponding path program 43 times [2018-11-10 10:00:14,222 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 10:00:14,222 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 10:00:14,223 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:00:14,223 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 10:00:14,223 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:00:14,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 10:00:15,405 INFO L134 CoverageAnalysis]: Checked inductivity of 201633 backedges. 30672 proven. 1411 refuted. 0 times theorem prover too weak. 169550 trivial. 0 not checked. [2018-11-10 10:00:15,405 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 10:00:15,405 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 10:00:15,412 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 10:00:15,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 10:00:15,660 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 10:00:16,631 INFO L134 CoverageAnalysis]: Checked inductivity of 201633 backedges. 30550 proven. 1323 refuted. 0 times theorem prover too weak. 169760 trivial. 0 not checked. [2018-11-10 10:00:16,648 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 10:00:16,649 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 23] total 49 [2018-11-10 10:00:16,650 INFO L460 AbstractCegarLoop]: Interpolant automaton has 50 states [2018-11-10 10:00:16,650 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2018-11-10 10:00:16,650 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=331, Invalid=2119, Unknown=0, NotChecked=0, Total=2450 [2018-11-10 10:00:16,650 INFO L87 Difference]: Start difference. First operand 1931 states and 1936 transitions. Second operand 50 states. [2018-11-10 10:00:18,357 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 10:00:18,357 INFO L93 Difference]: Finished difference Result 2245 states and 2256 transitions. [2018-11-10 10:00:18,358 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2018-11-10 10:00:18,358 INFO L78 Accepts]: Start accepts. Automaton has 50 states. Word has length 1782 [2018-11-10 10:00:18,358 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 10:00:18,361 INFO L225 Difference]: With dead ends: 2245 [2018-11-10 10:00:18,361 INFO L226 Difference]: Without dead ends: 2245 [2018-11-10 10:00:18,361 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1834 GetRequests, 1760 SyntacticMatches, 0 SemanticMatches, 74 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 952 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=577, Invalid=5123, Unknown=0, NotChecked=0, Total=5700 [2018-11-10 10:00:18,362 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2245 states. [2018-11-10 10:00:18,370 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2245 to 2218. [2018-11-10 10:00:18,370 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2218 states. [2018-11-10 10:00:18,372 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2218 states to 2218 states and 2228 transitions. [2018-11-10 10:00:18,372 INFO L78 Accepts]: Start accepts. Automaton has 2218 states and 2228 transitions. Word has length 1782 [2018-11-10 10:00:18,373 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 10:00:18,373 INFO L481 AbstractCegarLoop]: Abstraction has 2218 states and 2228 transitions. [2018-11-10 10:00:18,373 INFO L482 AbstractCegarLoop]: Interpolant automaton has 50 states. [2018-11-10 10:00:18,373 INFO L276 IsEmpty]: Start isEmpty. Operand 2218 states and 2228 transitions. [2018-11-10 10:00:18,386 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1922 [2018-11-10 10:00:18,386 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 10:00:18,386 INFO L375 BasicCegarLoop]: trace histogram [294, 273, 272, 272, 272, 272, 22, 22, 22, 22, 21, 21, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 10:00:18,387 INFO L424 AbstractCegarLoop]: === Iteration 59 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 10:00:18,387 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 10:00:18,387 INFO L82 PathProgramCache]: Analyzing trace with hash 1949089206, now seen corresponding path program 44 times [2018-11-10 10:00:18,387 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 10:00:18,387 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 10:00:18,387 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:00:18,387 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 10:00:18,387 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:00:18,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 10:00:20,217 INFO L134 CoverageAnalysis]: Checked inductivity of 236232 backedges. 60023 proven. 6585 refuted. 0 times theorem prover too weak. 169624 trivial. 0 not checked. [2018-11-10 10:00:20,218 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 10:00:20,218 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 10:00:20,224 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-10 10:00:20,481 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-10 10:00:20,481 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 10:00:20,495 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 10:00:22,315 INFO L134 CoverageAnalysis]: Checked inductivity of 236232 backedges. 90006 proven. 1180 refuted. 0 times theorem prover too weak. 145046 trivial. 0 not checked. [2018-11-10 10:00:22,333 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 10:00:22,333 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 44] total 93 [2018-11-10 10:00:22,334 INFO L460 AbstractCegarLoop]: Interpolant automaton has 93 states [2018-11-10 10:00:22,334 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 93 interpolants. [2018-11-10 10:00:22,334 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1301, Invalid=7255, Unknown=0, NotChecked=0, Total=8556 [2018-11-10 10:00:22,334 INFO L87 Difference]: Start difference. First operand 2218 states and 2228 transitions. Second operand 93 states. [2018-11-10 10:00:24,294 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 10:00:24,294 INFO L93 Difference]: Finished difference Result 1950 states and 1953 transitions. [2018-11-10 10:00:24,294 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 111 states. [2018-11-10 10:00:24,294 INFO L78 Accepts]: Start accepts. Automaton has 93 states. Word has length 1921 [2018-11-10 10:00:24,295 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 10:00:24,297 INFO L225 Difference]: With dead ends: 1950 [2018-11-10 10:00:24,297 INFO L226 Difference]: Without dead ends: 1941 [2018-11-10 10:00:24,299 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2056 GetRequests, 1881 SyntacticMatches, 0 SemanticMatches, 175 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9854 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=4707, Invalid=26445, Unknown=0, NotChecked=0, Total=31152 [2018-11-10 10:00:24,299 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1941 states. [2018-11-10 10:00:24,308 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1941 to 1937. [2018-11-10 10:00:24,308 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1937 states. [2018-11-10 10:00:24,310 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1937 states to 1937 states and 1940 transitions. [2018-11-10 10:00:24,310 INFO L78 Accepts]: Start accepts. Automaton has 1937 states and 1940 transitions. Word has length 1921 [2018-11-10 10:00:24,311 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 10:00:24,311 INFO L481 AbstractCegarLoop]: Abstraction has 1937 states and 1940 transitions. [2018-11-10 10:00:24,311 INFO L482 AbstractCegarLoop]: Interpolant automaton has 93 states. [2018-11-10 10:00:24,311 INFO L276 IsEmpty]: Start isEmpty. Operand 1937 states and 1940 transitions. [2018-11-10 10:00:24,334 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1928 [2018-11-10 10:00:24,334 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 10:00:24,334 INFO L375 BasicCegarLoop]: trace histogram [295, 274, 273, 273, 273, 273, 22, 22, 22, 22, 21, 21, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 10:00:24,335 INFO L424 AbstractCegarLoop]: === Iteration 60 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 10:00:24,335 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 10:00:24,335 INFO L82 PathProgramCache]: Analyzing trace with hash -1427912274, now seen corresponding path program 45 times [2018-11-10 10:00:24,335 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 10:00:24,335 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 10:00:24,336 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:00:24,336 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 10:00:24,336 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:00:24,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 10:00:26,183 INFO L134 CoverageAnalysis]: Checked inductivity of 237909 backedges. 63922 proven. 4227 refuted. 0 times theorem prover too weak. 169760 trivial. 0 not checked. [2018-11-10 10:00:26,184 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 10:00:26,184 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 10:00:26,190 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-10 10:00:26,843 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 23 check-sat command(s) [2018-11-10 10:00:26,844 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 10:00:26,855 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 10:00:28,272 INFO L134 CoverageAnalysis]: Checked inductivity of 237909 backedges. 62621 proven. 4205 refuted. 0 times theorem prover too weak. 171083 trivial. 0 not checked. [2018-11-10 10:00:28,289 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 10:00:28,290 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 31] total 77 [2018-11-10 10:00:28,291 INFO L460 AbstractCegarLoop]: Interpolant automaton has 77 states [2018-11-10 10:00:28,291 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 77 interpolants. [2018-11-10 10:00:28,291 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1148, Invalid=4704, Unknown=0, NotChecked=0, Total=5852 [2018-11-10 10:00:28,291 INFO L87 Difference]: Start difference. First operand 1937 states and 1940 transitions. Second operand 77 states. [2018-11-10 10:00:29,962 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 10:00:29,963 INFO L93 Difference]: Finished difference Result 2095 states and 2100 transitions. [2018-11-10 10:00:29,963 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 75 states. [2018-11-10 10:00:29,963 INFO L78 Accepts]: Start accepts. Automaton has 77 states. Word has length 1927 [2018-11-10 10:00:29,964 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 10:00:29,967 INFO L225 Difference]: With dead ends: 2095 [2018-11-10 10:00:29,967 INFO L226 Difference]: Without dead ends: 2095 [2018-11-10 10:00:29,969 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2045 GetRequests, 1903 SyntacticMatches, 0 SemanticMatches, 142 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6241 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=4928, Invalid=15664, Unknown=0, NotChecked=0, Total=20592 [2018-11-10 10:00:29,970 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2095 states. [2018-11-10 10:00:29,981 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2095 to 2088. [2018-11-10 10:00:29,981 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2088 states. [2018-11-10 10:00:29,983 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2088 states to 2088 states and 2093 transitions. [2018-11-10 10:00:29,984 INFO L78 Accepts]: Start accepts. Automaton has 2088 states and 2093 transitions. Word has length 1927 [2018-11-10 10:00:29,985 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 10:00:29,985 INFO L481 AbstractCegarLoop]: Abstraction has 2088 states and 2093 transitions. [2018-11-10 10:00:29,985 INFO L482 AbstractCegarLoop]: Interpolant automaton has 77 states. [2018-11-10 10:00:29,985 INFO L276 IsEmpty]: Start isEmpty. Operand 2088 states and 2093 transitions. [2018-11-10 10:00:30,000 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1934 [2018-11-10 10:00:30,000 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 10:00:30,000 INFO L375 BasicCegarLoop]: trace histogram [296, 275, 274, 274, 274, 274, 22, 22, 22, 22, 21, 21, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 10:00:30,001 INFO L424 AbstractCegarLoop]: === Iteration 61 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 10:00:30,001 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 10:00:30,001 INFO L82 PathProgramCache]: Analyzing trace with hash 398861558, now seen corresponding path program 46 times [2018-11-10 10:00:30,001 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 10:00:30,001 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 10:00:30,002 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:00:30,002 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 10:00:30,002 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:00:30,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 10:00:31,318 INFO L134 CoverageAnalysis]: Checked inductivity of 239592 backedges. 35237 proven. 1555 refuted. 0 times theorem prover too weak. 202800 trivial. 0 not checked. [2018-11-10 10:00:31,319 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 10:00:31,319 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 10:00:31,325 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-10 10:00:34,646 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-10 10:00:34,646 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 10:00:34,666 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 10:00:35,786 INFO L134 CoverageAnalysis]: Checked inductivity of 239592 backedges. 34986 proven. 1452 refuted. 0 times theorem prover too weak. 203154 trivial. 0 not checked. [2018-11-10 10:00:35,808 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 10:00:35,809 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 24] total 52 [2018-11-10 10:00:35,809 INFO L460 AbstractCegarLoop]: Interpolant automaton has 53 states [2018-11-10 10:00:35,809 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2018-11-10 10:00:35,810 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=361, Invalid=2395, Unknown=0, NotChecked=0, Total=2756 [2018-11-10 10:00:35,810 INFO L87 Difference]: Start difference. First operand 2088 states and 2093 transitions. Second operand 53 states. [2018-11-10 10:00:37,736 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 10:00:37,736 INFO L93 Difference]: Finished difference Result 2414 states and 2425 transitions. [2018-11-10 10:00:37,736 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 75 states. [2018-11-10 10:00:37,736 INFO L78 Accepts]: Start accepts. Automaton has 53 states. Word has length 1933 [2018-11-10 10:00:37,737 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 10:00:37,739 INFO L225 Difference]: With dead ends: 2414 [2018-11-10 10:00:37,739 INFO L226 Difference]: Without dead ends: 2414 [2018-11-10 10:00:37,739 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 1988 GetRequests, 1910 SyntacticMatches, 0 SemanticMatches, 78 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1095 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=639, Invalid=5681, Unknown=0, NotChecked=0, Total=6320 [2018-11-10 10:00:37,740 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2414 states. [2018-11-10 10:00:37,749 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2414 to 2387. [2018-11-10 10:00:37,749 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2387 states. [2018-11-10 10:00:37,751 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2387 states to 2387 states and 2397 transitions. [2018-11-10 10:00:37,751 INFO L78 Accepts]: Start accepts. Automaton has 2387 states and 2397 transitions. Word has length 1933 [2018-11-10 10:00:37,752 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 10:00:37,752 INFO L481 AbstractCegarLoop]: Abstraction has 2387 states and 2397 transitions. [2018-11-10 10:00:37,752 INFO L482 AbstractCegarLoop]: Interpolant automaton has 53 states. [2018-11-10 10:00:37,752 INFO L276 IsEmpty]: Start isEmpty. Operand 2387 states and 2397 transitions. [2018-11-10 10:00:37,769 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2079 [2018-11-10 10:00:37,769 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 10:00:37,769 INFO L375 BasicCegarLoop]: trace histogram [319, 297, 296, 296, 296, 296, 23, 23, 23, 23, 22, 22, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 10:00:37,770 INFO L424 AbstractCegarLoop]: === Iteration 62 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 10:00:37,770 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 10:00:37,770 INFO L82 PathProgramCache]: Analyzing trace with hash 1244923457, now seen corresponding path program 47 times [2018-11-10 10:00:37,770 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 10:00:37,770 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 10:00:37,771 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:00:37,771 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 10:00:37,771 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:00:37,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 10:00:39,803 INFO L134 CoverageAnalysis]: Checked inductivity of 279007 backedges. 68768 proven. 7228 refuted. 0 times theorem prover too weak. 203011 trivial. 0 not checked. [2018-11-10 10:00:39,803 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 10:00:39,803 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 10:00:39,810 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-10 10:00:47,684 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 56 check-sat command(s) [2018-11-10 10:00:47,684 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 10:00:47,711 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 10:00:49,954 INFO L134 CoverageAnalysis]: Checked inductivity of 279007 backedges. 102768 proven. 7848 refuted. 0 times theorem prover too weak. 168391 trivial. 0 not checked. [2018-11-10 10:00:49,977 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 10:00:49,978 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 50] total 101 [2018-11-10 10:00:49,978 INFO L460 AbstractCegarLoop]: Interpolant automaton has 101 states [2018-11-10 10:00:49,979 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 101 interpolants. [2018-11-10 10:00:49,979 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1396, Invalid=8704, Unknown=0, NotChecked=0, Total=10100 [2018-11-10 10:00:49,979 INFO L87 Difference]: Start difference. First operand 2387 states and 2397 transitions. Second operand 101 states. [2018-11-10 10:00:53,092 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 10:00:53,092 INFO L93 Difference]: Finished difference Result 2107 states and 2110 transitions. [2018-11-10 10:00:53,092 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 121 states. [2018-11-10 10:00:53,092 INFO L78 Accepts]: Start accepts. Automaton has 101 states. Word has length 2078 [2018-11-10 10:00:53,093 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 10:00:53,095 INFO L225 Difference]: With dead ends: 2107 [2018-11-10 10:00:53,095 INFO L226 Difference]: Without dead ends: 2098 [2018-11-10 10:00:53,098 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2245 GetRequests, 2033 SyntacticMatches, 0 SemanticMatches, 212 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15151 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=6669, Invalid=38913, Unknown=0, NotChecked=0, Total=45582 [2018-11-10 10:00:53,099 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2098 states. [2018-11-10 10:00:53,106 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2098 to 2094. [2018-11-10 10:00:53,106 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2094 states. [2018-11-10 10:00:53,108 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2094 states to 2094 states and 2097 transitions. [2018-11-10 10:00:53,108 INFO L78 Accepts]: Start accepts. Automaton has 2094 states and 2097 transitions. Word has length 2078 [2018-11-10 10:00:53,109 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 10:00:53,109 INFO L481 AbstractCegarLoop]: Abstraction has 2094 states and 2097 transitions. [2018-11-10 10:00:53,109 INFO L482 AbstractCegarLoop]: Interpolant automaton has 101 states. [2018-11-10 10:00:53,109 INFO L276 IsEmpty]: Start isEmpty. Operand 2094 states and 2097 transitions. [2018-11-10 10:00:53,125 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2085 [2018-11-10 10:00:53,125 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 10:00:53,126 INFO L375 BasicCegarLoop]: trace histogram [320, 298, 297, 297, 297, 297, 23, 23, 23, 23, 22, 22, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 10:00:53,126 INFO L424 AbstractCegarLoop]: === Iteration 63 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 10:00:53,126 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 10:00:53,126 INFO L82 PathProgramCache]: Analyzing trace with hash -195560967, now seen corresponding path program 48 times [2018-11-10 10:00:53,126 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 10:00:53,126 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 10:00:53,127 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:00:53,127 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 10:00:53,127 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:00:53,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 10:00:55,186 INFO L134 CoverageAnalysis]: Checked inductivity of 280830 backedges. 73050 proven. 4626 refuted. 0 times theorem prover too weak. 203154 trivial. 0 not checked. [2018-11-10 10:00:55,186 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 10:00:55,186 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 10:00:55,194 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-10 10:00:57,307 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 47 check-sat command(s) [2018-11-10 10:00:57,307 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 10:00:57,323 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 10:00:58,939 INFO L134 CoverageAnalysis]: Checked inductivity of 280830 backedges. 71621 proven. 4603 refuted. 0 times theorem prover too weak. 204606 trivial. 0 not checked. [2018-11-10 10:00:58,958 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 10:00:58,959 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 32] total 80 [2018-11-10 10:00:58,959 INFO L460 AbstractCegarLoop]: Interpolant automaton has 80 states [2018-11-10 10:00:58,960 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 80 interpolants. [2018-11-10 10:00:58,960 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1245, Invalid=5075, Unknown=0, NotChecked=0, Total=6320 [2018-11-10 10:00:58,960 INFO L87 Difference]: Start difference. First operand 2094 states and 2097 transitions. Second operand 80 states. [2018-11-10 10:01:00,645 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 10:01:00,645 INFO L93 Difference]: Finished difference Result 2258 states and 2263 transitions. [2018-11-10 10:01:00,646 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 78 states. [2018-11-10 10:01:00,646 INFO L78 Accepts]: Start accepts. Automaton has 80 states. Word has length 2084 [2018-11-10 10:01:00,646 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 10:01:00,648 INFO L225 Difference]: With dead ends: 2258 [2018-11-10 10:01:00,649 INFO L226 Difference]: Without dead ends: 2258 [2018-11-10 10:01:00,650 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2207 GetRequests, 2059 SyntacticMatches, 0 SemanticMatches, 148 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6801 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=5357, Invalid=16993, Unknown=0, NotChecked=0, Total=22350 [2018-11-10 10:01:00,650 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2258 states. [2018-11-10 10:01:00,658 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2258 to 2251. [2018-11-10 10:01:00,658 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2251 states. [2018-11-10 10:01:00,659 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2251 states to 2251 states and 2256 transitions. [2018-11-10 10:01:00,659 INFO L78 Accepts]: Start accepts. Automaton has 2251 states and 2256 transitions. Word has length 2084 [2018-11-10 10:01:00,660 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 10:01:00,660 INFO L481 AbstractCegarLoop]: Abstraction has 2251 states and 2256 transitions. [2018-11-10 10:01:00,660 INFO L482 AbstractCegarLoop]: Interpolant automaton has 80 states. [2018-11-10 10:01:00,660 INFO L276 IsEmpty]: Start isEmpty. Operand 2251 states and 2256 transitions. [2018-11-10 10:01:00,676 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2091 [2018-11-10 10:01:00,676 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 10:01:00,676 INFO L375 BasicCegarLoop]: trace histogram [321, 299, 298, 298, 298, 298, 23, 23, 23, 23, 22, 22, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 10:01:00,676 INFO L424 AbstractCegarLoop]: === Iteration 64 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 10:01:00,676 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 10:01:00,676 INFO L82 PathProgramCache]: Analyzing trace with hash 1942418689, now seen corresponding path program 49 times [2018-11-10 10:01:00,676 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 10:01:00,677 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 10:01:00,677 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:01:00,677 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 10:01:00,677 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:01:00,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 10:01:02,222 INFO L134 CoverageAnalysis]: Checked inductivity of 282659 backedges. 39965 proven. 1706 refuted. 0 times theorem prover too weak. 240988 trivial. 0 not checked. [2018-11-10 10:01:02,222 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 10:01:02,222 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 10:01:02,230 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 10:01:02,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 10:01:02,539 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 10:01:03,842 INFO L134 CoverageAnalysis]: Checked inductivity of 282659 backedges. 39831 proven. 1587 refuted. 0 times theorem prover too weak. 241241 trivial. 0 not checked. [2018-11-10 10:01:03,859 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 10:01:03,860 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 25] total 53 [2018-11-10 10:01:03,861 INFO L460 AbstractCegarLoop]: Interpolant automaton has 54 states [2018-11-10 10:01:03,861 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2018-11-10 10:01:03,861 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=384, Invalid=2478, Unknown=0, NotChecked=0, Total=2862 [2018-11-10 10:01:03,861 INFO L87 Difference]: Start difference. First operand 2251 states and 2256 transitions. Second operand 54 states. [2018-11-10 10:01:05,824 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 10:01:05,824 INFO L93 Difference]: Finished difference Result 2589 states and 2600 transitions. [2018-11-10 10:01:05,824 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 78 states. [2018-11-10 10:01:05,825 INFO L78 Accepts]: Start accepts. Automaton has 54 states. Word has length 2090 [2018-11-10 10:01:05,825 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 10:01:05,827 INFO L225 Difference]: With dead ends: 2589 [2018-11-10 10:01:05,828 INFO L226 Difference]: Without dead ends: 2589 [2018-11-10 10:01:05,828 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2146 GetRequests, 2066 SyntacticMatches, 0 SemanticMatches, 80 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1111 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=650, Invalid=5992, Unknown=0, NotChecked=0, Total=6642 [2018-11-10 10:01:05,829 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2589 states. [2018-11-10 10:01:05,838 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2589 to 2562. [2018-11-10 10:01:05,838 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2562 states. [2018-11-10 10:01:05,840 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2562 states to 2562 states and 2572 transitions. [2018-11-10 10:01:05,840 INFO L78 Accepts]: Start accepts. Automaton has 2562 states and 2572 transitions. Word has length 2090 [2018-11-10 10:01:05,841 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 10:01:05,841 INFO L481 AbstractCegarLoop]: Abstraction has 2562 states and 2572 transitions. [2018-11-10 10:01:05,841 INFO L482 AbstractCegarLoop]: Interpolant automaton has 54 states. [2018-11-10 10:01:05,841 INFO L276 IsEmpty]: Start isEmpty. Operand 2562 states and 2572 transitions. [2018-11-10 10:01:05,858 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2242 [2018-11-10 10:01:05,859 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 10:01:05,859 INFO L375 BasicCegarLoop]: trace histogram [345, 322, 321, 321, 321, 321, 24, 24, 24, 24, 23, 23, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 10:01:05,859 INFO L424 AbstractCegarLoop]: === Iteration 65 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 10:01:05,859 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 10:01:05,859 INFO L82 PathProgramCache]: Analyzing trace with hash 1481684878, now seen corresponding path program 50 times [2018-11-10 10:01:05,859 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 10:01:05,859 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 10:01:05,860 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:01:05,860 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 10:01:05,860 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:01:05,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 10:01:08,158 INFO L134 CoverageAnalysis]: Checked inductivity of 327316 backedges. 78324 proven. 7901 refuted. 0 times theorem prover too weak. 241091 trivial. 0 not checked. [2018-11-10 10:01:08,158 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 10:01:08,158 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 10:01:08,164 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-10 10:01:08,510 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-10 10:01:08,510 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 10:01:08,527 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 10:01:10,828 INFO L134 CoverageAnalysis]: Checked inductivity of 327316 backedges. 117534 proven. 1430 refuted. 0 times theorem prover too weak. 208352 trivial. 0 not checked. [2018-11-10 10:01:10,847 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 10:01:10,847 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 48] total 101 [2018-11-10 10:01:10,848 INFO L460 AbstractCegarLoop]: Interpolant automaton has 101 states [2018-11-10 10:01:10,848 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 101 interpolants. [2018-11-10 10:01:10,849 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1538, Invalid=8562, Unknown=0, NotChecked=0, Total=10100 [2018-11-10 10:01:10,849 INFO L87 Difference]: Start difference. First operand 2562 states and 2572 transitions. Second operand 101 states. [2018-11-10 10:01:13,324 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 10:01:13,324 INFO L93 Difference]: Finished difference Result 2270 states and 2273 transitions. [2018-11-10 10:01:13,324 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 121 states. [2018-11-10 10:01:13,324 INFO L78 Accepts]: Start accepts. Automaton has 101 states. Word has length 2241 [2018-11-10 10:01:13,325 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 10:01:13,327 INFO L225 Difference]: With dead ends: 2270 [2018-11-10 10:01:13,327 INFO L226 Difference]: Without dead ends: 2261 [2018-11-10 10:01:13,329 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2388 GetRequests, 2197 SyntacticMatches, 0 SemanticMatches, 191 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11806 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=5588, Invalid=31468, Unknown=0, NotChecked=0, Total=37056 [2018-11-10 10:01:13,330 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2261 states. [2018-11-10 10:01:13,336 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2261 to 2257. [2018-11-10 10:01:13,336 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2257 states. [2018-11-10 10:01:13,338 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2257 states to 2257 states and 2260 transitions. [2018-11-10 10:01:13,338 INFO L78 Accepts]: Start accepts. Automaton has 2257 states and 2260 transitions. Word has length 2241 [2018-11-10 10:01:13,339 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 10:01:13,339 INFO L481 AbstractCegarLoop]: Abstraction has 2257 states and 2260 transitions. [2018-11-10 10:01:13,339 INFO L482 AbstractCegarLoop]: Interpolant automaton has 101 states. [2018-11-10 10:01:13,339 INFO L276 IsEmpty]: Start isEmpty. Operand 2257 states and 2260 transitions. [2018-11-10 10:01:13,356 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2248 [2018-11-10 10:01:13,356 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 10:01:13,357 INFO L375 BasicCegarLoop]: trace histogram [346, 323, 322, 322, 322, 322, 24, 24, 24, 24, 23, 23, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 10:01:13,357 INFO L424 AbstractCegarLoop]: === Iteration 66 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 10:01:13,357 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 10:01:13,357 INFO L82 PathProgramCache]: Analyzing trace with hash -1523222138, now seen corresponding path program 51 times [2018-11-10 10:01:13,357 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 10:01:13,357 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 10:01:13,357 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:01:13,358 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 10:01:13,358 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:01:13,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 10:01:15,659 INFO L134 CoverageAnalysis]: Checked inductivity of 329291 backedges. 83007 proven. 5043 refuted. 0 times theorem prover too weak. 241241 trivial. 0 not checked. [2018-11-10 10:01:15,659 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 10:01:15,659 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 10:01:15,664 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-10 10:01:16,393 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 25 check-sat command(s) [2018-11-10 10:01:16,393 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 10:01:16,406 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 10:01:18,255 INFO L134 CoverageAnalysis]: Checked inductivity of 329291 backedges. 81444 proven. 5019 refuted. 0 times theorem prover too weak. 242828 trivial. 0 not checked. [2018-11-10 10:01:18,273 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 10:01:18,273 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 33] total 83 [2018-11-10 10:01:18,274 INFO L460 AbstractCegarLoop]: Interpolant automaton has 83 states [2018-11-10 10:01:18,274 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 83 interpolants. [2018-11-10 10:01:18,274 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1346, Invalid=5460, Unknown=0, NotChecked=0, Total=6806 [2018-11-10 10:01:18,274 INFO L87 Difference]: Start difference. First operand 2257 states and 2260 transitions. Second operand 83 states. [2018-11-10 10:01:20,060 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 10:01:20,060 INFO L93 Difference]: Finished difference Result 2427 states and 2432 transitions. [2018-11-10 10:01:20,061 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 81 states. [2018-11-10 10:01:20,061 INFO L78 Accepts]: Start accepts. Automaton has 83 states. Word has length 2247 [2018-11-10 10:01:20,062 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 10:01:20,065 INFO L225 Difference]: With dead ends: 2427 [2018-11-10 10:01:20,065 INFO L226 Difference]: Without dead ends: 2427 [2018-11-10 10:01:20,067 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2375 GetRequests, 2221 SyntacticMatches, 0 SemanticMatches, 154 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7385 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=5804, Invalid=18376, Unknown=0, NotChecked=0, Total=24180 [2018-11-10 10:01:20,068 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2427 states. [2018-11-10 10:01:20,076 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2427 to 2420. [2018-11-10 10:01:20,076 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2420 states. [2018-11-10 10:01:20,078 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2420 states to 2420 states and 2425 transitions. [2018-11-10 10:01:20,078 INFO L78 Accepts]: Start accepts. Automaton has 2420 states and 2425 transitions. Word has length 2247 [2018-11-10 10:01:20,080 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 10:01:20,080 INFO L481 AbstractCegarLoop]: Abstraction has 2420 states and 2425 transitions. [2018-11-10 10:01:20,080 INFO L482 AbstractCegarLoop]: Interpolant automaton has 83 states. [2018-11-10 10:01:20,080 INFO L276 IsEmpty]: Start isEmpty. Operand 2420 states and 2425 transitions. [2018-11-10 10:01:20,098 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2254 [2018-11-10 10:01:20,098 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 10:01:20,099 INFO L375 BasicCegarLoop]: trace histogram [347, 324, 323, 323, 323, 323, 24, 24, 24, 24, 23, 23, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 10:01:20,099 INFO L424 AbstractCegarLoop]: === Iteration 67 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 10:01:20,099 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 10:01:20,099 INFO L82 PathProgramCache]: Analyzing trace with hash 705829582, now seen corresponding path program 52 times [2018-11-10 10:01:20,100 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 10:01:20,100 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 10:01:20,100 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:01:20,100 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 10:01:20,100 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:01:20,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 10:01:21,953 INFO L134 CoverageAnalysis]: Checked inductivity of 331272 backedges. 46062 proven. 1864 refuted. 0 times theorem prover too weak. 283346 trivial. 0 not checked. [2018-11-10 10:01:21,954 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 10:01:21,954 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 10:01:21,961 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-10 10:01:25,034 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-10 10:01:25,034 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 10:01:25,057 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 10:01:26,601 INFO L134 CoverageAnalysis]: Checked inductivity of 331272 backedges. 45103 proven. 1728 refuted. 0 times theorem prover too weak. 284441 trivial. 0 not checked. [2018-11-10 10:01:26,624 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 10:01:26,624 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 26] total 62 [2018-11-10 10:01:26,625 INFO L460 AbstractCegarLoop]: Interpolant automaton has 63 states [2018-11-10 10:01:26,625 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 63 interpolants. [2018-11-10 10:01:26,625 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=461, Invalid=3445, Unknown=0, NotChecked=0, Total=3906 [2018-11-10 10:01:26,625 INFO L87 Difference]: Start difference. First operand 2420 states and 2425 transitions. Second operand 63 states. [2018-11-10 10:01:29,096 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 10:01:29,096 INFO L93 Difference]: Finished difference Result 2770 states and 2781 transitions. [2018-11-10 10:01:29,096 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 81 states. [2018-11-10 10:01:29,096 INFO L78 Accepts]: Start accepts. Automaton has 63 states. Word has length 2253 [2018-11-10 10:01:29,097 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 10:01:29,099 INFO L225 Difference]: With dead ends: 2770 [2018-11-10 10:01:29,099 INFO L226 Difference]: Without dead ends: 2770 [2018-11-10 10:01:29,100 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2318 GetRequests, 2228 SyntacticMatches, 0 SemanticMatches, 90 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1671 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=884, Invalid=7488, Unknown=0, NotChecked=0, Total=8372 [2018-11-10 10:01:29,101 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2770 states. [2018-11-10 10:01:29,111 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2770 to 2743. [2018-11-10 10:01:29,111 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2743 states. [2018-11-10 10:01:29,113 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2743 states to 2743 states and 2753 transitions. [2018-11-10 10:01:29,113 INFO L78 Accepts]: Start accepts. Automaton has 2743 states and 2753 transitions. Word has length 2253 [2018-11-10 10:01:29,114 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 10:01:29,114 INFO L481 AbstractCegarLoop]: Abstraction has 2743 states and 2753 transitions. [2018-11-10 10:01:29,114 INFO L482 AbstractCegarLoop]: Interpolant automaton has 63 states. [2018-11-10 10:01:29,114 INFO L276 IsEmpty]: Start isEmpty. Operand 2743 states and 2753 transitions. [2018-11-10 10:01:29,134 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2411 [2018-11-10 10:01:29,134 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 10:01:29,134 INFO L375 BasicCegarLoop]: trace histogram [372, 348, 347, 347, 347, 347, 25, 25, 25, 25, 24, 24, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 10:01:29,134 INFO L424 AbstractCegarLoop]: === Iteration 68 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 10:01:29,135 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 10:01:29,135 INFO L82 PathProgramCache]: Analyzing trace with hash 453423321, now seen corresponding path program 53 times [2018-11-10 10:01:29,135 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 10:01:29,135 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 10:01:29,135 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:01:29,135 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 10:01:29,135 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:01:29,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 10:01:31,770 INFO L134 CoverageAnalysis]: Checked inductivity of 381615 backedges. 88727 proven. 8604 refuted. 0 times theorem prover too weak. 284284 trivial. 0 not checked. [2018-11-10 10:01:31,770 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 10:01:31,770 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 10:01:31,777 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-10 10:01:37,295 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 58 check-sat command(s) [2018-11-10 10:01:37,295 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 10:01:37,330 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 10:01:40,154 INFO L134 CoverageAnalysis]: Checked inductivity of 381615 backedges. 132738 proven. 9358 refuted. 0 times theorem prover too weak. 239519 trivial. 0 not checked. [2018-11-10 10:01:40,179 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 10:01:40,180 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 54] total 109 [2018-11-10 10:01:40,181 INFO L460 AbstractCegarLoop]: Interpolant automaton has 109 states [2018-11-10 10:01:40,182 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 109 interpolants. [2018-11-10 10:01:40,182 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1639, Invalid=10133, Unknown=0, NotChecked=0, Total=11772 [2018-11-10 10:01:40,182 INFO L87 Difference]: Start difference. First operand 2743 states and 2753 transitions. Second operand 109 states. [2018-11-10 10:01:44,398 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 10:01:44,398 INFO L93 Difference]: Finished difference Result 2439 states and 2442 transitions. [2018-11-10 10:01:44,398 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 131 states. [2018-11-10 10:01:44,398 INFO L78 Accepts]: Start accepts. Automaton has 109 states. Word has length 2410 [2018-11-10 10:01:44,399 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 10:01:44,401 INFO L225 Difference]: With dead ends: 2439 [2018-11-10 10:01:44,401 INFO L226 Difference]: Without dead ends: 2430 [2018-11-10 10:01:44,404 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2591 GetRequests, 2361 SyntacticMatches, 0 SemanticMatches, 230 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17950 ImplicationChecksByTransitivity, 3.8s TimeCoverageRelationStatistics Valid=7839, Invalid=45753, Unknown=0, NotChecked=0, Total=53592 [2018-11-10 10:01:44,405 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2430 states. [2018-11-10 10:01:44,417 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2430 to 2426. [2018-11-10 10:01:44,417 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2426 states. [2018-11-10 10:01:44,419 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2426 states to 2426 states and 2429 transitions. [2018-11-10 10:01:44,419 INFO L78 Accepts]: Start accepts. Automaton has 2426 states and 2429 transitions. Word has length 2410 [2018-11-10 10:01:44,420 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 10:01:44,420 INFO L481 AbstractCegarLoop]: Abstraction has 2426 states and 2429 transitions. [2018-11-10 10:01:44,420 INFO L482 AbstractCegarLoop]: Interpolant automaton has 109 states. [2018-11-10 10:01:44,420 INFO L276 IsEmpty]: Start isEmpty. Operand 2426 states and 2429 transitions. [2018-11-10 10:01:44,441 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2417 [2018-11-10 10:01:44,441 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 10:01:44,441 INFO L375 BasicCegarLoop]: trace histogram [373, 349, 348, 348, 348, 348, 25, 25, 25, 25, 24, 24, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 10:01:44,441 INFO L424 AbstractCegarLoop]: === Iteration 69 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 10:01:44,441 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 10:01:44,442 INFO L82 PathProgramCache]: Analyzing trace with hash -611136879, now seen corresponding path program 54 times [2018-11-10 10:01:44,442 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 10:01:44,442 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 10:01:44,442 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:01:44,442 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 10:01:44,442 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:01:44,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 10:01:47,091 INFO L134 CoverageAnalysis]: Checked inductivity of 383748 backedges. 93829 proven. 5478 refuted. 0 times theorem prover too weak. 284441 trivial. 0 not checked. [2018-11-10 10:01:47,091 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 10:01:47,091 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 10:01:47,098 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-10 10:01:51,642 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 51 check-sat command(s) [2018-11-10 10:01:51,642 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 10:01:51,665 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 10:01:53,829 INFO L134 CoverageAnalysis]: Checked inductivity of 383748 backedges. 92126 proven. 5453 refuted. 0 times theorem prover too weak. 286169 trivial. 0 not checked. [2018-11-10 10:01:53,851 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 10:01:53,851 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 34] total 86 [2018-11-10 10:01:53,852 INFO L460 AbstractCegarLoop]: Interpolant automaton has 86 states [2018-11-10 10:01:53,852 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 86 interpolants. [2018-11-10 10:01:53,853 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1451, Invalid=5859, Unknown=0, NotChecked=0, Total=7310 [2018-11-10 10:01:53,853 INFO L87 Difference]: Start difference. First operand 2426 states and 2429 transitions. Second operand 86 states. [2018-11-10 10:01:55,936 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 10:01:55,936 INFO L93 Difference]: Finished difference Result 2602 states and 2607 transitions. [2018-11-10 10:01:55,936 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 84 states. [2018-11-10 10:01:55,936 INFO L78 Accepts]: Start accepts. Automaton has 86 states. Word has length 2416 [2018-11-10 10:01:55,937 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 10:01:55,939 INFO L225 Difference]: With dead ends: 2602 [2018-11-10 10:01:55,939 INFO L226 Difference]: Without dead ends: 2602 [2018-11-10 10:01:55,940 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2549 GetRequests, 2389 SyntacticMatches, 0 SemanticMatches, 160 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7993 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=6269, Invalid=19813, Unknown=0, NotChecked=0, Total=26082 [2018-11-10 10:01:55,942 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2602 states. [2018-11-10 10:01:55,950 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2602 to 2595. [2018-11-10 10:01:55,950 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2595 states. [2018-11-10 10:01:55,952 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2595 states to 2595 states and 2600 transitions. [2018-11-10 10:01:55,952 INFO L78 Accepts]: Start accepts. Automaton has 2595 states and 2600 transitions. Word has length 2416 [2018-11-10 10:01:55,953 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 10:01:55,953 INFO L481 AbstractCegarLoop]: Abstraction has 2595 states and 2600 transitions. [2018-11-10 10:01:55,953 INFO L482 AbstractCegarLoop]: Interpolant automaton has 86 states. [2018-11-10 10:01:55,953 INFO L276 IsEmpty]: Start isEmpty. Operand 2595 states and 2600 transitions. [2018-11-10 10:01:55,974 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2423 [2018-11-10 10:01:55,974 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 10:01:55,974 INFO L375 BasicCegarLoop]: trace histogram [374, 350, 349, 349, 349, 349, 25, 25, 25, 25, 24, 24, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 10:01:55,974 INFO L424 AbstractCegarLoop]: === Iteration 70 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 10:01:55,975 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 10:01:55,975 INFO L82 PathProgramCache]: Analyzing trace with hash 243956633, now seen corresponding path program 55 times [2018-11-10 10:01:55,975 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 10:01:55,975 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 10:01:55,975 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:01:55,975 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 10:01:55,976 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:01:56,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 10:01:57,952 INFO L134 CoverageAnalysis]: Checked inductivity of 385887 backedges. 50966 proven. 2029 refuted. 0 times theorem prover too weak. 332892 trivial. 0 not checked. [2018-11-10 10:01:57,952 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 10:01:57,952 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 10:01:57,959 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 10:01:58,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 10:01:58,309 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 10:02:00,039 INFO L134 CoverageAnalysis]: Checked inductivity of 385887 backedges. 50820 proven. 1875 refuted. 0 times theorem prover too weak. 333192 trivial. 0 not checked. [2018-11-10 10:02:00,057 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 10:02:00,057 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 27] total 57 [2018-11-10 10:02:00,058 INFO L460 AbstractCegarLoop]: Interpolant automaton has 58 states [2018-11-10 10:02:00,058 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 58 interpolants. [2018-11-10 10:02:00,058 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=441, Invalid=2865, Unknown=0, NotChecked=0, Total=3306 [2018-11-10 10:02:00,058 INFO L87 Difference]: Start difference. First operand 2595 states and 2600 transitions. Second operand 58 states. [2018-11-10 10:02:02,738 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 10:02:02,738 INFO L93 Difference]: Finished difference Result 2957 states and 2968 transitions. [2018-11-10 10:02:02,738 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 84 states. [2018-11-10 10:02:02,738 INFO L78 Accepts]: Start accepts. Automaton has 58 states. Word has length 2422 [2018-11-10 10:02:02,740 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 10:02:02,743 INFO L225 Difference]: With dead ends: 2957 [2018-11-10 10:02:02,743 INFO L226 Difference]: Without dead ends: 2957 [2018-11-10 10:02:02,743 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2482 GetRequests, 2396 SyntacticMatches, 0 SemanticMatches, 86 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1282 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=727, Invalid=6929, Unknown=0, NotChecked=0, Total=7656 [2018-11-10 10:02:02,744 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2957 states. [2018-11-10 10:02:02,755 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2957 to 2930. [2018-11-10 10:02:02,755 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2930 states. [2018-11-10 10:02:02,758 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2930 states to 2930 states and 2940 transitions. [2018-11-10 10:02:02,758 INFO L78 Accepts]: Start accepts. Automaton has 2930 states and 2940 transitions. Word has length 2422 [2018-11-10 10:02:02,759 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 10:02:02,759 INFO L481 AbstractCegarLoop]: Abstraction has 2930 states and 2940 transitions. [2018-11-10 10:02:02,759 INFO L482 AbstractCegarLoop]: Interpolant automaton has 58 states. [2018-11-10 10:02:02,759 INFO L276 IsEmpty]: Start isEmpty. Operand 2930 states and 2940 transitions. [2018-11-10 10:02:02,785 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2586 [2018-11-10 10:02:02,785 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 10:02:02,785 INFO L375 BasicCegarLoop]: trace histogram [400, 375, 374, 374, 374, 374, 26, 26, 26, 26, 25, 25, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 10:02:02,786 INFO L424 AbstractCegarLoop]: === Iteration 71 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 10:02:02,786 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 10:02:02,786 INFO L82 PathProgramCache]: Analyzing trace with hash -275902490, now seen corresponding path program 56 times [2018-11-10 10:02:02,786 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 10:02:02,786 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 10:02:02,787 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:02:02,787 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 10:02:02,787 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:02:02,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 10:02:05,655 INFO L134 CoverageAnalysis]: Checked inductivity of 442378 backedges. 100013 proven. 9337 refuted. 0 times theorem prover too weak. 333028 trivial. 0 not checked. [2018-11-10 10:02:05,655 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 10:02:05,656 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 10:02:05,664 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-10 10:02:06,028 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-10 10:02:06,028 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 10:02:06,047 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 10:02:08,958 INFO L134 CoverageAnalysis]: Checked inductivity of 442378 backedges. 150158 proven. 1704 refuted. 0 times theorem prover too weak. 290516 trivial. 0 not checked. [2018-11-10 10:02:08,976 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 10:02:08,977 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 52] total 109 [2018-11-10 10:02:08,977 INFO L460 AbstractCegarLoop]: Interpolant automaton has 109 states [2018-11-10 10:02:08,977 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 109 interpolants. [2018-11-10 10:02:08,978 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1795, Invalid=9977, Unknown=0, NotChecked=0, Total=11772 [2018-11-10 10:02:08,978 INFO L87 Difference]: Start difference. First operand 2930 states and 2940 transitions. Second operand 109 states. [2018-11-10 10:02:12,383 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 10:02:12,383 INFO L93 Difference]: Finished difference Result 2614 states and 2617 transitions. [2018-11-10 10:02:12,384 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 131 states. [2018-11-10 10:02:12,384 INFO L78 Accepts]: Start accepts. Automaton has 109 states. Word has length 2585 [2018-11-10 10:02:12,385 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 10:02:12,387 INFO L225 Difference]: With dead ends: 2614 [2018-11-10 10:02:12,387 INFO L226 Difference]: Without dead ends: 2605 [2018-11-10 10:02:12,390 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2744 GetRequests, 2537 SyntacticMatches, 0 SemanticMatches, 207 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13934 ImplicationChecksByTransitivity, 3.2s TimeCoverageRelationStatistics Valid=6545, Invalid=36927, Unknown=0, NotChecked=0, Total=43472 [2018-11-10 10:02:12,391 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2605 states. [2018-11-10 10:02:12,399 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2605 to 2601. [2018-11-10 10:02:12,399 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2601 states. [2018-11-10 10:02:12,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2601 states to 2601 states and 2604 transitions. [2018-11-10 10:02:12,401 INFO L78 Accepts]: Start accepts. Automaton has 2601 states and 2604 transitions. Word has length 2585 [2018-11-10 10:02:12,402 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 10:02:12,402 INFO L481 AbstractCegarLoop]: Abstraction has 2601 states and 2604 transitions. [2018-11-10 10:02:12,402 INFO L482 AbstractCegarLoop]: Interpolant automaton has 109 states. [2018-11-10 10:02:12,403 INFO L276 IsEmpty]: Start isEmpty. Operand 2601 states and 2604 transitions. [2018-11-10 10:02:12,426 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2592 [2018-11-10 10:02:12,426 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 10:02:12,427 INFO L375 BasicCegarLoop]: trace histogram [401, 376, 375, 375, 375, 375, 26, 26, 26, 26, 25, 25, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 10:02:12,427 INFO L424 AbstractCegarLoop]: === Iteration 72 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 10:02:12,427 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 10:02:12,427 INFO L82 PathProgramCache]: Analyzing trace with hash 1810081758, now seen corresponding path program 57 times [2018-11-10 10:02:12,427 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 10:02:12,428 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 10:02:12,428 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:02:12,428 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 10:02:12,428 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:02:12,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 10:02:15,350 INFO L134 CoverageAnalysis]: Checked inductivity of 444675 backedges. 105552 proven. 5931 refuted. 0 times theorem prover too weak. 333192 trivial. 0 not checked. [2018-11-10 10:02:15,350 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 10:02:15,351 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 10:02:15,357 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-10 10:02:16,450 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 27 check-sat command(s) [2018-11-10 10:02:16,450 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 10:02:16,465 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 10:02:18,595 INFO L134 CoverageAnalysis]: Checked inductivity of 444675 backedges. 56841 proven. 2028 refuted. 0 times theorem prover too weak. 385806 trivial. 0 not checked. [2018-11-10 10:02:18,614 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 10:02:18,614 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 29] total 88 [2018-11-10 10:02:18,615 INFO L460 AbstractCegarLoop]: Interpolant automaton has 88 states [2018-11-10 10:02:18,615 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 88 interpolants. [2018-11-10 10:02:18,616 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1204, Invalid=6452, Unknown=0, NotChecked=0, Total=7656 [2018-11-10 10:02:18,616 INFO L87 Difference]: Start difference. First operand 2601 states and 2604 transitions. Second operand 88 states. [2018-11-10 10:02:21,180 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 10:02:21,180 INFO L93 Difference]: Finished difference Result 2792 states and 2798 transitions. [2018-11-10 10:02:21,180 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 89 states. [2018-11-10 10:02:21,180 INFO L78 Accepts]: Start accepts. Automaton has 88 states. Word has length 2591 [2018-11-10 10:02:21,182 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 10:02:21,184 INFO L225 Difference]: With dead ends: 2792 [2018-11-10 10:02:21,184 INFO L226 Difference]: Without dead ends: 2792 [2018-11-10 10:02:21,186 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2730 GetRequests, 2564 SyntacticMatches, 0 SemanticMatches, 166 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6851 ImplicationChecksByTransitivity, 3.1s TimeCoverageRelationStatistics Valid=6425, Invalid=21631, Unknown=0, NotChecked=0, Total=28056 [2018-11-10 10:02:21,187 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2792 states. [2018-11-10 10:02:21,195 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2792 to 2782. [2018-11-10 10:02:21,195 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2782 states. [2018-11-10 10:02:21,197 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2782 states to 2782 states and 2788 transitions. [2018-11-10 10:02:21,197 INFO L78 Accepts]: Start accepts. Automaton has 2782 states and 2788 transitions. Word has length 2591 [2018-11-10 10:02:21,199 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 10:02:21,199 INFO L481 AbstractCegarLoop]: Abstraction has 2782 states and 2788 transitions. [2018-11-10 10:02:21,199 INFO L482 AbstractCegarLoop]: Interpolant automaton has 88 states. [2018-11-10 10:02:21,199 INFO L276 IsEmpty]: Start isEmpty. Operand 2782 states and 2788 transitions. [2018-11-10 10:02:21,222 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2604 [2018-11-10 10:02:21,222 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 10:02:21,223 INFO L375 BasicCegarLoop]: trace histogram [403, 378, 377, 377, 377, 377, 26, 26, 26, 26, 25, 25, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 10:02:21,223 INFO L424 AbstractCegarLoop]: === Iteration 73 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 10:02:21,223 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 10:02:21,223 INFO L82 PathProgramCache]: Analyzing trace with hash -1213884130, now seen corresponding path program 58 times [2018-11-10 10:02:21,224 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 10:02:21,224 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 10:02:21,224 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:02:21,224 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 10:02:21,224 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:02:21,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 10:02:23,943 INFO L134 CoverageAnalysis]: Checked inductivity of 449287 backedges. 61282 proven. 2255 refuted. 0 times theorem prover too weak. 385750 trivial. 0 not checked. [2018-11-10 10:02:23,943 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 10:02:23,943 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 10:02:23,951 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-10 10:02:24,268 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-10 10:02:24,269 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 10:02:24,286 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 10:02:26,905 INFO L134 CoverageAnalysis]: Checked inductivity of 449287 backedges. 61362 proven. 2175 refuted. 0 times theorem prover too weak. 385750 trivial. 0 not checked. [2018-11-10 10:02:26,923 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 10:02:26,923 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 57] total 87 [2018-11-10 10:02:26,924 INFO L460 AbstractCegarLoop]: Interpolant automaton has 87 states [2018-11-10 10:02:26,924 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 87 interpolants. [2018-11-10 10:02:26,924 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1712, Invalid=5770, Unknown=0, NotChecked=0, Total=7482 [2018-11-10 10:02:26,924 INFO L87 Difference]: Start difference. First operand 2782 states and 2788 transitions. Second operand 87 states. [2018-11-10 10:02:28,572 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 10:02:28,572 INFO L93 Difference]: Finished difference Result 3140 states and 3150 transitions. [2018-11-10 10:02:28,573 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 83 states. [2018-11-10 10:02:28,573 INFO L78 Accepts]: Start accepts. Automaton has 87 states. Word has length 2603 [2018-11-10 10:02:28,574 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 10:02:28,577 INFO L225 Difference]: With dead ends: 3140 [2018-11-10 10:02:28,577 INFO L226 Difference]: Without dead ends: 3140 [2018-11-10 10:02:28,578 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2713 GetRequests, 2575 SyntacticMatches, 0 SemanticMatches, 138 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3314 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=4889, Invalid=14571, Unknown=0, NotChecked=0, Total=19460 [2018-11-10 10:02:28,580 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3140 states. [2018-11-10 10:02:28,591 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3140 to 3129. [2018-11-10 10:02:28,591 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3129 states. [2018-11-10 10:02:28,594 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3129 states to 3129 states and 3139 transitions. [2018-11-10 10:02:28,594 INFO L78 Accepts]: Start accepts. Automaton has 3129 states and 3139 transitions. Word has length 2603 [2018-11-10 10:02:28,595 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 10:02:28,595 INFO L481 AbstractCegarLoop]: Abstraction has 3129 states and 3139 transitions. [2018-11-10 10:02:28,595 INFO L482 AbstractCegarLoop]: Interpolant automaton has 87 states. [2018-11-10 10:02:28,595 INFO L276 IsEmpty]: Start isEmpty. Operand 3129 states and 3139 transitions. [2018-11-10 10:02:28,622 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2767 [2018-11-10 10:02:28,622 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 10:02:28,622 INFO L375 BasicCegarLoop]: trace histogram [429, 403, 402, 402, 402, 402, 27, 27, 27, 27, 26, 26, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 10:02:28,623 INFO L424 AbstractCegarLoop]: === Iteration 74 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 10:02:28,623 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 10:02:28,623 INFO L82 PathProgramCache]: Analyzing trace with hash 629042417, now seen corresponding path program 59 times [2018-11-10 10:02:28,623 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 10:02:28,623 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 10:02:28,624 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:02:28,624 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 10:02:28,624 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:02:28,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 10:02:31,841 INFO L134 CoverageAnalysis]: Checked inductivity of 510097 backedges. 112218 proven. 10100 refuted. 0 times theorem prover too weak. 387779 trivial. 0 not checked. [2018-11-10 10:02:31,842 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 10:02:31,842 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 10:02:31,849 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-10 10:02:50,919 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 60 check-sat command(s) [2018-11-10 10:02:50,919 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 10:02:50,965 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 10:02:54,394 INFO L134 CoverageAnalysis]: Checked inductivity of 510097 backedges. 168020 proven. 10996 refuted. 0 times theorem prover too weak. 331081 trivial. 0 not checked. [2018-11-10 10:02:54,423 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 10:02:54,424 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 58] total 117 [2018-11-10 10:02:54,425 INFO L460 AbstractCegarLoop]: Interpolant automaton has 117 states [2018-11-10 10:02:54,426 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 117 interpolants. [2018-11-10 10:02:54,426 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1902, Invalid=11670, Unknown=0, NotChecked=0, Total=13572 [2018-11-10 10:02:54,426 INFO L87 Difference]: Start difference. First operand 3129 states and 3139 transitions. Second operand 117 states. [2018-11-10 10:02:58,507 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 10:02:58,508 INFO L93 Difference]: Finished difference Result 2795 states and 2798 transitions. [2018-11-10 10:02:58,508 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 141 states. [2018-11-10 10:02:58,508 INFO L78 Accepts]: Start accepts. Automaton has 117 states. Word has length 2766 [2018-11-10 10:02:58,509 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 10:02:58,512 INFO L225 Difference]: With dead ends: 2795 [2018-11-10 10:02:58,512 INFO L226 Difference]: Without dead ends: 2786 [2018-11-10 10:02:58,515 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2961 GetRequests, 2713 SyntacticMatches, 0 SemanticMatches, 248 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20985 ImplicationChecksByTransitivity, 4.3s TimeCoverageRelationStatistics Valid=9105, Invalid=53145, Unknown=0, NotChecked=0, Total=62250 [2018-11-10 10:02:58,516 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2786 states. [2018-11-10 10:02:58,525 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2786 to 2782. [2018-11-10 10:02:58,525 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2782 states. [2018-11-10 10:02:58,527 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2782 states to 2782 states and 2785 transitions. [2018-11-10 10:02:58,527 INFO L78 Accepts]: Start accepts. Automaton has 2782 states and 2785 transitions. Word has length 2766 [2018-11-10 10:02:58,529 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 10:02:58,529 INFO L481 AbstractCegarLoop]: Abstraction has 2782 states and 2785 transitions. [2018-11-10 10:02:58,529 INFO L482 AbstractCegarLoop]: Interpolant automaton has 117 states. [2018-11-10 10:02:58,529 INFO L276 IsEmpty]: Start isEmpty. Operand 2782 states and 2785 transitions. [2018-11-10 10:02:58,555 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2773 [2018-11-10 10:02:58,556 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 10:02:58,556 INFO L375 BasicCegarLoop]: trace histogram [430, 404, 403, 403, 403, 403, 27, 27, 27, 27, 26, 26, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 10:02:58,556 INFO L424 AbstractCegarLoop]: === Iteration 75 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 10:02:58,556 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 10:02:58,557 INFO L82 PathProgramCache]: Analyzing trace with hash 1843629225, now seen corresponding path program 60 times [2018-11-10 10:02:58,557 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 10:02:58,557 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 10:02:58,557 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:02:58,557 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 10:02:58,558 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:02:58,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 10:03:01,842 INFO L134 CoverageAnalysis]: Checked inductivity of 512564 backedges. 118212 proven. 6402 refuted. 0 times theorem prover too weak. 387950 trivial. 0 not checked. [2018-11-10 10:03:01,843 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 10:03:01,843 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 10:03:01,848 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-10 10:03:12,244 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 55 check-sat command(s) [2018-11-10 10:03:12,244 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 10:03:12,272 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 10:03:14,881 INFO L134 CoverageAnalysis]: Checked inductivity of 512564 backedges. 116211 proven. 6375 refuted. 0 times theorem prover too weak. 389978 trivial. 0 not checked. [2018-11-10 10:03:14,904 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 10:03:14,904 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 36] total 92 [2018-11-10 10:03:14,905 INFO L460 AbstractCegarLoop]: Interpolant automaton has 92 states [2018-11-10 10:03:14,905 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 92 interpolants. [2018-11-10 10:03:14,905 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1673, Invalid=6699, Unknown=0, NotChecked=0, Total=8372 [2018-11-10 10:03:14,905 INFO L87 Difference]: Start difference. First operand 2782 states and 2785 transitions. Second operand 92 states. [2018-11-10 10:03:16,992 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 10:03:16,993 INFO L93 Difference]: Finished difference Result 2970 states and 2975 transitions. [2018-11-10 10:03:16,993 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 90 states. [2018-11-10 10:03:16,993 INFO L78 Accepts]: Start accepts. Automaton has 92 states. Word has length 2772 [2018-11-10 10:03:16,994 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 10:03:16,997 INFO L225 Difference]: With dead ends: 2970 [2018-11-10 10:03:16,997 INFO L226 Difference]: Without dead ends: 2970 [2018-11-10 10:03:16,999 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2915 GetRequests, 2743 SyntacticMatches, 0 SemanticMatches, 172 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9281 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=7253, Invalid=22849, Unknown=0, NotChecked=0, Total=30102 [2018-11-10 10:03:17,000 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2970 states. [2018-11-10 10:03:17,010 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2970 to 2963. [2018-11-10 10:03:17,010 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2963 states. [2018-11-10 10:03:17,012 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2963 states to 2963 states and 2968 transitions. [2018-11-10 10:03:17,012 INFO L78 Accepts]: Start accepts. Automaton has 2963 states and 2968 transitions. Word has length 2772 [2018-11-10 10:03:17,014 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 10:03:17,014 INFO L481 AbstractCegarLoop]: Abstraction has 2963 states and 2968 transitions. [2018-11-10 10:03:17,014 INFO L482 AbstractCegarLoop]: Interpolant automaton has 92 states. [2018-11-10 10:03:17,014 INFO L276 IsEmpty]: Start isEmpty. Operand 2963 states and 2968 transitions. [2018-11-10 10:03:17,040 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2779 [2018-11-10 10:03:17,040 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 10:03:17,041 INFO L375 BasicCegarLoop]: trace histogram [431, 405, 404, 404, 404, 404, 27, 27, 27, 27, 26, 26, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 10:03:17,041 INFO L424 AbstractCegarLoop]: === Iteration 76 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 10:03:17,041 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 10:03:17,041 INFO L82 PathProgramCache]: Analyzing trace with hash -75705423, now seen corresponding path program 61 times [2018-11-10 10:03:17,042 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 10:03:17,042 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 10:03:17,042 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:03:17,042 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 10:03:17,042 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:03:17,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 10:03:19,532 INFO L134 CoverageAnalysis]: Checked inductivity of 515037 backedges. 63819 proven. 2380 refuted. 0 times theorem prover too weak. 448838 trivial. 0 not checked. [2018-11-10 10:03:19,532 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 10:03:19,532 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 10:03:19,540 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 10:03:19,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 10:03:19,930 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 10:03:22,097 INFO L134 CoverageAnalysis]: Checked inductivity of 515037 backedges. 63661 proven. 2187 refuted. 0 times theorem prover too weak. 449189 trivial. 0 not checked. [2018-11-10 10:03:22,116 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 10:03:22,117 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 29] total 61 [2018-11-10 10:03:22,117 INFO L460 AbstractCegarLoop]: Interpolant automaton has 62 states [2018-11-10 10:03:22,118 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2018-11-10 10:03:22,118 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=502, Invalid=3280, Unknown=0, NotChecked=0, Total=3782 [2018-11-10 10:03:22,118 INFO L87 Difference]: Start difference. First operand 2963 states and 2968 transitions. Second operand 62 states. [2018-11-10 10:03:24,673 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 10:03:24,673 INFO L93 Difference]: Finished difference Result 3349 states and 3360 transitions. [2018-11-10 10:03:24,674 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 90 states. [2018-11-10 10:03:24,674 INFO L78 Accepts]: Start accepts. Automaton has 62 states. Word has length 2778 [2018-11-10 10:03:24,675 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 10:03:24,679 INFO L225 Difference]: With dead ends: 3349 [2018-11-10 10:03:24,679 INFO L226 Difference]: Without dead ends: 3349 [2018-11-10 10:03:24,680 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 2842 GetRequests, 2750 SyntacticMatches, 0 SemanticMatches, 92 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1465 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=808, Invalid=7934, Unknown=0, NotChecked=0, Total=8742 [2018-11-10 10:03:24,681 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3349 states. [2018-11-10 10:03:24,701 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3349 to 3322. [2018-11-10 10:03:24,701 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3322 states. [2018-11-10 10:03:24,704 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3322 states to 3322 states and 3332 transitions. [2018-11-10 10:03:24,704 INFO L78 Accepts]: Start accepts. Automaton has 3322 states and 3332 transitions. Word has length 2778 [2018-11-10 10:03:24,706 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 10:03:24,706 INFO L481 AbstractCegarLoop]: Abstraction has 3322 states and 3332 transitions. [2018-11-10 10:03:24,706 INFO L482 AbstractCegarLoop]: Interpolant automaton has 62 states. [2018-11-10 10:03:24,706 INFO L276 IsEmpty]: Start isEmpty. Operand 3322 states and 3332 transitions. [2018-11-10 10:03:24,745 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2954 [2018-11-10 10:03:24,746 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 10:03:24,746 INFO L375 BasicCegarLoop]: trace histogram [459, 432, 431, 431, 431, 431, 28, 28, 28, 28, 27, 27, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 10:03:24,746 INFO L424 AbstractCegarLoop]: === Iteration 77 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 10:03:24,746 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 10:03:24,747 INFO L82 PathProgramCache]: Analyzing trace with hash 618350270, now seen corresponding path program 62 times [2018-11-10 10:03:24,747 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 10:03:24,747 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 10:03:24,747 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:03:24,747 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 10:03:24,747 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:03:24,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 10:03:28,364 INFO L134 CoverageAnalysis]: Checked inductivity of 585282 backedges. 125378 proven. 10893 refuted. 0 times theorem prover too weak. 449011 trivial. 0 not checked. [2018-11-10 10:03:28,364 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 10:03:28,364 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 10:03:28,371 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-10 10:03:28,784 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-10 10:03:28,784 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 10:03:28,806 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 10:03:32,437 INFO L134 CoverageAnalysis]: Checked inductivity of 585282 backedges. 188310 proven. 2002 refuted. 0 times theorem prover too weak. 394970 trivial. 0 not checked. [2018-11-10 10:03:32,456 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 10:03:32,456 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 56] total 117 [2018-11-10 10:03:32,457 INFO L460 AbstractCegarLoop]: Interpolant automaton has 117 states [2018-11-10 10:03:32,457 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 117 interpolants. [2018-11-10 10:03:32,457 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2072, Invalid=11500, Unknown=0, NotChecked=0, Total=13572 [2018-11-10 10:03:32,457 INFO L87 Difference]: Start difference. First operand 3322 states and 3332 transitions. Second operand 117 states. [2018-11-10 10:03:36,290 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 10:03:36,290 INFO L93 Difference]: Finished difference Result 2982 states and 2985 transitions. [2018-11-10 10:03:36,290 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 141 states. [2018-11-10 10:03:36,290 INFO L78 Accepts]: Start accepts. Automaton has 117 states. Word has length 2953 [2018-11-10 10:03:36,291 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 10:03:36,293 INFO L225 Difference]: With dead ends: 2982 [2018-11-10 10:03:36,293 INFO L226 Difference]: Without dead ends: 2973 [2018-11-10 10:03:36,295 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3124 GetRequests, 2901 SyntacticMatches, 0 SemanticMatches, 223 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16238 ImplicationChecksByTransitivity, 3.6s TimeCoverageRelationStatistics Valid=7578, Invalid=42822, Unknown=0, NotChecked=0, Total=50400 [2018-11-10 10:03:36,296 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2973 states. [2018-11-10 10:03:36,305 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2973 to 2969. [2018-11-10 10:03:36,305 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2969 states. [2018-11-10 10:03:36,307 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2969 states to 2969 states and 2972 transitions. [2018-11-10 10:03:36,307 INFO L78 Accepts]: Start accepts. Automaton has 2969 states and 2972 transitions. Word has length 2953 [2018-11-10 10:03:36,308 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 10:03:36,308 INFO L481 AbstractCegarLoop]: Abstraction has 2969 states and 2972 transitions. [2018-11-10 10:03:36,308 INFO L482 AbstractCegarLoop]: Interpolant automaton has 117 states. [2018-11-10 10:03:36,308 INFO L276 IsEmpty]: Start isEmpty. Operand 2969 states and 2972 transitions. [2018-11-10 10:03:36,336 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2960 [2018-11-10 10:03:36,337 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 10:03:36,337 INFO L375 BasicCegarLoop]: trace histogram [460, 433, 432, 432, 432, 432, 28, 28, 28, 28, 27, 27, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 10:03:36,337 INFO L424 AbstractCegarLoop]: === Iteration 78 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 10:03:36,337 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 10:03:36,337 INFO L82 PathProgramCache]: Analyzing trace with hash 419746998, now seen corresponding path program 63 times [2018-11-10 10:03:36,337 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 10:03:36,337 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 10:03:36,338 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:03:36,338 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 10:03:36,338 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:03:36,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 10:03:39,970 INFO L134 CoverageAnalysis]: Checked inductivity of 587925 backedges. 131845 proven. 6891 refuted. 0 times theorem prover too weak. 449189 trivial. 0 not checked. [2018-11-10 10:03:39,970 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 10:03:39,970 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 10:03:39,978 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-10 10:03:42,341 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 29 check-sat command(s) [2018-11-10 10:03:42,341 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 10:03:42,358 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 10:03:45,039 INFO L134 CoverageAnalysis]: Checked inductivity of 587925 backedges. 70650 proven. 2352 refuted. 0 times theorem prover too weak. 514923 trivial. 0 not checked. [2018-11-10 10:03:45,058 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 10:03:45,059 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 31] total 94 [2018-11-10 10:03:45,059 INFO L460 AbstractCegarLoop]: Interpolant automaton has 94 states [2018-11-10 10:03:45,059 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 94 interpolants. [2018-11-10 10:03:45,060 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1379, Invalid=7363, Unknown=0, NotChecked=0, Total=8742 [2018-11-10 10:03:45,060 INFO L87 Difference]: Start difference. First operand 2969 states and 2972 transitions. Second operand 94 states. [2018-11-10 10:03:47,934 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 10:03:47,934 INFO L93 Difference]: Finished difference Result 3172 states and 3178 transitions. [2018-11-10 10:03:47,935 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 95 states. [2018-11-10 10:03:47,935 INFO L78 Accepts]: Start accepts. Automaton has 94 states. Word has length 2959 [2018-11-10 10:03:47,936 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 10:03:47,939 INFO L225 Difference]: With dead ends: 3172 [2018-11-10 10:03:47,940 INFO L226 Difference]: Without dead ends: 3172 [2018-11-10 10:03:47,942 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3108 GetRequests, 2930 SyntacticMatches, 0 SemanticMatches, 178 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7910 ImplicationChecksByTransitivity, 3.5s TimeCoverageRelationStatistics Valid=7392, Invalid=24828, Unknown=0, NotChecked=0, Total=32220 [2018-11-10 10:03:47,943 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3172 states. [2018-11-10 10:03:47,954 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3172 to 3162. [2018-11-10 10:03:47,954 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3162 states. [2018-11-10 10:03:47,957 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3162 states to 3162 states and 3168 transitions. [2018-11-10 10:03:47,957 INFO L78 Accepts]: Start accepts. Automaton has 3162 states and 3168 transitions. Word has length 2959 [2018-11-10 10:03:47,958 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 10:03:47,958 INFO L481 AbstractCegarLoop]: Abstraction has 3162 states and 3168 transitions. [2018-11-10 10:03:47,958 INFO L482 AbstractCegarLoop]: Interpolant automaton has 94 states. [2018-11-10 10:03:47,959 INFO L276 IsEmpty]: Start isEmpty. Operand 3162 states and 3168 transitions. [2018-11-10 10:03:47,989 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2972 [2018-11-10 10:03:47,989 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 10:03:47,990 INFO L375 BasicCegarLoop]: trace histogram [462, 435, 434, 434, 434, 434, 28, 28, 28, 28, 27, 27, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 10:03:47,990 INFO L424 AbstractCegarLoop]: === Iteration 79 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 10:03:47,990 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 10:03:47,991 INFO L82 PathProgramCache]: Analyzing trace with hash -217331210, now seen corresponding path program 64 times [2018-11-10 10:03:47,991 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 10:03:47,991 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 10:03:47,991 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:03:47,991 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 10:03:47,991 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:03:48,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 10:03:51,454 INFO L134 CoverageAnalysis]: Checked inductivity of 593229 backedges. 75769 proven. 2624 refuted. 0 times theorem prover too weak. 514836 trivial. 0 not checked. [2018-11-10 10:03:51,454 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 10:03:51,454 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 10:03:51,460 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-10 10:03:51,808 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-10 10:03:51,808 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 10:03:51,827 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 10:03:55,052 INFO L134 CoverageAnalysis]: Checked inductivity of 593229 backedges. 75855 proven. 2538 refuted. 0 times theorem prover too weak. 514836 trivial. 0 not checked. [2018-11-10 10:03:55,070 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 10:03:55,070 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 61] total 93 [2018-11-10 10:03:55,071 INFO L460 AbstractCegarLoop]: Interpolant automaton has 93 states [2018-11-10 10:03:55,071 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 93 interpolants. [2018-11-10 10:03:55,072 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1954, Invalid=6602, Unknown=0, NotChecked=0, Total=8556 [2018-11-10 10:03:55,072 INFO L87 Difference]: Start difference. First operand 3162 states and 3168 transitions. Second operand 93 states. [2018-11-10 10:03:56,561 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 10:03:56,561 INFO L93 Difference]: Finished difference Result 3544 states and 3554 transitions. [2018-11-10 10:03:56,561 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 89 states. [2018-11-10 10:03:56,561 INFO L78 Accepts]: Start accepts. Automaton has 93 states. Word has length 2971 [2018-11-10 10:03:56,562 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 10:03:56,565 INFO L225 Difference]: With dead ends: 3544 [2018-11-10 10:03:56,565 INFO L226 Difference]: Without dead ends: 3544 [2018-11-10 10:03:56,566 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3089 GetRequests, 2941 SyntacticMatches, 0 SemanticMatches, 148 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3821 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=5599, Invalid=16751, Unknown=0, NotChecked=0, Total=22350 [2018-11-10 10:03:56,567 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3544 states. [2018-11-10 10:03:56,580 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3544 to 3533. [2018-11-10 10:03:56,580 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3533 states. [2018-11-10 10:03:56,582 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3533 states to 3533 states and 3543 transitions. [2018-11-10 10:03:56,583 INFO L78 Accepts]: Start accepts. Automaton has 3533 states and 3543 transitions. Word has length 2971 [2018-11-10 10:03:56,583 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 10:03:56,584 INFO L481 AbstractCegarLoop]: Abstraction has 3533 states and 3543 transitions. [2018-11-10 10:03:56,584 INFO L482 AbstractCegarLoop]: Interpolant automaton has 93 states. [2018-11-10 10:03:56,584 INFO L276 IsEmpty]: Start isEmpty. Operand 3533 states and 3543 transitions. [2018-11-10 10:03:56,616 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3147 [2018-11-10 10:03:56,617 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 10:03:56,617 INFO L375 BasicCegarLoop]: trace histogram [490, 462, 461, 461, 461, 461, 29, 29, 29, 29, 28, 28, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 10:03:56,617 INFO L424 AbstractCegarLoop]: === Iteration 80 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 10:03:56,617 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 10:03:56,617 INFO L82 PathProgramCache]: Analyzing trace with hash 532937353, now seen corresponding path program 65 times [2018-11-10 10:03:56,617 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 10:03:56,617 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 10:03:56,618 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:03:56,618 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 10:03:56,618 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:03:56,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 10:04:00,652 INFO L134 CoverageAnalysis]: Checked inductivity of 668461 backedges. 139529 proven. 11716 refuted. 0 times theorem prover too weak. 517216 trivial. 0 not checked. [2018-11-10 10:04:00,652 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 10:04:00,652 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 73 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 73 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 10:04:00,659 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-10 10:05:11,661 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 62 check-sat command(s) [2018-11-10 10:05:11,661 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 10:05:11,729 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 10:05:15,930 INFO L134 CoverageAnalysis]: Checked inductivity of 668461 backedges. 209046 proven. 12762 refuted. 0 times theorem prover too weak. 446653 trivial. 0 not checked. [2018-11-10 10:05:15,966 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 10:05:15,967 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [66, 62] total 125 [2018-11-10 10:05:15,968 INFO L460 AbstractCegarLoop]: Interpolant automaton has 125 states [2018-11-10 10:05:15,968 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 125 interpolants. [2018-11-10 10:05:15,968 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2185, Invalid=13315, Unknown=0, NotChecked=0, Total=15500 [2018-11-10 10:05:15,969 INFO L87 Difference]: Start difference. First operand 3533 states and 3543 transitions. Second operand 125 states. [2018-11-10 10:05:20,776 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 10:05:20,776 INFO L93 Difference]: Finished difference Result 3175 states and 3178 transitions. [2018-11-10 10:05:20,777 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 151 states. [2018-11-10 10:05:20,777 INFO L78 Accepts]: Start accepts. Automaton has 125 states. Word has length 3146 [2018-11-10 10:05:20,778 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 10:05:20,781 INFO L225 Difference]: With dead ends: 3175 [2018-11-10 10:05:20,781 INFO L226 Difference]: Without dead ends: 3166 [2018-11-10 10:05:20,785 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3355 GetRequests, 3089 SyntacticMatches, 0 SemanticMatches, 266 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24256 ImplicationChecksByTransitivity, 4.9s TimeCoverageRelationStatistics Valid=10467, Invalid=61089, Unknown=0, NotChecked=0, Total=71556 [2018-11-10 10:05:20,786 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3166 states. [2018-11-10 10:05:20,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3166 to 3162. [2018-11-10 10:05:20,796 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3162 states. [2018-11-10 10:05:20,799 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3162 states to 3162 states and 3165 transitions. [2018-11-10 10:05:20,799 INFO L78 Accepts]: Start accepts. Automaton has 3162 states and 3165 transitions. Word has length 3146 [2018-11-10 10:05:20,801 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 10:05:20,801 INFO L481 AbstractCegarLoop]: Abstraction has 3162 states and 3165 transitions. [2018-11-10 10:05:20,801 INFO L482 AbstractCegarLoop]: Interpolant automaton has 125 states. [2018-11-10 10:05:20,801 INFO L276 IsEmpty]: Start isEmpty. Operand 3162 states and 3165 transitions. [2018-11-10 10:05:20,837 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3153 [2018-11-10 10:05:20,837 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 10:05:20,837 INFO L375 BasicCegarLoop]: trace histogram [491, 463, 462, 462, 462, 462, 29, 29, 29, 29, 28, 28, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 10:05:20,838 INFO L424 AbstractCegarLoop]: === Iteration 81 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 10:05:20,838 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 10:05:20,838 INFO L82 PathProgramCache]: Analyzing trace with hash -236781503, now seen corresponding path program 66 times [2018-11-10 10:05:20,838 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 10:05:20,838 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 10:05:20,839 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:05:20,839 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 10:05:20,839 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:05:21,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 10:05:24,917 INFO L134 CoverageAnalysis]: Checked inductivity of 671286 backedges. 146487 proven. 7398 refuted. 0 times theorem prover too weak. 517401 trivial. 0 not checked. [2018-11-10 10:05:24,917 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 10:05:24,917 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 10:05:24,924 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-10 10:05:49,167 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 59 check-sat command(s) [2018-11-10 10:05:49,167 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 10:05:49,203 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 10:05:52,480 INFO L134 CoverageAnalysis]: Checked inductivity of 671286 backedges. 144164 proven. 7369 refuted. 0 times theorem prover too weak. 519753 trivial. 0 not checked. [2018-11-10 10:05:52,507 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 10:05:52,508 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [66, 38] total 98 [2018-11-10 10:05:52,509 INFO L460 AbstractCegarLoop]: Interpolant automaton has 98 states [2018-11-10 10:05:52,509 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 98 interpolants. [2018-11-10 10:05:52,509 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1911, Invalid=7595, Unknown=0, NotChecked=0, Total=9506 [2018-11-10 10:05:52,510 INFO L87 Difference]: Start difference. First operand 3162 states and 3165 transitions. Second operand 98 states. [2018-11-10 10:05:54,906 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 10:05:54,906 INFO L93 Difference]: Finished difference Result 3362 states and 3367 transitions. [2018-11-10 10:05:54,906 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2018-11-10 10:05:54,906 INFO L78 Accepts]: Start accepts. Automaton has 98 states. Word has length 3152 [2018-11-10 10:05:54,908 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 10:05:54,910 INFO L225 Difference]: With dead ends: 3362 [2018-11-10 10:05:54,910 INFO L226 Difference]: Without dead ends: 3362 [2018-11-10 10:05:54,912 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3305 GetRequests, 3121 SyntacticMatches, 0 SemanticMatches, 184 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10665 ImplicationChecksByTransitivity, 2.9s TimeCoverageRelationStatistics Valid=8309, Invalid=26101, Unknown=0, NotChecked=0, Total=34410 [2018-11-10 10:05:54,913 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3362 states. [2018-11-10 10:05:54,924 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3362 to 3355. [2018-11-10 10:05:54,924 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3355 states. [2018-11-10 10:05:54,927 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3355 states to 3355 states and 3360 transitions. [2018-11-10 10:05:54,927 INFO L78 Accepts]: Start accepts. Automaton has 3355 states and 3360 transitions. Word has length 3152 [2018-11-10 10:05:54,928 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 10:05:54,928 INFO L481 AbstractCegarLoop]: Abstraction has 3355 states and 3360 transitions. [2018-11-10 10:05:54,929 INFO L482 AbstractCegarLoop]: Interpolant automaton has 98 states. [2018-11-10 10:05:54,929 INFO L276 IsEmpty]: Start isEmpty. Operand 3355 states and 3360 transitions. [2018-11-10 10:05:54,962 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3159 [2018-11-10 10:05:54,962 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 10:05:54,963 INFO L375 BasicCegarLoop]: trace histogram [492, 464, 463, 463, 463, 463, 29, 29, 29, 29, 28, 28, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 10:05:54,963 INFO L424 AbstractCegarLoop]: === Iteration 82 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 10:05:54,963 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 10:05:54,964 INFO L82 PathProgramCache]: Analyzing trace with hash -1918452407, now seen corresponding path program 67 times [2018-11-10 10:05:54,964 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 10:05:54,964 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 10:05:54,964 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:05:54,964 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 10:05:54,964 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:05:55,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 10:05:58,138 INFO L134 CoverageAnalysis]: Checked inductivity of 674117 backedges. 78668 proven. 2759 refuted. 0 times theorem prover too weak. 592690 trivial. 0 not checked. [2018-11-10 10:05:58,138 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 10:05:58,138 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 75 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 75 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 10:05:58,144 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 10:05:58,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 10:05:58,620 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 10:06:01,380 INFO L134 CoverageAnalysis]: Checked inductivity of 674117 backedges. 78498 proven. 2523 refuted. 0 times theorem prover too weak. 593096 trivial. 0 not checked. [2018-11-10 10:06:01,399 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 10:06:01,400 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 31] total 65 [2018-11-10 10:06:01,401 INFO L460 AbstractCegarLoop]: Interpolant automaton has 66 states [2018-11-10 10:06:01,401 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 66 interpolants. [2018-11-10 10:06:01,401 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=567, Invalid=3723, Unknown=0, NotChecked=0, Total=4290 [2018-11-10 10:06:01,401 INFO L87 Difference]: Start difference. First operand 3355 states and 3360 transitions. Second operand 66 states. [2018-11-10 10:06:04,189 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 10:06:04,189 INFO L93 Difference]: Finished difference Result 3765 states and 3776 transitions. [2018-11-10 10:06:04,189 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2018-11-10 10:06:04,189 INFO L78 Accepts]: Start accepts. Automaton has 66 states. Word has length 3158 [2018-11-10 10:06:04,190 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 10:06:04,193 INFO L225 Difference]: With dead ends: 3765 [2018-11-10 10:06:04,193 INFO L226 Difference]: Without dead ends: 3765 [2018-11-10 10:06:04,194 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3226 GetRequests, 3128 SyntacticMatches, 0 SemanticMatches, 98 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1660 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=893, Invalid=9007, Unknown=0, NotChecked=0, Total=9900 [2018-11-10 10:06:04,195 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3765 states. [2018-11-10 10:06:04,211 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3765 to 3738. [2018-11-10 10:06:04,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3738 states. [2018-11-10 10:06:04,213 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3738 states to 3738 states and 3748 transitions. [2018-11-10 10:06:04,213 INFO L78 Accepts]: Start accepts. Automaton has 3738 states and 3748 transitions. Word has length 3158 [2018-11-10 10:06:04,214 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 10:06:04,214 INFO L481 AbstractCegarLoop]: Abstraction has 3738 states and 3748 transitions. [2018-11-10 10:06:04,214 INFO L482 AbstractCegarLoop]: Interpolant automaton has 66 states. [2018-11-10 10:06:04,214 INFO L276 IsEmpty]: Start isEmpty. Operand 3738 states and 3748 transitions. [2018-11-10 10:06:04,251 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3346 [2018-11-10 10:06:04,251 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 10:06:04,252 INFO L375 BasicCegarLoop]: trace histogram [522, 493, 492, 492, 492, 492, 30, 30, 30, 30, 29, 29, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 10:06:04,252 INFO L424 AbstractCegarLoop]: === Iteration 83 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 10:06:04,252 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 10:06:04,253 INFO L82 PathProgramCache]: Analyzing trace with hash -1980474346, now seen corresponding path program 68 times [2018-11-10 10:06:04,253 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 10:06:04,253 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 10:06:04,253 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:06:04,253 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 10:06:04,253 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:06:04,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 10:06:08,736 INFO L134 CoverageAnalysis]: Checked inductivity of 760180 backedges. 154707 proven. 12569 refuted. 0 times theorem prover too weak. 592904 trivial. 0 not checked. [2018-11-10 10:06:08,736 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 10:06:08,737 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 10:06:08,744 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-10 10:06:09,228 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-10 10:06:09,228 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 10:06:09,253 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 10:06:13,671 INFO L134 CoverageAnalysis]: Checked inductivity of 760180 backedges. 232422 proven. 2324 refuted. 0 times theorem prover too weak. 525434 trivial. 0 not checked. [2018-11-10 10:06:13,690 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 10:06:13,690 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 60] total 125 [2018-11-10 10:06:13,691 INFO L460 AbstractCegarLoop]: Interpolant automaton has 125 states [2018-11-10 10:06:13,691 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 125 interpolants. [2018-11-10 10:06:13,692 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2369, Invalid=13131, Unknown=0, NotChecked=0, Total=15500 [2018-11-10 10:06:13,692 INFO L87 Difference]: Start difference. First operand 3738 states and 3748 transitions. Second operand 125 states. [2018-11-10 10:06:16,819 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 10:06:16,819 INFO L93 Difference]: Finished difference Result 3374 states and 3377 transitions. [2018-11-10 10:06:16,819 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 151 states. [2018-11-10 10:06:16,819 INFO L78 Accepts]: Start accepts. Automaton has 125 states. Word has length 3345 [2018-11-10 10:06:16,820 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 10:06:16,823 INFO L225 Difference]: With dead ends: 3374 [2018-11-10 10:06:16,823 INFO L226 Difference]: Without dead ends: 3365 [2018-11-10 10:06:16,826 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3528 GetRequests, 3289 SyntacticMatches, 0 SemanticMatches, 239 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18718 ImplicationChecksByTransitivity, 4.1s TimeCoverageRelationStatistics Valid=8687, Invalid=49153, Unknown=0, NotChecked=0, Total=57840 [2018-11-10 10:06:16,827 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3365 states. [2018-11-10 10:06:16,838 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3365 to 3361. [2018-11-10 10:06:16,838 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3361 states. [2018-11-10 10:06:16,840 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3361 states to 3361 states and 3364 transitions. [2018-11-10 10:06:16,840 INFO L78 Accepts]: Start accepts. Automaton has 3361 states and 3364 transitions. Word has length 3345 [2018-11-10 10:06:16,842 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 10:06:16,842 INFO L481 AbstractCegarLoop]: Abstraction has 3361 states and 3364 transitions. [2018-11-10 10:06:16,842 INFO L482 AbstractCegarLoop]: Interpolant automaton has 125 states. [2018-11-10 10:06:16,842 INFO L276 IsEmpty]: Start isEmpty. Operand 3361 states and 3364 transitions. [2018-11-10 10:06:16,879 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3352 [2018-11-10 10:06:16,879 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 10:06:16,879 INFO L375 BasicCegarLoop]: trace histogram [523, 494, 493, 493, 493, 493, 30, 30, 30, 30, 29, 29, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 10:06:16,879 INFO L424 AbstractCegarLoop]: === Iteration 84 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 10:06:16,879 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 10:06:16,879 INFO L82 PathProgramCache]: Analyzing trace with hash -1554710514, now seen corresponding path program 69 times [2018-11-10 10:06:16,879 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 10:06:16,880 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 10:06:16,880 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:06:16,880 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 10:06:16,880 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:06:17,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 10:06:21,381 INFO L134 CoverageAnalysis]: Checked inductivity of 763193 backedges. 162174 proven. 7923 refuted. 0 times theorem prover too weak. 593096 trivial. 0 not checked. [2018-11-10 10:06:21,381 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 10:06:21,381 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 77 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 77 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 10:06:21,387 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-10 10:06:29,007 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 31 check-sat command(s) [2018-11-10 10:06:29,007 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 10:06:29,029 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 10:06:32,659 INFO L134 CoverageAnalysis]: Checked inductivity of 763193 backedges. 159681 proven. 7893 refuted. 0 times theorem prover too weak. 595619 trivial. 0 not checked. [2018-11-10 10:06:32,680 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 10:06:32,680 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 39] total 101 [2018-11-10 10:06:32,681 INFO L460 AbstractCegarLoop]: Interpolant automaton has 101 states [2018-11-10 10:06:32,681 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 101 interpolants. [2018-11-10 10:06:32,681 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2036, Invalid=8064, Unknown=0, NotChecked=0, Total=10100 [2018-11-10 10:06:32,681 INFO L87 Difference]: Start difference. First operand 3361 states and 3364 transitions. Second operand 101 states. [2018-11-10 10:06:35,354 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 10:06:35,354 INFO L93 Difference]: Finished difference Result 3567 states and 3572 transitions. [2018-11-10 10:06:35,354 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 99 states. [2018-11-10 10:06:35,354 INFO L78 Accepts]: Start accepts. Automaton has 101 states. Word has length 3351 [2018-11-10 10:06:35,355 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 10:06:35,358 INFO L225 Difference]: With dead ends: 3567 [2018-11-10 10:06:35,358 INFO L226 Difference]: Without dead ends: 3567 [2018-11-10 10:06:35,360 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3509 GetRequests, 3319 SyntacticMatches, 0 SemanticMatches, 190 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11393 ImplicationChecksByTransitivity, 3.1s TimeCoverageRelationStatistics Valid=8864, Invalid=27808, Unknown=0, NotChecked=0, Total=36672 [2018-11-10 10:06:35,361 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3567 states. [2018-11-10 10:06:35,374 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3567 to 3560. [2018-11-10 10:06:35,374 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3560 states. [2018-11-10 10:06:35,378 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3560 states to 3560 states and 3565 transitions. [2018-11-10 10:06:35,378 INFO L78 Accepts]: Start accepts. Automaton has 3560 states and 3565 transitions. Word has length 3351 [2018-11-10 10:06:35,380 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 10:06:35,380 INFO L481 AbstractCegarLoop]: Abstraction has 3560 states and 3565 transitions. [2018-11-10 10:06:35,380 INFO L482 AbstractCegarLoop]: Interpolant automaton has 101 states. [2018-11-10 10:06:35,380 INFO L276 IsEmpty]: Start isEmpty. Operand 3560 states and 3565 transitions. [2018-11-10 10:06:35,421 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3358 [2018-11-10 10:06:35,422 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 10:06:35,422 INFO L375 BasicCegarLoop]: trace histogram [524, 495, 494, 494, 494, 494, 30, 30, 30, 30, 29, 29, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 10:06:35,422 INFO L424 AbstractCegarLoop]: === Iteration 85 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 10:06:35,423 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 10:06:35,423 INFO L82 PathProgramCache]: Analyzing trace with hash -68996266, now seen corresponding path program 70 times [2018-11-10 10:06:35,423 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 10:06:35,423 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 10:06:35,424 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:06:35,424 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 10:06:35,424 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:06:35,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 10:06:39,022 INFO L134 CoverageAnalysis]: Checked inductivity of 766212 backedges. 87057 proven. 2959 refuted. 0 times theorem prover too weak. 676196 trivial. 0 not checked. [2018-11-10 10:06:39,023 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 10:06:39,023 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 10:06:39,028 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-10 10:06:51,100 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-10 10:06:51,100 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 10:06:51,146 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 10:06:54,246 INFO L134 CoverageAnalysis]: Checked inductivity of 766212 backedges. 86710 proven. 2700 refuted. 0 times theorem prover too weak. 676802 trivial. 0 not checked. [2018-11-10 10:06:54,277 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 10:06:54,277 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 32] total 68 [2018-11-10 10:06:54,278 INFO L460 AbstractCegarLoop]: Interpolant automaton has 69 states [2018-11-10 10:06:54,278 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2018-11-10 10:06:54,278 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=605, Invalid=4087, Unknown=0, NotChecked=0, Total=4692 [2018-11-10 10:06:54,278 INFO L87 Difference]: Start difference. First operand 3560 states and 3565 transitions. Second operand 69 states. [2018-11-10 10:06:57,555 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 10:06:57,555 INFO L93 Difference]: Finished difference Result 3982 states and 3993 transitions. [2018-11-10 10:06:57,555 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 99 states. [2018-11-10 10:06:57,555 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 3357 [2018-11-10 10:06:57,557 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 10:06:57,560 INFO L225 Difference]: With dead ends: 3982 [2018-11-10 10:06:57,560 INFO L226 Difference]: Without dead ends: 3982 [2018-11-10 10:06:57,560 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3428 GetRequests, 3326 SyntacticMatches, 0 SemanticMatches, 102 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1851 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=971, Invalid=9741, Unknown=0, NotChecked=0, Total=10712 [2018-11-10 10:06:57,561 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3982 states. [2018-11-10 10:06:57,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3982 to 3955. [2018-11-10 10:06:57,575 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3955 states. [2018-11-10 10:06:57,578 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3955 states to 3955 states and 3965 transitions. [2018-11-10 10:06:57,578 INFO L78 Accepts]: Start accepts. Automaton has 3955 states and 3965 transitions. Word has length 3357 [2018-11-10 10:06:57,579 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 10:06:57,579 INFO L481 AbstractCegarLoop]: Abstraction has 3955 states and 3965 transitions. [2018-11-10 10:06:57,580 INFO L482 AbstractCegarLoop]: Interpolant automaton has 69 states. [2018-11-10 10:06:57,580 INFO L276 IsEmpty]: Start isEmpty. Operand 3955 states and 3965 transitions. [2018-11-10 10:06:57,623 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3551 [2018-11-10 10:06:57,623 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 10:06:57,624 INFO L375 BasicCegarLoop]: trace histogram [555, 525, 524, 524, 524, 524, 31, 31, 31, 31, 30, 30, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 10:06:57,624 INFO L424 AbstractCegarLoop]: === Iteration 86 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 10:06:57,624 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 10:06:57,624 INFO L82 PathProgramCache]: Analyzing trace with hash -278226527, now seen corresponding path program 71 times [2018-11-10 10:06:57,624 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 10:06:57,625 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 10:06:57,625 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:06:57,625 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 10:06:57,625 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:06:57,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 10:07:02,560 INFO L134 CoverageAnalysis]: Checked inductivity of 861003 backedges. 170948 proven. 13452 refuted. 0 times theorem prover too weak. 676603 trivial. 0 not checked. [2018-11-10 10:07:02,560 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 10:07:02,560 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 79 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 79 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 10:07:02,567 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-10 10:07:36,416 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 74 check-sat command(s) [2018-11-10 10:07:36,417 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 10:07:36,479 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 10:07:41,564 INFO L134 CoverageAnalysis]: Checked inductivity of 861003 backedges. 256248 proven. 14656 refuted. 0 times theorem prover too weak. 590099 trivial. 0 not checked. [2018-11-10 10:07:41,600 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 10:07:41,600 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [70, 66] total 133 [2018-11-10 10:07:41,601 INFO L460 AbstractCegarLoop]: Interpolant automaton has 133 states [2018-11-10 10:07:41,601 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 133 interpolants. [2018-11-10 10:07:41,602 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2488, Invalid=15068, Unknown=0, NotChecked=0, Total=17556 [2018-11-10 10:07:41,602 INFO L87 Difference]: Start difference. First operand 3955 states and 3965 transitions. Second operand 133 states. [2018-11-10 10:07:46,306 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 10:07:46,306 INFO L93 Difference]: Finished difference Result 3579 states and 3582 transitions. [2018-11-10 10:07:46,306 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 161 states. [2018-11-10 10:07:46,306 INFO L78 Accepts]: Start accepts. Automaton has 133 states. Word has length 3550 [2018-11-10 10:07:46,308 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 10:07:46,311 INFO L225 Difference]: With dead ends: 3579 [2018-11-10 10:07:46,311 INFO L226 Difference]: Without dead ends: 3570 [2018-11-10 10:07:46,315 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3773 GetRequests, 3489 SyntacticMatches, 0 SemanticMatches, 284 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 27763 ImplicationChecksByTransitivity, 5.4s TimeCoverageRelationStatistics Valid=11925, Invalid=69585, Unknown=0, NotChecked=0, Total=81510 [2018-11-10 10:07:46,317 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3570 states. [2018-11-10 10:07:46,328 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3570 to 3566. [2018-11-10 10:07:46,328 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3566 states. [2018-11-10 10:07:46,331 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3566 states to 3566 states and 3569 transitions. [2018-11-10 10:07:46,332 INFO L78 Accepts]: Start accepts. Automaton has 3566 states and 3569 transitions. Word has length 3550 [2018-11-10 10:07:46,333 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 10:07:46,333 INFO L481 AbstractCegarLoop]: Abstraction has 3566 states and 3569 transitions. [2018-11-10 10:07:46,333 INFO L482 AbstractCegarLoop]: Interpolant automaton has 133 states. [2018-11-10 10:07:46,333 INFO L276 IsEmpty]: Start isEmpty. Operand 3566 states and 3569 transitions. [2018-11-10 10:07:46,376 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3557 [2018-11-10 10:07:46,376 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 10:07:46,377 INFO L375 BasicCegarLoop]: trace histogram [556, 526, 525, 525, 525, 525, 31, 31, 31, 31, 30, 30, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 10:07:46,377 INFO L424 AbstractCegarLoop]: === Iteration 87 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 10:07:46,378 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 10:07:46,378 INFO L82 PathProgramCache]: Analyzing trace with hash 1135895897, now seen corresponding path program 72 times [2018-11-10 10:07:46,378 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 10:07:46,378 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 10:07:46,379 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:07:46,379 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 10:07:46,379 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:07:46,662 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 10:07:51,332 INFO L134 CoverageAnalysis]: Checked inductivity of 864210 backedges. 178942 proven. 8466 refuted. 0 times theorem prover too weak. 676802 trivial. 0 not checked. [2018-11-10 10:07:51,332 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 10:07:51,332 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/z3 Starting monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 10:07:51,337 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-10 10:08:19,287 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 59 check-sat command(s) [2018-11-10 10:08:19,287 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-10 10:08:19,344 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 10:08:24,857 INFO L134 CoverageAnalysis]: Checked inductivity of 864210 backedges. 241440 proven. 50280 refuted. 0 times theorem prover too weak. 572490 trivial. 0 not checked. [2018-11-10 10:08:24,883 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-10 10:08:24,883 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [70, 58] total 127 [2018-11-10 10:08:24,884 INFO L460 AbstractCegarLoop]: Interpolant automaton has 127 states [2018-11-10 10:08:24,885 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 127 interpolants. [2018-11-10 10:08:24,885 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1939, Invalid=14063, Unknown=0, NotChecked=0, Total=16002 [2018-11-10 10:08:24,885 INFO L87 Difference]: Start difference. First operand 3566 states and 3569 transitions. Second operand 127 states. [2018-11-10 10:08:38,821 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 10:08:38,821 INFO L93 Difference]: Finished difference Result 3988 states and 3997 transitions. [2018-11-10 10:08:38,821 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 367 states. [2018-11-10 10:08:38,821 INFO L78 Accepts]: Start accepts. Automaton has 127 states. Word has length 3556 [2018-11-10 10:08:38,823 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 10:08:38,826 INFO L225 Difference]: With dead ends: 3988 [2018-11-10 10:08:38,826 INFO L226 Difference]: Without dead ends: 3988 [2018-11-10 10:08:38,831 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3959 GetRequests, 3499 SyntacticMatches, 2 SemanticMatches, 458 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 83104 ImplicationChecksByTransitivity, 14.1s TimeCoverageRelationStatistics Valid=29647, Invalid=181493, Unknown=0, NotChecked=0, Total=211140 [2018-11-10 10:08:38,833 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3988 states. [2018-11-10 10:08:38,845 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3988 to 3988. [2018-11-10 10:08:38,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3988 states. [2018-11-10 10:08:38,849 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3988 states to 3988 states and 3997 transitions. [2018-11-10 10:08:38,849 INFO L78 Accepts]: Start accepts. Automaton has 3988 states and 3997 transitions. Word has length 3556 [2018-11-10 10:08:38,850 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 10:08:38,851 INFO L481 AbstractCegarLoop]: Abstraction has 3988 states and 3997 transitions. [2018-11-10 10:08:38,851 INFO L482 AbstractCegarLoop]: Interpolant automaton has 127 states. [2018-11-10 10:08:38,851 INFO L276 IsEmpty]: Start isEmpty. Operand 3988 states and 3997 transitions. [2018-11-10 10:08:38,898 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3774 [2018-11-10 10:08:38,898 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 10:08:38,898 INFO L375 BasicCegarLoop]: trace histogram [591, 560, 559, 559, 559, 559, 32, 32, 32, 32, 31, 31, 31, 31, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 10:08:38,898 INFO L424 AbstractCegarLoop]: === Iteration 88 === [fooErr2REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION]=== [2018-11-10 10:08:38,898 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 10:08:38,899 INFO L82 PathProgramCache]: Analyzing trace with hash 820683566, now seen corresponding path program 73 times [2018-11-10 10:08:38,899 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 10:08:38,899 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 10:08:38,900 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:08:38,900 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 10:08:38,900 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 10:08:39,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 10:08:41,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 10:08:41,656 INFO L442 BasicCegarLoop]: Counterexample might be feasible [2018-11-10 10:08:42,021 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 10.11 10:08:42 BoogieIcfgContainer [2018-11-10 10:08:42,022 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-10 10:08:42,022 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-10 10:08:42,022 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-10 10:08:42,022 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-10 10:08:42,023 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.11 09:58:27" (3/4) ... [2018-11-10 10:08:42,025 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-11-10 10:08:42,350 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_94167245-8647-4129-a718-d66824449878/bin-2019/uautomizer/witness.graphml [2018-11-10 10:08:42,350 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-10 10:08:42,352 INFO L168 Benchmark]: Toolchain (without parser) took 615425.78 ms. Allocated memory was 1.0 GB in the beginning and 5.1 GB in the end (delta: 4.0 GB). Free memory was 960.3 MB in the beginning and 2.8 GB in the end (delta: -1.8 GB). Peak memory consumption was 2.2 GB. Max. memory is 11.5 GB. [2018-11-10 10:08:42,353 INFO L168 Benchmark]: CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 985.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-10 10:08:42,353 INFO L168 Benchmark]: CACSL2BoogieTranslator took 166.11 ms. Allocated memory is still 1.0 GB. Free memory was 960.3 MB in the beginning and 949.6 MB in the end (delta: 10.7 MB). Peak memory consumption was 10.7 MB. Max. memory is 11.5 GB. [2018-11-10 10:08:42,354 INFO L168 Benchmark]: Boogie Preprocessor took 21.40 ms. Allocated memory is still 1.0 GB. Free memory was 949.6 MB in the beginning and 946.9 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-11-10 10:08:42,354 INFO L168 Benchmark]: RCFGBuilder took 223.46 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 130.0 MB). Free memory was 946.9 MB in the beginning and 1.1 GB in the end (delta: -163.5 MB). Peak memory consumption was 14.5 MB. Max. memory is 11.5 GB. [2018-11-10 10:08:42,354 INFO L168 Benchmark]: TraceAbstraction took 614681.98 ms. Allocated memory was 1.2 GB in the beginning and 5.1 GB in the end (delta: 3.9 GB). Free memory was 1.1 GB in the beginning and 2.9 GB in the end (delta: -1.7 GB). Peak memory consumption was 2.2 GB. Max. memory is 11.5 GB. [2018-11-10 10:08:42,354 INFO L168 Benchmark]: Witness Printer took 328.21 ms. Allocated memory is still 5.1 GB. Free memory was 2.9 GB in the beginning and 2.8 GB in the end (delta: 81.6 MB). Peak memory consumption was 81.6 MB. Max. memory is 11.5 GB. [2018-11-10 10:08:42,356 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 985.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 166.11 ms. Allocated memory is still 1.0 GB. Free memory was 960.3 MB in the beginning and 949.6 MB in the end (delta: 10.7 MB). Peak memory consumption was 10.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 21.40 ms. Allocated memory is still 1.0 GB. Free memory was 949.6 MB in the beginning and 946.9 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 223.46 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 130.0 MB). Free memory was 946.9 MB in the beginning and 1.1 GB in the end (delta: -163.5 MB). Peak memory consumption was 14.5 MB. Max. memory is 11.5 GB. * TraceAbstraction took 614681.98 ms. Allocated memory was 1.2 GB in the beginning and 5.1 GB in the end (delta: 3.9 GB). Free memory was 1.1 GB in the beginning and 2.9 GB in the end (delta: -1.7 GB). Peak memory consumption was 2.2 GB. Max. memory is 11.5 GB. * Witness Printer took 328.21 ms. Allocated memory is still 5.1 GB. Free memory was 2.9 GB in the beginning and 2.8 GB in the end (delta: 81.6 MB). Peak memory consumption was 81.6 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 18]: array index can be out of bounds array index can be out of bounds We found a FailurePath: [L24] int i, b[32]; VAL [b={158:0}] [L25] FCALL char mask[32]; VAL [b={158:0}, mask={160:0}] [L26] i = 0 VAL [b={158:0}, i=0, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=0, mask={160:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=1, b={160:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=1, b={160:0}, b={160:0}, i=0, size=1] [L17] COND TRUE i <= size VAL [\old(size)=1, b={160:0}, b={160:0}, i=0, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={160:0}, b={160:0}, i=0, size=1] [L18] EXPR, FCALL b[i] VAL [\old(size)=1, b={160:0}, b={160:0}, b[i]=129, i=0, size=1] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=1, b={160:0}, b={160:0}, i=1, size=1] [L17] COND TRUE i <= size VAL [\old(size)=1, b={160:0}, b={160:0}, i=1, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={160:0}, b={160:0}, i=1, size=1] [L18] EXPR, FCALL b[i] VAL [\old(size)=1, b={160:0}, b={160:0}, b[i]=144, i=1, size=1] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=1, b={160:0}, b={160:0}, i=2, size=1] [L17] COND FALSE !(i <= size) VAL [\old(size)=1, b={160:0}, b={160:0}, i=2, size=1] [L20] RET return i; VAL [\old(size)=1, \result=2, b={160:0}, b={160:0}, i=2, size=1] [L27] EXPR foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=2, i=0, mask={160:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=2, i=0, mask={160:0}] [L26] i++ VAL [b={158:0}, i=1, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=1, mask={160:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=2, b={160:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=2, b={160:0}, b={160:0}, i=0, size=2] [L17] COND TRUE i <= size VAL [\old(size)=2, b={160:0}, b={160:0}, i=0, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={160:0}, b={160:0}, i=0, size=2] [L18] EXPR, FCALL b[i] VAL [\old(size)=2, b={160:0}, b={160:0}, b[i]=129, i=0, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={160:0}, b={160:0}, i=1, size=2] [L17] COND TRUE i <= size VAL [\old(size)=2, b={160:0}, b={160:0}, i=1, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={160:0}, b={160:0}, i=1, size=2] [L18] EXPR, FCALL b[i] VAL [\old(size)=2, b={160:0}, b={160:0}, b[i]=144, i=1, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={160:0}, b={160:0}, i=2, size=2] [L17] COND TRUE i <= size VAL [\old(size)=2, b={160:0}, b={160:0}, i=2, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={160:0}, b={160:0}, i=2, size=2] [L18] EXPR, FCALL b[i] VAL [\old(size)=2, b={160:0}, b={160:0}, b[i]=134, i=2, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={160:0}, b={160:0}, i=3, size=2] [L17] COND FALSE !(i <= size) VAL [\old(size)=2, b={160:0}, b={160:0}, i=3, size=2] [L20] RET return i; VAL [\old(size)=2, \result=3, b={160:0}, b={160:0}, i=3, size=2] [L27] EXPR foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=3, i=1, mask={160:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=3, i=1, mask={160:0}] [L26] i++ VAL [b={158:0}, i=2, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=2, mask={160:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=3, b={160:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=3, b={160:0}, b={160:0}, i=0, size=3] [L17] COND TRUE i <= size VAL [\old(size)=3, b={160:0}, b={160:0}, i=0, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={160:0}, b={160:0}, i=0, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={160:0}, b={160:0}, b[i]=129, i=0, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={160:0}, b={160:0}, i=1, size=3] [L17] COND TRUE i <= size VAL [\old(size)=3, b={160:0}, b={160:0}, i=1, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={160:0}, b={160:0}, i=1, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={160:0}, b={160:0}, b[i]=144, i=1, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={160:0}, b={160:0}, i=2, size=3] [L17] COND TRUE i <= size VAL [\old(size)=3, b={160:0}, b={160:0}, i=2, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={160:0}, b={160:0}, i=2, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={160:0}, b={160:0}, b[i]=134, i=2, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={160:0}, b={160:0}, i=3, size=3] [L17] COND TRUE i <= size VAL [\old(size)=3, b={160:0}, b={160:0}, i=3, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={160:0}, b={160:0}, i=3, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={160:0}, b={160:0}, b[i]=132, i=3, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={160:0}, b={160:0}, i=4, size=3] [L17] COND FALSE !(i <= size) VAL [\old(size)=3, b={160:0}, b={160:0}, i=4, size=3] [L20] RET return i; VAL [\old(size)=3, \result=4, b={160:0}, b={160:0}, i=4, size=3] [L27] EXPR foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=4, i=2, mask={160:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=4, i=2, mask={160:0}] [L26] i++ VAL [b={158:0}, i=3, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=3, mask={160:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=4, b={160:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=4, b={160:0}, b={160:0}, i=0, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={160:0}, b={160:0}, i=0, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={160:0}, b={160:0}, i=0, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={160:0}, b={160:0}, b[i]=129, i=0, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={160:0}, b={160:0}, i=1, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={160:0}, b={160:0}, i=1, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={160:0}, b={160:0}, i=1, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={160:0}, b={160:0}, b[i]=144, i=1, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={160:0}, b={160:0}, i=2, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={160:0}, b={160:0}, i=2, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={160:0}, b={160:0}, i=2, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={160:0}, b={160:0}, b[i]=134, i=2, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={160:0}, b={160:0}, i=3, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={160:0}, b={160:0}, i=3, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={160:0}, b={160:0}, i=3, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={160:0}, b={160:0}, b[i]=132, i=3, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={160:0}, b={160:0}, i=4, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={160:0}, b={160:0}, i=4, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={160:0}, b={160:0}, i=4, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={160:0}, b={160:0}, b[i]=141, i=4, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={160:0}, b={160:0}, i=5, size=4] [L17] COND FALSE !(i <= size) VAL [\old(size)=4, b={160:0}, b={160:0}, i=5, size=4] [L20] RET return i; VAL [\old(size)=4, \result=5, b={160:0}, b={160:0}, i=5, size=4] [L27] EXPR foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=5, i=3, mask={160:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=5, i=3, mask={160:0}] [L26] i++ VAL [b={158:0}, i=4, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=4, mask={160:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=5, b={160:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=5, b={160:0}, b={160:0}, i=0, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={160:0}, b={160:0}, i=0, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={160:0}, b={160:0}, i=0, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={160:0}, b={160:0}, b[i]=129, i=0, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={160:0}, b={160:0}, i=1, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={160:0}, b={160:0}, i=1, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={160:0}, b={160:0}, i=1, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={160:0}, b={160:0}, b[i]=144, i=1, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={160:0}, b={160:0}, i=2, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={160:0}, b={160:0}, i=2, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={160:0}, b={160:0}, i=2, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={160:0}, b={160:0}, b[i]=134, i=2, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={160:0}, b={160:0}, i=3, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={160:0}, b={160:0}, i=3, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={160:0}, b={160:0}, i=3, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={160:0}, b={160:0}, b[i]=132, i=3, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={160:0}, b={160:0}, i=4, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={160:0}, b={160:0}, i=4, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={160:0}, b={160:0}, i=4, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={160:0}, b={160:0}, b[i]=141, i=4, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={160:0}, b={160:0}, i=5, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={160:0}, b={160:0}, i=5, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={160:0}, b={160:0}, i=5, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={160:0}, b={160:0}, b[i]=146, i=5, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={160:0}, b={160:0}, i=6, size=5] [L17] COND FALSE !(i <= size) VAL [\old(size)=5, b={160:0}, b={160:0}, i=6, size=5] [L20] RET return i; VAL [\old(size)=5, \result=6, b={160:0}, b={160:0}, i=6, size=5] [L27] EXPR foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=6, i=4, mask={160:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=6, i=4, mask={160:0}] [L26] i++ VAL [b={158:0}, i=5, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=5, mask={160:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=6, b={160:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=6, b={160:0}, b={160:0}, i=0, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={160:0}, b={160:0}, i=0, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={160:0}, b={160:0}, i=0, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={160:0}, b={160:0}, b[i]=129, i=0, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={160:0}, b={160:0}, i=1, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={160:0}, b={160:0}, i=1, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={160:0}, b={160:0}, i=1, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={160:0}, b={160:0}, b[i]=144, i=1, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={160:0}, b={160:0}, i=2, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={160:0}, b={160:0}, i=2, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={160:0}, b={160:0}, i=2, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={160:0}, b={160:0}, b[i]=134, i=2, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={160:0}, b={160:0}, i=3, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={160:0}, b={160:0}, i=3, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={160:0}, b={160:0}, i=3, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={160:0}, b={160:0}, b[i]=132, i=3, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={160:0}, b={160:0}, i=4, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={160:0}, b={160:0}, i=4, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={160:0}, b={160:0}, i=4, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={160:0}, b={160:0}, b[i]=141, i=4, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={160:0}, b={160:0}, i=5, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={160:0}, b={160:0}, i=5, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={160:0}, b={160:0}, i=5, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={160:0}, b={160:0}, b[i]=146, i=5, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={160:0}, b={160:0}, i=6, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={160:0}, b={160:0}, i=6, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={160:0}, b={160:0}, i=6, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={160:0}, b={160:0}, b[i]=142, i=6, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={160:0}, b={160:0}, i=7, size=6] [L17] COND FALSE !(i <= size) VAL [\old(size)=6, b={160:0}, b={160:0}, i=7, size=6] [L20] RET return i; VAL [\old(size)=6, \result=7, b={160:0}, b={160:0}, i=7, size=6] [L27] EXPR foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=7, i=5, mask={160:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=7, i=5, mask={160:0}] [L26] i++ VAL [b={158:0}, i=6, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=6, mask={160:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=7, b={160:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=7, b={160:0}, b={160:0}, i=0, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={160:0}, b={160:0}, i=0, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={160:0}, b={160:0}, i=0, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={160:0}, b={160:0}, b[i]=129, i=0, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={160:0}, b={160:0}, i=1, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={160:0}, b={160:0}, i=1, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={160:0}, b={160:0}, i=1, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={160:0}, b={160:0}, b[i]=144, i=1, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={160:0}, b={160:0}, i=2, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={160:0}, b={160:0}, i=2, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={160:0}, b={160:0}, i=2, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={160:0}, b={160:0}, b[i]=134, i=2, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={160:0}, b={160:0}, i=3, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={160:0}, b={160:0}, i=3, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={160:0}, b={160:0}, i=3, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={160:0}, b={160:0}, b[i]=132, i=3, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={160:0}, b={160:0}, i=4, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={160:0}, b={160:0}, i=4, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={160:0}, b={160:0}, i=4, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={160:0}, b={160:0}, b[i]=141, i=4, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={160:0}, b={160:0}, i=5, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={160:0}, b={160:0}, i=5, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={160:0}, b={160:0}, i=5, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={160:0}, b={160:0}, b[i]=146, i=5, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={160:0}, b={160:0}, i=6, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={160:0}, b={160:0}, i=6, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={160:0}, b={160:0}, i=6, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={160:0}, b={160:0}, b[i]=142, i=6, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={160:0}, b={160:0}, i=7, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={160:0}, b={160:0}, i=7, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={160:0}, b={160:0}, i=7, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={160:0}, b={160:0}, b[i]=157, i=7, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={160:0}, b={160:0}, i=8, size=7] [L17] COND FALSE !(i <= size) VAL [\old(size)=7, b={160:0}, b={160:0}, i=8, size=7] [L20] RET return i; VAL [\old(size)=7, \result=8, b={160:0}, b={160:0}, i=8, size=7] [L27] EXPR foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=8, i=6, mask={160:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=8, i=6, mask={160:0}] [L26] i++ VAL [b={158:0}, i=7, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=7, mask={160:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=8, b={160:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=8, b={160:0}, b={160:0}, i=0, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={160:0}, b={160:0}, i=0, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={160:0}, b={160:0}, i=0, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={160:0}, b={160:0}, b[i]=129, i=0, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={160:0}, b={160:0}, i=1, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={160:0}, b={160:0}, i=1, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={160:0}, b={160:0}, i=1, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={160:0}, b={160:0}, b[i]=144, i=1, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={160:0}, b={160:0}, i=2, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={160:0}, b={160:0}, i=2, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={160:0}, b={160:0}, i=2, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={160:0}, b={160:0}, b[i]=134, i=2, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={160:0}, b={160:0}, i=3, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={160:0}, b={160:0}, i=3, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={160:0}, b={160:0}, i=3, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={160:0}, b={160:0}, b[i]=132, i=3, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={160:0}, b={160:0}, i=4, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={160:0}, b={160:0}, i=4, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={160:0}, b={160:0}, i=4, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={160:0}, b={160:0}, b[i]=141, i=4, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={160:0}, b={160:0}, i=5, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={160:0}, b={160:0}, i=5, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={160:0}, b={160:0}, i=5, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={160:0}, b={160:0}, b[i]=146, i=5, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={160:0}, b={160:0}, i=6, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={160:0}, b={160:0}, i=6, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={160:0}, b={160:0}, i=6, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={160:0}, b={160:0}, b[i]=142, i=6, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={160:0}, b={160:0}, i=7, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={160:0}, b={160:0}, i=7, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={160:0}, b={160:0}, i=7, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={160:0}, b={160:0}, b[i]=157, i=7, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={160:0}, b={160:0}, i=8, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={160:0}, b={160:0}, i=8, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={160:0}, b={160:0}, i=8, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={160:0}, b={160:0}, b[i]=145, i=8, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={160:0}, b={160:0}, i=9, size=8] [L17] COND FALSE !(i <= size) VAL [\old(size)=8, b={160:0}, b={160:0}, i=9, size=8] [L20] RET return i; VAL [\old(size)=8, \result=9, b={160:0}, b={160:0}, i=9, size=8] [L27] EXPR foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=9, i=7, mask={160:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=9, i=7, mask={160:0}] [L26] i++ VAL [b={158:0}, i=8, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=8, mask={160:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=9, b={160:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=9, b={160:0}, b={160:0}, i=0, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={160:0}, b={160:0}, i=0, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={160:0}, b={160:0}, i=0, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={160:0}, b={160:0}, b[i]=129, i=0, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={160:0}, b={160:0}, i=1, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={160:0}, b={160:0}, i=1, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={160:0}, b={160:0}, i=1, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={160:0}, b={160:0}, b[i]=144, i=1, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={160:0}, b={160:0}, i=2, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={160:0}, b={160:0}, i=2, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={160:0}, b={160:0}, i=2, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={160:0}, b={160:0}, b[i]=134, i=2, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={160:0}, b={160:0}, i=3, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={160:0}, b={160:0}, i=3, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={160:0}, b={160:0}, i=3, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={160:0}, b={160:0}, b[i]=132, i=3, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={160:0}, b={160:0}, i=4, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={160:0}, b={160:0}, i=4, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={160:0}, b={160:0}, i=4, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={160:0}, b={160:0}, b[i]=141, i=4, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={160:0}, b={160:0}, i=5, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={160:0}, b={160:0}, i=5, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={160:0}, b={160:0}, i=5, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={160:0}, b={160:0}, b[i]=146, i=5, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={160:0}, b={160:0}, i=6, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={160:0}, b={160:0}, i=6, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={160:0}, b={160:0}, i=6, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={160:0}, b={160:0}, b[i]=142, i=6, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={160:0}, b={160:0}, i=7, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={160:0}, b={160:0}, i=7, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={160:0}, b={160:0}, i=7, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={160:0}, b={160:0}, b[i]=157, i=7, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={160:0}, b={160:0}, i=8, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={160:0}, b={160:0}, i=8, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={160:0}, b={160:0}, i=8, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={160:0}, b={160:0}, b[i]=145, i=8, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={160:0}, b={160:0}, i=9, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={160:0}, b={160:0}, i=9, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={160:0}, b={160:0}, i=9, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={160:0}, b={160:0}, b[i]=153, i=9, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={160:0}, b={160:0}, i=10, size=9] [L17] COND FALSE !(i <= size) VAL [\old(size)=9, b={160:0}, b={160:0}, i=10, size=9] [L20] RET return i; VAL [\old(size)=9, \result=10, b={160:0}, b={160:0}, i=10, size=9] [L27] EXPR foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=10, i=8, mask={160:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=10, i=8, mask={160:0}] [L26] i++ VAL [b={158:0}, i=9, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=9, mask={160:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=10, b={160:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=10, b={160:0}, b={160:0}, i=0, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={160:0}, b={160:0}, i=0, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={160:0}, b={160:0}, i=0, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={160:0}, b={160:0}, b[i]=129, i=0, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={160:0}, b={160:0}, i=1, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={160:0}, b={160:0}, i=1, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={160:0}, b={160:0}, i=1, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={160:0}, b={160:0}, b[i]=144, i=1, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={160:0}, b={160:0}, i=2, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={160:0}, b={160:0}, i=2, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={160:0}, b={160:0}, i=2, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={160:0}, b={160:0}, b[i]=134, i=2, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={160:0}, b={160:0}, i=3, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={160:0}, b={160:0}, i=3, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={160:0}, b={160:0}, i=3, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={160:0}, b={160:0}, b[i]=132, i=3, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={160:0}, b={160:0}, i=4, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={160:0}, b={160:0}, i=4, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={160:0}, b={160:0}, i=4, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={160:0}, b={160:0}, b[i]=141, i=4, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={160:0}, b={160:0}, i=5, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={160:0}, b={160:0}, i=5, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={160:0}, b={160:0}, i=5, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={160:0}, b={160:0}, b[i]=146, i=5, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={160:0}, b={160:0}, i=6, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={160:0}, b={160:0}, i=6, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={160:0}, b={160:0}, i=6, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={160:0}, b={160:0}, b[i]=142, i=6, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={160:0}, b={160:0}, i=7, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={160:0}, b={160:0}, i=7, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={160:0}, b={160:0}, i=7, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={160:0}, b={160:0}, b[i]=157, i=7, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={160:0}, b={160:0}, i=8, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={160:0}, b={160:0}, i=8, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={160:0}, b={160:0}, i=8, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={160:0}, b={160:0}, b[i]=145, i=8, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={160:0}, b={160:0}, i=9, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={160:0}, b={160:0}, i=9, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={160:0}, b={160:0}, i=9, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={160:0}, b={160:0}, b[i]=153, i=9, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={160:0}, b={160:0}, i=10, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={160:0}, b={160:0}, i=10, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={160:0}, b={160:0}, i=10, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={160:0}, b={160:0}, b[i]=149, i=10, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={160:0}, b={160:0}, i=11, size=10] [L17] COND FALSE !(i <= size) VAL [\old(size)=10, b={160:0}, b={160:0}, i=11, size=10] [L20] RET return i; VAL [\old(size)=10, \result=11, b={160:0}, b={160:0}, i=11, size=10] [L27] EXPR foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=11, i=9, mask={160:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=11, i=9, mask={160:0}] [L26] i++ VAL [b={158:0}, i=10, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=10, mask={160:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=11, b={160:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=11, b={160:0}, b={160:0}, i=0, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={160:0}, b={160:0}, i=0, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={160:0}, b={160:0}, i=0, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={160:0}, b={160:0}, b[i]=129, i=0, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={160:0}, b={160:0}, i=1, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={160:0}, b={160:0}, i=1, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={160:0}, b={160:0}, i=1, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={160:0}, b={160:0}, b[i]=144, i=1, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={160:0}, b={160:0}, i=2, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={160:0}, b={160:0}, i=2, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={160:0}, b={160:0}, i=2, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={160:0}, b={160:0}, b[i]=134, i=2, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={160:0}, b={160:0}, i=3, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={160:0}, b={160:0}, i=3, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={160:0}, b={160:0}, i=3, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={160:0}, b={160:0}, b[i]=132, i=3, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={160:0}, b={160:0}, i=4, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={160:0}, b={160:0}, i=4, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={160:0}, b={160:0}, i=4, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={160:0}, b={160:0}, b[i]=141, i=4, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={160:0}, b={160:0}, i=5, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={160:0}, b={160:0}, i=5, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={160:0}, b={160:0}, i=5, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={160:0}, b={160:0}, b[i]=146, i=5, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={160:0}, b={160:0}, i=6, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={160:0}, b={160:0}, i=6, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={160:0}, b={160:0}, i=6, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={160:0}, b={160:0}, b[i]=142, i=6, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={160:0}, b={160:0}, i=7, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={160:0}, b={160:0}, i=7, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={160:0}, b={160:0}, i=7, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={160:0}, b={160:0}, b[i]=157, i=7, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={160:0}, b={160:0}, i=8, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={160:0}, b={160:0}, i=8, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={160:0}, b={160:0}, i=8, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={160:0}, b={160:0}, b[i]=145, i=8, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={160:0}, b={160:0}, i=9, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={160:0}, b={160:0}, i=9, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={160:0}, b={160:0}, i=9, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={160:0}, b={160:0}, b[i]=153, i=9, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={160:0}, b={160:0}, i=10, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={160:0}, b={160:0}, i=10, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={160:0}, b={160:0}, i=10, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={160:0}, b={160:0}, b[i]=149, i=10, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={160:0}, b={160:0}, i=11, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={160:0}, b={160:0}, i=11, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={160:0}, b={160:0}, i=11, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={160:0}, b={160:0}, b[i]=135, i=11, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={160:0}, b={160:0}, i=12, size=11] [L17] COND FALSE !(i <= size) VAL [\old(size)=11, b={160:0}, b={160:0}, i=12, size=11] [L20] RET return i; VAL [\old(size)=11, \result=12, b={160:0}, b={160:0}, i=12, size=11] [L27] EXPR foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=12, i=10, mask={160:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=12, i=10, mask={160:0}] [L26] i++ VAL [b={158:0}, i=11, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=11, mask={160:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=12, b={160:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=12, b={160:0}, b={160:0}, i=0, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={160:0}, b={160:0}, i=0, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={160:0}, b={160:0}, i=0, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={160:0}, b={160:0}, b[i]=129, i=0, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={160:0}, b={160:0}, i=1, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={160:0}, b={160:0}, i=1, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={160:0}, b={160:0}, i=1, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={160:0}, b={160:0}, b[i]=144, i=1, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={160:0}, b={160:0}, i=2, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={160:0}, b={160:0}, i=2, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={160:0}, b={160:0}, i=2, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={160:0}, b={160:0}, b[i]=134, i=2, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={160:0}, b={160:0}, i=3, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={160:0}, b={160:0}, i=3, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={160:0}, b={160:0}, i=3, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={160:0}, b={160:0}, b[i]=132, i=3, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={160:0}, b={160:0}, i=4, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={160:0}, b={160:0}, i=4, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={160:0}, b={160:0}, i=4, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={160:0}, b={160:0}, b[i]=141, i=4, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={160:0}, b={160:0}, i=5, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={160:0}, b={160:0}, i=5, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={160:0}, b={160:0}, i=5, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={160:0}, b={160:0}, b[i]=146, i=5, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={160:0}, b={160:0}, i=6, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={160:0}, b={160:0}, i=6, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={160:0}, b={160:0}, i=6, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={160:0}, b={160:0}, b[i]=142, i=6, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={160:0}, b={160:0}, i=7, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={160:0}, b={160:0}, i=7, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={160:0}, b={160:0}, i=7, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={160:0}, b={160:0}, b[i]=157, i=7, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={160:0}, b={160:0}, i=8, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={160:0}, b={160:0}, i=8, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={160:0}, b={160:0}, i=8, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={160:0}, b={160:0}, b[i]=145, i=8, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={160:0}, b={160:0}, i=9, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={160:0}, b={160:0}, i=9, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={160:0}, b={160:0}, i=9, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={160:0}, b={160:0}, b[i]=153, i=9, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={160:0}, b={160:0}, i=10, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={160:0}, b={160:0}, i=10, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={160:0}, b={160:0}, i=10, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={160:0}, b={160:0}, b[i]=149, i=10, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={160:0}, b={160:0}, i=11, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={160:0}, b={160:0}, i=11, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={160:0}, b={160:0}, i=11, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={160:0}, b={160:0}, b[i]=135, i=11, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={160:0}, b={160:0}, i=12, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={160:0}, b={160:0}, i=12, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={160:0}, b={160:0}, i=12, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={160:0}, b={160:0}, b[i]=139, i=12, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={160:0}, b={160:0}, i=13, size=12] [L17] COND FALSE !(i <= size) VAL [\old(size)=12, b={160:0}, b={160:0}, i=13, size=12] [L20] RET return i; VAL [\old(size)=12, \result=13, b={160:0}, b={160:0}, i=13, size=12] [L27] EXPR foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=13, i=11, mask={160:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=13, i=11, mask={160:0}] [L26] i++ VAL [b={158:0}, i=12, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=12, mask={160:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=13, b={160:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=13, b={160:0}, b={160:0}, i=0, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={160:0}, b={160:0}, i=0, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={160:0}, b={160:0}, i=0, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={160:0}, b={160:0}, b[i]=129, i=0, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={160:0}, b={160:0}, i=1, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={160:0}, b={160:0}, i=1, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={160:0}, b={160:0}, i=1, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={160:0}, b={160:0}, b[i]=144, i=1, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={160:0}, b={160:0}, i=2, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={160:0}, b={160:0}, i=2, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={160:0}, b={160:0}, i=2, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={160:0}, b={160:0}, b[i]=134, i=2, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={160:0}, b={160:0}, i=3, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={160:0}, b={160:0}, i=3, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={160:0}, b={160:0}, i=3, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={160:0}, b={160:0}, b[i]=132, i=3, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={160:0}, b={160:0}, i=4, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={160:0}, b={160:0}, i=4, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={160:0}, b={160:0}, i=4, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={160:0}, b={160:0}, b[i]=141, i=4, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={160:0}, b={160:0}, i=5, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={160:0}, b={160:0}, i=5, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={160:0}, b={160:0}, i=5, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={160:0}, b={160:0}, b[i]=146, i=5, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={160:0}, b={160:0}, i=6, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={160:0}, b={160:0}, i=6, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={160:0}, b={160:0}, i=6, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={160:0}, b={160:0}, b[i]=142, i=6, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={160:0}, b={160:0}, i=7, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={160:0}, b={160:0}, i=7, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={160:0}, b={160:0}, i=7, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={160:0}, b={160:0}, b[i]=157, i=7, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={160:0}, b={160:0}, i=8, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={160:0}, b={160:0}, i=8, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={160:0}, b={160:0}, i=8, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={160:0}, b={160:0}, b[i]=145, i=8, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={160:0}, b={160:0}, i=9, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={160:0}, b={160:0}, i=9, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={160:0}, b={160:0}, i=9, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={160:0}, b={160:0}, b[i]=153, i=9, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={160:0}, b={160:0}, i=10, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={160:0}, b={160:0}, i=10, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={160:0}, b={160:0}, i=10, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={160:0}, b={160:0}, b[i]=149, i=10, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={160:0}, b={160:0}, i=11, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={160:0}, b={160:0}, i=11, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={160:0}, b={160:0}, i=11, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={160:0}, b={160:0}, b[i]=135, i=11, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={160:0}, b={160:0}, i=12, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={160:0}, b={160:0}, i=12, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={160:0}, b={160:0}, i=12, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={160:0}, b={160:0}, b[i]=139, i=12, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={160:0}, b={160:0}, i=13, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={160:0}, b={160:0}, i=13, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={160:0}, b={160:0}, i=13, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={160:0}, b={160:0}, b[i]=136, i=13, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={160:0}, b={160:0}, i=14, size=13] [L17] COND FALSE !(i <= size) VAL [\old(size)=13, b={160:0}, b={160:0}, i=14, size=13] [L20] RET return i; VAL [\old(size)=13, \result=14, b={160:0}, b={160:0}, i=14, size=13] [L27] EXPR foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=14, i=12, mask={160:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=14, i=12, mask={160:0}] [L26] i++ VAL [b={158:0}, i=13, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=13, mask={160:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=14, b={160:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=14, b={160:0}, b={160:0}, i=0, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={160:0}, b={160:0}, i=0, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={160:0}, b={160:0}, i=0, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={160:0}, b={160:0}, b[i]=129, i=0, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={160:0}, b={160:0}, i=1, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={160:0}, b={160:0}, i=1, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={160:0}, b={160:0}, i=1, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={160:0}, b={160:0}, b[i]=144, i=1, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={160:0}, b={160:0}, i=2, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={160:0}, b={160:0}, i=2, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={160:0}, b={160:0}, i=2, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={160:0}, b={160:0}, b[i]=134, i=2, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={160:0}, b={160:0}, i=3, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={160:0}, b={160:0}, i=3, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={160:0}, b={160:0}, i=3, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={160:0}, b={160:0}, b[i]=132, i=3, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={160:0}, b={160:0}, i=4, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={160:0}, b={160:0}, i=4, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={160:0}, b={160:0}, i=4, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={160:0}, b={160:0}, b[i]=141, i=4, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={160:0}, b={160:0}, i=5, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={160:0}, b={160:0}, i=5, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={160:0}, b={160:0}, i=5, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={160:0}, b={160:0}, b[i]=146, i=5, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={160:0}, b={160:0}, i=6, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={160:0}, b={160:0}, i=6, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={160:0}, b={160:0}, i=6, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={160:0}, b={160:0}, b[i]=142, i=6, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={160:0}, b={160:0}, i=7, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={160:0}, b={160:0}, i=7, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={160:0}, b={160:0}, i=7, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={160:0}, b={160:0}, b[i]=157, i=7, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={160:0}, b={160:0}, i=8, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={160:0}, b={160:0}, i=8, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={160:0}, b={160:0}, i=8, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={160:0}, b={160:0}, b[i]=145, i=8, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={160:0}, b={160:0}, i=9, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={160:0}, b={160:0}, i=9, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={160:0}, b={160:0}, i=9, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={160:0}, b={160:0}, b[i]=153, i=9, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={160:0}, b={160:0}, i=10, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={160:0}, b={160:0}, i=10, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={160:0}, b={160:0}, i=10, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={160:0}, b={160:0}, b[i]=149, i=10, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={160:0}, b={160:0}, i=11, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={160:0}, b={160:0}, i=11, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={160:0}, b={160:0}, i=11, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={160:0}, b={160:0}, b[i]=135, i=11, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={160:0}, b={160:0}, i=12, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={160:0}, b={160:0}, i=12, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={160:0}, b={160:0}, i=12, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={160:0}, b={160:0}, b[i]=139, i=12, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={160:0}, b={160:0}, i=13, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={160:0}, b={160:0}, i=13, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={160:0}, b={160:0}, i=13, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={160:0}, b={160:0}, b[i]=136, i=13, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={160:0}, b={160:0}, i=14, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={160:0}, b={160:0}, i=14, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={160:0}, b={160:0}, i=14, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={160:0}, b={160:0}, b[i]=152, i=14, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={160:0}, b={160:0}, i=15, size=14] [L17] COND FALSE !(i <= size) VAL [\old(size)=14, b={160:0}, b={160:0}, i=15, size=14] [L20] RET return i; VAL [\old(size)=14, \result=15, b={160:0}, b={160:0}, i=15, size=14] [L27] EXPR foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=15, i=13, mask={160:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=15, i=13, mask={160:0}] [L26] i++ VAL [b={158:0}, i=14, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=14, mask={160:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=15, b={160:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=15, b={160:0}, b={160:0}, i=0, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={160:0}, b={160:0}, i=0, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={160:0}, b={160:0}, i=0, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={160:0}, b={160:0}, b[i]=129, i=0, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={160:0}, b={160:0}, i=1, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={160:0}, b={160:0}, i=1, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={160:0}, b={160:0}, i=1, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={160:0}, b={160:0}, b[i]=144, i=1, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={160:0}, b={160:0}, i=2, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={160:0}, b={160:0}, i=2, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={160:0}, b={160:0}, i=2, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={160:0}, b={160:0}, b[i]=134, i=2, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={160:0}, b={160:0}, i=3, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={160:0}, b={160:0}, i=3, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={160:0}, b={160:0}, i=3, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={160:0}, b={160:0}, b[i]=132, i=3, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={160:0}, b={160:0}, i=4, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={160:0}, b={160:0}, i=4, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={160:0}, b={160:0}, i=4, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={160:0}, b={160:0}, b[i]=141, i=4, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={160:0}, b={160:0}, i=5, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={160:0}, b={160:0}, i=5, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={160:0}, b={160:0}, i=5, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={160:0}, b={160:0}, b[i]=146, i=5, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={160:0}, b={160:0}, i=6, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={160:0}, b={160:0}, i=6, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={160:0}, b={160:0}, i=6, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={160:0}, b={160:0}, b[i]=142, i=6, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={160:0}, b={160:0}, i=7, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={160:0}, b={160:0}, i=7, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={160:0}, b={160:0}, i=7, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={160:0}, b={160:0}, b[i]=157, i=7, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={160:0}, b={160:0}, i=8, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={160:0}, b={160:0}, i=8, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={160:0}, b={160:0}, i=8, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={160:0}, b={160:0}, b[i]=145, i=8, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={160:0}, b={160:0}, i=9, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={160:0}, b={160:0}, i=9, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={160:0}, b={160:0}, i=9, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={160:0}, b={160:0}, b[i]=153, i=9, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={160:0}, b={160:0}, i=10, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={160:0}, b={160:0}, i=10, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={160:0}, b={160:0}, i=10, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={160:0}, b={160:0}, b[i]=149, i=10, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={160:0}, b={160:0}, i=11, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={160:0}, b={160:0}, i=11, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={160:0}, b={160:0}, i=11, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={160:0}, b={160:0}, b[i]=135, i=11, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={160:0}, b={160:0}, i=12, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={160:0}, b={160:0}, i=12, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={160:0}, b={160:0}, i=12, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={160:0}, b={160:0}, b[i]=139, i=12, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={160:0}, b={160:0}, i=13, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={160:0}, b={160:0}, i=13, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={160:0}, b={160:0}, i=13, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={160:0}, b={160:0}, b[i]=136, i=13, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={160:0}, b={160:0}, i=14, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={160:0}, b={160:0}, i=14, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={160:0}, b={160:0}, i=14, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={160:0}, b={160:0}, b[i]=152, i=14, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={160:0}, b={160:0}, i=15, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={160:0}, b={160:0}, i=15, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={160:0}, b={160:0}, i=15, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={160:0}, b={160:0}, b[i]=150, i=15, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={160:0}, b={160:0}, i=16, size=15] [L17] COND FALSE !(i <= size) VAL [\old(size)=15, b={160:0}, b={160:0}, i=16, size=15] [L20] RET return i; VAL [\old(size)=15, \result=16, b={160:0}, b={160:0}, i=16, size=15] [L27] EXPR foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=16, i=14, mask={160:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=16, i=14, mask={160:0}] [L26] i++ VAL [b={158:0}, i=15, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=15, mask={160:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=16, b={160:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=16, b={160:0}, b={160:0}, i=0, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={160:0}, b={160:0}, i=0, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={160:0}, b={160:0}, i=0, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={160:0}, b={160:0}, b[i]=129, i=0, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={160:0}, b={160:0}, i=1, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={160:0}, b={160:0}, i=1, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={160:0}, b={160:0}, i=1, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={160:0}, b={160:0}, b[i]=144, i=1, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={160:0}, b={160:0}, i=2, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={160:0}, b={160:0}, i=2, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={160:0}, b={160:0}, i=2, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={160:0}, b={160:0}, b[i]=134, i=2, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={160:0}, b={160:0}, i=3, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={160:0}, b={160:0}, i=3, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={160:0}, b={160:0}, i=3, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={160:0}, b={160:0}, b[i]=132, i=3, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={160:0}, b={160:0}, i=4, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={160:0}, b={160:0}, i=4, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={160:0}, b={160:0}, i=4, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={160:0}, b={160:0}, b[i]=141, i=4, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={160:0}, b={160:0}, i=5, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={160:0}, b={160:0}, i=5, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={160:0}, b={160:0}, i=5, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={160:0}, b={160:0}, b[i]=146, i=5, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={160:0}, b={160:0}, i=6, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={160:0}, b={160:0}, i=6, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={160:0}, b={160:0}, i=6, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={160:0}, b={160:0}, b[i]=142, i=6, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={160:0}, b={160:0}, i=7, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={160:0}, b={160:0}, i=7, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={160:0}, b={160:0}, i=7, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={160:0}, b={160:0}, b[i]=157, i=7, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={160:0}, b={160:0}, i=8, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={160:0}, b={160:0}, i=8, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={160:0}, b={160:0}, i=8, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={160:0}, b={160:0}, b[i]=145, i=8, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={160:0}, b={160:0}, i=9, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={160:0}, b={160:0}, i=9, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={160:0}, b={160:0}, i=9, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={160:0}, b={160:0}, b[i]=153, i=9, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={160:0}, b={160:0}, i=10, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={160:0}, b={160:0}, i=10, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={160:0}, b={160:0}, i=10, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={160:0}, b={160:0}, b[i]=149, i=10, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={160:0}, b={160:0}, i=11, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={160:0}, b={160:0}, i=11, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={160:0}, b={160:0}, i=11, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={160:0}, b={160:0}, b[i]=135, i=11, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={160:0}, b={160:0}, i=12, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={160:0}, b={160:0}, i=12, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={160:0}, b={160:0}, i=12, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={160:0}, b={160:0}, b[i]=139, i=12, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={160:0}, b={160:0}, i=13, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={160:0}, b={160:0}, i=13, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={160:0}, b={160:0}, i=13, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={160:0}, b={160:0}, b[i]=136, i=13, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={160:0}, b={160:0}, i=14, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={160:0}, b={160:0}, i=14, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={160:0}, b={160:0}, i=14, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={160:0}, b={160:0}, b[i]=152, i=14, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={160:0}, b={160:0}, i=15, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={160:0}, b={160:0}, i=15, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={160:0}, b={160:0}, i=15, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={160:0}, b={160:0}, b[i]=150, i=15, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={160:0}, b={160:0}, i=16, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={160:0}, b={160:0}, i=16, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={160:0}, b={160:0}, i=16, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={160:0}, b={160:0}, b[i]=156, i=16, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={160:0}, b={160:0}, i=17, size=16] [L17] COND FALSE !(i <= size) VAL [\old(size)=16, b={160:0}, b={160:0}, i=17, size=16] [L20] RET return i; VAL [\old(size)=16, \result=17, b={160:0}, b={160:0}, i=17, size=16] [L27] EXPR foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=17, i=15, mask={160:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=17, i=15, mask={160:0}] [L26] i++ VAL [b={158:0}, i=16, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=16, mask={160:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=17, b={160:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=17, b={160:0}, b={160:0}, i=0, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={160:0}, b={160:0}, i=0, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={160:0}, b={160:0}, i=0, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={160:0}, b={160:0}, b[i]=129, i=0, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={160:0}, b={160:0}, i=1, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={160:0}, b={160:0}, i=1, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={160:0}, b={160:0}, i=1, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={160:0}, b={160:0}, b[i]=144, i=1, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={160:0}, b={160:0}, i=2, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={160:0}, b={160:0}, i=2, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={160:0}, b={160:0}, i=2, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={160:0}, b={160:0}, b[i]=134, i=2, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={160:0}, b={160:0}, i=3, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={160:0}, b={160:0}, i=3, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={160:0}, b={160:0}, i=3, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={160:0}, b={160:0}, b[i]=132, i=3, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={160:0}, b={160:0}, i=4, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={160:0}, b={160:0}, i=4, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={160:0}, b={160:0}, i=4, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={160:0}, b={160:0}, b[i]=141, i=4, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={160:0}, b={160:0}, i=5, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={160:0}, b={160:0}, i=5, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={160:0}, b={160:0}, i=5, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={160:0}, b={160:0}, b[i]=146, i=5, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={160:0}, b={160:0}, i=6, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={160:0}, b={160:0}, i=6, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={160:0}, b={160:0}, i=6, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={160:0}, b={160:0}, b[i]=142, i=6, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={160:0}, b={160:0}, i=7, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={160:0}, b={160:0}, i=7, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={160:0}, b={160:0}, i=7, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={160:0}, b={160:0}, b[i]=157, i=7, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={160:0}, b={160:0}, i=8, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={160:0}, b={160:0}, i=8, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={160:0}, b={160:0}, i=8, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={160:0}, b={160:0}, b[i]=145, i=8, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={160:0}, b={160:0}, i=9, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={160:0}, b={160:0}, i=9, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={160:0}, b={160:0}, i=9, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={160:0}, b={160:0}, b[i]=153, i=9, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={160:0}, b={160:0}, i=10, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={160:0}, b={160:0}, i=10, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={160:0}, b={160:0}, i=10, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={160:0}, b={160:0}, b[i]=149, i=10, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={160:0}, b={160:0}, i=11, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={160:0}, b={160:0}, i=11, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={160:0}, b={160:0}, i=11, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={160:0}, b={160:0}, b[i]=135, i=11, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={160:0}, b={160:0}, i=12, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={160:0}, b={160:0}, i=12, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={160:0}, b={160:0}, i=12, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={160:0}, b={160:0}, b[i]=139, i=12, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={160:0}, b={160:0}, i=13, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={160:0}, b={160:0}, i=13, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={160:0}, b={160:0}, i=13, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={160:0}, b={160:0}, b[i]=136, i=13, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={160:0}, b={160:0}, i=14, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={160:0}, b={160:0}, i=14, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={160:0}, b={160:0}, i=14, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={160:0}, b={160:0}, b[i]=152, i=14, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={160:0}, b={160:0}, i=15, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={160:0}, b={160:0}, i=15, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={160:0}, b={160:0}, i=15, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={160:0}, b={160:0}, b[i]=150, i=15, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={160:0}, b={160:0}, i=16, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={160:0}, b={160:0}, i=16, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={160:0}, b={160:0}, i=16, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={160:0}, b={160:0}, b[i]=156, i=16, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={160:0}, b={160:0}, i=17, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={160:0}, b={160:0}, i=17, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={160:0}, b={160:0}, i=17, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={160:0}, b={160:0}, b[i]=161, i=17, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={160:0}, b={160:0}, i=18, size=17] [L17] COND FALSE !(i <= size) VAL [\old(size)=17, b={160:0}, b={160:0}, i=18, size=17] [L20] RET return i; VAL [\old(size)=17, \result=18, b={160:0}, b={160:0}, i=18, size=17] [L27] EXPR foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=18, i=16, mask={160:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=18, i=16, mask={160:0}] [L26] i++ VAL [b={158:0}, i=17, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=17, mask={160:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=18, b={160:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=18, b={160:0}, b={160:0}, i=0, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={160:0}, b={160:0}, i=0, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={160:0}, b={160:0}, i=0, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={160:0}, b={160:0}, b[i]=129, i=0, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={160:0}, b={160:0}, i=1, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={160:0}, b={160:0}, i=1, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={160:0}, b={160:0}, i=1, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={160:0}, b={160:0}, b[i]=144, i=1, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={160:0}, b={160:0}, i=2, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={160:0}, b={160:0}, i=2, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={160:0}, b={160:0}, i=2, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={160:0}, b={160:0}, b[i]=134, i=2, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={160:0}, b={160:0}, i=3, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={160:0}, b={160:0}, i=3, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={160:0}, b={160:0}, i=3, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={160:0}, b={160:0}, b[i]=132, i=3, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={160:0}, b={160:0}, i=4, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={160:0}, b={160:0}, i=4, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={160:0}, b={160:0}, i=4, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={160:0}, b={160:0}, b[i]=141, i=4, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={160:0}, b={160:0}, i=5, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={160:0}, b={160:0}, i=5, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={160:0}, b={160:0}, i=5, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={160:0}, b={160:0}, b[i]=146, i=5, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={160:0}, b={160:0}, i=6, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={160:0}, b={160:0}, i=6, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={160:0}, b={160:0}, i=6, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={160:0}, b={160:0}, b[i]=142, i=6, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={160:0}, b={160:0}, i=7, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={160:0}, b={160:0}, i=7, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={160:0}, b={160:0}, i=7, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={160:0}, b={160:0}, b[i]=157, i=7, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={160:0}, b={160:0}, i=8, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={160:0}, b={160:0}, i=8, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={160:0}, b={160:0}, i=8, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={160:0}, b={160:0}, b[i]=145, i=8, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={160:0}, b={160:0}, i=9, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={160:0}, b={160:0}, i=9, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={160:0}, b={160:0}, i=9, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={160:0}, b={160:0}, b[i]=153, i=9, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={160:0}, b={160:0}, i=10, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={160:0}, b={160:0}, i=10, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={160:0}, b={160:0}, i=10, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={160:0}, b={160:0}, b[i]=149, i=10, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={160:0}, b={160:0}, i=11, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={160:0}, b={160:0}, i=11, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={160:0}, b={160:0}, i=11, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={160:0}, b={160:0}, b[i]=135, i=11, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={160:0}, b={160:0}, i=12, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={160:0}, b={160:0}, i=12, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={160:0}, b={160:0}, i=12, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={160:0}, b={160:0}, b[i]=139, i=12, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={160:0}, b={160:0}, i=13, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={160:0}, b={160:0}, i=13, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={160:0}, b={160:0}, i=13, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={160:0}, b={160:0}, b[i]=136, i=13, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={160:0}, b={160:0}, i=14, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={160:0}, b={160:0}, i=14, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={160:0}, b={160:0}, i=14, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={160:0}, b={160:0}, b[i]=152, i=14, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={160:0}, b={160:0}, i=15, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={160:0}, b={160:0}, i=15, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={160:0}, b={160:0}, i=15, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={160:0}, b={160:0}, b[i]=150, i=15, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={160:0}, b={160:0}, i=16, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={160:0}, b={160:0}, i=16, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={160:0}, b={160:0}, i=16, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={160:0}, b={160:0}, b[i]=156, i=16, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={160:0}, b={160:0}, i=17, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={160:0}, b={160:0}, i=17, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={160:0}, b={160:0}, i=17, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={160:0}, b={160:0}, b[i]=161, i=17, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={160:0}, b={160:0}, i=18, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={160:0}, b={160:0}, i=18, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={160:0}, b={160:0}, i=18, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={160:0}, b={160:0}, b[i]=154, i=18, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={160:0}, b={160:0}, i=19, size=18] [L17] COND FALSE !(i <= size) VAL [\old(size)=18, b={160:0}, b={160:0}, i=19, size=18] [L20] RET return i; VAL [\old(size)=18, \result=19, b={160:0}, b={160:0}, i=19, size=18] [L27] EXPR foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=19, i=17, mask={160:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=19, i=17, mask={160:0}] [L26] i++ VAL [b={158:0}, i=18, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=18, mask={160:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=19, b={160:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=19, b={160:0}, b={160:0}, i=0, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={160:0}, b={160:0}, i=0, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=0, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=129, i=0, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=1, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={160:0}, b={160:0}, i=1, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=1, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=144, i=1, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=2, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={160:0}, b={160:0}, i=2, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=2, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=134, i=2, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=3, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={160:0}, b={160:0}, i=3, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=3, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=132, i=3, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=4, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={160:0}, b={160:0}, i=4, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=4, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=141, i=4, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=5, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={160:0}, b={160:0}, i=5, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=5, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=146, i=5, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=6, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={160:0}, b={160:0}, i=6, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=6, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=142, i=6, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=7, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={160:0}, b={160:0}, i=7, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=7, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=157, i=7, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=8, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={160:0}, b={160:0}, i=8, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=8, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=145, i=8, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=9, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={160:0}, b={160:0}, i=9, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=9, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=153, i=9, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=10, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={160:0}, b={160:0}, i=10, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=10, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=149, i=10, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=11, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={160:0}, b={160:0}, i=11, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=11, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=135, i=11, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=12, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={160:0}, b={160:0}, i=12, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=12, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=139, i=12, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=13, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={160:0}, b={160:0}, i=13, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=13, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=136, i=13, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=14, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={160:0}, b={160:0}, i=14, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=14, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=152, i=14, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=15, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={160:0}, b={160:0}, i=15, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=15, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=150, i=15, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=16, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={160:0}, b={160:0}, i=16, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=16, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=156, i=16, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=17, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={160:0}, b={160:0}, i=17, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=17, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=161, i=17, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=18, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={160:0}, b={160:0}, i=18, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=18, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=154, i=18, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=19, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={160:0}, b={160:0}, i=19, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={160:0}, b={160:0}, i=19, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={160:0}, b={160:0}, b[i]=162, i=19, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={160:0}, b={160:0}, i=20, size=19] [L17] COND FALSE !(i <= size) VAL [\old(size)=19, b={160:0}, b={160:0}, i=20, size=19] [L20] RET return i; VAL [\old(size)=19, \result=20, b={160:0}, b={160:0}, i=20, size=19] [L27] EXPR foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=20, i=18, mask={160:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=20, i=18, mask={160:0}] [L26] i++ VAL [b={158:0}, i=19, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=19, mask={160:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=20, b={160:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=20, b={160:0}, b={160:0}, i=0, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={160:0}, b={160:0}, i=0, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=0, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=129, i=0, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=1, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={160:0}, b={160:0}, i=1, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=1, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=144, i=1, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=2, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={160:0}, b={160:0}, i=2, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=2, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=134, i=2, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=3, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={160:0}, b={160:0}, i=3, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=3, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=132, i=3, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=4, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={160:0}, b={160:0}, i=4, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=4, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=141, i=4, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=5, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={160:0}, b={160:0}, i=5, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=5, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=146, i=5, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=6, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={160:0}, b={160:0}, i=6, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=6, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=142, i=6, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=7, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={160:0}, b={160:0}, i=7, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=7, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=157, i=7, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=8, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={160:0}, b={160:0}, i=8, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=8, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=145, i=8, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=9, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={160:0}, b={160:0}, i=9, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=9, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=153, i=9, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=10, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={160:0}, b={160:0}, i=10, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=10, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=149, i=10, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=11, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={160:0}, b={160:0}, i=11, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=11, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=135, i=11, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=12, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={160:0}, b={160:0}, i=12, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=12, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=139, i=12, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=13, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={160:0}, b={160:0}, i=13, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=13, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=136, i=13, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=14, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={160:0}, b={160:0}, i=14, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=14, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=152, i=14, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=15, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={160:0}, b={160:0}, i=15, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=15, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=150, i=15, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=16, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={160:0}, b={160:0}, i=16, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=16, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=156, i=16, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=17, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={160:0}, b={160:0}, i=17, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=17, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=161, i=17, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=18, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={160:0}, b={160:0}, i=18, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=18, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=154, i=18, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=19, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={160:0}, b={160:0}, i=19, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=19, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=162, i=19, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=20, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={160:0}, b={160:0}, i=20, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={160:0}, b={160:0}, i=20, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={160:0}, b={160:0}, b[i]=148, i=20, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={160:0}, b={160:0}, i=21, size=20] [L17] COND FALSE !(i <= size) VAL [\old(size)=20, b={160:0}, b={160:0}, i=21, size=20] [L20] RET return i; VAL [\old(size)=20, \result=21, b={160:0}, b={160:0}, i=21, size=20] [L27] EXPR foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=21, i=19, mask={160:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=21, i=19, mask={160:0}] [L26] i++ VAL [b={158:0}, i=20, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=20, mask={160:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=21, b={160:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=21, b={160:0}, b={160:0}, i=0, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={160:0}, b={160:0}, i=0, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=0, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=129, i=0, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=1, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={160:0}, b={160:0}, i=1, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=1, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=144, i=1, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=2, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={160:0}, b={160:0}, i=2, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=2, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=134, i=2, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=3, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={160:0}, b={160:0}, i=3, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=3, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=132, i=3, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=4, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={160:0}, b={160:0}, i=4, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=4, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=141, i=4, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=5, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={160:0}, b={160:0}, i=5, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=5, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=146, i=5, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=6, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={160:0}, b={160:0}, i=6, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=6, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=142, i=6, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=7, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={160:0}, b={160:0}, i=7, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=7, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=157, i=7, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=8, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={160:0}, b={160:0}, i=8, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=8, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=145, i=8, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=9, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={160:0}, b={160:0}, i=9, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=9, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=153, i=9, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=10, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={160:0}, b={160:0}, i=10, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=10, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=149, i=10, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=11, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={160:0}, b={160:0}, i=11, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=11, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=135, i=11, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=12, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={160:0}, b={160:0}, i=12, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=12, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=139, i=12, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=13, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={160:0}, b={160:0}, i=13, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=13, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=136, i=13, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=14, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={160:0}, b={160:0}, i=14, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=14, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=152, i=14, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=15, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={160:0}, b={160:0}, i=15, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=15, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=150, i=15, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=16, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={160:0}, b={160:0}, i=16, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=16, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=156, i=16, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=17, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={160:0}, b={160:0}, i=17, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=17, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=161, i=17, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=18, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={160:0}, b={160:0}, i=18, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=18, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=154, i=18, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=19, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={160:0}, b={160:0}, i=19, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=19, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=162, i=19, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=20, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={160:0}, b={160:0}, i=20, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=20, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=148, i=20, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=21, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={160:0}, b={160:0}, i=21, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={160:0}, b={160:0}, i=21, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={160:0}, b={160:0}, b[i]=137, i=21, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={160:0}, b={160:0}, i=22, size=21] [L17] COND FALSE !(i <= size) VAL [\old(size)=21, b={160:0}, b={160:0}, i=22, size=21] [L20] RET return i; VAL [\old(size)=21, \result=22, b={160:0}, b={160:0}, i=22, size=21] [L27] EXPR foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=22, i=20, mask={160:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=22, i=20, mask={160:0}] [L26] i++ VAL [b={158:0}, i=21, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=21, mask={160:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=22, b={160:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=22, b={160:0}, b={160:0}, i=0, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={160:0}, b={160:0}, i=0, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=0, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=129, i=0, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=1, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={160:0}, b={160:0}, i=1, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=1, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=144, i=1, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=2, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={160:0}, b={160:0}, i=2, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=2, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=134, i=2, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=3, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={160:0}, b={160:0}, i=3, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=3, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=132, i=3, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=4, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={160:0}, b={160:0}, i=4, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=4, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=141, i=4, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=5, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={160:0}, b={160:0}, i=5, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=5, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=146, i=5, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=6, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={160:0}, b={160:0}, i=6, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=6, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=142, i=6, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=7, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={160:0}, b={160:0}, i=7, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=7, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=157, i=7, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=8, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={160:0}, b={160:0}, i=8, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=8, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=145, i=8, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=9, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={160:0}, b={160:0}, i=9, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=9, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=153, i=9, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=10, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={160:0}, b={160:0}, i=10, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=10, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=149, i=10, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=11, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={160:0}, b={160:0}, i=11, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=11, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=135, i=11, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=12, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={160:0}, b={160:0}, i=12, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=12, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=139, i=12, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=13, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={160:0}, b={160:0}, i=13, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=13, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=136, i=13, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=14, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={160:0}, b={160:0}, i=14, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=14, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=152, i=14, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=15, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={160:0}, b={160:0}, i=15, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=15, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=150, i=15, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=16, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={160:0}, b={160:0}, i=16, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=16, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=156, i=16, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=17, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={160:0}, b={160:0}, i=17, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=17, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=161, i=17, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=18, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={160:0}, b={160:0}, i=18, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=18, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=154, i=18, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=19, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={160:0}, b={160:0}, i=19, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=19, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=162, i=19, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=20, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={160:0}, b={160:0}, i=20, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=20, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=148, i=20, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=21, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={160:0}, b={160:0}, i=21, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=21, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=137, i=21, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=22, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={160:0}, b={160:0}, i=22, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={160:0}, b={160:0}, i=22, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={160:0}, b={160:0}, b[i]=151, i=22, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={160:0}, b={160:0}, i=23, size=22] [L17] COND FALSE !(i <= size) VAL [\old(size)=22, b={160:0}, b={160:0}, i=23, size=22] [L20] RET return i; VAL [\old(size)=22, \result=23, b={160:0}, b={160:0}, i=23, size=22] [L27] EXPR foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=23, i=21, mask={160:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=23, i=21, mask={160:0}] [L26] i++ VAL [b={158:0}, i=22, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=22, mask={160:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=23, b={160:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=23, b={160:0}, b={160:0}, i=0, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={160:0}, b={160:0}, i=0, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=0, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=129, i=0, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=1, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={160:0}, b={160:0}, i=1, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=1, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=144, i=1, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=2, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={160:0}, b={160:0}, i=2, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=2, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=134, i=2, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=3, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={160:0}, b={160:0}, i=3, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=3, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=132, i=3, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=4, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={160:0}, b={160:0}, i=4, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=4, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=141, i=4, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=5, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={160:0}, b={160:0}, i=5, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=5, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=146, i=5, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=6, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={160:0}, b={160:0}, i=6, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=6, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=142, i=6, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=7, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={160:0}, b={160:0}, i=7, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=7, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=157, i=7, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=8, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={160:0}, b={160:0}, i=8, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=8, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=145, i=8, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=9, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={160:0}, b={160:0}, i=9, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=9, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=153, i=9, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=10, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={160:0}, b={160:0}, i=10, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=10, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=149, i=10, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=11, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={160:0}, b={160:0}, i=11, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=11, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=135, i=11, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=12, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={160:0}, b={160:0}, i=12, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=12, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=139, i=12, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=13, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={160:0}, b={160:0}, i=13, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=13, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=136, i=13, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=14, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={160:0}, b={160:0}, i=14, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=14, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=152, i=14, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=15, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={160:0}, b={160:0}, i=15, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=15, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=150, i=15, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=16, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={160:0}, b={160:0}, i=16, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=16, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=156, i=16, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=17, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={160:0}, b={160:0}, i=17, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=17, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=161, i=17, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=18, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={160:0}, b={160:0}, i=18, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=18, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=154, i=18, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=19, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={160:0}, b={160:0}, i=19, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=19, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=162, i=19, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=20, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={160:0}, b={160:0}, i=20, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=20, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=148, i=20, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=21, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={160:0}, b={160:0}, i=21, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=21, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=137, i=21, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=22, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={160:0}, b={160:0}, i=22, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=22, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=151, i=22, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=23, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={160:0}, b={160:0}, i=23, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={160:0}, b={160:0}, i=23, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={160:0}, b={160:0}, b[i]=163, i=23, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={160:0}, b={160:0}, i=24, size=23] [L17] COND FALSE !(i <= size) VAL [\old(size)=23, b={160:0}, b={160:0}, i=24, size=23] [L20] RET return i; VAL [\old(size)=23, \result=24, b={160:0}, b={160:0}, i=24, size=23] [L27] EXPR foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=24, i=22, mask={160:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=24, i=22, mask={160:0}] [L26] i++ VAL [b={158:0}, i=23, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=23, mask={160:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=24, b={160:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=24, b={160:0}, b={160:0}, i=0, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={160:0}, b={160:0}, i=0, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=0, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=129, i=0, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=1, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={160:0}, b={160:0}, i=1, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=1, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=144, i=1, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=2, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={160:0}, b={160:0}, i=2, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=2, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=134, i=2, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=3, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={160:0}, b={160:0}, i=3, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=3, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=132, i=3, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=4, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={160:0}, b={160:0}, i=4, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=4, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=141, i=4, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=5, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={160:0}, b={160:0}, i=5, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=5, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=146, i=5, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=6, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={160:0}, b={160:0}, i=6, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=6, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=142, i=6, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=7, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={160:0}, b={160:0}, i=7, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=7, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=157, i=7, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=8, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={160:0}, b={160:0}, i=8, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=8, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=145, i=8, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=9, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={160:0}, b={160:0}, i=9, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=9, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=153, i=9, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=10, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={160:0}, b={160:0}, i=10, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=10, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=149, i=10, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=11, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={160:0}, b={160:0}, i=11, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=11, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=135, i=11, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=12, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={160:0}, b={160:0}, i=12, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=12, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=139, i=12, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=13, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={160:0}, b={160:0}, i=13, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=13, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=136, i=13, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=14, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={160:0}, b={160:0}, i=14, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=14, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=152, i=14, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=15, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={160:0}, b={160:0}, i=15, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=15, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=150, i=15, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=16, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={160:0}, b={160:0}, i=16, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=16, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=156, i=16, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=17, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={160:0}, b={160:0}, i=17, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=17, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=161, i=17, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=18, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={160:0}, b={160:0}, i=18, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=18, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=154, i=18, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=19, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={160:0}, b={160:0}, i=19, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=19, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=162, i=19, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=20, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={160:0}, b={160:0}, i=20, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=20, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=148, i=20, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=21, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={160:0}, b={160:0}, i=21, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=21, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=137, i=21, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=22, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={160:0}, b={160:0}, i=22, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=22, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=151, i=22, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=23, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={160:0}, b={160:0}, i=23, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=23, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=163, i=23, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=24, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={160:0}, b={160:0}, i=24, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={160:0}, b={160:0}, i=24, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={160:0}, b={160:0}, b[i]=131, i=24, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={160:0}, b={160:0}, i=25, size=24] [L17] COND FALSE !(i <= size) VAL [\old(size)=24, b={160:0}, b={160:0}, i=25, size=24] [L20] RET return i; VAL [\old(size)=24, \result=25, b={160:0}, b={160:0}, i=25, size=24] [L27] EXPR foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=25, i=23, mask={160:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=25, i=23, mask={160:0}] [L26] i++ VAL [b={158:0}, i=24, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=24, mask={160:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=25, b={160:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=25, b={160:0}, b={160:0}, i=0, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={160:0}, b={160:0}, i=0, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=0, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=129, i=0, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=1, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={160:0}, b={160:0}, i=1, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=1, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=144, i=1, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=2, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={160:0}, b={160:0}, i=2, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=2, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=134, i=2, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=3, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={160:0}, b={160:0}, i=3, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=3, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=132, i=3, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=4, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={160:0}, b={160:0}, i=4, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=4, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=141, i=4, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=5, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={160:0}, b={160:0}, i=5, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=5, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=146, i=5, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=6, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={160:0}, b={160:0}, i=6, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=6, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=142, i=6, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=7, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={160:0}, b={160:0}, i=7, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=7, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=157, i=7, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=8, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={160:0}, b={160:0}, i=8, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=8, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=145, i=8, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=9, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={160:0}, b={160:0}, i=9, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=9, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=153, i=9, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=10, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={160:0}, b={160:0}, i=10, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=10, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=149, i=10, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=11, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={160:0}, b={160:0}, i=11, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=11, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=135, i=11, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=12, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={160:0}, b={160:0}, i=12, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=12, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=139, i=12, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=13, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={160:0}, b={160:0}, i=13, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=13, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=136, i=13, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=14, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={160:0}, b={160:0}, i=14, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=14, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=152, i=14, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=15, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={160:0}, b={160:0}, i=15, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=15, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=150, i=15, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=16, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={160:0}, b={160:0}, i=16, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=16, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=156, i=16, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=17, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={160:0}, b={160:0}, i=17, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=17, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=161, i=17, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=18, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={160:0}, b={160:0}, i=18, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=18, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=154, i=18, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=19, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={160:0}, b={160:0}, i=19, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=19, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=162, i=19, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=20, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={160:0}, b={160:0}, i=20, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=20, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=148, i=20, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=21, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={160:0}, b={160:0}, i=21, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=21, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=137, i=21, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=22, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={160:0}, b={160:0}, i=22, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=22, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=151, i=22, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=23, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={160:0}, b={160:0}, i=23, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=23, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=163, i=23, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=24, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={160:0}, b={160:0}, i=24, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=24, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=131, i=24, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=25, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={160:0}, b={160:0}, i=25, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={160:0}, b={160:0}, i=25, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={160:0}, b={160:0}, b[i]=133, i=25, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={160:0}, b={160:0}, i=26, size=25] [L17] COND FALSE !(i <= size) VAL [\old(size)=25, b={160:0}, b={160:0}, i=26, size=25] [L20] RET return i; VAL [\old(size)=25, \result=26, b={160:0}, b={160:0}, i=26, size=25] [L27] EXPR foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=26, i=24, mask={160:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=26, i=24, mask={160:0}] [L26] i++ VAL [b={158:0}, i=25, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=25, mask={160:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=26, b={160:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=26, b={160:0}, b={160:0}, i=0, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={160:0}, b={160:0}, i=0, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=0, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=129, i=0, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=1, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={160:0}, b={160:0}, i=1, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=1, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=144, i=1, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=2, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={160:0}, b={160:0}, i=2, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=2, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=134, i=2, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=3, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={160:0}, b={160:0}, i=3, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=3, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=132, i=3, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=4, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={160:0}, b={160:0}, i=4, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=4, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=141, i=4, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=5, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={160:0}, b={160:0}, i=5, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=5, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=146, i=5, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=6, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={160:0}, b={160:0}, i=6, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=6, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=142, i=6, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=7, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={160:0}, b={160:0}, i=7, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=7, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=157, i=7, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=8, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={160:0}, b={160:0}, i=8, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=8, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=145, i=8, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=9, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={160:0}, b={160:0}, i=9, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=9, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=153, i=9, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=10, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={160:0}, b={160:0}, i=10, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=10, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=149, i=10, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=11, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={160:0}, b={160:0}, i=11, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=11, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=135, i=11, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=12, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={160:0}, b={160:0}, i=12, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=12, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=139, i=12, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=13, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={160:0}, b={160:0}, i=13, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=13, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=136, i=13, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=14, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={160:0}, b={160:0}, i=14, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=14, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=152, i=14, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=15, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={160:0}, b={160:0}, i=15, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=15, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=150, i=15, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=16, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={160:0}, b={160:0}, i=16, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=16, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=156, i=16, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=17, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={160:0}, b={160:0}, i=17, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=17, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=161, i=17, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=18, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={160:0}, b={160:0}, i=18, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=18, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=154, i=18, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=19, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={160:0}, b={160:0}, i=19, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=19, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=162, i=19, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=20, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={160:0}, b={160:0}, i=20, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=20, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=148, i=20, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=21, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={160:0}, b={160:0}, i=21, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=21, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=137, i=21, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=22, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={160:0}, b={160:0}, i=22, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=22, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=151, i=22, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=23, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={160:0}, b={160:0}, i=23, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=23, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=163, i=23, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=24, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={160:0}, b={160:0}, i=24, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=24, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=131, i=24, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=25, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={160:0}, b={160:0}, i=25, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=25, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=133, i=25, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=26, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={160:0}, b={160:0}, i=26, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={160:0}, b={160:0}, i=26, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={160:0}, b={160:0}, b[i]=130, i=26, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={160:0}, b={160:0}, i=27, size=26] [L17] COND FALSE !(i <= size) VAL [\old(size)=26, b={160:0}, b={160:0}, i=27, size=26] [L20] RET return i; VAL [\old(size)=26, \result=27, b={160:0}, b={160:0}, i=27, size=26] [L27] EXPR foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=27, i=25, mask={160:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=27, i=25, mask={160:0}] [L26] i++ VAL [b={158:0}, i=26, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=26, mask={160:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=27, b={160:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=27, b={160:0}, b={160:0}, i=0, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={160:0}, b={160:0}, i=0, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=0, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=129, i=0, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=1, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={160:0}, b={160:0}, i=1, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=1, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=144, i=1, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=2, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={160:0}, b={160:0}, i=2, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=2, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=134, i=2, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=3, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={160:0}, b={160:0}, i=3, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=3, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=132, i=3, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=4, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={160:0}, b={160:0}, i=4, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=4, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=141, i=4, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=5, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={160:0}, b={160:0}, i=5, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=5, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=146, i=5, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=6, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={160:0}, b={160:0}, i=6, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=6, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=142, i=6, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=7, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={160:0}, b={160:0}, i=7, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=7, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=157, i=7, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=8, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={160:0}, b={160:0}, i=8, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=8, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=145, i=8, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=9, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={160:0}, b={160:0}, i=9, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=9, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=153, i=9, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=10, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={160:0}, b={160:0}, i=10, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=10, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=149, i=10, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=11, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={160:0}, b={160:0}, i=11, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=11, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=135, i=11, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=12, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={160:0}, b={160:0}, i=12, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=12, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=139, i=12, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=13, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={160:0}, b={160:0}, i=13, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=13, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=136, i=13, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=14, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={160:0}, b={160:0}, i=14, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=14, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=152, i=14, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=15, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={160:0}, b={160:0}, i=15, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=15, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=150, i=15, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=16, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={160:0}, b={160:0}, i=16, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=16, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=156, i=16, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=17, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={160:0}, b={160:0}, i=17, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=17, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=161, i=17, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=18, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={160:0}, b={160:0}, i=18, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=18, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=154, i=18, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=19, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={160:0}, b={160:0}, i=19, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=19, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=162, i=19, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=20, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={160:0}, b={160:0}, i=20, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=20, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=148, i=20, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=21, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={160:0}, b={160:0}, i=21, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=21, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=137, i=21, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=22, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={160:0}, b={160:0}, i=22, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=22, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=151, i=22, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=23, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={160:0}, b={160:0}, i=23, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=23, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=163, i=23, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=24, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={160:0}, b={160:0}, i=24, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=24, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=131, i=24, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=25, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={160:0}, b={160:0}, i=25, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=25, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=133, i=25, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=26, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={160:0}, b={160:0}, i=26, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=26, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=130, i=26, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=27, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={160:0}, b={160:0}, i=27, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={160:0}, b={160:0}, i=27, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={160:0}, b={160:0}, b[i]=138, i=27, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={160:0}, b={160:0}, i=28, size=27] [L17] COND FALSE !(i <= size) VAL [\old(size)=27, b={160:0}, b={160:0}, i=28, size=27] [L20] RET return i; VAL [\old(size)=27, \result=28, b={160:0}, b={160:0}, i=28, size=27] [L27] EXPR foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=28, i=26, mask={160:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=28, i=26, mask={160:0}] [L26] i++ VAL [b={158:0}, i=27, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=27, mask={160:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=28, b={160:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=28, b={160:0}, b={160:0}, i=0, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={160:0}, b={160:0}, i=0, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=0, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=129, i=0, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=1, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={160:0}, b={160:0}, i=1, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=1, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=144, i=1, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=2, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={160:0}, b={160:0}, i=2, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=2, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=134, i=2, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=3, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={160:0}, b={160:0}, i=3, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=3, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=132, i=3, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=4, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={160:0}, b={160:0}, i=4, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=4, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=141, i=4, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=5, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={160:0}, b={160:0}, i=5, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=5, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=146, i=5, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=6, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={160:0}, b={160:0}, i=6, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=6, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=142, i=6, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=7, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={160:0}, b={160:0}, i=7, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=7, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=157, i=7, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=8, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={160:0}, b={160:0}, i=8, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=8, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=145, i=8, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=9, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={160:0}, b={160:0}, i=9, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=9, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=153, i=9, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=10, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={160:0}, b={160:0}, i=10, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=10, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=149, i=10, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=11, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={160:0}, b={160:0}, i=11, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=11, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=135, i=11, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=12, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={160:0}, b={160:0}, i=12, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=12, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=139, i=12, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=13, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={160:0}, b={160:0}, i=13, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=13, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=136, i=13, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=14, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={160:0}, b={160:0}, i=14, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=14, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=152, i=14, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=15, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={160:0}, b={160:0}, i=15, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=15, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=150, i=15, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=16, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={160:0}, b={160:0}, i=16, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=16, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=156, i=16, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=17, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={160:0}, b={160:0}, i=17, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=17, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=161, i=17, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=18, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={160:0}, b={160:0}, i=18, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=18, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=154, i=18, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=19, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={160:0}, b={160:0}, i=19, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=19, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=162, i=19, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=20, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={160:0}, b={160:0}, i=20, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=20, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=148, i=20, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=21, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={160:0}, b={160:0}, i=21, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=21, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=137, i=21, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=22, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={160:0}, b={160:0}, i=22, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=22, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=151, i=22, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=23, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={160:0}, b={160:0}, i=23, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=23, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=163, i=23, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=24, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={160:0}, b={160:0}, i=24, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=24, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=131, i=24, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=25, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={160:0}, b={160:0}, i=25, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=25, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=133, i=25, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=26, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={160:0}, b={160:0}, i=26, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=26, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=130, i=26, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=27, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={160:0}, b={160:0}, i=27, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=27, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=138, i=27, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=28, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={160:0}, b={160:0}, i=28, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={160:0}, b={160:0}, i=28, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={160:0}, b={160:0}, b[i]=143, i=28, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={160:0}, b={160:0}, i=29, size=28] [L17] COND FALSE !(i <= size) VAL [\old(size)=28, b={160:0}, b={160:0}, i=29, size=28] [L20] RET return i; VAL [\old(size)=28, \result=29, b={160:0}, b={160:0}, i=29, size=28] [L27] EXPR foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=29, i=27, mask={160:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=29, i=27, mask={160:0}] [L26] i++ VAL [b={158:0}, i=28, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=28, mask={160:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=29, b={160:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=29, b={160:0}, b={160:0}, i=0, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={160:0}, b={160:0}, i=0, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=0, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=129, i=0, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=1, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={160:0}, b={160:0}, i=1, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=1, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=144, i=1, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=2, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={160:0}, b={160:0}, i=2, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=2, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=134, i=2, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=3, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={160:0}, b={160:0}, i=3, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=3, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=132, i=3, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=4, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={160:0}, b={160:0}, i=4, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=4, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=141, i=4, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=5, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={160:0}, b={160:0}, i=5, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=5, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=146, i=5, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=6, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={160:0}, b={160:0}, i=6, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=6, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=142, i=6, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=7, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={160:0}, b={160:0}, i=7, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=7, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=157, i=7, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=8, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={160:0}, b={160:0}, i=8, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=8, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=145, i=8, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=9, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={160:0}, b={160:0}, i=9, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=9, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=153, i=9, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=10, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={160:0}, b={160:0}, i=10, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=10, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=149, i=10, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=11, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={160:0}, b={160:0}, i=11, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=11, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=135, i=11, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=12, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={160:0}, b={160:0}, i=12, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=12, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=139, i=12, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=13, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={160:0}, b={160:0}, i=13, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=13, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=136, i=13, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=14, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={160:0}, b={160:0}, i=14, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=14, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=152, i=14, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=15, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={160:0}, b={160:0}, i=15, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=15, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=150, i=15, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=16, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={160:0}, b={160:0}, i=16, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=16, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=156, i=16, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=17, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={160:0}, b={160:0}, i=17, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=17, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=161, i=17, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=18, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={160:0}, b={160:0}, i=18, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=18, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=154, i=18, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=19, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={160:0}, b={160:0}, i=19, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=19, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=162, i=19, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=20, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={160:0}, b={160:0}, i=20, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=20, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=148, i=20, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=21, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={160:0}, b={160:0}, i=21, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=21, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=137, i=21, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=22, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={160:0}, b={160:0}, i=22, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=22, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=151, i=22, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=23, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={160:0}, b={160:0}, i=23, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=23, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=163, i=23, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=24, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={160:0}, b={160:0}, i=24, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=24, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=131, i=24, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=25, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={160:0}, b={160:0}, i=25, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=25, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=133, i=25, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=26, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={160:0}, b={160:0}, i=26, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=26, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=130, i=26, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=27, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={160:0}, b={160:0}, i=27, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=27, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=138, i=27, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=28, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={160:0}, b={160:0}, i=28, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=28, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=143, i=28, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=29, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={160:0}, b={160:0}, i=29, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={160:0}, b={160:0}, i=29, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={160:0}, b={160:0}, b[i]=155, i=29, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={160:0}, b={160:0}, i=30, size=29] [L17] COND FALSE !(i <= size) VAL [\old(size)=29, b={160:0}, b={160:0}, i=30, size=29] [L20] RET return i; VAL [\old(size)=29, \result=30, b={160:0}, b={160:0}, i=30, size=29] [L27] EXPR foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=30, i=28, mask={160:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=30, i=28, mask={160:0}] [L26] i++ VAL [b={158:0}, i=29, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=29, mask={160:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=30, b={160:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=30, b={160:0}, b={160:0}, i=0, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={160:0}, b={160:0}, i=0, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=0, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=129, i=0, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=1, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={160:0}, b={160:0}, i=1, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=1, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=144, i=1, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=2, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={160:0}, b={160:0}, i=2, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=2, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=134, i=2, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=3, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={160:0}, b={160:0}, i=3, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=3, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=132, i=3, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=4, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={160:0}, b={160:0}, i=4, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=4, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=141, i=4, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=5, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={160:0}, b={160:0}, i=5, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=5, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=146, i=5, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=6, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={160:0}, b={160:0}, i=6, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=6, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=142, i=6, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=7, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={160:0}, b={160:0}, i=7, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=7, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=157, i=7, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=8, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={160:0}, b={160:0}, i=8, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=8, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=145, i=8, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=9, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={160:0}, b={160:0}, i=9, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=9, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=153, i=9, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=10, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={160:0}, b={160:0}, i=10, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=10, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=149, i=10, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=11, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={160:0}, b={160:0}, i=11, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=11, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=135, i=11, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=12, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={160:0}, b={160:0}, i=12, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=12, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=139, i=12, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=13, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={160:0}, b={160:0}, i=13, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=13, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=136, i=13, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=14, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={160:0}, b={160:0}, i=14, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=14, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=152, i=14, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=15, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={160:0}, b={160:0}, i=15, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=15, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=150, i=15, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=16, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={160:0}, b={160:0}, i=16, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=16, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=156, i=16, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=17, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={160:0}, b={160:0}, i=17, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=17, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=161, i=17, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=18, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={160:0}, b={160:0}, i=18, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=18, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=154, i=18, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=19, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={160:0}, b={160:0}, i=19, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=19, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=162, i=19, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=20, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={160:0}, b={160:0}, i=20, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=20, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=148, i=20, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=21, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={160:0}, b={160:0}, i=21, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=21, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=137, i=21, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=22, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={160:0}, b={160:0}, i=22, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=22, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=151, i=22, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=23, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={160:0}, b={160:0}, i=23, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=23, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=163, i=23, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=24, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={160:0}, b={160:0}, i=24, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=24, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=131, i=24, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=25, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={160:0}, b={160:0}, i=25, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=25, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=133, i=25, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=26, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={160:0}, b={160:0}, i=26, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=26, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=130, i=26, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=27, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={160:0}, b={160:0}, i=27, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=27, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=138, i=27, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=28, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={160:0}, b={160:0}, i=28, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=28, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=143, i=28, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=29, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={160:0}, b={160:0}, i=29, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=29, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=155, i=29, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=30, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={160:0}, b={160:0}, i=30, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={160:0}, b={160:0}, i=30, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={160:0}, b={160:0}, b[i]=164, i=30, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={160:0}, b={160:0}, i=31, size=30] [L17] COND FALSE !(i <= size) VAL [\old(size)=30, b={160:0}, b={160:0}, i=31, size=30] [L20] RET return i; VAL [\old(size)=30, \result=31, b={160:0}, b={160:0}, i=31, size=30] [L27] EXPR foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=31, i=29, mask={160:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=31, i=29, mask={160:0}] [L26] i++ VAL [b={158:0}, i=30, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=30, mask={160:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=31, b={160:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=31, b={160:0}, b={160:0}, i=0, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={160:0}, b={160:0}, i=0, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=0, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=129, i=0, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=1, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={160:0}, b={160:0}, i=1, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=1, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=144, i=1, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=2, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={160:0}, b={160:0}, i=2, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=2, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=134, i=2, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=3, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={160:0}, b={160:0}, i=3, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=3, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=132, i=3, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=4, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={160:0}, b={160:0}, i=4, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=4, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=141, i=4, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=5, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={160:0}, b={160:0}, i=5, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=5, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=146, i=5, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=6, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={160:0}, b={160:0}, i=6, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=6, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=142, i=6, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=7, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={160:0}, b={160:0}, i=7, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=7, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=157, i=7, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=8, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={160:0}, b={160:0}, i=8, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=8, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=145, i=8, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=9, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={160:0}, b={160:0}, i=9, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=9, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=153, i=9, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=10, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={160:0}, b={160:0}, i=10, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=10, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=149, i=10, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=11, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={160:0}, b={160:0}, i=11, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=11, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=135, i=11, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=12, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={160:0}, b={160:0}, i=12, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=12, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=139, i=12, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=13, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={160:0}, b={160:0}, i=13, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=13, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=136, i=13, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=14, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={160:0}, b={160:0}, i=14, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=14, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=152, i=14, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=15, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={160:0}, b={160:0}, i=15, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=15, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=150, i=15, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=16, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={160:0}, b={160:0}, i=16, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=16, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=156, i=16, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=17, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={160:0}, b={160:0}, i=17, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=17, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=161, i=17, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=18, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={160:0}, b={160:0}, i=18, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=18, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=154, i=18, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=19, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={160:0}, b={160:0}, i=19, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=19, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=162, i=19, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=20, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={160:0}, b={160:0}, i=20, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=20, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=148, i=20, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=21, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={160:0}, b={160:0}, i=21, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=21, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=137, i=21, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=22, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={160:0}, b={160:0}, i=22, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=22, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=151, i=22, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=23, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={160:0}, b={160:0}, i=23, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=23, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=163, i=23, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=24, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={160:0}, b={160:0}, i=24, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=24, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=131, i=24, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=25, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={160:0}, b={160:0}, i=25, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=25, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=133, i=25, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=26, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={160:0}, b={160:0}, i=26, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=26, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=130, i=26, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=27, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={160:0}, b={160:0}, i=27, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=27, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=138, i=27, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=28, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={160:0}, b={160:0}, i=28, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=28, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=143, i=28, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=29, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={160:0}, b={160:0}, i=29, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=29, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=155, i=29, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=30, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={160:0}, b={160:0}, i=30, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=30, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=164, i=30, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=31, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={160:0}, b={160:0}, i=31, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={160:0}, b={160:0}, i=31, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={160:0}, b={160:0}, b[i]=140, i=31, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={160:0}, b={160:0}, i=32, size=31] [L17] COND FALSE !(i <= size) VAL [\old(size)=31, b={160:0}, b={160:0}, i=32, size=31] [L20] RET return i; VAL [\old(size)=31, \result=32, b={160:0}, b={160:0}, i=32, size=31] [L27] EXPR foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=32, i=30, mask={160:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={158:0}, foo(mask, i + 1)=32, i=30, mask={160:0}] [L26] i++ VAL [b={158:0}, i=31, mask={160:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={158:0}, i=31, mask={160:0}] [L27] CALL foo(mask, i + 1) VAL [\old(size)=32, b={160:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=32, b={160:0}, b={160:0}, i=0, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={160:0}, b={160:0}, i=0, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={160:0}, b={160:0}, i=0, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={160:0}, b={160:0}, b[i]=129, i=0, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={160:0}, b={160:0}, i=1, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={160:0}, b={160:0}, i=1, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={160:0}, b={160:0}, i=1, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={160:0}, b={160:0}, b[i]=144, i=1, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={160:0}, b={160:0}, i=2, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={160:0}, b={160:0}, i=2, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={160:0}, b={160:0}, i=2, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={160:0}, b={160:0}, b[i]=134, i=2, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={160:0}, b={160:0}, i=3, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={160:0}, b={160:0}, i=3, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={160:0}, b={160:0}, i=3, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={160:0}, b={160:0}, b[i]=132, i=3, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={160:0}, b={160:0}, i=4, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={160:0}, b={160:0}, i=4, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={160:0}, b={160:0}, i=4, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={160:0}, b={160:0}, b[i]=141, i=4, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={160:0}, b={160:0}, i=5, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={160:0}, b={160:0}, i=5, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={160:0}, b={160:0}, i=5, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={160:0}, b={160:0}, b[i]=146, i=5, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={160:0}, b={160:0}, i=6, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={160:0}, b={160:0}, i=6, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={160:0}, b={160:0}, i=6, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={160:0}, b={160:0}, b[i]=142, i=6, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={160:0}, b={160:0}, i=7, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={160:0}, b={160:0}, i=7, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={160:0}, b={160:0}, i=7, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={160:0}, b={160:0}, b[i]=157, i=7, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={160:0}, b={160:0}, i=8, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={160:0}, b={160:0}, i=8, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={160:0}, b={160:0}, i=8, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={160:0}, b={160:0}, b[i]=145, i=8, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={160:0}, b={160:0}, i=9, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={160:0}, b={160:0}, i=9, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={160:0}, b={160:0}, i=9, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={160:0}, b={160:0}, b[i]=153, i=9, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={160:0}, b={160:0}, i=10, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={160:0}, b={160:0}, i=10, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={160:0}, b={160:0}, i=10, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={160:0}, b={160:0}, b[i]=149, i=10, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={160:0}, b={160:0}, i=11, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={160:0}, b={160:0}, i=11, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={160:0}, b={160:0}, i=11, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={160:0}, b={160:0}, b[i]=135, i=11, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={160:0}, b={160:0}, i=12, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={160:0}, b={160:0}, i=12, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={160:0}, b={160:0}, i=12, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={160:0}, b={160:0}, b[i]=139, i=12, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={160:0}, b={160:0}, i=13, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={160:0}, b={160:0}, i=13, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={160:0}, b={160:0}, i=13, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={160:0}, b={160:0}, b[i]=136, i=13, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={160:0}, b={160:0}, i=14, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={160:0}, b={160:0}, i=14, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={160:0}, b={160:0}, i=14, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={160:0}, b={160:0}, b[i]=152, i=14, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={160:0}, b={160:0}, i=15, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={160:0}, b={160:0}, i=15, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={160:0}, b={160:0}, i=15, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={160:0}, b={160:0}, b[i]=150, i=15, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={160:0}, b={160:0}, i=16, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={160:0}, b={160:0}, i=16, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={160:0}, b={160:0}, i=16, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={160:0}, b={160:0}, b[i]=156, i=16, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={160:0}, b={160:0}, i=17, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={160:0}, b={160:0}, i=17, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={160:0}, b={160:0}, i=17, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={160:0}, b={160:0}, b[i]=161, i=17, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={160:0}, b={160:0}, i=18, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={160:0}, b={160:0}, i=18, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={160:0}, b={160:0}, i=18, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={160:0}, b={160:0}, b[i]=154, i=18, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={160:0}, b={160:0}, i=19, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={160:0}, b={160:0}, i=19, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={160:0}, b={160:0}, i=19, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={160:0}, b={160:0}, b[i]=162, i=19, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={160:0}, b={160:0}, i=20, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={160:0}, b={160:0}, i=20, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={160:0}, b={160:0}, i=20, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={160:0}, b={160:0}, b[i]=148, i=20, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={160:0}, b={160:0}, i=21, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={160:0}, b={160:0}, i=21, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={160:0}, b={160:0}, i=21, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={160:0}, b={160:0}, b[i]=137, i=21, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={160:0}, b={160:0}, i=22, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={160:0}, b={160:0}, i=22, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={160:0}, b={160:0}, i=22, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={160:0}, b={160:0}, b[i]=151, i=22, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={160:0}, b={160:0}, i=23, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={160:0}, b={160:0}, i=23, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={160:0}, b={160:0}, i=23, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={160:0}, b={160:0}, b[i]=163, i=23, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={160:0}, b={160:0}, i=24, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={160:0}, b={160:0}, i=24, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={160:0}, b={160:0}, i=24, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={160:0}, b={160:0}, b[i]=131, i=24, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={160:0}, b={160:0}, i=25, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={160:0}, b={160:0}, i=25, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={160:0}, b={160:0}, i=25, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={160:0}, b={160:0}, b[i]=133, i=25, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={160:0}, b={160:0}, i=26, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={160:0}, b={160:0}, i=26, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={160:0}, b={160:0}, i=26, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={160:0}, b={160:0}, b[i]=130, i=26, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={160:0}, b={160:0}, i=27, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={160:0}, b={160:0}, i=27, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={160:0}, b={160:0}, i=27, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={160:0}, b={160:0}, b[i]=138, i=27, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={160:0}, b={160:0}, i=28, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={160:0}, b={160:0}, i=28, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={160:0}, b={160:0}, i=28, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={160:0}, b={160:0}, b[i]=143, i=28, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={160:0}, b={160:0}, i=29, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={160:0}, b={160:0}, i=29, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={160:0}, b={160:0}, i=29, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={160:0}, b={160:0}, b[i]=155, i=29, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={160:0}, b={160:0}, i=30, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={160:0}, b={160:0}, i=30, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={160:0}, b={160:0}, i=30, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={160:0}, b={160:0}, b[i]=164, i=30, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={160:0}, b={160:0}, i=31, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={160:0}, b={160:0}, i=31, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={160:0}, b={160:0}, i=31, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={160:0}, b={160:0}, b[i]=140, i=31, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={160:0}, b={160:0}, i=32, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={160:0}, b={160:0}, i=32, size=32] [L18] a[i] VAL [\old(size)=32, b={160:0}, b={160:0}, i=32, size=32] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 54 locations, 8 error locations. UNSAFE Result, 614.6s OverallTime, 88 OverallIterations, 591 TraceHistogramMax, 135.3s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 4798 SDtfs, 85695 SDslu, 81424 SDs, 0 SdLazy, 216385 SolverSat, 13673 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 50.6s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 117976 GetRequests, 109327 SyntacticMatches, 21 SemanticMatches, 8628 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 454935 ImplicationChecksByTransitivity, 131.0s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=3988occurred in iteration=87, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.7s AutomataMinimizationTime, 87 MinimizatonAttempts, 1189 StatesRemovedByMinimization, 83 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 3.8s SsaConstructionTime, 261.3s SatisfiabilityAnalysisTime, 141.1s InterpolantComputationTime, 226012 NumberOfCodeBlocks, 209502 NumberOfCodeBlocksAsserted, 1320 NumberOfCheckSat, 222073 ConstructedInterpolants, 115 QuantifiedInterpolants, 737663436 SizeOfPredicates, 197 NumberOfNonLiveVariables, 214454 ConjunctsInSsa, 2594 ConjunctsInUnsatCore, 166 InterpolantComputations, 9 PerfectInterpolantSequences, 32786079/33246488 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...