./Ultimate.py --spec ../../sv-benchmarks/c/ReachSafety.prp --file ../../sv-benchmarks/c/systemc/toy2_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 1dbac8bc Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_761f9461-ca5b-4fc5-9ded-29cffd327127/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_761f9461-ca5b-4fc5-9ded-29cffd327127/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_761f9461-ca5b-4fc5-9ded-29cffd327127/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_761f9461-ca5b-4fc5-9ded-29cffd327127/bin-2019/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/systemc/toy2_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_761f9461-ca5b-4fc5-9ded-29cffd327127/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_761f9461-ca5b-4fc5-9ded-29cffd327127/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c8989412e094655bcf4508d76eb9764ed06d0b34 ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-1dbac8b [2018-11-10 07:04:45,491 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-10 07:04:45,492 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-10 07:04:45,500 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-10 07:04:45,500 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-10 07:04:45,501 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-10 07:04:45,502 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-10 07:04:45,503 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-10 07:04:45,504 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-10 07:04:45,504 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-10 07:04:45,505 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-10 07:04:45,505 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-10 07:04:45,506 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-10 07:04:45,506 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-10 07:04:45,507 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-10 07:04:45,508 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-10 07:04:45,508 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-10 07:04:45,509 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-10 07:04:45,510 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-10 07:04:45,511 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-10 07:04:45,512 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-10 07:04:45,513 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-10 07:04:45,514 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-10 07:04:45,514 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-10 07:04:45,514 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-10 07:04:45,515 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-10 07:04:45,515 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-10 07:04:45,516 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-10 07:04:45,516 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-10 07:04:45,517 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-10 07:04:45,517 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-10 07:04:45,518 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-10 07:04:45,518 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-10 07:04:45,518 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-10 07:04:45,518 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-10 07:04:45,519 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-10 07:04:45,519 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_761f9461-ca5b-4fc5-9ded-29cffd327127/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2018-11-10 07:04:45,528 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-10 07:04:45,528 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-10 07:04:45,529 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-10 07:04:45,529 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-11-10 07:04:45,530 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-10 07:04:45,530 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-10 07:04:45,530 INFO L133 SettingsManager]: * Use SBE=true [2018-11-10 07:04:45,530 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-10 07:04:45,530 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-10 07:04:45,530 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-10 07:04:45,531 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-10 07:04:45,531 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-10 07:04:45,531 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-10 07:04:45,531 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-10 07:04:45,531 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-10 07:04:45,531 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-10 07:04:45,531 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-10 07:04:45,532 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-10 07:04:45,532 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-10 07:04:45,532 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-10 07:04:45,532 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-10 07:04:45,532 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-10 07:04:45,532 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-10 07:04:45,532 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-10 07:04:45,533 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-10 07:04:45,533 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-10 07:04:45,533 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-10 07:04:45,533 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-10 07:04:45,533 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-10 07:04:45,533 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_761f9461-ca5b-4fc5-9ded-29cffd327127/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c8989412e094655bcf4508d76eb9764ed06d0b34 [2018-11-10 07:04:45,556 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-10 07:04:45,565 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-10 07:04:45,566 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-10 07:04:45,567 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-10 07:04:45,567 INFO L276 PluginConnector]: CDTParser initialized [2018-11-10 07:04:45,568 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_761f9461-ca5b-4fc5-9ded-29cffd327127/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/toy2_false-unreach-call_false-termination.cil.c [2018-11-10 07:04:45,602 INFO L218 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_761f9461-ca5b-4fc5-9ded-29cffd327127/bin-2019/uautomizer/data/576e279c0/7dd372c3795545e695c19bc94f099549/FLAGc25aa677b [2018-11-10 07:04:46,013 INFO L298 CDTParser]: Found 1 translation units. [2018-11-10 07:04:46,013 INFO L158 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_761f9461-ca5b-4fc5-9ded-29cffd327127/sv-benchmarks/c/systemc/toy2_false-unreach-call_false-termination.cil.c [2018-11-10 07:04:46,021 INFO L346 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_761f9461-ca5b-4fc5-9ded-29cffd327127/bin-2019/uautomizer/data/576e279c0/7dd372c3795545e695c19bc94f099549/FLAGc25aa677b [2018-11-10 07:04:46,029 INFO L354 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_761f9461-ca5b-4fc5-9ded-29cffd327127/bin-2019/uautomizer/data/576e279c0/7dd372c3795545e695c19bc94f099549 [2018-11-10 07:04:46,031 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-10 07:04:46,032 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-11-10 07:04:46,032 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-10 07:04:46,032 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-10 07:04:46,034 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-10 07:04:46,035 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.11 07:04:46" (1/1) ... [2018-11-10 07:04:46,037 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4d841a26 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 07:04:46, skipping insertion in model container [2018-11-10 07:04:46,037 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.11 07:04:46" (1/1) ... [2018-11-10 07:04:46,043 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-10 07:04:46,063 INFO L174 MainTranslator]: Built tables and reachable declarations [2018-11-10 07:04:46,187 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-11-10 07:04:46,190 INFO L189 MainTranslator]: Completed pre-run [2018-11-10 07:04:46,217 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-11-10 07:04:46,225 INFO L193 MainTranslator]: Completed translation [2018-11-10 07:04:46,226 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 07:04:46 WrapperNode [2018-11-10 07:04:46,226 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-10 07:04:46,226 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-10 07:04:46,226 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-10 07:04:46,227 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-10 07:04:46,234 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 07:04:46" (1/1) ... [2018-11-10 07:04:46,234 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 07:04:46" (1/1) ... [2018-11-10 07:04:46,239 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 07:04:46" (1/1) ... [2018-11-10 07:04:46,239 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 07:04:46" (1/1) ... [2018-11-10 07:04:46,245 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 07:04:46" (1/1) ... [2018-11-10 07:04:46,254 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 07:04:46" (1/1) ... [2018-11-10 07:04:46,255 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 07:04:46" (1/1) ... [2018-11-10 07:04:46,295 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-10 07:04:46,296 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-10 07:04:46,296 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-10 07:04:46,296 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-10 07:04:46,297 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 07:04:46" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_761f9461-ca5b-4fc5-9ded-29cffd327127/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-10 07:04:46,351 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-10 07:04:46,351 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-10 07:04:46,351 INFO L138 BoogieDeclarations]: Found implementation of procedure error [2018-11-10 07:04:46,351 INFO L138 BoogieDeclarations]: Found implementation of procedure write_loop [2018-11-10 07:04:46,351 INFO L138 BoogieDeclarations]: Found implementation of procedure compute1 [2018-11-10 07:04:46,351 INFO L138 BoogieDeclarations]: Found implementation of procedure compute2 [2018-11-10 07:04:46,351 INFO L138 BoogieDeclarations]: Found implementation of procedure write_back [2018-11-10 07:04:46,352 INFO L138 BoogieDeclarations]: Found implementation of procedure read [2018-11-10 07:04:46,352 INFO L138 BoogieDeclarations]: Found implementation of procedure eval [2018-11-10 07:04:46,352 INFO L138 BoogieDeclarations]: Found implementation of procedure start_simulation [2018-11-10 07:04:46,352 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-10 07:04:46,352 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-11-10 07:04:46,352 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-11-10 07:04:46,352 INFO L130 BoogieDeclarations]: Found specification of procedure error [2018-11-10 07:04:46,352 INFO L130 BoogieDeclarations]: Found specification of procedure write_loop [2018-11-10 07:04:46,352 INFO L130 BoogieDeclarations]: Found specification of procedure compute1 [2018-11-10 07:04:46,353 INFO L130 BoogieDeclarations]: Found specification of procedure compute2 [2018-11-10 07:04:46,353 INFO L130 BoogieDeclarations]: Found specification of procedure write_back [2018-11-10 07:04:46,353 INFO L130 BoogieDeclarations]: Found specification of procedure read [2018-11-10 07:04:46,353 INFO L130 BoogieDeclarations]: Found specification of procedure eval [2018-11-10 07:04:46,353 INFO L130 BoogieDeclarations]: Found specification of procedure start_simulation [2018-11-10 07:04:46,353 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-10 07:04:46,353 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-10 07:04:46,353 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-10 07:04:46,801 INFO L341 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-10 07:04:46,802 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.11 07:04:46 BoogieIcfgContainer [2018-11-10 07:04:46,802 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-10 07:04:46,802 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-10 07:04:46,803 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-10 07:04:46,805 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-10 07:04:46,805 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 10.11 07:04:46" (1/3) ... [2018-11-10 07:04:46,806 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@58ec9a43 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 10.11 07:04:46, skipping insertion in model container [2018-11-10 07:04:46,806 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 07:04:46" (2/3) ... [2018-11-10 07:04:46,807 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@58ec9a43 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 10.11 07:04:46, skipping insertion in model container [2018-11-10 07:04:46,807 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.11 07:04:46" (3/3) ... [2018-11-10 07:04:46,809 INFO L112 eAbstractionObserver]: Analyzing ICFG toy2_false-unreach-call_false-termination.cil.c [2018-11-10 07:04:46,815 INFO L136 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-10 07:04:46,820 INFO L148 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-10 07:04:46,828 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-10 07:04:46,846 INFO L135 ementStrategyFactory]: Using default assertion order modulation [2018-11-10 07:04:46,846 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-10 07:04:46,846 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-10 07:04:46,846 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-10 07:04:46,846 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-10 07:04:46,847 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-10 07:04:46,847 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-10 07:04:46,847 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-10 07:04:46,847 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-10 07:04:46,862 INFO L276 IsEmpty]: Start isEmpty. Operand 164 states. [2018-11-10 07:04:46,867 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-11-10 07:04:46,867 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 07:04:46,868 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 07:04:46,870 INFO L424 AbstractCegarLoop]: === Iteration 1 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 07:04:46,873 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 07:04:46,873 INFO L82 PathProgramCache]: Analyzing trace with hash -226925251, now seen corresponding path program 1 times [2018-11-10 07:04:46,874 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 07:04:46,875 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 07:04:46,908 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:46,909 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 07:04:46,909 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:46,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:04:47,048 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:04:47,050 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 07:04:47,050 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 07:04:47,053 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-10 07:04:47,061 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 07:04:47,061 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 07:04:47,062 INFO L87 Difference]: Start difference. First operand 164 states. Second operand 3 states. [2018-11-10 07:04:47,096 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 07:04:47,096 INFO L93 Difference]: Finished difference Result 310 states and 521 transitions. [2018-11-10 07:04:47,097 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 07:04:47,097 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 48 [2018-11-10 07:04:47,098 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 07:04:47,106 INFO L225 Difference]: With dead ends: 310 [2018-11-10 07:04:47,106 INFO L226 Difference]: Without dead ends: 155 [2018-11-10 07:04:47,108 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 07:04:47,119 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 155 states. [2018-11-10 07:04:47,139 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 155 to 155. [2018-11-10 07:04:47,140 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 155 states. [2018-11-10 07:04:47,141 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 155 states to 155 states and 247 transitions. [2018-11-10 07:04:47,142 INFO L78 Accepts]: Start accepts. Automaton has 155 states and 247 transitions. Word has length 48 [2018-11-10 07:04:47,142 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 07:04:47,142 INFO L481 AbstractCegarLoop]: Abstraction has 155 states and 247 transitions. [2018-11-10 07:04:47,142 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-10 07:04:47,142 INFO L276 IsEmpty]: Start isEmpty. Operand 155 states and 247 transitions. [2018-11-10 07:04:47,143 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-11-10 07:04:47,143 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 07:04:47,143 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 07:04:47,144 INFO L424 AbstractCegarLoop]: === Iteration 2 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 07:04:47,144 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 07:04:47,144 INFO L82 PathProgramCache]: Analyzing trace with hash -1070930753, now seen corresponding path program 1 times [2018-11-10 07:04:47,144 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 07:04:47,144 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 07:04:47,145 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:47,145 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 07:04:47,145 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:47,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:04:47,225 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:04:47,226 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 07:04:47,226 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-10 07:04:47,227 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-10 07:04:47,227 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-10 07:04:47,227 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-10 07:04:47,228 INFO L87 Difference]: Start difference. First operand 155 states and 247 transitions. Second operand 4 states. [2018-11-10 07:04:47,376 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 07:04:47,376 INFO L93 Difference]: Finished difference Result 433 states and 698 transitions. [2018-11-10 07:04:47,377 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-10 07:04:47,377 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 48 [2018-11-10 07:04:47,377 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 07:04:47,380 INFO L225 Difference]: With dead ends: 433 [2018-11-10 07:04:47,380 INFO L226 Difference]: Without dead ends: 295 [2018-11-10 07:04:47,381 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-10 07:04:47,382 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 295 states. [2018-11-10 07:04:47,407 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 295 to 287. [2018-11-10 07:04:47,408 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 287 states. [2018-11-10 07:04:47,411 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 287 states to 287 states and 461 transitions. [2018-11-10 07:04:47,411 INFO L78 Accepts]: Start accepts. Automaton has 287 states and 461 transitions. Word has length 48 [2018-11-10 07:04:47,412 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 07:04:47,412 INFO L481 AbstractCegarLoop]: Abstraction has 287 states and 461 transitions. [2018-11-10 07:04:47,412 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-10 07:04:47,412 INFO L276 IsEmpty]: Start isEmpty. Operand 287 states and 461 transitions. [2018-11-10 07:04:47,415 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-11-10 07:04:47,415 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 07:04:47,415 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 07:04:47,415 INFO L424 AbstractCegarLoop]: === Iteration 3 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 07:04:47,415 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 07:04:47,415 INFO L82 PathProgramCache]: Analyzing trace with hash 1681653119, now seen corresponding path program 1 times [2018-11-10 07:04:47,416 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 07:04:47,416 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 07:04:47,417 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:47,418 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 07:04:47,418 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:47,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:04:47,475 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:04:47,475 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 07:04:47,476 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-10 07:04:47,476 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-10 07:04:47,477 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-10 07:04:47,477 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-10 07:04:47,477 INFO L87 Difference]: Start difference. First operand 287 states and 461 transitions. Second operand 4 states. [2018-11-10 07:04:47,626 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 07:04:47,626 INFO L93 Difference]: Finished difference Result 758 states and 1218 transitions. [2018-11-10 07:04:47,626 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-10 07:04:47,626 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 48 [2018-11-10 07:04:47,627 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 07:04:47,629 INFO L225 Difference]: With dead ends: 758 [2018-11-10 07:04:47,629 INFO L226 Difference]: Without dead ends: 499 [2018-11-10 07:04:47,631 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-10 07:04:47,631 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 499 states. [2018-11-10 07:04:47,659 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 499 to 487. [2018-11-10 07:04:47,659 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 487 states. [2018-11-10 07:04:47,661 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 487 states to 487 states and 779 transitions. [2018-11-10 07:04:47,661 INFO L78 Accepts]: Start accepts. Automaton has 487 states and 779 transitions. Word has length 48 [2018-11-10 07:04:47,661 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 07:04:47,662 INFO L481 AbstractCegarLoop]: Abstraction has 487 states and 779 transitions. [2018-11-10 07:04:47,662 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-10 07:04:47,662 INFO L276 IsEmpty]: Start isEmpty. Operand 487 states and 779 transitions. [2018-11-10 07:04:47,665 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-11-10 07:04:47,665 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 07:04:47,665 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 07:04:47,665 INFO L424 AbstractCegarLoop]: === Iteration 4 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 07:04:47,666 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 07:04:47,666 INFO L82 PathProgramCache]: Analyzing trace with hash 1956412733, now seen corresponding path program 1 times [2018-11-10 07:04:47,666 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 07:04:47,667 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 07:04:47,668 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:47,668 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 07:04:47,668 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:47,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:04:47,725 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:04:47,725 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 07:04:47,725 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 07:04:47,726 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-10 07:04:47,726 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 07:04:47,726 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 07:04:47,726 INFO L87 Difference]: Start difference. First operand 487 states and 779 transitions. Second operand 3 states. [2018-11-10 07:04:47,809 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 07:04:47,809 INFO L93 Difference]: Finished difference Result 1247 states and 1979 transitions. [2018-11-10 07:04:47,809 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 07:04:47,809 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 48 [2018-11-10 07:04:47,810 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 07:04:47,813 INFO L225 Difference]: With dead ends: 1247 [2018-11-10 07:04:47,814 INFO L226 Difference]: Without dead ends: 792 [2018-11-10 07:04:47,815 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 07:04:47,816 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 792 states. [2018-11-10 07:04:47,853 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 792 to 785. [2018-11-10 07:04:47,854 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 785 states. [2018-11-10 07:04:47,858 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 785 states to 785 states and 1235 transitions. [2018-11-10 07:04:47,858 INFO L78 Accepts]: Start accepts. Automaton has 785 states and 1235 transitions. Word has length 48 [2018-11-10 07:04:47,859 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 07:04:47,859 INFO L481 AbstractCegarLoop]: Abstraction has 785 states and 1235 transitions. [2018-11-10 07:04:47,859 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-10 07:04:47,859 INFO L276 IsEmpty]: Start isEmpty. Operand 785 states and 1235 transitions. [2018-11-10 07:04:47,861 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-11-10 07:04:47,861 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 07:04:47,861 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 07:04:47,861 INFO L424 AbstractCegarLoop]: === Iteration 5 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 07:04:47,861 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 07:04:47,862 INFO L82 PathProgramCache]: Analyzing trace with hash 1979044987, now seen corresponding path program 1 times [2018-11-10 07:04:47,862 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 07:04:47,862 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 07:04:47,864 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:47,864 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 07:04:47,864 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:47,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:04:47,907 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:04:47,908 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 07:04:47,908 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 07:04:47,908 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-10 07:04:47,909 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 07:04:47,909 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 07:04:47,909 INFO L87 Difference]: Start difference. First operand 785 states and 1235 transitions. Second operand 3 states. [2018-11-10 07:04:48,042 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 07:04:48,043 INFO L93 Difference]: Finished difference Result 2078 states and 3338 transitions. [2018-11-10 07:04:48,043 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 07:04:48,044 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 48 [2018-11-10 07:04:48,044 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 07:04:48,049 INFO L225 Difference]: With dead ends: 2078 [2018-11-10 07:04:48,050 INFO L226 Difference]: Without dead ends: 1327 [2018-11-10 07:04:48,053 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 07:04:48,054 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1327 states. [2018-11-10 07:04:48,108 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1327 to 1309. [2018-11-10 07:04:48,109 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1309 states. [2018-11-10 07:04:48,115 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1309 states to 1309 states and 2074 transitions. [2018-11-10 07:04:48,116 INFO L78 Accepts]: Start accepts. Automaton has 1309 states and 2074 transitions. Word has length 48 [2018-11-10 07:04:48,116 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 07:04:48,116 INFO L481 AbstractCegarLoop]: Abstraction has 1309 states and 2074 transitions. [2018-11-10 07:04:48,116 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-10 07:04:48,116 INFO L276 IsEmpty]: Start isEmpty. Operand 1309 states and 2074 transitions. [2018-11-10 07:04:48,117 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-11-10 07:04:48,117 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 07:04:48,117 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 07:04:48,118 INFO L424 AbstractCegarLoop]: === Iteration 6 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 07:04:48,118 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 07:04:48,119 INFO L82 PathProgramCache]: Analyzing trace with hash -1101629998, now seen corresponding path program 1 times [2018-11-10 07:04:48,119 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 07:04:48,119 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 07:04:48,119 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:48,120 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 07:04:48,120 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:48,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:04:48,183 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:04:48,183 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 07:04:48,184 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 07:04:48,184 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-10 07:04:48,184 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 07:04:48,184 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 07:04:48,184 INFO L87 Difference]: Start difference. First operand 1309 states and 2074 transitions. Second operand 3 states. [2018-11-10 07:04:48,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 07:04:48,264 INFO L93 Difference]: Finished difference Result 2647 states and 4219 transitions. [2018-11-10 07:04:48,265 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 07:04:48,265 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 48 [2018-11-10 07:04:48,265 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 07:04:48,269 INFO L225 Difference]: With dead ends: 2647 [2018-11-10 07:04:48,269 INFO L226 Difference]: Without dead ends: 1390 [2018-11-10 07:04:48,272 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 07:04:48,273 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1390 states. [2018-11-10 07:04:48,333 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1390 to 1390. [2018-11-10 07:04:48,334 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1390 states. [2018-11-10 07:04:48,338 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1390 states to 1390 states and 2206 transitions. [2018-11-10 07:04:48,339 INFO L78 Accepts]: Start accepts. Automaton has 1390 states and 2206 transitions. Word has length 48 [2018-11-10 07:04:48,339 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 07:04:48,339 INFO L481 AbstractCegarLoop]: Abstraction has 1390 states and 2206 transitions. [2018-11-10 07:04:48,339 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-10 07:04:48,340 INFO L276 IsEmpty]: Start isEmpty. Operand 1390 states and 2206 transitions. [2018-11-10 07:04:48,341 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-11-10 07:04:48,341 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 07:04:48,341 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 07:04:48,341 INFO L424 AbstractCegarLoop]: === Iteration 7 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 07:04:48,341 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 07:04:48,341 INFO L82 PathProgramCache]: Analyzing trace with hash -2053291954, now seen corresponding path program 1 times [2018-11-10 07:04:48,342 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 07:04:48,342 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 07:04:48,342 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:48,342 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 07:04:48,343 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:48,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:04:48,378 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:04:48,378 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 07:04:48,378 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-10 07:04:48,379 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-10 07:04:48,379 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-10 07:04:48,379 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-10 07:04:48,379 INFO L87 Difference]: Start difference. First operand 1390 states and 2206 transitions. Second operand 4 states. [2018-11-10 07:04:48,501 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 07:04:48,501 INFO L93 Difference]: Finished difference Result 3100 states and 4923 transitions. [2018-11-10 07:04:48,502 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-10 07:04:48,502 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 48 [2018-11-10 07:04:48,502 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 07:04:48,506 INFO L225 Difference]: With dead ends: 3100 [2018-11-10 07:04:48,506 INFO L226 Difference]: Without dead ends: 1752 [2018-11-10 07:04:48,509 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-10 07:04:48,510 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1752 states. [2018-11-10 07:04:48,551 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1752 to 1731. [2018-11-10 07:04:48,551 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1731 states. [2018-11-10 07:04:48,556 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1731 states to 1731 states and 2718 transitions. [2018-11-10 07:04:48,556 INFO L78 Accepts]: Start accepts. Automaton has 1731 states and 2718 transitions. Word has length 48 [2018-11-10 07:04:48,556 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 07:04:48,557 INFO L481 AbstractCegarLoop]: Abstraction has 1731 states and 2718 transitions. [2018-11-10 07:04:48,557 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-10 07:04:48,557 INFO L276 IsEmpty]: Start isEmpty. Operand 1731 states and 2718 transitions. [2018-11-10 07:04:48,557 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-11-10 07:04:48,558 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 07:04:48,558 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 07:04:48,558 INFO L424 AbstractCegarLoop]: === Iteration 8 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 07:04:48,558 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 07:04:48,558 INFO L82 PathProgramCache]: Analyzing trace with hash 436237008, now seen corresponding path program 1 times [2018-11-10 07:04:48,558 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 07:04:48,558 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 07:04:48,559 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:48,559 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 07:04:48,559 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:48,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:04:48,595 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:04:48,595 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 07:04:48,595 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-10 07:04:48,596 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-10 07:04:48,596 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-10 07:04:48,596 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-10 07:04:48,596 INFO L87 Difference]: Start difference. First operand 1731 states and 2718 transitions. Second operand 4 states. [2018-11-10 07:04:48,774 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 07:04:48,774 INFO L93 Difference]: Finished difference Result 4978 states and 7896 transitions. [2018-11-10 07:04:48,774 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-10 07:04:48,774 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 48 [2018-11-10 07:04:48,775 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 07:04:48,782 INFO L225 Difference]: With dead ends: 4978 [2018-11-10 07:04:48,783 INFO L226 Difference]: Without dead ends: 3307 [2018-11-10 07:04:48,786 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-10 07:04:48,788 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3307 states. [2018-11-10 07:04:48,877 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3307 to 3268. [2018-11-10 07:04:48,877 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3268 states. [2018-11-10 07:04:48,891 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3268 states to 3268 states and 5179 transitions. [2018-11-10 07:04:48,892 INFO L78 Accepts]: Start accepts. Automaton has 3268 states and 5179 transitions. Word has length 48 [2018-11-10 07:04:48,892 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 07:04:48,892 INFO L481 AbstractCegarLoop]: Abstraction has 3268 states and 5179 transitions. [2018-11-10 07:04:48,892 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-10 07:04:48,892 INFO L276 IsEmpty]: Start isEmpty. Operand 3268 states and 5179 transitions. [2018-11-10 07:04:48,893 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-11-10 07:04:48,894 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 07:04:48,894 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 07:04:48,894 INFO L424 AbstractCegarLoop]: === Iteration 9 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 07:04:48,894 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 07:04:48,894 INFO L82 PathProgramCache]: Analyzing trace with hash 858938834, now seen corresponding path program 1 times [2018-11-10 07:04:48,894 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 07:04:48,894 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 07:04:48,895 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:48,895 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 07:04:48,895 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:48,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:04:48,939 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:04:48,939 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 07:04:48,940 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 07:04:48,940 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-10 07:04:48,940 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 07:04:48,940 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 07:04:48,940 INFO L87 Difference]: Start difference. First operand 3268 states and 5179 transitions. Second operand 3 states. [2018-11-10 07:04:49,054 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 07:04:49,054 INFO L93 Difference]: Finished difference Result 6876 states and 11081 transitions. [2018-11-10 07:04:49,055 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 07:04:49,055 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 48 [2018-11-10 07:04:49,055 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 07:04:49,064 INFO L225 Difference]: With dead ends: 6876 [2018-11-10 07:04:49,064 INFO L226 Difference]: Without dead ends: 3751 [2018-11-10 07:04:49,073 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 07:04:49,075 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3751 states. [2018-11-10 07:04:49,201 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3751 to 3751. [2018-11-10 07:04:49,201 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3751 states. [2018-11-10 07:04:49,209 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3751 states to 3751 states and 5911 transitions. [2018-11-10 07:04:49,210 INFO L78 Accepts]: Start accepts. Automaton has 3751 states and 5911 transitions. Word has length 48 [2018-11-10 07:04:49,210 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 07:04:49,210 INFO L481 AbstractCegarLoop]: Abstraction has 3751 states and 5911 transitions. [2018-11-10 07:04:49,210 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-10 07:04:49,210 INFO L276 IsEmpty]: Start isEmpty. Operand 3751 states and 5911 transitions. [2018-11-10 07:04:49,211 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-11-10 07:04:49,211 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 07:04:49,211 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 07:04:49,212 INFO L424 AbstractCegarLoop]: === Iteration 10 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 07:04:49,212 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 07:04:49,212 INFO L82 PathProgramCache]: Analyzing trace with hash -830004908, now seen corresponding path program 1 times [2018-11-10 07:04:49,212 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 07:04:49,212 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 07:04:49,213 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:49,213 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 07:04:49,213 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:49,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:04:49,244 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:04:49,244 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 07:04:49,244 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 07:04:49,244 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-10 07:04:49,244 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 07:04:49,245 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 07:04:49,245 INFO L87 Difference]: Start difference. First operand 3751 states and 5911 transitions. Second operand 3 states. [2018-11-10 07:04:49,387 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 07:04:49,388 INFO L93 Difference]: Finished difference Result 8150 states and 13119 transitions. [2018-11-10 07:04:49,388 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 07:04:49,388 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 48 [2018-11-10 07:04:49,389 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 07:04:49,399 INFO L225 Difference]: With dead ends: 8150 [2018-11-10 07:04:49,399 INFO L226 Difference]: Without dead ends: 4451 [2018-11-10 07:04:49,407 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 07:04:49,410 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4451 states. [2018-11-10 07:04:49,516 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4451 to 4371. [2018-11-10 07:04:49,516 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4371 states. [2018-11-10 07:04:49,525 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4371 states to 4371 states and 6832 transitions. [2018-11-10 07:04:49,526 INFO L78 Accepts]: Start accepts. Automaton has 4371 states and 6832 transitions. Word has length 48 [2018-11-10 07:04:49,526 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 07:04:49,526 INFO L481 AbstractCegarLoop]: Abstraction has 4371 states and 6832 transitions. [2018-11-10 07:04:49,527 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-10 07:04:49,527 INFO L276 IsEmpty]: Start isEmpty. Operand 4371 states and 6832 transitions. [2018-11-10 07:04:49,532 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2018-11-10 07:04:49,532 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 07:04:49,532 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 07:04:49,532 INFO L424 AbstractCegarLoop]: === Iteration 11 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 07:04:49,532 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 07:04:49,532 INFO L82 PathProgramCache]: Analyzing trace with hash -1408012478, now seen corresponding path program 1 times [2018-11-10 07:04:49,532 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 07:04:49,532 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 07:04:49,533 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:49,533 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 07:04:49,533 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:49,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:04:49,589 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 21 proven. 7 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-11-10 07:04:49,589 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 07:04:49,589 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_761f9461-ca5b-4fc5-9ded-29cffd327127/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 07:04:49,604 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 07:04:49,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:04:49,676 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 07:04:49,708 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 25 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-11-10 07:04:49,725 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-10 07:04:49,725 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [7] total 8 [2018-11-10 07:04:49,725 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-10 07:04:49,726 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-10 07:04:49,726 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-11-10 07:04:49,726 INFO L87 Difference]: Start difference. First operand 4371 states and 6832 transitions. Second operand 8 states. [2018-11-10 07:04:50,817 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 07:04:50,817 INFO L93 Difference]: Finished difference Result 16535 states and 27891 transitions. [2018-11-10 07:04:50,817 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-11-10 07:04:50,818 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 85 [2018-11-10 07:04:50,818 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 07:04:50,831 INFO L225 Difference]: With dead ends: 16535 [2018-11-10 07:04:50,832 INFO L226 Difference]: Without dead ends: 4154 [2018-11-10 07:04:50,867 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 119 GetRequests, 99 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 101 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=124, Invalid=338, Unknown=0, NotChecked=0, Total=462 [2018-11-10 07:04:50,869 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4154 states. [2018-11-10 07:04:50,985 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4154 to 2830. [2018-11-10 07:04:50,985 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2830 states. [2018-11-10 07:04:50,991 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2830 states to 2830 states and 4249 transitions. [2018-11-10 07:04:50,992 INFO L78 Accepts]: Start accepts. Automaton has 2830 states and 4249 transitions. Word has length 85 [2018-11-10 07:04:50,992 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 07:04:50,992 INFO L481 AbstractCegarLoop]: Abstraction has 2830 states and 4249 transitions. [2018-11-10 07:04:50,992 INFO L482 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-10 07:04:50,992 INFO L276 IsEmpty]: Start isEmpty. Operand 2830 states and 4249 transitions. [2018-11-10 07:04:50,998 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 129 [2018-11-10 07:04:50,998 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 07:04:50,998 INFO L375 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 07:04:50,998 INFO L424 AbstractCegarLoop]: === Iteration 12 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 07:04:50,998 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 07:04:50,998 INFO L82 PathProgramCache]: Analyzing trace with hash -1358285186, now seen corresponding path program 1 times [2018-11-10 07:04:50,999 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 07:04:50,999 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 07:04:50,999 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:50,999 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 07:04:51,000 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:51,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:04:51,060 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 32 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-11-10 07:04:51,061 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 07:04:51,061 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 07:04:51,061 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-10 07:04:51,061 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 07:04:51,061 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 07:04:51,061 INFO L87 Difference]: Start difference. First operand 2830 states and 4249 transitions. Second operand 5 states. [2018-11-10 07:04:51,345 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 07:04:51,345 INFO L93 Difference]: Finished difference Result 5431 states and 8245 transitions. [2018-11-10 07:04:51,346 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-10 07:04:51,346 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 128 [2018-11-10 07:04:51,346 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 07:04:51,359 INFO L225 Difference]: With dead ends: 5431 [2018-11-10 07:04:51,359 INFO L226 Difference]: Without dead ends: 3763 [2018-11-10 07:04:51,364 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2018-11-10 07:04:51,367 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3763 states. [2018-11-10 07:04:51,513 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3763 to 3660. [2018-11-10 07:04:51,513 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3660 states. [2018-11-10 07:04:51,522 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3660 states to 3660 states and 5585 transitions. [2018-11-10 07:04:51,522 INFO L78 Accepts]: Start accepts. Automaton has 3660 states and 5585 transitions. Word has length 128 [2018-11-10 07:04:51,523 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 07:04:51,523 INFO L481 AbstractCegarLoop]: Abstraction has 3660 states and 5585 transitions. [2018-11-10 07:04:51,523 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-10 07:04:51,523 INFO L276 IsEmpty]: Start isEmpty. Operand 3660 states and 5585 transitions. [2018-11-10 07:04:51,531 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 129 [2018-11-10 07:04:51,531 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 07:04:51,531 INFO L375 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 07:04:51,531 INFO L424 AbstractCegarLoop]: === Iteration 13 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 07:04:51,531 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 07:04:51,531 INFO L82 PathProgramCache]: Analyzing trace with hash 374483266, now seen corresponding path program 1 times [2018-11-10 07:04:51,532 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 07:04:51,532 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 07:04:51,532 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:51,532 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 07:04:51,532 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:51,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:04:51,601 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 32 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-10 07:04:51,601 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 07:04:51,601 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_761f9461-ca5b-4fc5-9ded-29cffd327127/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 07:04:51,608 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 07:04:51,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:04:51,685 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 07:04:51,732 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 33 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-11-10 07:04:51,749 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-10 07:04:51,749 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [5] total 7 [2018-11-10 07:04:51,750 INFO L460 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-10 07:04:51,750 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-10 07:04:51,750 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-10 07:04:51,750 INFO L87 Difference]: Start difference. First operand 3660 states and 5585 transitions. Second operand 7 states. [2018-11-10 07:04:52,083 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 07:04:52,083 INFO L93 Difference]: Finished difference Result 6899 states and 10643 transitions. [2018-11-10 07:04:52,084 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-10 07:04:52,084 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 128 [2018-11-10 07:04:52,084 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 07:04:52,094 INFO L225 Difference]: With dead ends: 6899 [2018-11-10 07:04:52,094 INFO L226 Difference]: Without dead ends: 3284 [2018-11-10 07:04:52,102 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 143 GetRequests, 132 SyntacticMatches, 1 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=47, Invalid=85, Unknown=0, NotChecked=0, Total=132 [2018-11-10 07:04:52,104 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3284 states. [2018-11-10 07:04:52,207 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3284 to 3073. [2018-11-10 07:04:52,207 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3073 states. [2018-11-10 07:04:52,213 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3073 states to 3073 states and 4581 transitions. [2018-11-10 07:04:52,214 INFO L78 Accepts]: Start accepts. Automaton has 3073 states and 4581 transitions. Word has length 128 [2018-11-10 07:04:52,214 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 07:04:52,214 INFO L481 AbstractCegarLoop]: Abstraction has 3073 states and 4581 transitions. [2018-11-10 07:04:52,214 INFO L482 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-10 07:04:52,214 INFO L276 IsEmpty]: Start isEmpty. Operand 3073 states and 4581 transitions. [2018-11-10 07:04:52,219 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 129 [2018-11-10 07:04:52,219 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 07:04:52,219 INFO L375 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 07:04:52,220 INFO L424 AbstractCegarLoop]: === Iteration 14 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 07:04:52,220 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 07:04:52,220 INFO L82 PathProgramCache]: Analyzing trace with hash 1250502272, now seen corresponding path program 1 times [2018-11-10 07:04:52,220 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 07:04:52,220 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 07:04:52,221 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:52,221 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 07:04:52,221 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:52,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:04:52,264 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 38 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-11-10 07:04:52,264 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 07:04:52,264 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 07:04:52,264 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-10 07:04:52,265 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 07:04:52,265 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 07:04:52,265 INFO L87 Difference]: Start difference. First operand 3073 states and 4581 transitions. Second operand 3 states. [2018-11-10 07:04:52,403 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 07:04:52,403 INFO L93 Difference]: Finished difference Result 5840 states and 8798 transitions. [2018-11-10 07:04:52,404 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 07:04:52,404 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 128 [2018-11-10 07:04:52,404 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 07:04:52,415 INFO L225 Difference]: With dead ends: 5840 [2018-11-10 07:04:52,415 INFO L226 Difference]: Without dead ends: 2848 [2018-11-10 07:04:52,424 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 07:04:52,426 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2848 states. [2018-11-10 07:04:52,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2848 to 2742. [2018-11-10 07:04:52,575 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2742 states. [2018-11-10 07:04:52,579 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2742 states to 2742 states and 3940 transitions. [2018-11-10 07:04:52,580 INFO L78 Accepts]: Start accepts. Automaton has 2742 states and 3940 transitions. Word has length 128 [2018-11-10 07:04:52,580 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 07:04:52,580 INFO L481 AbstractCegarLoop]: Abstraction has 2742 states and 3940 transitions. [2018-11-10 07:04:52,580 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-10 07:04:52,580 INFO L276 IsEmpty]: Start isEmpty. Operand 2742 states and 3940 transitions. [2018-11-10 07:04:52,585 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 131 [2018-11-10 07:04:52,585 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 07:04:52,585 INFO L375 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 07:04:52,585 INFO L424 AbstractCegarLoop]: === Iteration 15 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 07:04:52,586 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 07:04:52,586 INFO L82 PathProgramCache]: Analyzing trace with hash 1849294983, now seen corresponding path program 1 times [2018-11-10 07:04:52,586 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 07:04:52,586 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 07:04:52,586 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:52,587 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 07:04:52,587 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:52,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:04:52,644 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 32 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-11-10 07:04:52,644 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 07:04:52,644 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-10 07:04:52,644 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-10 07:04:52,645 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-10 07:04:52,645 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-10 07:04:52,645 INFO L87 Difference]: Start difference. First operand 2742 states and 3940 transitions. Second operand 4 states. [2018-11-10 07:04:52,925 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 07:04:52,925 INFO L93 Difference]: Finished difference Result 7633 states and 11092 transitions. [2018-11-10 07:04:52,925 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-10 07:04:52,925 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 130 [2018-11-10 07:04:52,925 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 07:04:52,940 INFO L225 Difference]: With dead ends: 7633 [2018-11-10 07:04:52,940 INFO L226 Difference]: Without dead ends: 4900 [2018-11-10 07:04:52,946 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-10 07:04:52,950 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4900 states. [2018-11-10 07:04:53,107 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4900 to 4649. [2018-11-10 07:04:53,108 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4649 states. [2018-11-10 07:04:53,116 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4649 states to 4649 states and 6803 transitions. [2018-11-10 07:04:53,117 INFO L78 Accepts]: Start accepts. Automaton has 4649 states and 6803 transitions. Word has length 130 [2018-11-10 07:04:53,117 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 07:04:53,117 INFO L481 AbstractCegarLoop]: Abstraction has 4649 states and 6803 transitions. [2018-11-10 07:04:53,117 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-10 07:04:53,117 INFO L276 IsEmpty]: Start isEmpty. Operand 4649 states and 6803 transitions. [2018-11-10 07:04:53,122 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 141 [2018-11-10 07:04:53,122 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 07:04:53,123 INFO L375 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 07:04:53,123 INFO L424 AbstractCegarLoop]: === Iteration 16 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 07:04:53,123 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 07:04:53,123 INFO L82 PathProgramCache]: Analyzing trace with hash -858873014, now seen corresponding path program 1 times [2018-11-10 07:04:53,123 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 07:04:53,123 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 07:04:53,124 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:53,124 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 07:04:53,124 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:53,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:04:53,178 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 32 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-10 07:04:53,178 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 07:04:53,178 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_761f9461-ca5b-4fc5-9ded-29cffd327127/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 07:04:53,184 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 07:04:53,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:04:53,264 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 07:04:53,283 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 36 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-10 07:04:53,299 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-10 07:04:53,299 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [5] total 6 [2018-11-10 07:04:53,300 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-10 07:04:53,300 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-10 07:04:53,300 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-10 07:04:53,300 INFO L87 Difference]: Start difference. First operand 4649 states and 6803 transitions. Second operand 6 states. [2018-11-10 07:04:53,921 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 07:04:53,921 INFO L93 Difference]: Finished difference Result 11610 states and 18207 transitions. [2018-11-10 07:04:53,922 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-10 07:04:53,922 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 140 [2018-11-10 07:04:53,923 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 07:04:53,951 INFO L225 Difference]: With dead ends: 11610 [2018-11-10 07:04:53,951 INFO L226 Difference]: Without dead ends: 6987 [2018-11-10 07:04:53,968 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 150 GetRequests, 144 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2018-11-10 07:04:53,973 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6987 states. [2018-11-10 07:04:54,318 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6987 to 6404. [2018-11-10 07:04:54,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6404 states. [2018-11-10 07:04:54,336 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6404 states to 6404 states and 9454 transitions. [2018-11-10 07:04:54,338 INFO L78 Accepts]: Start accepts. Automaton has 6404 states and 9454 transitions. Word has length 140 [2018-11-10 07:04:54,338 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 07:04:54,338 INFO L481 AbstractCegarLoop]: Abstraction has 6404 states and 9454 transitions. [2018-11-10 07:04:54,338 INFO L482 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-10 07:04:54,338 INFO L276 IsEmpty]: Start isEmpty. Operand 6404 states and 9454 transitions. [2018-11-10 07:04:54,349 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 159 [2018-11-10 07:04:54,350 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 07:04:54,350 INFO L375 BasicCegarLoop]: trace histogram [5, 5, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 07:04:54,350 INFO L424 AbstractCegarLoop]: === Iteration 17 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 07:04:54,350 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 07:04:54,350 INFO L82 PathProgramCache]: Analyzing trace with hash -1269629646, now seen corresponding path program 1 times [2018-11-10 07:04:54,350 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 07:04:54,351 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 07:04:54,351 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:54,351 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 07:04:54,351 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:54,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:04:54,398 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 49 proven. 0 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-11-10 07:04:54,398 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 07:04:54,398 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 07:04:54,399 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-10 07:04:54,399 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 07:04:54,399 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 07:04:54,399 INFO L87 Difference]: Start difference. First operand 6404 states and 9454 transitions. Second operand 3 states. [2018-11-10 07:04:54,797 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 07:04:54,797 INFO L93 Difference]: Finished difference Result 13350 states and 19738 transitions. [2018-11-10 07:04:54,798 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 07:04:54,798 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 158 [2018-11-10 07:04:54,798 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 07:04:54,826 INFO L225 Difference]: With dead ends: 13350 [2018-11-10 07:04:54,826 INFO L226 Difference]: Without dead ends: 6983 [2018-11-10 07:04:54,844 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 07:04:54,849 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6983 states. [2018-11-10 07:04:55,328 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6983 to 6920. [2018-11-10 07:04:55,328 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6920 states. [2018-11-10 07:04:55,339 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6920 states to 6920 states and 9801 transitions. [2018-11-10 07:04:55,341 INFO L78 Accepts]: Start accepts. Automaton has 6920 states and 9801 transitions. Word has length 158 [2018-11-10 07:04:55,341 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 07:04:55,341 INFO L481 AbstractCegarLoop]: Abstraction has 6920 states and 9801 transitions. [2018-11-10 07:04:55,341 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-10 07:04:55,341 INFO L276 IsEmpty]: Start isEmpty. Operand 6920 states and 9801 transitions. [2018-11-10 07:04:55,348 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 159 [2018-11-10 07:04:55,348 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 07:04:55,349 INFO L375 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 07:04:55,349 INFO L424 AbstractCegarLoop]: === Iteration 18 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 07:04:55,349 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 07:04:55,349 INFO L82 PathProgramCache]: Analyzing trace with hash 792371704, now seen corresponding path program 1 times [2018-11-10 07:04:55,349 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 07:04:55,349 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 07:04:55,350 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:55,350 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 07:04:55,350 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:55,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:04:55,386 INFO L134 CoverageAnalysis]: Checked inductivity of 79 backedges. 42 proven. 0 refuted. 0 times theorem prover too weak. 37 trivial. 0 not checked. [2018-11-10 07:04:55,386 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 07:04:55,386 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 07:04:55,386 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-10 07:04:55,386 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 07:04:55,387 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 07:04:55,387 INFO L87 Difference]: Start difference. First operand 6920 states and 9801 transitions. Second operand 3 states. [2018-11-10 07:04:55,627 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 07:04:55,627 INFO L93 Difference]: Finished difference Result 13801 states and 19550 transitions. [2018-11-10 07:04:55,628 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 07:04:55,628 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 158 [2018-11-10 07:04:55,628 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 07:04:55,643 INFO L225 Difference]: With dead ends: 13801 [2018-11-10 07:04:55,643 INFO L226 Difference]: Without dead ends: 6894 [2018-11-10 07:04:55,652 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 07:04:55,656 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6894 states. [2018-11-10 07:04:55,871 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6894 to 6894. [2018-11-10 07:04:55,872 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6894 states. [2018-11-10 07:04:55,882 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6894 states to 6894 states and 9763 transitions. [2018-11-10 07:04:55,884 INFO L78 Accepts]: Start accepts. Automaton has 6894 states and 9763 transitions. Word has length 158 [2018-11-10 07:04:55,884 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 07:04:55,884 INFO L481 AbstractCegarLoop]: Abstraction has 6894 states and 9763 transitions. [2018-11-10 07:04:55,884 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-10 07:04:55,884 INFO L276 IsEmpty]: Start isEmpty. Operand 6894 states and 9763 transitions. [2018-11-10 07:04:55,891 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 159 [2018-11-10 07:04:55,891 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 07:04:55,891 INFO L375 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 07:04:55,891 INFO L424 AbstractCegarLoop]: === Iteration 19 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 07:04:55,892 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 07:04:55,892 INFO L82 PathProgramCache]: Analyzing trace with hash 1057019194, now seen corresponding path program 1 times [2018-11-10 07:04:55,892 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 07:04:55,892 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 07:04:55,892 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:55,893 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 07:04:55,893 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:55,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:04:55,969 INFO L134 CoverageAnalysis]: Checked inductivity of 79 backedges. 51 proven. 18 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-10 07:04:55,969 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 07:04:55,969 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_761f9461-ca5b-4fc5-9ded-29cffd327127/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 07:04:55,976 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 07:04:56,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:04:56,057 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 07:04:56,141 INFO L134 CoverageAnalysis]: Checked inductivity of 79 backedges. 63 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-10 07:04:56,168 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-10 07:04:56,169 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [9] total 10 [2018-11-10 07:04:56,169 INFO L460 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-10 07:04:56,169 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-10 07:04:56,169 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2018-11-10 07:04:56,170 INFO L87 Difference]: Start difference. First operand 6894 states and 9763 transitions. Second operand 10 states. [2018-11-10 07:04:57,617 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 07:04:57,617 INFO L93 Difference]: Finished difference Result 15835 states and 23101 transitions. [2018-11-10 07:04:57,617 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-11-10 07:04:57,618 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 158 [2018-11-10 07:04:57,618 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 07:04:57,650 INFO L225 Difference]: With dead ends: 15835 [2018-11-10 07:04:57,650 INFO L226 Difference]: Without dead ends: 9825 [2018-11-10 07:04:57,667 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 183 GetRequests, 166 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 51 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=89, Invalid=253, Unknown=0, NotChecked=0, Total=342 [2018-11-10 07:04:57,673 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9825 states. [2018-11-10 07:04:58,023 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9825 to 7732. [2018-11-10 07:04:58,023 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7732 states. [2018-11-10 07:04:58,037 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7732 states to 7732 states and 10708 transitions. [2018-11-10 07:04:58,038 INFO L78 Accepts]: Start accepts. Automaton has 7732 states and 10708 transitions. Word has length 158 [2018-11-10 07:04:58,039 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 07:04:58,039 INFO L481 AbstractCegarLoop]: Abstraction has 7732 states and 10708 transitions. [2018-11-10 07:04:58,039 INFO L482 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-10 07:04:58,039 INFO L276 IsEmpty]: Start isEmpty. Operand 7732 states and 10708 transitions. [2018-11-10 07:04:58,046 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 172 [2018-11-10 07:04:58,046 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 07:04:58,047 INFO L375 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 07:04:58,047 INFO L424 AbstractCegarLoop]: === Iteration 20 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 07:04:58,047 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 07:04:58,047 INFO L82 PathProgramCache]: Analyzing trace with hash -794082158, now seen corresponding path program 1 times [2018-11-10 07:04:58,047 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 07:04:58,047 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 07:04:58,048 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:58,048 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 07:04:58,048 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:58,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:04:58,133 INFO L134 CoverageAnalysis]: Checked inductivity of 79 backedges. 55 proven. 4 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-11-10 07:04:58,133 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 07:04:58,133 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_761f9461-ca5b-4fc5-9ded-29cffd327127/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 07:04:58,148 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 07:04:58,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:04:58,249 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 07:04:58,270 INFO L134 CoverageAnalysis]: Checked inductivity of 79 backedges. 63 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-10 07:04:58,287 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-10 07:04:58,287 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [4] total 5 [2018-11-10 07:04:58,287 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-10 07:04:58,288 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 07:04:58,288 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 07:04:58,288 INFO L87 Difference]: Start difference. First operand 7732 states and 10708 transitions. Second operand 5 states. [2018-11-10 07:04:59,027 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 07:04:59,027 INFO L93 Difference]: Finished difference Result 20291 states and 28216 transitions. [2018-11-10 07:04:59,028 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-10 07:04:59,028 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 171 [2018-11-10 07:04:59,028 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 07:04:59,055 INFO L225 Difference]: With dead ends: 20291 [2018-11-10 07:04:59,055 INFO L226 Difference]: Without dead ends: 12485 [2018-11-10 07:04:59,075 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 183 GetRequests, 176 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2018-11-10 07:04:59,081 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12485 states. [2018-11-10 07:04:59,601 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12485 to 11840. [2018-11-10 07:04:59,601 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11840 states. [2018-11-10 07:04:59,616 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11840 states to 11840 states and 15184 transitions. [2018-11-10 07:04:59,618 INFO L78 Accepts]: Start accepts. Automaton has 11840 states and 15184 transitions. Word has length 171 [2018-11-10 07:04:59,618 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 07:04:59,618 INFO L481 AbstractCegarLoop]: Abstraction has 11840 states and 15184 transitions. [2018-11-10 07:04:59,618 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-10 07:04:59,618 INFO L276 IsEmpty]: Start isEmpty. Operand 11840 states and 15184 transitions. [2018-11-10 07:04:59,626 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 173 [2018-11-10 07:04:59,626 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 07:04:59,626 INFO L375 BasicCegarLoop]: trace histogram [5, 5, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 07:04:59,626 INFO L424 AbstractCegarLoop]: === Iteration 21 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 07:04:59,626 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 07:04:59,626 INFO L82 PathProgramCache]: Analyzing trace with hash 786601903, now seen corresponding path program 1 times [2018-11-10 07:04:59,627 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 07:04:59,627 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 07:04:59,627 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:59,627 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 07:04:59,627 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:04:59,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:04:59,678 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 44 proven. 12 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2018-11-10 07:04:59,678 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 07:04:59,679 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_761f9461-ca5b-4fc5-9ded-29cffd327127/bin-2019/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 07:04:59,685 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 07:04:59,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:04:59,759 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 07:04:59,786 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 63 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-11-10 07:04:59,803 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-10 07:04:59,803 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [5] total 6 [2018-11-10 07:04:59,803 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-10 07:04:59,803 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-10 07:04:59,803 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-10 07:04:59,804 INFO L87 Difference]: Start difference. First operand 11840 states and 15184 transitions. Second operand 6 states. [2018-11-10 07:05:00,544 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 07:05:00,544 INFO L93 Difference]: Finished difference Result 24953 states and 32190 transitions. [2018-11-10 07:05:00,544 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-10 07:05:00,545 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 172 [2018-11-10 07:05:00,545 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 07:05:00,578 INFO L225 Difference]: With dead ends: 24953 [2018-11-10 07:05:00,578 INFO L226 Difference]: Without dead ends: 13145 [2018-11-10 07:05:00,600 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 182 GetRequests, 176 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2018-11-10 07:05:00,608 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13145 states. [2018-11-10 07:05:01,268 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13145 to 13061. [2018-11-10 07:05:01,268 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13061 states. [2018-11-10 07:05:01,282 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13061 states to 13061 states and 16047 transitions. [2018-11-10 07:05:01,284 INFO L78 Accepts]: Start accepts. Automaton has 13061 states and 16047 transitions. Word has length 172 [2018-11-10 07:05:01,284 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 07:05:01,284 INFO L481 AbstractCegarLoop]: Abstraction has 13061 states and 16047 transitions. [2018-11-10 07:05:01,284 INFO L482 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-10 07:05:01,284 INFO L276 IsEmpty]: Start isEmpty. Operand 13061 states and 16047 transitions. [2018-11-10 07:05:01,290 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 175 [2018-11-10 07:05:01,290 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 07:05:01,290 INFO L375 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 07:05:01,291 INFO L424 AbstractCegarLoop]: === Iteration 22 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 07:05:01,291 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 07:05:01,291 INFO L82 PathProgramCache]: Analyzing trace with hash -727068288, now seen corresponding path program 1 times [2018-11-10 07:05:01,291 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 07:05:01,291 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 07:05:01,291 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:05:01,292 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 07:05:01,292 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:05:01,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:05:01,359 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 46 proven. 10 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-11-10 07:05:01,360 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 07:05:01,360 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_761f9461-ca5b-4fc5-9ded-29cffd327127/bin-2019/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 07:05:01,372 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 07:05:01,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:05:01,467 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 07:05:01,490 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 35 proven. 0 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2018-11-10 07:05:01,517 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-10 07:05:01,517 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [5] total 6 [2018-11-10 07:05:01,517 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-10 07:05:01,518 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-10 07:05:01,518 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-10 07:05:01,518 INFO L87 Difference]: Start difference. First operand 13061 states and 16047 transitions. Second operand 6 states. [2018-11-10 07:05:02,232 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 07:05:02,232 INFO L93 Difference]: Finished difference Result 19350 states and 23538 transitions. [2018-11-10 07:05:02,232 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-10 07:05:02,232 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 174 [2018-11-10 07:05:02,232 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 07:05:02,244 INFO L225 Difference]: With dead ends: 19350 [2018-11-10 07:05:02,244 INFO L226 Difference]: Without dead ends: 6645 [2018-11-10 07:05:02,258 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 189 GetRequests, 180 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=34, Invalid=76, Unknown=0, NotChecked=0, Total=110 [2018-11-10 07:05:02,261 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6645 states. [2018-11-10 07:05:02,599 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6645 to 6044. [2018-11-10 07:05:02,600 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6044 states. [2018-11-10 07:05:02,604 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6044 states to 6044 states and 7046 transitions. [2018-11-10 07:05:02,605 INFO L78 Accepts]: Start accepts. Automaton has 6044 states and 7046 transitions. Word has length 174 [2018-11-10 07:05:02,605 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 07:05:02,605 INFO L481 AbstractCegarLoop]: Abstraction has 6044 states and 7046 transitions. [2018-11-10 07:05:02,605 INFO L482 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-10 07:05:02,605 INFO L276 IsEmpty]: Start isEmpty. Operand 6044 states and 7046 transitions. [2018-11-10 07:05:02,608 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 178 [2018-11-10 07:05:02,608 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 07:05:02,608 INFO L375 BasicCegarLoop]: trace histogram [6, 6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 07:05:02,608 INFO L424 AbstractCegarLoop]: === Iteration 23 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 07:05:02,608 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 07:05:02,608 INFO L82 PathProgramCache]: Analyzing trace with hash 1620284641, now seen corresponding path program 1 times [2018-11-10 07:05:02,608 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 07:05:02,608 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 07:05:02,609 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:05:02,609 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 07:05:02,609 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:05:02,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:05:02,648 INFO L134 CoverageAnalysis]: Checked inductivity of 124 backedges. 53 proven. 0 refuted. 0 times theorem prover too weak. 71 trivial. 0 not checked. [2018-11-10 07:05:02,648 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 07:05:02,648 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 07:05:02,648 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-10 07:05:02,648 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 07:05:02,648 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 07:05:02,649 INFO L87 Difference]: Start difference. First operand 6044 states and 7046 transitions. Second operand 3 states. [2018-11-10 07:05:02,790 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 07:05:02,790 INFO L93 Difference]: Finished difference Result 6047 states and 7048 transitions. [2018-11-10 07:05:02,791 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 07:05:02,791 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 177 [2018-11-10 07:05:02,791 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 07:05:02,795 INFO L225 Difference]: With dead ends: 6047 [2018-11-10 07:05:02,795 INFO L226 Difference]: Without dead ends: 4029 [2018-11-10 07:05:02,798 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 07:05:02,799 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4029 states. [2018-11-10 07:05:02,943 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4029 to 4029. [2018-11-10 07:05:02,943 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4029 states. [2018-11-10 07:05:02,947 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4029 states to 4029 states and 4721 transitions. [2018-11-10 07:05:02,947 INFO L78 Accepts]: Start accepts. Automaton has 4029 states and 4721 transitions. Word has length 177 [2018-11-10 07:05:02,948 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 07:05:02,948 INFO L481 AbstractCegarLoop]: Abstraction has 4029 states and 4721 transitions. [2018-11-10 07:05:02,948 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-10 07:05:02,948 INFO L276 IsEmpty]: Start isEmpty. Operand 4029 states and 4721 transitions. [2018-11-10 07:05:02,950 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 189 [2018-11-10 07:05:02,950 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 07:05:02,950 INFO L375 BasicCegarLoop]: trace histogram [6, 6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 07:05:02,950 INFO L424 AbstractCegarLoop]: === Iteration 24 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 07:05:02,950 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 07:05:02,950 INFO L82 PathProgramCache]: Analyzing trace with hash 1754777468, now seen corresponding path program 1 times [2018-11-10 07:05:02,951 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 07:05:02,951 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 07:05:02,951 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:05:02,951 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 07:05:02,951 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:05:02,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:05:02,986 INFO L134 CoverageAnalysis]: Checked inductivity of 125 backedges. 89 proven. 0 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-11-10 07:05:02,986 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 07:05:02,987 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 07:05:02,987 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-10 07:05:02,987 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 07:05:02,987 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 07:05:02,987 INFO L87 Difference]: Start difference. First operand 4029 states and 4721 transitions. Second operand 3 states. [2018-11-10 07:05:03,142 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 07:05:03,142 INFO L93 Difference]: Finished difference Result 6385 states and 7509 transitions. [2018-11-10 07:05:03,142 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 07:05:03,142 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 188 [2018-11-10 07:05:03,143 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 07:05:03,147 INFO L225 Difference]: With dead ends: 6385 [2018-11-10 07:05:03,147 INFO L226 Difference]: Without dead ends: 3916 [2018-11-10 07:05:03,150 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 07:05:03,151 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3916 states. [2018-11-10 07:05:03,292 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3916 to 3916. [2018-11-10 07:05:03,292 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3916 states. [2018-11-10 07:05:03,295 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3916 states to 3916 states and 4570 transitions. [2018-11-10 07:05:03,296 INFO L78 Accepts]: Start accepts. Automaton has 3916 states and 4570 transitions. Word has length 188 [2018-11-10 07:05:03,296 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 07:05:03,296 INFO L481 AbstractCegarLoop]: Abstraction has 3916 states and 4570 transitions. [2018-11-10 07:05:03,296 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-10 07:05:03,296 INFO L276 IsEmpty]: Start isEmpty. Operand 3916 states and 4570 transitions. [2018-11-10 07:05:03,298 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 199 [2018-11-10 07:05:03,299 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 07:05:03,299 INFO L375 BasicCegarLoop]: trace histogram [6, 6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 07:05:03,299 INFO L424 AbstractCegarLoop]: === Iteration 25 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 07:05:03,299 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 07:05:03,299 INFO L82 PathProgramCache]: Analyzing trace with hash 1349585374, now seen corresponding path program 1 times [2018-11-10 07:05:03,299 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 07:05:03,299 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 07:05:03,300 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:05:03,300 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 07:05:03,300 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:05:03,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:05:03,352 INFO L134 CoverageAnalysis]: Checked inductivity of 133 backedges. 98 proven. 0 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2018-11-10 07:05:03,353 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 07:05:03,353 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-10 07:05:03,353 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-10 07:05:03,353 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-10 07:05:03,353 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-10 07:05:03,353 INFO L87 Difference]: Start difference. First operand 3916 states and 4570 transitions. Second operand 4 states. [2018-11-10 07:05:03,583 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 07:05:03,583 INFO L93 Difference]: Finished difference Result 6670 states and 7839 transitions. [2018-11-10 07:05:03,583 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-10 07:05:03,583 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 198 [2018-11-10 07:05:03,583 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 07:05:03,588 INFO L225 Difference]: With dead ends: 6670 [2018-11-10 07:05:03,588 INFO L226 Difference]: Without dead ends: 4136 [2018-11-10 07:05:03,590 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-10 07:05:03,592 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4136 states. [2018-11-10 07:05:03,744 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4136 to 4115. [2018-11-10 07:05:03,744 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4115 states. [2018-11-10 07:05:03,748 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4115 states to 4115 states and 4748 transitions. [2018-11-10 07:05:03,748 INFO L78 Accepts]: Start accepts. Automaton has 4115 states and 4748 transitions. Word has length 198 [2018-11-10 07:05:03,748 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 07:05:03,749 INFO L481 AbstractCegarLoop]: Abstraction has 4115 states and 4748 transitions. [2018-11-10 07:05:03,749 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-10 07:05:03,749 INFO L276 IsEmpty]: Start isEmpty. Operand 4115 states and 4748 transitions. [2018-11-10 07:05:03,750 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 201 [2018-11-10 07:05:03,750 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 07:05:03,751 INFO L375 BasicCegarLoop]: trace histogram [6, 6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 07:05:03,751 INFO L424 AbstractCegarLoop]: === Iteration 26 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 07:05:03,751 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 07:05:03,751 INFO L82 PathProgramCache]: Analyzing trace with hash 1722736907, now seen corresponding path program 1 times [2018-11-10 07:05:03,751 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 07:05:03,751 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 07:05:03,751 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:05:03,751 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 07:05:03,752 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:05:03,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:05:03,850 INFO L134 CoverageAnalysis]: Checked inductivity of 133 backedges. 74 proven. 0 refuted. 0 times theorem prover too weak. 59 trivial. 0 not checked. [2018-11-10 07:05:03,851 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 07:05:03,851 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-10 07:05:03,851 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-10 07:05:03,851 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-10 07:05:03,851 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-10 07:05:03,852 INFO L87 Difference]: Start difference. First operand 4115 states and 4748 transitions. Second operand 4 states. [2018-11-10 07:05:04,066 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 07:05:04,066 INFO L93 Difference]: Finished difference Result 4789 states and 5487 transitions. [2018-11-10 07:05:04,066 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-10 07:05:04,066 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 200 [2018-11-10 07:05:04,067 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 07:05:04,069 INFO L225 Difference]: With dead ends: 4789 [2018-11-10 07:05:04,069 INFO L226 Difference]: Without dead ends: 2213 [2018-11-10 07:05:04,071 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-10 07:05:04,071 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2213 states. [2018-11-10 07:05:04,146 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2213 to 2082. [2018-11-10 07:05:04,146 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2082 states. [2018-11-10 07:05:04,148 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2082 states to 2082 states and 2367 transitions. [2018-11-10 07:05:04,149 INFO L78 Accepts]: Start accepts. Automaton has 2082 states and 2367 transitions. Word has length 200 [2018-11-10 07:05:04,149 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 07:05:04,149 INFO L481 AbstractCegarLoop]: Abstraction has 2082 states and 2367 transitions. [2018-11-10 07:05:04,149 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-10 07:05:04,149 INFO L276 IsEmpty]: Start isEmpty. Operand 2082 states and 2367 transitions. [2018-11-10 07:05:04,151 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 226 [2018-11-10 07:05:04,151 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 07:05:04,151 INFO L375 BasicCegarLoop]: trace histogram [6, 6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 07:05:04,151 INFO L424 AbstractCegarLoop]: === Iteration 27 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 07:05:04,152 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 07:05:04,152 INFO L82 PathProgramCache]: Analyzing trace with hash 800536731, now seen corresponding path program 1 times [2018-11-10 07:05:04,152 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 07:05:04,152 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 07:05:04,152 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:05:04,153 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 07:05:04,153 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:05:04,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:05:04,369 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 47 proven. 77 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-11-10 07:05:04,369 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 07:05:04,369 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_761f9461-ca5b-4fc5-9ded-29cffd327127/bin-2019/uautomizer/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 07:05:04,374 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 07:05:04,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:05:04,456 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 07:05:04,578 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 84 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-11-10 07:05:04,594 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-10 07:05:04,594 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [16] total 20 [2018-11-10 07:05:04,595 INFO L460 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-11-10 07:05:04,595 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-11-10 07:05:04,595 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=340, Unknown=0, NotChecked=0, Total=380 [2018-11-10 07:05:04,596 INFO L87 Difference]: Start difference. First operand 2082 states and 2367 transitions. Second operand 20 states. [2018-11-10 07:05:06,917 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 07:05:06,917 INFO L93 Difference]: Finished difference Result 2841 states and 3219 transitions. [2018-11-10 07:05:06,917 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2018-11-10 07:05:06,917 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 225 [2018-11-10 07:05:06,918 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 07:05:06,920 INFO L225 Difference]: With dead ends: 2841 [2018-11-10 07:05:06,920 INFO L226 Difference]: Without dead ends: 1689 [2018-11-10 07:05:06,921 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 330 GetRequests, 254 SyntacticMatches, 0 SemanticMatches, 76 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1681 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=762, Invalid=5244, Unknown=0, NotChecked=0, Total=6006 [2018-11-10 07:05:06,922 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1689 states. [2018-11-10 07:05:06,994 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1689 to 1593. [2018-11-10 07:05:06,994 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1593 states. [2018-11-10 07:05:06,996 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1593 states to 1593 states and 1796 transitions. [2018-11-10 07:05:06,996 INFO L78 Accepts]: Start accepts. Automaton has 1593 states and 1796 transitions. Word has length 225 [2018-11-10 07:05:06,996 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 07:05:06,996 INFO L481 AbstractCegarLoop]: Abstraction has 1593 states and 1796 transitions. [2018-11-10 07:05:06,996 INFO L482 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-11-10 07:05:06,996 INFO L276 IsEmpty]: Start isEmpty. Operand 1593 states and 1796 transitions. [2018-11-10 07:05:06,997 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 250 [2018-11-10 07:05:06,997 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 07:05:06,997 INFO L375 BasicCegarLoop]: trace histogram [6, 6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 07:05:06,997 INFO L424 AbstractCegarLoop]: === Iteration 28 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 07:05:06,998 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 07:05:06,998 INFO L82 PathProgramCache]: Analyzing trace with hash 613651828, now seen corresponding path program 1 times [2018-11-10 07:05:06,998 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 07:05:06,998 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 07:05:06,999 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:05:06,999 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 07:05:06,999 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 07:05:07,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 07:05:07,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 07:05:07,125 INFO L442 BasicCegarLoop]: Counterexample might be feasible [2018-11-10 07:05:07,257 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 10.11 07:05:07 BoogieIcfgContainer [2018-11-10 07:05:07,257 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-10 07:05:07,258 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-10 07:05:07,258 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-10 07:05:07,258 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-10 07:05:07,258 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.11 07:04:46" (3/4) ... [2018-11-10 07:05:07,262 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-11-10 07:05:07,410 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_761f9461-ca5b-4fc5-9ded-29cffd327127/bin-2019/uautomizer/witness.graphml [2018-11-10 07:05:07,410 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-10 07:05:07,411 INFO L168 Benchmark]: Toolchain (without parser) took 21379.67 ms. Allocated memory was 1.0 GB in the beginning and 2.7 GB in the end (delta: 1.7 GB). Free memory was 954.9 MB in the beginning and 1.1 GB in the end (delta: -194.5 MB). Peak memory consumption was 1.5 GB. Max. memory is 11.5 GB. [2018-11-10 07:05:07,413 INFO L168 Benchmark]: CDTParser took 0.10 ms. Allocated memory is still 1.0 GB. Free memory is still 980.1 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-10 07:05:07,413 INFO L168 Benchmark]: CACSL2BoogieTranslator took 194.04 ms. Allocated memory is still 1.0 GB. Free memory was 954.9 MB in the beginning and 938.7 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. [2018-11-10 07:05:07,413 INFO L168 Benchmark]: Boogie Preprocessor took 69.15 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 159.9 MB). Free memory was 938.7 MB in the beginning and 1.2 GB in the end (delta: -225.3 MB). Peak memory consumption was 18.5 MB. Max. memory is 11.5 GB. [2018-11-10 07:05:07,414 INFO L168 Benchmark]: RCFGBuilder took 506.30 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 57.8 MB). Peak memory consumption was 57.8 MB. Max. memory is 11.5 GB. [2018-11-10 07:05:07,414 INFO L168 Benchmark]: TraceAbstraction took 20455.05 ms. Allocated memory was 1.2 GB in the beginning and 2.7 GB in the end (delta: 1.6 GB). Free memory was 1.1 GB in the beginning and 1.2 GB in the end (delta: -117.8 MB). Peak memory consumption was 1.4 GB. Max. memory is 11.5 GB. [2018-11-10 07:05:07,414 INFO L168 Benchmark]: Witness Printer took 152.46 ms. Allocated memory is still 2.7 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 71.3 MB). Peak memory consumption was 71.3 MB. Max. memory is 11.5 GB. [2018-11-10 07:05:07,416 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.10 ms. Allocated memory is still 1.0 GB. Free memory is still 980.1 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 194.04 ms. Allocated memory is still 1.0 GB. Free memory was 954.9 MB in the beginning and 938.7 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 69.15 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 159.9 MB). Free memory was 938.7 MB in the beginning and 1.2 GB in the end (delta: -225.3 MB). Peak memory consumption was 18.5 MB. Max. memory is 11.5 GB. * RCFGBuilder took 506.30 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 57.8 MB). Peak memory consumption was 57.8 MB. Max. memory is 11.5 GB. * TraceAbstraction took 20455.05 ms. Allocated memory was 1.2 GB in the beginning and 2.7 GB in the end (delta: 1.6 GB). Free memory was 1.1 GB in the beginning and 1.2 GB in the end (delta: -117.8 MB). Peak memory consumption was 1.4 GB. Max. memory is 11.5 GB. * Witness Printer took 152.46 ms. Allocated memory is still 2.7 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 71.3 MB). Peak memory consumption was 71.3 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 13]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L18] int c ; [L19] int c_t ; [L20] int c_req_up ; [L21] int p_in ; [L22] int p_out ; [L23] int wl_st ; [L24] int c1_st ; [L25] int c2_st ; [L26] int wb_st ; [L27] int r_st ; [L28] int wl_i ; [L29] int c1_i ; [L30] int c2_i ; [L31] int wb_i ; [L32] int r_i ; [L33] int wl_pc ; [L34] int c1_pc ; [L35] int c2_pc ; [L36] int wb_pc ; [L37] int e_e ; [L38] int e_f ; [L39] int e_g ; [L40] int e_c ; [L41] int e_p_in ; [L42] int e_wl ; [L48] int d ; [L49] int data ; [L50] int processed ; [L51] static int t_b ; VAL [\old(c)=17, \old(c1_i)=4, \old(c1_pc)=29, \old(c1_st)=24, \old(c2_i)=14, \old(c2_pc)=28, \old(c2_st)=25, \old(c_req_up)=30, \old(c_t)=20, \old(d)=23, \old(data)=18, \old(e_c)=11, \old(e_e)=31, \old(e_f)=21, \old(e_g)=10, \old(e_p_in)=8, \old(e_wl)=13, \old(p_in)=15, \old(p_out)=9, \old(processed)=16, \old(r_i)=26, \old(r_st)=7, \old(t_b)=12, \old(wb_i)=5, \old(wb_pc)=19, \old(wb_st)=3, \old(wl_i)=27, \old(wl_pc)=22, \old(wl_st)=6, c=0, c1_i=0, c1_pc=0, c1_st=0, c2_i=0, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=0, e_e=0, e_f=0, e_g=0, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=0, wb_pc=0, wb_st=0, wl_i=0, wl_pc=0, wl_st=0] [L679] int __retres1 ; [L683] e_wl = 2 [L684] e_c = e_wl [L685] e_g = e_c [L686] e_f = e_g [L687] e_e = e_f [L688] wl_pc = 0 [L689] c1_pc = 0 [L690] c2_pc = 0 [L691] wb_pc = 0 [L692] wb_i = 1 [L693] c2_i = wb_i [L694] c1_i = c2_i [L695] wl_i = c1_i [L696] r_i = 0 [L697] c_req_up = 0 [L698] d = 0 [L699] c = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=0, \old(e_e)=0, \old(e_f)=0, \old(e_g)=0, \old(e_wl)=0, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L700] CALL start_simulation() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L390] int kernel_st ; [L393] kernel_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L394] COND FALSE !((int )c_req_up == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L405] COND TRUE (int )wl_i == 1 [L406] wl_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L410] COND TRUE (int )c1_i == 1 [L411] c1_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L415] COND TRUE (int )c2_i == 1 [L416] c2_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L420] COND TRUE (int )wb_i == 1 [L421] wb_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L425] COND FALSE !((int )r_i == 1) [L428] r_st = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L430] COND FALSE !((int )e_f == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L435] COND FALSE !((int )e_g == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L440] COND FALSE !((int )e_e == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L445] COND FALSE !((int )e_c == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L450] COND FALSE !((int )e_wl == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L455] COND FALSE !((int )wl_pc == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L463] COND FALSE !((int )wl_pc == 2) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L473] COND FALSE !((int )c1_pc == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L482] COND FALSE !((int )c2_pc == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L491] COND FALSE !((int )wb_pc == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L500] COND FALSE !((int )e_c == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L505] COND FALSE !((int )e_e == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L510] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L515] COND FALSE !((int )e_g == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L520] COND FALSE !((int )e_c == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L525] COND FALSE !((int )e_wl == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L531] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L534] kernel_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L535] CALL eval() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L276] int tmp ; [L277] int tmp___0 ; [L278] int tmp___1 ; [L279] int tmp___2 ; [L280] int tmp___3 ; VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L284] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L286] COND TRUE (int )wl_st == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L307] COND TRUE (int )wl_st == 0 [L309] tmp = __VERIFIER_nondet_int() [L311] COND TRUE \read(tmp) [L313] wl_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L314] CALL write_loop() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=1, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L53] int t ; VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=1, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L56] COND TRUE (int )wl_pc == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=1, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L70] wl_st = 2 [L71] wl_pc = 1 [L72] RET e_wl = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=1, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L314] write_loop() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L322] COND TRUE (int )c1_st == 0 [L324] tmp___0 = __VERIFIER_nondet_int() [L326] COND TRUE \read(tmp___0) [L328] c1_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L329] CALL compute1() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L127] COND TRUE (int )c1_pc == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L138] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L140] c1_st = 2 [L141] RET c1_pc = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L329] compute1() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L337] COND TRUE (int )c2_st == 0 [L339] tmp___1 = __VERIFIER_nondet_int() [L341] COND TRUE \read(tmp___1) [L343] c2_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L344] CALL compute2() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L172] COND TRUE (int )c2_pc == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L183] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L185] c2_st = 2 [L186] RET c2_pc = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L344] compute2() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L352] COND TRUE (int )wb_st == 0 [L354] tmp___2 = __VERIFIER_nondet_int() [L356] COND TRUE \read(tmp___2) [L358] wb_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L359] CALL write_back() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L217] COND TRUE (int )wb_pc == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L228] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L230] wb_st = 2 [L231] RET wb_pc = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L359] write_back() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L367] COND FALSE !((int )r_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L284] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L286] COND FALSE !((int )wl_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L289] COND FALSE !((int )c1_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L292] COND FALSE !((int )c2_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L295] COND FALSE !((int )wb_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L298] COND FALSE, RET !((int )r_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L535] eval() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L537] kernel_st = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L538] COND FALSE !((int )c_req_up == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L549] kernel_st = 3 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L550] COND FALSE !((int )e_f == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L555] COND FALSE !((int )e_g == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L560] COND FALSE !((int )e_e == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L565] COND FALSE !((int )e_c == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L570] COND TRUE (int )e_wl == 0 [L571] e_wl = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L575] COND TRUE (int )wl_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L576] COND TRUE (int )e_wl == 1 [L577] wl_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L593] COND TRUE (int )c1_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L594] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L602] COND TRUE (int )c2_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L603] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L611] COND TRUE (int )wb_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L612] COND FALSE !((int )e_g == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L620] COND FALSE !((int )e_c == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L625] COND FALSE !((int )e_e == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L630] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L635] COND FALSE !((int )e_g == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L640] COND FALSE !((int )e_c == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L645] COND TRUE (int )e_wl == 1 [L646] e_wl = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L650] COND TRUE (int )wl_st == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L531] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L534] kernel_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L535] CALL eval() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L276] int tmp ; [L277] int tmp___0 ; [L278] int tmp___1 ; [L279] int tmp___2 ; [L280] int tmp___3 ; VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L284] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L286] COND TRUE (int )wl_st == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L307] COND TRUE (int )wl_st == 0 [L309] tmp = __VERIFIER_nondet_int() [L311] COND TRUE \read(tmp) [L313] wl_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L314] CALL write_loop() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L53] int t ; VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L56] COND FALSE !((int )wl_pc == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L59] COND FALSE !((int )wl_pc == 2) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L62] COND TRUE (int )wl_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L77] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L79] t = d [L80] data = d [L81] processed = 0 [L82] e_f = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L83] COND TRUE (int )c1_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L84] COND TRUE (int )e_f == 1 [L85] c1_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L92] COND TRUE (int )c2_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L93] COND TRUE (int )e_f == 1 [L94] c2_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L101] e_f = 2 [L102] wl_st = 2 [L103] wl_pc = 2 [L104] RET t_b = t VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L314] write_loop() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L322] COND TRUE (int )c1_st == 0 [L324] tmp___0 = __VERIFIER_nondet_int() [L326] COND TRUE \read(tmp___0) [L328] c1_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L329] CALL compute1() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L127] COND FALSE !((int )c1_pc == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L130] COND TRUE (int )c1_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L145] COND TRUE ! processed [L146] data += 1 [L147] e_g = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L148] COND TRUE (int )wb_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L149] COND TRUE (int )e_g == 1 [L150] wb_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L157] e_g = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L138] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L140] c1_st = 2 [L141] RET c1_pc = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L329] compute1() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L337] COND TRUE (int )c2_st == 0 [L339] tmp___1 = __VERIFIER_nondet_int() [L341] COND TRUE \read(tmp___1) [L343] c2_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L344] CALL compute2() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L172] COND FALSE !((int )c2_pc == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L175] COND TRUE (int )c2_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L190] COND TRUE ! processed [L191] data += 1 [L192] e_g = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L193] COND TRUE (int )wb_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L194] COND TRUE (int )e_g == 1 [L195] wb_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L202] e_g = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L183] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L185] c2_st = 2 [L186] RET c2_pc = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L344] compute2() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L352] COND TRUE (int )wb_st == 0 [L354] tmp___2 = __VERIFIER_nondet_int() [L356] COND TRUE \read(tmp___2) [L358] wb_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L359] CALL write_back() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L217] COND FALSE !((int )wb_pc == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L220] COND TRUE (int )wb_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L235] c_t = data [L236] c_req_up = 1 [L237] processed = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L228] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L230] wb_st = 2 [L231] RET wb_pc = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L359] write_back() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L367] COND FALSE !((int )r_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L284] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L286] COND FALSE !((int )wl_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L289] COND FALSE !((int )c1_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L292] COND FALSE !((int )c2_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L295] COND FALSE !((int )wb_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L298] COND FALSE, RET !((int )r_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L535] eval() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=1, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L537] kernel_st = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L538] COND TRUE (int )c_req_up == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L539] COND TRUE c != c_t [L540] c = c_t [L541] e_c = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L545] c_req_up = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L549] kernel_st = 3 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L550] COND FALSE !((int )e_f == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L555] COND FALSE !((int )e_g == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L560] COND FALSE !((int )e_e == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L565] COND TRUE (int )e_c == 0 [L566] e_c = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L570] COND FALSE !((int )e_wl == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L575] COND FALSE !((int )wl_pc == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L583] COND TRUE (int )wl_pc == 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L584] COND FALSE !((int )e_e == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L593] COND TRUE (int )c1_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L594] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L602] COND TRUE (int )c2_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L603] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L611] COND TRUE (int )wb_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L612] COND FALSE !((int )e_g == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L620] COND TRUE (int )e_c == 1 [L621] r_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L625] COND FALSE !((int )e_e == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L630] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L635] COND FALSE !((int )e_g == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L640] COND TRUE (int )e_c == 1 [L641] e_c = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L645] COND FALSE !((int )e_wl == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L650] COND FALSE !((int )wl_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L653] COND FALSE !((int )c1_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L656] COND FALSE !((int )c2_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L659] COND FALSE !((int )wb_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L662] COND TRUE (int )r_st == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L531] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L534] kernel_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=1, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L535] CALL eval() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L276] int tmp ; [L277] int tmp___0 ; [L278] int tmp___1 ; [L279] int tmp___2 ; [L280] int tmp___3 ; VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L284] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L286] COND FALSE !((int )wl_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L289] COND FALSE !((int )c1_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L292] COND FALSE !((int )c2_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L295] COND FALSE !((int )wb_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L298] COND TRUE (int )r_st == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L307] COND FALSE !((int )wl_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L322] COND FALSE !((int )c1_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L337] COND FALSE !((int )c2_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L352] COND FALSE !((int )wb_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L367] COND TRUE (int )r_st == 0 [L369] tmp___3 = __VERIFIER_nondet_int() [L371] COND TRUE \read(tmp___3) [L373] r_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, tmp___3=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L374] CALL read() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=1, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L249] d = c [L250] e_e = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=1, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L251] COND FALSE !((int )wl_pc == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=1, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L259] COND TRUE (int )wl_pc == 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=1, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L260] COND TRUE (int )e_e == 1 [L261] wl_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=1, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L269] e_e = 2 [L270] RET r_st = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=1, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L374] read() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp___3=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L284] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp___3=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L286] COND TRUE (int )wl_st == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp___3=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L307] COND TRUE (int )wl_st == 0 [L309] tmp = __VERIFIER_nondet_int() [L311] COND TRUE \read(tmp) [L313] wl_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___3=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L314] CALL write_loop() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L53] int t ; VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L56] COND FALSE !((int )wl_pc == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L59] COND TRUE (int )wl_pc == 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L108] t = t_b VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L109] COND FALSE !(d == t + 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L113] CALL error() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L13] __VERIFIER_error() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 11 procedures, 164 locations, 1 error locations. UNSAFE Result, 20.4s OverallTime, 28 OverallIterations, 6 TraceHistogramMax, 11.8s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 7864 SDtfs, 15366 SDslu, 11376 SDs, 0 SdLazy, 7561 SolverSat, 1811 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 4.2s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 1574 GetRequests, 1378 SyntacticMatches, 8 SemanticMatches, 188 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1856 ImplicationChecksByTransitivity, 2.0s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=13061occurred in iteration=21, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 5.0s AutomataMinimizationTime, 27 MinimizatonAttempts, 6497 StatesRemovedByMinimization, 21 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.2s SsaConstructionTime, 0.7s SatisfiabilityAnalysisTime, 1.6s InterpolantComputationTime, 4700 NumberOfCodeBlocks, 4700 NumberOfCodeBlocksAsserted, 36 NumberOfCheckSat, 4416 ConstructedInterpolants, 0 QuantifiedInterpolants, 1259825 SizeOfPredicates, 6 NumberOfNonLiveVariables, 8066 ConjunctsInSsa, 38 ConjunctsInUnsatCore, 35 InterpolantComputations, 27 PerfectInterpolantSequences, 1833/1968 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...