./Ultimate.py --spec ../../sv-benchmarks/c/ReachSafety.prp --file ../../sv-benchmarks/c/systemc/transmitter.03_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 1dbac8bc Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_09fd18e7-b77b-4718-afeb-627057a89c31/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_09fd18e7-b77b-4718-afeb-627057a89c31/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_09fd18e7-b77b-4718-afeb-627057a89c31/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_09fd18e7-b77b-4718-afeb-627057a89c31/bin-2019/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.03_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_09fd18e7-b77b-4718-afeb-627057a89c31/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_09fd18e7-b77b-4718-afeb-627057a89c31/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 447c919af4e106e36f468570351956f4c77293d2 .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-1dbac8b [2018-11-10 08:33:45,074 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-10 08:33:45,075 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-10 08:33:45,083 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-10 08:33:45,083 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-10 08:33:45,084 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-10 08:33:45,085 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-10 08:33:45,086 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-10 08:33:45,087 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-10 08:33:45,088 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-10 08:33:45,088 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-10 08:33:45,089 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-10 08:33:45,089 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-10 08:33:45,090 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-10 08:33:45,091 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-10 08:33:45,091 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-10 08:33:45,092 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-10 08:33:45,093 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-10 08:33:45,094 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-10 08:33:45,096 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-10 08:33:45,096 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-10 08:33:45,097 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-10 08:33:45,099 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-10 08:33:45,099 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-10 08:33:45,099 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-10 08:33:45,100 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-10 08:33:45,100 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-10 08:33:45,101 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-10 08:33:45,101 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-10 08:33:45,102 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-10 08:33:45,102 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-10 08:33:45,103 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-10 08:33:45,103 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-10 08:33:45,103 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-10 08:33:45,104 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-10 08:33:45,104 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-10 08:33:45,104 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_09fd18e7-b77b-4718-afeb-627057a89c31/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2018-11-10 08:33:45,114 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-10 08:33:45,115 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-10 08:33:45,115 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-10 08:33:45,115 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-11-10 08:33:45,116 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-10 08:33:45,116 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-10 08:33:45,116 INFO L133 SettingsManager]: * Use SBE=true [2018-11-10 08:33:45,116 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-10 08:33:45,117 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-10 08:33:45,117 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-10 08:33:45,117 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-10 08:33:45,117 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-10 08:33:45,117 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-10 08:33:45,117 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-10 08:33:45,117 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-10 08:33:45,117 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-10 08:33:45,118 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-10 08:33:45,118 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-10 08:33:45,118 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-10 08:33:45,118 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-10 08:33:45,118 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-10 08:33:45,118 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-10 08:33:45,118 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-10 08:33:45,119 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-10 08:33:45,119 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-10 08:33:45,119 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-10 08:33:45,119 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-10 08:33:45,119 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-10 08:33:45,119 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-10 08:33:45,120 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_09fd18e7-b77b-4718-afeb-627057a89c31/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 447c919af4e106e36f468570351956f4c77293d2 [2018-11-10 08:33:45,140 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-10 08:33:45,149 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-10 08:33:45,152 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-10 08:33:45,153 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-10 08:33:45,153 INFO L276 PluginConnector]: CDTParser initialized [2018-11-10 08:33:45,154 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_09fd18e7-b77b-4718-afeb-627057a89c31/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/transmitter.03_false-unreach-call_false-termination.cil.c [2018-11-10 08:33:45,198 INFO L218 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_09fd18e7-b77b-4718-afeb-627057a89c31/bin-2019/uautomizer/data/185f46ce6/e8d1593d2f6e4d16bdb359aecab25734/FLAGcb4445a27 [2018-11-10 08:33:45,509 INFO L298 CDTParser]: Found 1 translation units. [2018-11-10 08:33:45,510 INFO L158 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_09fd18e7-b77b-4718-afeb-627057a89c31/sv-benchmarks/c/systemc/transmitter.03_false-unreach-call_false-termination.cil.c [2018-11-10 08:33:45,518 INFO L346 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_09fd18e7-b77b-4718-afeb-627057a89c31/bin-2019/uautomizer/data/185f46ce6/e8d1593d2f6e4d16bdb359aecab25734/FLAGcb4445a27 [2018-11-10 08:33:45,529 INFO L354 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_09fd18e7-b77b-4718-afeb-627057a89c31/bin-2019/uautomizer/data/185f46ce6/e8d1593d2f6e4d16bdb359aecab25734 [2018-11-10 08:33:45,532 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-10 08:33:45,533 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-11-10 08:33:45,534 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-10 08:33:45,534 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-10 08:33:45,537 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-10 08:33:45,538 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.11 08:33:45" (1/1) ... [2018-11-10 08:33:45,540 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@49481402 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 08:33:45, skipping insertion in model container [2018-11-10 08:33:45,540 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.11 08:33:45" (1/1) ... [2018-11-10 08:33:45,548 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-10 08:33:45,575 INFO L174 MainTranslator]: Built tables and reachable declarations [2018-11-10 08:33:45,726 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-11-10 08:33:45,730 INFO L189 MainTranslator]: Completed pre-run [2018-11-10 08:33:45,754 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-11-10 08:33:45,764 INFO L193 MainTranslator]: Completed translation [2018-11-10 08:33:45,764 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 08:33:45 WrapperNode [2018-11-10 08:33:45,765 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-10 08:33:45,765 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-10 08:33:45,765 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-10 08:33:45,765 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-10 08:33:45,773 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 08:33:45" (1/1) ... [2018-11-10 08:33:45,773 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 08:33:45" (1/1) ... [2018-11-10 08:33:45,777 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 08:33:45" (1/1) ... [2018-11-10 08:33:45,778 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 08:33:45" (1/1) ... [2018-11-10 08:33:45,782 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 08:33:45" (1/1) ... [2018-11-10 08:33:45,789 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 08:33:45" (1/1) ... [2018-11-10 08:33:45,790 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 08:33:45" (1/1) ... [2018-11-10 08:33:45,792 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-10 08:33:45,792 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-10 08:33:45,792 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-10 08:33:45,792 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-10 08:33:45,792 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 08:33:45" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_09fd18e7-b77b-4718-afeb-627057a89c31/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-10 08:33:45,867 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-10 08:33:45,867 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-10 08:33:45,867 INFO L138 BoogieDeclarations]: Found implementation of procedure error [2018-11-10 08:33:45,867 INFO L138 BoogieDeclarations]: Found implementation of procedure master [2018-11-10 08:33:45,867 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit1 [2018-11-10 08:33:45,867 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit2 [2018-11-10 08:33:45,867 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit3 [2018-11-10 08:33:45,868 INFO L138 BoogieDeclarations]: Found implementation of procedure is_master_triggered [2018-11-10 08:33:45,868 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit1_triggered [2018-11-10 08:33:45,868 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit2_triggered [2018-11-10 08:33:45,868 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit3_triggered [2018-11-10 08:33:45,868 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels [2018-11-10 08:33:45,868 INFO L138 BoogieDeclarations]: Found implementation of procedure init_threads [2018-11-10 08:33:45,868 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread [2018-11-10 08:33:45,869 INFO L138 BoogieDeclarations]: Found implementation of procedure eval [2018-11-10 08:33:45,869 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events [2018-11-10 08:33:45,869 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events [2018-11-10 08:33:45,869 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads [2018-11-10 08:33:45,869 INFO L138 BoogieDeclarations]: Found implementation of procedure immediate_notify [2018-11-10 08:33:45,869 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_time_events [2018-11-10 08:33:45,869 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_time_events [2018-11-10 08:33:45,869 INFO L138 BoogieDeclarations]: Found implementation of procedure init_model [2018-11-10 08:33:45,870 INFO L138 BoogieDeclarations]: Found implementation of procedure stop_simulation [2018-11-10 08:33:45,870 INFO L138 BoogieDeclarations]: Found implementation of procedure start_simulation [2018-11-10 08:33:45,870 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-10 08:33:45,870 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-11-10 08:33:45,870 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-11-10 08:33:45,870 INFO L130 BoogieDeclarations]: Found specification of procedure error [2018-11-10 08:33:45,870 INFO L130 BoogieDeclarations]: Found specification of procedure is_master_triggered [2018-11-10 08:33:45,870 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit1_triggered [2018-11-10 08:33:45,870 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit2_triggered [2018-11-10 08:33:45,870 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit3_triggered [2018-11-10 08:33:45,871 INFO L130 BoogieDeclarations]: Found specification of procedure immediate_notify [2018-11-10 08:33:45,871 INFO L130 BoogieDeclarations]: Found specification of procedure master [2018-11-10 08:33:45,871 INFO L130 BoogieDeclarations]: Found specification of procedure transmit1 [2018-11-10 08:33:45,871 INFO L130 BoogieDeclarations]: Found specification of procedure transmit2 [2018-11-10 08:33:45,871 INFO L130 BoogieDeclarations]: Found specification of procedure transmit3 [2018-11-10 08:33:45,871 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels [2018-11-10 08:33:45,871 INFO L130 BoogieDeclarations]: Found specification of procedure init_threads [2018-11-10 08:33:45,871 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread [2018-11-10 08:33:45,871 INFO L130 BoogieDeclarations]: Found specification of procedure eval [2018-11-10 08:33:45,871 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events [2018-11-10 08:33:45,872 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events [2018-11-10 08:33:45,872 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads [2018-11-10 08:33:45,872 INFO L130 BoogieDeclarations]: Found specification of procedure fire_time_events [2018-11-10 08:33:45,872 INFO L130 BoogieDeclarations]: Found specification of procedure reset_time_events [2018-11-10 08:33:45,872 INFO L130 BoogieDeclarations]: Found specification of procedure init_model [2018-11-10 08:33:45,872 INFO L130 BoogieDeclarations]: Found specification of procedure stop_simulation [2018-11-10 08:33:45,872 INFO L130 BoogieDeclarations]: Found specification of procedure start_simulation [2018-11-10 08:33:45,872 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-10 08:33:45,872 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-10 08:33:45,872 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-10 08:33:46,247 INFO L341 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-10 08:33:46,247 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.11 08:33:46 BoogieIcfgContainer [2018-11-10 08:33:46,247 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-10 08:33:46,248 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-10 08:33:46,248 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-10 08:33:46,250 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-10 08:33:46,250 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 10.11 08:33:45" (1/3) ... [2018-11-10 08:33:46,250 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@c1ca145 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 10.11 08:33:46, skipping insertion in model container [2018-11-10 08:33:46,250 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 08:33:45" (2/3) ... [2018-11-10 08:33:46,250 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@c1ca145 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 10.11 08:33:46, skipping insertion in model container [2018-11-10 08:33:46,251 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.11 08:33:46" (3/3) ... [2018-11-10 08:33:46,252 INFO L112 eAbstractionObserver]: Analyzing ICFG transmitter.03_false-unreach-call_false-termination.cil.c [2018-11-10 08:33:46,257 INFO L136 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-10 08:33:46,262 INFO L148 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-10 08:33:46,271 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-10 08:33:46,291 INFO L135 ementStrategyFactory]: Using default assertion order modulation [2018-11-10 08:33:46,291 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-10 08:33:46,291 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-10 08:33:46,291 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-10 08:33:46,291 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-10 08:33:46,292 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-10 08:33:46,292 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-10 08:33:46,292 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-10 08:33:46,292 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-10 08:33:46,307 INFO L276 IsEmpty]: Start isEmpty. Operand 206 states. [2018-11-10 08:33:46,314 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2018-11-10 08:33:46,314 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 08:33:46,315 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:33:46,317 INFO L424 AbstractCegarLoop]: === Iteration 1 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 08:33:46,320 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:33:46,320 INFO L82 PathProgramCache]: Analyzing trace with hash 391396075, now seen corresponding path program 1 times [2018-11-10 08:33:46,322 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:33:46,322 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:33:46,358 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:46,359 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:33:46,359 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:46,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:33:46,564 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 08:33:46,566 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 08:33:46,566 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 08:33:46,570 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-10 08:33:46,581 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 08:33:46,581 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 08:33:46,583 INFO L87 Difference]: Start difference. First operand 206 states. Second operand 5 states. [2018-11-10 08:33:47,018 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 08:33:47,018 INFO L93 Difference]: Finished difference Result 427 states and 625 transitions. [2018-11-10 08:33:47,018 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-10 08:33:47,019 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 107 [2018-11-10 08:33:47,020 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 08:33:47,030 INFO L225 Difference]: With dead ends: 427 [2018-11-10 08:33:47,030 INFO L226 Difference]: Without dead ends: 230 [2018-11-10 08:33:47,034 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-10 08:33:47,045 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 230 states. [2018-11-10 08:33:47,080 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 230 to 197. [2018-11-10 08:33:47,081 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 197 states. [2018-11-10 08:33:47,083 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 197 states to 197 states and 265 transitions. [2018-11-10 08:33:47,085 INFO L78 Accepts]: Start accepts. Automaton has 197 states and 265 transitions. Word has length 107 [2018-11-10 08:33:47,085 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 08:33:47,085 INFO L481 AbstractCegarLoop]: Abstraction has 197 states and 265 transitions. [2018-11-10 08:33:47,085 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-10 08:33:47,085 INFO L276 IsEmpty]: Start isEmpty. Operand 197 states and 265 transitions. [2018-11-10 08:33:47,088 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2018-11-10 08:33:47,088 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 08:33:47,089 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:33:47,089 INFO L424 AbstractCegarLoop]: === Iteration 2 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 08:33:47,089 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:33:47,089 INFO L82 PathProgramCache]: Analyzing trace with hash -1487734871, now seen corresponding path program 1 times [2018-11-10 08:33:47,089 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:33:47,090 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:33:47,090 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:47,091 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:33:47,091 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:47,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:33:47,199 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 08:33:47,199 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 08:33:47,199 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 08:33:47,200 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-10 08:33:47,201 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 08:33:47,201 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 08:33:47,201 INFO L87 Difference]: Start difference. First operand 197 states and 265 transitions. Second operand 5 states. [2018-11-10 08:33:47,480 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 08:33:47,480 INFO L93 Difference]: Finished difference Result 406 states and 563 transitions. [2018-11-10 08:33:47,481 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-10 08:33:47,481 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 107 [2018-11-10 08:33:47,481 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 08:33:47,483 INFO L225 Difference]: With dead ends: 406 [2018-11-10 08:33:47,483 INFO L226 Difference]: Without dead ends: 230 [2018-11-10 08:33:47,484 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-10 08:33:47,485 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 230 states. [2018-11-10 08:33:47,498 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 230 to 197. [2018-11-10 08:33:47,498 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 197 states. [2018-11-10 08:33:47,499 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 197 states to 197 states and 264 transitions. [2018-11-10 08:33:47,500 INFO L78 Accepts]: Start accepts. Automaton has 197 states and 264 transitions. Word has length 107 [2018-11-10 08:33:47,500 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 08:33:47,500 INFO L481 AbstractCegarLoop]: Abstraction has 197 states and 264 transitions. [2018-11-10 08:33:47,500 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-10 08:33:47,500 INFO L276 IsEmpty]: Start isEmpty. Operand 197 states and 264 transitions. [2018-11-10 08:33:47,501 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2018-11-10 08:33:47,501 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 08:33:47,501 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:33:47,502 INFO L424 AbstractCegarLoop]: === Iteration 3 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 08:33:47,502 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:33:47,502 INFO L82 PathProgramCache]: Analyzing trace with hash -162878677, now seen corresponding path program 1 times [2018-11-10 08:33:47,502 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:33:47,502 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:33:47,503 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:47,503 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:33:47,503 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:47,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:33:47,585 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 08:33:47,585 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 08:33:47,585 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 08:33:47,586 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-10 08:33:47,586 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 08:33:47,586 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 08:33:47,586 INFO L87 Difference]: Start difference. First operand 197 states and 264 transitions. Second operand 5 states. [2018-11-10 08:33:47,863 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 08:33:47,863 INFO L93 Difference]: Finished difference Result 404 states and 557 transitions. [2018-11-10 08:33:47,864 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-10 08:33:47,864 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 107 [2018-11-10 08:33:47,864 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 08:33:47,865 INFO L225 Difference]: With dead ends: 404 [2018-11-10 08:33:47,866 INFO L226 Difference]: Without dead ends: 228 [2018-11-10 08:33:47,867 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-10 08:33:47,867 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 228 states. [2018-11-10 08:33:47,882 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 228 to 197. [2018-11-10 08:33:47,882 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 197 states. [2018-11-10 08:33:47,883 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 197 states to 197 states and 263 transitions. [2018-11-10 08:33:47,883 INFO L78 Accepts]: Start accepts. Automaton has 197 states and 263 transitions. Word has length 107 [2018-11-10 08:33:47,883 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 08:33:47,884 INFO L481 AbstractCegarLoop]: Abstraction has 197 states and 263 transitions. [2018-11-10 08:33:47,884 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-10 08:33:47,884 INFO L276 IsEmpty]: Start isEmpty. Operand 197 states and 263 transitions. [2018-11-10 08:33:47,885 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2018-11-10 08:33:47,885 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 08:33:47,885 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:33:47,887 INFO L424 AbstractCegarLoop]: === Iteration 4 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 08:33:47,887 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:33:47,888 INFO L82 PathProgramCache]: Analyzing trace with hash 1403879273, now seen corresponding path program 1 times [2018-11-10 08:33:47,888 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:33:47,888 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:33:47,888 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:47,888 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:33:47,888 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:47,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:33:47,951 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 08:33:47,951 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 08:33:47,951 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 08:33:47,952 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-10 08:33:47,952 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 08:33:47,952 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 08:33:47,952 INFO L87 Difference]: Start difference. First operand 197 states and 263 transitions. Second operand 5 states. [2018-11-10 08:33:48,170 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 08:33:48,170 INFO L93 Difference]: Finished difference Result 424 states and 587 transitions. [2018-11-10 08:33:48,171 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-10 08:33:48,171 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 107 [2018-11-10 08:33:48,174 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 08:33:48,175 INFO L225 Difference]: With dead ends: 424 [2018-11-10 08:33:48,175 INFO L226 Difference]: Without dead ends: 248 [2018-11-10 08:33:48,176 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-10 08:33:48,176 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 248 states. [2018-11-10 08:33:48,192 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 248 to 197. [2018-11-10 08:33:48,192 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 197 states. [2018-11-10 08:33:48,194 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 197 states to 197 states and 262 transitions. [2018-11-10 08:33:48,194 INFO L78 Accepts]: Start accepts. Automaton has 197 states and 262 transitions. Word has length 107 [2018-11-10 08:33:48,194 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 08:33:48,194 INFO L481 AbstractCegarLoop]: Abstraction has 197 states and 262 transitions. [2018-11-10 08:33:48,195 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-10 08:33:48,195 INFO L276 IsEmpty]: Start isEmpty. Operand 197 states and 262 transitions. [2018-11-10 08:33:48,196 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2018-11-10 08:33:48,196 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 08:33:48,196 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:33:48,196 INFO L424 AbstractCegarLoop]: === Iteration 5 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 08:33:48,197 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:33:48,197 INFO L82 PathProgramCache]: Analyzing trace with hash 261376807, now seen corresponding path program 1 times [2018-11-10 08:33:48,197 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:33:48,197 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:33:48,198 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:48,198 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:33:48,198 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:48,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:33:48,265 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 08:33:48,265 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 08:33:48,265 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 08:33:48,265 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-10 08:33:48,266 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 08:33:48,266 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 08:33:48,266 INFO L87 Difference]: Start difference. First operand 197 states and 262 transitions. Second operand 5 states. [2018-11-10 08:33:48,490 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 08:33:48,490 INFO L93 Difference]: Finished difference Result 422 states and 581 transitions. [2018-11-10 08:33:48,491 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-10 08:33:48,491 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 107 [2018-11-10 08:33:48,491 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 08:33:48,492 INFO L225 Difference]: With dead ends: 422 [2018-11-10 08:33:48,492 INFO L226 Difference]: Without dead ends: 246 [2018-11-10 08:33:48,493 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-10 08:33:48,493 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 246 states. [2018-11-10 08:33:48,505 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 246 to 197. [2018-11-10 08:33:48,505 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 197 states. [2018-11-10 08:33:48,506 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 197 states to 197 states and 261 transitions. [2018-11-10 08:33:48,506 INFO L78 Accepts]: Start accepts. Automaton has 197 states and 261 transitions. Word has length 107 [2018-11-10 08:33:48,507 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 08:33:48,507 INFO L481 AbstractCegarLoop]: Abstraction has 197 states and 261 transitions. [2018-11-10 08:33:48,507 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-10 08:33:48,507 INFO L276 IsEmpty]: Start isEmpty. Operand 197 states and 261 transitions. [2018-11-10 08:33:48,508 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2018-11-10 08:33:48,508 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 08:33:48,508 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:33:48,508 INFO L424 AbstractCegarLoop]: === Iteration 6 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 08:33:48,508 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:33:48,509 INFO L82 PathProgramCache]: Analyzing trace with hash 501616553, now seen corresponding path program 1 times [2018-11-10 08:33:48,509 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:33:48,509 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:33:48,509 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:48,509 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:33:48,510 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:48,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:33:48,568 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 08:33:48,569 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 08:33:48,569 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 08:33:48,569 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-10 08:33:48,569 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 08:33:48,569 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 08:33:48,569 INFO L87 Difference]: Start difference. First operand 197 states and 261 transitions. Second operand 5 states. [2018-11-10 08:33:48,800 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 08:33:48,800 INFO L93 Difference]: Finished difference Result 420 states and 575 transitions. [2018-11-10 08:33:48,801 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-10 08:33:48,801 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 107 [2018-11-10 08:33:48,801 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 08:33:48,802 INFO L225 Difference]: With dead ends: 420 [2018-11-10 08:33:48,802 INFO L226 Difference]: Without dead ends: 244 [2018-11-10 08:33:48,803 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-10 08:33:48,803 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 244 states. [2018-11-10 08:33:48,816 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 244 to 197. [2018-11-10 08:33:48,816 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 197 states. [2018-11-10 08:33:48,817 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 197 states to 197 states and 260 transitions. [2018-11-10 08:33:48,817 INFO L78 Accepts]: Start accepts. Automaton has 197 states and 260 transitions. Word has length 107 [2018-11-10 08:33:48,818 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 08:33:48,818 INFO L481 AbstractCegarLoop]: Abstraction has 197 states and 260 transitions. [2018-11-10 08:33:48,818 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-10 08:33:48,818 INFO L276 IsEmpty]: Start isEmpty. Operand 197 states and 260 transitions. [2018-11-10 08:33:48,819 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2018-11-10 08:33:48,819 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 08:33:48,819 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:33:48,819 INFO L424 AbstractCegarLoop]: === Iteration 7 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 08:33:48,819 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:33:48,819 INFO L82 PathProgramCache]: Analyzing trace with hash 1340650215, now seen corresponding path program 1 times [2018-11-10 08:33:48,819 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:33:48,820 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:33:48,820 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:48,820 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:33:48,820 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:48,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:33:48,878 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 08:33:48,878 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 08:33:48,878 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-10 08:33:48,879 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-10 08:33:48,879 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-10 08:33:48,879 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-10 08:33:48,879 INFO L87 Difference]: Start difference. First operand 197 states and 260 transitions. Second operand 6 states. [2018-11-10 08:33:48,907 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 08:33:48,908 INFO L93 Difference]: Finished difference Result 388 states and 528 transitions. [2018-11-10 08:33:48,908 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-10 08:33:48,908 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 107 [2018-11-10 08:33:48,908 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 08:33:48,910 INFO L225 Difference]: With dead ends: 388 [2018-11-10 08:33:48,910 INFO L226 Difference]: Without dead ends: 213 [2018-11-10 08:33:48,911 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-10 08:33:48,911 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 213 states. [2018-11-10 08:33:48,923 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 213 to 202. [2018-11-10 08:33:48,923 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 202 states. [2018-11-10 08:33:48,924 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 202 states to 202 states and 265 transitions. [2018-11-10 08:33:48,924 INFO L78 Accepts]: Start accepts. Automaton has 202 states and 265 transitions. Word has length 107 [2018-11-10 08:33:48,924 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 08:33:48,925 INFO L481 AbstractCegarLoop]: Abstraction has 202 states and 265 transitions. [2018-11-10 08:33:48,925 INFO L482 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-10 08:33:48,925 INFO L276 IsEmpty]: Start isEmpty. Operand 202 states and 265 transitions. [2018-11-10 08:33:48,926 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2018-11-10 08:33:48,926 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 08:33:48,926 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:33:48,926 INFO L424 AbstractCegarLoop]: === Iteration 8 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 08:33:48,926 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:33:48,927 INFO L82 PathProgramCache]: Analyzing trace with hash -345529623, now seen corresponding path program 1 times [2018-11-10 08:33:48,927 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:33:48,927 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:33:48,927 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:48,927 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:33:48,928 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:48,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:33:48,997 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 08:33:48,998 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 08:33:48,998 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-10 08:33:48,998 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-10 08:33:48,998 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-10 08:33:48,998 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-10 08:33:48,999 INFO L87 Difference]: Start difference. First operand 202 states and 265 transitions. Second operand 4 states. [2018-11-10 08:33:49,126 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 08:33:49,126 INFO L93 Difference]: Finished difference Result 555 states and 751 transitions. [2018-11-10 08:33:49,127 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-10 08:33:49,127 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 107 [2018-11-10 08:33:49,127 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 08:33:49,129 INFO L225 Difference]: With dead ends: 555 [2018-11-10 08:33:49,129 INFO L226 Difference]: Without dead ends: 375 [2018-11-10 08:33:49,129 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-10 08:33:49,130 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 375 states. [2018-11-10 08:33:49,150 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 375 to 369. [2018-11-10 08:33:49,150 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 369 states. [2018-11-10 08:33:49,151 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 369 states to 369 states and 483 transitions. [2018-11-10 08:33:49,152 INFO L78 Accepts]: Start accepts. Automaton has 369 states and 483 transitions. Word has length 107 [2018-11-10 08:33:49,152 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 08:33:49,152 INFO L481 AbstractCegarLoop]: Abstraction has 369 states and 483 transitions. [2018-11-10 08:33:49,152 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-10 08:33:49,152 INFO L276 IsEmpty]: Start isEmpty. Operand 369 states and 483 transitions. [2018-11-10 08:33:49,153 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2018-11-10 08:33:49,153 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 08:33:49,153 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:33:49,153 INFO L424 AbstractCegarLoop]: === Iteration 9 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 08:33:49,153 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:33:49,154 INFO L82 PathProgramCache]: Analyzing trace with hash 1474196296, now seen corresponding path program 1 times [2018-11-10 08:33:49,154 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:33:49,154 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:33:49,154 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:49,154 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:33:49,154 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:49,163 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:33:49,202 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 08:33:49,202 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 08:33:49,202 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-10 08:33:49,202 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-10 08:33:49,202 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-10 08:33:49,203 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-10 08:33:49,203 INFO L87 Difference]: Start difference. First operand 369 states and 483 transitions. Second operand 6 states. [2018-11-10 08:33:49,235 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 08:33:49,235 INFO L93 Difference]: Finished difference Result 729 states and 977 transitions. [2018-11-10 08:33:49,236 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-10 08:33:49,236 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 107 [2018-11-10 08:33:49,236 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 08:33:49,238 INFO L225 Difference]: With dead ends: 729 [2018-11-10 08:33:49,238 INFO L226 Difference]: Without dead ends: 382 [2018-11-10 08:33:49,239 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-10 08:33:49,239 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 382 states. [2018-11-10 08:33:49,258 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 382 to 374. [2018-11-10 08:33:49,258 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 374 states. [2018-11-10 08:33:49,259 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 374 states to 374 states and 487 transitions. [2018-11-10 08:33:49,260 INFO L78 Accepts]: Start accepts. Automaton has 374 states and 487 transitions. Word has length 107 [2018-11-10 08:33:49,260 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 08:33:49,260 INFO L481 AbstractCegarLoop]: Abstraction has 374 states and 487 transitions. [2018-11-10 08:33:49,260 INFO L482 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-10 08:33:49,260 INFO L276 IsEmpty]: Start isEmpty. Operand 374 states and 487 transitions. [2018-11-10 08:33:49,261 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2018-11-10 08:33:49,261 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 08:33:49,261 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:33:49,262 INFO L424 AbstractCegarLoop]: === Iteration 10 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 08:33:49,262 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:33:49,262 INFO L82 PathProgramCache]: Analyzing trace with hash 1514871046, now seen corresponding path program 1 times [2018-11-10 08:33:49,262 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:33:49,262 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:33:49,262 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:49,263 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:33:49,263 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:49,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:33:49,310 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 08:33:49,310 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 08:33:49,310 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-10 08:33:49,310 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-10 08:33:49,311 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-10 08:33:49,311 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-10 08:33:49,311 INFO L87 Difference]: Start difference. First operand 374 states and 487 transitions. Second operand 6 states. [2018-11-10 08:33:49,341 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 08:33:49,342 INFO L93 Difference]: Finished difference Result 746 states and 996 transitions. [2018-11-10 08:33:49,342 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-10 08:33:49,342 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 107 [2018-11-10 08:33:49,342 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 08:33:49,344 INFO L225 Difference]: With dead ends: 746 [2018-11-10 08:33:49,344 INFO L226 Difference]: Without dead ends: 394 [2018-11-10 08:33:49,345 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-10 08:33:49,345 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 394 states. [2018-11-10 08:33:49,363 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 394 to 384. [2018-11-10 08:33:49,363 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 384 states. [2018-11-10 08:33:49,364 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 384 states to 384 states and 497 transitions. [2018-11-10 08:33:49,364 INFO L78 Accepts]: Start accepts. Automaton has 384 states and 497 transitions. Word has length 107 [2018-11-10 08:33:49,365 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 08:33:49,365 INFO L481 AbstractCegarLoop]: Abstraction has 384 states and 497 transitions. [2018-11-10 08:33:49,365 INFO L482 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-10 08:33:49,365 INFO L276 IsEmpty]: Start isEmpty. Operand 384 states and 497 transitions. [2018-11-10 08:33:49,366 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2018-11-10 08:33:49,366 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 08:33:49,366 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:33:49,366 INFO L424 AbstractCegarLoop]: === Iteration 11 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 08:33:49,366 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:33:49,366 INFO L82 PathProgramCache]: Analyzing trace with hash 1161782664, now seen corresponding path program 1 times [2018-11-10 08:33:49,367 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:33:49,367 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:33:49,367 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:49,367 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:33:49,367 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:49,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:33:49,414 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 08:33:49,414 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 08:33:49,414 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-10 08:33:49,414 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-10 08:33:49,414 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-10 08:33:49,415 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-10 08:33:49,415 INFO L87 Difference]: Start difference. First operand 384 states and 497 transitions. Second operand 4 states. [2018-11-10 08:33:49,549 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 08:33:49,549 INFO L93 Difference]: Finished difference Result 1092 states and 1463 transitions. [2018-11-10 08:33:49,550 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-10 08:33:49,550 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 107 [2018-11-10 08:33:49,550 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 08:33:49,552 INFO L225 Difference]: With dead ends: 1092 [2018-11-10 08:33:49,552 INFO L226 Difference]: Without dead ends: 730 [2018-11-10 08:33:49,554 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-10 08:33:49,554 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 730 states. [2018-11-10 08:33:49,585 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 730 to 727. [2018-11-10 08:33:49,585 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 727 states. [2018-11-10 08:33:49,587 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 727 states to 727 states and 937 transitions. [2018-11-10 08:33:49,587 INFO L78 Accepts]: Start accepts. Automaton has 727 states and 937 transitions. Word has length 107 [2018-11-10 08:33:49,587 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 08:33:49,587 INFO L481 AbstractCegarLoop]: Abstraction has 727 states and 937 transitions. [2018-11-10 08:33:49,587 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-10 08:33:49,587 INFO L276 IsEmpty]: Start isEmpty. Operand 727 states and 937 transitions. [2018-11-10 08:33:49,589 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2018-11-10 08:33:49,589 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 08:33:49,589 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:33:49,589 INFO L424 AbstractCegarLoop]: === Iteration 12 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 08:33:49,589 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:33:49,590 INFO L82 PathProgramCache]: Analyzing trace with hash -82292794, now seen corresponding path program 1 times [2018-11-10 08:33:49,590 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:33:49,590 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:33:49,590 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:49,590 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:33:49,591 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:49,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:33:49,639 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-10 08:33:49,639 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 08:33:49,639 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-10 08:33:49,639 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-10 08:33:49,639 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-10 08:33:49,640 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-10 08:33:49,640 INFO L87 Difference]: Start difference. First operand 727 states and 937 transitions. Second operand 6 states. [2018-11-10 08:33:49,692 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 08:33:49,692 INFO L93 Difference]: Finished difference Result 1446 states and 1907 transitions. [2018-11-10 08:33:49,693 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-10 08:33:49,693 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 129 [2018-11-10 08:33:49,693 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 08:33:49,695 INFO L225 Difference]: With dead ends: 1446 [2018-11-10 08:33:49,696 INFO L226 Difference]: Without dead ends: 741 [2018-11-10 08:33:49,697 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-10 08:33:49,698 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 741 states. [2018-11-10 08:33:49,730 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 741 to 737. [2018-11-10 08:33:49,730 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 737 states. [2018-11-10 08:33:49,733 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 737 states to 737 states and 945 transitions. [2018-11-10 08:33:49,733 INFO L78 Accepts]: Start accepts. Automaton has 737 states and 945 transitions. Word has length 129 [2018-11-10 08:33:49,733 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 08:33:49,733 INFO L481 AbstractCegarLoop]: Abstraction has 737 states and 945 transitions. [2018-11-10 08:33:49,733 INFO L482 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-10 08:33:49,733 INFO L276 IsEmpty]: Start isEmpty. Operand 737 states and 945 transitions. [2018-11-10 08:33:49,734 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2018-11-10 08:33:49,735 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 08:33:49,735 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:33:49,735 INFO L424 AbstractCegarLoop]: === Iteration 13 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 08:33:49,735 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:33:49,735 INFO L82 PathProgramCache]: Analyzing trace with hash 119531140, now seen corresponding path program 1 times [2018-11-10 08:33:49,735 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:33:49,735 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:33:49,736 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:49,736 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:33:49,736 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:49,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:33:49,799 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-10 08:33:49,799 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 08:33:49,800 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 08:33:49,800 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-10 08:33:49,800 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 08:33:49,800 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 08:33:49,800 INFO L87 Difference]: Start difference. First operand 737 states and 945 transitions. Second operand 5 states. [2018-11-10 08:33:50,060 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 08:33:50,060 INFO L93 Difference]: Finished difference Result 1451 states and 1868 transitions. [2018-11-10 08:33:50,060 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-10 08:33:50,061 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 129 [2018-11-10 08:33:50,061 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 08:33:50,063 INFO L225 Difference]: With dead ends: 1451 [2018-11-10 08:33:50,063 INFO L226 Difference]: Without dead ends: 737 [2018-11-10 08:33:50,064 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-10 08:33:50,064 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 737 states. [2018-11-10 08:33:50,095 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 737 to 737. [2018-11-10 08:33:50,095 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 737 states. [2018-11-10 08:33:50,097 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 737 states to 737 states and 937 transitions. [2018-11-10 08:33:50,097 INFO L78 Accepts]: Start accepts. Automaton has 737 states and 937 transitions. Word has length 129 [2018-11-10 08:33:50,098 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 08:33:50,098 INFO L481 AbstractCegarLoop]: Abstraction has 737 states and 937 transitions. [2018-11-10 08:33:50,098 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-10 08:33:50,098 INFO L276 IsEmpty]: Start isEmpty. Operand 737 states and 937 transitions. [2018-11-10 08:33:50,099 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2018-11-10 08:33:50,099 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 08:33:50,099 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:33:50,099 INFO L424 AbstractCegarLoop]: === Iteration 14 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 08:33:50,100 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:33:50,100 INFO L82 PathProgramCache]: Analyzing trace with hash 1506316550, now seen corresponding path program 1 times [2018-11-10 08:33:50,100 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:33:50,100 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:33:50,101 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:50,101 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:33:50,101 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:50,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:33:50,157 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-10 08:33:50,157 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 08:33:50,157 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 08:33:50,157 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-10 08:33:50,157 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 08:33:50,158 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 08:33:50,158 INFO L87 Difference]: Start difference. First operand 737 states and 937 transitions. Second operand 5 states. [2018-11-10 08:33:50,378 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 08:33:50,378 INFO L93 Difference]: Finished difference Result 1451 states and 1852 transitions. [2018-11-10 08:33:50,379 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-10 08:33:50,379 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 129 [2018-11-10 08:33:50,379 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 08:33:50,381 INFO L225 Difference]: With dead ends: 1451 [2018-11-10 08:33:50,381 INFO L226 Difference]: Without dead ends: 737 [2018-11-10 08:33:50,382 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-10 08:33:50,383 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 737 states. [2018-11-10 08:33:50,412 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 737 to 737. [2018-11-10 08:33:50,412 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 737 states. [2018-11-10 08:33:50,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 737 states to 737 states and 929 transitions. [2018-11-10 08:33:50,415 INFO L78 Accepts]: Start accepts. Automaton has 737 states and 929 transitions. Word has length 129 [2018-11-10 08:33:50,415 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 08:33:50,415 INFO L481 AbstractCegarLoop]: Abstraction has 737 states and 929 transitions. [2018-11-10 08:33:50,415 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-10 08:33:50,415 INFO L276 IsEmpty]: Start isEmpty. Operand 737 states and 929 transitions. [2018-11-10 08:33:50,416 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2018-11-10 08:33:50,416 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 08:33:50,417 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:33:50,417 INFO L424 AbstractCegarLoop]: === Iteration 15 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 08:33:50,417 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:33:50,417 INFO L82 PathProgramCache]: Analyzing trace with hash -1912631740, now seen corresponding path program 1 times [2018-11-10 08:33:50,417 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:33:50,417 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:33:50,418 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:50,418 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:33:50,418 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:50,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:33:50,468 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-10 08:33:50,468 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 08:33:50,468 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 08:33:50,468 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-10 08:33:50,468 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 08:33:50,469 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 08:33:50,469 INFO L87 Difference]: Start difference. First operand 737 states and 929 transitions. Second operand 5 states. [2018-11-10 08:33:50,781 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 08:33:50,781 INFO L93 Difference]: Finished difference Result 1821 states and 2327 transitions. [2018-11-10 08:33:50,782 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-10 08:33:50,782 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 129 [2018-11-10 08:33:50,782 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 08:33:50,785 INFO L225 Difference]: With dead ends: 1821 [2018-11-10 08:33:50,786 INFO L226 Difference]: Without dead ends: 1107 [2018-11-10 08:33:50,787 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-10 08:33:50,788 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1107 states. [2018-11-10 08:33:50,828 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1107 to 1031. [2018-11-10 08:33:50,829 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1031 states. [2018-11-10 08:33:50,831 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1031 states to 1031 states and 1275 transitions. [2018-11-10 08:33:50,831 INFO L78 Accepts]: Start accepts. Automaton has 1031 states and 1275 transitions. Word has length 129 [2018-11-10 08:33:50,831 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 08:33:50,832 INFO L481 AbstractCegarLoop]: Abstraction has 1031 states and 1275 transitions. [2018-11-10 08:33:50,832 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-10 08:33:50,832 INFO L276 IsEmpty]: Start isEmpty. Operand 1031 states and 1275 transitions. [2018-11-10 08:33:50,833 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2018-11-10 08:33:50,833 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 08:33:50,833 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:33:50,833 INFO L424 AbstractCegarLoop]: === Iteration 16 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 08:33:50,833 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:33:50,834 INFO L82 PathProgramCache]: Analyzing trace with hash -1468731066, now seen corresponding path program 1 times [2018-11-10 08:33:50,834 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:33:50,834 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:33:50,834 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:50,834 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:33:50,834 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:50,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:33:50,885 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-10 08:33:50,885 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 08:33:50,886 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 08:33:50,886 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-10 08:33:50,886 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 08:33:50,886 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 08:33:50,886 INFO L87 Difference]: Start difference. First operand 1031 states and 1275 transitions. Second operand 5 states. [2018-11-10 08:33:51,262 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 08:33:51,262 INFO L93 Difference]: Finished difference Result 2426 states and 3146 transitions. [2018-11-10 08:33:51,262 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-10 08:33:51,262 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 129 [2018-11-10 08:33:51,263 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 08:33:51,267 INFO L225 Difference]: With dead ends: 2426 [2018-11-10 08:33:51,267 INFO L226 Difference]: Without dead ends: 1420 [2018-11-10 08:33:51,269 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-10 08:33:51,270 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1420 states. [2018-11-10 08:33:51,320 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1420 to 1239. [2018-11-10 08:33:51,320 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1239 states. [2018-11-10 08:33:51,323 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1239 states to 1239 states and 1497 transitions. [2018-11-10 08:33:51,323 INFO L78 Accepts]: Start accepts. Automaton has 1239 states and 1497 transitions. Word has length 129 [2018-11-10 08:33:51,324 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 08:33:51,324 INFO L481 AbstractCegarLoop]: Abstraction has 1239 states and 1497 transitions. [2018-11-10 08:33:51,324 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-10 08:33:51,324 INFO L276 IsEmpty]: Start isEmpty. Operand 1239 states and 1497 transitions. [2018-11-10 08:33:51,325 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2018-11-10 08:33:51,325 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 08:33:51,325 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:33:51,325 INFO L424 AbstractCegarLoop]: === Iteration 17 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 08:33:51,325 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:33:51,325 INFO L82 PathProgramCache]: Analyzing trace with hash 69608964, now seen corresponding path program 1 times [2018-11-10 08:33:51,325 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:33:51,326 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:33:51,326 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:51,326 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:33:51,326 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:51,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:33:51,374 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-10 08:33:51,375 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 08:33:51,375 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 08:33:51,375 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-10 08:33:51,375 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 08:33:51,375 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 08:33:51,376 INFO L87 Difference]: Start difference. First operand 1239 states and 1497 transitions. Second operand 5 states. [2018-11-10 08:33:51,717 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 08:33:51,717 INFO L93 Difference]: Finished difference Result 2635 states and 3316 transitions. [2018-11-10 08:33:51,718 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-10 08:33:51,718 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 129 [2018-11-10 08:33:51,718 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 08:33:51,722 INFO L225 Difference]: With dead ends: 2635 [2018-11-10 08:33:51,722 INFO L226 Difference]: Without dead ends: 1419 [2018-11-10 08:33:51,724 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-10 08:33:51,725 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1419 states. [2018-11-10 08:33:51,779 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1419 to 1305. [2018-11-10 08:33:51,779 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1305 states. [2018-11-10 08:33:51,781 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1305 states to 1305 states and 1543 transitions. [2018-11-10 08:33:51,781 INFO L78 Accepts]: Start accepts. Automaton has 1305 states and 1543 transitions. Word has length 129 [2018-11-10 08:33:51,782 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 08:33:51,782 INFO L481 AbstractCegarLoop]: Abstraction has 1305 states and 1543 transitions. [2018-11-10 08:33:51,782 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-10 08:33:51,782 INFO L276 IsEmpty]: Start isEmpty. Operand 1305 states and 1543 transitions. [2018-11-10 08:33:51,783 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2018-11-10 08:33:51,783 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 08:33:51,783 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:33:51,783 INFO L424 AbstractCegarLoop]: === Iteration 18 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 08:33:51,784 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:33:51,784 INFO L82 PathProgramCache]: Analyzing trace with hash -1958977146, now seen corresponding path program 1 times [2018-11-10 08:33:51,784 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:33:51,784 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:33:51,784 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:51,784 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:33:51,785 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:51,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:33:51,831 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-10 08:33:51,831 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 08:33:51,831 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 08:33:51,832 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-10 08:33:51,832 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 08:33:51,832 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 08:33:51,832 INFO L87 Difference]: Start difference. First operand 1305 states and 1543 transitions. Second operand 5 states. [2018-11-10 08:33:52,183 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 08:33:52,183 INFO L93 Difference]: Finished difference Result 2923 states and 3618 transitions. [2018-11-10 08:33:52,184 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-10 08:33:52,184 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 129 [2018-11-10 08:33:52,184 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 08:33:52,189 INFO L225 Difference]: With dead ends: 2923 [2018-11-10 08:33:52,189 INFO L226 Difference]: Without dead ends: 1643 [2018-11-10 08:33:52,192 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-10 08:33:52,193 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1643 states. [2018-11-10 08:33:52,291 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1643 to 1460. [2018-11-10 08:33:52,291 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1460 states. [2018-11-10 08:33:52,294 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1460 states to 1460 states and 1691 transitions. [2018-11-10 08:33:52,294 INFO L78 Accepts]: Start accepts. Automaton has 1460 states and 1691 transitions. Word has length 129 [2018-11-10 08:33:52,294 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 08:33:52,294 INFO L481 AbstractCegarLoop]: Abstraction has 1460 states and 1691 transitions. [2018-11-10 08:33:52,294 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-10 08:33:52,295 INFO L276 IsEmpty]: Start isEmpty. Operand 1460 states and 1691 transitions. [2018-11-10 08:33:52,296 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2018-11-10 08:33:52,296 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 08:33:52,296 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:33:52,296 INFO L424 AbstractCegarLoop]: === Iteration 19 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 08:33:52,296 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:33:52,296 INFO L82 PathProgramCache]: Analyzing trace with hash 1854909892, now seen corresponding path program 1 times [2018-11-10 08:33:52,297 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:33:52,297 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:33:52,297 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:52,297 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:33:52,297 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:52,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:33:52,327 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 7 proven. 3 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-11-10 08:33:52,327 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 08:33:52,327 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_09fd18e7-b77b-4718-afeb-627057a89c31/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 08:33:52,337 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:33:52,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:33:52,403 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 08:33:52,443 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-11-10 08:33:52,469 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-10 08:33:52,470 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [3] total 3 [2018-11-10 08:33:52,470 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-10 08:33:52,470 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 08:33:52,471 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 08:33:52,471 INFO L87 Difference]: Start difference. First operand 1460 states and 1691 transitions. Second operand 3 states. [2018-11-10 08:33:52,617 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 08:33:52,617 INFO L93 Difference]: Finished difference Result 4220 states and 4970 transitions. [2018-11-10 08:33:52,617 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 08:33:52,617 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 129 [2018-11-10 08:33:52,618 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 08:33:52,624 INFO L225 Difference]: With dead ends: 4220 [2018-11-10 08:33:52,624 INFO L226 Difference]: Without dead ends: 2785 [2018-11-10 08:33:52,627 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 131 GetRequests, 129 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 08:33:52,629 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2785 states. [2018-11-10 08:33:52,757 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2785 to 2647. [2018-11-10 08:33:52,757 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2647 states. [2018-11-10 08:33:52,762 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2647 states to 2647 states and 3131 transitions. [2018-11-10 08:33:52,762 INFO L78 Accepts]: Start accepts. Automaton has 2647 states and 3131 transitions. Word has length 129 [2018-11-10 08:33:52,763 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 08:33:52,763 INFO L481 AbstractCegarLoop]: Abstraction has 2647 states and 3131 transitions. [2018-11-10 08:33:52,763 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-10 08:33:52,763 INFO L276 IsEmpty]: Start isEmpty. Operand 2647 states and 3131 transitions. [2018-11-10 08:33:52,765 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 132 [2018-11-10 08:33:52,766 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 08:33:52,766 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:33:52,766 INFO L424 AbstractCegarLoop]: === Iteration 20 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 08:33:52,766 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:33:52,766 INFO L82 PathProgramCache]: Analyzing trace with hash -541916442, now seen corresponding path program 1 times [2018-11-10 08:33:52,766 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:33:52,766 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:33:52,767 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:52,767 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:33:52,767 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:52,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:33:52,803 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-11-10 08:33:52,803 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 08:33:52,804 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 08:33:52,804 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-10 08:33:52,804 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 08:33:52,804 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 08:33:52,804 INFO L87 Difference]: Start difference. First operand 2647 states and 3131 transitions. Second operand 3 states. [2018-11-10 08:33:53,055 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 08:33:53,055 INFO L93 Difference]: Finished difference Result 7839 states and 9342 transitions. [2018-11-10 08:33:53,055 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 08:33:53,055 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 131 [2018-11-10 08:33:53,056 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 08:33:53,065 INFO L225 Difference]: With dead ends: 7839 [2018-11-10 08:33:53,066 INFO L226 Difference]: Without dead ends: 3936 [2018-11-10 08:33:53,072 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 08:33:53,075 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3936 states. [2018-11-10 08:33:53,394 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3936 to 3936. [2018-11-10 08:33:53,394 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3936 states. [2018-11-10 08:33:53,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3936 states to 3936 states and 4683 transitions. [2018-11-10 08:33:53,407 INFO L78 Accepts]: Start accepts. Automaton has 3936 states and 4683 transitions. Word has length 131 [2018-11-10 08:33:53,407 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 08:33:53,407 INFO L481 AbstractCegarLoop]: Abstraction has 3936 states and 4683 transitions. [2018-11-10 08:33:53,407 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-10 08:33:53,407 INFO L276 IsEmpty]: Start isEmpty. Operand 3936 states and 4683 transitions. [2018-11-10 08:33:53,414 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 186 [2018-11-10 08:33:53,414 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 08:33:53,414 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:33:53,414 INFO L424 AbstractCegarLoop]: === Iteration 21 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 08:33:53,415 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:33:53,415 INFO L82 PathProgramCache]: Analyzing trace with hash -248325411, now seen corresponding path program 1 times [2018-11-10 08:33:53,415 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:33:53,415 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:33:53,415 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:53,415 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:33:53,416 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:53,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:33:53,482 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-11-10 08:33:53,483 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 08:33:53,483 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-10 08:33:53,483 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-10 08:33:53,483 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-10 08:33:53,483 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-10 08:33:53,484 INFO L87 Difference]: Start difference. First operand 3936 states and 4683 transitions. Second operand 4 states. [2018-11-10 08:33:53,888 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 08:33:53,888 INFO L93 Difference]: Finished difference Result 7839 states and 9314 transitions. [2018-11-10 08:33:53,889 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-10 08:33:53,890 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 185 [2018-11-10 08:33:53,890 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 08:33:53,906 INFO L225 Difference]: With dead ends: 7839 [2018-11-10 08:33:53,906 INFO L226 Difference]: Without dead ends: 3926 [2018-11-10 08:33:53,915 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-10 08:33:53,918 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3926 states. [2018-11-10 08:33:54,209 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3926 to 3926. [2018-11-10 08:33:54,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3926 states. [2018-11-10 08:33:54,219 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3926 states to 3926 states and 4661 transitions. [2018-11-10 08:33:54,220 INFO L78 Accepts]: Start accepts. Automaton has 3926 states and 4661 transitions. Word has length 185 [2018-11-10 08:33:54,220 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 08:33:54,220 INFO L481 AbstractCegarLoop]: Abstraction has 3926 states and 4661 transitions. [2018-11-10 08:33:54,221 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-10 08:33:54,221 INFO L276 IsEmpty]: Start isEmpty. Operand 3926 states and 4661 transitions. [2018-11-10 08:33:54,227 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 186 [2018-11-10 08:33:54,227 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 08:33:54,227 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:33:54,227 INFO L424 AbstractCegarLoop]: === Iteration 22 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 08:33:54,227 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:33:54,228 INFO L82 PathProgramCache]: Analyzing trace with hash 644744734, now seen corresponding path program 1 times [2018-11-10 08:33:54,228 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:33:54,228 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:33:54,228 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:54,228 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:33:54,229 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:54,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:33:54,299 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 43 trivial. 0 not checked. [2018-11-10 08:33:54,300 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 08:33:54,300 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 08:33:54,300 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-10 08:33:54,300 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 08:33:54,300 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 08:33:54,301 INFO L87 Difference]: Start difference. First operand 3926 states and 4661 transitions. Second operand 3 states. [2018-11-10 08:33:54,841 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 08:33:54,842 INFO L93 Difference]: Finished difference Result 10434 states and 12655 transitions. [2018-11-10 08:33:54,842 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 08:33:54,842 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 185 [2018-11-10 08:33:54,842 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 08:33:54,867 INFO L225 Difference]: With dead ends: 10434 [2018-11-10 08:33:54,867 INFO L226 Difference]: Without dead ends: 6533 [2018-11-10 08:33:54,879 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 08:33:54,884 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6533 states. [2018-11-10 08:33:55,359 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6533 to 6527. [2018-11-10 08:33:55,360 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6527 states. [2018-11-10 08:33:55,376 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6527 states to 6527 states and 7846 transitions. [2018-11-10 08:33:55,377 INFO L78 Accepts]: Start accepts. Automaton has 6527 states and 7846 transitions. Word has length 185 [2018-11-10 08:33:55,378 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 08:33:55,378 INFO L481 AbstractCegarLoop]: Abstraction has 6527 states and 7846 transitions. [2018-11-10 08:33:55,378 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-10 08:33:55,378 INFO L276 IsEmpty]: Start isEmpty. Operand 6527 states and 7846 transitions. [2018-11-10 08:33:55,388 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 187 [2018-11-10 08:33:55,388 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 08:33:55,388 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:33:55,389 INFO L424 AbstractCegarLoop]: === Iteration 23 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 08:33:55,389 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:33:55,390 INFO L82 PathProgramCache]: Analyzing trace with hash -1440585158, now seen corresponding path program 1 times [2018-11-10 08:33:55,390 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:33:55,390 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:33:55,391 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:55,391 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:33:55,391 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:55,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:33:55,492 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 4 proven. 11 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2018-11-10 08:33:55,492 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 08:33:55,492 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_09fd18e7-b77b-4718-afeb-627057a89c31/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 08:33:55,501 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:33:55,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:33:55,594 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 08:33:55,640 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 42 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-11-10 08:33:55,667 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-10 08:33:55,667 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [6] total 7 [2018-11-10 08:33:55,667 INFO L460 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-10 08:33:55,668 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-10 08:33:55,668 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2018-11-10 08:33:55,668 INFO L87 Difference]: Start difference. First operand 6527 states and 7846 transitions. Second operand 7 states. [2018-11-10 08:33:56,748 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 08:33:56,748 INFO L93 Difference]: Finished difference Result 15764 states and 19985 transitions. [2018-11-10 08:33:56,749 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-10 08:33:56,749 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 186 [2018-11-10 08:33:56,749 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 08:33:56,768 INFO L225 Difference]: With dead ends: 15764 [2018-11-10 08:33:56,769 INFO L226 Difference]: Without dead ends: 7192 [2018-11-10 08:33:56,786 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 194 GetRequests, 188 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2018-11-10 08:33:56,791 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7192 states. [2018-11-10 08:33:57,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7192 to 7183. [2018-11-10 08:33:57,110 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7183 states. [2018-11-10 08:33:57,120 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7183 states to 7183 states and 8658 transitions. [2018-11-10 08:33:57,122 INFO L78 Accepts]: Start accepts. Automaton has 7183 states and 8658 transitions. Word has length 186 [2018-11-10 08:33:57,122 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 08:33:57,122 INFO L481 AbstractCegarLoop]: Abstraction has 7183 states and 8658 transitions. [2018-11-10 08:33:57,122 INFO L482 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-10 08:33:57,123 INFO L276 IsEmpty]: Start isEmpty. Operand 7183 states and 8658 transitions. [2018-11-10 08:33:57,135 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 392 [2018-11-10 08:33:57,135 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 08:33:57,135 INFO L375 BasicCegarLoop]: trace histogram [6, 6, 6, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:33:57,135 INFO L424 AbstractCegarLoop]: === Iteration 24 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 08:33:57,135 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:33:57,136 INFO L82 PathProgramCache]: Analyzing trace with hash 1570200887, now seen corresponding path program 1 times [2018-11-10 08:33:57,136 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:33:57,136 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:33:57,136 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:57,136 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:33:57,136 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:57,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:33:57,304 INFO L134 CoverageAnalysis]: Checked inductivity of 404 backedges. 36 proven. 55 refuted. 0 times theorem prover too weak. 313 trivial. 0 not checked. [2018-11-10 08:33:57,304 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 08:33:57,304 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_09fd18e7-b77b-4718-afeb-627057a89c31/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 08:33:57,324 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:33:57,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:33:57,433 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 08:33:57,489 INFO L134 CoverageAnalysis]: Checked inductivity of 404 backedges. 231 proven. 0 refuted. 0 times theorem prover too weak. 173 trivial. 0 not checked. [2018-11-10 08:33:57,507 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-10 08:33:57,507 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [5] total 6 [2018-11-10 08:33:57,508 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-10 08:33:57,508 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-10 08:33:57,508 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-10 08:33:57,508 INFO L87 Difference]: Start difference. First operand 7183 states and 8658 transitions. Second operand 6 states. [2018-11-10 08:33:58,572 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 08:33:58,572 INFO L93 Difference]: Finished difference Result 18153 states and 23095 transitions. [2018-11-10 08:33:58,572 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-10 08:33:58,572 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 391 [2018-11-10 08:33:58,573 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 08:33:58,597 INFO L225 Difference]: With dead ends: 18153 [2018-11-10 08:33:58,597 INFO L226 Difference]: Without dead ends: 10993 [2018-11-10 08:33:58,607 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 401 GetRequests, 395 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2018-11-10 08:33:58,615 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10993 states. [2018-11-10 08:33:59,128 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10993 to 10797. [2018-11-10 08:33:59,128 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10797 states. [2018-11-10 08:33:59,143 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10797 states to 10797 states and 13039 transitions. [2018-11-10 08:33:59,145 INFO L78 Accepts]: Start accepts. Automaton has 10797 states and 13039 transitions. Word has length 391 [2018-11-10 08:33:59,146 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 08:33:59,146 INFO L481 AbstractCegarLoop]: Abstraction has 10797 states and 13039 transitions. [2018-11-10 08:33:59,146 INFO L482 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-10 08:33:59,146 INFO L276 IsEmpty]: Start isEmpty. Operand 10797 states and 13039 transitions. [2018-11-10 08:33:59,157 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 260 [2018-11-10 08:33:59,157 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 08:33:59,157 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:33:59,158 INFO L424 AbstractCegarLoop]: === Iteration 25 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 08:33:59,158 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:33:59,158 INFO L82 PathProgramCache]: Analyzing trace with hash 806603942, now seen corresponding path program 1 times [2018-11-10 08:33:59,158 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:33:59,158 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:33:59,159 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:59,159 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:33:59,159 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:33:59,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:33:59,217 INFO L134 CoverageAnalysis]: Checked inductivity of 153 backedges. 17 proven. 8 refuted. 0 times theorem prover too weak. 128 trivial. 0 not checked. [2018-11-10 08:33:59,217 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 08:33:59,217 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_09fd18e7-b77b-4718-afeb-627057a89c31/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 08:33:59,225 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:33:59,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:33:59,304 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 08:33:59,360 INFO L134 CoverageAnalysis]: Checked inductivity of 153 backedges. 110 proven. 0 refuted. 0 times theorem prover too weak. 43 trivial. 0 not checked. [2018-11-10 08:33:59,376 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-10 08:33:59,376 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [4] total 6 [2018-11-10 08:33:59,377 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-10 08:33:59,377 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-10 08:33:59,377 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-10 08:33:59,377 INFO L87 Difference]: Start difference. First operand 10797 states and 13039 transitions. Second operand 6 states. [2018-11-10 08:34:00,866 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 08:34:00,866 INFO L93 Difference]: Finished difference Result 28643 states and 35681 transitions. [2018-11-10 08:34:00,866 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-10 08:34:00,866 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 259 [2018-11-10 08:34:00,867 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 08:34:00,885 INFO L225 Difference]: With dead ends: 28643 [2018-11-10 08:34:00,885 INFO L226 Difference]: Without dead ends: 5614 [2018-11-10 08:34:00,911 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 267 GetRequests, 261 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=33, Unknown=0, NotChecked=0, Total=56 [2018-11-10 08:34:00,914 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5614 states. [2018-11-10 08:34:01,200 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5614 to 5607. [2018-11-10 08:34:01,200 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5607 states. [2018-11-10 08:34:01,207 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5607 states to 5607 states and 6564 transitions. [2018-11-10 08:34:01,209 INFO L78 Accepts]: Start accepts. Automaton has 5607 states and 6564 transitions. Word has length 259 [2018-11-10 08:34:01,210 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 08:34:01,210 INFO L481 AbstractCegarLoop]: Abstraction has 5607 states and 6564 transitions. [2018-11-10 08:34:01,210 INFO L482 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-10 08:34:01,210 INFO L276 IsEmpty]: Start isEmpty. Operand 5607 states and 6564 transitions. [2018-11-10 08:34:01,218 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 439 [2018-11-10 08:34:01,218 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 08:34:01,218 INFO L375 BasicCegarLoop]: trace histogram [6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:34:01,218 INFO L424 AbstractCegarLoop]: === Iteration 26 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 08:34:01,219 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:34:01,219 INFO L82 PathProgramCache]: Analyzing trace with hash -1338139830, now seen corresponding path program 1 times [2018-11-10 08:34:01,219 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:34:01,219 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:34:01,219 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:34:01,220 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:34:01,220 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:34:01,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:34:01,394 INFO L134 CoverageAnalysis]: Checked inductivity of 560 backedges. 42 proven. 26 refuted. 0 times theorem prover too weak. 492 trivial. 0 not checked. [2018-11-10 08:34:01,394 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-10 08:34:01,394 INFO L225 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_09fd18e7-b77b-4718-afeb-627057a89c31/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-10 08:34:01,404 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:34:01,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:34:01,529 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 08:34:01,623 INFO L134 CoverageAnalysis]: Checked inductivity of 560 backedges. 419 proven. 0 refuted. 0 times theorem prover too weak. 141 trivial. 0 not checked. [2018-11-10 08:34:01,639 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-10 08:34:01,640 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [8] total 9 [2018-11-10 08:34:01,640 INFO L460 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-10 08:34:01,640 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-10 08:34:01,640 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2018-11-10 08:34:01,641 INFO L87 Difference]: Start difference. First operand 5607 states and 6564 transitions. Second operand 9 states. [2018-11-10 08:34:01,884 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 08:34:01,885 INFO L93 Difference]: Finished difference Result 7296 states and 8526 transitions. [2018-11-10 08:34:01,885 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-10 08:34:01,885 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 438 [2018-11-10 08:34:01,885 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-10 08:34:01,889 INFO L225 Difference]: With dead ends: 7296 [2018-11-10 08:34:01,889 INFO L226 Difference]: Without dead ends: 1714 [2018-11-10 08:34:01,894 INFO L605 BasicCegarLoop]: 0 DeclaredPredicates, 458 GetRequests, 442 SyntacticMatches, 2 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=61, Invalid=179, Unknown=0, NotChecked=0, Total=240 [2018-11-10 08:34:01,895 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1714 states. [2018-11-10 08:34:01,975 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1714 to 1660. [2018-11-10 08:34:01,976 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1660 states. [2018-11-10 08:34:01,977 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1660 states to 1660 states and 1803 transitions. [2018-11-10 08:34:01,978 INFO L78 Accepts]: Start accepts. Automaton has 1660 states and 1803 transitions. Word has length 438 [2018-11-10 08:34:01,978 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-10 08:34:01,978 INFO L481 AbstractCegarLoop]: Abstraction has 1660 states and 1803 transitions. [2018-11-10 08:34:01,979 INFO L482 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-10 08:34:01,979 INFO L276 IsEmpty]: Start isEmpty. Operand 1660 states and 1803 transitions. [2018-11-10 08:34:01,981 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 318 [2018-11-10 08:34:01,981 INFO L367 BasicCegarLoop]: Found error trace [2018-11-10 08:34:01,981 INFO L375 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:34:01,981 INFO L424 AbstractCegarLoop]: === Iteration 27 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-10 08:34:01,981 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:34:01,981 INFO L82 PathProgramCache]: Analyzing trace with hash 168081796, now seen corresponding path program 1 times [2018-11-10 08:34:01,982 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:34:01,982 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:34:01,982 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:34:01,982 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:34:01,982 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:34:01,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 08:34:02,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 08:34:02,077 INFO L442 BasicCegarLoop]: Counterexample might be feasible [2018-11-10 08:34:02,190 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 10.11 08:34:02 BoogieIcfgContainer [2018-11-10 08:34:02,190 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-10 08:34:02,191 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-10 08:34:02,191 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-10 08:34:02,191 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-10 08:34:02,191 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.11 08:33:46" (3/4) ... [2018-11-10 08:34:02,193 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-11-10 08:34:02,296 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_09fd18e7-b77b-4718-afeb-627057a89c31/bin-2019/uautomizer/witness.graphml [2018-11-10 08:34:02,296 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-10 08:34:02,297 INFO L168 Benchmark]: Toolchain (without parser) took 16764.50 ms. Allocated memory was 1.0 GB in the beginning and 2.3 GB in the end (delta: 1.3 GB). Free memory was 959.1 MB in the beginning and 1.3 GB in the end (delta: -364.7 MB). Peak memory consumption was 913.5 MB. Max. memory is 11.5 GB. [2018-11-10 08:34:02,298 INFO L168 Benchmark]: CDTParser took 0.10 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-10 08:34:02,299 INFO L168 Benchmark]: CACSL2BoogieTranslator took 231.05 ms. Allocated memory is still 1.0 GB. Free memory was 959.1 MB in the beginning and 943.0 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. [2018-11-10 08:34:02,299 INFO L168 Benchmark]: Boogie Preprocessor took 26.49 ms. Allocated memory is still 1.0 GB. Free memory was 943.0 MB in the beginning and 940.3 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-11-10 08:34:02,299 INFO L168 Benchmark]: RCFGBuilder took 455.60 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 135.8 MB). Free memory was 940.3 MB in the beginning and 1.1 GB in the end (delta: -144.9 MB). Peak memory consumption was 15.4 MB. Max. memory is 11.5 GB. [2018-11-10 08:34:02,299 INFO L168 Benchmark]: TraceAbstraction took 15942.66 ms. Allocated memory was 1.2 GB in the beginning and 2.3 GB in the end (delta: 1.1 GB). Free memory was 1.1 GB in the beginning and 1.4 GB in the end (delta: -267.1 MB). Peak memory consumption was 875.4 MB. Max. memory is 11.5 GB. [2018-11-10 08:34:02,299 INFO L168 Benchmark]: Witness Printer took 105.52 ms. Allocated memory is still 2.3 GB. Free memory was 1.4 GB in the beginning and 1.3 GB in the end (delta: 28.5 MB). Peak memory consumption was 28.5 MB. Max. memory is 11.5 GB. [2018-11-10 08:34:02,301 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.10 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 231.05 ms. Allocated memory is still 1.0 GB. Free memory was 959.1 MB in the beginning and 943.0 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 26.49 ms. Allocated memory is still 1.0 GB. Free memory was 943.0 MB in the beginning and 940.3 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 455.60 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 135.8 MB). Free memory was 940.3 MB in the beginning and 1.1 GB in the end (delta: -144.9 MB). Peak memory consumption was 15.4 MB. Max. memory is 11.5 GB. * TraceAbstraction took 15942.66 ms. Allocated memory was 1.2 GB in the beginning and 2.3 GB in the end (delta: 1.1 GB). Free memory was 1.1 GB in the beginning and 1.4 GB in the end (delta: -267.1 MB). Peak memory consumption was 875.4 MB. Max. memory is 11.5 GB. * Witness Printer took 105.52 ms. Allocated memory is still 2.3 GB. Free memory was 1.4 GB in the beginning and 1.3 GB in the end (delta: 28.5 MB). Peak memory consumption was 28.5 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 11]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int m_st ; [L20] int t1_st ; [L21] int t2_st ; [L22] int t3_st ; [L23] int m_i ; [L24] int t1_i ; [L25] int t2_i ; [L26] int t3_i ; [L27] int M_E = 2; [L28] int T1_E = 2; [L29] int T2_E = 2; [L30] int T3_E = 2; [L31] int E_1 = 2; [L32] int E_2 = 2; [L33] int E_3 = 2; VAL [\old(E_1)=18, \old(E_2)=5, \old(E_3)=21, \old(M_E)=15, \old(m_i)=7, \old(m_pc)=13, \old(m_st)=14, \old(T1_E)=3, \old(t1_i)=17, \old(t1_pc)=9, \old(t1_st)=4, \old(T2_E)=16, \old(t2_i)=6, \old(t2_pc)=10, \old(t2_st)=11, \old(T3_E)=19, \old(t3_i)=20, \old(t3_pc)=8, \old(t3_st)=12, E_1=2, E_2=2, E_3=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0] [L687] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0] [L691] CALL init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0] [L600] m_i = 1 [L601] t1_i = 1 [L602] t2_i = 1 [L603] RET t3_i = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L691] init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L692] CALL start_simulation() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L628] int kernel_st ; [L629] int tmp ; [L630] int tmp___0 ; [L634] kernel_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L635] FCALL update_channels() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L636] CALL init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L271] COND TRUE m_i == 1 [L272] m_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L276] COND TRUE t1_i == 1 [L277] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L281] COND TRUE t2_i == 1 [L282] t2_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L286] COND TRUE t3_i == 1 [L287] RET t3_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L636] init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L637] CALL fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L408] COND FALSE !(M_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L413] COND FALSE !(T1_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L418] COND FALSE !(T2_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L423] COND FALSE !(T3_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L428] COND FALSE !(E_1 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L433] COND FALSE !(E_2 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L438] COND FALSE, RET !(E_3 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L637] fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L638] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L491] int tmp ; [L492] int tmp___0 ; [L493] int tmp___1 ; [L494] int tmp___2 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L498] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L184] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L187] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L197] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L199] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L498] EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L498] tmp = is_master_triggered() [L500] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=0] [L506] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L203] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L206] COND FALSE !(t1_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L216] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L218] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L506] EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=0] [L506] tmp___0 = is_transmit1_triggered() [L508] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0] [L514] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L222] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L225] COND FALSE !(t2_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L235] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L237] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L514] EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0] [L514] tmp___1 = is_transmit2_triggered() [L516] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0] [L522] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L241] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L244] COND FALSE !(t3_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L254] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, __retres1=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L256] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L522] EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0] [L522] tmp___2 = is_transmit3_triggered() [L524] COND FALSE, RET !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L638] activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L639] CALL reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L451] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L456] COND FALSE !(T1_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L461] COND FALSE !(T2_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L466] COND FALSE !(T3_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L471] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L476] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L481] COND FALSE, RET !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L639] reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L642] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L645] kernel_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, kernel_st=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L646] CALL eval() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L327] int tmp ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L331] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L334] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L296] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L299] COND TRUE m_st == 0 [L300] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, __retres1=1, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L322] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L334] EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L334] tmp = exists_runnable_thread() [L336] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=1] [L341] COND TRUE m_st == 0 [L342] int tmp_ndt_1; [L343] tmp_ndt_1 = __VERIFIER_nondet_int() [L344] COND FALSE !(\read(tmp_ndt_1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=1, tmp_ndt_1=0] [L355] COND TRUE t1_st == 0 [L356] int tmp_ndt_2; [L357] tmp_ndt_2 = __VERIFIER_nondet_int() [L358] COND TRUE \read(tmp_ndt_2) [L360] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1] [L361] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L84] COND TRUE t1_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L95] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L97] t1_pc = 1 [L98] RET t1_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L361] transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1] [L369] COND TRUE t2_st == 0 [L370] int tmp_ndt_3; [L371] tmp_ndt_3 = __VERIFIER_nondet_int() [L372] COND TRUE \read(tmp_ndt_3) [L374] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L375] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L119] COND TRUE t2_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L130] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L132] t2_pc = 1 [L133] RET t2_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L375] transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L383] COND TRUE t3_st == 0 [L384] int tmp_ndt_4; [L385] tmp_ndt_4 = __VERIFIER_nondet_int() [L386] COND TRUE \read(tmp_ndt_4) [L388] t3_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1] [L389] CALL transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1] [L154] COND TRUE t3_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1] [L165] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1] [L167] t3_pc = 1 [L168] RET t3_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=1, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L389] transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1] [L331] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1] [L334] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L296] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L299] COND TRUE m_st == 0 [L300] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, __retres1=1, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L322] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L334] EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1] [L334] tmp = exists_runnable_thread() [L336] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1] [L341] COND TRUE m_st == 0 [L342] int tmp_ndt_1; [L343] tmp_ndt_1 = __VERIFIER_nondet_int() [L344] COND TRUE \read(tmp_ndt_1) [L346] m_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1] [L347] CALL master() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L43] COND TRUE m_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L54] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L57] E_1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L58] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L538] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L491] int tmp ; [L492] int tmp___0 ; [L493] int tmp___1 ; [L494] int tmp___2 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L498] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L184] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L187] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L197] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L199] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L498] EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L498] tmp = is_master_triggered() [L500] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=0] [L506] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L203] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L206] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L207] COND TRUE E_1 == 1 [L208] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, __retres1=1, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L218] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \result=1, __retres1=1, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L506] EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, is_transmit1_triggered()=1, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=0] [L506] tmp___0 = is_transmit1_triggered() [L508] COND TRUE \read(tmp___0) [L509] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=0, tmp___0=1] [L514] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L222] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L225] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L226] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L235] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L237] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L514] EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=0, tmp___0=1] [L514] tmp___1 = is_transmit2_triggered() [L516] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=0, tmp___0=1, tmp___1=0] [L522] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L241] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L244] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L245] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L254] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, __retres1=0, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L256] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L522] EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=0, tmp___0=1, tmp___1=0] [L522] tmp___2 = is_transmit3_triggered() [L524] COND FALSE, RET !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=0, tmp___0=1, tmp___1=0, tmp___2=0] [L538] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L58] immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L59] E_1 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L62] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L64] m_pc = 1 [L65] RET m_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L347] master() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1] [L355] COND TRUE t1_st == 0 [L356] int tmp_ndt_2; [L357] tmp_ndt_2 = __VERIFIER_nondet_int() [L358] COND TRUE \read(tmp_ndt_2) [L360] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1] [L361] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L84] COND FALSE !(t1_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L87] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L103] E_2 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L104] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L538] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L491] int tmp ; [L492] int tmp___0 ; [L493] int tmp___1 ; [L494] int tmp___2 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L498] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L184] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L187] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L188] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L197] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L199] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L498] EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L498] tmp = is_master_triggered() [L500] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=0] [L506] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L203] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L206] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L207] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L216] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L218] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L506] EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=0] [L506] tmp___0 = is_transmit1_triggered() [L508] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=0, tmp___0=0] [L514] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L222] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L225] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L226] COND TRUE E_2 == 1 [L227] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, __retres1=1, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L237] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \result=1, __retres1=1, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L514] EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, is_transmit2_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=0, tmp___0=0] [L514] tmp___1 = is_transmit2_triggered() [L516] COND TRUE \read(tmp___1) [L517] t2_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=0, tmp___0=0, tmp___1=1] [L522] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L241] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L244] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L245] COND FALSE !(E_3 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L254] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, __retres1=0, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L256] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L522] EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, is_transmit3_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=0, tmp___0=0, tmp___1=1] [L522] tmp___2 = is_transmit3_triggered() [L524] COND FALSE, RET !(\read(tmp___2)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=0, tmp___0=0, tmp___1=1, tmp___2=0] [L538] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L104] immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L105] E_2 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L95] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L97] t1_pc = 1 [L98] RET t1_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L361] transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1] [L369] COND TRUE t2_st == 0 [L370] int tmp_ndt_3; [L371] tmp_ndt_3 = __VERIFIER_nondet_int() [L372] COND TRUE \read(tmp_ndt_3) [L374] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1] [L375] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L119] COND FALSE !(t2_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L122] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L138] E_3 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L139] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L538] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L491] int tmp ; [L492] int tmp___0 ; [L493] int tmp___1 ; [L494] int tmp___2 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L498] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L184] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L187] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L188] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L197] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L199] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L498] EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L498] tmp = is_master_triggered() [L500] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=0] [L506] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L203] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L206] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L207] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L216] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L218] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L506] EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=0] [L506] tmp___0 = is_transmit1_triggered() [L508] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=0, tmp___0=0] [L514] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L222] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L225] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L226] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L235] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, __retres1=0, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L237] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \result=0, __retres1=0, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L514] EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=0, tmp___0=0] [L514] tmp___1 = is_transmit2_triggered() [L516] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=0, tmp___0=0, tmp___1=0] [L522] CALL, EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L241] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L244] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L245] COND TRUE E_3 == 1 [L246] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, __retres1=1, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L256] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, \result=1, __retres1=1, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L522] EXPR is_transmit3_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, is_transmit3_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, tmp=0, tmp___0=0, tmp___1=0] [L522] tmp___2 = is_transmit3_triggered() [L524] COND TRUE \read(tmp___2) [L525] RET t3_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=1] [L538] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0] [L139] immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0] [L140] E_3 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0] [L130] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0] [L132] t2_pc = 1 [L133] RET t2_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=2, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0] [L375] transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1] [L383] COND TRUE t3_st == 0 [L384] int tmp_ndt_4; [L385] tmp_ndt_4 = __VERIFIER_nondet_int() [L386] COND TRUE \read(tmp_ndt_4) [L388] t3_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=0, \old(t3_st)=0, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1, tmp_ndt_4=1] [L389] CALL transmit3() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1] [L154] COND FALSE !(t3_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1] [L157] COND TRUE t3_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1] [L173] CALL error() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1] [L11] __VERIFIER_error() VAL [\old(E_1)=2, \old(E_2)=2, \old(E_3)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \old(T3_E)=2, \old(t3_i)=0, \old(t3_pc)=1, \old(t3_st)=1, E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 25 procedures, 206 locations, 1 error locations. UNSAFE Result, 15.9s OverallTime, 27 OverallIterations, 6 TraceHistogramMax, 9.4s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 7795 SDtfs, 9346 SDslu, 8775 SDs, 0 SdLazy, 5993 SolverSat, 2301 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 3.9s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 1628 GetRequests, 1478 SyntacticMatches, 37 SemanticMatches, 113 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 29 ImplicationChecksByTransitivity, 0.9s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=10797occurred in iteration=24, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 3.1s AutomataMinimizationTime, 26 MinimizatonAttempts, 1250 StatesRemovedByMinimization, 22 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.1s SsaConstructionTime, 0.5s SatisfiabilityAnalysisTime, 1.5s InterpolantComputationTime, 5704 NumberOfCodeBlocks, 5704 NumberOfCodeBlocksAsserted, 32 NumberOfCheckSat, 5356 ConstructedInterpolants, 0 QuantifiedInterpolants, 1703175 SizeOfPredicates, 2 NumberOfNonLiveVariables, 5591 ConjunctsInSsa, 16 ConjunctsInUnsatCore, 31 InterpolantComputations, 26 PerfectInterpolantSequences, 2527/2630 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...