./Ultimate.py --spec ../../sv-benchmarks/c/Termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.01_true-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 1dbac8bc Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_3ff55cc6-e111-44d6-94ef-9fb4125db8b6/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_3ff55cc6-e111-44d6-94ef-9fb4125db8b6/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_3ff55cc6-e111-44d6-94ef-9fb4125db8b6/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_3ff55cc6-e111-44d6-94ef-9fb4125db8b6/bin-2019/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.01_true-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_3ff55cc6-e111-44d6-94ef-9fb4125db8b6/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_3ff55cc6-e111-44d6-94ef-9fb4125db8b6/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 2216fd6115b2bb44c4633e353be739828d7cac46 .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.23-1dbac8b [2018-11-10 08:08:25,183 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-10 08:08:25,184 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-10 08:08:25,192 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-10 08:08:25,192 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-10 08:08:25,193 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-10 08:08:25,194 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-10 08:08:25,195 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-10 08:08:25,196 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-10 08:08:25,196 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-10 08:08:25,197 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-10 08:08:25,197 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-10 08:08:25,198 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-10 08:08:25,198 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-10 08:08:25,199 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-10 08:08:25,200 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-10 08:08:25,200 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-10 08:08:25,201 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-10 08:08:25,203 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-10 08:08:25,204 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-10 08:08:25,204 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-10 08:08:25,205 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-10 08:08:25,206 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-10 08:08:25,207 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-10 08:08:25,207 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-10 08:08:25,207 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-10 08:08:25,208 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-10 08:08:25,208 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-10 08:08:25,209 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-10 08:08:25,210 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-10 08:08:25,210 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-10 08:08:25,210 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-10 08:08:25,210 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-10 08:08:25,211 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-10 08:08:25,211 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-10 08:08:25,212 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-10 08:08:25,212 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_3ff55cc6-e111-44d6-94ef-9fb4125db8b6/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2018-11-10 08:08:25,222 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-10 08:08:25,222 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-10 08:08:25,223 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-10 08:08:25,223 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-10 08:08:25,223 INFO L133 SettingsManager]: * Use SBE=true [2018-11-10 08:08:25,223 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2018-11-10 08:08:25,224 INFO L133 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2018-11-10 08:08:25,224 INFO L133 SettingsManager]: * Use old map elimination=false [2018-11-10 08:08:25,224 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false [2018-11-10 08:08:25,224 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true [2018-11-10 08:08:25,224 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2018-11-10 08:08:25,224 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-10 08:08:25,224 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-10 08:08:25,224 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-10 08:08:25,225 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-10 08:08:25,225 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-10 08:08:25,225 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-10 08:08:25,225 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2018-11-10 08:08:25,225 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2018-11-10 08:08:25,225 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2018-11-10 08:08:25,225 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-10 08:08:25,225 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-10 08:08:25,226 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false [2018-11-10 08:08:25,226 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2018-11-10 08:08:25,226 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-10 08:08:25,226 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-10 08:08:25,226 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2018-11-10 08:08:25,226 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-10 08:08:25,226 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-10 08:08:25,227 INFO L133 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2018-11-10 08:08:25,227 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-11-10 08:08:25,227 INFO L133 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_3ff55cc6-e111-44d6-94ef-9fb4125db8b6/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2216fd6115b2bb44c4633e353be739828d7cac46 [2018-11-10 08:08:25,249 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-10 08:08:25,258 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-10 08:08:25,260 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-10 08:08:25,261 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-10 08:08:25,262 INFO L276 PluginConnector]: CDTParser initialized [2018-11-10 08:08:25,262 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_3ff55cc6-e111-44d6-94ef-9fb4125db8b6/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/token_ring.01_true-unreach-call_false-termination.cil.c [2018-11-10 08:08:25,299 INFO L218 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_3ff55cc6-e111-44d6-94ef-9fb4125db8b6/bin-2019/uautomizer/data/f6486cd49/00c9d401486f4660aeb82066da762190/FLAG871a60822 [2018-11-10 08:08:25,605 INFO L298 CDTParser]: Found 1 translation units. [2018-11-10 08:08:25,606 INFO L158 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_3ff55cc6-e111-44d6-94ef-9fb4125db8b6/sv-benchmarks/c/systemc/token_ring.01_true-unreach-call_false-termination.cil.c [2018-11-10 08:08:25,611 INFO L346 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_3ff55cc6-e111-44d6-94ef-9fb4125db8b6/bin-2019/uautomizer/data/f6486cd49/00c9d401486f4660aeb82066da762190/FLAG871a60822 [2018-11-10 08:08:25,619 INFO L354 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_3ff55cc6-e111-44d6-94ef-9fb4125db8b6/bin-2019/uautomizer/data/f6486cd49/00c9d401486f4660aeb82066da762190 [2018-11-10 08:08:25,621 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-10 08:08:25,622 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-10 08:08:25,623 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-10 08:08:25,623 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-10 08:08:25,625 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-10 08:08:25,626 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.11 08:08:25" (1/1) ... [2018-11-10 08:08:25,628 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7ce791db and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 08:08:25, skipping insertion in model container [2018-11-10 08:08:25,628 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.11 08:08:25" (1/1) ... [2018-11-10 08:08:25,633 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-10 08:08:25,651 INFO L174 MainTranslator]: Built tables and reachable declarations [2018-11-10 08:08:25,758 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-11-10 08:08:25,762 INFO L189 MainTranslator]: Completed pre-run [2018-11-10 08:08:25,784 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-11-10 08:08:25,794 INFO L193 MainTranslator]: Completed translation [2018-11-10 08:08:25,794 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 08:08:25 WrapperNode [2018-11-10 08:08:25,794 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-10 08:08:25,795 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-10 08:08:25,795 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-10 08:08:25,795 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-10 08:08:25,800 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 08:08:25" (1/1) ... [2018-11-10 08:08:25,804 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 08:08:25" (1/1) ... [2018-11-10 08:08:25,823 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-10 08:08:25,823 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-10 08:08:25,823 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-10 08:08:25,823 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-10 08:08:25,829 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 08:08:25" (1/1) ... [2018-11-10 08:08:25,829 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 08:08:25" (1/1) ... [2018-11-10 08:08:25,831 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 08:08:25" (1/1) ... [2018-11-10 08:08:25,831 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 08:08:25" (1/1) ... [2018-11-10 08:08:25,835 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 08:08:25" (1/1) ... [2018-11-10 08:08:25,891 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 08:08:25" (1/1) ... [2018-11-10 08:08:25,892 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 08:08:25" (1/1) ... [2018-11-10 08:08:25,893 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-10 08:08:25,894 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-10 08:08:25,894 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-10 08:08:25,894 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-10 08:08:25,894 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 08:08:25" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3ff55cc6-e111-44d6-94ef-9fb4125db8b6/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-10 08:08:25,938 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-10 08:08:25,938 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-10 08:08:26,341 INFO L341 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-10 08:08:26,341 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.11 08:08:26 BoogieIcfgContainer [2018-11-10 08:08:26,341 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-10 08:08:26,342 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2018-11-10 08:08:26,342 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2018-11-10 08:08:26,344 INFO L276 PluginConnector]: BuchiAutomizer initialized [2018-11-10 08:08:26,344 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-10 08:08:26,344 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 10.11 08:08:25" (1/3) ... [2018-11-10 08:08:26,345 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7f839380 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 10.11 08:08:26, skipping insertion in model container [2018-11-10 08:08:26,345 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-10 08:08:26,345 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 08:08:25" (2/3) ... [2018-11-10 08:08:26,345 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7f839380 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 10.11 08:08:26, skipping insertion in model container [2018-11-10 08:08:26,345 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-10 08:08:26,346 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.11 08:08:26" (3/3) ... [2018-11-10 08:08:26,347 INFO L375 chiAutomizerObserver]: Analyzing ICFG token_ring.01_true-unreach-call_false-termination.cil.c [2018-11-10 08:08:26,379 INFO L135 ementStrategyFactory]: Using default assertion order modulation [2018-11-10 08:08:26,379 INFO L374 BuchiCegarLoop]: Interprodecural is true [2018-11-10 08:08:26,379 INFO L375 BuchiCegarLoop]: Hoare is false [2018-11-10 08:08:26,379 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2018-11-10 08:08:26,379 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-10 08:08:26,379 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-10 08:08:26,380 INFO L379 BuchiCegarLoop]: Difference is false [2018-11-10 08:08:26,380 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-10 08:08:26,380 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2018-11-10 08:08:26,392 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 156 states. [2018-11-10 08:08:26,413 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 121 [2018-11-10 08:08:26,413 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 08:08:26,413 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 08:08:26,419 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:08:26,419 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:08:26,419 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ [2018-11-10 08:08:26,419 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 156 states. [2018-11-10 08:08:26,423 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 121 [2018-11-10 08:08:26,423 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 08:08:26,423 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 08:08:26,424 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:08:26,424 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:08:26,431 INFO L793 eck$LassoCheckResult]: Stem: 117#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 9#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 35#L381true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret7, start_simulation_#t~ret8, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 13#L153true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 106#L160true assume !(~m_i~0 == 1);~m_st~0 := 2; 91#L160-2true assume ~t1_i~0 == 1;~t1_st~0 := 0; 119#L165-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46#L249true assume !(~M_E~0 == 0); 40#L249-2true assume !(~T1_E~0 == 0); 60#L254-1true assume !(~E_M~0 == 0); 111#L259-1true assume !(~E_1~0 == 0); 116#L264-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 27#L114true assume ~m_pc~0 == 1; 133#L115true assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 28#L125true is_master_triggered_#res := is_master_triggered_~__retres1~0; 134#L126true activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 92#L309true assume !(activate_threads_~tmp~1 != 0); 67#L309-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 51#L133true assume ~t1_pc~0 == 1; 144#L134true assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 53#L144true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 145#L145true activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 96#L317true assume !(activate_threads_~tmp___0~0 != 0); 98#L317-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11#L277true assume !(~M_E~0 == 1); 150#L277-2true assume !(~T1_E~0 == 1); 47#L282-1true assume !(~E_M~0 == 1); 61#L287-1true assume !(~E_1~0 == 1); 112#L292-1true assume { :end_inline_reset_delta_events } true; 135#L418-3true [2018-11-10 08:08:26,432 INFO L795 eck$LassoCheckResult]: Loop: 135#L418-3true assume true; 129#L418-1true assume !false; 88#L419true start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_~tmp~0;havoc eval_~tmp~0; 68#L224true assume !true; 121#L239true assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 12#L153-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 36#L249-3true assume ~M_E~0 == 0;~M_E~0 := 1; 8#L249-5true assume ~T1_E~0 == 0;~T1_E~0 := 1; 54#L254-3true assume ~E_M~0 == 0;~E_M~0 := 1; 107#L259-3true assume ~E_1~0 == 0;~E_1~0 := 1; 114#L264-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7#L114-9true assume !(~m_pc~0 == 1); 5#L114-11true is_master_triggered_~__retres1~0 := 0; 17#L125-3true is_master_triggered_#res := is_master_triggered_~__retres1~0; 125#L126-3true activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 58#L309-9true assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 62#L309-11true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 24#L133-9true assume !(~t1_pc~0 == 1); 18#L133-11true is_transmit1_triggered_~__retres1~1 := 0; 78#L144-3true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 157#L145-3true activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 64#L317-9true assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 71#L317-11true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 149#L277-3true assume ~M_E~0 == 1;~M_E~0 := 2; 141#L277-5true assume ~T1_E~0 == 1;~T1_E~0 := 2; 41#L282-3true assume !(~E_M~0 == 1); 57#L287-3true assume ~E_1~0 == 1;~E_1~0 := 2; 109#L292-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 146#L178-1true assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 102#L190-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 31#L191-1true start_simulation_#t~ret7 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret7;havoc start_simulation_#t~ret7; 151#L437true assume !(start_simulation_~tmp~3 == 0); 136#L437-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret6, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 143#L178-2true assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 101#L190-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 30#L191-2true stop_simulation_#t~ret6 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret6;havoc stop_simulation_#t~ret6; 34#L392true assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 120#L399true stop_simulation_#res := stop_simulation_~__retres2~0; 82#L400true start_simulation_#t~ret8 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 23#L450true assume !(start_simulation_~tmp___0~1 != 0); 135#L418-3true [2018-11-10 08:08:26,435 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:08:26,435 INFO L82 PathProgramCache]: Analyzing trace with hash -704910459, now seen corresponding path program 1 times [2018-11-10 08:08:26,436 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:08:26,437 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:08:26,473 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:26,473 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:08:26,473 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:26,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:08:26,529 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 08:08:26,531 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 08:08:26,532 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 08:08:26,535 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 08:08:26,535 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:08:26,535 INFO L82 PathProgramCache]: Analyzing trace with hash -900877463, now seen corresponding path program 1 times [2018-11-10 08:08:26,535 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:08:26,535 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:08:26,536 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:26,536 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:08:26,536 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:26,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:08:26,545 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 08:08:26,546 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 08:08:26,546 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 08:08:26,547 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 08:08:26,560 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 08:08:26,560 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 08:08:26,561 INFO L87 Difference]: Start difference. First operand 156 states. Second operand 3 states. [2018-11-10 08:08:26,583 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 08:08:26,583 INFO L93 Difference]: Finished difference Result 155 states and 223 transitions. [2018-11-10 08:08:26,584 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 08:08:26,585 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 155 states and 223 transitions. [2018-11-10 08:08:26,587 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 119 [2018-11-10 08:08:26,590 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 155 states to 150 states and 218 transitions. [2018-11-10 08:08:26,591 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 150 [2018-11-10 08:08:26,592 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 150 [2018-11-10 08:08:26,592 INFO L73 IsDeterministic]: Start isDeterministic. Operand 150 states and 218 transitions. [2018-11-10 08:08:26,593 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 08:08:26,593 INFO L705 BuchiCegarLoop]: Abstraction has 150 states and 218 transitions. [2018-11-10 08:08:26,604 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150 states and 218 transitions. [2018-11-10 08:08:26,613 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150 to 150. [2018-11-10 08:08:26,614 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 150 states. [2018-11-10 08:08:26,615 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 150 states to 150 states and 218 transitions. [2018-11-10 08:08:26,615 INFO L728 BuchiCegarLoop]: Abstraction has 150 states and 218 transitions. [2018-11-10 08:08:26,615 INFO L608 BuchiCegarLoop]: Abstraction has 150 states and 218 transitions. [2018-11-10 08:08:26,615 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ [2018-11-10 08:08:26,616 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 150 states and 218 transitions. [2018-11-10 08:08:26,617 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 119 [2018-11-10 08:08:26,617 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 08:08:26,617 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 08:08:26,618 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:08:26,618 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:08:26,619 INFO L793 eck$LassoCheckResult]: Stem: 466#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 332#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 333#L381 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret7, start_simulation_#t~ret8, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 338#L153 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 339#L160 assume ~m_i~0 == 1;~m_st~0 := 0; 446#L160-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 447#L165-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 397#L249 assume !(~M_E~0 == 0); 389#L249-2 assume !(~T1_E~0 == 0); 390#L254-1 assume !(~E_M~0 == 0); 416#L259-1 assume !(~E_1~0 == 0); 464#L264-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 366#L114 assume ~m_pc~0 == 1; 367#L115 assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 352#L125 is_master_triggered_#res := is_master_triggered_~__retres1~0; 370#L126 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 448#L309 assume !(activate_threads_~tmp~1 != 0); 424#L309-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 404#L133 assume ~t1_pc~0 == 1; 405#L134 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 407#L144 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 408#L145 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 452#L317 assume !(activate_threads_~tmp___0~0 != 0); 453#L317-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 334#L277 assume !(~M_E~0 == 1); 335#L277-2 assume !(~T1_E~0 == 1); 398#L282-1 assume !(~E_M~0 == 1); 399#L287-1 assume !(~E_1~0 == 1); 417#L292-1 assume { :end_inline_reset_delta_events } true; 356#L418-3 [2018-11-10 08:08:26,619 INFO L795 eck$LassoCheckResult]: Loop: 356#L418-3 assume true; 467#L418-1 assume !false; 442#L419 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_~tmp~0;havoc eval_~tmp~0; 365#L224 assume true; 425#L200-1 assume !false; 458#L201 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 459#L178 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 457#L190 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 420#L191 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 391#L205 assume !(eval_~tmp~0 != 0); 392#L239 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 336#L153-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 337#L249-3 assume ~M_E~0 == 0;~M_E~0 := 1; 330#L249-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 331#L254-3 assume ~E_M~0 == 0;~E_M~0 := 1; 409#L259-3 assume ~E_1~0 == 0;~E_1~0 := 1; 461#L264-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 328#L114-9 assume !(~m_pc~0 == 1); 326#L114-11 is_master_triggered_~__retres1~0 := 0; 327#L125-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 348#L126-3 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 414#L309-9 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 415#L309-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 360#L133-9 assume !(~t1_pc~0 == 1); 344#L133-11 is_transmit1_triggered_~__retres1~1 := 0; 345#L144-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 435#L145-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 418#L317-9 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 419#L317-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 426#L277-3 assume ~M_E~0 == 1;~M_E~0 := 2; 469#L277-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 385#L282-3 assume !(~E_M~0 == 1); 386#L287-3 assume ~E_1~0 == 1;~E_1~0 := 2; 413#L292-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 463#L178-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 456#L190-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 373#L191-1 start_simulation_#t~ret7 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret7;havoc start_simulation_#t~ret7; 374#L437 assume !(start_simulation_~tmp~3 == 0); 325#L437-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret6, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 468#L178-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 450#L190-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 368#L191-2 stop_simulation_#t~ret6 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret6;havoc stop_simulation_#t~ret6; 369#L392 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 378#L399 stop_simulation_#res := stop_simulation_~__retres2~0; 437#L400 start_simulation_#t~ret8 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 355#L450 assume !(start_simulation_~tmp___0~1 != 0); 356#L418-3 [2018-11-10 08:08:26,619 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:08:26,619 INFO L82 PathProgramCache]: Analyzing trace with hash -845459069, now seen corresponding path program 1 times [2018-11-10 08:08:26,619 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:08:26,619 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:08:26,620 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:26,620 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:08:26,620 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:26,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:08:26,655 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 08:08:26,655 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 08:08:26,655 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 08:08:26,655 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 08:08:26,655 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:08:26,656 INFO L82 PathProgramCache]: Analyzing trace with hash 1637572638, now seen corresponding path program 1 times [2018-11-10 08:08:26,656 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:08:26,656 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:08:26,656 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:26,657 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:08:26,657 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:26,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:08:26,700 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 08:08:26,700 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 08:08:26,700 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 08:08:26,700 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 08:08:26,700 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 08:08:26,701 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 08:08:26,701 INFO L87 Difference]: Start difference. First operand 150 states and 218 transitions. cyclomatic complexity: 69 Second operand 3 states. [2018-11-10 08:08:26,742 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 08:08:26,743 INFO L93 Difference]: Finished difference Result 262 states and 372 transitions. [2018-11-10 08:08:26,743 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 08:08:26,743 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 262 states and 372 transitions. [2018-11-10 08:08:26,745 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 230 [2018-11-10 08:08:26,747 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 262 states to 262 states and 372 transitions. [2018-11-10 08:08:26,747 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 262 [2018-11-10 08:08:26,748 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 262 [2018-11-10 08:08:26,748 INFO L73 IsDeterministic]: Start isDeterministic. Operand 262 states and 372 transitions. [2018-11-10 08:08:26,749 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 08:08:26,749 INFO L705 BuchiCegarLoop]: Abstraction has 262 states and 372 transitions. [2018-11-10 08:08:26,750 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 262 states and 372 transitions. [2018-11-10 08:08:26,757 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 262 to 249. [2018-11-10 08:08:26,757 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 249 states. [2018-11-10 08:08:26,759 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 249 states to 249 states and 355 transitions. [2018-11-10 08:08:26,759 INFO L728 BuchiCegarLoop]: Abstraction has 249 states and 355 transitions. [2018-11-10 08:08:26,759 INFO L608 BuchiCegarLoop]: Abstraction has 249 states and 355 transitions. [2018-11-10 08:08:26,759 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ [2018-11-10 08:08:26,759 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 249 states and 355 transitions. [2018-11-10 08:08:26,761 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 217 [2018-11-10 08:08:26,761 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 08:08:26,761 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 08:08:26,762 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:08:26,762 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:08:26,762 INFO L793 eck$LassoCheckResult]: Stem: 882#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 749#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 750#L381 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret7, start_simulation_#t~ret8, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 755#L153 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 756#L160 assume ~m_i~0 == 1;~m_st~0 := 0; 862#L160-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 863#L165-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 811#L249 assume !(~M_E~0 == 0); 802#L249-2 assume !(~T1_E~0 == 0); 803#L254-1 assume !(~E_M~0 == 0); 832#L259-1 assume !(~E_1~0 == 0); 880#L264-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 781#L114 assume !(~m_pc~0 == 1); 766#L114-2 is_master_triggered_~__retres1~0 := 0; 767#L125 is_master_triggered_#res := is_master_triggered_~__retres1~0; 786#L126 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 864#L309 assume !(activate_threads_~tmp~1 != 0); 841#L309-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 818#L133 assume ~t1_pc~0 == 1; 819#L134 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 821#L144 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 822#L145 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 868#L317 assume !(activate_threads_~tmp___0~0 != 0); 869#L317-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 751#L277 assume !(~M_E~0 == 1); 752#L277-2 assume !(~T1_E~0 == 1); 812#L282-1 assume !(~E_M~0 == 1); 813#L287-1 assume !(~E_1~0 == 1); 833#L292-1 assume { :end_inline_reset_delta_events } true; 774#L418-3 [2018-11-10 08:08:26,763 INFO L795 eck$LassoCheckResult]: Loop: 774#L418-3 assume true; 896#L418-1 assume !false; 858#L419 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_~tmp~0;havoc eval_~tmp~0; 780#L224 assume true; 840#L200-1 assume !false; 874#L201 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 875#L178 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 873#L190 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 834#L191 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 804#L205 assume !(eval_~tmp~0 != 0); 805#L239 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 753#L153-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 754#L249-3 assume ~M_E~0 == 0;~M_E~0 := 1; 747#L249-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 748#L254-3 assume ~E_M~0 == 0;~E_M~0 := 1; 823#L259-3 assume ~E_1~0 == 0;~E_1~0 := 1; 877#L264-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 746#L114-9 assume !(~m_pc~0 == 1); 742#L114-11 is_master_triggered_~__retres1~0 := 0; 743#L125-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 762#L126-3 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 829#L309-9 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 830#L309-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 777#L133-9 assume ~t1_pc~0 == 1; 778#L134-3 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 764#L144-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 852#L145-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 836#L317-9 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 837#L317-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 844#L277-3 assume ~M_E~0 == 1;~M_E~0 := 2; 898#L277-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 798#L282-3 assume !(~E_M~0 == 1); 799#L287-3 assume ~E_1~0 == 1;~E_1~0 := 2; 828#L292-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 879#L178-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 872#L190-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 787#L191-1 start_simulation_#t~ret7 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret7;havoc start_simulation_#t~ret7; 788#L437 assume !(start_simulation_~tmp~3 == 0); 745#L437-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret6, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 897#L178-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 866#L190-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 784#L191-2 stop_simulation_#t~ret6 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret6;havoc stop_simulation_#t~ret6; 785#L392 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 792#L399 stop_simulation_#res := stop_simulation_~__retres2~0; 853#L400 start_simulation_#t~ret8 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 773#L450 assume !(start_simulation_~tmp___0~1 != 0); 774#L418-3 [2018-11-10 08:08:26,763 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:08:26,763 INFO L82 PathProgramCache]: Analyzing trace with hash 1269536452, now seen corresponding path program 1 times [2018-11-10 08:08:26,763 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:08:26,763 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:08:26,764 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:26,764 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:08:26,764 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:26,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:08:26,799 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 08:08:26,799 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 08:08:26,799 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 08:08:26,800 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 08:08:26,800 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:08:26,800 INFO L82 PathProgramCache]: Analyzing trace with hash 857591709, now seen corresponding path program 1 times [2018-11-10 08:08:26,800 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:08:26,800 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:08:26,801 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:26,801 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:08:26,801 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:26,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:08:26,827 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 08:08:26,827 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 08:08:26,827 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 08:08:26,827 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 08:08:26,827 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 08:08:26,828 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 08:08:26,828 INFO L87 Difference]: Start difference. First operand 249 states and 355 transitions. cyclomatic complexity: 108 Second operand 3 states. [2018-11-10 08:08:26,884 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 08:08:26,884 INFO L93 Difference]: Finished difference Result 429 states and 604 transitions. [2018-11-10 08:08:26,885 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 08:08:26,885 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 429 states and 604 transitions. [2018-11-10 08:08:26,888 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 392 [2018-11-10 08:08:26,890 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 429 states to 429 states and 604 transitions. [2018-11-10 08:08:26,890 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 429 [2018-11-10 08:08:26,891 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 429 [2018-11-10 08:08:26,891 INFO L73 IsDeterministic]: Start isDeterministic. Operand 429 states and 604 transitions. [2018-11-10 08:08:26,893 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 08:08:26,893 INFO L705 BuchiCegarLoop]: Abstraction has 429 states and 604 transitions. [2018-11-10 08:08:26,893 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 429 states and 604 transitions. [2018-11-10 08:08:26,903 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 429 to 423. [2018-11-10 08:08:26,903 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 423 states. [2018-11-10 08:08:26,904 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 423 states to 423 states and 598 transitions. [2018-11-10 08:08:26,904 INFO L728 BuchiCegarLoop]: Abstraction has 423 states and 598 transitions. [2018-11-10 08:08:26,905 INFO L608 BuchiCegarLoop]: Abstraction has 423 states and 598 transitions. [2018-11-10 08:08:26,905 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ [2018-11-10 08:08:26,905 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 423 states and 598 transitions. [2018-11-10 08:08:26,907 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 386 [2018-11-10 08:08:26,907 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 08:08:26,907 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 08:08:26,908 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:08:26,908 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:08:26,908 INFO L793 eck$LassoCheckResult]: Stem: 1570#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 1435#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 1436#L381 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret7, start_simulation_#t~ret8, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 1441#L153 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1442#L160 assume ~m_i~0 == 1;~m_st~0 := 0; 1548#L160-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 1549#L165-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1496#L249 assume !(~M_E~0 == 0); 1487#L249-2 assume !(~T1_E~0 == 0); 1488#L254-1 assume !(~E_M~0 == 0); 1515#L259-1 assume !(~E_1~0 == 0); 1567#L264-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1465#L114 assume !(~m_pc~0 == 1); 1452#L114-2 is_master_triggered_~__retres1~0 := 0; 1453#L125 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1470#L126 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 1550#L309 assume !(activate_threads_~tmp~1 != 0); 1525#L309-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1503#L133 assume !(~t1_pc~0 == 1); 1504#L133-2 is_transmit1_triggered_~__retres1~1 := 0; 1505#L144 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1506#L145 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 1554#L317 assume !(activate_threads_~tmp___0~0 != 0); 1555#L317-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1437#L277 assume !(~M_E~0 == 1); 1438#L277-2 assume !(~T1_E~0 == 1); 1497#L282-1 assume !(~E_M~0 == 1); 1498#L287-1 assume !(~E_1~0 == 1); 1516#L292-1 assume { :end_inline_reset_delta_events } true; 1568#L418-3 [2018-11-10 08:08:26,908 INFO L795 eck$LassoCheckResult]: Loop: 1568#L418-3 assume true; 1691#L418-1 assume !false; 1689#L419 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_~tmp~0;havoc eval_~tmp~0; 1493#L224 assume true; 1685#L200-1 assume !false; 1683#L201 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 1675#L178 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 1673#L190 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 1671#L191 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 1668#L205 assume !(eval_~tmp~0 != 0); 1669#L239 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 1775#L153-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 1773#L249-3 assume ~M_E~0 == 0;~M_E~0 := 1; 1771#L249-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 1767#L254-3 assume ~E_M~0 == 0;~E_M~0 := 1; 1563#L259-3 assume ~E_1~0 == 0;~E_1~0 := 1; 1564#L264-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1431#L114-9 assume !(~m_pc~0 == 1); 1432#L114-11 is_master_triggered_~__retres1~0 := 0; 1770#L125-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1768#L126-3 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 1766#L309-9 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 1765#L309-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1462#L133-9 assume !(~t1_pc~0 == 1); 1449#L133-11 is_transmit1_triggered_~__retres1~1 := 0; 1450#L144-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1536#L145-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 1753#L317-9 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 1752#L317-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1751#L277-3 assume ~M_E~0 == 1;~M_E~0 := 2; 1749#L277-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 1747#L282-3 assume !(~E_M~0 == 1); 1745#L287-3 assume ~E_1~0 == 1;~E_1~0 := 2; 1743#L292-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 1741#L178-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 1738#L190-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 1736#L191-1 start_simulation_#t~ret7 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret7;havoc start_simulation_#t~ret7; 1735#L437 assume !(start_simulation_~tmp~3 == 0); 1710#L437-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret6, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 1707#L178-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 1704#L190-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 1702#L191-2 stop_simulation_#t~ret6 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret6;havoc stop_simulation_#t~ret6; 1700#L392 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 1698#L399 stop_simulation_#res := stop_simulation_~__retres2~0; 1696#L400 start_simulation_#t~ret8 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 1694#L450 assume !(start_simulation_~tmp___0~1 != 0); 1568#L418-3 [2018-11-10 08:08:26,908 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:08:26,908 INFO L82 PathProgramCache]: Analyzing trace with hash 396697797, now seen corresponding path program 1 times [2018-11-10 08:08:26,908 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:08:26,908 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:08:26,909 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:26,909 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:08:26,909 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:26,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 08:08:26,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 08:08:26,933 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:08:26,934 INFO L82 PathProgramCache]: Analyzing trace with hash 1637572638, now seen corresponding path program 2 times [2018-11-10 08:08:26,934 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:08:26,934 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:08:26,934 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:26,934 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:08:26,935 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:26,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:08:26,960 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 08:08:26,961 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 08:08:26,961 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 08:08:26,961 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 08:08:26,961 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 08:08:26,961 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 08:08:26,961 INFO L87 Difference]: Start difference. First operand 423 states and 598 transitions. cyclomatic complexity: 179 Second operand 3 states. [2018-11-10 08:08:27,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 08:08:27,016 INFO L93 Difference]: Finished difference Result 633 states and 881 transitions. [2018-11-10 08:08:27,017 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 08:08:27,017 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 633 states and 881 transitions. [2018-11-10 08:08:27,019 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 577 [2018-11-10 08:08:27,020 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 633 states to 633 states and 881 transitions. [2018-11-10 08:08:27,021 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 633 [2018-11-10 08:08:27,021 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 633 [2018-11-10 08:08:27,021 INFO L73 IsDeterministic]: Start isDeterministic. Operand 633 states and 881 transitions. [2018-11-10 08:08:27,022 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 08:08:27,022 INFO L705 BuchiCegarLoop]: Abstraction has 633 states and 881 transitions. [2018-11-10 08:08:27,022 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 633 states and 881 transitions. [2018-11-10 08:08:27,030 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 633 to 632. [2018-11-10 08:08:27,030 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 632 states. [2018-11-10 08:08:27,032 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 632 states to 632 states and 880 transitions. [2018-11-10 08:08:27,032 INFO L728 BuchiCegarLoop]: Abstraction has 632 states and 880 transitions. [2018-11-10 08:08:27,032 INFO L608 BuchiCegarLoop]: Abstraction has 632 states and 880 transitions. [2018-11-10 08:08:27,032 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ [2018-11-10 08:08:27,032 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 632 states and 880 transitions. [2018-11-10 08:08:27,035 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 576 [2018-11-10 08:08:27,035 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 08:08:27,035 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 08:08:27,036 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:08:27,036 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:08:27,037 INFO L793 eck$LassoCheckResult]: Stem: 2655#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 2499#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 2500#L381 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret7, start_simulation_#t~ret8, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 2505#L153 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2506#L160 assume ~m_i~0 == 1;~m_st~0 := 0; 2626#L160-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 2627#L165-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2567#L249 assume !(~M_E~0 == 0); 2557#L249-2 assume !(~T1_E~0 == 0); 2558#L254-1 assume ~E_M~0 == 0;~E_M~0 := 1; 2586#L259-1 assume !(~E_1~0 == 0); 2718#L264-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2717#L114 assume !(~m_pc~0 == 1); 2518#L114-2 is_master_triggered_~__retres1~0 := 0; 2519#L125 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2538#L126 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 2628#L309 assume !(activate_threads_~tmp~1 != 0); 2629#L309-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2705#L133 assume !(~t1_pc~0 == 1); 2701#L133-2 is_transmit1_triggered_~__retres1~1 := 0; 2699#L144 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2678#L145 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 2633#L317 assume !(activate_threads_~tmp___0~0 != 0); 2634#L317-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2501#L277 assume !(~M_E~0 == 1); 2502#L277-2 assume !(~T1_E~0 == 1); 2568#L282-1 assume ~E_M~0 == 1;~E_M~0 := 2; 2569#L287-1 assume !(~E_1~0 == 1); 2588#L292-1 assume { :end_inline_reset_delta_events } true; 2653#L418-3 [2018-11-10 08:08:27,037 INFO L795 eck$LassoCheckResult]: Loop: 2653#L418-3 assume true; 2774#L418-1 assume !false; 2770#L419 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_~tmp~0;havoc eval_~tmp~0; 2733#L224 assume true; 2765#L200-1 assume !false; 2761#L201 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 2757#L178 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 2754#L190 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 2747#L191 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 2743#L205 assume !(eval_~tmp~0 != 0); 2744#L239 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 2895#L153-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 2894#L249-3 assume ~M_E~0 == 0;~M_E~0 := 1; 2893#L249-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 2892#L254-3 assume !(~E_M~0 == 0); 2890#L259-3 assume ~E_1~0 == 0;~E_1~0 := 1; 2888#L264-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2886#L114-9 assume !(~m_pc~0 == 1); 2884#L114-11 is_master_triggered_~__retres1~0 := 0; 2882#L125-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2880#L126-3 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 2878#L309-9 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 2875#L309-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2872#L133-9 assume !(~t1_pc~0 == 1); 2869#L133-11 is_transmit1_triggered_~__retres1~1 := 0; 2866#L144-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2863#L145-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 2860#L317-9 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 2857#L317-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2854#L277-3 assume ~M_E~0 == 1;~M_E~0 := 2; 2851#L277-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 2848#L282-3 assume !(~E_M~0 == 1); 2846#L287-3 assume ~E_1~0 == 1;~E_1~0 := 2; 2844#L292-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 2842#L178-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 2839#L190-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 2837#L191-1 start_simulation_#t~ret7 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret7;havoc start_simulation_#t~ret7; 2834#L437 assume !(start_simulation_~tmp~3 == 0); 2832#L437-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret6, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 2830#L178-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 2801#L190-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 2796#L191-2 stop_simulation_#t~ret6 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret6;havoc stop_simulation_#t~ret6; 2793#L392 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 2790#L399 stop_simulation_#res := stop_simulation_~__retres2~0; 2786#L400 start_simulation_#t~ret8 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 2781#L450 assume !(start_simulation_~tmp___0~1 != 0); 2653#L418-3 [2018-11-10 08:08:27,037 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:08:27,037 INFO L82 PathProgramCache]: Analyzing trace with hash 1214344325, now seen corresponding path program 1 times [2018-11-10 08:08:27,037 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:08:27,037 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:08:27,038 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:27,038 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 08:08:27,040 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:27,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:08:27,061 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 08:08:27,061 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 08:08:27,061 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 08:08:27,062 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 08:08:27,062 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:08:27,062 INFO L82 PathProgramCache]: Analyzing trace with hash 1912332252, now seen corresponding path program 1 times [2018-11-10 08:08:27,062 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:08:27,062 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:08:27,063 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:27,063 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:08:27,063 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:27,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:08:27,110 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 08:08:27,110 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 08:08:27,110 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 08:08:27,111 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 08:08:27,111 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 08:08:27,111 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 08:08:27,111 INFO L87 Difference]: Start difference. First operand 632 states and 880 transitions. cyclomatic complexity: 252 Second operand 3 states. [2018-11-10 08:08:27,162 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 08:08:27,162 INFO L93 Difference]: Finished difference Result 423 states and 577 transitions. [2018-11-10 08:08:27,163 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 08:08:27,163 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 423 states and 577 transitions. [2018-11-10 08:08:27,166 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 386 [2018-11-10 08:08:27,168 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 423 states to 423 states and 577 transitions. [2018-11-10 08:08:27,170 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 423 [2018-11-10 08:08:27,170 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 423 [2018-11-10 08:08:27,170 INFO L73 IsDeterministic]: Start isDeterministic. Operand 423 states and 577 transitions. [2018-11-10 08:08:27,171 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 08:08:27,171 INFO L705 BuchiCegarLoop]: Abstraction has 423 states and 577 transitions. [2018-11-10 08:08:27,172 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 423 states and 577 transitions. [2018-11-10 08:08:27,180 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 423 to 423. [2018-11-10 08:08:27,180 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 423 states. [2018-11-10 08:08:27,181 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 423 states to 423 states and 577 transitions. [2018-11-10 08:08:27,182 INFO L728 BuchiCegarLoop]: Abstraction has 423 states and 577 transitions. [2018-11-10 08:08:27,182 INFO L608 BuchiCegarLoop]: Abstraction has 423 states and 577 transitions. [2018-11-10 08:08:27,182 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ [2018-11-10 08:08:27,182 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 423 states and 577 transitions. [2018-11-10 08:08:27,184 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 386 [2018-11-10 08:08:27,184 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 08:08:27,184 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 08:08:27,185 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:08:27,185 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:08:27,185 INFO L793 eck$LassoCheckResult]: Stem: 3694#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 3560#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 3561#L381 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret7, start_simulation_#t~ret8, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 3566#L153 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3567#L160 assume ~m_i~0 == 1;~m_st~0 := 0; 3673#L160-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 3674#L165-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3620#L249 assume !(~M_E~0 == 0); 3609#L249-2 assume !(~T1_E~0 == 0); 3610#L254-1 assume !(~E_M~0 == 0); 3639#L259-1 assume !(~E_1~0 == 0); 3692#L264-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3591#L114 assume !(~m_pc~0 == 1); 3578#L114-2 is_master_triggered_~__retres1~0 := 0; 3579#L125 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3592#L126 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 3675#L309 assume !(activate_threads_~tmp~1 != 0); 3647#L309-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3626#L133 assume !(~t1_pc~0 == 1); 3627#L133-2 is_transmit1_triggered_~__retres1~1 := 0; 3630#L144 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3631#L145 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 3679#L317 assume !(activate_threads_~tmp___0~0 != 0); 3680#L317-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3562#L277 assume !(~M_E~0 == 1); 3563#L277-2 assume !(~T1_E~0 == 1); 3621#L282-1 assume !(~E_M~0 == 1); 3622#L287-1 assume !(~E_1~0 == 1); 3640#L292-1 assume { :end_inline_reset_delta_events } true; 3585#L418-3 [2018-11-10 08:08:27,185 INFO L795 eck$LassoCheckResult]: Loop: 3585#L418-3 assume true; 3701#L418-1 assume !false; 3668#L419 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_~tmp~0;havoc eval_~tmp~0; 3619#L224 assume true; 3648#L200-1 assume !false; 3685#L201 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 3686#L178 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 3684#L190 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 3641#L191 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 3615#L205 assume !(eval_~tmp~0 != 0); 3616#L239 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 3564#L153-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 3565#L249-3 assume ~M_E~0 == 0;~M_E~0 := 1; 3558#L249-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 3559#L254-3 assume !(~E_M~0 == 0); 3632#L259-3 assume ~E_1~0 == 0;~E_1~0 := 1; 3688#L264-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3557#L114-9 assume !(~m_pc~0 == 1); 3553#L114-11 is_master_triggered_~__retres1~0 := 0; 3554#L125-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3573#L126-3 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 3637#L309-9 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 3638#L309-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3588#L133-9 assume !(~t1_pc~0 == 1); 3574#L133-11 is_transmit1_triggered_~__retres1~1 := 0; 3575#L144-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3660#L145-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 3642#L317-9 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 3643#L317-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3652#L277-3 assume ~M_E~0 == 1;~M_E~0 := 2; 3709#L277-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 3611#L282-3 assume !(~E_M~0 == 1); 3612#L287-3 assume ~E_1~0 == 1;~E_1~0 := 2; 3636#L292-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 3710#L178-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 3683#L190-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 3597#L191-1 start_simulation_#t~ret7 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret7;havoc start_simulation_#t~ret7; 3598#L437 assume !(start_simulation_~tmp~3 == 0); 3556#L437-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret6, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 3704#L178-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 3677#L190-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 3595#L191-2 stop_simulation_#t~ret6 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret6;havoc stop_simulation_#t~ret6; 3596#L392 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 3602#L399 stop_simulation_#res := stop_simulation_~__retres2~0; 3663#L400 start_simulation_#t~ret8 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 3584#L450 assume !(start_simulation_~tmp___0~1 != 0); 3585#L418-3 [2018-11-10 08:08:27,185 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:08:27,186 INFO L82 PathProgramCache]: Analyzing trace with hash 396697797, now seen corresponding path program 2 times [2018-11-10 08:08:27,186 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:08:27,186 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:08:27,187 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:27,187 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:08:27,187 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:27,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 08:08:27,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 08:08:27,197 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:08:27,197 INFO L82 PathProgramCache]: Analyzing trace with hash 1912332252, now seen corresponding path program 2 times [2018-11-10 08:08:27,197 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:08:27,198 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:08:27,198 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:27,198 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 08:08:27,199 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:27,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:08:27,249 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 08:08:27,250 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 08:08:27,250 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 08:08:27,250 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 08:08:27,250 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 08:08:27,250 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 08:08:27,251 INFO L87 Difference]: Start difference. First operand 423 states and 577 transitions. cyclomatic complexity: 158 Second operand 5 states. [2018-11-10 08:08:27,318 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 08:08:27,319 INFO L93 Difference]: Finished difference Result 729 states and 970 transitions. [2018-11-10 08:08:27,319 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-10 08:08:27,319 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 729 states and 970 transitions. [2018-11-10 08:08:27,321 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 684 [2018-11-10 08:08:27,323 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 729 states to 729 states and 970 transitions. [2018-11-10 08:08:27,324 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 729 [2018-11-10 08:08:27,324 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 729 [2018-11-10 08:08:27,324 INFO L73 IsDeterministic]: Start isDeterministic. Operand 729 states and 970 transitions. [2018-11-10 08:08:27,325 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 08:08:27,325 INFO L705 BuchiCegarLoop]: Abstraction has 729 states and 970 transitions. [2018-11-10 08:08:27,326 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 729 states and 970 transitions. [2018-11-10 08:08:27,330 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 729 to 435. [2018-11-10 08:08:27,331 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 435 states. [2018-11-10 08:08:27,332 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 435 states to 435 states and 589 transitions. [2018-11-10 08:08:27,332 INFO L728 BuchiCegarLoop]: Abstraction has 435 states and 589 transitions. [2018-11-10 08:08:27,332 INFO L608 BuchiCegarLoop]: Abstraction has 435 states and 589 transitions. [2018-11-10 08:08:27,332 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ [2018-11-10 08:08:27,332 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 435 states and 589 transitions. [2018-11-10 08:08:27,333 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 398 [2018-11-10 08:08:27,333 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 08:08:27,334 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 08:08:27,334 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:08:27,334 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:08:27,335 INFO L793 eck$LassoCheckResult]: Stem: 4865#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 4728#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 4729#L381 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret7, start_simulation_#t~ret8, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 4734#L153 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4735#L160 assume ~m_i~0 == 1;~m_st~0 := 0; 4840#L160-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 4841#L165-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4789#L249 assume !(~M_E~0 == 0); 4782#L249-2 assume !(~T1_E~0 == 0); 4783#L254-1 assume !(~E_M~0 == 0); 4807#L259-1 assume !(~E_1~0 == 0); 4861#L264-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4760#L114 assume !(~m_pc~0 == 1); 4746#L114-2 is_master_triggered_~__retres1~0 := 0; 4747#L125 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4765#L126 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 4842#L309 assume !(activate_threads_~tmp~1 != 0); 4817#L309-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4796#L133 assume !(~t1_pc~0 == 1); 4797#L133-2 is_transmit1_triggered_~__retres1~1 := 0; 4798#L144 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4799#L145 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 4846#L317 assume !(activate_threads_~tmp___0~0 != 0); 4847#L317-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4730#L277 assume !(~M_E~0 == 1); 4731#L277-2 assume !(~T1_E~0 == 1); 4790#L282-1 assume !(~E_M~0 == 1); 4791#L287-1 assume !(~E_1~0 == 1); 4808#L292-1 assume { :end_inline_reset_delta_events } true; 4862#L418-3 [2018-11-10 08:08:27,335 INFO L795 eck$LassoCheckResult]: Loop: 4862#L418-3 assume true; 5006#L418-1 assume !false; 5004#L419 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_~tmp~0;havoc eval_~tmp~0; 4787#L224 assume true; 4983#L200-1 assume !false; 4972#L201 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 4969#L178 assume !(~m_st~0 == 0); 4964#L182 assume !(~t1_st~0 == 0);exists_runnable_thread_~__retres1~2 := 0; 4959#L190 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 4953#L191 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 4922#L205 assume !(eval_~tmp~0 != 0); 4923#L239 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 4951#L153-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 4950#L249-3 assume ~M_E~0 == 0;~M_E~0 := 1; 4726#L249-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 4727#L254-3 assume !(~E_M~0 == 0); 4800#L259-3 assume ~E_1~0 == 0;~E_1~0 := 1; 4856#L264-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4725#L114-9 assume !(~m_pc~0 == 1); 4721#L114-11 is_master_triggered_~__retres1~0 := 0; 4722#L125-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4925#L126-3 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 4926#L309-9 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 4809#L309-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4754#L133-9 assume !(~t1_pc~0 == 1); 4755#L133-11 is_transmit1_triggered_~__retres1~1 := 0; 5088#L144-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5087#L145-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 5086#L317-9 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 5085#L317-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5084#L277-3 assume ~M_E~0 == 1;~M_E~0 := 2; 5083#L277-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 5082#L282-3 assume !(~E_M~0 == 1); 5081#L287-3 assume ~E_1~0 == 1;~E_1~0 := 2; 5080#L292-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 5079#L178-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 5076#L190-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 5041#L191-1 start_simulation_#t~ret7 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret7;havoc start_simulation_#t~ret7; 5035#L437 assume !(start_simulation_~tmp~3 == 0); 5029#L437-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret6, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 5028#L178-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 5021#L190-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 5017#L191-2 stop_simulation_#t~ret6 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret6;havoc stop_simulation_#t~ret6; 5015#L392 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 5013#L399 stop_simulation_#res := stop_simulation_~__retres2~0; 5011#L400 start_simulation_#t~ret8 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 5009#L450 assume !(start_simulation_~tmp___0~1 != 0); 4862#L418-3 [2018-11-10 08:08:27,335 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:08:27,335 INFO L82 PathProgramCache]: Analyzing trace with hash 396697797, now seen corresponding path program 3 times [2018-11-10 08:08:27,335 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:08:27,335 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:08:27,336 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:27,336 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 08:08:27,336 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:27,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 08:08:27,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 08:08:27,346 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:08:27,346 INFO L82 PathProgramCache]: Analyzing trace with hash -788354865, now seen corresponding path program 1 times [2018-11-10 08:08:27,346 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:08:27,346 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:08:27,347 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:27,347 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 08:08:27,347 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:27,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:08:27,404 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 08:08:27,404 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 08:08:27,404 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 08:08:27,404 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 08:08:27,404 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 08:08:27,404 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 08:08:27,405 INFO L87 Difference]: Start difference. First operand 435 states and 589 transitions. cyclomatic complexity: 158 Second operand 5 states. [2018-11-10 08:08:27,460 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 08:08:27,460 INFO L93 Difference]: Finished difference Result 532 states and 708 transitions. [2018-11-10 08:08:27,461 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-10 08:08:27,461 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 708 transitions. [2018-11-10 08:08:27,463 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 495 [2018-11-10 08:08:27,464 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 532 states and 708 transitions. [2018-11-10 08:08:27,464 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2018-11-10 08:08:27,465 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2018-11-10 08:08:27,465 INFO L73 IsDeterministic]: Start isDeterministic. Operand 532 states and 708 transitions. [2018-11-10 08:08:27,466 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 08:08:27,466 INFO L705 BuchiCegarLoop]: Abstraction has 532 states and 708 transitions. [2018-11-10 08:08:27,466 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states and 708 transitions. [2018-11-10 08:08:27,470 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 438. [2018-11-10 08:08:27,470 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 438 states. [2018-11-10 08:08:27,471 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 438 states to 438 states and 580 transitions. [2018-11-10 08:08:27,471 INFO L728 BuchiCegarLoop]: Abstraction has 438 states and 580 transitions. [2018-11-10 08:08:27,471 INFO L608 BuchiCegarLoop]: Abstraction has 438 states and 580 transitions. [2018-11-10 08:08:27,471 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ [2018-11-10 08:08:27,472 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 438 states and 580 transitions. [2018-11-10 08:08:27,473 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 401 [2018-11-10 08:08:27,473 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 08:08:27,474 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 08:08:27,474 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:08:27,474 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:08:27,475 INFO L793 eck$LassoCheckResult]: Stem: 5850#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 5710#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 5711#L381 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret7, start_simulation_#t~ret8, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 5716#L153 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5717#L160 assume ~m_i~0 == 1;~m_st~0 := 0; 5826#L160-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 5827#L165-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5772#L249 assume !(~M_E~0 == 0); 5761#L249-2 assume !(~T1_E~0 == 0); 5762#L254-1 assume !(~E_M~0 == 0); 5792#L259-1 assume !(~E_1~0 == 0); 5846#L264-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5742#L114 assume !(~m_pc~0 == 1); 5728#L114-2 is_master_triggered_~__retres1~0 := 0; 5729#L125 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5743#L126 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 5828#L309 assume !(activate_threads_~tmp~1 != 0); 5800#L309-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5779#L133 assume !(~t1_pc~0 == 1); 5780#L133-2 is_transmit1_triggered_~__retres1~1 := 0; 5783#L144 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5784#L145 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 5832#L317 assume !(activate_threads_~tmp___0~0 != 0); 5833#L317-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5712#L277 assume !(~M_E~0 == 1); 5713#L277-2 assume !(~T1_E~0 == 1); 5773#L282-1 assume !(~E_M~0 == 1); 5774#L287-1 assume !(~E_1~0 == 1); 5793#L292-1 assume { :end_inline_reset_delta_events } true; 5847#L418-3 [2018-11-10 08:08:27,475 INFO L795 eck$LassoCheckResult]: Loop: 5847#L418-3 assume true; 6024#L418-1 assume !false; 6021#L419 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_~tmp~0;havoc eval_~tmp~0; 6020#L224 assume true; 6019#L200-1 assume !false; 6017#L201 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 6015#L178 assume !(~m_st~0 == 0); 6016#L182 assume !(~t1_st~0 == 0);exists_runnable_thread_~__retres1~2 := 0; 6014#L190 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 6012#L191 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 5988#L205 assume !(eval_~tmp~0 != 0); 5984#L239 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 5979#L153-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 5974#L249-3 assume ~M_E~0 == 0;~M_E~0 := 1; 5966#L249-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 5960#L254-3 assume !(~E_M~0 == 0); 5956#L259-3 assume ~E_1~0 == 0;~E_1~0 := 1; 5950#L264-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5938#L114-9 assume !(~m_pc~0 == 1); 5939#L114-11 is_master_triggered_~__retres1~0 := 0; 6018#L125-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5909#L126-3 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 5790#L309-9 assume !(activate_threads_~tmp~1 != 0); 5791#L309-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5738#L133-9 assume !(~t1_pc~0 == 1); 5739#L133-11 is_transmit1_triggered_~__retres1~1 := 0; 6084#L144-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6081#L145-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 6077#L317-9 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 6075#L317-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6072#L277-3 assume ~M_E~0 == 1;~M_E~0 := 2; 6068#L277-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 6064#L282-3 assume !(~E_M~0 == 1); 6062#L287-3 assume ~E_1~0 == 1;~E_1~0 := 2; 6059#L292-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 6056#L178-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 6050#L190-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 6047#L191-1 start_simulation_#t~ret7 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret7;havoc start_simulation_#t~ret7; 6043#L437 assume !(start_simulation_~tmp~3 == 0); 6039#L437-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret6, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 6037#L178-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 6034#L190-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 6032#L191-2 stop_simulation_#t~ret6 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret6;havoc stop_simulation_#t~ret6; 6030#L392 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 6028#L399 stop_simulation_#res := stop_simulation_~__retres2~0; 6026#L400 start_simulation_#t~ret8 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 6025#L450 assume !(start_simulation_~tmp___0~1 != 0); 5847#L418-3 [2018-11-10 08:08:27,475 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:08:27,475 INFO L82 PathProgramCache]: Analyzing trace with hash 396697797, now seen corresponding path program 4 times [2018-11-10 08:08:27,475 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:08:27,475 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:08:27,476 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:27,476 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:08:27,476 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:27,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 08:08:27,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 08:08:27,485 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:08:27,485 INFO L82 PathProgramCache]: Analyzing trace with hash -647806255, now seen corresponding path program 1 times [2018-11-10 08:08:27,485 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:08:27,485 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:08:27,486 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:27,486 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 08:08:27,486 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:27,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:08:27,509 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 08:08:27,510 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 08:08:27,510 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 08:08:27,510 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 08:08:27,510 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 08:08:27,510 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 08:08:27,511 INFO L87 Difference]: Start difference. First operand 438 states and 580 transitions. cyclomatic complexity: 146 Second operand 3 states. [2018-11-10 08:08:27,531 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 08:08:27,532 INFO L93 Difference]: Finished difference Result 510 states and 657 transitions. [2018-11-10 08:08:27,532 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 08:08:27,532 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 510 states and 657 transitions. [2018-11-10 08:08:27,534 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 451 [2018-11-10 08:08:27,535 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 510 states to 510 states and 657 transitions. [2018-11-10 08:08:27,535 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 510 [2018-11-10 08:08:27,536 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 510 [2018-11-10 08:08:27,536 INFO L73 IsDeterministic]: Start isDeterministic. Operand 510 states and 657 transitions. [2018-11-10 08:08:27,536 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 08:08:27,537 INFO L705 BuchiCegarLoop]: Abstraction has 510 states and 657 transitions. [2018-11-10 08:08:27,537 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 510 states and 657 transitions. [2018-11-10 08:08:27,541 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 510 to 510. [2018-11-10 08:08:27,541 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 510 states. [2018-11-10 08:08:27,542 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 510 states to 510 states and 657 transitions. [2018-11-10 08:08:27,542 INFO L728 BuchiCegarLoop]: Abstraction has 510 states and 657 transitions. [2018-11-10 08:08:27,542 INFO L608 BuchiCegarLoop]: Abstraction has 510 states and 657 transitions. [2018-11-10 08:08:27,542 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ [2018-11-10 08:08:27,542 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 510 states and 657 transitions. [2018-11-10 08:08:27,544 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 451 [2018-11-10 08:08:27,544 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 08:08:27,544 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 08:08:27,544 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:08:27,544 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:08:27,545 INFO L793 eck$LassoCheckResult]: Stem: 6811#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 6663#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 6664#L381 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret7, start_simulation_#t~ret8, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 6669#L153 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6670#L160 assume ~m_i~0 == 1;~m_st~0 := 0; 6785#L160-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 6786#L165-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6722#L249 assume !(~M_E~0 == 0); 6712#L249-2 assume !(~T1_E~0 == 0); 6713#L254-1 assume !(~E_M~0 == 0); 6743#L259-1 assume !(~E_1~0 == 0); 6808#L264-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6695#L114 assume !(~m_pc~0 == 1); 6681#L114-2 is_master_triggered_~__retres1~0 := 0; 6682#L125 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6696#L126 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 6787#L309 assume !(activate_threads_~tmp~1 != 0); 6756#L309-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6730#L133 assume !(~t1_pc~0 == 1); 6731#L133-2 is_transmit1_triggered_~__retres1~1 := 0; 6734#L144 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6735#L145 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 6793#L317 assume !(activate_threads_~tmp___0~0 != 0); 6794#L317-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6665#L277 assume !(~M_E~0 == 1); 6666#L277-2 assume !(~T1_E~0 == 1); 6723#L282-1 assume !(~E_M~0 == 1); 6724#L287-1 assume !(~E_1~0 == 1); 6744#L292-1 assume { :end_inline_reset_delta_events } true; 6809#L418-3 assume true; 7038#L418-1 assume !false; 7035#L419 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_~tmp~0;havoc eval_~tmp~0; 6949#L224 [2018-11-10 08:08:27,545 INFO L795 eck$LassoCheckResult]: Loop: 6949#L224 assume true; 7029#L200-1 assume !false; 7025#L201 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 7021#L178 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 7017#L190 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 7013#L191 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 7012#L205 assume eval_~tmp~0 != 0; 7010#L205-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 6753#L213 assume !(eval_~tmp_ndt_1~0 != 0); 6754#L210 assume !(~t1_st~0 == 0); 6949#L224 [2018-11-10 08:08:27,545 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:08:27,545 INFO L82 PathProgramCache]: Analyzing trace with hash -1725805832, now seen corresponding path program 1 times [2018-11-10 08:08:27,545 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:08:27,545 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:08:27,546 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:27,546 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:08:27,546 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:27,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 08:08:27,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 08:08:27,555 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:08:27,556 INFO L82 PathProgramCache]: Analyzing trace with hash 1423259343, now seen corresponding path program 1 times [2018-11-10 08:08:27,556 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:08:27,556 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:08:27,556 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:27,557 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:08:27,557 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:27,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 08:08:27,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 08:08:27,562 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:08:27,562 INFO L82 PathProgramCache]: Analyzing trace with hash 801863942, now seen corresponding path program 1 times [2018-11-10 08:08:27,562 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:08:27,563 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:08:27,563 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:27,563 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:08:27,563 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:27,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:08:27,592 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 08:08:27,593 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 08:08:27,593 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 08:08:27,642 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 08:08:27,643 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 08:08:27,643 INFO L87 Difference]: Start difference. First operand 510 states and 657 transitions. cyclomatic complexity: 153 Second operand 3 states. [2018-11-10 08:08:27,777 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 08:08:27,777 INFO L93 Difference]: Finished difference Result 829 states and 1043 transitions. [2018-11-10 08:08:27,778 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 08:08:27,778 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 829 states and 1043 transitions. [2018-11-10 08:08:27,780 INFO L131 ngComponentsAnalysis]: Automaton has 9 accepting balls. 640 [2018-11-10 08:08:27,782 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 829 states to 829 states and 1043 transitions. [2018-11-10 08:08:27,783 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 829 [2018-11-10 08:08:27,783 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 829 [2018-11-10 08:08:27,783 INFO L73 IsDeterministic]: Start isDeterministic. Operand 829 states and 1043 transitions. [2018-11-10 08:08:27,784 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 08:08:27,784 INFO L705 BuchiCegarLoop]: Abstraction has 829 states and 1043 transitions. [2018-11-10 08:08:27,785 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 829 states and 1043 transitions. [2018-11-10 08:08:27,790 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 829 to 809. [2018-11-10 08:08:27,790 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 809 states. [2018-11-10 08:08:27,792 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 809 states to 809 states and 1023 transitions. [2018-11-10 08:08:27,792 INFO L728 BuchiCegarLoop]: Abstraction has 809 states and 1023 transitions. [2018-11-10 08:08:27,792 INFO L608 BuchiCegarLoop]: Abstraction has 809 states and 1023 transitions. [2018-11-10 08:08:27,792 INFO L442 BuchiCegarLoop]: ======== Iteration 10============ [2018-11-10 08:08:27,792 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 809 states and 1023 transitions. [2018-11-10 08:08:27,794 INFO L131 ngComponentsAnalysis]: Automaton has 9 accepting balls. 620 [2018-11-10 08:08:27,794 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 08:08:27,794 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 08:08:27,794 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:08:27,795 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:08:27,795 INFO L793 eck$LassoCheckResult]: Stem: 8171#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 8010#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 8011#L381 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret7, start_simulation_#t~ret8, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 8016#L153 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8017#L160 assume ~m_i~0 == 1;~m_st~0 := 0; 8140#L160-2 assume !(~t1_i~0 == 1);~t1_st~0 := 2; 8141#L165-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8172#L249 assume !(~M_E~0 == 0); 8064#L249-2 assume !(~T1_E~0 == 0); 8065#L254-1 assume !(~E_M~0 == 0); 8164#L259-1 assume !(~E_1~0 == 0); 8165#L264-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8042#L114 assume !(~m_pc~0 == 1); 8043#L114-2 is_master_triggered_~__retres1~0 := 0; 8044#L125 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8045#L126 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 8189#L309 assume !(activate_threads_~tmp~1 != 0); 8109#L309-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8110#L133 assume !(~t1_pc~0 == 1); 8125#L133-2 is_transmit1_triggered_~__retres1~1 := 0; 8126#L144 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8197#L145 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 8198#L317 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 8150#L317-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8012#L277 assume !(~M_E~0 == 1); 8013#L277-2 assume !(~T1_E~0 == 1); 8076#L282-1 assume !(~E_M~0 == 1); 8077#L287-1 assume !(~E_1~0 == 1); 8166#L292-1 assume { :end_inline_reset_delta_events } true; 8167#L418-3 assume true; 8668#L418-1 assume !false; 8657#L419 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_~tmp~0;havoc eval_~tmp~0; 8653#L224 [2018-11-10 08:08:27,795 INFO L795 eck$LassoCheckResult]: Loop: 8653#L224 assume true; 8651#L200-1 assume !false; 8648#L201 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 8645#L178 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 8641#L190 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 8638#L191 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 8634#L205 assume eval_~tmp~0 != 0; 8631#L205-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 8106#L213 assume !(eval_~tmp_ndt_1~0 != 0); 8107#L210 assume ~t1_st~0 == 0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 8378#L227 assume !(eval_~tmp_ndt_2~0 != 0); 8653#L224 [2018-11-10 08:08:27,795 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:08:27,795 INFO L82 PathProgramCache]: Analyzing trace with hash 590449212, now seen corresponding path program 1 times [2018-11-10 08:08:27,795 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:08:27,795 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:08:27,796 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:27,796 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:08:27,796 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:27,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 08:08:27,805 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 08:08:27,806 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 08:08:27,806 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 08:08:27,806 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 08:08:27,806 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:08:27,806 INFO L82 PathProgramCache]: Analyzing trace with hash 1171364355, now seen corresponding path program 1 times [2018-11-10 08:08:27,807 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:08:27,807 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:08:27,808 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:27,808 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:08:27,808 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:27,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 08:08:27,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 08:08:27,850 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 08:08:27,850 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 08:08:27,851 INFO L87 Difference]: Start difference. First operand 809 states and 1023 transitions. cyclomatic complexity: 223 Second operand 3 states. [2018-11-10 08:08:27,854 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 08:08:27,854 INFO L93 Difference]: Finished difference Result 531 states and 674 transitions. [2018-11-10 08:08:27,855 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 08:08:27,855 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 531 states and 674 transitions. [2018-11-10 08:08:27,857 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 470 [2018-11-10 08:08:27,858 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 531 states to 531 states and 674 transitions. [2018-11-10 08:08:27,858 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 531 [2018-11-10 08:08:27,858 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 531 [2018-11-10 08:08:27,859 INFO L73 IsDeterministic]: Start isDeterministic. Operand 531 states and 674 transitions. [2018-11-10 08:08:27,859 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 08:08:27,859 INFO L705 BuchiCegarLoop]: Abstraction has 531 states and 674 transitions. [2018-11-10 08:08:27,860 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 531 states and 674 transitions. [2018-11-10 08:08:27,864 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 531 to 531. [2018-11-10 08:08:27,864 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 531 states. [2018-11-10 08:08:27,865 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 531 states to 531 states and 674 transitions. [2018-11-10 08:08:27,865 INFO L728 BuchiCegarLoop]: Abstraction has 531 states and 674 transitions. [2018-11-10 08:08:27,865 INFO L608 BuchiCegarLoop]: Abstraction has 531 states and 674 transitions. [2018-11-10 08:08:27,865 INFO L442 BuchiCegarLoop]: ======== Iteration 11============ [2018-11-10 08:08:27,865 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 531 states and 674 transitions. [2018-11-10 08:08:27,867 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 470 [2018-11-10 08:08:27,867 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 08:08:27,867 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 08:08:27,867 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:08:27,867 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 08:08:27,867 INFO L793 eck$LassoCheckResult]: Stem: 9502#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 9355#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 9356#L381 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret7, start_simulation_#t~ret8, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 9361#L153 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9362#L160 assume ~m_i~0 == 1;~m_st~0 := 0; 9480#L160-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 9481#L165-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9418#L249 assume !(~M_E~0 == 0); 9408#L249-2 assume !(~T1_E~0 == 0); 9409#L254-1 assume !(~E_M~0 == 0); 9438#L259-1 assume !(~E_1~0 == 0); 9498#L264-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9387#L114 assume !(~m_pc~0 == 1); 9373#L114-2 is_master_triggered_~__retres1~0 := 0; 9374#L125 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9390#L126 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 9482#L309 assume !(activate_threads_~tmp~1 != 0); 9452#L309-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9423#L133 assume !(~t1_pc~0 == 1); 9424#L133-2 is_transmit1_triggered_~__retres1~1 := 0; 9427#L144 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9428#L145 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 9486#L317 assume !(activate_threads_~tmp___0~0 != 0); 9487#L317-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9357#L277 assume !(~M_E~0 == 1); 9358#L277-2 assume !(~T1_E~0 == 1); 9419#L282-1 assume !(~E_M~0 == 1); 9420#L287-1 assume !(~E_1~0 == 1); 9439#L292-1 assume { :end_inline_reset_delta_events } true; 9499#L418-3 assume true; 9571#L418-1 assume !false; 9568#L419 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_~tmp~0;havoc eval_~tmp~0; 9567#L224 [2018-11-10 08:08:27,868 INFO L795 eck$LassoCheckResult]: Loop: 9567#L224 assume true; 9566#L200-1 assume !false; 9565#L201 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 9563#L178 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~2 := 1; 9562#L190 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 9561#L191 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 9560#L205 assume eval_~tmp~0 != 0; 9556#L205-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 9551#L213 assume !(eval_~tmp_ndt_1~0 != 0); 9552#L210 assume ~t1_st~0 == 0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 9569#L227 assume !(eval_~tmp_ndt_2~0 != 0); 9567#L224 [2018-11-10 08:08:27,868 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:08:27,868 INFO L82 PathProgramCache]: Analyzing trace with hash -1725805832, now seen corresponding path program 2 times [2018-11-10 08:08:27,868 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:08:27,868 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:08:27,869 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:27,869 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 08:08:27,869 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:27,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 08:08:27,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 08:08:27,879 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:08:27,879 INFO L82 PathProgramCache]: Analyzing trace with hash 1171364355, now seen corresponding path program 2 times [2018-11-10 08:08:27,879 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:08:27,879 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:08:27,880 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:27,880 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 08:08:27,880 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:27,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 08:08:27,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 08:08:27,885 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 08:08:27,885 INFO L82 PathProgramCache]: Analyzing trace with hash -912023892, now seen corresponding path program 1 times [2018-11-10 08:08:27,885 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 08:08:27,885 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 08:08:27,886 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:27,886 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 08:08:27,886 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 08:08:27,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 08:08:27,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 08:08:28,099 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 10.11 08:08:28 BoogieIcfgContainer [2018-11-10 08:08:28,099 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2018-11-10 08:08:28,100 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-10 08:08:28,101 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-10 08:08:28,101 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-10 08:08:28,102 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.11 08:08:26" (3/4) ... [2018-11-10 08:08:28,105 INFO L141 WitnessPrinter]: Generating witness for non-termination counterexample [2018-11-10 08:08:28,142 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_3ff55cc6-e111-44d6-94ef-9fb4125db8b6/bin-2019/uautomizer/witness.graphml [2018-11-10 08:08:28,142 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-10 08:08:28,143 INFO L168 Benchmark]: Toolchain (without parser) took 2521.41 ms. Allocated memory was 1.0 GB in the beginning and 1.3 GB in the end (delta: 230.7 MB). Free memory was 954.8 MB in the beginning and 1.2 GB in the end (delta: -264.7 MB). There was no memory consumed. Max. memory is 11.5 GB. [2018-11-10 08:08:28,144 INFO L168 Benchmark]: CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 980.1 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-10 08:08:28,144 INFO L168 Benchmark]: CACSL2BoogieTranslator took 171.44 ms. Allocated memory is still 1.0 GB. Free memory was 954.8 MB in the beginning and 941.4 MB in the end (delta: 13.4 MB). Peak memory consumption was 13.4 MB. Max. memory is 11.5 GB. [2018-11-10 08:08:28,145 INFO L168 Benchmark]: Boogie Procedure Inliner took 28.42 ms. Allocated memory is still 1.0 GB. Free memory was 941.4 MB in the beginning and 937.7 MB in the end (delta: 3.8 MB). Peak memory consumption was 3.8 MB. Max. memory is 11.5 GB. [2018-11-10 08:08:28,145 INFO L168 Benchmark]: Boogie Preprocessor took 70.20 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 162.0 MB). Free memory was 937.7 MB in the beginning and 1.2 GB in the end (delta: -228.4 MB). Peak memory consumption was 18.5 MB. Max. memory is 11.5 GB. [2018-11-10 08:08:28,145 INFO L168 Benchmark]: RCFGBuilder took 447.72 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 53.4 MB). Peak memory consumption was 53.4 MB. Max. memory is 11.5 GB. [2018-11-10 08:08:28,145 INFO L168 Benchmark]: BuchiAutomizer took 1758.00 ms. Allocated memory was 1.2 GB in the beginning and 1.3 GB in the end (delta: 68.7 MB). Free memory was 1.1 GB in the beginning and 1.2 GB in the end (delta: -109.6 MB). Peak memory consumption was 301.2 MB. Max. memory is 11.5 GB. [2018-11-10 08:08:28,146 INFO L168 Benchmark]: Witness Printer took 41.89 ms. Allocated memory is still 1.3 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-11-10 08:08:28,147 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 980.1 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 171.44 ms. Allocated memory is still 1.0 GB. Free memory was 954.8 MB in the beginning and 941.4 MB in the end (delta: 13.4 MB). Peak memory consumption was 13.4 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 28.42 ms. Allocated memory is still 1.0 GB. Free memory was 941.4 MB in the beginning and 937.7 MB in the end (delta: 3.8 MB). Peak memory consumption was 3.8 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 70.20 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 162.0 MB). Free memory was 937.7 MB in the beginning and 1.2 GB in the end (delta: -228.4 MB). Peak memory consumption was 18.5 MB. Max. memory is 11.5 GB. * RCFGBuilder took 447.72 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 53.4 MB). Peak memory consumption was 53.4 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 1758.00 ms. Allocated memory was 1.2 GB in the beginning and 1.3 GB in the end (delta: 68.7 MB). Free memory was 1.1 GB in the beginning and 1.2 GB in the end (delta: -109.6 MB). Peak memory consumption was 301.2 MB. Max. memory is 11.5 GB. * Witness Printer took 41.89 ms. Allocated memory is still 1.3 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 10 terminating modules (10 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.10 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 531 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 1.7s and 11 iterations. TraceHistogramMax:1. Analysis of lassos took 0.9s. Construction of modules took 0.3s. Büchi inclusion checks took 0.1s. Highest rank in rank-based complementation 0. Minimization of det autom 10. Minimization of nondet autom 0. Automata minimization 0.0s AutomataMinimizationTime, 10 MinimizatonAttempts, 428 StatesRemovedByMinimization, 6 NontrivialMinimizations. Non-live state removal took 0.0s Buchi closure took 0.0s. Biggest automaton had 809 states and ocurred in iteration 9. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 2132 SDtfs, 2106 SDslu, 1720 SDs, 0 SdLazy, 180 SolverSat, 75 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.3s Time LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc1 concLT0 SILN1 SILU0 SILI4 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 200]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {\result=0, token=0, __retres1=0, tmp=1, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3ce41df7=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7f55cfdc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4ef502d5=0, kernel_st=1, __retres1=0, tmp___0=0, t1_pc=0, __retres1=1, T1_E=2, \result=0, E_1=2, tmp_ndt_1=0, M_E=2, tmp_ndt_2=0, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6d6b6794=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3c480a4=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@e0a6ef1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6688319f=0, t1_st=0, local=0, m_st=0, E_M=2, tmp___0=0, tmp=0, __retres1=0, t1_i=1, m_pc=0, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 200]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int m_st ; [L17] int t1_st ; [L18] int m_i ; [L19] int t1_i ; [L20] int M_E = 2; [L21] int T1_E = 2; [L22] int E_M = 2; [L23] int E_1 = 2; [L27] int token ; [L29] int local ; [L463] int __retres1 ; [L467] CALL init_model() [L378] m_i = 1 [L379] RET t1_i = 1 [L467] init_model() [L468] CALL start_simulation() [L404] int kernel_st ; [L405] int tmp ; [L406] int tmp___0 ; [L410] kernel_st = 0 [L411] FCALL update_channels() [L412] CALL init_threads() [L160] COND TRUE m_i == 1 [L161] m_st = 0 [L165] COND TRUE t1_i == 1 [L166] RET t1_st = 0 [L412] init_threads() [L413] CALL fire_delta_events() [L249] COND FALSE !(M_E == 0) [L254] COND FALSE !(T1_E == 0) [L259] COND FALSE !(E_M == 0) [L264] COND FALSE, RET !(E_1 == 0) [L413] fire_delta_events() [L414] CALL activate_threads() [L302] int tmp ; [L303] int tmp___0 ; [L307] CALL, EXPR is_master_triggered() [L111] int __retres1 ; [L114] COND FALSE !(m_pc == 1) [L124] __retres1 = 0 [L126] RET return (__retres1); [L307] EXPR is_master_triggered() [L307] tmp = is_master_triggered() [L309] COND FALSE !(\read(tmp)) [L315] CALL, EXPR is_transmit1_triggered() [L130] int __retres1 ; [L133] COND FALSE !(t1_pc == 1) [L143] __retres1 = 0 [L145] RET return (__retres1); [L315] EXPR is_transmit1_triggered() [L315] tmp___0 = is_transmit1_triggered() [L317] COND FALSE, RET !(\read(tmp___0)) [L414] activate_threads() [L415] CALL reset_delta_events() [L277] COND FALSE !(M_E == 1) [L282] COND FALSE !(T1_E == 1) [L287] COND FALSE !(E_M == 1) [L292] COND FALSE, RET !(E_1 == 1) [L415] reset_delta_events() [L418] COND TRUE 1 [L421] kernel_st = 1 [L422] CALL eval() [L196] int tmp ; Loop: [L200] COND TRUE 1 [L203] CALL, EXPR exists_runnable_thread() [L175] int __retres1 ; [L178] COND TRUE m_st == 0 [L179] __retres1 = 1 [L191] RET return (__retres1); [L203] EXPR exists_runnable_thread() [L203] tmp = exists_runnable_thread() [L205] COND TRUE \read(tmp) [L210] COND TRUE m_st == 0 [L211] int tmp_ndt_1; [L212] tmp_ndt_1 = __VERIFIER_nondet_int() [L213] COND FALSE !(\read(tmp_ndt_1)) [L224] COND TRUE t1_st == 0 [L225] int tmp_ndt_2; [L226] tmp_ndt_2 = __VERIFIER_nondet_int() [L227] COND FALSE !(\read(tmp_ndt_2)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...