./Ultimate.py --spec ../../sv-benchmarks/c/Termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.02_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 1dbac8bc Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_79c1851b-7519-4818-bc22-2690e43b7ac5/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_79c1851b-7519-4818-bc22-2690e43b7ac5/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_79c1851b-7519-4818-bc22-2690e43b7ac5/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_79c1851b-7519-4818-bc22-2690e43b7ac5/bin-2019/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.02_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_79c1851b-7519-4818-bc22-2690e43b7ac5/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_79c1851b-7519-4818-bc22-2690e43b7ac5/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 216b1eba72c80bc0eec8bb9ab0298bf8baf472d8 .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.23-1dbac8b [2018-11-10 01:03:45,634 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-10 01:03:45,636 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-10 01:03:45,644 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-10 01:03:45,645 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-10 01:03:45,645 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-10 01:03:45,646 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-10 01:03:45,647 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-10 01:03:45,648 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-10 01:03:45,649 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-10 01:03:45,650 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-10 01:03:45,650 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-10 01:03:45,650 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-10 01:03:45,651 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-10 01:03:45,652 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-10 01:03:45,652 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-10 01:03:45,653 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-10 01:03:45,654 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-10 01:03:45,656 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-10 01:03:45,657 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-10 01:03:45,658 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-10 01:03:45,659 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-10 01:03:45,661 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-10 01:03:45,661 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-10 01:03:45,661 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-10 01:03:45,662 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-10 01:03:45,663 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-10 01:03:45,663 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-10 01:03:45,664 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-10 01:03:45,665 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-10 01:03:45,665 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-10 01:03:45,666 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-10 01:03:45,666 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-10 01:03:45,666 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-10 01:03:45,667 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-10 01:03:45,668 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-10 01:03:45,668 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_79c1851b-7519-4818-bc22-2690e43b7ac5/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2018-11-10 01:03:45,682 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-10 01:03:45,682 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-10 01:03:45,683 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-10 01:03:45,683 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-10 01:03:45,684 INFO L133 SettingsManager]: * Use SBE=true [2018-11-10 01:03:45,684 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2018-11-10 01:03:45,684 INFO L133 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2018-11-10 01:03:45,684 INFO L133 SettingsManager]: * Use old map elimination=false [2018-11-10 01:03:45,684 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false [2018-11-10 01:03:45,684 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true [2018-11-10 01:03:45,685 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2018-11-10 01:03:45,685 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-10 01:03:45,685 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-10 01:03:45,685 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-10 01:03:45,685 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-10 01:03:45,685 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-10 01:03:45,686 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-10 01:03:45,686 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2018-11-10 01:03:45,686 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2018-11-10 01:03:45,686 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2018-11-10 01:03:45,686 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-10 01:03:45,686 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-10 01:03:45,687 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false [2018-11-10 01:03:45,687 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2018-11-10 01:03:45,687 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-10 01:03:45,687 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-10 01:03:45,687 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2018-11-10 01:03:45,687 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-10 01:03:45,688 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-10 01:03:45,688 INFO L133 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2018-11-10 01:03:45,689 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-11-10 01:03:45,689 INFO L133 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_79c1851b-7519-4818-bc22-2690e43b7ac5/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 216b1eba72c80bc0eec8bb9ab0298bf8baf472d8 [2018-11-10 01:03:45,719 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-10 01:03:45,730 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-10 01:03:45,732 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-10 01:03:45,733 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-10 01:03:45,734 INFO L276 PluginConnector]: CDTParser initialized [2018-11-10 01:03:45,734 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_79c1851b-7519-4818-bc22-2690e43b7ac5/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/token_ring.02_false-unreach-call_false-termination.cil.c [2018-11-10 01:03:45,782 INFO L218 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_79c1851b-7519-4818-bc22-2690e43b7ac5/bin-2019/uautomizer/data/8195d8aa8/2da65753c89041f4a6d4405b93049033/FLAGde645e9c9 [2018-11-10 01:03:46,163 INFO L298 CDTParser]: Found 1 translation units. [2018-11-10 01:03:46,163 INFO L158 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_79c1851b-7519-4818-bc22-2690e43b7ac5/sv-benchmarks/c/systemc/token_ring.02_false-unreach-call_false-termination.cil.c [2018-11-10 01:03:46,173 INFO L346 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_79c1851b-7519-4818-bc22-2690e43b7ac5/bin-2019/uautomizer/data/8195d8aa8/2da65753c89041f4a6d4405b93049033/FLAGde645e9c9 [2018-11-10 01:03:46,185 INFO L354 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_79c1851b-7519-4818-bc22-2690e43b7ac5/bin-2019/uautomizer/data/8195d8aa8/2da65753c89041f4a6d4405b93049033 [2018-11-10 01:03:46,188 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-10 01:03:46,189 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-10 01:03:46,190 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-10 01:03:46,190 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-10 01:03:46,193 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-10 01:03:46,194 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.11 01:03:46" (1/1) ... [2018-11-10 01:03:46,196 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7ce791db and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 01:03:46, skipping insertion in model container [2018-11-10 01:03:46,196 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.11 01:03:46" (1/1) ... [2018-11-10 01:03:46,205 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-10 01:03:46,236 INFO L174 MainTranslator]: Built tables and reachable declarations [2018-11-10 01:03:46,412 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-11-10 01:03:46,416 INFO L189 MainTranslator]: Completed pre-run [2018-11-10 01:03:46,446 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-11-10 01:03:46,459 INFO L193 MainTranslator]: Completed translation [2018-11-10 01:03:46,460 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 01:03:46 WrapperNode [2018-11-10 01:03:46,460 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-10 01:03:46,461 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-10 01:03:46,461 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-10 01:03:46,461 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-10 01:03:46,467 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 01:03:46" (1/1) ... [2018-11-10 01:03:46,474 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 01:03:46" (1/1) ... [2018-11-10 01:03:46,502 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-10 01:03:46,502 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-10 01:03:46,502 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-10 01:03:46,502 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-10 01:03:46,560 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 01:03:46" (1/1) ... [2018-11-10 01:03:46,561 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 01:03:46" (1/1) ... [2018-11-10 01:03:46,563 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 01:03:46" (1/1) ... [2018-11-10 01:03:46,563 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 01:03:46" (1/1) ... [2018-11-10 01:03:46,569 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 01:03:46" (1/1) ... [2018-11-10 01:03:46,581 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 01:03:46" (1/1) ... [2018-11-10 01:03:46,584 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 01:03:46" (1/1) ... [2018-11-10 01:03:46,589 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-10 01:03:46,589 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-10 01:03:46,589 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-10 01:03:46,590 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-10 01:03:46,590 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 01:03:46" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_79c1851b-7519-4818-bc22-2690e43b7ac5/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-10 01:03:46,638 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-10 01:03:46,638 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-10 01:03:47,336 INFO L341 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-10 01:03:47,336 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.11 01:03:47 BoogieIcfgContainer [2018-11-10 01:03:47,336 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-10 01:03:47,337 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2018-11-10 01:03:47,337 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2018-11-10 01:03:47,339 INFO L276 PluginConnector]: BuchiAutomizer initialized [2018-11-10 01:03:47,340 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-10 01:03:47,340 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 10.11 01:03:46" (1/3) ... [2018-11-10 01:03:47,341 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5b25d145 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 10.11 01:03:47, skipping insertion in model container [2018-11-10 01:03:47,341 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-10 01:03:47,341 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 01:03:46" (2/3) ... [2018-11-10 01:03:47,342 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5b25d145 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 10.11 01:03:47, skipping insertion in model container [2018-11-10 01:03:47,342 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-10 01:03:47,342 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.11 01:03:47" (3/3) ... [2018-11-10 01:03:47,343 INFO L375 chiAutomizerObserver]: Analyzing ICFG token_ring.02_false-unreach-call_false-termination.cil.c [2018-11-10 01:03:47,389 INFO L135 ementStrategyFactory]: Using default assertion order modulation [2018-11-10 01:03:47,390 INFO L374 BuchiCegarLoop]: Interprodecural is true [2018-11-10 01:03:47,390 INFO L375 BuchiCegarLoop]: Hoare is false [2018-11-10 01:03:47,391 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2018-11-10 01:03:47,391 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-10 01:03:47,391 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-10 01:03:47,391 INFO L379 BuchiCegarLoop]: Difference is false [2018-11-10 01:03:47,391 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-10 01:03:47,391 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2018-11-10 01:03:47,410 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 243 states. [2018-11-10 01:03:47,444 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 196 [2018-11-10 01:03:47,444 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 01:03:47,444 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 01:03:47,454 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 01:03:47,454 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 01:03:47,454 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ [2018-11-10 01:03:47,454 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 243 states. [2018-11-10 01:03:47,463 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 196 [2018-11-10 01:03:47,463 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 01:03:47,463 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 01:03:47,465 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 01:03:47,465 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 01:03:47,472 INFO L793 eck$LassoCheckResult]: Stem: 105#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 8#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 167#L518true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 90#L226true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 245#L233true assume !(~m_i~0 == 1);~m_st~0 := 2; 243#L233-2true assume ~t1_i~0 == 1;~t1_st~0 := 0; 141#L238-1true assume !(~t2_i~0 == 1);~t2_st~0 := 2; 151#L243-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 127#L346true assume !(~M_E~0 == 0); 122#L346-2true assume !(~T1_E~0 == 0); 10#L351-1true assume !(~T2_E~0 == 0); 36#L356-1true assume ~E_M~0 == 0;~E_M~0 := 1; 60#L361-1true assume !(~E_1~0 == 0); 205#L366-1true assume !(~E_2~0 == 0); 234#L371-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 183#L168true assume ~m_pc~0 == 1; 31#L169true assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 186#L179true is_master_triggered_#res := is_master_triggered_~__retres1~0; 32#L180true activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 184#L427true assume !(activate_threads_~tmp~1 != 0); 56#L427-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 97#L187true assume !(~t1_pc~0 == 1); 116#L187-2true is_transmit1_triggered_~__retres1~1 := 0; 98#L198true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 150#L199true activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 87#L435true assume !(activate_threads_~tmp___0~0 != 0); 91#L435-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 240#L206true assume ~t2_pc~0 == 1; 42#L207true assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 241#L217true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 44#L218true activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 222#L443true assume !(activate_threads_~tmp___1~0 != 0); 201#L443-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29#L384true assume !(~M_E~0 == 1); 11#L384-2true assume ~T1_E~0 == 1;~T1_E~0 := 2; 35#L389-1true assume !(~T2_E~0 == 1); 57#L394-1true assume !(~E_M~0 == 1); 202#L399-1true assume !(~E_1~0 == 1); 229#L404-1true assume !(~E_2~0 == 1); 128#L409-1true assume { :end_inline_reset_delta_events } true; 126#L555-3true [2018-11-10 01:03:47,473 INFO L795 eck$LassoCheckResult]: Loop: 126#L555-3true assume true; 7#L555-1true assume !false; 100#L556true start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 129#L321true assume !true; 93#L336true assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 88#L226-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 123#L346-3true assume ~M_E~0 == 0;~M_E~0 := 1; 124#L346-5true assume ~T1_E~0 == 0;~T1_E~0 := 1; 16#L351-3true assume ~T2_E~0 == 0;~T2_E~0 := 1; 38#L356-3true assume ~E_M~0 == 0;~E_M~0 := 1; 69#L361-3true assume ~E_1~0 == 0;~E_1~0 := 1; 209#L366-3true assume ~E_2~0 == 0;~E_2~0 := 1; 239#L371-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 51#L168-12true assume ~m_pc~0 == 1; 19#L169-4true assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 170#L179-4true is_master_triggered_#res := is_master_triggered_~__retres1~0; 21#L180-4true activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 55#L427-12true assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 39#L427-14true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 77#L187-12true assume ~t1_pc~0 == 1; 156#L188-4true assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 110#L198-4true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 157#L199-4true activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 165#L435-12true assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 168#L435-14true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 221#L206-12true assume !(~t2_pc~0 == 1); 219#L206-14true is_transmit2_triggered_~__retres1~2 := 0; 228#L217-4true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 63#L218-4true activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 200#L443-12true assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 175#L443-14true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14#L384-3true assume ~M_E~0 == 1;~M_E~0 := 2; 17#L384-5true assume ~T1_E~0 == 1;~T1_E~0 := 2; 37#L389-3true assume ~T2_E~0 == 1;~T2_E~0 := 2; 66#L394-3true assume ~E_M~0 == 1;~E_M~0 := 2; 207#L399-3true assume ~E_1~0 == 1;~E_1~0 := 2; 237#L404-3true assume !(~E_2~0 == 1); 131#L409-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 216#L256-1true assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 47#L273-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 4#L274-1true start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 135#L574true assume !(start_simulation_~tmp~3 == 0); 137#L574-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 187#L256-2true assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 43#L273-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 3#L274-2true stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 166#L529true assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 242#L536true stop_simulation_#res := stop_simulation_~__retres2~0; 171#L537true start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 53#L587true assume !(start_simulation_~tmp___0~1 != 0); 126#L555-3true [2018-11-10 01:03:47,478 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 01:03:47,478 INFO L82 PathProgramCache]: Analyzing trace with hash 332551043, now seen corresponding path program 1 times [2018-11-10 01:03:47,480 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 01:03:47,480 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 01:03:47,529 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:47,529 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 01:03:47,529 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:47,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 01:03:47,606 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 01:03:47,609 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 01:03:47,610 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 01:03:47,615 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 01:03:47,615 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 01:03:47,615 INFO L82 PathProgramCache]: Analyzing trace with hash 556081131, now seen corresponding path program 1 times [2018-11-10 01:03:47,616 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 01:03:47,616 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 01:03:47,617 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:47,617 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 01:03:47,617 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:47,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 01:03:47,631 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 01:03:47,631 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 01:03:47,631 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 01:03:47,633 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 01:03:47,651 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 01:03:47,652 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 01:03:47,654 INFO L87 Difference]: Start difference. First operand 243 states. Second operand 3 states. [2018-11-10 01:03:47,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 01:03:47,693 INFO L93 Difference]: Finished difference Result 241 states and 355 transitions. [2018-11-10 01:03:47,693 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 01:03:47,696 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 241 states and 355 transitions. [2018-11-10 01:03:47,700 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 192 [2018-11-10 01:03:47,707 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 241 states to 235 states and 349 transitions. [2018-11-10 01:03:47,708 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 235 [2018-11-10 01:03:47,710 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 235 [2018-11-10 01:03:47,710 INFO L73 IsDeterministic]: Start isDeterministic. Operand 235 states and 349 transitions. [2018-11-10 01:03:47,712 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 01:03:47,712 INFO L705 BuchiCegarLoop]: Abstraction has 235 states and 349 transitions. [2018-11-10 01:03:47,734 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 235 states and 349 transitions. [2018-11-10 01:03:47,753 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 235 to 235. [2018-11-10 01:03:47,754 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 235 states. [2018-11-10 01:03:47,755 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 235 states to 235 states and 349 transitions. [2018-11-10 01:03:47,757 INFO L728 BuchiCegarLoop]: Abstraction has 235 states and 349 transitions. [2018-11-10 01:03:47,757 INFO L608 BuchiCegarLoop]: Abstraction has 235 states and 349 transitions. [2018-11-10 01:03:47,757 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ [2018-11-10 01:03:47,757 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 235 states and 349 transitions. [2018-11-10 01:03:47,760 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 192 [2018-11-10 01:03:47,760 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 01:03:47,760 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 01:03:47,762 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 01:03:47,762 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 01:03:47,763 INFO L793 eck$LassoCheckResult]: Stem: 661#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 504#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 505#L518 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 643#L226 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 644#L233 assume ~m_i~0 == 1;~m_st~0 := 0; 727#L233-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 691#L238-1 assume !(~t2_i~0 == 1);~t2_st~0 := 2; 692#L243-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 677#L346 assume !(~M_E~0 == 0); 675#L346-2 assume !(~T1_E~0 == 0); 506#L351-1 assume !(~T2_E~0 == 0); 507#L356-1 assume ~E_M~0 == 0;~E_M~0 := 1; 560#L361-1 assume !(~E_1~0 == 0); 592#L366-1 assume !(~E_2~0 == 0); 721#L371-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 712#L168 assume ~m_pc~0 == 1; 551#L169 assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 552#L179 is_master_triggered_#res := is_master_triggered_~__retres1~0; 554#L180 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 555#L427 assume !(activate_threads_~tmp~1 != 0); 584#L427-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 585#L187 assume !(~t1_pc~0 == 1); 653#L187-2 is_transmit1_triggered_~__retres1~1 := 0; 655#L198 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 656#L199 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 638#L435 assume !(activate_threads_~tmp___0~0 != 0); 639#L435-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 645#L206 assume ~t2_pc~0 == 1; 567#L207 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 568#L217 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 571#L218 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 572#L443 assume !(activate_threads_~tmp___1~0 != 0); 718#L443-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 548#L384 assume !(~M_E~0 == 1); 508#L384-2 assume ~T1_E~0 == 1;~T1_E~0 := 2; 509#L389-1 assume !(~T2_E~0 == 1); 559#L394-1 assume !(~E_M~0 == 1); 586#L399-1 assume !(~E_1~0 == 1); 719#L404-1 assume !(~E_2~0 == 1); 678#L409-1 assume { :end_inline_reset_delta_events } true; 582#L555-3 [2018-11-10 01:03:47,763 INFO L795 eck$LassoCheckResult]: Loop: 582#L555-3 assume true; 502#L555-1 assume !false; 503#L556 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 511#L321 assume true; 679#L283-1 assume !false; 578#L284 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 579#L256 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 576#L273 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 497#L274 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 498#L288 assume !(eval_~tmp~0 != 0); 647#L336 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 640#L226-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 641#L346-3 assume ~M_E~0 == 0;~M_E~0 := 1; 676#L346-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 519#L351-3 assume ~T2_E~0 == 0;~T2_E~0 := 1; 520#L356-3 assume ~E_M~0 == 0;~E_M~0 := 1; 562#L361-3 assume ~E_1~0 == 0;~E_1~0 := 1; 607#L366-3 assume ~E_2~0 == 0;~E_2~0 := 1; 723#L371-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 580#L168-12 assume !(~m_pc~0 == 1); 528#L168-14 is_master_triggered_~__retres1~0 := 0; 527#L179-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 529#L180-4 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 530#L427-12 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 563#L427-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 564#L187-12 assume ~t1_pc~0 == 1; 620#L188-4 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 646#L198-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 664#L199-4 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 698#L435-12 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 703#L435-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 705#L206-12 assume ~t2_pc~0 == 1; 594#L207-4 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 595#L217-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 597#L218-4 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 598#L443-12 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 708#L443-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 516#L384-3 assume ~M_E~0 == 1;~M_E~0 := 2; 517#L384-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 521#L389-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 561#L394-3 assume ~E_M~0 == 1;~E_M~0 := 2; 604#L399-3 assume ~E_1~0 == 1;~E_1~0 := 2; 722#L404-3 assume !(~E_2~0 == 1); 682#L409-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 683#L256-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 575#L273-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 495#L274-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 496#L574 assume !(start_simulation_~tmp~3 == 0); 635#L574-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 687#L256-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 570#L273-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 493#L274-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 494#L529 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 704#L536 stop_simulation_#res := stop_simulation_~__retres2~0; 706#L537 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 581#L587 assume !(start_simulation_~tmp___0~1 != 0); 582#L555-3 [2018-11-10 01:03:47,763 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 01:03:47,764 INFO L82 PathProgramCache]: Analyzing trace with hash 726917829, now seen corresponding path program 1 times [2018-11-10 01:03:47,764 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 01:03:47,764 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 01:03:47,765 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:47,765 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 01:03:47,768 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:47,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 01:03:47,812 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 01:03:47,813 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 01:03:47,813 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 01:03:47,814 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 01:03:47,814 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 01:03:47,814 INFO L82 PathProgramCache]: Analyzing trace with hash 1475294048, now seen corresponding path program 1 times [2018-11-10 01:03:47,814 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 01:03:47,814 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 01:03:47,815 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:47,816 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 01:03:47,816 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:47,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 01:03:47,905 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 01:03:47,905 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 01:03:47,906 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 01:03:47,907 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 01:03:47,907 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 01:03:47,907 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 01:03:47,909 INFO L87 Difference]: Start difference. First operand 235 states and 349 transitions. cyclomatic complexity: 115 Second operand 3 states. [2018-11-10 01:03:47,944 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 01:03:47,944 INFO L93 Difference]: Finished difference Result 235 states and 348 transitions. [2018-11-10 01:03:47,945 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 01:03:47,946 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 235 states and 348 transitions. [2018-11-10 01:03:47,949 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 192 [2018-11-10 01:03:47,951 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 235 states to 235 states and 348 transitions. [2018-11-10 01:03:47,951 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 235 [2018-11-10 01:03:47,952 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 235 [2018-11-10 01:03:47,956 INFO L73 IsDeterministic]: Start isDeterministic. Operand 235 states and 348 transitions. [2018-11-10 01:03:47,957 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 01:03:47,958 INFO L705 BuchiCegarLoop]: Abstraction has 235 states and 348 transitions. [2018-11-10 01:03:47,958 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 235 states and 348 transitions. [2018-11-10 01:03:47,965 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 235 to 235. [2018-11-10 01:03:47,966 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 235 states. [2018-11-10 01:03:47,967 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 235 states to 235 states and 348 transitions. [2018-11-10 01:03:47,967 INFO L728 BuchiCegarLoop]: Abstraction has 235 states and 348 transitions. [2018-11-10 01:03:47,967 INFO L608 BuchiCegarLoop]: Abstraction has 235 states and 348 transitions. [2018-11-10 01:03:47,967 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ [2018-11-10 01:03:47,967 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 235 states and 348 transitions. [2018-11-10 01:03:47,969 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 192 [2018-11-10 01:03:47,970 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 01:03:47,970 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 01:03:47,971 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 01:03:47,971 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 01:03:47,972 INFO L793 eck$LassoCheckResult]: Stem: 1138#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 981#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 982#L518 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 1120#L226 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1121#L233 assume ~m_i~0 == 1;~m_st~0 := 0; 1204#L233-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 1168#L238-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 1169#L243-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1154#L346 assume !(~M_E~0 == 0); 1152#L346-2 assume !(~T1_E~0 == 0); 983#L351-1 assume !(~T2_E~0 == 0); 984#L356-1 assume ~E_M~0 == 0;~E_M~0 := 1; 1037#L361-1 assume !(~E_1~0 == 0); 1069#L366-1 assume !(~E_2~0 == 0); 1198#L371-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1189#L168 assume ~m_pc~0 == 1; 1028#L169 assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 1029#L179 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1031#L180 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1032#L427 assume !(activate_threads_~tmp~1 != 0); 1061#L427-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1062#L187 assume !(~t1_pc~0 == 1); 1130#L187-2 is_transmit1_triggered_~__retres1~1 := 0; 1132#L198 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1133#L199 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1115#L435 assume !(activate_threads_~tmp___0~0 != 0); 1116#L435-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1122#L206 assume ~t2_pc~0 == 1; 1044#L207 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 1045#L217 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1048#L218 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1049#L443 assume !(activate_threads_~tmp___1~0 != 0); 1195#L443-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1025#L384 assume !(~M_E~0 == 1); 985#L384-2 assume ~T1_E~0 == 1;~T1_E~0 := 2; 986#L389-1 assume !(~T2_E~0 == 1); 1036#L394-1 assume !(~E_M~0 == 1); 1063#L399-1 assume !(~E_1~0 == 1); 1196#L404-1 assume !(~E_2~0 == 1); 1155#L409-1 assume { :end_inline_reset_delta_events } true; 1059#L555-3 [2018-11-10 01:03:47,972 INFO L795 eck$LassoCheckResult]: Loop: 1059#L555-3 assume true; 979#L555-1 assume !false; 980#L556 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 988#L321 assume true; 1156#L283-1 assume !false; 1055#L284 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1056#L256 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 1053#L273 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 974#L274 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 975#L288 assume !(eval_~tmp~0 != 0); 1124#L336 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 1117#L226-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 1118#L346-3 assume ~M_E~0 == 0;~M_E~0 := 1; 1153#L346-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 996#L351-3 assume ~T2_E~0 == 0;~T2_E~0 := 1; 997#L356-3 assume ~E_M~0 == 0;~E_M~0 := 1; 1039#L361-3 assume ~E_1~0 == 0;~E_1~0 := 1; 1084#L366-3 assume ~E_2~0 == 0;~E_2~0 := 1; 1200#L371-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1057#L168-12 assume ~m_pc~0 == 1; 1003#L169-4 assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 1004#L179-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1006#L180-4 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1007#L427-12 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 1040#L427-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1041#L187-12 assume ~t1_pc~0 == 1; 1097#L188-4 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 1123#L198-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1141#L199-4 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1175#L435-12 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 1180#L435-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1182#L206-12 assume !(~t2_pc~0 == 1); 1073#L206-14 is_transmit2_triggered_~__retres1~2 := 0; 1072#L217-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1074#L218-4 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1075#L443-12 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 1185#L443-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 993#L384-3 assume ~M_E~0 == 1;~M_E~0 := 2; 994#L384-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 998#L389-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 1038#L394-3 assume ~E_M~0 == 1;~E_M~0 := 2; 1081#L399-3 assume ~E_1~0 == 1;~E_1~0 := 2; 1199#L404-3 assume !(~E_2~0 == 1); 1159#L409-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1160#L256-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 1052#L273-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 972#L274-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 973#L574 assume !(start_simulation_~tmp~3 == 0); 1112#L574-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1164#L256-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 1047#L273-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 970#L274-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 971#L529 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 1181#L536 stop_simulation_#res := stop_simulation_~__retres2~0; 1183#L537 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 1058#L587 assume !(start_simulation_~tmp___0~1 != 0); 1059#L555-3 [2018-11-10 01:03:47,972 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 01:03:47,972 INFO L82 PathProgramCache]: Analyzing trace with hash -1324066169, now seen corresponding path program 1 times [2018-11-10 01:03:47,972 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 01:03:47,973 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 01:03:47,973 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:47,974 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 01:03:47,974 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:47,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 01:03:48,009 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 01:03:48,009 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 01:03:48,010 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 01:03:48,010 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 01:03:48,010 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 01:03:48,010 INFO L82 PathProgramCache]: Analyzing trace with hash -1707569952, now seen corresponding path program 1 times [2018-11-10 01:03:48,010 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 01:03:48,011 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 01:03:48,011 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:48,012 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 01:03:48,012 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:48,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 01:03:48,057 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 01:03:48,058 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 01:03:48,058 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 01:03:48,058 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 01:03:48,059 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 01:03:48,059 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 01:03:48,059 INFO L87 Difference]: Start difference. First operand 235 states and 348 transitions. cyclomatic complexity: 114 Second operand 3 states. [2018-11-10 01:03:48,112 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 01:03:48,113 INFO L93 Difference]: Finished difference Result 235 states and 338 transitions. [2018-11-10 01:03:48,113 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 01:03:48,113 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 235 states and 338 transitions. [2018-11-10 01:03:48,115 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 192 [2018-11-10 01:03:48,116 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 235 states to 235 states and 338 transitions. [2018-11-10 01:03:48,116 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 235 [2018-11-10 01:03:48,117 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 235 [2018-11-10 01:03:48,117 INFO L73 IsDeterministic]: Start isDeterministic. Operand 235 states and 338 transitions. [2018-11-10 01:03:48,118 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 01:03:48,118 INFO L705 BuchiCegarLoop]: Abstraction has 235 states and 338 transitions. [2018-11-10 01:03:48,118 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 235 states and 338 transitions. [2018-11-10 01:03:48,129 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 235 to 235. [2018-11-10 01:03:48,129 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 235 states. [2018-11-10 01:03:48,130 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 235 states to 235 states and 338 transitions. [2018-11-10 01:03:48,130 INFO L728 BuchiCegarLoop]: Abstraction has 235 states and 338 transitions. [2018-11-10 01:03:48,131 INFO L608 BuchiCegarLoop]: Abstraction has 235 states and 338 transitions. [2018-11-10 01:03:48,131 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ [2018-11-10 01:03:48,131 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 235 states and 338 transitions. [2018-11-10 01:03:48,134 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 192 [2018-11-10 01:03:48,134 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 01:03:48,134 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 01:03:48,136 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 01:03:48,136 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 01:03:48,136 INFO L793 eck$LassoCheckResult]: Stem: 1612#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 1458#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1459#L518 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 1594#L226 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1595#L233 assume ~m_i~0 == 1;~m_st~0 := 0; 1681#L233-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 1642#L238-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 1643#L243-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1628#L346 assume !(~M_E~0 == 0); 1626#L346-2 assume !(~T1_E~0 == 0); 1460#L351-1 assume !(~T2_E~0 == 0); 1461#L356-1 assume !(~E_M~0 == 0); 1509#L361-1 assume !(~E_1~0 == 0); 1542#L366-1 assume !(~E_2~0 == 0); 1675#L371-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1666#L168 assume !(~m_pc~0 == 1); 1503#L168-2 is_master_triggered_~__retres1~0 := 0; 1659#L179 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1504#L180 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1505#L427 assume !(activate_threads_~tmp~1 != 0); 1534#L427-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1535#L187 assume !(~t1_pc~0 == 1); 1604#L187-2 is_transmit1_triggered_~__retres1~1 := 0; 1606#L198 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1607#L199 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1589#L435 assume !(activate_threads_~tmp___0~0 != 0); 1590#L435-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1596#L206 assume ~t2_pc~0 == 1; 1516#L207 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 1517#L217 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1520#L218 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1521#L443 assume !(activate_threads_~tmp___1~0 != 0); 1672#L443-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1499#L384 assume !(~M_E~0 == 1); 1462#L384-2 assume ~T1_E~0 == 1;~T1_E~0 := 2; 1463#L389-1 assume !(~T2_E~0 == 1); 1508#L394-1 assume !(~E_M~0 == 1); 1536#L399-1 assume !(~E_1~0 == 1); 1673#L404-1 assume !(~E_2~0 == 1); 1629#L409-1 assume { :end_inline_reset_delta_events } true; 1532#L555-3 [2018-11-10 01:03:48,137 INFO L795 eck$LassoCheckResult]: Loop: 1532#L555-3 assume true; 1456#L555-1 assume !false; 1457#L556 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 1465#L321 assume true; 1630#L283-1 assume !false; 1528#L284 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1529#L256 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 1526#L273 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1451#L274 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 1452#L288 assume !(eval_~tmp~0 != 0); 1598#L336 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 1591#L226-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 1592#L346-3 assume ~M_E~0 == 0;~M_E~0 := 1; 1627#L346-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 1473#L351-3 assume ~T2_E~0 == 0;~T2_E~0 := 1; 1474#L356-3 assume !(~E_M~0 == 0); 1511#L361-3 assume ~E_1~0 == 0;~E_1~0 := 1; 1558#L366-3 assume ~E_2~0 == 0;~E_2~0 := 1; 1677#L371-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1530#L168-12 assume !(~m_pc~0 == 1); 1481#L168-14 is_master_triggered_~__retres1~0 := 0; 1522#L179-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1482#L180-4 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1483#L427-12 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 1512#L427-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1513#L187-12 assume ~t1_pc~0 == 1; 1571#L188-4 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 1597#L198-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1615#L199-4 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1649#L435-12 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 1654#L435-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1656#L206-12 assume ~t2_pc~0 == 1; 1544#L207-4 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 1545#L217-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1547#L218-4 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1548#L443-12 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 1660#L443-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1470#L384-3 assume ~M_E~0 == 1;~M_E~0 := 2; 1471#L384-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 1475#L389-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 1510#L394-3 assume !(~E_M~0 == 1); 1554#L399-3 assume ~E_1~0 == 1;~E_1~0 := 2; 1676#L404-3 assume !(~E_2~0 == 1); 1633#L409-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1634#L256-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 1525#L273-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1449#L274-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 1450#L574 assume !(start_simulation_~tmp~3 == 0); 1586#L574-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1638#L256-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 1519#L273-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1447#L274-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 1448#L529 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 1655#L536 stop_simulation_#res := stop_simulation_~__retres2~0; 1657#L537 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 1531#L587 assume !(start_simulation_~tmp___0~1 != 0); 1532#L555-3 [2018-11-10 01:03:48,137 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 01:03:48,137 INFO L82 PathProgramCache]: Analyzing trace with hash -1995466806, now seen corresponding path program 1 times [2018-11-10 01:03:48,137 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 01:03:48,138 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 01:03:48,139 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:48,139 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 01:03:48,139 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:48,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 01:03:48,176 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 01:03:48,176 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 01:03:48,176 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 01:03:48,177 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 01:03:48,177 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 01:03:48,177 INFO L82 PathProgramCache]: Analyzing trace with hash 877872416, now seen corresponding path program 1 times [2018-11-10 01:03:48,177 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 01:03:48,177 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 01:03:48,178 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:48,178 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 01:03:48,179 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:48,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 01:03:48,224 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 01:03:48,225 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 01:03:48,225 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 01:03:48,225 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 01:03:48,226 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 01:03:48,226 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 01:03:48,226 INFO L87 Difference]: Start difference. First operand 235 states and 338 transitions. cyclomatic complexity: 104 Second operand 3 states. [2018-11-10 01:03:48,303 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 01:03:48,303 INFO L93 Difference]: Finished difference Result 398 states and 565 transitions. [2018-11-10 01:03:48,304 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 01:03:48,304 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 398 states and 565 transitions. [2018-11-10 01:03:48,306 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 354 [2018-11-10 01:03:48,309 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 398 states to 398 states and 565 transitions. [2018-11-10 01:03:48,309 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 398 [2018-11-10 01:03:48,310 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 398 [2018-11-10 01:03:48,310 INFO L73 IsDeterministic]: Start isDeterministic. Operand 398 states and 565 transitions. [2018-11-10 01:03:48,311 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 01:03:48,312 INFO L705 BuchiCegarLoop]: Abstraction has 398 states and 565 transitions. [2018-11-10 01:03:48,312 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 398 states and 565 transitions. [2018-11-10 01:03:48,323 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 398 to 395. [2018-11-10 01:03:48,323 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 395 states. [2018-11-10 01:03:48,326 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 395 states to 395 states and 562 transitions. [2018-11-10 01:03:48,326 INFO L728 BuchiCegarLoop]: Abstraction has 395 states and 562 transitions. [2018-11-10 01:03:48,326 INFO L608 BuchiCegarLoop]: Abstraction has 395 states and 562 transitions. [2018-11-10 01:03:48,326 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ [2018-11-10 01:03:48,326 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 395 states and 562 transitions. [2018-11-10 01:03:48,329 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 351 [2018-11-10 01:03:48,329 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 01:03:48,329 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 01:03:48,330 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 01:03:48,331 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 01:03:48,331 INFO L793 eck$LassoCheckResult]: Stem: 2253#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 2098#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 2099#L518 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 2233#L226 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2234#L233 assume ~m_i~0 == 1;~m_st~0 := 0; 2343#L233-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 2285#L238-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 2286#L243-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2270#L346 assume !(~M_E~0 == 0); 2267#L346-2 assume !(~T1_E~0 == 0); 2100#L351-1 assume !(~T2_E~0 == 0); 2101#L356-1 assume !(~E_M~0 == 0); 2149#L361-1 assume !(~E_1~0 == 0); 2181#L366-1 assume !(~E_2~0 == 0); 2324#L371-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2312#L168 assume !(~m_pc~0 == 1); 2143#L168-2 is_master_triggered_~__retres1~0 := 0; 2303#L179 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2144#L180 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2145#L427 assume !(activate_threads_~tmp~1 != 0); 2176#L427-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2177#L187 assume !(~t1_pc~0 == 1); 2243#L187-2 is_transmit1_triggered_~__retres1~1 := 0; 2245#L198 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2246#L199 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2228#L435 assume !(activate_threads_~tmp___0~0 != 0); 2229#L435-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2235#L206 assume !(~t2_pc~0 == 1); 2340#L206-2 is_transmit2_triggered_~__retres1~2 := 0; 2341#L217 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2157#L218 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2158#L443 assume !(activate_threads_~tmp___1~0 != 0); 2320#L443-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2139#L384 assume !(~M_E~0 == 1); 2102#L384-2 assume ~T1_E~0 == 1;~T1_E~0 := 2; 2103#L389-1 assume !(~T2_E~0 == 1); 2148#L394-1 assume !(~E_M~0 == 1); 2178#L399-1 assume !(~E_1~0 == 1); 2321#L404-1 assume !(~E_2~0 == 1); 2271#L409-1 assume { :end_inline_reset_delta_events } true; 2170#L555-3 [2018-11-10 01:03:48,331 INFO L795 eck$LassoCheckResult]: Loop: 2170#L555-3 assume true; 2269#L555-1 assume !false; 2407#L556 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 2105#L321 assume true; 2406#L283-1 assume !false; 2405#L284 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2403#L256 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 2164#L273 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2091#L274 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 2092#L288 assume !(eval_~tmp~0 != 0); 2280#L336 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 2464#L226-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 2463#L346-3 assume ~M_E~0 == 0;~M_E~0 := 1; 2462#L346-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 2461#L351-3 assume ~T2_E~0 == 0;~T2_E~0 := 1; 2460#L356-3 assume !(~E_M~0 == 0); 2459#L361-3 assume ~E_1~0 == 0;~E_1~0 := 1; 2426#L366-3 assume ~E_2~0 == 0;~E_2~0 := 1; 2342#L371-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2168#L168-12 assume !(~m_pc~0 == 1); 2121#L168-14 is_master_triggered_~__retres1~0 := 0; 2423#L179-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2122#L180-4 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2123#L427-12 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 2172#L427-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2414#L187-12 assume ~t1_pc~0 == 1; 2412#L188-4 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 2411#L198-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2410#L199-4 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2409#L435-12 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 2408#L435-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2337#L206-12 assume !(~t2_pc~0 == 1); 2334#L206-14 is_transmit2_triggered_~__retres1~2 := 0; 2335#L217-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2186#L218-4 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2187#L443-12 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 2304#L443-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2110#L384-3 assume ~M_E~0 == 1;~M_E~0 := 2; 2111#L384-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 2115#L389-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 2150#L394-3 assume !(~E_M~0 == 1); 2190#L399-3 assume ~E_1~0 == 1;~E_1~0 := 2; 2327#L404-3 assume !(~E_2~0 == 1); 2275#L409-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2276#L256-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 2163#L273-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2089#L274-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 2090#L574 assume !(start_simulation_~tmp~3 == 0); 2225#L574-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2281#L256-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 2156#L273-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2087#L274-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 2088#L529 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 2298#L536 stop_simulation_#res := stop_simulation_~__retres2~0; 2301#L537 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 2169#L587 assume !(start_simulation_~tmp___0~1 != 0); 2170#L555-3 [2018-11-10 01:03:48,332 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 01:03:48,332 INFO L82 PathProgramCache]: Analyzing trace with hash 1020175755, now seen corresponding path program 1 times [2018-11-10 01:03:48,332 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 01:03:48,332 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 01:03:48,333 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:48,333 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 01:03:48,334 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:48,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 01:03:48,378 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 01:03:48,379 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 01:03:48,379 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 01:03:48,379 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 01:03:48,380 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 01:03:48,380 INFO L82 PathProgramCache]: Analyzing trace with hash -1179731615, now seen corresponding path program 1 times [2018-11-10 01:03:48,380 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 01:03:48,380 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 01:03:48,381 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:48,381 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 01:03:48,381 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:48,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 01:03:48,420 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 01:03:48,420 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 01:03:48,420 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 01:03:48,421 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 01:03:48,421 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 01:03:48,421 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 01:03:48,421 INFO L87 Difference]: Start difference. First operand 395 states and 562 transitions. cyclomatic complexity: 169 Second operand 3 states. [2018-11-10 01:03:48,446 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 01:03:48,446 INFO L93 Difference]: Finished difference Result 395 states and 554 transitions. [2018-11-10 01:03:48,447 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 01:03:48,447 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 395 states and 554 transitions. [2018-11-10 01:03:48,450 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 351 [2018-11-10 01:03:48,451 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 395 states to 395 states and 554 transitions. [2018-11-10 01:03:48,452 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 395 [2018-11-10 01:03:48,452 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 395 [2018-11-10 01:03:48,452 INFO L73 IsDeterministic]: Start isDeterministic. Operand 395 states and 554 transitions. [2018-11-10 01:03:48,453 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 01:03:48,453 INFO L705 BuchiCegarLoop]: Abstraction has 395 states and 554 transitions. [2018-11-10 01:03:48,454 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 395 states and 554 transitions. [2018-11-10 01:03:48,459 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 395 to 395. [2018-11-10 01:03:48,459 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 395 states. [2018-11-10 01:03:48,461 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 395 states to 395 states and 554 transitions. [2018-11-10 01:03:48,461 INFO L728 BuchiCegarLoop]: Abstraction has 395 states and 554 transitions. [2018-11-10 01:03:48,462 INFO L608 BuchiCegarLoop]: Abstraction has 395 states and 554 transitions. [2018-11-10 01:03:48,462 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ [2018-11-10 01:03:48,462 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 395 states and 554 transitions. [2018-11-10 01:03:48,464 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 351 [2018-11-10 01:03:48,464 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 01:03:48,464 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 01:03:48,465 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 01:03:48,465 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 01:03:48,466 INFO L793 eck$LassoCheckResult]: Stem: 3046#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 2895#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 2896#L518 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 3028#L226 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3029#L233 assume ~m_i~0 == 1;~m_st~0 := 0; 3129#L233-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 3077#L238-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 3078#L243-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3062#L346 assume !(~M_E~0 == 0); 3060#L346-2 assume !(~T1_E~0 == 0); 2897#L351-1 assume !(~T2_E~0 == 0); 2898#L356-1 assume !(~E_M~0 == 0); 2946#L361-1 assume !(~E_1~0 == 0); 2976#L366-1 assume !(~E_2~0 == 0); 3114#L371-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3104#L168 assume !(~m_pc~0 == 1); 2940#L168-2 is_master_triggered_~__retres1~0 := 0; 3094#L179 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2941#L180 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2942#L427 assume !(activate_threads_~tmp~1 != 0); 2968#L427-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2969#L187 assume !(~t1_pc~0 == 1); 3038#L187-2 is_transmit1_triggered_~__retres1~1 := 0; 3040#L198 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3041#L199 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 3023#L435 assume !(activate_threads_~tmp___0~0 != 0); 3024#L435-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3030#L206 assume !(~t2_pc~0 == 1); 3126#L206-2 is_transmit2_triggered_~__retres1~2 := 0; 3127#L217 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2954#L218 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2955#L443 assume !(activate_threads_~tmp___1~0 != 0); 3111#L443-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2936#L384 assume !(~M_E~0 == 1); 2899#L384-2 assume !(~T1_E~0 == 1); 2900#L389-1 assume !(~T2_E~0 == 1); 2945#L394-1 assume !(~E_M~0 == 1); 2970#L399-1 assume !(~E_1~0 == 1); 3112#L404-1 assume !(~E_2~0 == 1); 3063#L409-1 assume { :end_inline_reset_delta_events } true; 2966#L555-3 [2018-11-10 01:03:48,466 INFO L795 eck$LassoCheckResult]: Loop: 2966#L555-3 assume true; 2893#L555-1 assume !false; 2894#L556 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 2902#L321 assume true; 3064#L283-1 assume !false; 2962#L284 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2963#L256 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 2960#L273 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2888#L274 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 2889#L288 assume !(eval_~tmp~0 != 0); 3032#L336 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 3025#L226-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 3026#L346-3 assume ~M_E~0 == 0;~M_E~0 := 1; 3061#L346-5 assume !(~T1_E~0 == 0); 2910#L351-3 assume ~T2_E~0 == 0;~T2_E~0 := 1; 2911#L356-3 assume !(~E_M~0 == 0); 2948#L361-3 assume ~E_1~0 == 0;~E_1~0 := 1; 2992#L366-3 assume ~E_2~0 == 0;~E_2~0 := 1; 3117#L371-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2964#L168-12 assume !(~m_pc~0 == 1); 2918#L168-14 is_master_triggered_~__retres1~0 := 0; 2956#L179-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2919#L180-4 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2920#L427-12 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 2949#L427-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2950#L187-12 assume ~t1_pc~0 == 1; 3005#L188-4 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 3031#L198-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3049#L199-4 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 3084#L435-12 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 3089#L435-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3091#L206-12 assume !(~t2_pc~0 == 1); 3122#L206-14 is_transmit2_triggered_~__retres1~2 := 0; 3271#L217-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3269#L218-4 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3267#L443-12 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 3265#L443-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3264#L384-3 assume ~M_E~0 == 1;~M_E~0 := 2; 3260#L384-5 assume !(~T1_E~0 == 1); 3258#L389-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 3256#L394-3 assume !(~E_M~0 == 1); 3254#L399-3 assume ~E_1~0 == 1;~E_1~0 := 2; 3252#L404-3 assume !(~E_2~0 == 1); 3244#L409-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 3238#L256-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 3235#L273-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 3233#L274-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 3231#L574 assume !(start_simulation_~tmp~3 == 0); 3020#L574-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 3073#L256-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 2953#L273-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2884#L274-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 2885#L529 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 3090#L536 stop_simulation_#res := stop_simulation_~__retres2~0; 3092#L537 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 2965#L587 assume !(start_simulation_~tmp___0~1 != 0); 2966#L555-3 [2018-11-10 01:03:48,466 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 01:03:48,467 INFO L82 PathProgramCache]: Analyzing trace with hash 1077434057, now seen corresponding path program 1 times [2018-11-10 01:03:48,467 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 01:03:48,467 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 01:03:48,468 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:48,468 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 01:03:48,468 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:48,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 01:03:48,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 01:03:48,500 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 01:03:48,501 INFO L82 PathProgramCache]: Analyzing trace with hash 223697697, now seen corresponding path program 1 times [2018-11-10 01:03:48,501 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 01:03:48,501 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 01:03:48,502 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:48,502 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 01:03:48,502 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:48,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 01:03:48,541 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 01:03:48,542 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 01:03:48,542 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 01:03:48,542 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 01:03:48,542 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 01:03:48,543 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 01:03:48,543 INFO L87 Difference]: Start difference. First operand 395 states and 554 transitions. cyclomatic complexity: 161 Second operand 3 states. [2018-11-10 01:03:48,614 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 01:03:48,614 INFO L93 Difference]: Finished difference Result 580 states and 808 transitions. [2018-11-10 01:03:48,615 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 01:03:48,616 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 580 states and 808 transitions. [2018-11-10 01:03:48,621 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 509 [2018-11-10 01:03:48,625 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 580 states to 580 states and 808 transitions. [2018-11-10 01:03:48,626 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 580 [2018-11-10 01:03:48,626 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 580 [2018-11-10 01:03:48,627 INFO L73 IsDeterministic]: Start isDeterministic. Operand 580 states and 808 transitions. [2018-11-10 01:03:48,628 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 01:03:48,628 INFO L705 BuchiCegarLoop]: Abstraction has 580 states and 808 transitions. [2018-11-10 01:03:48,629 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 580 states and 808 transitions. [2018-11-10 01:03:48,639 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 580 to 579. [2018-11-10 01:03:48,639 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 579 states. [2018-11-10 01:03:48,642 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 579 states to 579 states and 807 transitions. [2018-11-10 01:03:48,642 INFO L728 BuchiCegarLoop]: Abstraction has 579 states and 807 transitions. [2018-11-10 01:03:48,642 INFO L608 BuchiCegarLoop]: Abstraction has 579 states and 807 transitions. [2018-11-10 01:03:48,642 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ [2018-11-10 01:03:48,642 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 579 states and 807 transitions. [2018-11-10 01:03:48,646 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 508 [2018-11-10 01:03:48,646 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 01:03:48,646 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 01:03:48,647 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 01:03:48,648 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 01:03:48,648 INFO L793 eck$LassoCheckResult]: Stem: 4023#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 3876#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 3877#L518 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 4005#L226 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4006#L233 assume ~m_i~0 == 1;~m_st~0 := 0; 4112#L233-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 4056#L238-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 4057#L243-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4041#L346 assume !(~M_E~0 == 0); 4039#L346-2 assume !(~T1_E~0 == 0); 3878#L351-1 assume !(~T2_E~0 == 0); 3879#L356-1 assume !(~E_M~0 == 0); 3927#L361-1 assume !(~E_1~0 == 0); 3957#L366-1 assume ~E_2~0 == 0;~E_2~0 := 1; 4095#L371-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4084#L168 assume !(~m_pc~0 == 1); 3921#L168-2 is_master_triggered_~__retres1~0 := 0; 4074#L179 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3922#L180 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 3923#L427 assume !(activate_threads_~tmp~1 != 0); 3949#L427-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3950#L187 assume !(~t1_pc~0 == 1); 4015#L187-2 is_transmit1_triggered_~__retres1~1 := 0; 4017#L198 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4018#L199 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 4000#L435 assume !(activate_threads_~tmp___0~0 != 0); 4001#L435-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4007#L206 assume !(~t2_pc~0 == 1); 4110#L206-2 is_transmit2_triggered_~__retres1~2 := 0; 4111#L217 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3935#L218 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3936#L443 assume !(activate_threads_~tmp___1~0 != 0); 4091#L443-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3917#L384 assume !(~M_E~0 == 1); 3880#L384-2 assume !(~T1_E~0 == 1); 3881#L389-1 assume !(~T2_E~0 == 1); 3926#L394-1 assume !(~E_M~0 == 1); 3951#L399-1 assume !(~E_1~0 == 1); 4092#L404-1 assume ~E_2~0 == 1;~E_2~0 := 2; 4042#L409-1 assume { :end_inline_reset_delta_events } true; 3947#L555-3 [2018-11-10 01:03:48,648 INFO L795 eck$LassoCheckResult]: Loop: 3947#L555-3 assume true; 3874#L555-1 assume !false; 3875#L556 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 3883#L321 assume true; 4043#L283-1 assume !false; 3943#L284 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 3944#L256 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 3941#L273 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 3869#L274 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 3870#L288 assume !(eval_~tmp~0 != 0); 4009#L336 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 4002#L226-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 4003#L346-3 assume ~M_E~0 == 0;~M_E~0 := 1; 4040#L346-5 assume !(~T1_E~0 == 0); 3891#L351-3 assume ~T2_E~0 == 0;~T2_E~0 := 1; 3892#L356-3 assume !(~E_M~0 == 0); 3929#L361-3 assume ~E_1~0 == 0;~E_1~0 := 1; 3971#L366-3 assume ~E_2~0 == 0;~E_2~0 := 1; 4100#L371-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3945#L168-12 assume !(~m_pc~0 == 1); 3899#L168-14 is_master_triggered_~__retres1~0 := 0; 3937#L179-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3900#L180-4 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 3901#L427-12 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 3930#L427-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3931#L187-12 assume ~t1_pc~0 == 1; 3982#L188-4 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 4008#L198-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4352#L199-4 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 4351#L435-12 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 4350#L435-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4349#L206-12 assume !(~t2_pc~0 == 1); 4348#L206-14 is_transmit2_triggered_~__retres1~2 := 0; 4346#L217-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4344#L218-4 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 4342#L443-12 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 4340#L443-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4338#L384-3 assume ~M_E~0 == 1;~M_E~0 := 2; 4336#L384-5 assume !(~T1_E~0 == 1); 4334#L389-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 4332#L394-3 assume !(~E_M~0 == 1); 4330#L399-3 assume ~E_1~0 == 1;~E_1~0 := 2; 4329#L404-3 assume ~E_2~0 == 1;~E_2~0 := 2; 4327#L409-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4325#L256-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 4323#L273-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 4322#L274-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 4321#L574 assume !(start_simulation_~tmp~3 == 0); 3997#L574-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4052#L256-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 3934#L273-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 3865#L274-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 3866#L529 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 4070#L536 stop_simulation_#res := stop_simulation_~__retres2~0; 4072#L537 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 3946#L587 assume !(start_simulation_~tmp___0~1 != 0); 3947#L555-3 [2018-11-10 01:03:48,649 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 01:03:48,649 INFO L82 PathProgramCache]: Analyzing trace with hash -845794039, now seen corresponding path program 1 times [2018-11-10 01:03:48,649 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 01:03:48,649 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 01:03:48,650 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:48,650 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 01:03:48,650 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:48,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 01:03:48,674 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 01:03:48,675 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 01:03:48,675 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 01:03:48,675 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 01:03:48,675 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 01:03:48,676 INFO L82 PathProgramCache]: Analyzing trace with hash 1234814947, now seen corresponding path program 1 times [2018-11-10 01:03:48,676 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 01:03:48,676 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 01:03:48,677 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:48,677 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 01:03:48,677 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:48,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 01:03:48,714 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 01:03:48,714 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 01:03:48,714 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 01:03:48,715 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 01:03:48,715 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 01:03:48,715 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 01:03:48,715 INFO L87 Difference]: Start difference. First operand 579 states and 807 transitions. cyclomatic complexity: 230 Second operand 3 states. [2018-11-10 01:03:48,743 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 01:03:48,744 INFO L93 Difference]: Finished difference Result 395 states and 541 transitions. [2018-11-10 01:03:48,749 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 01:03:48,749 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 395 states and 541 transitions. [2018-11-10 01:03:48,752 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 351 [2018-11-10 01:03:48,754 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 395 states to 395 states and 541 transitions. [2018-11-10 01:03:48,755 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 395 [2018-11-10 01:03:48,755 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 395 [2018-11-10 01:03:48,755 INFO L73 IsDeterministic]: Start isDeterministic. Operand 395 states and 541 transitions. [2018-11-10 01:03:48,756 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 01:03:48,756 INFO L705 BuchiCegarLoop]: Abstraction has 395 states and 541 transitions. [2018-11-10 01:03:48,757 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 395 states and 541 transitions. [2018-11-10 01:03:48,763 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 395 to 395. [2018-11-10 01:03:48,763 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 395 states. [2018-11-10 01:03:48,765 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 395 states to 395 states and 541 transitions. [2018-11-10 01:03:48,765 INFO L728 BuchiCegarLoop]: Abstraction has 395 states and 541 transitions. [2018-11-10 01:03:48,765 INFO L608 BuchiCegarLoop]: Abstraction has 395 states and 541 transitions. [2018-11-10 01:03:48,765 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ [2018-11-10 01:03:48,766 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 395 states and 541 transitions. [2018-11-10 01:03:48,768 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 351 [2018-11-10 01:03:48,768 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 01:03:48,769 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 01:03:48,769 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 01:03:48,770 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 01:03:48,770 INFO L793 eck$LassoCheckResult]: Stem: 5005#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 4859#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 4860#L518 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 4987#L226 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4988#L233 assume ~m_i~0 == 1;~m_st~0 := 0; 5092#L233-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 5036#L238-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 5037#L243-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5021#L346 assume !(~M_E~0 == 0); 5019#L346-2 assume !(~T1_E~0 == 0); 4861#L351-1 assume !(~T2_E~0 == 0); 4862#L356-1 assume !(~E_M~0 == 0); 4910#L361-1 assume !(~E_1~0 == 0); 4939#L366-1 assume !(~E_2~0 == 0); 5073#L371-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5063#L168 assume !(~m_pc~0 == 1); 4904#L168-2 is_master_triggered_~__retres1~0 := 0; 5053#L179 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4905#L180 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 4906#L427 assume !(activate_threads_~tmp~1 != 0); 4932#L427-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4933#L187 assume !(~t1_pc~0 == 1); 4997#L187-2 is_transmit1_triggered_~__retres1~1 := 0; 4999#L198 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5000#L199 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 4982#L435 assume !(activate_threads_~tmp___0~0 != 0); 4983#L435-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4989#L206 assume !(~t2_pc~0 == 1); 5089#L206-2 is_transmit2_triggered_~__retres1~2 := 0; 5090#L217 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4918#L218 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 4919#L443 assume !(activate_threads_~tmp___1~0 != 0); 5070#L443-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4900#L384 assume !(~M_E~0 == 1); 4863#L384-2 assume !(~T1_E~0 == 1); 4864#L389-1 assume !(~T2_E~0 == 1); 4909#L394-1 assume !(~E_M~0 == 1); 4934#L399-1 assume !(~E_1~0 == 1); 5071#L404-1 assume !(~E_2~0 == 1); 5022#L409-1 assume { :end_inline_reset_delta_events } true; 4930#L555-3 [2018-11-10 01:03:48,770 INFO L795 eck$LassoCheckResult]: Loop: 4930#L555-3 assume true; 4857#L555-1 assume !false; 4858#L556 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 4866#L321 assume true; 5023#L283-1 assume !false; 4926#L284 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4927#L256 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 4924#L273 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 4852#L274 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 4853#L288 assume !(eval_~tmp~0 != 0); 4991#L336 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 4984#L226-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 4985#L346-3 assume ~M_E~0 == 0;~M_E~0 := 1; 5020#L346-5 assume !(~T1_E~0 == 0); 4874#L351-3 assume ~T2_E~0 == 0;~T2_E~0 := 1; 4875#L356-3 assume !(~E_M~0 == 0); 4912#L361-3 assume ~E_1~0 == 0;~E_1~0 := 1; 4953#L366-3 assume !(~E_2~0 == 0); 5077#L371-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4928#L168-12 assume !(~m_pc~0 == 1); 4882#L168-14 is_master_triggered_~__retres1~0 := 0; 4920#L179-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4883#L180-4 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 4884#L427-12 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 4913#L427-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4914#L187-12 assume ~t1_pc~0 == 1; 4964#L188-4 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 4990#L198-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5008#L199-4 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 5043#L435-12 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 5048#L435-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5050#L206-12 assume !(~t2_pc~0 == 1); 5084#L206-14 is_transmit2_triggered_~__retres1~2 := 0; 5234#L217-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5232#L218-4 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 5230#L443-12 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 5228#L443-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5227#L384-3 assume ~M_E~0 == 1;~M_E~0 := 2; 5223#L384-5 assume !(~T1_E~0 == 1); 5221#L389-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 5219#L394-3 assume !(~E_M~0 == 1); 5217#L399-3 assume ~E_1~0 == 1;~E_1~0 := 2; 5215#L404-3 assume !(~E_2~0 == 1); 5207#L409-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 5201#L256-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 5198#L273-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 5196#L274-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 5194#L574 assume !(start_simulation_~tmp~3 == 0); 4979#L574-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 5032#L256-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 4917#L273-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 4848#L274-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 4849#L529 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 5049#L536 stop_simulation_#res := stop_simulation_~__retres2~0; 5051#L537 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 4929#L587 assume !(start_simulation_~tmp___0~1 != 0); 4930#L555-3 [2018-11-10 01:03:48,771 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 01:03:48,771 INFO L82 PathProgramCache]: Analyzing trace with hash 1077434057, now seen corresponding path program 2 times [2018-11-10 01:03:48,771 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 01:03:48,771 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 01:03:48,772 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:48,772 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 01:03:48,772 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:48,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 01:03:48,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 01:03:48,789 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 01:03:48,789 INFO L82 PathProgramCache]: Analyzing trace with hash -1621669469, now seen corresponding path program 1 times [2018-11-10 01:03:48,789 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 01:03:48,789 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 01:03:48,790 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:48,790 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 01:03:48,790 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:48,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 01:03:48,822 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 01:03:48,823 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 01:03:48,823 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 01:03:48,823 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 01:03:48,823 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 01:03:48,824 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 01:03:48,826 INFO L87 Difference]: Start difference. First operand 395 states and 541 transitions. cyclomatic complexity: 148 Second operand 5 states. [2018-11-10 01:03:48,919 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 01:03:48,919 INFO L93 Difference]: Finished difference Result 677 states and 917 transitions. [2018-11-10 01:03:48,919 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-10 01:03:48,919 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 677 states and 917 transitions. [2018-11-10 01:03:48,923 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 631 [2018-11-10 01:03:48,927 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 677 states to 677 states and 917 transitions. [2018-11-10 01:03:48,927 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 677 [2018-11-10 01:03:48,928 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 677 [2018-11-10 01:03:48,928 INFO L73 IsDeterministic]: Start isDeterministic. Operand 677 states and 917 transitions. [2018-11-10 01:03:48,930 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 01:03:48,930 INFO L705 BuchiCegarLoop]: Abstraction has 677 states and 917 transitions. [2018-11-10 01:03:48,931 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 677 states and 917 transitions. [2018-11-10 01:03:48,938 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 677 to 401. [2018-11-10 01:03:48,939 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 401 states. [2018-11-10 01:03:48,940 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 401 states to 401 states and 547 transitions. [2018-11-10 01:03:48,940 INFO L728 BuchiCegarLoop]: Abstraction has 401 states and 547 transitions. [2018-11-10 01:03:48,940 INFO L608 BuchiCegarLoop]: Abstraction has 401 states and 547 transitions. [2018-11-10 01:03:48,941 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ [2018-11-10 01:03:48,941 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 401 states and 547 transitions. [2018-11-10 01:03:48,943 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 357 [2018-11-10 01:03:48,943 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 01:03:48,943 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 01:03:48,944 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 01:03:48,944 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 01:03:48,944 INFO L793 eck$LassoCheckResult]: Stem: 6100#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 5947#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 5948#L518 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 6080#L226 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6081#L233 assume ~m_i~0 == 1;~m_st~0 := 0; 6198#L233-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 6137#L238-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 6138#L243-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6120#L346 assume !(~M_E~0 == 0); 6116#L346-2 assume !(~T1_E~0 == 0); 5949#L351-1 assume !(~T2_E~0 == 0); 5950#L356-1 assume !(~E_M~0 == 0); 5998#L361-1 assume !(~E_1~0 == 0); 6030#L366-1 assume !(~E_2~0 == 0); 6178#L371-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6166#L168 assume !(~m_pc~0 == 1); 5992#L168-2 is_master_triggered_~__retres1~0 := 0; 6156#L179 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5993#L180 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 5994#L427 assume !(activate_threads_~tmp~1 != 0); 6023#L427-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6024#L187 assume !(~t1_pc~0 == 1); 6091#L187-2 is_transmit1_triggered_~__retres1~1 := 0; 6093#L198 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6094#L199 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 6075#L435 assume !(activate_threads_~tmp___0~0 != 0); 6076#L435-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6082#L206 assume !(~t2_pc~0 == 1); 6196#L206-2 is_transmit2_triggered_~__retres1~2 := 0; 6197#L217 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6008#L218 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 6009#L443 assume !(activate_threads_~tmp___1~0 != 0); 6175#L443-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5988#L384 assume !(~M_E~0 == 1); 5951#L384-2 assume !(~T1_E~0 == 1); 5952#L389-1 assume !(~T2_E~0 == 1); 5997#L394-1 assume !(~E_M~0 == 1); 6025#L399-1 assume !(~E_1~0 == 1); 6176#L404-1 assume !(~E_2~0 == 1); 6121#L409-1 assume { :end_inline_reset_delta_events } true; 6122#L555-3 [2018-11-10 01:03:48,944 INFO L795 eck$LassoCheckResult]: Loop: 6122#L555-3 assume true; 6318#L555-1 assume !false; 6317#L556 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 6115#L321 assume true; 6316#L283-1 assume !false; 6017#L284 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6018#L256 assume !(~m_st~0 == 0); 6189#L260 assume !(~t1_st~0 == 0); 6276#L264 assume !(~t2_st~0 == 0);exists_runnable_thread_~__retres1~3 := 0; 6275#L273 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 6256#L274 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 6232#L288 assume !(eval_~tmp~0 != 0); 6084#L336 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 6085#L226-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 6117#L346-3 assume ~M_E~0 == 0;~M_E~0 := 1; 6118#L346-5 assume !(~T1_E~0 == 0); 6278#L351-3 assume ~T2_E~0 == 0;~T2_E~0 := 1; 6001#L356-3 assume !(~E_M~0 == 0); 6002#L361-3 assume ~E_1~0 == 0;~E_1~0 := 1; 6183#L366-3 assume !(~E_2~0 == 0); 6184#L371-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6019#L168-12 assume !(~m_pc~0 == 1); 5970#L168-14 is_master_triggered_~__retres1~0 := 0; 6010#L179-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5971#L180-4 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 5972#L427-12 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 6003#L427-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6004#L187-12 assume ~t1_pc~0 == 1; 6057#L188-4 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 6083#L198-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6103#L199-4 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 6145#L435-12 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 6150#L435-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6152#L206-12 assume !(~t2_pc~0 == 1); 6192#L206-14 is_transmit2_triggered_~__retres1~2 := 0; 6315#L217-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6314#L218-4 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 6173#L443-12 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 6174#L443-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5959#L384-3 assume ~M_E~0 == 1;~M_E~0 := 2; 5960#L384-5 assume !(~T1_E~0 == 1); 5964#L389-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 6312#L394-3 assume !(~E_M~0 == 1); 6181#L399-3 assume ~E_1~0 == 1;~E_1~0 := 2; 6182#L404-3 assume !(~E_2~0 == 1); 6127#L409-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6128#L256-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 6013#L273-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 5938#L274-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 5939#L574 assume !(start_simulation_~tmp~3 == 0); 6132#L574-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6133#L256-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 6007#L273-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 5936#L274-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 5937#L529 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 6151#L536 stop_simulation_#res := stop_simulation_~__retres2~0; 6153#L537 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 6154#L587 assume !(start_simulation_~tmp___0~1 != 0); 6122#L555-3 [2018-11-10 01:03:48,944 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 01:03:48,945 INFO L82 PathProgramCache]: Analyzing trace with hash 1077434057, now seen corresponding path program 3 times [2018-11-10 01:03:48,945 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 01:03:48,945 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 01:03:48,946 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:48,946 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 01:03:48,946 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:48,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 01:03:48,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 01:03:48,959 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 01:03:48,960 INFO L82 PathProgramCache]: Analyzing trace with hash -845440580, now seen corresponding path program 1 times [2018-11-10 01:03:48,960 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 01:03:48,960 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 01:03:48,964 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:48,965 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 01:03:48,965 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:48,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 01:03:49,023 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 01:03:49,023 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 01:03:49,023 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 01:03:49,024 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 01:03:49,024 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 01:03:49,026 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 01:03:49,026 INFO L87 Difference]: Start difference. First operand 401 states and 547 transitions. cyclomatic complexity: 148 Second operand 5 states. [2018-11-10 01:03:49,129 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 01:03:49,129 INFO L93 Difference]: Finished difference Result 540 states and 733 transitions. [2018-11-10 01:03:49,130 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-10 01:03:49,130 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 540 states and 733 transitions. [2018-11-10 01:03:49,133 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 496 [2018-11-10 01:03:49,134 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 540 states to 540 states and 733 transitions. [2018-11-10 01:03:49,135 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 540 [2018-11-10 01:03:49,135 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 540 [2018-11-10 01:03:49,135 INFO L73 IsDeterministic]: Start isDeterministic. Operand 540 states and 733 transitions. [2018-11-10 01:03:49,136 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 01:03:49,137 INFO L705 BuchiCegarLoop]: Abstraction has 540 states and 733 transitions. [2018-11-10 01:03:49,137 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 540 states and 733 transitions. [2018-11-10 01:03:49,143 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 540 to 404. [2018-11-10 01:03:49,143 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 404 states. [2018-11-10 01:03:49,144 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 404 states to 404 states and 541 transitions. [2018-11-10 01:03:49,144 INFO L728 BuchiCegarLoop]: Abstraction has 404 states and 541 transitions. [2018-11-10 01:03:49,144 INFO L608 BuchiCegarLoop]: Abstraction has 404 states and 541 transitions. [2018-11-10 01:03:49,144 INFO L442 BuchiCegarLoop]: ======== Iteration 10============ [2018-11-10 01:03:49,145 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 404 states and 541 transitions. [2018-11-10 01:03:49,146 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 360 [2018-11-10 01:03:49,146 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 01:03:49,147 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 01:03:49,148 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 01:03:49,148 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 01:03:49,148 INFO L793 eck$LassoCheckResult]: Stem: 7055#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 6901#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 6902#L518 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 7034#L226 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7035#L233 assume ~m_i~0 == 1;~m_st~0 := 0; 7156#L233-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 7088#L238-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 7089#L243-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7073#L346 assume !(~M_E~0 == 0); 7070#L346-2 assume !(~T1_E~0 == 0); 6903#L351-1 assume !(~T2_E~0 == 0); 6904#L356-1 assume !(~E_M~0 == 0); 6952#L361-1 assume !(~E_1~0 == 0); 6986#L366-1 assume !(~E_2~0 == 0); 7131#L371-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7120#L168 assume !(~m_pc~0 == 1); 6946#L168-2 is_master_triggered_~__retres1~0 := 0; 7111#L179 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6947#L180 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 6948#L427 assume !(activate_threads_~tmp~1 != 0); 6979#L427-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6980#L187 assume !(~t1_pc~0 == 1); 7044#L187-2 is_transmit1_triggered_~__retres1~1 := 0; 7046#L198 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7047#L199 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 7029#L435 assume !(activate_threads_~tmp___0~0 != 0); 7030#L435-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7036#L206 assume !(~t2_pc~0 == 1); 7148#L206-2 is_transmit2_triggered_~__retres1~2 := 0; 7149#L217 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6962#L218 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 6963#L443 assume !(activate_threads_~tmp___1~0 != 0); 7128#L443-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6942#L384 assume !(~M_E~0 == 1); 6905#L384-2 assume !(~T1_E~0 == 1); 6906#L389-1 assume !(~T2_E~0 == 1); 6951#L394-1 assume !(~E_M~0 == 1); 6981#L399-1 assume !(~E_1~0 == 1); 7129#L404-1 assume !(~E_2~0 == 1); 7074#L409-1 assume { :end_inline_reset_delta_events } true; 7075#L555-3 [2018-11-10 01:03:49,148 INFO L795 eck$LassoCheckResult]: Loop: 7075#L555-3 assume true; 6899#L555-1 assume !false; 6900#L556 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 7270#L321 assume true; 7253#L283-1 assume !false; 7252#L284 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 7249#L256 assume !(~m_st~0 == 0); 7250#L260 assume !(~t1_st~0 == 0); 7247#L264 assume !(~t2_st~0 == 0);exists_runnable_thread_~__retres1~3 := 0; 7248#L273 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 7244#L274 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 7241#L288 assume !(eval_~tmp~0 != 0); 7238#L336 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 7236#L226-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 7235#L346-3 assume ~M_E~0 == 0;~M_E~0 := 1; 7232#L346-5 assume !(~T1_E~0 == 0); 7231#L351-3 assume ~T2_E~0 == 0;~T2_E~0 := 1; 7228#L356-3 assume !(~E_M~0 == 0); 7225#L361-3 assume ~E_1~0 == 0;~E_1~0 := 1; 7222#L366-3 assume !(~E_2~0 == 0); 7216#L371-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7213#L168-12 assume !(~m_pc~0 == 1); 7212#L168-14 is_master_triggered_~__retres1~0 := 0; 7211#L179-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7210#L180-4 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 7209#L427-12 assume !(activate_threads_~tmp~1 != 0); 7208#L427-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7207#L187-12 assume ~t1_pc~0 == 1; 7205#L188-4 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 7204#L198-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7097#L199-4 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 7098#L435-12 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 7104#L435-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7107#L206-12 assume !(~t2_pc~0 == 1); 7143#L206-14 is_transmit2_triggered_~__retres1~2 := 0; 7144#L217-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6990#L218-4 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 6991#L443-12 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 7112#L443-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6913#L384-3 assume ~M_E~0 == 1;~M_E~0 := 2; 6914#L384-5 assume !(~T1_E~0 == 1); 6918#L389-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 6953#L394-3 assume !(~E_M~0 == 1); 6994#L399-3 assume ~E_1~0 == 1;~E_1~0 := 2; 7133#L404-3 assume !(~E_2~0 == 1); 7079#L409-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 7080#L256-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 7237#L273-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 6892#L274-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 6893#L574 assume !(start_simulation_~tmp~3 == 0); 7026#L574-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 7084#L256-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 6961#L273-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 6890#L274-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 6891#L529 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 7154#L536 stop_simulation_#res := stop_simulation_~__retres2~0; 7155#L537 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 7274#L587 assume !(start_simulation_~tmp___0~1 != 0); 7075#L555-3 [2018-11-10 01:03:49,149 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 01:03:49,149 INFO L82 PathProgramCache]: Analyzing trace with hash 1077434057, now seen corresponding path program 4 times [2018-11-10 01:03:49,149 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 01:03:49,149 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 01:03:49,150 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:49,150 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 01:03:49,150 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:49,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 01:03:49,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 01:03:49,164 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 01:03:49,164 INFO L82 PathProgramCache]: Analyzing trace with hash -917827138, now seen corresponding path program 1 times [2018-11-10 01:03:49,164 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 01:03:49,164 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 01:03:49,165 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:49,165 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 01:03:49,165 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:49,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 01:03:49,192 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 01:03:49,193 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 01:03:49,193 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 01:03:49,193 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 01:03:49,193 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 01:03:49,194 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 01:03:49,194 INFO L87 Difference]: Start difference. First operand 404 states and 541 transitions. cyclomatic complexity: 139 Second operand 3 states. [2018-11-10 01:03:49,237 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 01:03:49,237 INFO L93 Difference]: Finished difference Result 522 states and 689 transitions. [2018-11-10 01:03:49,238 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 01:03:49,238 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 522 states and 689 transitions. [2018-11-10 01:03:49,240 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 440 [2018-11-10 01:03:49,242 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 522 states to 522 states and 689 transitions. [2018-11-10 01:03:49,242 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 522 [2018-11-10 01:03:49,243 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 522 [2018-11-10 01:03:49,243 INFO L73 IsDeterministic]: Start isDeterministic. Operand 522 states and 689 transitions. [2018-11-10 01:03:49,244 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 01:03:49,244 INFO L705 BuchiCegarLoop]: Abstraction has 522 states and 689 transitions. [2018-11-10 01:03:49,244 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 522 states and 689 transitions. [2018-11-10 01:03:49,249 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 522 to 522. [2018-11-10 01:03:49,249 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 522 states. [2018-11-10 01:03:49,251 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 522 states to 522 states and 689 transitions. [2018-11-10 01:03:49,251 INFO L728 BuchiCegarLoop]: Abstraction has 522 states and 689 transitions. [2018-11-10 01:03:49,251 INFO L608 BuchiCegarLoop]: Abstraction has 522 states and 689 transitions. [2018-11-10 01:03:49,251 INFO L442 BuchiCegarLoop]: ======== Iteration 11============ [2018-11-10 01:03:49,251 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 522 states and 689 transitions. [2018-11-10 01:03:49,253 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 440 [2018-11-10 01:03:49,253 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 01:03:49,254 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 01:03:49,254 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 01:03:49,254 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 01:03:49,255 INFO L793 eck$LassoCheckResult]: Stem: 7981#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 7833#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 7834#L518 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 7962#L226 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7963#L233 assume ~m_i~0 == 1;~m_st~0 := 0; 8064#L233-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 8013#L238-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 8014#L243-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7997#L346 assume !(~M_E~0 == 0); 7995#L346-2 assume !(~T1_E~0 == 0); 7835#L351-1 assume !(~T2_E~0 == 0); 7836#L356-1 assume !(~E_M~0 == 0); 7884#L361-1 assume !(~E_1~0 == 0); 7914#L366-1 assume !(~E_2~0 == 0); 8049#L371-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8040#L168 assume !(~m_pc~0 == 1); 7878#L168-2 is_master_triggered_~__retres1~0 := 0; 8030#L179 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7879#L180 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 7880#L427 assume !(activate_threads_~tmp~1 != 0); 7907#L427-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7908#L187 assume !(~t1_pc~0 == 1); 7972#L187-2 is_transmit1_triggered_~__retres1~1 := 0; 7974#L198 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7975#L199 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 7957#L435 assume !(activate_threads_~tmp___0~0 != 0); 7958#L435-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7964#L206 assume !(~t2_pc~0 == 1); 8062#L206-2 is_transmit2_triggered_~__retres1~2 := 0; 8063#L217 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7892#L218 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 7893#L443 assume !(activate_threads_~tmp___1~0 != 0); 8046#L443-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7874#L384 assume !(~M_E~0 == 1); 7837#L384-2 assume !(~T1_E~0 == 1); 7838#L389-1 assume !(~T2_E~0 == 1); 7883#L394-1 assume !(~E_M~0 == 1); 7909#L399-1 assume !(~E_1~0 == 1); 8047#L404-1 assume !(~E_2~0 == 1); 7998#L409-1 assume { :end_inline_reset_delta_events } true; 7999#L555-3 assume true; 8314#L555-1 assume !false; 8309#L556 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 8307#L321 [2018-11-10 01:03:49,255 INFO L795 eck$LassoCheckResult]: Loop: 8307#L321 assume true; 8306#L283-1 assume !false; 8305#L284 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 8304#L256 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 8303#L273 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 8302#L274 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 8301#L288 assume eval_~tmp~0 != 0; 8300#L288-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 7828#L296 assume !(eval_~tmp_ndt_1~0 != 0); 7830#L293 assume !(~t1_st~0 == 0); 8310#L307 assume !(~t2_st~0 == 0); 8307#L321 [2018-11-10 01:03:49,255 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 01:03:49,255 INFO L82 PathProgramCache]: Analyzing trace with hash 1547564041, now seen corresponding path program 1 times [2018-11-10 01:03:49,255 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 01:03:49,256 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 01:03:49,256 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:49,256 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 01:03:49,257 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:49,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 01:03:49,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 01:03:49,271 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 01:03:49,271 INFO L82 PathProgramCache]: Analyzing trace with hash 1117275699, now seen corresponding path program 1 times [2018-11-10 01:03:49,271 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 01:03:49,271 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 01:03:49,272 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:49,272 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 01:03:49,273 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:49,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 01:03:49,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 01:03:49,279 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 01:03:49,280 INFO L82 PathProgramCache]: Analyzing trace with hash 1567030571, now seen corresponding path program 1 times [2018-11-10 01:03:49,280 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 01:03:49,280 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 01:03:49,281 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:49,281 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 01:03:49,281 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:49,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 01:03:49,317 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 01:03:49,317 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 01:03:49,317 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 01:03:49,397 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 01:03:49,397 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 01:03:49,397 INFO L87 Difference]: Start difference. First operand 522 states and 689 transitions. cyclomatic complexity: 170 Second operand 3 states. [2018-11-10 01:03:49,570 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 01:03:49,570 INFO L93 Difference]: Finished difference Result 910 states and 1183 transitions. [2018-11-10 01:03:49,571 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 01:03:49,572 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 910 states and 1183 transitions. [2018-11-10 01:03:49,575 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 752 [2018-11-10 01:03:49,577 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 910 states to 910 states and 1183 transitions. [2018-11-10 01:03:49,577 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 910 [2018-11-10 01:03:49,578 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 910 [2018-11-10 01:03:49,578 INFO L73 IsDeterministic]: Start isDeterministic. Operand 910 states and 1183 transitions. [2018-11-10 01:03:49,580 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 01:03:49,580 INFO L705 BuchiCegarLoop]: Abstraction has 910 states and 1183 transitions. [2018-11-10 01:03:49,581 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 910 states and 1183 transitions. [2018-11-10 01:03:49,589 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 910 to 864. [2018-11-10 01:03:49,589 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 864 states. [2018-11-10 01:03:49,591 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 864 states to 864 states and 1131 transitions. [2018-11-10 01:03:49,591 INFO L728 BuchiCegarLoop]: Abstraction has 864 states and 1131 transitions. [2018-11-10 01:03:49,591 INFO L608 BuchiCegarLoop]: Abstraction has 864 states and 1131 transitions. [2018-11-10 01:03:49,591 INFO L442 BuchiCegarLoop]: ======== Iteration 12============ [2018-11-10 01:03:49,592 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 864 states and 1131 transitions. [2018-11-10 01:03:49,594 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 706 [2018-11-10 01:03:49,595 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 01:03:49,595 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 01:03:49,595 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 01:03:49,595 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 01:03:49,596 INFO L793 eck$LassoCheckResult]: Stem: 9438#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 9273#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 9274#L518 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 9411#L226 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9412#L233 assume ~m_i~0 == 1;~m_st~0 := 0; 9582#L233-2 assume !(~t1_i~0 == 1);~t1_st~0 := 2; 9583#L238-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 9902#L243-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9901#L346 assume !(~M_E~0 == 0); 9460#L346-2 assume !(~T1_E~0 == 0); 9461#L351-1 assume !(~T2_E~0 == 0); 9326#L356-1 assume !(~E_M~0 == 0); 9327#L361-1 assume !(~E_1~0 == 0); 9545#L366-1 assume !(~E_2~0 == 0); 9546#L371-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9527#L168 assume !(~m_pc~0 == 1); 9320#L168-2 is_master_triggered_~__retres1~0 := 0; 9531#L179 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9321#L180 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 9322#L427 assume !(activate_threads_~tmp~1 != 0); 9351#L427-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9352#L187 assume !(~t1_pc~0 == 1); 9451#L187-2 is_transmit1_triggered_~__retres1~1 := 0; 9452#L198 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9494#L199 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 9495#L435 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 9406#L435-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9898#L206 assume !(~t2_pc~0 == 1); 9578#L206-2 is_transmit2_triggered_~__retres1~2 := 0; 9579#L217 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9581#L218 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 9565#L443 assume !(activate_threads_~tmp___1~0 != 0); 9566#L443-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9315#L384 assume !(~M_E~0 == 1); 9316#L384-2 assume !(~T1_E~0 == 1); 9896#L389-1 assume !(~T2_E~0 == 1); 9353#L394-1 assume !(~E_M~0 == 1); 9354#L399-1 assume !(~E_1~0 == 1); 9570#L404-1 assume !(~E_2~0 == 1); 9466#L409-1 assume { :end_inline_reset_delta_events } true; 9467#L555-3 assume true; 9978#L555-1 assume !false; 9976#L556 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 9974#L321 [2018-11-10 01:03:49,596 INFO L795 eck$LassoCheckResult]: Loop: 9974#L321 assume true; 9973#L283-1 assume !false; 9972#L284 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 9971#L256 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 9970#L273 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 9969#L274 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 9935#L288 assume eval_~tmp~0 != 0; 9934#L288-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 9268#L296 assume !(eval_~tmp_ndt_1~0 != 0); 9270#L293 assume ~t1_st~0 == 0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 9880#L310 assume !(eval_~tmp_ndt_2~0 != 0); 9977#L307 assume !(~t2_st~0 == 0); 9974#L321 [2018-11-10 01:03:49,596 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 01:03:49,596 INFO L82 PathProgramCache]: Analyzing trace with hash -1782617847, now seen corresponding path program 1 times [2018-11-10 01:03:49,596 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 01:03:49,596 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 01:03:49,597 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:49,597 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 01:03:49,597 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:49,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 01:03:49,617 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 01:03:49,618 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 01:03:49,618 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 01:03:49,618 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 01:03:49,618 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 01:03:49,618 INFO L82 PathProgramCache]: Analyzing trace with hash 275700557, now seen corresponding path program 1 times [2018-11-10 01:03:49,619 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 01:03:49,619 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 01:03:49,619 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:49,619 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 01:03:49,620 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:49,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 01:03:49,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 01:03:49,691 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 01:03:49,691 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 01:03:49,691 INFO L87 Difference]: Start difference. First operand 864 states and 1131 transitions. cyclomatic complexity: 270 Second operand 3 states. [2018-11-10 01:03:49,697 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 01:03:49,697 INFO L93 Difference]: Finished difference Result 825 states and 1080 transitions. [2018-11-10 01:03:49,698 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 01:03:49,698 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 825 states and 1080 transitions. [2018-11-10 01:03:49,701 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 706 [2018-11-10 01:03:49,703 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 825 states to 825 states and 1080 transitions. [2018-11-10 01:03:49,703 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 825 [2018-11-10 01:03:49,704 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 825 [2018-11-10 01:03:49,704 INFO L73 IsDeterministic]: Start isDeterministic. Operand 825 states and 1080 transitions. [2018-11-10 01:03:49,705 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 01:03:49,705 INFO L705 BuchiCegarLoop]: Abstraction has 825 states and 1080 transitions. [2018-11-10 01:03:49,706 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 825 states and 1080 transitions. [2018-11-10 01:03:49,713 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 825 to 825. [2018-11-10 01:03:49,714 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 825 states. [2018-11-10 01:03:49,715 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 825 states to 825 states and 1080 transitions. [2018-11-10 01:03:49,715 INFO L728 BuchiCegarLoop]: Abstraction has 825 states and 1080 transitions. [2018-11-10 01:03:49,716 INFO L608 BuchiCegarLoop]: Abstraction has 825 states and 1080 transitions. [2018-11-10 01:03:49,716 INFO L442 BuchiCegarLoop]: ======== Iteration 13============ [2018-11-10 01:03:49,716 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 825 states and 1080 transitions. [2018-11-10 01:03:49,719 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 706 [2018-11-10 01:03:49,719 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 01:03:49,719 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 01:03:49,719 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 01:03:49,720 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 01:03:49,720 INFO L793 eck$LassoCheckResult]: Stem: 11130#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 10968#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 10969#L518 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 11105#L226 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11106#L233 assume ~m_i~0 == 1;~m_st~0 := 0; 11236#L233-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 11170#L238-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 11171#L243-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11150#L346 assume !(~M_E~0 == 0); 11148#L346-2 assume !(~T1_E~0 == 0); 10970#L351-1 assume !(~T2_E~0 == 0); 10971#L356-1 assume !(~E_M~0 == 0); 11019#L361-1 assume !(~E_1~0 == 0); 11057#L366-1 assume !(~E_2~0 == 0); 11219#L371-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11207#L168 assume !(~m_pc~0 == 1); 11013#L168-2 is_master_triggered_~__retres1~0 := 0; 11197#L179 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11014#L180 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 11015#L427 assume !(activate_threads_~tmp~1 != 0); 11049#L427-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11050#L187 assume !(~t1_pc~0 == 1); 11118#L187-2 is_transmit1_triggered_~__retres1~1 := 0; 11122#L198 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11123#L199 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 11099#L435 assume !(activate_threads_~tmp___0~0 != 0); 11100#L435-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11107#L206 assume !(~t2_pc~0 == 1); 11232#L206-2 is_transmit2_triggered_~__retres1~2 := 0; 11233#L217 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11030#L218 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 11031#L443 assume !(activate_threads_~tmp___1~0 != 0); 11214#L443-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11011#L384 assume !(~M_E~0 == 1); 10972#L384-2 assume !(~T1_E~0 == 1); 10973#L389-1 assume !(~T2_E~0 == 1); 11018#L394-1 assume !(~E_M~0 == 1); 11051#L399-1 assume !(~E_1~0 == 1); 11215#L404-1 assume !(~E_2~0 == 1); 11151#L409-1 assume { :end_inline_reset_delta_events } true; 11152#L555-3 assume true; 11581#L555-1 assume !false; 11579#L556 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 11576#L321 [2018-11-10 01:03:49,720 INFO L795 eck$LassoCheckResult]: Loop: 11576#L321 assume true; 11575#L283-1 assume !false; 11572#L284 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 11570#L256 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 11568#L273 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 11566#L274 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 11564#L288 assume eval_~tmp~0 != 0; 11562#L288-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 11559#L296 assume !(eval_~tmp_ndt_1~0 != 0); 11560#L293 assume ~t1_st~0 == 0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 11330#L310 assume !(eval_~tmp_ndt_2~0 != 0); 11580#L307 assume !(~t2_st~0 == 0); 11576#L321 [2018-11-10 01:03:49,720 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 01:03:49,720 INFO L82 PathProgramCache]: Analyzing trace with hash 1547564041, now seen corresponding path program 2 times [2018-11-10 01:03:49,720 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 01:03:49,721 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 01:03:49,721 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:49,721 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 01:03:49,722 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:49,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 01:03:49,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 01:03:49,734 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 01:03:49,735 INFO L82 PathProgramCache]: Analyzing trace with hash 275700557, now seen corresponding path program 2 times [2018-11-10 01:03:49,735 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 01:03:49,735 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 01:03:49,736 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:49,736 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 01:03:49,736 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:49,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 01:03:49,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 01:03:49,742 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 01:03:49,742 INFO L82 PathProgramCache]: Analyzing trace with hash 1333199701, now seen corresponding path program 1 times [2018-11-10 01:03:49,742 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 01:03:49,742 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 01:03:49,743 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:49,743 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 01:03:49,743 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:49,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 01:03:49,766 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 01:03:49,766 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 01:03:49,766 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 01:03:49,821 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 01:03:49,822 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 01:03:49,822 INFO L87 Difference]: Start difference. First operand 825 states and 1080 transitions. cyclomatic complexity: 258 Second operand 3 states. [2018-11-10 01:03:49,854 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 01:03:49,854 INFO L93 Difference]: Finished difference Result 980 states and 1271 transitions. [2018-11-10 01:03:49,855 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 01:03:49,855 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 980 states and 1271 transitions. [2018-11-10 01:03:49,858 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 861 [2018-11-10 01:03:49,861 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 980 states to 980 states and 1271 transitions. [2018-11-10 01:03:49,861 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 980 [2018-11-10 01:03:49,862 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 980 [2018-11-10 01:03:49,862 INFO L73 IsDeterministic]: Start isDeterministic. Operand 980 states and 1271 transitions. [2018-11-10 01:03:49,863 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 01:03:49,863 INFO L705 BuchiCegarLoop]: Abstraction has 980 states and 1271 transitions. [2018-11-10 01:03:49,864 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 980 states and 1271 transitions. [2018-11-10 01:03:49,872 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 980 to 960. [2018-11-10 01:03:49,872 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 960 states. [2018-11-10 01:03:49,874 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 960 states to 960 states and 1251 transitions. [2018-11-10 01:03:49,874 INFO L728 BuchiCegarLoop]: Abstraction has 960 states and 1251 transitions. [2018-11-10 01:03:49,874 INFO L608 BuchiCegarLoop]: Abstraction has 960 states and 1251 transitions. [2018-11-10 01:03:49,874 INFO L442 BuchiCegarLoop]: ======== Iteration 14============ [2018-11-10 01:03:49,874 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 960 states and 1251 transitions. [2018-11-10 01:03:49,878 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 841 [2018-11-10 01:03:49,878 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 01:03:49,878 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 01:03:49,878 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 01:03:49,878 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 01:03:49,879 INFO L793 eck$LassoCheckResult]: Stem: 12938#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 12781#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 12782#L518 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 12916#L226 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12917#L233 assume ~m_i~0 == 1;~m_st~0 := 0; 13052#L233-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 12980#L238-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 12981#L243-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12957#L346 assume !(~M_E~0 == 0); 12955#L346-2 assume !(~T1_E~0 == 0); 12783#L351-1 assume !(~T2_E~0 == 0); 12784#L356-1 assume !(~E_M~0 == 0); 12832#L361-1 assume !(~E_1~0 == 0); 12870#L366-1 assume !(~E_2~0 == 0); 13032#L371-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13018#L168 assume !(~m_pc~0 == 1); 12826#L168-2 is_master_triggered_~__retres1~0 := 0; 13008#L179 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12827#L180 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 12828#L427 assume !(activate_threads_~tmp~1 != 0); 12862#L427-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12863#L187 assume !(~t1_pc~0 == 1); 12927#L187-2 is_transmit1_triggered_~__retres1~1 := 0; 12930#L198 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12931#L199 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 12910#L435 assume !(activate_threads_~tmp___0~0 != 0); 12911#L435-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12918#L206 assume !(~t2_pc~0 == 1); 13050#L206-2 is_transmit2_triggered_~__retres1~2 := 0; 13051#L217 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12843#L218 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 12844#L443 assume !(activate_threads_~tmp___1~0 != 0); 13027#L443-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12824#L384 assume !(~M_E~0 == 1); 12785#L384-2 assume !(~T1_E~0 == 1); 12786#L389-1 assume !(~T2_E~0 == 1); 12831#L394-1 assume !(~E_M~0 == 1); 12864#L399-1 assume !(~E_1~0 == 1); 13028#L404-1 assume !(~E_2~0 == 1); 12958#L409-1 assume { :end_inline_reset_delta_events } true; 12959#L555-3 assume true; 13586#L555-1 assume !false; 13584#L556 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 13577#L321 [2018-11-10 01:03:49,879 INFO L795 eck$LassoCheckResult]: Loop: 13577#L321 assume true; 13573#L283-1 assume !false; 13569#L284 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 13537#L256 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~3 := 1; 13534#L273 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 13532#L274 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 13529#L288 assume eval_~tmp~0 != 0; 13527#L288-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 13517#L296 assume !(eval_~tmp_ndt_1~0 != 0); 12977#L293 assume ~t1_st~0 == 0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 12964#L310 assume !(eval_~tmp_ndt_2~0 != 0); 12965#L307 assume ~t2_st~0 == 0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 13582#L324 assume !(eval_~tmp_ndt_3~0 != 0); 13577#L321 [2018-11-10 01:03:49,879 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 01:03:49,879 INFO L82 PathProgramCache]: Analyzing trace with hash 1547564041, now seen corresponding path program 3 times [2018-11-10 01:03:49,879 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 01:03:49,879 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 01:03:49,880 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:49,880 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 01:03:49,880 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:49,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 01:03:49,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 01:03:49,892 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 01:03:49,892 INFO L82 PathProgramCache]: Analyzing trace with hash -43220106, now seen corresponding path program 1 times [2018-11-10 01:03:49,892 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 01:03:49,892 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 01:03:49,893 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:49,893 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 01:03:49,893 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:49,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 01:03:49,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 01:03:49,901 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 01:03:49,901 INFO L82 PathProgramCache]: Analyzing trace with hash -1620485010, now seen corresponding path program 1 times [2018-11-10 01:03:49,901 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 01:03:49,901 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 01:03:49,902 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:49,902 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 01:03:49,902 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 01:03:49,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 01:03:49,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 01:03:50,201 WARN L179 SmtUtils]: Spent 207.00 ms on a formula simplification. DAG size of input: 105 DAG size of output: 72 [2018-11-10 01:03:50,288 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 10.11 01:03:50 BoogieIcfgContainer [2018-11-10 01:03:50,289 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2018-11-10 01:03:50,289 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-10 01:03:50,289 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-10 01:03:50,289 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-10 01:03:50,290 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.11 01:03:47" (3/4) ... [2018-11-10 01:03:50,293 INFO L141 WitnessPrinter]: Generating witness for non-termination counterexample [2018-11-10 01:03:50,347 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_79c1851b-7519-4818-bc22-2690e43b7ac5/bin-2019/uautomizer/witness.graphml [2018-11-10 01:03:50,347 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-10 01:03:50,348 INFO L168 Benchmark]: Toolchain (without parser) took 4160.08 ms. Allocated memory was 1.0 GB in the beginning and 1.3 GB in the end (delta: 226.5 MB). Free memory was 960.2 MB in the beginning and 1.0 GB in the end (delta: -73.5 MB). Peak memory consumption was 153.0 MB. Max. memory is 11.5 GB. [2018-11-10 01:03:50,349 INFO L168 Benchmark]: CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 985.5 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-10 01:03:50,349 INFO L168 Benchmark]: CACSL2BoogieTranslator took 270.69 ms. Allocated memory is still 1.0 GB. Free memory was 960.2 MB in the beginning and 944.1 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. [2018-11-10 01:03:50,349 INFO L168 Benchmark]: Boogie Procedure Inliner took 41.50 ms. Allocated memory is still 1.0 GB. Free memory was 944.1 MB in the beginning and 941.4 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-11-10 01:03:50,350 INFO L168 Benchmark]: Boogie Preprocessor took 86.71 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 158.9 MB). Free memory was 941.4 MB in the beginning and 1.2 GB in the end (delta: -211.3 MB). Peak memory consumption was 15.8 MB. Max. memory is 11.5 GB. [2018-11-10 01:03:50,350 INFO L168 Benchmark]: RCFGBuilder took 747.04 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 57.1 MB). Peak memory consumption was 57.1 MB. Max. memory is 11.5 GB. [2018-11-10 01:03:50,350 INFO L168 Benchmark]: BuchiAutomizer took 2952.04 ms. Allocated memory was 1.2 GB in the beginning and 1.3 GB in the end (delta: 67.6 MB). Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 56.4 MB). Peak memory consumption was 124.1 MB. Max. memory is 11.5 GB. [2018-11-10 01:03:50,351 INFO L168 Benchmark]: Witness Printer took 58.16 ms. Allocated memory is still 1.3 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2018-11-10 01:03:50,352 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 985.5 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 270.69 ms. Allocated memory is still 1.0 GB. Free memory was 960.2 MB in the beginning and 944.1 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 41.50 ms. Allocated memory is still 1.0 GB. Free memory was 944.1 MB in the beginning and 941.4 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 86.71 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 158.9 MB). Free memory was 941.4 MB in the beginning and 1.2 GB in the end (delta: -211.3 MB). Peak memory consumption was 15.8 MB. Max. memory is 11.5 GB. * RCFGBuilder took 747.04 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 57.1 MB). Peak memory consumption was 57.1 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 2952.04 ms. Allocated memory was 1.2 GB in the beginning and 1.3 GB in the end (delta: 67.6 MB). Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 56.4 MB). Peak memory consumption was 124.1 MB. Max. memory is 11.5 GB. * Witness Printer took 58.16 ms. Allocated memory is still 1.3 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 13 terminating modules (13 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.13 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 960 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 2.8s and 14 iterations. TraceHistogramMax:1. Analysis of lassos took 1.6s. Construction of modules took 0.5s. Büchi inclusion checks took 0.3s. Highest rank in rank-based complementation 0. Minimization of det autom 13. Minimization of nondet autom 0. Automata minimization 0.1s AutomataMinimizationTime, 13 MinimizatonAttempts, 482 StatesRemovedByMinimization, 6 NontrivialMinimizations. Non-live state removal took 0.0s Buchi closure took 0.0s. Biggest automaton had 960 states and ocurred in iteration 13. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 4393 SDtfs, 4336 SDslu, 2783 SDs, 0 SdLazy, 204 SolverSat, 112 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.5s Time LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc2 concLT0 SILN1 SILU0 SILI6 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 283]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {\result=0, token=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3cdac8b1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@65c3e48e=0, tmp=1, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@77a0ecf=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@395de0f7=0, T2_E=2, kernel_st=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@24625af1=0, __retres1=0, tmp___0=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@30f30c3d=0, t2_st=0, t1_pc=0, E_2=2, __retres1=1, T1_E=2, \result=0, E_1=2, tmp_ndt_1=0, M_E=2, tmp_ndt_2=0, tmp=0, tmp_ndt_3=0, __retres1=0, t2_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6e2a56f2=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@26222644=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@63dae31e=0, t1_st=0, \result=0, t2_pc=0, local=0, m_st=0, tmp___1=0, E_M=2, tmp___0=0, tmp=0, __retres1=0, t1_i=1, m_pc=0, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 283]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int m_st ; [L18] int t1_st ; [L19] int t2_st ; [L20] int m_i ; [L21] int t1_i ; [L22] int t2_i ; [L23] int M_E = 2; [L24] int T1_E = 2; [L25] int T2_E = 2; [L26] int E_M = 2; [L27] int E_1 = 2; [L28] int E_2 = 2; [L33] int token ; [L35] int local ; [L600] int __retres1 ; [L604] CALL init_model() [L514] m_i = 1 [L515] t1_i = 1 [L516] RET t2_i = 1 [L604] init_model() [L605] CALL start_simulation() [L541] int kernel_st ; [L542] int tmp ; [L543] int tmp___0 ; [L547] kernel_st = 0 [L548] FCALL update_channels() [L549] CALL init_threads() [L233] COND TRUE m_i == 1 [L234] m_st = 0 [L238] COND TRUE t1_i == 1 [L239] t1_st = 0 [L243] COND TRUE t2_i == 1 [L244] RET t2_st = 0 [L549] init_threads() [L550] CALL fire_delta_events() [L346] COND FALSE !(M_E == 0) [L351] COND FALSE !(T1_E == 0) [L356] COND FALSE !(T2_E == 0) [L361] COND FALSE !(E_M == 0) [L366] COND FALSE !(E_1 == 0) [L371] COND FALSE, RET !(E_2 == 0) [L550] fire_delta_events() [L551] CALL activate_threads() [L419] int tmp ; [L420] int tmp___0 ; [L421] int tmp___1 ; [L425] CALL, EXPR is_master_triggered() [L165] int __retres1 ; [L168] COND FALSE !(m_pc == 1) [L178] __retres1 = 0 [L180] RET return (__retres1); [L425] EXPR is_master_triggered() [L425] tmp = is_master_triggered() [L427] COND FALSE !(\read(tmp)) [L433] CALL, EXPR is_transmit1_triggered() [L184] int __retres1 ; [L187] COND FALSE !(t1_pc == 1) [L197] __retres1 = 0 [L199] RET return (__retres1); [L433] EXPR is_transmit1_triggered() [L433] tmp___0 = is_transmit1_triggered() [L435] COND FALSE !(\read(tmp___0)) [L441] CALL, EXPR is_transmit2_triggered() [L203] int __retres1 ; [L206] COND FALSE !(t2_pc == 1) [L216] __retres1 = 0 [L218] RET return (__retres1); [L441] EXPR is_transmit2_triggered() [L441] tmp___1 = is_transmit2_triggered() [L443] COND FALSE, RET !(\read(tmp___1)) [L551] activate_threads() [L552] CALL reset_delta_events() [L384] COND FALSE !(M_E == 1) [L389] COND FALSE !(T1_E == 1) [L394] COND FALSE !(T2_E == 1) [L399] COND FALSE !(E_M == 1) [L404] COND FALSE !(E_1 == 1) [L409] COND FALSE, RET !(E_2 == 1) [L552] reset_delta_events() [L555] COND TRUE 1 [L558] kernel_st = 1 [L559] CALL eval() [L279] int tmp ; Loop: [L283] COND TRUE 1 [L286] CALL, EXPR exists_runnable_thread() [L253] int __retres1 ; [L256] COND TRUE m_st == 0 [L257] __retres1 = 1 [L274] RET return (__retres1); [L286] EXPR exists_runnable_thread() [L286] tmp = exists_runnable_thread() [L288] COND TRUE \read(tmp) [L293] COND TRUE m_st == 0 [L294] int tmp_ndt_1; [L295] tmp_ndt_1 = __VERIFIER_nondet_int() [L296] COND FALSE !(\read(tmp_ndt_1)) [L307] COND TRUE t1_st == 0 [L308] int tmp_ndt_2; [L309] tmp_ndt_2 = __VERIFIER_nondet_int() [L310] COND FALSE !(\read(tmp_ndt_2)) [L321] COND TRUE t2_st == 0 [L322] int tmp_ndt_3; [L323] tmp_ndt_3 = __VERIFIER_nondet_int() [L324] COND FALSE !(\read(tmp_ndt_3)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...