./Ultimate.py --spec ../../sv-benchmarks/c/Termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.04_true-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 1dbac8bc Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_49fa53c9-7f6f-4c3d-8e2d-784bb3e03274/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_49fa53c9-7f6f-4c3d-8e2d-784bb3e03274/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_49fa53c9-7f6f-4c3d-8e2d-784bb3e03274/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_49fa53c9-7f6f-4c3d-8e2d-784bb3e03274/bin-2019/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.04_true-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_49fa53c9-7f6f-4c3d-8e2d-784bb3e03274/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_49fa53c9-7f6f-4c3d-8e2d-784bb3e03274/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 0d93d749d4c7ad15cc29deef6885966e95a2d557 ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.23-1dbac8b [2018-11-10 06:55:27,621 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-10 06:55:27,622 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-10 06:55:27,629 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-10 06:55:27,629 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-10 06:55:27,630 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-10 06:55:27,631 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-10 06:55:27,632 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-10 06:55:27,633 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-10 06:55:27,634 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-10 06:55:27,635 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-10 06:55:27,635 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-10 06:55:27,636 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-10 06:55:27,636 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-10 06:55:27,638 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-10 06:55:27,638 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-10 06:55:27,639 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-10 06:55:27,640 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-10 06:55:27,642 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-10 06:55:27,644 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-10 06:55:27,644 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-10 06:55:27,645 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-10 06:55:27,647 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-10 06:55:27,648 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-10 06:55:27,648 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-10 06:55:27,649 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-10 06:55:27,649 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-10 06:55:27,650 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-10 06:55:27,651 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-10 06:55:27,652 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-10 06:55:27,652 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-10 06:55:27,652 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-10 06:55:27,653 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-10 06:55:27,653 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-10 06:55:27,653 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-10 06:55:27,654 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-10 06:55:27,655 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_49fa53c9-7f6f-4c3d-8e2d-784bb3e03274/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2018-11-10 06:55:27,666 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-10 06:55:27,666 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-10 06:55:27,667 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-10 06:55:27,667 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-10 06:55:27,667 INFO L133 SettingsManager]: * Use SBE=true [2018-11-10 06:55:27,667 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2018-11-10 06:55:27,668 INFO L133 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2018-11-10 06:55:27,668 INFO L133 SettingsManager]: * Use old map elimination=false [2018-11-10 06:55:27,668 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false [2018-11-10 06:55:27,668 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true [2018-11-10 06:55:27,668 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2018-11-10 06:55:27,668 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-10 06:55:27,668 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-10 06:55:27,668 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-10 06:55:27,668 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-10 06:55:27,668 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-10 06:55:27,669 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-10 06:55:27,669 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2018-11-10 06:55:27,669 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2018-11-10 06:55:27,669 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2018-11-10 06:55:27,669 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-10 06:55:27,669 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-10 06:55:27,669 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false [2018-11-10 06:55:27,670 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2018-11-10 06:55:27,670 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-10 06:55:27,671 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-10 06:55:27,671 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2018-11-10 06:55:27,671 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-10 06:55:27,672 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-10 06:55:27,672 INFO L133 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2018-11-10 06:55:27,672 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-11-10 06:55:27,672 INFO L133 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_49fa53c9-7f6f-4c3d-8e2d-784bb3e03274/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 0d93d749d4c7ad15cc29deef6885966e95a2d557 [2018-11-10 06:55:27,697 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-10 06:55:27,705 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-10 06:55:27,707 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-10 06:55:27,708 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-10 06:55:27,709 INFO L276 PluginConnector]: CDTParser initialized [2018-11-10 06:55:27,709 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_49fa53c9-7f6f-4c3d-8e2d-784bb3e03274/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/token_ring.04_true-unreach-call_false-termination.cil.c [2018-11-10 06:55:27,748 INFO L218 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_49fa53c9-7f6f-4c3d-8e2d-784bb3e03274/bin-2019/uautomizer/data/14655c7ef/761e181e13f8412f8b3afad02cac79db/FLAG6d337b92e [2018-11-10 06:55:28,106 INFO L298 CDTParser]: Found 1 translation units. [2018-11-10 06:55:28,107 INFO L158 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_49fa53c9-7f6f-4c3d-8e2d-784bb3e03274/sv-benchmarks/c/systemc/token_ring.04_true-unreach-call_false-termination.cil.c [2018-11-10 06:55:28,117 INFO L346 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_49fa53c9-7f6f-4c3d-8e2d-784bb3e03274/bin-2019/uautomizer/data/14655c7ef/761e181e13f8412f8b3afad02cac79db/FLAG6d337b92e [2018-11-10 06:55:28,129 INFO L354 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_49fa53c9-7f6f-4c3d-8e2d-784bb3e03274/bin-2019/uautomizer/data/14655c7ef/761e181e13f8412f8b3afad02cac79db [2018-11-10 06:55:28,132 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-10 06:55:28,134 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-10 06:55:28,134 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-10 06:55:28,135 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-10 06:55:28,138 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-10 06:55:28,138 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.11 06:55:28" (1/1) ... [2018-11-10 06:55:28,140 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@f1788b0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 06:55:28, skipping insertion in model container [2018-11-10 06:55:28,141 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.11 06:55:28" (1/1) ... [2018-11-10 06:55:28,150 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-10 06:55:28,179 INFO L174 MainTranslator]: Built tables and reachable declarations [2018-11-10 06:55:28,318 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-11-10 06:55:28,322 INFO L189 MainTranslator]: Completed pre-run [2018-11-10 06:55:28,359 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-11-10 06:55:28,374 INFO L193 MainTranslator]: Completed translation [2018-11-10 06:55:28,374 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 06:55:28 WrapperNode [2018-11-10 06:55:28,374 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-10 06:55:28,375 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-10 06:55:28,375 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-10 06:55:28,375 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-10 06:55:28,380 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 06:55:28" (1/1) ... [2018-11-10 06:55:28,386 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 06:55:28" (1/1) ... [2018-11-10 06:55:28,418 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-10 06:55:28,419 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-10 06:55:28,419 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-10 06:55:28,419 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-10 06:55:28,474 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 06:55:28" (1/1) ... [2018-11-10 06:55:28,474 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 06:55:28" (1/1) ... [2018-11-10 06:55:28,478 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 06:55:28" (1/1) ... [2018-11-10 06:55:28,478 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 06:55:28" (1/1) ... [2018-11-10 06:55:28,486 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 06:55:28" (1/1) ... [2018-11-10 06:55:28,499 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 06:55:28" (1/1) ... [2018-11-10 06:55:28,501 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 06:55:28" (1/1) ... [2018-11-10 06:55:28,506 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-10 06:55:28,506 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-10 06:55:28,506 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-10 06:55:28,506 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-10 06:55:28,507 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 06:55:28" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_49fa53c9-7f6f-4c3d-8e2d-784bb3e03274/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-10 06:55:28,568 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-10 06:55:28,568 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-10 06:55:29,382 INFO L341 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-10 06:55:29,383 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.11 06:55:29 BoogieIcfgContainer [2018-11-10 06:55:29,383 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-10 06:55:29,383 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2018-11-10 06:55:29,383 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2018-11-10 06:55:29,386 INFO L276 PluginConnector]: BuchiAutomizer initialized [2018-11-10 06:55:29,387 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-10 06:55:29,387 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 10.11 06:55:28" (1/3) ... [2018-11-10 06:55:29,387 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5cb6ff1c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 10.11 06:55:29, skipping insertion in model container [2018-11-10 06:55:29,388 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-10 06:55:29,388 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 06:55:28" (2/3) ... [2018-11-10 06:55:29,388 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5cb6ff1c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 10.11 06:55:29, skipping insertion in model container [2018-11-10 06:55:29,388 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-10 06:55:29,388 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.11 06:55:29" (3/3) ... [2018-11-10 06:55:29,390 INFO L375 chiAutomizerObserver]: Analyzing ICFG token_ring.04_true-unreach-call_false-termination.cil.c [2018-11-10 06:55:29,425 INFO L135 ementStrategyFactory]: Using default assertion order modulation [2018-11-10 06:55:29,426 INFO L374 BuchiCegarLoop]: Interprodecural is true [2018-11-10 06:55:29,426 INFO L375 BuchiCegarLoop]: Hoare is false [2018-11-10 06:55:29,426 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2018-11-10 06:55:29,426 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-10 06:55:29,426 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-10 06:55:29,426 INFO L379 BuchiCegarLoop]: Difference is false [2018-11-10 06:55:29,426 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-10 06:55:29,427 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2018-11-10 06:55:29,447 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 438 states. [2018-11-10 06:55:29,478 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 367 [2018-11-10 06:55:29,479 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:55:29,479 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:55:29,486 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:29,487 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:29,487 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ [2018-11-10 06:55:29,487 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 438 states. [2018-11-10 06:55:29,493 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 367 [2018-11-10 06:55:29,493 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:55:29,493 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:55:29,494 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:29,495 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:29,501 INFO L793 eck$LassoCheckResult]: Stem: 287#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 186#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 438#L756true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 60#L336true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 91#L343true assume !(~m_i~0 == 1);~m_st~0 := 2; 95#L343-2true assume ~t1_i~0 == 1;~t1_st~0 := 0; 350#L348-1true assume !(~t2_i~0 == 1);~t2_st~0 := 2; 127#L353-1true assume !(~t3_i~0 == 1);~t3_st~0 := 2; 62#L358-1true assume !(~t4_i~0 == 1);~t4_st~0 := 2; 316#L363-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 373#L504true assume !(~M_E~0 == 0); 376#L504-2true assume ~T1_E~0 == 0;~T1_E~0 := 1; 162#L509-1true assume !(~T2_E~0 == 0); 432#L514-1true assume !(~T3_E~0 == 0); 101#L519-1true assume !(~T4_E~0 == 0); 358#L524-1true assume !(~E_M~0 == 0); 132#L529-1true assume !(~E_1~0 == 0); 67#L534-1true assume !(~E_2~0 == 0); 322#L539-1true assume !(~E_3~0 == 0); 12#L544-1true assume ~E_4~0 == 0;~E_4~0 := 1; 202#L549-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 236#L240true assume ~m_pc~0 == 1; 181#L241true assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 238#L251true is_master_triggered_#res := is_master_triggered_~__retres1~0; 183#L252true activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 318#L627true assume !(activate_threads_~tmp~1 != 0); 319#L627-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 61#L259true assume !(~t1_pc~0 == 1); 51#L259-2true is_transmit1_triggered_~__retres1~1 := 0; 63#L270true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 332#L271true activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 440#L635true assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 428#L635-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 159#L278true assume ~t2_pc~0 == 1; 31#L279true assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 160#L289true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 32#L290true activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 4#L643true assume !(activate_threads_~tmp___1~0 != 0); 7#L643-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 284#L297true assume !(~t3_pc~0 == 1); 282#L297-2true is_transmit3_triggered_~__retres1~3 := 0; 286#L308true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 128#L309true activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 105#L651true assume !(activate_threads_~tmp___2~0 != 0); 97#L651-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 422#L316true assume ~t4_pc~0 == 1; 250#L317true assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 421#L327true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 248#L328true activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 216#L659true assume !(activate_threads_~tmp___3~0 != 0); 218#L659-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 131#L562true assume !(~M_E~0 == 1); 133#L562-2true assume !(~T1_E~0 == 1); 66#L567-1true assume !(~T2_E~0 == 1); 320#L572-1true assume !(~T3_E~0 == 1); 9#L577-1true assume !(~T4_E~0 == 1); 220#L582-1true assume !(~E_M~0 == 1); 37#L587-1true assume ~E_1~0 == 1;~E_1~0 := 2; 384#L592-1true assume !(~E_2~0 == 1); 156#L597-1true assume !(~E_3~0 == 1); 429#L602-1true assume !(~E_4~0 == 1); 98#L607-1true assume { :end_inline_reset_delta_events } true; 267#L793-3true [2018-11-10 06:55:29,502 INFO L795 eck$LassoCheckResult]: Loop: 267#L793-3true assume true; 265#L793-1true assume !false; 106#L794true start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 68#L479true assume !true; 203#L494true assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 65#L336-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 377#L504-3true assume !(~M_E~0 == 0); 246#L504-5true assume ~T1_E~0 == 0;~T1_E~0 := 1; 165#L509-3true assume ~T2_E~0 == 0;~T2_E~0 := 1; 437#L514-3true assume ~T3_E~0 == 0;~T3_E~0 := 1; 87#L519-3true assume ~T4_E~0 == 0;~T4_E~0 := 1; 334#L524-3true assume ~E_M~0 == 0;~E_M~0 := 1; 124#L529-3true assume ~E_1~0 == 0;~E_1~0 := 1; 47#L534-3true assume ~E_2~0 == 0;~E_2~0 := 1; 311#L539-3true assume !(~E_3~0 == 0); 82#L544-3true assume ~E_4~0 == 0;~E_4~0 := 1; 208#L549-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 212#L240-18true assume !(~m_pc~0 == 1); 209#L240-20true is_master_triggered_~__retres1~0 := 0; 245#L251-6true is_master_triggered_#res := is_master_triggered_~__retres1~0; 193#L252-6true activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 283#L627-18true assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 285#L627-20true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 356#L259-18true assume !(~t1_pc~0 == 1); 355#L259-20true is_transmit1_triggered_~__retres1~1 := 0; 367#L270-6true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 330#L271-6true activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 395#L635-18true assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 397#L635-20true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 42#L278-18true assume ~t2_pc~0 == 1; 16#L279-6true assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 137#L289-6true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 17#L290-6true activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 75#L643-18true assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 76#L643-20true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 273#L297-18true assume ~t3_pc~0 == 1; 122#L298-6true assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 278#L308-6true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 123#L309-6true activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 169#L651-18true assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 170#L651-20true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 391#L316-18true assume ~t4_pc~0 == 1; 241#L317-6true assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 408#L327-6true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 240#L328-6true activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 184#L659-18true assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 185#L659-20true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 134#L562-3true assume ~M_E~0 == 1;~M_E~0 := 2; 125#L562-5true assume ~T1_E~0 == 1;~T1_E~0 := 2; 44#L567-3true assume ~T2_E~0 == 1;~T2_E~0 := 2; 307#L572-3true assume ~T3_E~0 == 1;~T3_E~0 := 2; 81#L577-3true assume ~T4_E~0 == 1;~T4_E~0 := 2; 205#L582-3true assume !(~E_M~0 == 1); 28#L587-3true assume ~E_1~0 == 1;~E_1~0 := 2; 374#L592-3true assume ~E_2~0 == 1;~E_2~0 := 2; 161#L597-3true assume ~E_3~0 == 1;~E_3~0 := 2; 431#L602-3true assume ~E_4~0 == 1;~E_4~0 := 2; 100#L607-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 92#L376-1true assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 342#L403-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 417#L404-1true start_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 388#L812true assume !(start_simulation_~tmp~3 == 0); 392#L812-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret12, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 93#L376-2true assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 347#L403-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 420#L404-2true stop_simulation_#t~ret12 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret12;havoc stop_simulation_#t~ret12; 331#L767true assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 41#L774true stop_simulation_#res := stop_simulation_~__retres2~0; 13#L775true start_simulation_#t~ret14 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 323#L825true assume !(start_simulation_~tmp___0~1 != 0); 267#L793-3true [2018-11-10 06:55:29,507 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:29,508 INFO L82 PathProgramCache]: Analyzing trace with hash 1553035642, now seen corresponding path program 1 times [2018-11-10 06:55:29,509 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:29,510 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:29,547 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:29,547 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:55:29,547 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:29,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:55:29,613 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:55:29,615 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:55:29,616 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:55:29,619 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 06:55:29,619 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:29,619 INFO L82 PathProgramCache]: Analyzing trace with hash -1090307619, now seen corresponding path program 1 times [2018-11-10 06:55:29,619 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:29,620 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:29,620 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:29,620 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:55:29,620 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:29,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:55:29,636 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:55:29,636 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:55:29,636 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 06:55:29,638 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 06:55:29,652 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 06:55:29,653 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 06:55:29,654 INFO L87 Difference]: Start difference. First operand 438 states. Second operand 3 states. [2018-11-10 06:55:29,681 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:55:29,681 INFO L93 Difference]: Finished difference Result 437 states and 649 transitions. [2018-11-10 06:55:29,682 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 06:55:29,683 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 437 states and 649 transitions. [2018-11-10 06:55:29,688 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 365 [2018-11-10 06:55:29,695 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 437 states to 432 states and 644 transitions. [2018-11-10 06:55:29,696 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 432 [2018-11-10 06:55:29,698 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 432 [2018-11-10 06:55:29,698 INFO L73 IsDeterministic]: Start isDeterministic. Operand 432 states and 644 transitions. [2018-11-10 06:55:29,700 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:55:29,701 INFO L705 BuchiCegarLoop]: Abstraction has 432 states and 644 transitions. [2018-11-10 06:55:29,714 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 432 states and 644 transitions. [2018-11-10 06:55:29,736 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 432 to 432. [2018-11-10 06:55:29,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 432 states. [2018-11-10 06:55:29,738 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 432 states to 432 states and 644 transitions. [2018-11-10 06:55:29,739 INFO L728 BuchiCegarLoop]: Abstraction has 432 states and 644 transitions. [2018-11-10 06:55:29,739 INFO L608 BuchiCegarLoop]: Abstraction has 432 states and 644 transitions. [2018-11-10 06:55:29,740 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ [2018-11-10 06:55:29,740 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 432 states and 644 transitions. [2018-11-10 06:55:29,741 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 365 [2018-11-10 06:55:29,742 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:55:29,742 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:55:29,743 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:29,744 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:29,744 INFO L793 eck$LassoCheckResult]: Stem: 1255#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 1164#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1165#L756 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 991#L336 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 992#L343 assume ~m_i~0 == 1;~m_st~0 := 0; 1037#L343-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 1041#L348-1 assume !(~t2_i~0 == 1);~t2_st~0 := 2; 1098#L353-1 assume !(~t3_i~0 == 1);~t3_st~0 := 2; 995#L358-1 assume !(~t4_i~0 == 1);~t4_st~0 := 2; 996#L363-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1270#L504 assume !(~M_E~0 == 0); 1304#L504-2 assume ~T1_E~0 == 0;~T1_E~0 := 1; 1125#L509-1 assume !(~T2_E~0 == 0); 1126#L514-1 assume !(~T3_E~0 == 0); 1051#L519-1 assume !(~T4_E~0 == 0); 1052#L524-1 assume !(~E_M~0 == 0); 1105#L529-1 assume !(~E_1~0 == 0); 1005#L534-1 assume !(~E_2~0 == 0); 1006#L539-1 assume !(~E_3~0 == 0); 901#L544-1 assume ~E_4~0 == 0;~E_4~0 := 1; 902#L549-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1194#L240 assume ~m_pc~0 == 1; 1157#L241 assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 1158#L251 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1160#L252 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1161#L627 assume !(activate_threads_~tmp~1 != 0); 1271#L627-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 993#L259 assume !(~t1_pc~0 == 1); 974#L259-2 is_transmit1_triggered_~__retres1~1 := 0; 975#L270 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 997#L271 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1285#L635 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 1314#L635-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1122#L278 assume ~t2_pc~0 == 1; 945#L279 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 946#L289 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 948#L290 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 886#L643 assume !(activate_threads_~tmp___1~0 != 0); 887#L643-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 892#L297 assume !(~t3_pc~0 == 1); 1101#L297-2 is_transmit3_triggered_~__retres1~3 := 0; 1102#L308 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1099#L309 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1057#L651 assume !(activate_threads_~tmp___2~0 != 0); 1044#L651-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1045#L316 assume ~t4_pc~0 == 1; 1229#L317 assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 1230#L327 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1228#L328 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1203#L659 assume !(activate_threads_~tmp___3~0 != 0); 1204#L659-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1103#L562 assume !(~M_E~0 == 1); 1104#L562-2 assume !(~T1_E~0 == 1); 1003#L567-1 assume !(~T2_E~0 == 1); 1004#L572-1 assume !(~T3_E~0 == 1); 895#L577-1 assume !(~T4_E~0 == 1); 896#L582-1 assume !(~E_M~0 == 1); 952#L587-1 assume ~E_1~0 == 1;~E_1~0 := 2; 953#L592-1 assume !(~E_2~0 == 1); 1120#L597-1 assume !(~E_3~0 == 1); 1121#L602-1 assume !(~E_4~0 == 1); 1046#L607-1 assume { :end_inline_reset_delta_events } true; 1047#L793-3 [2018-11-10 06:55:29,745 INFO L795 eck$LassoCheckResult]: Loop: 1047#L793-3 assume true; 1246#L793-1 assume !false; 1058#L794 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 1007#L479 assume true; 980#L413-1 assume !false; 981#L414 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1034#L376 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 983#L403 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1291#L404 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 1266#L418 assume !(eval_~tmp~0 != 0); 1195#L494 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 1001#L336-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 1002#L504-3 assume !(~M_E~0 == 0); 1225#L504-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 1130#L509-3 assume ~T2_E~0 == 0;~T2_E~0 := 1; 1131#L514-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 1030#L519-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 1031#L524-3 assume ~E_M~0 == 0;~E_M~0 := 1; 1096#L529-3 assume ~E_1~0 == 0;~E_1~0 := 1; 965#L534-3 assume ~E_2~0 == 0;~E_2~0 := 1; 966#L539-3 assume !(~E_3~0 == 0); 1023#L544-3 assume ~E_4~0 == 0;~E_4~0 := 1; 1024#L549-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1199#L240-18 assume ~m_pc~0 == 1; 1171#L241-6 assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 1172#L251-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1175#L252-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1176#L627-18 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 1253#L627-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1254#L259-18 assume !(~t1_pc~0 == 1); 1281#L259-20 is_transmit1_triggered_~__retres1~1 := 0; 1280#L270-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1282#L271-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1283#L635-18 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 1309#L635-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 956#L278-18 assume ~t2_pc~0 == 1; 910#L279-6 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 912#L289-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 913#L290-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 914#L643-18 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 1014#L643-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1015#L297-18 assume ~t3_pc~0 == 1; 1091#L298-6 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 1092#L308-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1094#L309-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1095#L651-18 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 1138#L651-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1139#L316-18 assume ~t4_pc~0 == 1; 1217#L317-6 assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 1218#L327-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1216#L328-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1162#L659-18 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 1163#L659-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1106#L562-3 assume ~M_E~0 == 1;~M_E~0 := 2; 1097#L562-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 960#L567-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 961#L572-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 1021#L577-3 assume ~T4_E~0 == 1;~T4_E~0 := 2; 1022#L582-3 assume !(~E_M~0 == 1); 939#L587-3 assume ~E_1~0 == 1;~E_1~0 := 2; 940#L592-3 assume ~E_2~0 == 1;~E_2~0 := 2; 1123#L597-3 assume ~E_3~0 == 1;~E_3~0 := 2; 1124#L602-3 assume ~E_4~0 == 1;~E_4~0 := 2; 1050#L607-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1038#L376-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 989#L403-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1297#L404-1 start_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 1306#L812 assume !(start_simulation_~tmp~3 == 0); 1272#L812-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret12, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1039#L376-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 999#L403-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1301#L404-2 stop_simulation_#t~ret12 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret12;havoc stop_simulation_#t~ret12; 1284#L767 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 955#L774 stop_simulation_#res := stop_simulation_~__retres2~0; 903#L775 start_simulation_#t~ret14 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 904#L825 assume !(start_simulation_~tmp___0~1 != 0); 1047#L793-3 [2018-11-10 06:55:29,745 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:29,745 INFO L82 PathProgramCache]: Analyzing trace with hash 1119306556, now seen corresponding path program 1 times [2018-11-10 06:55:29,745 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:29,745 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:29,750 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:29,750 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:55:29,751 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:29,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:55:29,781 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:55:29,781 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:55:29,781 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:55:29,782 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 06:55:29,782 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:29,782 INFO L82 PathProgramCache]: Analyzing trace with hash 672629802, now seen corresponding path program 1 times [2018-11-10 06:55:29,782 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:29,782 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:29,783 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:29,783 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:55:29,783 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:29,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:55:29,834 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:55:29,834 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:55:29,834 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:55:29,834 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 06:55:29,835 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 06:55:29,835 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 06:55:29,835 INFO L87 Difference]: Start difference. First operand 432 states and 644 transitions. cyclomatic complexity: 213 Second operand 3 states. [2018-11-10 06:55:29,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:55:29,849 INFO L93 Difference]: Finished difference Result 432 states and 643 transitions. [2018-11-10 06:55:29,854 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 06:55:29,855 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 432 states and 643 transitions. [2018-11-10 06:55:29,858 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 365 [2018-11-10 06:55:29,861 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 432 states to 432 states and 643 transitions. [2018-11-10 06:55:29,861 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 432 [2018-11-10 06:55:29,862 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 432 [2018-11-10 06:55:29,862 INFO L73 IsDeterministic]: Start isDeterministic. Operand 432 states and 643 transitions. [2018-11-10 06:55:29,864 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:55:29,864 INFO L705 BuchiCegarLoop]: Abstraction has 432 states and 643 transitions. [2018-11-10 06:55:29,865 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 432 states and 643 transitions. [2018-11-10 06:55:29,875 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 432 to 432. [2018-11-10 06:55:29,875 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 432 states. [2018-11-10 06:55:29,876 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 432 states to 432 states and 643 transitions. [2018-11-10 06:55:29,877 INFO L728 BuchiCegarLoop]: Abstraction has 432 states and 643 transitions. [2018-11-10 06:55:29,877 INFO L608 BuchiCegarLoop]: Abstraction has 432 states and 643 transitions. [2018-11-10 06:55:29,877 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ [2018-11-10 06:55:29,877 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 432 states and 643 transitions. [2018-11-10 06:55:29,881 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 365 [2018-11-10 06:55:29,881 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:55:29,881 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:55:29,883 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:29,883 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:29,883 INFO L793 eck$LassoCheckResult]: Stem: 2126#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 2035#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2036#L756 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 1862#L336 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1863#L343 assume ~m_i~0 == 1;~m_st~0 := 0; 1908#L343-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 1912#L348-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 1969#L353-1 assume !(~t3_i~0 == 1);~t3_st~0 := 2; 1866#L358-1 assume !(~t4_i~0 == 1);~t4_st~0 := 2; 1867#L363-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2141#L504 assume !(~M_E~0 == 0); 2175#L504-2 assume ~T1_E~0 == 0;~T1_E~0 := 1; 1996#L509-1 assume !(~T2_E~0 == 0); 1997#L514-1 assume !(~T3_E~0 == 0); 1922#L519-1 assume !(~T4_E~0 == 0); 1923#L524-1 assume !(~E_M~0 == 0); 1976#L529-1 assume !(~E_1~0 == 0); 1876#L534-1 assume !(~E_2~0 == 0); 1877#L539-1 assume !(~E_3~0 == 0); 1772#L544-1 assume ~E_4~0 == 0;~E_4~0 := 1; 1773#L549-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2065#L240 assume ~m_pc~0 == 1; 2028#L241 assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 2029#L251 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2031#L252 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2032#L627 assume !(activate_threads_~tmp~1 != 0); 2142#L627-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1864#L259 assume !(~t1_pc~0 == 1); 1845#L259-2 is_transmit1_triggered_~__retres1~1 := 0; 1846#L270 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1868#L271 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2156#L635 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 2185#L635-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1993#L278 assume ~t2_pc~0 == 1; 1816#L279 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 1817#L289 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1819#L290 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1757#L643 assume !(activate_threads_~tmp___1~0 != 0); 1758#L643-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1763#L297 assume !(~t3_pc~0 == 1); 1972#L297-2 is_transmit3_triggered_~__retres1~3 := 0; 1973#L308 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1970#L309 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1928#L651 assume !(activate_threads_~tmp___2~0 != 0); 1915#L651-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1916#L316 assume ~t4_pc~0 == 1; 2100#L317 assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 2101#L327 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2099#L328 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2074#L659 assume !(activate_threads_~tmp___3~0 != 0); 2075#L659-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1974#L562 assume !(~M_E~0 == 1); 1975#L562-2 assume !(~T1_E~0 == 1); 1874#L567-1 assume !(~T2_E~0 == 1); 1875#L572-1 assume !(~T3_E~0 == 1); 1766#L577-1 assume !(~T4_E~0 == 1); 1767#L582-1 assume !(~E_M~0 == 1); 1823#L587-1 assume ~E_1~0 == 1;~E_1~0 := 2; 1824#L592-1 assume !(~E_2~0 == 1); 1991#L597-1 assume !(~E_3~0 == 1); 1992#L602-1 assume !(~E_4~0 == 1); 1917#L607-1 assume { :end_inline_reset_delta_events } true; 1918#L793-3 [2018-11-10 06:55:29,884 INFO L795 eck$LassoCheckResult]: Loop: 1918#L793-3 assume true; 2117#L793-1 assume !false; 1929#L794 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 1878#L479 assume true; 1851#L413-1 assume !false; 1852#L414 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1905#L376 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 1854#L403 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2162#L404 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 2137#L418 assume !(eval_~tmp~0 != 0); 2066#L494 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 1872#L336-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 1873#L504-3 assume !(~M_E~0 == 0); 2096#L504-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 2001#L509-3 assume ~T2_E~0 == 0;~T2_E~0 := 1; 2002#L514-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 1901#L519-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 1902#L524-3 assume ~E_M~0 == 0;~E_M~0 := 1; 1967#L529-3 assume ~E_1~0 == 0;~E_1~0 := 1; 1836#L534-3 assume ~E_2~0 == 0;~E_2~0 := 1; 1837#L539-3 assume !(~E_3~0 == 0); 1894#L544-3 assume ~E_4~0 == 0;~E_4~0 := 1; 1895#L549-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2070#L240-18 assume ~m_pc~0 == 1; 2042#L241-6 assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 2043#L251-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2046#L252-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2047#L627-18 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 2124#L627-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2125#L259-18 assume ~t1_pc~0 == 1; 2150#L260-6 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 2151#L270-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2153#L271-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2154#L635-18 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 2180#L635-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1827#L278-18 assume ~t2_pc~0 == 1; 1781#L279-6 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 1783#L289-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1784#L290-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1785#L643-18 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 1885#L643-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1886#L297-18 assume ~t3_pc~0 == 1; 1962#L298-6 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 1963#L308-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1965#L309-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1966#L651-18 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 2009#L651-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2010#L316-18 assume ~t4_pc~0 == 1; 2088#L317-6 assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 2089#L327-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2087#L328-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2033#L659-18 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 2034#L659-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1977#L562-3 assume ~M_E~0 == 1;~M_E~0 := 2; 1968#L562-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 1831#L567-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 1832#L572-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 1892#L577-3 assume ~T4_E~0 == 1;~T4_E~0 := 2; 1893#L582-3 assume !(~E_M~0 == 1); 1810#L587-3 assume ~E_1~0 == 1;~E_1~0 := 2; 1811#L592-3 assume ~E_2~0 == 1;~E_2~0 := 2; 1994#L597-3 assume ~E_3~0 == 1;~E_3~0 := 2; 1995#L602-3 assume ~E_4~0 == 1;~E_4~0 := 2; 1921#L607-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1909#L376-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 1860#L403-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2168#L404-1 start_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 2177#L812 assume !(start_simulation_~tmp~3 == 0); 2143#L812-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret12, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1910#L376-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 1870#L403-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2172#L404-2 stop_simulation_#t~ret12 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret12;havoc stop_simulation_#t~ret12; 2155#L767 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 1826#L774 stop_simulation_#res := stop_simulation_~__retres2~0; 1774#L775 start_simulation_#t~ret14 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 1775#L825 assume !(start_simulation_~tmp___0~1 != 0); 1918#L793-3 [2018-11-10 06:55:29,884 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:29,884 INFO L82 PathProgramCache]: Analyzing trace with hash 1078631806, now seen corresponding path program 1 times [2018-11-10 06:55:29,884 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:29,885 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:29,885 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:29,885 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:55:29,890 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:29,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:55:29,918 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:55:29,918 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:55:29,918 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:55:29,918 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 06:55:29,918 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:29,919 INFO L82 PathProgramCache]: Analyzing trace with hash -1728895319, now seen corresponding path program 1 times [2018-11-10 06:55:29,919 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:29,919 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:29,919 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:29,919 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:55:29,920 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:29,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:55:29,970 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:55:29,971 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:55:29,971 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:55:29,971 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 06:55:29,972 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 06:55:29,972 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 06:55:29,972 INFO L87 Difference]: Start difference. First operand 432 states and 643 transitions. cyclomatic complexity: 212 Second operand 3 states. [2018-11-10 06:55:29,979 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:55:29,980 INFO L93 Difference]: Finished difference Result 432 states and 642 transitions. [2018-11-10 06:55:29,980 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 06:55:29,980 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 432 states and 642 transitions. [2018-11-10 06:55:29,982 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 365 [2018-11-10 06:55:29,984 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 432 states to 432 states and 642 transitions. [2018-11-10 06:55:29,984 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 432 [2018-11-10 06:55:29,984 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 432 [2018-11-10 06:55:29,984 INFO L73 IsDeterministic]: Start isDeterministic. Operand 432 states and 642 transitions. [2018-11-10 06:55:29,985 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:55:29,985 INFO L705 BuchiCegarLoop]: Abstraction has 432 states and 642 transitions. [2018-11-10 06:55:29,986 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 432 states and 642 transitions. [2018-11-10 06:55:29,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 432 to 432. [2018-11-10 06:55:29,992 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 432 states. [2018-11-10 06:55:29,993 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 432 states to 432 states and 642 transitions. [2018-11-10 06:55:29,993 INFO L728 BuchiCegarLoop]: Abstraction has 432 states and 642 transitions. [2018-11-10 06:55:29,993 INFO L608 BuchiCegarLoop]: Abstraction has 432 states and 642 transitions. [2018-11-10 06:55:29,993 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ [2018-11-10 06:55:29,994 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 432 states and 642 transitions. [2018-11-10 06:55:29,995 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 365 [2018-11-10 06:55:29,995 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:55:29,995 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:55:29,996 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:29,996 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:29,997 INFO L793 eck$LassoCheckResult]: Stem: 2997#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 2906#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2907#L756 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 2733#L336 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2734#L343 assume ~m_i~0 == 1;~m_st~0 := 0; 2779#L343-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 2783#L348-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 2840#L353-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 2737#L358-1 assume !(~t4_i~0 == 1);~t4_st~0 := 2; 2738#L363-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3012#L504 assume !(~M_E~0 == 0); 3046#L504-2 assume ~T1_E~0 == 0;~T1_E~0 := 1; 2867#L509-1 assume !(~T2_E~0 == 0); 2868#L514-1 assume !(~T3_E~0 == 0); 2793#L519-1 assume !(~T4_E~0 == 0); 2794#L524-1 assume !(~E_M~0 == 0); 2847#L529-1 assume !(~E_1~0 == 0); 2747#L534-1 assume !(~E_2~0 == 0); 2748#L539-1 assume !(~E_3~0 == 0); 2643#L544-1 assume ~E_4~0 == 0;~E_4~0 := 1; 2644#L549-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2936#L240 assume ~m_pc~0 == 1; 2899#L241 assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 2900#L251 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2902#L252 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2903#L627 assume !(activate_threads_~tmp~1 != 0); 3013#L627-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2735#L259 assume !(~t1_pc~0 == 1); 2716#L259-2 is_transmit1_triggered_~__retres1~1 := 0; 2717#L270 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2739#L271 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3027#L635 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 3056#L635-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2864#L278 assume ~t2_pc~0 == 1; 2687#L279 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 2688#L289 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2690#L290 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2628#L643 assume !(activate_threads_~tmp___1~0 != 0); 2629#L643-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2634#L297 assume !(~t3_pc~0 == 1); 2843#L297-2 is_transmit3_triggered_~__retres1~3 := 0; 2844#L308 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2841#L309 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2799#L651 assume !(activate_threads_~tmp___2~0 != 0); 2786#L651-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2787#L316 assume ~t4_pc~0 == 1; 2971#L317 assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 2972#L327 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2970#L328 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2945#L659 assume !(activate_threads_~tmp___3~0 != 0); 2946#L659-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2845#L562 assume !(~M_E~0 == 1); 2846#L562-2 assume !(~T1_E~0 == 1); 2745#L567-1 assume !(~T2_E~0 == 1); 2746#L572-1 assume !(~T3_E~0 == 1); 2637#L577-1 assume !(~T4_E~0 == 1); 2638#L582-1 assume !(~E_M~0 == 1); 2694#L587-1 assume ~E_1~0 == 1;~E_1~0 := 2; 2695#L592-1 assume !(~E_2~0 == 1); 2862#L597-1 assume !(~E_3~0 == 1); 2863#L602-1 assume !(~E_4~0 == 1); 2788#L607-1 assume { :end_inline_reset_delta_events } true; 2789#L793-3 [2018-11-10 06:55:29,997 INFO L795 eck$LassoCheckResult]: Loop: 2789#L793-3 assume true; 2988#L793-1 assume !false; 2800#L794 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 2749#L479 assume true; 2722#L413-1 assume !false; 2723#L414 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2776#L376 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 2725#L403 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3033#L404 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 3008#L418 assume !(eval_~tmp~0 != 0); 2937#L494 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 2743#L336-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 2744#L504-3 assume !(~M_E~0 == 0); 2967#L504-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 2872#L509-3 assume ~T2_E~0 == 0;~T2_E~0 := 1; 2873#L514-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 2772#L519-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 2773#L524-3 assume ~E_M~0 == 0;~E_M~0 := 1; 2838#L529-3 assume ~E_1~0 == 0;~E_1~0 := 1; 2707#L534-3 assume ~E_2~0 == 0;~E_2~0 := 1; 2708#L539-3 assume !(~E_3~0 == 0); 2765#L544-3 assume ~E_4~0 == 0;~E_4~0 := 1; 2766#L549-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2941#L240-18 assume ~m_pc~0 == 1; 2913#L241-6 assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 2914#L251-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2917#L252-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2918#L627-18 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 2995#L627-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2996#L259-18 assume ~t1_pc~0 == 1; 3021#L260-6 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 3022#L270-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3024#L271-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3025#L635-18 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 3051#L635-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2698#L278-18 assume ~t2_pc~0 == 1; 2652#L279-6 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 2654#L289-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2655#L290-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2656#L643-18 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 2756#L643-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2757#L297-18 assume ~t3_pc~0 == 1; 2833#L298-6 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 2834#L308-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2836#L309-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2837#L651-18 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 2880#L651-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2881#L316-18 assume !(~t4_pc~0 == 1); 2961#L316-20 is_transmit4_triggered_~__retres1~4 := 0; 2960#L327-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2958#L328-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2904#L659-18 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 2905#L659-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2848#L562-3 assume ~M_E~0 == 1;~M_E~0 := 2; 2839#L562-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 2702#L567-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 2703#L572-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 2763#L577-3 assume ~T4_E~0 == 1;~T4_E~0 := 2; 2764#L582-3 assume !(~E_M~0 == 1); 2681#L587-3 assume ~E_1~0 == 1;~E_1~0 := 2; 2682#L592-3 assume ~E_2~0 == 1;~E_2~0 := 2; 2865#L597-3 assume ~E_3~0 == 1;~E_3~0 := 2; 2866#L602-3 assume ~E_4~0 == 1;~E_4~0 := 2; 2792#L607-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2780#L376-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 2731#L403-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3039#L404-1 start_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 3048#L812 assume !(start_simulation_~tmp~3 == 0); 3014#L812-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret12, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2781#L376-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 2741#L403-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3043#L404-2 stop_simulation_#t~ret12 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret12;havoc stop_simulation_#t~ret12; 3026#L767 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 2697#L774 stop_simulation_#res := stop_simulation_~__retres2~0; 2645#L775 start_simulation_#t~ret14 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 2646#L825 assume !(start_simulation_~tmp___0~1 != 0); 2789#L793-3 [2018-11-10 06:55:29,997 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:29,998 INFO L82 PathProgramCache]: Analyzing trace with hash -308153604, now seen corresponding path program 1 times [2018-11-10 06:55:29,998 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:30,002 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:30,003 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:30,003 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:55:30,003 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:30,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:55:30,033 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:55:30,033 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:55:30,033 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:55:30,033 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 06:55:30,034 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:30,034 INFO L82 PathProgramCache]: Analyzing trace with hash 1594397290, now seen corresponding path program 1 times [2018-11-10 06:55:30,034 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:30,034 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:30,035 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:30,035 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:55:30,035 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:30,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:55:30,070 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:55:30,070 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:55:30,071 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:55:30,071 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 06:55:30,071 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 06:55:30,071 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 06:55:30,071 INFO L87 Difference]: Start difference. First operand 432 states and 642 transitions. cyclomatic complexity: 211 Second operand 3 states. [2018-11-10 06:55:30,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:55:30,078 INFO L93 Difference]: Finished difference Result 432 states and 641 transitions. [2018-11-10 06:55:30,078 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 06:55:30,079 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 432 states and 641 transitions. [2018-11-10 06:55:30,081 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 365 [2018-11-10 06:55:30,082 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 432 states to 432 states and 641 transitions. [2018-11-10 06:55:30,082 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 432 [2018-11-10 06:55:30,083 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 432 [2018-11-10 06:55:30,083 INFO L73 IsDeterministic]: Start isDeterministic. Operand 432 states and 641 transitions. [2018-11-10 06:55:30,084 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:55:30,084 INFO L705 BuchiCegarLoop]: Abstraction has 432 states and 641 transitions. [2018-11-10 06:55:30,084 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 432 states and 641 transitions. [2018-11-10 06:55:30,088 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 432 to 432. [2018-11-10 06:55:30,088 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 432 states. [2018-11-10 06:55:30,089 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 432 states to 432 states and 641 transitions. [2018-11-10 06:55:30,089 INFO L728 BuchiCegarLoop]: Abstraction has 432 states and 641 transitions. [2018-11-10 06:55:30,089 INFO L608 BuchiCegarLoop]: Abstraction has 432 states and 641 transitions. [2018-11-10 06:55:30,089 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ [2018-11-10 06:55:30,089 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 432 states and 641 transitions. [2018-11-10 06:55:30,091 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 365 [2018-11-10 06:55:30,091 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:55:30,091 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:55:30,092 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:30,093 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:30,093 INFO L793 eck$LassoCheckResult]: Stem: 3868#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 3777#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3778#L756 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 3606#L336 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3607#L343 assume ~m_i~0 == 1;~m_st~0 := 0; 3651#L343-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 3654#L348-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 3711#L353-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 3608#L358-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 3609#L363-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3883#L504 assume !(~M_E~0 == 0); 3917#L504-2 assume ~T1_E~0 == 0;~T1_E~0 := 1; 3738#L509-1 assume !(~T2_E~0 == 0); 3739#L514-1 assume !(~T3_E~0 == 0); 3664#L519-1 assume !(~T4_E~0 == 0); 3665#L524-1 assume !(~E_M~0 == 0); 3718#L529-1 assume !(~E_1~0 == 0); 3618#L534-1 assume !(~E_2~0 == 0); 3619#L539-1 assume !(~E_3~0 == 0); 3514#L544-1 assume ~E_4~0 == 0;~E_4~0 := 1; 3515#L549-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3807#L240 assume ~m_pc~0 == 1; 3770#L241 assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 3771#L251 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3773#L252 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 3774#L627 assume !(activate_threads_~tmp~1 != 0); 3884#L627-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3604#L259 assume !(~t1_pc~0 == 1); 3587#L259-2 is_transmit1_triggered_~__retres1~1 := 0; 3588#L270 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3610#L271 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3898#L635 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 3927#L635-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3735#L278 assume ~t2_pc~0 == 1; 3558#L279 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 3559#L289 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3561#L290 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3499#L643 assume !(activate_threads_~tmp___1~0 != 0); 3500#L643-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3505#L297 assume !(~t3_pc~0 == 1); 3714#L297-2 is_transmit3_triggered_~__retres1~3 := 0; 3715#L308 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3712#L309 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3670#L651 assume !(activate_threads_~tmp___2~0 != 0); 3657#L651-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3658#L316 assume ~t4_pc~0 == 1; 3842#L317 assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 3843#L327 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3841#L328 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3816#L659 assume !(activate_threads_~tmp___3~0 != 0); 3817#L659-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3716#L562 assume !(~M_E~0 == 1); 3717#L562-2 assume !(~T1_E~0 == 1); 3616#L567-1 assume !(~T2_E~0 == 1); 3617#L572-1 assume !(~T3_E~0 == 1); 3508#L577-1 assume !(~T4_E~0 == 1); 3509#L582-1 assume !(~E_M~0 == 1); 3565#L587-1 assume ~E_1~0 == 1;~E_1~0 := 2; 3566#L592-1 assume !(~E_2~0 == 1); 3733#L597-1 assume !(~E_3~0 == 1); 3734#L602-1 assume !(~E_4~0 == 1); 3659#L607-1 assume { :end_inline_reset_delta_events } true; 3660#L793-3 [2018-11-10 06:55:30,093 INFO L795 eck$LassoCheckResult]: Loop: 3660#L793-3 assume true; 3859#L793-1 assume !false; 3671#L794 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 3620#L479 assume true; 3593#L413-1 assume !false; 3594#L414 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3647#L376 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 3596#L403 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3904#L404 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 3879#L418 assume !(eval_~tmp~0 != 0); 3808#L494 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 3614#L336-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 3615#L504-3 assume !(~M_E~0 == 0); 3838#L504-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 3743#L509-3 assume ~T2_E~0 == 0;~T2_E~0 := 1; 3744#L514-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 3643#L519-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 3644#L524-3 assume ~E_M~0 == 0;~E_M~0 := 1; 3709#L529-3 assume ~E_1~0 == 0;~E_1~0 := 1; 3578#L534-3 assume ~E_2~0 == 0;~E_2~0 := 1; 3579#L539-3 assume !(~E_3~0 == 0); 3636#L544-3 assume ~E_4~0 == 0;~E_4~0 := 1; 3637#L549-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3812#L240-18 assume ~m_pc~0 == 1; 3784#L241-6 assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 3785#L251-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3788#L252-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 3789#L627-18 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 3866#L627-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3867#L259-18 assume ~t1_pc~0 == 1; 3892#L260-6 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 3893#L270-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3895#L271-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3896#L635-18 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 3922#L635-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3569#L278-18 assume ~t2_pc~0 == 1; 3523#L279-6 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 3525#L289-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3526#L290-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3527#L643-18 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 3627#L643-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3628#L297-18 assume ~t3_pc~0 == 1; 3704#L298-6 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 3705#L308-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3707#L309-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3708#L651-18 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 3751#L651-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3752#L316-18 assume ~t4_pc~0 == 1; 3830#L317-6 assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 3831#L327-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3829#L328-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3775#L659-18 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 3776#L659-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3719#L562-3 assume ~M_E~0 == 1;~M_E~0 := 2; 3710#L562-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 3573#L567-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 3574#L572-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 3634#L577-3 assume ~T4_E~0 == 1;~T4_E~0 := 2; 3635#L582-3 assume !(~E_M~0 == 1); 3552#L587-3 assume ~E_1~0 == 1;~E_1~0 := 2; 3553#L592-3 assume ~E_2~0 == 1;~E_2~0 := 2; 3736#L597-3 assume ~E_3~0 == 1;~E_3~0 := 2; 3737#L602-3 assume ~E_4~0 == 1;~E_4~0 := 2; 3663#L607-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3650#L376-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 3602#L403-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3910#L404-1 start_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 3919#L812 assume !(start_simulation_~tmp~3 == 0); 3885#L812-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret12, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3652#L376-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 3612#L403-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3914#L404-2 stop_simulation_#t~ret12 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret12;havoc stop_simulation_#t~ret12; 3897#L767 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 3568#L774 stop_simulation_#res := stop_simulation_~__retres2~0; 3516#L775 start_simulation_#t~ret14 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 3517#L825 assume !(start_simulation_~tmp___0~1 != 0); 3660#L793-3 [2018-11-10 06:55:30,093 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:30,094 INFO L82 PathProgramCache]: Analyzing trace with hash -1184172610, now seen corresponding path program 1 times [2018-11-10 06:55:30,094 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:30,094 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:30,095 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:30,095 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:55:30,095 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:30,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:55:30,117 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:55:30,117 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:55:30,117 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 06:55:30,117 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 06:55:30,117 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:30,118 INFO L82 PathProgramCache]: Analyzing trace with hash -1728895319, now seen corresponding path program 2 times [2018-11-10 06:55:30,118 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:30,118 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:30,119 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:30,119 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:55:30,119 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:30,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:55:30,164 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:55:30,165 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:55:30,165 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:55:30,165 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 06:55:30,165 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 06:55:30,165 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 06:55:30,165 INFO L87 Difference]: Start difference. First operand 432 states and 641 transitions. cyclomatic complexity: 210 Second operand 3 states. [2018-11-10 06:55:30,184 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:55:30,184 INFO L93 Difference]: Finished difference Result 432 states and 636 transitions. [2018-11-10 06:55:30,184 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 06:55:30,185 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 432 states and 636 transitions. [2018-11-10 06:55:30,186 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 365 [2018-11-10 06:55:30,187 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 432 states to 432 states and 636 transitions. [2018-11-10 06:55:30,188 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 432 [2018-11-10 06:55:30,188 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 432 [2018-11-10 06:55:30,188 INFO L73 IsDeterministic]: Start isDeterministic. Operand 432 states and 636 transitions. [2018-11-10 06:55:30,189 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:55:30,189 INFO L705 BuchiCegarLoop]: Abstraction has 432 states and 636 transitions. [2018-11-10 06:55:30,189 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 432 states and 636 transitions. [2018-11-10 06:55:30,192 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 432 to 432. [2018-11-10 06:55:30,192 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 432 states. [2018-11-10 06:55:30,193 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 432 states to 432 states and 636 transitions. [2018-11-10 06:55:30,193 INFO L728 BuchiCegarLoop]: Abstraction has 432 states and 636 transitions. [2018-11-10 06:55:30,193 INFO L608 BuchiCegarLoop]: Abstraction has 432 states and 636 transitions. [2018-11-10 06:55:30,194 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ [2018-11-10 06:55:30,194 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 432 states and 636 transitions. [2018-11-10 06:55:30,195 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 365 [2018-11-10 06:55:30,195 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:55:30,195 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:55:30,196 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:30,196 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:30,196 INFO L793 eck$LassoCheckResult]: Stem: 4739#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 4648#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 4649#L756 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 4475#L336 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4476#L343 assume ~m_i~0 == 1;~m_st~0 := 0; 4522#L343-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 4525#L348-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 4582#L353-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 4479#L358-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 4480#L363-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4754#L504 assume !(~M_E~0 == 0); 4788#L504-2 assume !(~T1_E~0 == 0); 4609#L509-1 assume !(~T2_E~0 == 0); 4610#L514-1 assume !(~T3_E~0 == 0); 4536#L519-1 assume !(~T4_E~0 == 0); 4537#L524-1 assume !(~E_M~0 == 0); 4589#L529-1 assume !(~E_1~0 == 0); 4489#L534-1 assume !(~E_2~0 == 0); 4490#L539-1 assume !(~E_3~0 == 0); 4385#L544-1 assume ~E_4~0 == 0;~E_4~0 := 1; 4386#L549-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4678#L240 assume ~m_pc~0 == 1; 4641#L241 assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 4642#L251 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4644#L252 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 4645#L627 assume !(activate_threads_~tmp~1 != 0); 4755#L627-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4477#L259 assume !(~t1_pc~0 == 1); 4458#L259-2 is_transmit1_triggered_~__retres1~1 := 0; 4459#L270 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4481#L271 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 4769#L635 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 4798#L635-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4606#L278 assume ~t2_pc~0 == 1; 4429#L279 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 4430#L289 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4432#L290 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 4372#L643 assume !(activate_threads_~tmp___1~0 != 0); 4373#L643-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4378#L297 assume !(~t3_pc~0 == 1); 4585#L297-2 is_transmit3_triggered_~__retres1~3 := 0; 4586#L308 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4583#L309 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4541#L651 assume !(activate_threads_~tmp___2~0 != 0); 4528#L651-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4529#L316 assume ~t4_pc~0 == 1; 4713#L317 assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 4714#L327 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4712#L328 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4687#L659 assume !(activate_threads_~tmp___3~0 != 0); 4688#L659-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4587#L562 assume !(~M_E~0 == 1); 4588#L562-2 assume !(~T1_E~0 == 1); 4487#L567-1 assume !(~T2_E~0 == 1); 4488#L572-1 assume !(~T3_E~0 == 1); 4383#L577-1 assume !(~T4_E~0 == 1); 4384#L582-1 assume !(~E_M~0 == 1); 4436#L587-1 assume ~E_1~0 == 1;~E_1~0 := 2; 4437#L592-1 assume !(~E_2~0 == 1); 4604#L597-1 assume !(~E_3~0 == 1); 4605#L602-1 assume !(~E_4~0 == 1); 4530#L607-1 assume { :end_inline_reset_delta_events } true; 4531#L793-3 [2018-11-10 06:55:30,197 INFO L795 eck$LassoCheckResult]: Loop: 4531#L793-3 assume true; 4730#L793-1 assume !false; 4542#L794 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 4491#L479 assume true; 4464#L413-1 assume !false; 4465#L414 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 4518#L376 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 4467#L403 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 4777#L404 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 4750#L418 assume !(eval_~tmp~0 != 0); 4680#L494 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 4485#L336-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 4486#L504-3 assume !(~M_E~0 == 0); 4709#L504-5 assume !(~T1_E~0 == 0); 4614#L509-3 assume ~T2_E~0 == 0;~T2_E~0 := 1; 4615#L514-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 4514#L519-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 4515#L524-3 assume ~E_M~0 == 0;~E_M~0 := 1; 4580#L529-3 assume ~E_1~0 == 0;~E_1~0 := 1; 4452#L534-3 assume ~E_2~0 == 0;~E_2~0 := 1; 4453#L539-3 assume !(~E_3~0 == 0); 4507#L544-3 assume ~E_4~0 == 0;~E_4~0 := 1; 4508#L549-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4683#L240-18 assume !(~m_pc~0 == 1); 4657#L240-20 is_master_triggered_~__retres1~0 := 0; 4656#L251-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4659#L252-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 4660#L627-18 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 4737#L627-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4738#L259-18 assume ~t1_pc~0 == 1; 4763#L260-6 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 4764#L270-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4766#L271-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 4767#L635-18 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 4793#L635-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4440#L278-18 assume ~t2_pc~0 == 1; 4394#L279-6 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 4396#L289-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4397#L290-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 4398#L643-18 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 4498#L643-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4499#L297-18 assume ~t3_pc~0 == 1; 4573#L298-6 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 4574#L308-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4576#L309-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4577#L651-18 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 4622#L651-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4623#L316-18 assume ~t4_pc~0 == 1; 4701#L317-6 assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 4702#L327-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4700#L328-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4646#L659-18 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 4647#L659-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4590#L562-3 assume ~M_E~0 == 1;~M_E~0 := 2; 4581#L562-5 assume !(~T1_E~0 == 1); 4441#L567-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 4442#L572-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 4505#L577-3 assume ~T4_E~0 == 1;~T4_E~0 := 2; 4506#L582-3 assume !(~E_M~0 == 1); 4423#L587-3 assume ~E_1~0 == 1;~E_1~0 := 2; 4424#L592-3 assume ~E_2~0 == 1;~E_2~0 := 2; 4607#L597-3 assume ~E_3~0 == 1;~E_3~0 := 2; 4608#L602-3 assume ~E_4~0 == 1;~E_4~0 := 2; 4534#L607-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 4521#L376-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 4473#L403-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 4781#L404-1 start_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 4790#L812 assume !(start_simulation_~tmp~3 == 0); 4756#L812-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret12, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 4523#L376-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 4483#L403-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 4785#L404-2 stop_simulation_#t~ret12 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret12;havoc stop_simulation_#t~ret12; 4768#L767 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 4439#L774 stop_simulation_#res := stop_simulation_~__retres2~0; 4387#L775 start_simulation_#t~ret14 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 4388#L825 assume !(start_simulation_~tmp___0~1 != 0); 4531#L793-3 [2018-11-10 06:55:30,197 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:30,197 INFO L82 PathProgramCache]: Analyzing trace with hash 1082208576, now seen corresponding path program 1 times [2018-11-10 06:55:30,197 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:30,197 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:30,198 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:30,198 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 06:55:30,198 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:30,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:55:30,235 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:55:30,236 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:55:30,236 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 06:55:30,236 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 06:55:30,236 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:30,236 INFO L82 PathProgramCache]: Analyzing trace with hash 2093751594, now seen corresponding path program 1 times [2018-11-10 06:55:30,236 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:30,236 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:30,237 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:30,237 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:55:30,237 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:30,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:55:30,263 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:55:30,263 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:55:30,263 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:55:30,263 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 06:55:30,264 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 06:55:30,264 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 06:55:30,264 INFO L87 Difference]: Start difference. First operand 432 states and 636 transitions. cyclomatic complexity: 205 Second operand 3 states. [2018-11-10 06:55:30,297 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:55:30,297 INFO L93 Difference]: Finished difference Result 432 states and 624 transitions. [2018-11-10 06:55:30,298 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 06:55:30,298 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 432 states and 624 transitions. [2018-11-10 06:55:30,300 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 365 [2018-11-10 06:55:30,301 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 432 states to 432 states and 624 transitions. [2018-11-10 06:55:30,301 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 432 [2018-11-10 06:55:30,301 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 432 [2018-11-10 06:55:30,301 INFO L73 IsDeterministic]: Start isDeterministic. Operand 432 states and 624 transitions. [2018-11-10 06:55:30,302 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:55:30,302 INFO L705 BuchiCegarLoop]: Abstraction has 432 states and 624 transitions. [2018-11-10 06:55:30,303 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 432 states and 624 transitions. [2018-11-10 06:55:30,306 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 432 to 432. [2018-11-10 06:55:30,306 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 432 states. [2018-11-10 06:55:30,307 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 432 states to 432 states and 624 transitions. [2018-11-10 06:55:30,308 INFO L728 BuchiCegarLoop]: Abstraction has 432 states and 624 transitions. [2018-11-10 06:55:30,308 INFO L608 BuchiCegarLoop]: Abstraction has 432 states and 624 transitions. [2018-11-10 06:55:30,308 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ [2018-11-10 06:55:30,308 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 432 states and 624 transitions. [2018-11-10 06:55:30,310 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 365 [2018-11-10 06:55:30,310 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:55:30,310 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:55:30,311 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:30,311 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:30,311 INFO L793 eck$LassoCheckResult]: Stem: 5603#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 5519#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 5520#L756 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 5346#L336 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5347#L343 assume ~m_i~0 == 1;~m_st~0 := 0; 5393#L343-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 5396#L348-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 5453#L353-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 5350#L358-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 5351#L363-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5618#L504 assume !(~M_E~0 == 0); 5652#L504-2 assume !(~T1_E~0 == 0); 5480#L509-1 assume !(~T2_E~0 == 0); 5481#L514-1 assume !(~T3_E~0 == 0); 5406#L519-1 assume !(~T4_E~0 == 0); 5407#L524-1 assume !(~E_M~0 == 0); 5460#L529-1 assume !(~E_1~0 == 0); 5360#L534-1 assume !(~E_2~0 == 0); 5361#L539-1 assume !(~E_3~0 == 0); 5256#L544-1 assume !(~E_4~0 == 0); 5257#L549-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5549#L240 assume ~m_pc~0 == 1; 5512#L241 assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 5513#L251 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5515#L252 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 5516#L627 assume !(activate_threads_~tmp~1 != 0); 5619#L627-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5348#L259 assume !(~t1_pc~0 == 1); 5329#L259-2 is_transmit1_triggered_~__retres1~1 := 0; 5330#L270 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5352#L271 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 5633#L635 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 5669#L635-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5477#L278 assume ~t2_pc~0 == 1; 5300#L279 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 5301#L289 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5303#L290 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5243#L643 assume !(activate_threads_~tmp___1~0 != 0); 5244#L643-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5249#L297 assume !(~t3_pc~0 == 1); 5456#L297-2 is_transmit3_triggered_~__retres1~3 := 0; 5457#L308 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5454#L309 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5412#L651 assume !(activate_threads_~tmp___2~0 != 0); 5399#L651-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5400#L316 assume !(~t4_pc~0 == 1); 5582#L316-2 is_transmit4_triggered_~__retres1~4 := 0; 5668#L327 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5580#L328 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5558#L659 assume !(activate_threads_~tmp___3~0 != 0); 5559#L659-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5458#L562 assume !(~M_E~0 == 1); 5459#L562-2 assume !(~T1_E~0 == 1); 5358#L567-1 assume !(~T2_E~0 == 1); 5359#L572-1 assume !(~T3_E~0 == 1); 5252#L577-1 assume !(~T4_E~0 == 1); 5253#L582-1 assume !(~E_M~0 == 1); 5307#L587-1 assume ~E_1~0 == 1;~E_1~0 := 2; 5308#L592-1 assume !(~E_2~0 == 1); 5475#L597-1 assume !(~E_3~0 == 1); 5476#L602-1 assume !(~E_4~0 == 1); 5401#L607-1 assume { :end_inline_reset_delta_events } true; 5402#L793-3 [2018-11-10 06:55:30,311 INFO L795 eck$LassoCheckResult]: Loop: 5402#L793-3 assume true; 5594#L793-1 assume !false; 5413#L794 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 5362#L479 assume true; 5335#L413-1 assume !false; 5336#L414 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 5389#L376 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 5338#L403 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 5639#L404 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 5614#L418 assume !(eval_~tmp~0 != 0); 5551#L494 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 5356#L336-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 5357#L504-3 assume !(~M_E~0 == 0); 5577#L504-5 assume !(~T1_E~0 == 0); 5485#L509-3 assume ~T2_E~0 == 0;~T2_E~0 := 1; 5486#L514-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 5385#L519-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 5386#L524-3 assume ~E_M~0 == 0;~E_M~0 := 1; 5451#L529-3 assume ~E_1~0 == 0;~E_1~0 := 1; 5320#L534-3 assume ~E_2~0 == 0;~E_2~0 := 1; 5321#L539-3 assume !(~E_3~0 == 0); 5378#L544-3 assume !(~E_4~0 == 0); 5379#L549-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5554#L240-18 assume ~m_pc~0 == 1; 5527#L241-6 assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 5528#L251-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5530#L252-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 5531#L627-18 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 5601#L627-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5602#L259-18 assume ~t1_pc~0 == 1; 5627#L260-6 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 5628#L270-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5630#L271-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 5631#L635-18 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 5661#L635-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5311#L278-18 assume ~t2_pc~0 == 1; 5265#L279-6 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 5267#L289-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5268#L290-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5269#L643-18 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 5369#L643-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5370#L297-18 assume ~t3_pc~0 == 1; 5448#L298-6 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 5449#L308-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5444#L309-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5445#L651-18 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 5493#L651-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5494#L316-18 assume !(~t4_pc~0 == 1); 5572#L316-20 is_transmit4_triggered_~__retres1~4 := 0; 5653#L327-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5570#L328-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5517#L659-18 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 5518#L659-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5461#L562-3 assume ~M_E~0 == 1;~M_E~0 := 2; 5452#L562-5 assume !(~T1_E~0 == 1); 5312#L567-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 5313#L572-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 5375#L577-3 assume ~T4_E~0 == 1;~T4_E~0 := 2; 5376#L582-3 assume !(~E_M~0 == 1); 5294#L587-3 assume ~E_1~0 == 1;~E_1~0 := 2; 5295#L592-3 assume ~E_2~0 == 1;~E_2~0 := 2; 5478#L597-3 assume ~E_3~0 == 1;~E_3~0 := 2; 5479#L602-3 assume !(~E_4~0 == 1); 5405#L607-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 5392#L376-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 5344#L403-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 5643#L404-1 start_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 5656#L812 assume !(start_simulation_~tmp~3 == 0); 5620#L812-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret12, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 5394#L376-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 5354#L403-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 5647#L404-2 stop_simulation_#t~ret12 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret12;havoc stop_simulation_#t~ret12; 5632#L767 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 5310#L774 stop_simulation_#res := stop_simulation_~__retres2~0; 5258#L775 start_simulation_#t~ret14 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 5259#L825 assume !(start_simulation_~tmp___0~1 != 0); 5402#L793-3 [2018-11-10 06:55:30,312 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:30,312 INFO L82 PathProgramCache]: Analyzing trace with hash -1995156477, now seen corresponding path program 1 times [2018-11-10 06:55:30,312 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:30,312 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:30,313 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:30,313 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:55:30,313 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:30,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:55:30,358 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:55:30,359 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:55:30,359 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 06:55:30,359 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 06:55:30,359 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:30,359 INFO L82 PathProgramCache]: Analyzing trace with hash 1771523562, now seen corresponding path program 1 times [2018-11-10 06:55:30,360 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:30,360 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:30,360 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:30,360 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:55:30,361 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:30,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:55:30,386 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:55:30,386 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:55:30,386 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:55:30,386 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 06:55:30,386 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 06:55:30,387 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 06:55:30,387 INFO L87 Difference]: Start difference. First operand 432 states and 624 transitions. cyclomatic complexity: 193 Second operand 3 states. [2018-11-10 06:55:30,475 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:55:30,475 INFO L93 Difference]: Finished difference Result 787 states and 1123 transitions. [2018-11-10 06:55:30,475 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 06:55:30,476 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 787 states and 1123 transitions. [2018-11-10 06:55:30,480 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 719 [2018-11-10 06:55:30,483 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 787 states to 787 states and 1123 transitions. [2018-11-10 06:55:30,484 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 787 [2018-11-10 06:55:30,484 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 787 [2018-11-10 06:55:30,485 INFO L73 IsDeterministic]: Start isDeterministic. Operand 787 states and 1123 transitions. [2018-11-10 06:55:30,486 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:55:30,486 INFO L705 BuchiCegarLoop]: Abstraction has 787 states and 1123 transitions. [2018-11-10 06:55:30,487 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 787 states and 1123 transitions. [2018-11-10 06:55:30,515 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 787 to 753. [2018-11-10 06:55:30,515 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 753 states. [2018-11-10 06:55:30,518 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 753 states to 753 states and 1077 transitions. [2018-11-10 06:55:30,518 INFO L728 BuchiCegarLoop]: Abstraction has 753 states and 1077 transitions. [2018-11-10 06:55:30,518 INFO L608 BuchiCegarLoop]: Abstraction has 753 states and 1077 transitions. [2018-11-10 06:55:30,518 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ [2018-11-10 06:55:30,518 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 753 states and 1077 transitions. [2018-11-10 06:55:30,521 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 685 [2018-11-10 06:55:30,521 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:55:30,521 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:55:30,522 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:30,522 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:30,523 INFO L793 eck$LassoCheckResult]: Stem: 6844#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 6747#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 6748#L756 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 6572#L336 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6573#L343 assume ~m_i~0 == 1;~m_st~0 := 0; 6621#L343-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 6624#L348-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 6683#L353-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 6576#L358-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 6577#L363-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6863#L504 assume !(~M_E~0 == 0); 6897#L504-2 assume !(~T1_E~0 == 0); 6711#L509-1 assume !(~T2_E~0 == 0); 6712#L514-1 assume !(~T3_E~0 == 0); 6635#L519-1 assume !(~T4_E~0 == 0); 6636#L524-1 assume !(~E_M~0 == 0); 6690#L529-1 assume !(~E_1~0 == 0); 6586#L534-1 assume !(~E_2~0 == 0); 6587#L539-1 assume !(~E_3~0 == 0); 6482#L544-1 assume !(~E_4~0 == 0); 6483#L549-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6777#L240 assume !(~m_pc~0 == 1); 6807#L240-2 is_master_triggered_~__retres1~0 := 0; 6810#L251 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6743#L252 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 6744#L627 assume !(activate_threads_~tmp~1 != 0); 6864#L627-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6574#L259 assume !(~t1_pc~0 == 1); 6555#L259-2 is_transmit1_triggered_~__retres1~1 := 0; 6556#L270 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6578#L271 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 6878#L635 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 6916#L635-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6708#L278 assume ~t2_pc~0 == 1; 6526#L279 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 6527#L289 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6529#L290 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 6469#L643 assume !(activate_threads_~tmp___1~0 != 0); 6470#L643-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6475#L297 assume !(~t3_pc~0 == 1); 6686#L297-2 is_transmit3_triggered_~__retres1~3 := 0; 6687#L308 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6684#L309 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 6640#L651 assume !(activate_threads_~tmp___2~0 != 0); 6627#L651-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6628#L316 assume !(~t4_pc~0 == 1); 6823#L316-2 is_transmit4_triggered_~__retres1~4 := 0; 6915#L327 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6821#L328 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 6789#L659 assume !(activate_threads_~tmp___3~0 != 0); 6790#L659-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6688#L562 assume !(~M_E~0 == 1); 6689#L562-2 assume !(~T1_E~0 == 1); 6584#L567-1 assume !(~T2_E~0 == 1); 6585#L572-1 assume !(~T3_E~0 == 1); 6480#L577-1 assume !(~T4_E~0 == 1); 6481#L582-1 assume !(~E_M~0 == 1); 6533#L587-1 assume ~E_1~0 == 1;~E_1~0 := 2; 6534#L592-1 assume !(~E_2~0 == 1); 6706#L597-1 assume !(~E_3~0 == 1); 6707#L602-1 assume !(~E_4~0 == 1); 6629#L607-1 assume { :end_inline_reset_delta_events } true; 6630#L793-3 [2018-11-10 06:55:30,523 INFO L795 eck$LassoCheckResult]: Loop: 6630#L793-3 assume true; 6835#L793-1 assume !false; 6641#L794 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 6588#L479 assume true; 6561#L413-1 assume !false; 6562#L414 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 6617#L376 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 6564#L403 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 6884#L404 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 6859#L418 assume !(eval_~tmp~0 != 0); 6779#L494 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 6582#L336-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 6583#L504-3 assume !(~M_E~0 == 0); 6820#L504-5 assume !(~T1_E~0 == 0); 6716#L509-3 assume ~T2_E~0 == 0;~T2_E~0 := 1; 6717#L514-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 6613#L519-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 6614#L524-3 assume ~E_M~0 == 0;~E_M~0 := 1; 6681#L529-3 assume ~E_1~0 == 0;~E_1~0 := 1; 6546#L534-3 assume ~E_2~0 == 0;~E_2~0 := 1; 6547#L539-3 assume !(~E_3~0 == 0); 6607#L544-3 assume !(~E_4~0 == 0); 6608#L549-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6783#L240-18 assume !(~m_pc~0 == 1); 6784#L240-20 is_master_triggered_~__retres1~0 := 0; 6785#L251-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6758#L252-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 6759#L627-18 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 6842#L627-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6843#L259-18 assume ~t1_pc~0 == 1; 6872#L260-6 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 6873#L270-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6875#L271-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 6876#L635-18 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 6906#L635-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6537#L278-18 assume ~t2_pc~0 == 1; 6491#L279-6 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 6493#L289-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6494#L290-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 6495#L643-18 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 6595#L643-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6596#L297-18 assume ~t3_pc~0 == 1; 6674#L298-6 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 6675#L308-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6677#L309-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 6678#L651-18 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 6724#L651-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6725#L316-18 assume !(~t4_pc~0 == 1); 6813#L316-20 is_transmit4_triggered_~__retres1~4 := 0; 6898#L327-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6811#L328-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 6745#L659-18 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 6746#L659-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6691#L562-3 assume ~M_E~0 == 1;~M_E~0 := 2; 6682#L562-5 assume !(~T1_E~0 == 1); 6538#L567-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 6539#L572-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 6604#L577-3 assume ~T4_E~0 == 1;~T4_E~0 := 2; 6605#L582-3 assume !(~E_M~0 == 1); 6520#L587-3 assume ~E_1~0 == 1;~E_1~0 := 2; 6521#L592-3 assume ~E_2~0 == 1;~E_2~0 := 2; 6709#L597-3 assume ~E_3~0 == 1;~E_3~0 := 2; 6710#L602-3 assume !(~E_4~0 == 1); 6633#L607-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 6620#L376-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 6570#L403-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 6888#L404-1 start_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 6901#L812 assume !(start_simulation_~tmp~3 == 0); 6865#L812-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret12, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 6622#L376-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 6580#L403-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 6892#L404-2 stop_simulation_#t~ret12 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret12;havoc stop_simulation_#t~ret12; 6877#L767 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 6536#L774 stop_simulation_#res := stop_simulation_~__retres2~0; 6484#L775 start_simulation_#t~ret14 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 6485#L825 assume !(start_simulation_~tmp___0~1 != 0); 6630#L793-3 [2018-11-10 06:55:30,523 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:30,524 INFO L82 PathProgramCache]: Analyzing trace with hash 1814636100, now seen corresponding path program 1 times [2018-11-10 06:55:30,524 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:30,524 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:30,525 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:30,525 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:55:30,525 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:30,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:55:30,566 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:55:30,567 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:55:30,567 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 06:55:30,568 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 06:55:30,568 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:30,569 INFO L82 PathProgramCache]: Analyzing trace with hash 1497745067, now seen corresponding path program 1 times [2018-11-10 06:55:30,569 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:30,569 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:30,569 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:30,570 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:55:30,570 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:30,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:55:30,588 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:55:30,589 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:55:30,589 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:55:30,589 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 06:55:30,589 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 06:55:30,589 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 06:55:30,590 INFO L87 Difference]: Start difference. First operand 753 states and 1077 transitions. cyclomatic complexity: 326 Second operand 3 states. [2018-11-10 06:55:30,647 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:55:30,647 INFO L93 Difference]: Finished difference Result 1353 states and 1920 transitions. [2018-11-10 06:55:30,648 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 06:55:30,649 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1353 states and 1920 transitions. [2018-11-10 06:55:30,655 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1280 [2018-11-10 06:55:30,663 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1353 states to 1353 states and 1920 transitions. [2018-11-10 06:55:30,663 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1353 [2018-11-10 06:55:30,665 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1353 [2018-11-10 06:55:30,665 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1353 states and 1920 transitions. [2018-11-10 06:55:30,667 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:55:30,667 INFO L705 BuchiCegarLoop]: Abstraction has 1353 states and 1920 transitions. [2018-11-10 06:55:30,669 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1353 states and 1920 transitions. [2018-11-10 06:55:30,685 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1353 to 1347. [2018-11-10 06:55:30,685 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1347 states. [2018-11-10 06:55:30,688 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1347 states to 1347 states and 1914 transitions. [2018-11-10 06:55:30,689 INFO L728 BuchiCegarLoop]: Abstraction has 1347 states and 1914 transitions. [2018-11-10 06:55:30,689 INFO L608 BuchiCegarLoop]: Abstraction has 1347 states and 1914 transitions. [2018-11-10 06:55:30,689 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ [2018-11-10 06:55:30,689 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1347 states and 1914 transitions. [2018-11-10 06:55:30,695 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1274 [2018-11-10 06:55:30,695 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:55:30,695 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:55:30,696 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:30,696 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:30,696 INFO L793 eck$LassoCheckResult]: Stem: 8963#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 8864#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 8865#L756 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 8688#L336 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8689#L343 assume ~m_i~0 == 1;~m_st~0 := 0; 8735#L343-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 8738#L348-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 8796#L353-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 8692#L358-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 8693#L363-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8982#L504 assume !(~M_E~0 == 0); 9016#L504-2 assume !(~T1_E~0 == 0); 8827#L509-1 assume !(~T2_E~0 == 0); 8828#L514-1 assume !(~T3_E~0 == 0); 8748#L519-1 assume !(~T4_E~0 == 0); 8749#L524-1 assume !(~E_M~0 == 0); 8803#L529-1 assume !(~E_1~0 == 0); 8702#L534-1 assume !(~E_2~0 == 0); 8703#L539-1 assume !(~E_3~0 == 0); 8595#L544-1 assume !(~E_4~0 == 0); 8596#L549-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8894#L240 assume !(~m_pc~0 == 1); 8923#L240-2 is_master_triggered_~__retres1~0 := 0; 8926#L251 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8860#L252 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 8861#L627 assume !(activate_threads_~tmp~1 != 0); 8983#L627-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8690#L259 assume !(~t1_pc~0 == 1); 8671#L259-2 is_transmit1_triggered_~__retres1~1 := 0; 8672#L270 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8694#L271 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 8997#L635 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 9043#L635-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8824#L278 assume !(~t2_pc~0 == 1); 8812#L278-2 is_transmit2_triggered_~__retres1~2 := 0; 8813#L289 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8639#L290 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 8582#L643 assume !(activate_threads_~tmp___1~0 != 0); 8583#L643-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8588#L297 assume !(~t3_pc~0 == 1); 8799#L297-2 is_transmit3_triggered_~__retres1~3 := 0; 8800#L308 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8797#L309 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 8755#L651 assume !(activate_threads_~tmp___2~0 != 0); 8741#L651-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8742#L316 assume !(~t4_pc~0 == 1); 8940#L316-2 is_transmit4_triggered_~__retres1~4 := 0; 9041#L327 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8938#L328 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 8905#L659 assume !(activate_threads_~tmp___3~0 != 0); 8906#L659-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8801#L562 assume !(~M_E~0 == 1); 8802#L562-2 assume !(~T1_E~0 == 1); 8700#L567-1 assume !(~T2_E~0 == 1); 8701#L572-1 assume !(~T3_E~0 == 1); 8591#L577-1 assume !(~T4_E~0 == 1); 8592#L582-1 assume !(~E_M~0 == 1); 8647#L587-1 assume ~E_1~0 == 1;~E_1~0 := 2; 8648#L592-1 assume !(~E_2~0 == 1); 8822#L597-1 assume !(~E_3~0 == 1); 8823#L602-1 assume !(~E_4~0 == 1); 8743#L607-1 assume { :end_inline_reset_delta_events } true; 8744#L793-3 [2018-11-10 06:55:30,696 INFO L795 eck$LassoCheckResult]: Loop: 8744#L793-3 assume true; 8952#L793-1 assume !false; 8756#L794 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 8704#L479 assume true; 8677#L413-1 assume !false; 8678#L414 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 8731#L376 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 8680#L403 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 9003#L404 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 8978#L418 assume !(eval_~tmp~0 != 0); 8895#L494 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 8698#L336-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 8699#L504-3 assume !(~M_E~0 == 0); 8934#L504-5 assume !(~T1_E~0 == 0); 8935#L509-3 assume ~T2_E~0 == 0;~T2_E~0 := 1; 9910#L514-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 9907#L519-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 9905#L524-3 assume ~E_M~0 == 0;~E_M~0 := 1; 9903#L529-3 assume ~E_1~0 == 0;~E_1~0 := 1; 9901#L534-3 assume ~E_2~0 == 0;~E_2~0 := 1; 9899#L539-3 assume !(~E_3~0 == 0); 9897#L544-3 assume !(~E_4~0 == 0); 9894#L549-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9893#L240-18 assume !(~m_pc~0 == 1); 9892#L240-20 is_master_triggered_~__retres1~0 := 0; 9890#L251-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9888#L252-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 9886#L627-18 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 9883#L627-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9881#L259-18 assume ~t1_pc~0 == 1; 9878#L260-6 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 9876#L270-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9874#L271-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 9872#L635-18 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 9869#L635-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9868#L278-18 assume !(~t2_pc~0 == 1); 9866#L278-20 is_transmit2_triggered_~__retres1~2 := 0; 9865#L289-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9864#L290-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 9863#L643-18 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 9862#L643-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9861#L297-18 assume ~t3_pc~0 == 1; 8787#L298-6 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 8788#L308-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8790#L309-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 8791#L651-18 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 8841#L651-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8842#L316-18 assume !(~t4_pc~0 == 1); 8929#L316-20 is_transmit4_triggered_~__retres1~4 := 0; 9018#L327-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9033#L328-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 9833#L659-18 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 9832#L659-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9831#L562-3 assume ~M_E~0 == 1;~M_E~0 := 2; 9830#L562-5 assume !(~T1_E~0 == 1); 9829#L567-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 9828#L572-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 8717#L577-3 assume ~T4_E~0 == 1;~T4_E~0 := 2; 8718#L582-3 assume !(~E_M~0 == 1); 8897#L587-3 assume ~E_1~0 == 1;~E_1~0 := 2; 9017#L592-3 assume ~E_2~0 == 1;~E_2~0 := 2; 8825#L597-3 assume ~E_3~0 == 1;~E_3~0 := 2; 8826#L602-3 assume !(~E_4~0 == 1); 8747#L607-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 8734#L376-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 8686#L403-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 9007#L404-1 start_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 9021#L812 assume !(start_simulation_~tmp~3 == 0); 8984#L812-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret12, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 8736#L376-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 8696#L403-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 9011#L404-2 stop_simulation_#t~ret12 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret12;havoc stop_simulation_#t~ret12; 8996#L767 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 8652#L774 stop_simulation_#res := stop_simulation_~__retres2~0; 8597#L775 start_simulation_#t~ret14 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 8598#L825 assume !(start_simulation_~tmp___0~1 != 0); 8744#L793-3 [2018-11-10 06:55:30,697 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:30,697 INFO L82 PathProgramCache]: Analyzing trace with hash 842961413, now seen corresponding path program 1 times [2018-11-10 06:55:30,697 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:30,697 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:30,698 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:30,698 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:55:30,698 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:30,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:55:30,726 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:55:30,726 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:55:30,726 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 06:55:30,726 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 06:55:30,727 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:30,727 INFO L82 PathProgramCache]: Analyzing trace with hash 1012570348, now seen corresponding path program 1 times [2018-11-10 06:55:30,727 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:30,727 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:30,728 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:30,728 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:55:30,728 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:30,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:55:30,762 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:55:30,762 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:55:30,762 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:55:30,762 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 06:55:30,763 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 06:55:30,763 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 06:55:30,763 INFO L87 Difference]: Start difference. First operand 1347 states and 1914 transitions. cyclomatic complexity: 571 Second operand 3 states. [2018-11-10 06:55:30,807 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:55:30,807 INFO L93 Difference]: Finished difference Result 1347 states and 1877 transitions. [2018-11-10 06:55:30,808 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 06:55:30,808 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1347 states and 1877 transitions. [2018-11-10 06:55:30,815 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1274 [2018-11-10 06:55:30,820 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1347 states to 1347 states and 1877 transitions. [2018-11-10 06:55:30,820 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1347 [2018-11-10 06:55:30,821 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1347 [2018-11-10 06:55:30,821 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1347 states and 1877 transitions. [2018-11-10 06:55:30,823 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:55:30,823 INFO L705 BuchiCegarLoop]: Abstraction has 1347 states and 1877 transitions. [2018-11-10 06:55:30,824 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1347 states and 1877 transitions. [2018-11-10 06:55:30,838 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1347 to 1347. [2018-11-10 06:55:30,838 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1347 states. [2018-11-10 06:55:30,841 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1347 states to 1347 states and 1877 transitions. [2018-11-10 06:55:30,841 INFO L728 BuchiCegarLoop]: Abstraction has 1347 states and 1877 transitions. [2018-11-10 06:55:30,842 INFO L608 BuchiCegarLoop]: Abstraction has 1347 states and 1877 transitions. [2018-11-10 06:55:30,842 INFO L442 BuchiCegarLoop]: ======== Iteration 10============ [2018-11-10 06:55:30,842 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1347 states and 1877 transitions. [2018-11-10 06:55:30,847 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1274 [2018-11-10 06:55:30,847 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:55:30,847 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:55:30,848 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:30,848 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:30,848 INFO L793 eck$LassoCheckResult]: Stem: 11667#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 11569#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 11570#L756 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 11391#L336 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11392#L343 assume ~m_i~0 == 1;~m_st~0 := 0; 11439#L343-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 11442#L348-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 11500#L353-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 11395#L358-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 11396#L363-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11688#L504 assume !(~M_E~0 == 0); 11727#L504-2 assume !(~T1_E~0 == 0); 11532#L509-1 assume !(~T2_E~0 == 0); 11533#L514-1 assume !(~T3_E~0 == 0); 11453#L519-1 assume !(~T4_E~0 == 0); 11454#L524-1 assume !(~E_M~0 == 0); 11507#L529-1 assume !(~E_1~0 == 0); 11405#L534-1 assume !(~E_2~0 == 0); 11406#L539-1 assume !(~E_3~0 == 0); 11296#L544-1 assume !(~E_4~0 == 0); 11297#L549-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11599#L240 assume !(~m_pc~0 == 1); 11626#L240-2 is_master_triggered_~__retres1~0 := 0; 11629#L251 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11565#L252 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 11566#L627 assume !(activate_threads_~tmp~1 != 0); 11689#L627-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11393#L259 assume !(~t1_pc~0 == 1); 11374#L259-2 is_transmit1_triggered_~__retres1~1 := 0; 11375#L270 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11397#L271 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 11702#L635 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 11747#L635-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11529#L278 assume !(~t2_pc~0 == 1); 11516#L278-2 is_transmit2_triggered_~__retres1~2 := 0; 11517#L289 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11340#L290 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 11283#L643 assume !(activate_threads_~tmp___1~0 != 0); 11284#L643-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11289#L297 assume !(~t3_pc~0 == 1); 11503#L297-2 is_transmit3_triggered_~__retres1~3 := 0; 11504#L308 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11501#L309 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 11459#L651 assume !(activate_threads_~tmp___2~0 != 0); 11445#L651-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11446#L316 assume !(~t4_pc~0 == 1); 11642#L316-2 is_transmit4_triggered_~__retres1~4 := 0; 11746#L327 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11640#L328 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 11610#L659 assume !(activate_threads_~tmp___3~0 != 0); 11611#L659-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11505#L562 assume !(~M_E~0 == 1); 11506#L562-2 assume !(~T1_E~0 == 1); 11403#L567-1 assume !(~T2_E~0 == 1); 11404#L572-1 assume !(~T3_E~0 == 1); 11294#L577-1 assume !(~T4_E~0 == 1); 11295#L582-1 assume !(~E_M~0 == 1); 11348#L587-1 assume !(~E_1~0 == 1); 11349#L592-1 assume !(~E_2~0 == 1); 11527#L597-1 assume !(~E_3~0 == 1); 11528#L602-1 assume !(~E_4~0 == 1); 11447#L607-1 assume { :end_inline_reset_delta_events } true; 11448#L793-3 [2018-11-10 06:55:30,848 INFO L795 eck$LassoCheckResult]: Loop: 11448#L793-3 assume true; 11654#L793-1 assume !false; 11460#L794 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 11407#L479 assume true; 11380#L413-1 assume !false; 11381#L414 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 11435#L376 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 11384#L403 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 11707#L404 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 11682#L418 assume !(eval_~tmp~0 != 0); 11683#L494 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 12579#L336-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 12578#L504-3 assume !(~M_E~0 == 0); 12577#L504-5 assume !(~T1_E~0 == 0); 12576#L509-3 assume ~T2_E~0 == 0;~T2_E~0 := 1; 12575#L514-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 12574#L519-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 12573#L524-3 assume ~E_M~0 == 0;~E_M~0 := 1; 12572#L529-3 assume !(~E_1~0 == 0); 12571#L534-3 assume ~E_2~0 == 0;~E_2~0 := 1; 12569#L539-3 assume !(~E_3~0 == 0); 12568#L544-3 assume !(~E_4~0 == 0); 12566#L549-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12564#L240-18 assume !(~m_pc~0 == 1); 12562#L240-20 is_master_triggered_~__retres1~0 := 0; 12561#L251-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12560#L252-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 11663#L627-18 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 11664#L627-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11665#L259-18 assume !(~t1_pc~0 == 1); 11697#L259-20 is_transmit1_triggered_~__retres1~1 := 0; 11722#L270-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11698#L271-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 11699#L635-18 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 11737#L635-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11356#L278-18 assume !(~t2_pc~0 == 1); 11353#L278-20 is_transmit2_triggered_~__retres1~2 := 0; 11354#L289-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11308#L290-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 11309#L643-18 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 11414#L643-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11415#L297-18 assume ~t3_pc~0 == 1; 11491#L298-6 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 11492#L308-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11494#L309-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 11495#L651-18 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 11546#L651-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11547#L316-18 assume !(~t4_pc~0 == 1); 11632#L316-20 is_transmit4_triggered_~__retres1~4 := 0; 11728#L327-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11630#L328-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 11567#L659-18 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 11568#L659-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11508#L562-3 assume ~M_E~0 == 1;~M_E~0 := 2; 11499#L562-5 assume !(~T1_E~0 == 1); 11360#L567-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 11361#L572-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 11421#L577-3 assume ~T4_E~0 == 1;~T4_E~0 := 2; 11422#L582-3 assume !(~E_M~0 == 1); 11334#L587-3 assume !(~E_1~0 == 1); 11335#L592-3 assume ~E_2~0 == 1;~E_2~0 := 2; 11530#L597-3 assume ~E_3~0 == 1;~E_3~0 := 2; 11531#L602-3 assume !(~E_4~0 == 1); 11451#L607-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 11438#L376-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 11389#L403-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 11713#L404-1 start_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 11732#L812 assume !(start_simulation_~tmp~3 == 0); 11690#L812-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret12, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 11440#L376-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 11399#L403-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 12389#L404-2 stop_simulation_#t~ret12 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret12;havoc stop_simulation_#t~ret12; 12387#L767 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 11355#L774 stop_simulation_#res := stop_simulation_~__retres2~0; 11298#L775 start_simulation_#t~ret14 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 11299#L825 assume !(start_simulation_~tmp___0~1 != 0); 11448#L793-3 [2018-11-10 06:55:30,848 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:30,849 INFO L82 PathProgramCache]: Analyzing trace with hash 844808455, now seen corresponding path program 1 times [2018-11-10 06:55:30,849 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:30,849 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:30,849 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:30,849 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:55:30,850 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:30,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:55:30,900 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:55:30,900 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:55:30,900 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 06:55:30,900 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 06:55:30,901 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:30,901 INFO L82 PathProgramCache]: Analyzing trace with hash -2035490643, now seen corresponding path program 1 times [2018-11-10 06:55:30,901 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:30,901 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:30,902 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:30,902 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:55:30,902 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:30,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:55:30,926 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:55:30,926 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:55:30,926 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:55:30,926 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 06:55:30,927 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 06:55:30,927 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 06:55:30,927 INFO L87 Difference]: Start difference. First operand 1347 states and 1877 transitions. cyclomatic complexity: 534 Second operand 5 states. [2018-11-10 06:55:31,055 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:55:31,055 INFO L93 Difference]: Finished difference Result 1800 states and 2498 transitions. [2018-11-10 06:55:31,056 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-10 06:55:31,057 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1800 states and 2498 transitions. [2018-11-10 06:55:31,066 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1723 [2018-11-10 06:55:31,073 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1800 states to 1800 states and 2498 transitions. [2018-11-10 06:55:31,074 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1800 [2018-11-10 06:55:31,075 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1800 [2018-11-10 06:55:31,075 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1800 states and 2498 transitions. [2018-11-10 06:55:31,078 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:55:31,078 INFO L705 BuchiCegarLoop]: Abstraction has 1800 states and 2498 transitions. [2018-11-10 06:55:31,080 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1800 states and 2498 transitions. [2018-11-10 06:55:31,097 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1800 to 1353. [2018-11-10 06:55:31,097 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1353 states. [2018-11-10 06:55:31,100 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1353 states to 1353 states and 1860 transitions. [2018-11-10 06:55:31,101 INFO L728 BuchiCegarLoop]: Abstraction has 1353 states and 1860 transitions. [2018-11-10 06:55:31,101 INFO L608 BuchiCegarLoop]: Abstraction has 1353 states and 1860 transitions. [2018-11-10 06:55:31,101 INFO L442 BuchiCegarLoop]: ======== Iteration 11============ [2018-11-10 06:55:31,101 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1353 states and 1860 transitions. [2018-11-10 06:55:31,105 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1280 [2018-11-10 06:55:31,106 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:55:31,106 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:55:31,107 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:31,107 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:31,107 INFO L793 eck$LassoCheckResult]: Stem: 14873#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 14756#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 14757#L756 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 14554#L336 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14555#L343 assume ~m_i~0 == 1;~m_st~0 := 0; 14605#L343-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 14610#L348-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 14671#L353-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 14558#L358-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 14559#L363-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14908#L504 assume !(~M_E~0 == 0); 14971#L504-2 assume !(~T1_E~0 == 0); 14712#L509-1 assume !(~T2_E~0 == 0); 14713#L514-1 assume !(~T3_E~0 == 0); 14620#L519-1 assume !(~T4_E~0 == 0); 14621#L524-1 assume !(~E_M~0 == 0); 14680#L529-1 assume !(~E_1~0 == 0); 14568#L534-1 assume !(~E_2~0 == 0); 14569#L539-1 assume !(~E_3~0 == 0); 14456#L544-1 assume !(~E_4~0 == 0); 14457#L549-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14789#L240 assume !(~m_pc~0 == 1); 14820#L240-2 is_master_triggered_~__retres1~0 := 0; 14823#L251 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14751#L252 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 14752#L627 assume !(activate_threads_~tmp~1 != 0); 14910#L627-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14556#L259 assume !(~t1_pc~0 == 1); 14535#L259-2 is_transmit1_triggered_~__retres1~1 := 0; 14536#L270 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14560#L271 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 14929#L635 assume !(activate_threads_~tmp___0~0 != 0); 15022#L635-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14709#L278 assume !(~t2_pc~0 == 1); 14692#L278-2 is_transmit2_triggered_~__retres1~2 := 0; 14693#L289 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14500#L290 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 14441#L643 assume !(activate_threads_~tmp___1~0 != 0); 14442#L643-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14447#L297 assume !(~t3_pc~0 == 1); 14676#L297-2 is_transmit3_triggered_~__retres1~3 := 0; 14677#L308 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14672#L309 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 14627#L651 assume !(activate_threads_~tmp___2~0 != 0); 14613#L651-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 14614#L316 assume !(~t4_pc~0 == 1); 14838#L316-2 is_transmit4_triggered_~__retres1~4 := 0; 15017#L327 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 14836#L328 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 14805#L659 assume !(activate_threads_~tmp___3~0 != 0); 14806#L659-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14678#L562 assume !(~M_E~0 == 1); 14679#L562-2 assume !(~T1_E~0 == 1); 14566#L567-1 assume !(~T2_E~0 == 1); 14567#L572-1 assume !(~T3_E~0 == 1); 14450#L577-1 assume !(~T4_E~0 == 1); 14451#L582-1 assume !(~E_M~0 == 1); 14506#L587-1 assume !(~E_1~0 == 1); 14507#L592-1 assume !(~E_2~0 == 1); 14706#L597-1 assume !(~E_3~0 == 1); 14707#L602-1 assume !(~E_4~0 == 1); 14615#L607-1 assume { :end_inline_reset_delta_events } true; 14616#L793-3 [2018-11-10 06:55:31,107 INFO L795 eck$LassoCheckResult]: Loop: 14616#L793-3 assume true; 15431#L793-1 assume !false; 15424#L794 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 15418#L479 assume true; 15414#L413-1 assume !false; 15409#L414 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 15397#L376 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 15390#L403 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 15384#L404 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 15379#L418 assume !(eval_~tmp~0 != 0); 15380#L494 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 15716#L336-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 15715#L504-3 assume !(~M_E~0 == 0); 15714#L504-5 assume !(~T1_E~0 == 0); 15713#L509-3 assume ~T2_E~0 == 0;~T2_E~0 := 1; 15712#L514-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 15711#L519-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 15710#L524-3 assume ~E_M~0 == 0;~E_M~0 := 1; 15709#L529-3 assume !(~E_1~0 == 0); 15708#L534-3 assume ~E_2~0 == 0;~E_2~0 := 1; 15707#L539-3 assume !(~E_3~0 == 0); 15706#L544-3 assume !(~E_4~0 == 0); 14796#L549-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14797#L240-18 assume !(~m_pc~0 == 1); 14800#L240-20 is_master_triggered_~__retres1~0 := 0; 15701#L251-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15700#L252-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 15699#L627-18 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 15698#L627-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14959#L259-18 assume !(~t1_pc~0 == 1); 14924#L259-20 is_transmit1_triggered_~__retres1~1 := 0; 14966#L270-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14967#L271-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 14991#L635-18 assume !(activate_threads_~tmp___0~0 != 0); 14992#L635-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14515#L278-18 assume !(~t2_pc~0 == 1); 14516#L278-20 is_transmit2_triggered_~__retres1~2 := 0; 15682#L289-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15681#L290-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 15680#L643-18 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 15678#L643-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15676#L297-18 assume ~t3_pc~0 == 1; 15673#L298-6 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 14866#L308-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14667#L309-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 14668#L651-18 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 14725#L651-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 14726#L316-18 assume !(~t4_pc~0 == 1); 14828#L316-20 is_transmit4_triggered_~__retres1~4 := 0; 14972#L327-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 15377#L328-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 15371#L659-18 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 14755#L659-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14681#L562-3 assume ~M_E~0 == 1;~M_E~0 := 2; 14670#L562-5 assume !(~T1_E~0 == 1); 14520#L567-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 14521#L572-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 14586#L577-3 assume ~T4_E~0 == 1;~T4_E~0 := 2; 14587#L582-3 assume !(~E_M~0 == 1); 15341#L587-3 assume !(~E_1~0 == 1); 15337#L592-3 assume ~E_2~0 == 1;~E_2~0 := 2; 15331#L597-3 assume ~E_3~0 == 1;~E_3~0 := 2; 15327#L602-3 assume !(~E_4~0 == 1); 15324#L607-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 15240#L376-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 14942#L403-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 14943#L404-1 start_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 14980#L812 assume !(start_simulation_~tmp~3 == 0); 14981#L812-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret12, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 15469#L376-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 15464#L403-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 15462#L404-2 stop_simulation_#t~ret12 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret12;havoc stop_simulation_#t~ret12; 15460#L767 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 15458#L774 stop_simulation_#res := stop_simulation_~__retres2~0; 15455#L775 start_simulation_#t~ret14 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 15453#L825 assume !(start_simulation_~tmp___0~1 != 0); 14616#L793-3 [2018-11-10 06:55:31,107 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:31,107 INFO L82 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 1 times [2018-11-10 06:55:31,108 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:31,108 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:31,108 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:31,108 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:55:31,108 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:31,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:55:31,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:55:31,144 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:31,145 INFO L82 PathProgramCache]: Analyzing trace with hash 1362083375, now seen corresponding path program 1 times [2018-11-10 06:55:31,145 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:31,145 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:31,145 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:31,146 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:55:31,146 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:31,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:55:31,189 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:55:31,189 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:55:31,190 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:55:31,190 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 06:55:31,190 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 06:55:31,190 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 06:55:31,190 INFO L87 Difference]: Start difference. First operand 1353 states and 1860 transitions. cyclomatic complexity: 511 Second operand 3 states. [2018-11-10 06:55:31,259 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:55:31,260 INFO L93 Difference]: Finished difference Result 2038 states and 2781 transitions. [2018-11-10 06:55:31,261 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 06:55:31,261 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2038 states and 2781 transitions. [2018-11-10 06:55:31,269 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1919 [2018-11-10 06:55:31,277 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2038 states to 2038 states and 2781 transitions. [2018-11-10 06:55:31,278 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2038 [2018-11-10 06:55:31,279 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2038 [2018-11-10 06:55:31,280 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2038 states and 2781 transitions. [2018-11-10 06:55:31,282 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:55:31,283 INFO L705 BuchiCegarLoop]: Abstraction has 2038 states and 2781 transitions. [2018-11-10 06:55:31,284 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2038 states and 2781 transitions. [2018-11-10 06:55:31,307 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2038 to 2036. [2018-11-10 06:55:31,307 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2036 states. [2018-11-10 06:55:31,311 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2036 states to 2036 states and 2779 transitions. [2018-11-10 06:55:31,312 INFO L728 BuchiCegarLoop]: Abstraction has 2036 states and 2779 transitions. [2018-11-10 06:55:31,312 INFO L608 BuchiCegarLoop]: Abstraction has 2036 states and 2779 transitions. [2018-11-10 06:55:31,312 INFO L442 BuchiCegarLoop]: ======== Iteration 12============ [2018-11-10 06:55:31,312 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2036 states and 2779 transitions. [2018-11-10 06:55:31,318 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1917 [2018-11-10 06:55:31,318 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:55:31,318 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:55:31,319 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:31,319 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:31,320 INFO L793 eck$LassoCheckResult]: Stem: 18236#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 18124#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 18125#L756 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 17942#L336 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17943#L343 assume ~m_i~0 == 1;~m_st~0 := 0; 17992#L343-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 17995#L348-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 18052#L353-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 17947#L358-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 17948#L363-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18255#L504 assume !(~M_E~0 == 0); 18300#L504-2 assume !(~T1_E~0 == 0); 18089#L509-1 assume !(~T2_E~0 == 0); 18090#L514-1 assume !(~T3_E~0 == 0); 18006#L519-1 assume !(~T4_E~0 == 0); 18007#L524-1 assume ~E_M~0 == 0;~E_M~0 := 1; 18298#L529-1 assume !(~E_1~0 == 0); 18359#L534-1 assume !(~E_2~0 == 0); 18260#L539-1 assume !(~E_3~0 == 0); 18261#L544-1 assume !(~E_4~0 == 0); 18358#L549-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 18357#L240 assume !(~m_pc~0 == 1); 18356#L240-2 is_master_triggered_~__retres1~0 := 0; 18355#L251 is_master_triggered_#res := is_master_triggered_~__retres1~0; 18120#L252 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 18121#L627 assume !(activate_threads_~tmp~1 != 0); 18258#L627-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 17944#L259 assume !(~t1_pc~0 == 1); 17945#L259-2 is_transmit1_triggered_~__retres1~1 := 0; 18352#L270 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 18275#L271 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 18276#L635 assume !(activate_threads_~tmp___0~0 != 0); 18351#L635-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 18084#L278 assume !(~t2_pc~0 == 1); 18085#L278-2 is_transmit2_triggered_~__retres1~2 := 0; 18088#L289 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 17897#L290 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 17898#L643 assume !(activate_threads_~tmp___1~0 != 0); 18349#L643-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 18230#L297 assume !(~t3_pc~0 == 1); 18231#L297-2 is_transmit3_triggered_~__retres1~3 := 0; 18234#L308 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 18053#L309 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 18054#L651 assume !(activate_threads_~tmp___2~0 != 0); 18338#L651-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 18337#L316 assume !(~t4_pc~0 == 1); 18335#L316-2 is_transmit4_triggered_~__retres1~4 := 0; 18334#L327 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 18333#L328 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 18332#L659 assume !(activate_threads_~tmp___3~0 != 0); 18331#L659-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18330#L562 assume !(~M_E~0 == 1); 18329#L562-2 assume !(~T1_E~0 == 1); 18328#L567-1 assume !(~T2_E~0 == 1); 18327#L572-1 assume !(~T3_E~0 == 1); 18326#L577-1 assume !(~T4_E~0 == 1); 18168#L582-1 assume ~E_M~0 == 1;~E_M~0 := 2; 17903#L587-1 assume !(~E_1~0 == 1); 17904#L592-1 assume !(~E_2~0 == 1); 18082#L597-1 assume !(~E_3~0 == 1); 18083#L602-1 assume !(~E_4~0 == 1); 18000#L607-1 assume { :end_inline_reset_delta_events } true; 18001#L793-3 [2018-11-10 06:55:31,320 INFO L795 eck$LassoCheckResult]: Loop: 18001#L793-3 assume true; 18661#L793-1 assume !false; 18656#L794 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 18652#L479 assume true; 18650#L413-1 assume !false; 18648#L414 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 18644#L376 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 18640#L403 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 18636#L404 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 18633#L418 assume !(eval_~tmp~0 != 0); 18634#L494 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 18939#L336-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 18938#L504-3 assume !(~M_E~0 == 0); 18937#L504-5 assume !(~T1_E~0 == 0); 18936#L509-3 assume ~T2_E~0 == 0;~T2_E~0 := 1; 18935#L514-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 18934#L519-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 18931#L524-3 assume ~E_M~0 == 0;~E_M~0 := 1; 18929#L529-3 assume !(~E_1~0 == 0); 18927#L534-3 assume ~E_2~0 == 0;~E_2~0 := 1; 18925#L539-3 assume !(~E_3~0 == 0); 18923#L544-3 assume !(~E_4~0 == 0); 18921#L549-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 18919#L240-18 assume !(~m_pc~0 == 1); 18917#L240-20 is_master_triggered_~__retres1~0 := 0; 18915#L251-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 18913#L252-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 18910#L627-18 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 18908#L627-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 18906#L259-18 assume !(~t1_pc~0 == 1); 18903#L259-20 is_transmit1_triggered_~__retres1~1 := 0; 18901#L270-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 18899#L271-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 18897#L635-18 assume !(activate_threads_~tmp___0~0 != 0); 18895#L635-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 18893#L278-18 assume !(~t2_pc~0 == 1); 18891#L278-20 is_transmit2_triggered_~__retres1~2 := 0; 18889#L289-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 18887#L290-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 18885#L643-18 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 18884#L643-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 18881#L297-18 assume ~t3_pc~0 == 1; 18878#L298-6 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 18876#L308-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 18874#L309-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 18872#L651-18 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 18871#L651-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 18863#L316-18 assume !(~t4_pc~0 == 1); 18860#L316-20 is_transmit4_triggered_~__retres1~4 := 0; 18857#L327-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 18854#L328-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 18851#L659-18 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 18848#L659-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18845#L562-3 assume ~M_E~0 == 1;~M_E~0 := 2; 18841#L562-5 assume !(~T1_E~0 == 1); 18837#L567-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 18823#L572-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 18410#L577-3 assume ~T4_E~0 == 1;~T4_E~0 := 2; 18411#L582-3 assume ~E_M~0 == 1;~E_M~0 := 2; 18399#L587-3 assume !(~E_1~0 == 1); 18400#L592-3 assume ~E_2~0 == 1;~E_2~0 := 2; 18391#L597-3 assume ~E_3~0 == 1;~E_3~0 := 2; 18392#L602-3 assume !(~E_4~0 == 1); 18383#L607-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 18384#L376-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 18371#L403-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 18372#L404-1 start_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 18362#L812 assume !(start_simulation_~tmp~3 == 0); 18363#L812-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret12, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 18701#L376-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 18694#L403-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 18690#L404-2 stop_simulation_#t~ret12 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret12;havoc stop_simulation_#t~ret12; 18686#L767 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 18679#L774 stop_simulation_#res := stop_simulation_~__retres2~0; 18674#L775 start_simulation_#t~ret14 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 18670#L825 assume !(start_simulation_~tmp___0~1 != 0); 18001#L793-3 [2018-11-10 06:55:31,320 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:31,320 INFO L82 PathProgramCache]: Analyzing trace with hash 1842238409, now seen corresponding path program 1 times [2018-11-10 06:55:31,320 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:31,320 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:31,321 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:31,321 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:55:31,321 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:31,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:55:31,364 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:55:31,365 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:55:31,365 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 06:55:31,365 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 06:55:31,365 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:31,365 INFO L82 PathProgramCache]: Analyzing trace with hash -938739215, now seen corresponding path program 1 times [2018-11-10 06:55:31,365 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:31,365 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:31,366 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:31,366 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:55:31,366 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:31,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:55:31,389 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:55:31,389 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:55:31,389 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 06:55:31,390 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 06:55:31,390 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 06:55:31,390 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 06:55:31,390 INFO L87 Difference]: Start difference. First operand 2036 states and 2779 transitions. cyclomatic complexity: 747 Second operand 3 states. [2018-11-10 06:55:31,455 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:55:31,455 INFO L93 Difference]: Finished difference Result 1353 states and 1833 transitions. [2018-11-10 06:55:31,456 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 06:55:31,457 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1353 states and 1833 transitions. [2018-11-10 06:55:31,461 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1280 [2018-11-10 06:55:31,466 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1353 states to 1353 states and 1833 transitions. [2018-11-10 06:55:31,466 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1353 [2018-11-10 06:55:31,467 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1353 [2018-11-10 06:55:31,467 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1353 states and 1833 transitions. [2018-11-10 06:55:31,469 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:55:31,469 INFO L705 BuchiCegarLoop]: Abstraction has 1353 states and 1833 transitions. [2018-11-10 06:55:31,470 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1353 states and 1833 transitions. [2018-11-10 06:55:31,484 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1353 to 1353. [2018-11-10 06:55:31,484 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1353 states. [2018-11-10 06:55:31,487 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1353 states to 1353 states and 1833 transitions. [2018-11-10 06:55:31,487 INFO L728 BuchiCegarLoop]: Abstraction has 1353 states and 1833 transitions. [2018-11-10 06:55:31,488 INFO L608 BuchiCegarLoop]: Abstraction has 1353 states and 1833 transitions. [2018-11-10 06:55:31,488 INFO L442 BuchiCegarLoop]: ======== Iteration 13============ [2018-11-10 06:55:31,488 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1353 states and 1833 transitions. [2018-11-10 06:55:31,491 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1280 [2018-11-10 06:55:31,492 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:55:31,492 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:55:31,492 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:31,493 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:31,493 INFO L793 eck$LassoCheckResult]: Stem: 21615#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 21518#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 21519#L756 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 21340#L336 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21341#L343 assume ~m_i~0 == 1;~m_st~0 := 0; 21388#L343-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 21391#L348-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 21449#L353-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 21344#L358-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 21345#L363-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21634#L504 assume !(~M_E~0 == 0); 21677#L504-2 assume !(~T1_E~0 == 0); 21482#L509-1 assume !(~T2_E~0 == 0); 21483#L514-1 assume !(~T3_E~0 == 0); 21402#L519-1 assume !(~T4_E~0 == 0); 21403#L524-1 assume !(~E_M~0 == 0); 21456#L529-1 assume !(~E_1~0 == 0); 21354#L534-1 assume !(~E_2~0 == 0); 21355#L539-1 assume !(~E_3~0 == 0); 21251#L544-1 assume !(~E_4~0 == 0); 21252#L549-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 21544#L240 assume !(~m_pc~0 == 1); 21576#L240-2 is_master_triggered_~__retres1~0 := 0; 21579#L251 is_master_triggered_#res := is_master_triggered_~__retres1~0; 21514#L252 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 21515#L627 assume !(activate_threads_~tmp~1 != 0); 21635#L627-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 21342#L259 assume !(~t1_pc~0 == 1); 21322#L259-2 is_transmit1_triggered_~__retres1~1 := 0; 21323#L270 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 21346#L271 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 21647#L635 assume !(activate_threads_~tmp___0~0 != 0); 21702#L635-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 21479#L278 assume !(~t2_pc~0 == 1); 21466#L278-2 is_transmit2_triggered_~__retres1~2 := 0; 21467#L289 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 21295#L290 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 21238#L643 assume !(activate_threads_~tmp___1~0 != 0); 21239#L643-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 21244#L297 assume !(~t3_pc~0 == 1); 21452#L297-2 is_transmit3_triggered_~__retres1~3 := 0; 21453#L308 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 21450#L309 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 21407#L651 assume !(activate_threads_~tmp___2~0 != 0); 21394#L651-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 21395#L316 assume !(~t4_pc~0 == 1); 21592#L316-2 is_transmit4_triggered_~__retres1~4 := 0; 21700#L327 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 21590#L328 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 21556#L659 assume !(activate_threads_~tmp___3~0 != 0); 21557#L659-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21454#L562 assume !(~M_E~0 == 1); 21455#L562-2 assume !(~T1_E~0 == 1); 21352#L567-1 assume !(~T2_E~0 == 1); 21353#L572-1 assume !(~T3_E~0 == 1); 21247#L577-1 assume !(~T4_E~0 == 1); 21248#L582-1 assume !(~E_M~0 == 1); 21300#L587-1 assume !(~E_1~0 == 1); 21301#L592-1 assume !(~E_2~0 == 1); 21477#L597-1 assume !(~E_3~0 == 1); 21478#L602-1 assume !(~E_4~0 == 1); 21396#L607-1 assume { :end_inline_reset_delta_events } true; 21397#L793-3 [2018-11-10 06:55:31,493 INFO L795 eck$LassoCheckResult]: Loop: 21397#L793-3 assume true; 22207#L793-1 assume !false; 22193#L794 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 22190#L479 assume true; 22188#L413-1 assume !false; 22186#L414 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 22160#L376 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 22156#L403 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 22150#L404 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 22146#L418 assume !(eval_~tmp~0 != 0); 22147#L494 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 22447#L336-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 22446#L504-3 assume !(~M_E~0 == 0); 22445#L504-5 assume !(~T1_E~0 == 0); 22444#L509-3 assume ~T2_E~0 == 0;~T2_E~0 := 1; 22443#L514-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 22442#L519-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 22440#L524-3 assume !(~E_M~0 == 0); 22438#L529-3 assume !(~E_1~0 == 0); 22436#L534-3 assume ~E_2~0 == 0;~E_2~0 := 1; 22434#L539-3 assume !(~E_3~0 == 0); 22432#L544-3 assume !(~E_4~0 == 0); 22430#L549-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 22428#L240-18 assume !(~m_pc~0 == 1); 22426#L240-20 is_master_triggered_~__retres1~0 := 0; 22424#L251-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 22422#L252-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 22420#L627-18 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 22418#L627-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22415#L259-18 assume !(~t1_pc~0 == 1); 22412#L259-20 is_transmit1_triggered_~__retres1~1 := 0; 22410#L270-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22409#L271-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 22406#L635-18 assume !(activate_threads_~tmp___0~0 != 0); 22404#L635-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22403#L278-18 assume !(~t2_pc~0 == 1); 22402#L278-20 is_transmit2_triggered_~__retres1~2 := 0; 22401#L289-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22400#L290-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 22399#L643-18 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 22397#L643-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22395#L297-18 assume ~t3_pc~0 == 1; 22392#L298-6 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 22390#L308-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 22388#L309-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 22386#L651-18 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 22383#L651-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 22379#L316-18 assume !(~t4_pc~0 == 1); 22377#L316-20 is_transmit4_triggered_~__retres1~4 := 0; 22375#L327-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 22373#L328-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 22371#L659-18 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 22369#L659-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22367#L562-3 assume ~M_E~0 == 1;~M_E~0 := 2; 22365#L562-5 assume !(~T1_E~0 == 1); 22363#L567-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 22361#L572-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 22359#L577-3 assume ~T4_E~0 == 1;~T4_E~0 := 2; 22358#L582-3 assume !(~E_M~0 == 1); 22355#L587-3 assume !(~E_1~0 == 1); 22353#L592-3 assume ~E_2~0 == 1;~E_2~0 := 2; 22351#L597-3 assume ~E_3~0 == 1;~E_3~0 := 2; 22349#L602-3 assume !(~E_4~0 == 1); 22347#L607-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 22345#L376-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 22337#L403-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 22273#L404-1 start_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 22272#L812 assume !(start_simulation_~tmp~3 == 0); 22270#L812-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret12, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 22258#L376-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 22246#L403-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 22241#L404-2 stop_simulation_#t~ret12 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret12;havoc stop_simulation_#t~ret12; 22236#L767 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 22229#L774 stop_simulation_#res := stop_simulation_~__retres2~0; 22224#L775 start_simulation_#t~ret14 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 22218#L825 assume !(start_simulation_~tmp___0~1 != 0); 21397#L793-3 [2018-11-10 06:55:31,493 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:31,493 INFO L82 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 2 times [2018-11-10 06:55:31,493 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:31,494 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:31,494 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:31,494 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:55:31,494 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:31,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:55:31,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:55:31,513 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:31,514 INFO L82 PathProgramCache]: Analyzing trace with hash 1922783153, now seen corresponding path program 1 times [2018-11-10 06:55:31,514 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:31,514 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:31,515 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:31,515 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 06:55:31,515 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:31,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:55:31,554 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:55:31,555 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:55:31,555 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 06:55:31,555 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 06:55:31,555 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 06:55:31,555 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 06:55:31,555 INFO L87 Difference]: Start difference. First operand 1353 states and 1833 transitions. cyclomatic complexity: 484 Second operand 5 states. [2018-11-10 06:55:31,645 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:55:31,645 INFO L93 Difference]: Finished difference Result 2397 states and 3206 transitions. [2018-11-10 06:55:31,646 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-10 06:55:31,646 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2397 states and 3206 transitions. [2018-11-10 06:55:31,653 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2316 [2018-11-10 06:55:31,661 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2397 states to 2397 states and 3206 transitions. [2018-11-10 06:55:31,661 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2397 [2018-11-10 06:55:31,663 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2397 [2018-11-10 06:55:31,663 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2397 states and 3206 transitions. [2018-11-10 06:55:31,666 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:55:31,666 INFO L705 BuchiCegarLoop]: Abstraction has 2397 states and 3206 transitions. [2018-11-10 06:55:31,668 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2397 states and 3206 transitions. [2018-11-10 06:55:31,685 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2397 to 1365. [2018-11-10 06:55:31,685 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1365 states. [2018-11-10 06:55:31,688 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1365 states to 1365 states and 1845 transitions. [2018-11-10 06:55:31,688 INFO L728 BuchiCegarLoop]: Abstraction has 1365 states and 1845 transitions. [2018-11-10 06:55:31,688 INFO L608 BuchiCegarLoop]: Abstraction has 1365 states and 1845 transitions. [2018-11-10 06:55:31,688 INFO L442 BuchiCegarLoop]: ======== Iteration 14============ [2018-11-10 06:55:31,688 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1365 states and 1845 transitions. [2018-11-10 06:55:31,691 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1292 [2018-11-10 06:55:31,692 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:55:31,692 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:55:31,692 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:31,692 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:31,693 INFO L793 eck$LassoCheckResult]: Stem: 25377#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 25282#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 25283#L756 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 25107#L336 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25108#L343 assume ~m_i~0 == 1;~m_st~0 := 0; 25154#L343-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 25157#L348-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 25214#L353-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 25111#L358-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 25112#L363-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25394#L504 assume !(~M_E~0 == 0); 25434#L504-2 assume !(~T1_E~0 == 0); 25247#L509-1 assume !(~T2_E~0 == 0); 25248#L514-1 assume !(~T3_E~0 == 0); 25167#L519-1 assume !(~T4_E~0 == 0); 25168#L524-1 assume !(~E_M~0 == 0); 25221#L529-1 assume !(~E_1~0 == 0); 25121#L534-1 assume !(~E_2~0 == 0); 25122#L539-1 assume !(~E_3~0 == 0); 25017#L544-1 assume !(~E_4~0 == 0); 25018#L549-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 25308#L240 assume !(~m_pc~0 == 1); 25337#L240-2 is_master_triggered_~__retres1~0 := 0; 25339#L251 is_master_triggered_#res := is_master_triggered_~__retres1~0; 25278#L252 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 25279#L627 assume !(activate_threads_~tmp~1 != 0); 25395#L627-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 25109#L259 assume !(~t1_pc~0 == 1); 25090#L259-2 is_transmit1_triggered_~__retres1~1 := 0; 25091#L270 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 25113#L271 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 25407#L635 assume !(activate_threads_~tmp___0~0 != 0); 25456#L635-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 25244#L278 assume !(~t2_pc~0 == 1); 25231#L278-2 is_transmit2_triggered_~__retres1~2 := 0; 25232#L289 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 25061#L290 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 25004#L643 assume !(activate_threads_~tmp___1~0 != 0); 25005#L643-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 25008#L297 assume !(~t3_pc~0 == 1); 25217#L297-2 is_transmit3_triggered_~__retres1~3 := 0; 25218#L308 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 25215#L309 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 25173#L651 assume !(activate_threads_~tmp___2~0 != 0); 25160#L651-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 25161#L316 assume !(~t4_pc~0 == 1); 25354#L316-2 is_transmit4_triggered_~__retres1~4 := 0; 25455#L327 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 25352#L328 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 25320#L659 assume !(activate_threads_~tmp___3~0 != 0); 25321#L659-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25219#L562 assume !(~M_E~0 == 1); 25220#L562-2 assume !(~T1_E~0 == 1); 25119#L567-1 assume !(~T2_E~0 == 1); 25120#L572-1 assume !(~T3_E~0 == 1); 25011#L577-1 assume !(~T4_E~0 == 1); 25012#L582-1 assume !(~E_M~0 == 1); 25066#L587-1 assume !(~E_1~0 == 1); 25067#L592-1 assume !(~E_2~0 == 1); 25242#L597-1 assume !(~E_3~0 == 1); 25243#L602-1 assume !(~E_4~0 == 1); 25162#L607-1 assume { :end_inline_reset_delta_events } true; 25163#L793-3 [2018-11-10 06:55:31,693 INFO L795 eck$LassoCheckResult]: Loop: 25163#L793-3 assume true; 25705#L793-1 assume !false; 25674#L794 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 25670#L479 assume true; 25609#L413-1 assume !false; 25580#L414 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 25575#L376 assume !(~m_st~0 == 0); 25569#L380 assume !(~t1_st~0 == 0); 25565#L384 assume !(~t2_st~0 == 0); 25562#L388 assume !(~t3_st~0 == 0); 25558#L392 assume !(~t4_st~0 == 0);exists_runnable_thread_~__retres1~5 := 0; 25555#L403 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 25526#L404 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 25511#L418 assume !(eval_~tmp~0 != 0); 25493#L494 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 25494#L336-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 25435#L504-3 assume !(~M_E~0 == 0); 25436#L504-5 assume !(~T1_E~0 == 0); 25797#L509-3 assume ~T2_E~0 == 0;~T2_E~0 := 1; 25459#L514-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 25146#L519-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 25147#L524-3 assume !(~E_M~0 == 0); 25410#L529-3 assume !(~E_1~0 == 0); 25794#L534-3 assume ~E_2~0 == 0;~E_2~0 := 1; 25793#L539-3 assume !(~E_3~0 == 0); 25792#L544-3 assume !(~E_4~0 == 0); 25791#L549-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 25790#L240-18 assume !(~m_pc~0 == 1); 25789#L240-20 is_master_triggered_~__retres1~0 := 0; 25788#L251-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 25787#L252-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 25786#L627-18 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 25785#L627-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 25784#L259-18 assume !(~t1_pc~0 == 1); 25782#L259-20 is_transmit1_triggered_~__retres1~1 := 0; 25781#L270-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 25780#L271-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 25779#L635-18 assume !(activate_threads_~tmp___0~0 != 0); 25778#L635-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 25777#L278-18 assume !(~t2_pc~0 == 1); 25776#L278-20 is_transmit2_triggered_~__retres1~2 := 0; 25775#L289-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 25774#L290-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 25773#L643-18 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 25772#L643-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 25771#L297-18 assume ~t3_pc~0 == 1; 25769#L298-6 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 25768#L308-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 25767#L309-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 25766#L651-18 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 25765#L651-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 25763#L316-18 assume !(~t4_pc~0 == 1); 25762#L316-20 is_transmit4_triggered_~__retres1~4 := 0; 25761#L327-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 25760#L328-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 25759#L659-18 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 25758#L659-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25757#L562-3 assume ~M_E~0 == 1;~M_E~0 := 2; 25756#L562-5 assume !(~T1_E~0 == 1); 25755#L567-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 25754#L572-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 25753#L577-3 assume ~T4_E~0 == 1;~T4_E~0 := 2; 25752#L582-3 assume !(~E_M~0 == 1); 25751#L587-3 assume !(~E_1~0 == 1); 25750#L592-3 assume ~E_2~0 == 1;~E_2~0 := 2; 25749#L597-3 assume ~E_3~0 == 1;~E_3~0 := 2; 25748#L602-3 assume !(~E_4~0 == 1); 25747#L607-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 25746#L376-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 25740#L403-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 25739#L404-1 start_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 25734#L812 assume !(start_simulation_~tmp~3 == 0); 25724#L812-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret12, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 25722#L376-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 25717#L403-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 25713#L404-2 stop_simulation_#t~ret12 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret12;havoc stop_simulation_#t~ret12; 25711#L767 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 25709#L774 stop_simulation_#res := stop_simulation_~__retres2~0; 25707#L775 start_simulation_#t~ret14 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 25706#L825 assume !(start_simulation_~tmp___0~1 != 0); 25163#L793-3 [2018-11-10 06:55:31,693 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:31,693 INFO L82 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 3 times [2018-11-10 06:55:31,693 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:31,693 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:31,694 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:31,694 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:55:31,694 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:31,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:55:31,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:55:31,711 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:31,711 INFO L82 PathProgramCache]: Analyzing trace with hash -1574088667, now seen corresponding path program 1 times [2018-11-10 06:55:31,711 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:31,711 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:31,712 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:31,712 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 06:55:31,712 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:31,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:55:31,753 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:55:31,753 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:55:31,754 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 06:55:31,754 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 06:55:31,754 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 06:55:31,754 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 06:55:31,754 INFO L87 Difference]: Start difference. First operand 1365 states and 1845 transitions. cyclomatic complexity: 484 Second operand 5 states. [2018-11-10 06:55:31,869 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:55:31,869 INFO L93 Difference]: Finished difference Result 1775 states and 2390 transitions. [2018-11-10 06:55:31,870 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-10 06:55:31,870 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1775 states and 2390 transitions. [2018-11-10 06:55:31,876 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1698 [2018-11-10 06:55:31,883 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1775 states to 1775 states and 2390 transitions. [2018-11-10 06:55:31,883 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1775 [2018-11-10 06:55:31,885 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1775 [2018-11-10 06:55:31,885 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1775 states and 2390 transitions. [2018-11-10 06:55:31,887 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:55:31,887 INFO L705 BuchiCegarLoop]: Abstraction has 1775 states and 2390 transitions. [2018-11-10 06:55:31,889 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1775 states and 2390 transitions. [2018-11-10 06:55:31,909 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1775 to 1371. [2018-11-10 06:55:31,909 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1371 states. [2018-11-10 06:55:31,913 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1371 states to 1371 states and 1828 transitions. [2018-11-10 06:55:31,913 INFO L728 BuchiCegarLoop]: Abstraction has 1371 states and 1828 transitions. [2018-11-10 06:55:31,913 INFO L608 BuchiCegarLoop]: Abstraction has 1371 states and 1828 transitions. [2018-11-10 06:55:31,913 INFO L442 BuchiCegarLoop]: ======== Iteration 15============ [2018-11-10 06:55:31,913 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1371 states and 1828 transitions. [2018-11-10 06:55:31,920 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1298 [2018-11-10 06:55:31,920 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:55:31,920 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:55:31,921 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:31,922 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:31,922 INFO L793 eck$LassoCheckResult]: Stem: 28613#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 28471#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 28472#L756 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 28267#L336 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28268#L343 assume ~m_i~0 == 1;~m_st~0 := 0; 28321#L343-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 28326#L348-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 28387#L353-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 28271#L358-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 28272#L363-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28641#L504 assume !(~M_E~0 == 0); 28698#L504-2 assume !(~T1_E~0 == 0); 28430#L509-1 assume !(~T2_E~0 == 0); 28431#L514-1 assume !(~T3_E~0 == 0); 28336#L519-1 assume !(~T4_E~0 == 0); 28337#L524-1 assume !(~E_M~0 == 0); 28397#L529-1 assume !(~E_1~0 == 0); 28281#L534-1 assume !(~E_2~0 == 0); 28282#L539-1 assume !(~E_3~0 == 0); 28170#L544-1 assume !(~E_4~0 == 0); 28171#L549-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 28499#L240 assume !(~m_pc~0 == 1); 28545#L240-2 is_master_triggered_~__retres1~0 := 0; 28548#L251 is_master_triggered_#res := is_master_triggered_~__retres1~0; 28466#L252 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 28467#L627 assume !(activate_threads_~tmp~1 != 0); 28642#L627-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 28269#L259 assume !(~t1_pc~0 == 1); 28250#L259-2 is_transmit1_triggered_~__retres1~1 := 0; 28251#L270 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 28273#L271 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 28661#L635 assume !(activate_threads_~tmp___0~0 != 0); 28759#L635-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 28427#L278 assume !(~t2_pc~0 == 1); 28411#L278-2 is_transmit2_triggered_~__retres1~2 := 0; 28412#L289 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 28215#L290 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 28155#L643 assume !(activate_threads_~tmp___1~0 != 0); 28156#L643-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 28161#L297 assume !(~t3_pc~0 == 1); 28393#L297-2 is_transmit3_triggered_~__retres1~3 := 0; 28394#L308 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 28388#L309 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 28343#L651 assume !(activate_threads_~tmp___2~0 != 0); 28329#L651-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 28330#L316 assume !(~t4_pc~0 == 1); 28567#L316-2 is_transmit4_triggered_~__retres1~4 := 0; 28753#L327 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 28565#L328 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 28517#L659 assume !(activate_threads_~tmp___3~0 != 0); 28518#L659-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28395#L562 assume !(~M_E~0 == 1); 28396#L562-2 assume !(~T1_E~0 == 1); 28279#L567-1 assume !(~T2_E~0 == 1); 28280#L572-1 assume !(~T3_E~0 == 1); 28164#L577-1 assume !(~T4_E~0 == 1); 28165#L582-1 assume !(~E_M~0 == 1); 28222#L587-1 assume !(~E_1~0 == 1); 28223#L592-1 assume !(~E_2~0 == 1); 28422#L597-1 assume !(~E_3~0 == 1); 28423#L602-1 assume !(~E_4~0 == 1); 28331#L607-1 assume { :end_inline_reset_delta_events } true; 28332#L793-3 [2018-11-10 06:55:31,922 INFO L795 eck$LassoCheckResult]: Loop: 28332#L793-3 assume true; 29203#L793-1 assume !false; 29200#L794 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 29197#L479 assume true; 29196#L413-1 assume !false; 29195#L414 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 29192#L376 assume !(~m_st~0 == 0); 29193#L380 assume !(~t1_st~0 == 0); 29194#L384 assume !(~t2_st~0 == 0); 29189#L388 assume !(~t3_st~0 == 0); 29191#L392 assume !(~t4_st~0 == 0);exists_runnable_thread_~__retres1~5 := 0; 29188#L403 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 29185#L404 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 29186#L418 assume !(eval_~tmp~0 != 0); 29365#L494 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 29363#L336-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 29361#L504-3 assume !(~M_E~0 == 0); 29359#L504-5 assume !(~T1_E~0 == 0); 29357#L509-3 assume ~T2_E~0 == 0;~T2_E~0 := 1; 29353#L514-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 29351#L519-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 29349#L524-3 assume !(~E_M~0 == 0); 29347#L529-3 assume !(~E_1~0 == 0); 29344#L534-3 assume ~E_2~0 == 0;~E_2~0 := 1; 29342#L539-3 assume !(~E_3~0 == 0); 29339#L544-3 assume !(~E_4~0 == 0); 28508#L549-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 28509#L240-18 assume !(~m_pc~0 == 1); 28510#L240-20 is_master_triggered_~__retres1~0 := 0; 28511#L251-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 28481#L252-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 28482#L627-18 assume !(activate_threads_~tmp~1 != 0); 28611#L627-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 28612#L259-18 assume !(~t1_pc~0 == 1); 28686#L259-20 is_transmit1_triggered_~__retres1~1 := 0; 28687#L270-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 28657#L271-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 28658#L635-18 assume !(activate_threads_~tmp___0~0 != 0); 28724#L635-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 28231#L278-18 assume !(~t2_pc~0 == 1); 28232#L278-20 is_transmit2_triggered_~__retres1~2 := 0; 28402#L289-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 28403#L290-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 28292#L643-18 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 28293#L643-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 28294#L297-18 assume ~t3_pc~0 == 1; 28379#L298-6 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 28380#L308-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 28382#L309-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 28383#L651-18 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 29416#L651-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 28716#L316-18 assume !(~t4_pc~0 == 1); 28554#L316-20 is_transmit4_triggered_~__retres1~4 := 0; 28738#L327-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 28739#L328-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 28468#L659-18 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 28469#L659-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28470#L562-3 assume ~M_E~0 == 1;~M_E~0 := 2; 29413#L562-5 assume !(~T1_E~0 == 1); 28236#L567-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 28237#L572-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 28303#L577-3 assume ~T4_E~0 == 1;~T4_E~0 := 2; 28304#L582-3 assume !(~E_M~0 == 1); 28208#L587-3 assume !(~E_1~0 == 1); 28209#L592-3 assume ~E_2~0 == 1;~E_2~0 := 2; 28428#L597-3 assume ~E_3~0 == 1;~E_3~0 := 2; 28429#L602-3 assume !(~E_4~0 == 1); 28335#L607-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 28322#L376-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 28265#L403-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 28674#L404-1 start_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 28712#L812 assume !(start_simulation_~tmp~3 == 0); 28713#L812-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret12, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 29233#L376-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 29227#L403-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 29224#L404-2 stop_simulation_#t~ret12 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret12;havoc stop_simulation_#t~ret12; 29222#L767 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 29218#L774 stop_simulation_#res := stop_simulation_~__retres2~0; 29213#L775 start_simulation_#t~ret14 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 29210#L825 assume !(start_simulation_~tmp___0~1 != 0); 28332#L793-3 [2018-11-10 06:55:31,922 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:31,923 INFO L82 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 4 times [2018-11-10 06:55:31,923 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:31,923 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:31,924 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:31,924 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:55:31,924 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:31,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:55:31,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:55:31,941 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:31,942 INFO L82 PathProgramCache]: Analyzing trace with hash -1589607385, now seen corresponding path program 1 times [2018-11-10 06:55:31,942 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:31,942 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:31,943 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:31,943 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 06:55:31,943 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:31,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:55:31,971 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:55:31,972 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:55:31,972 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:55:31,972 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 06:55:31,972 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 06:55:31,972 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 06:55:31,973 INFO L87 Difference]: Start difference. First operand 1371 states and 1828 transitions. cyclomatic complexity: 461 Second operand 3 states. [2018-11-10 06:55:32,001 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:55:32,002 INFO L93 Difference]: Finished difference Result 2037 states and 2675 transitions. [2018-11-10 06:55:32,003 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 06:55:32,003 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2037 states and 2675 transitions. [2018-11-10 06:55:32,012 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1957 [2018-11-10 06:55:32,021 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2037 states to 2037 states and 2675 transitions. [2018-11-10 06:55:32,021 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2037 [2018-11-10 06:55:32,022 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2037 [2018-11-10 06:55:32,023 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2037 states and 2675 transitions. [2018-11-10 06:55:32,025 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:55:32,025 INFO L705 BuchiCegarLoop]: Abstraction has 2037 states and 2675 transitions. [2018-11-10 06:55:32,027 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2037 states and 2675 transitions. [2018-11-10 06:55:32,054 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2037 to 2037. [2018-11-10 06:55:32,054 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2037 states. [2018-11-10 06:55:32,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2037 states to 2037 states and 2675 transitions. [2018-11-10 06:55:32,059 INFO L728 BuchiCegarLoop]: Abstraction has 2037 states and 2675 transitions. [2018-11-10 06:55:32,059 INFO L608 BuchiCegarLoop]: Abstraction has 2037 states and 2675 transitions. [2018-11-10 06:55:32,059 INFO L442 BuchiCegarLoop]: ======== Iteration 16============ [2018-11-10 06:55:32,059 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2037 states and 2675 transitions. [2018-11-10 06:55:32,066 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1957 [2018-11-10 06:55:32,066 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:55:32,066 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:55:32,067 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:32,067 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:32,067 INFO L793 eck$LassoCheckResult]: Stem: 31986#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 31868#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 31869#L756 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 31679#L336 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31680#L343 assume ~m_i~0 == 1;~m_st~0 := 0; 31729#L343-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 31734#L348-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 31795#L353-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 31683#L358-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 31684#L363-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32013#L504 assume !(~M_E~0 == 0); 32059#L504-2 assume !(~T1_E~0 == 0); 31831#L509-1 assume !(~T2_E~0 == 0); 31832#L514-1 assume !(~T3_E~0 == 0); 31745#L519-1 assume !(~T4_E~0 == 0); 31746#L524-1 assume !(~E_M~0 == 0); 31802#L529-1 assume !(~E_1~0 == 0); 31693#L534-1 assume !(~E_2~0 == 0); 31694#L539-1 assume !(~E_3~0 == 0); 31584#L544-1 assume !(~E_4~0 == 0); 31585#L549-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 31893#L240 assume !(~m_pc~0 == 1); 31931#L240-2 is_master_triggered_~__retres1~0 := 0; 31933#L251 is_master_triggered_#res := is_master_triggered_~__retres1~0; 31864#L252 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 31865#L627 assume !(activate_threads_~tmp~1 != 0); 32014#L627-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 31681#L259 assume !(~t1_pc~0 == 1); 31661#L259-2 is_transmit1_triggered_~__retres1~1 := 0; 31662#L270 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 31685#L271 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 32028#L635 assume !(activate_threads_~tmp___0~0 != 0); 32093#L635-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 31828#L278 assume !(~t2_pc~0 == 1); 31812#L278-2 is_transmit2_triggered_~__retres1~2 := 0; 31813#L289 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 31629#L290 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 31569#L643 assume !(activate_threads_~tmp___1~0 != 0); 31570#L643-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 31575#L297 assume !(~t3_pc~0 == 1); 31798#L297-2 is_transmit3_triggered_~__retres1~3 := 0; 31799#L308 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 31796#L309 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 31751#L651 assume !(activate_threads_~tmp___2~0 != 0); 31737#L651-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 31738#L316 assume !(~t4_pc~0 == 1); 31951#L316-2 is_transmit4_triggered_~__retres1~4 := 0; 32091#L327 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 31949#L328 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 31909#L659 assume !(activate_threads_~tmp___3~0 != 0); 31910#L659-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31800#L562 assume !(~M_E~0 == 1); 31801#L562-2 assume !(~T1_E~0 == 1); 31691#L567-1 assume !(~T2_E~0 == 1); 31692#L572-1 assume !(~T3_E~0 == 1); 31578#L577-1 assume !(~T4_E~0 == 1); 31579#L582-1 assume !(~E_M~0 == 1); 31636#L587-1 assume !(~E_1~0 == 1); 31637#L592-1 assume !(~E_2~0 == 1); 31825#L597-1 assume !(~E_3~0 == 1); 31826#L602-1 assume !(~E_4~0 == 1); 31739#L607-1 assume { :end_inline_reset_delta_events } true; 31740#L793-3 assume true; 33503#L793-1 assume !false; 33457#L794 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 33454#L479 [2018-11-10 06:55:32,068 INFO L795 eck$LassoCheckResult]: Loop: 33454#L479 assume true; 33453#L413-1 assume !false; 33452#L414 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 33450#L376 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 33451#L403 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 33449#L404 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 33394#L418 assume eval_~tmp~0 != 0; 33362#L418-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 32098#L426 assume !(eval_~tmp_ndt_1~0 != 0); 32099#L423 assume !(~t1_st~0 == 0); 32616#L437 assume !(~t2_st~0 == 0); 32614#L451 assume !(~t3_st~0 == 0); 33458#L465 assume !(~t4_st~0 == 0); 33454#L479 [2018-11-10 06:55:32,068 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:32,068 INFO L82 PathProgramCache]: Analyzing trace with hash 1231592563, now seen corresponding path program 1 times [2018-11-10 06:55:32,068 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:32,068 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:32,069 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:32,069 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:55:32,069 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:32,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:55:32,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:55:32,089 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:32,090 INFO L82 PathProgramCache]: Analyzing trace with hash -1018803263, now seen corresponding path program 1 times [2018-11-10 06:55:32,090 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:32,090 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:32,091 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:32,091 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:55:32,091 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:32,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:55:32,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:55:32,097 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:32,097 INFO L82 PathProgramCache]: Analyzing trace with hash -1098975089, now seen corresponding path program 1 times [2018-11-10 06:55:32,097 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:32,097 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:32,098 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:32,098 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:55:32,098 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:32,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:55:32,134 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:55:32,135 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:55:32,135 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:55:32,210 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 06:55:32,210 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 06:55:32,211 INFO L87 Difference]: Start difference. First operand 2037 states and 2675 transitions. cyclomatic complexity: 644 Second operand 3 states. [2018-11-10 06:55:32,368 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:55:32,368 INFO L93 Difference]: Finished difference Result 3436 states and 4477 transitions. [2018-11-10 06:55:32,369 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 06:55:32,369 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3436 states and 4477 transitions. [2018-11-10 06:55:32,380 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 3282 [2018-11-10 06:55:32,392 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3436 states to 3436 states and 4477 transitions. [2018-11-10 06:55:32,392 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3436 [2018-11-10 06:55:32,394 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3436 [2018-11-10 06:55:32,394 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3436 states and 4477 transitions. [2018-11-10 06:55:32,397 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:55:32,397 INFO L705 BuchiCegarLoop]: Abstraction has 3436 states and 4477 transitions. [2018-11-10 06:55:32,400 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3436 states and 4477 transitions. [2018-11-10 06:55:32,429 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3436 to 3436. [2018-11-10 06:55:32,429 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3436 states. [2018-11-10 06:55:32,435 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3436 states to 3436 states and 4477 transitions. [2018-11-10 06:55:32,435 INFO L728 BuchiCegarLoop]: Abstraction has 3436 states and 4477 transitions. [2018-11-10 06:55:32,435 INFO L608 BuchiCegarLoop]: Abstraction has 3436 states and 4477 transitions. [2018-11-10 06:55:32,435 INFO L442 BuchiCegarLoop]: ======== Iteration 17============ [2018-11-10 06:55:32,435 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3436 states and 4477 transitions. [2018-11-10 06:55:32,444 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 3282 [2018-11-10 06:55:32,444 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:55:32,444 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:55:32,445 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:32,445 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:32,445 INFO L793 eck$LassoCheckResult]: Stem: 37459#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 37344#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 37345#L756 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 37159#L336 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 37160#L343 assume ~m_i~0 == 1;~m_st~0 := 0; 37205#L343-2 assume !(~t1_i~0 == 1);~t1_st~0 := 2; 37210#L348-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 37271#L353-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 37163#L358-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 37164#L363-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37484#L504 assume !(~M_E~0 == 0); 37537#L504-2 assume !(~T1_E~0 == 0); 37308#L509-1 assume !(~T2_E~0 == 0); 37309#L514-1 assume !(~T3_E~0 == 0); 37221#L519-1 assume !(~T4_E~0 == 0); 37222#L524-1 assume !(~E_M~0 == 0); 37278#L529-1 assume !(~E_1~0 == 0); 37172#L534-1 assume !(~E_2~0 == 0); 37173#L539-1 assume !(~E_3~0 == 0); 37066#L544-1 assume !(~E_4~0 == 0); 37067#L549-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 37371#L240 assume !(~m_pc~0 == 1); 37414#L240-2 is_master_triggered_~__retres1~0 := 0; 37417#L251 is_master_triggered_#res := is_master_triggered_~__retres1~0; 37340#L252 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 37341#L627 assume !(activate_threads_~tmp~1 != 0); 37486#L627-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 37161#L259 assume !(~t1_pc~0 == 1); 37142#L259-2 is_transmit1_triggered_~__retres1~1 := 0; 37143#L270 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 37165#L271 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 37502#L635 assume !(activate_threads_~tmp___0~0 != 0); 37562#L635-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 37305#L278 assume !(~t2_pc~0 == 1); 37290#L278-2 is_transmit2_triggered_~__retres1~2 := 0; 37291#L289 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 37110#L290 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 37111#L643 assume !(activate_threads_~tmp___1~0 != 0); 37056#L643-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 37057#L297 assume !(~t3_pc~0 == 1); 37274#L297-2 is_transmit3_triggered_~__retres1~3 := 0; 37275#L308 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 37272#L309 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 37228#L651 assume !(activate_threads_~tmp___2~0 != 0); 37214#L651-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 37215#L316 assume !(~t4_pc~0 == 1); 37434#L316-2 is_transmit4_triggered_~__retres1~4 := 0; 37559#L327 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 37432#L328 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 37391#L659 assume !(activate_threads_~tmp___3~0 != 0); 37392#L659-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37276#L562 assume !(~M_E~0 == 1); 37277#L562-2 assume !(~T1_E~0 == 1); 37170#L567-1 assume !(~T2_E~0 == 1); 37171#L572-1 assume !(~T3_E~0 == 1); 39062#L577-1 assume !(~T4_E~0 == 1); 39060#L582-1 assume !(~E_M~0 == 1); 37118#L587-1 assume !(~E_1~0 == 1); 37119#L592-1 assume !(~E_2~0 == 1); 37303#L597-1 assume !(~E_3~0 == 1); 37304#L602-1 assume !(~E_4~0 == 1); 39047#L607-1 assume { :end_inline_reset_delta_events } true; 39045#L793-3 assume true; 39025#L793-1 assume !false; 39018#L794 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 39009#L479 [2018-11-10 06:55:32,445 INFO L795 eck$LassoCheckResult]: Loop: 39009#L479 assume true; 39003#L413-1 assume !false; 38998#L414 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 38993#L376 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 38987#L403 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 38981#L404 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 38973#L418 assume eval_~tmp~0 != 0; 38966#L418-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 38960#L426 assume !(eval_~tmp_ndt_1~0 != 0); 38952#L423 assume !(~t1_st~0 == 0); 38947#L437 assume !(~t2_st~0 == 0); 38940#L451 assume !(~t3_st~0 == 0); 39019#L465 assume !(~t4_st~0 == 0); 39009#L479 [2018-11-10 06:55:32,446 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:32,446 INFO L82 PathProgramCache]: Analyzing trace with hash 1433416497, now seen corresponding path program 1 times [2018-11-10 06:55:32,446 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:32,446 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:32,447 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:32,447 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:55:32,447 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:32,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:55:32,476 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:55:32,476 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:55:32,476 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:55:32,476 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 06:55:32,476 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:32,476 INFO L82 PathProgramCache]: Analyzing trace with hash -1018803263, now seen corresponding path program 2 times [2018-11-10 06:55:32,477 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:32,477 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:32,477 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:32,477 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:55:32,477 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:32,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:55:32,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:55:32,556 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 06:55:32,557 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 06:55:32,557 INFO L87 Difference]: Start difference. First operand 3436 states and 4477 transitions. cyclomatic complexity: 1047 Second operand 3 states. [2018-11-10 06:55:32,569 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:55:32,569 INFO L93 Difference]: Finished difference Result 3374 states and 4395 transitions. [2018-11-10 06:55:32,570 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 06:55:32,570 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3374 states and 4395 transitions. [2018-11-10 06:55:32,580 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 3282 [2018-11-10 06:55:32,591 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3374 states to 3374 states and 4395 transitions. [2018-11-10 06:55:32,591 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3374 [2018-11-10 06:55:32,593 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3374 [2018-11-10 06:55:32,593 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3374 states and 4395 transitions. [2018-11-10 06:55:32,595 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:55:32,596 INFO L705 BuchiCegarLoop]: Abstraction has 3374 states and 4395 transitions. [2018-11-10 06:55:32,598 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3374 states and 4395 transitions. [2018-11-10 06:55:32,624 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3374 to 3374. [2018-11-10 06:55:32,624 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3374 states. [2018-11-10 06:55:32,629 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3374 states to 3374 states and 4395 transitions. [2018-11-10 06:55:32,630 INFO L728 BuchiCegarLoop]: Abstraction has 3374 states and 4395 transitions. [2018-11-10 06:55:32,630 INFO L608 BuchiCegarLoop]: Abstraction has 3374 states and 4395 transitions. [2018-11-10 06:55:32,630 INFO L442 BuchiCegarLoop]: ======== Iteration 18============ [2018-11-10 06:55:32,630 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3374 states and 4395 transitions. [2018-11-10 06:55:32,638 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 3282 [2018-11-10 06:55:32,638 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:55:32,638 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:55:32,639 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:32,639 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:32,639 INFO L793 eck$LassoCheckResult]: Stem: 44251#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 44152#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 44153#L756 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 43974#L336 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 43975#L343 assume ~m_i~0 == 1;~m_st~0 := 0; 44020#L343-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 44023#L348-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 44080#L353-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 43978#L358-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 43979#L363-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 44271#L504 assume !(~M_E~0 == 0); 44314#L504-2 assume !(~T1_E~0 == 0); 44118#L509-1 assume !(~T2_E~0 == 0); 44119#L514-1 assume !(~T3_E~0 == 0); 44034#L519-1 assume !(~T4_E~0 == 0); 44035#L524-1 assume !(~E_M~0 == 0); 44087#L529-1 assume !(~E_1~0 == 0); 43987#L534-1 assume !(~E_2~0 == 0); 43988#L539-1 assume !(~E_3~0 == 0); 43881#L544-1 assume !(~E_4~0 == 0); 43882#L549-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 44178#L240 assume !(~m_pc~0 == 1); 44212#L240-2 is_master_triggered_~__retres1~0 := 0; 44215#L251 is_master_triggered_#res := is_master_triggered_~__retres1~0; 44148#L252 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 44149#L627 assume !(activate_threads_~tmp~1 != 0); 44272#L627-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 43976#L259 assume !(~t1_pc~0 == 1); 43958#L259-2 is_transmit1_triggered_~__retres1~1 := 0; 43959#L270 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 43980#L271 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 44285#L635 assume !(activate_threads_~tmp___0~0 != 0); 44343#L635-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 44115#L278 assume !(~t2_pc~0 == 1); 44099#L278-2 is_transmit2_triggered_~__retres1~2 := 0; 44100#L289 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 43925#L290 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 43868#L643 assume !(activate_threads_~tmp___1~0 != 0); 43869#L643-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 43874#L297 assume !(~t3_pc~0 == 1); 44083#L297-2 is_transmit3_triggered_~__retres1~3 := 0; 44084#L308 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 44081#L309 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 44039#L651 assume !(activate_threads_~tmp___2~0 != 0); 44026#L651-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 44027#L316 assume !(~t4_pc~0 == 1); 44228#L316-2 is_transmit4_triggered_~__retres1~4 := 0; 44342#L327 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 44226#L328 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 44192#L659 assume !(activate_threads_~tmp___3~0 != 0); 44193#L659-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44085#L562 assume !(~M_E~0 == 1); 44086#L562-2 assume !(~T1_E~0 == 1); 43985#L567-1 assume !(~T2_E~0 == 1); 43986#L572-1 assume !(~T3_E~0 == 1); 43879#L577-1 assume !(~T4_E~0 == 1); 43880#L582-1 assume !(~E_M~0 == 1); 43933#L587-1 assume !(~E_1~0 == 1); 43934#L592-1 assume !(~E_2~0 == 1); 44113#L597-1 assume !(~E_3~0 == 1); 44114#L602-1 assume !(~E_4~0 == 1); 44028#L607-1 assume { :end_inline_reset_delta_events } true; 44029#L793-3 assume true; 44984#L793-1 assume !false; 44944#L794 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 44938#L479 [2018-11-10 06:55:32,639 INFO L795 eck$LassoCheckResult]: Loop: 44938#L479 assume true; 44933#L413-1 assume !false; 44928#L414 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 44921#L376 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 44915#L403 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 44910#L404 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 44905#L418 assume eval_~tmp~0 != 0; 44901#L418-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 44897#L426 assume !(eval_~tmp_ndt_1~0 != 0); 44896#L423 assume ~t1_st~0 == 0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 44745#L440 assume !(eval_~tmp_ndt_2~0 != 0); 44895#L437 assume !(~t2_st~0 == 0); 44990#L451 assume !(~t3_st~0 == 0); 44945#L465 assume !(~t4_st~0 == 0); 44938#L479 [2018-11-10 06:55:32,639 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:32,639 INFO L82 PathProgramCache]: Analyzing trace with hash 1231592563, now seen corresponding path program 2 times [2018-11-10 06:55:32,639 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:32,640 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:32,640 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:32,640 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 06:55:32,640 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:32,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:55:32,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:55:32,656 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:32,656 INFO L82 PathProgramCache]: Analyzing trace with hash -1666258566, now seen corresponding path program 1 times [2018-11-10 06:55:32,656 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:32,656 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:32,657 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:32,657 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 06:55:32,657 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:32,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:55:32,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:55:32,662 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:32,662 INFO L82 PathProgramCache]: Analyzing trace with hash 143382124, now seen corresponding path program 1 times [2018-11-10 06:55:32,662 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:32,662 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:32,663 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:32,663 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:55:32,663 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:32,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:55:32,698 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:55:32,698 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:55:32,699 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:55:32,752 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 06:55:32,752 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 06:55:32,752 INFO L87 Difference]: Start difference. First operand 3374 states and 4395 transitions. cyclomatic complexity: 1027 Second operand 3 states. [2018-11-10 06:55:32,799 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:55:32,800 INFO L93 Difference]: Finished difference Result 4541 states and 5891 transitions. [2018-11-10 06:55:32,801 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 06:55:32,801 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4541 states and 5891 transitions. [2018-11-10 06:55:32,814 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4445 [2018-11-10 06:55:32,827 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4541 states to 4541 states and 5891 transitions. [2018-11-10 06:55:32,827 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4541 [2018-11-10 06:55:32,830 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4541 [2018-11-10 06:55:32,830 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4541 states and 5891 transitions. [2018-11-10 06:55:32,833 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:55:32,834 INFO L705 BuchiCegarLoop]: Abstraction has 4541 states and 5891 transitions. [2018-11-10 06:55:32,837 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4541 states and 5891 transitions. [2018-11-10 06:55:32,871 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4541 to 4389. [2018-11-10 06:55:32,871 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4389 states. [2018-11-10 06:55:32,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4389 states to 4389 states and 5699 transitions. [2018-11-10 06:55:32,879 INFO L728 BuchiCegarLoop]: Abstraction has 4389 states and 5699 transitions. [2018-11-10 06:55:32,879 INFO L608 BuchiCegarLoop]: Abstraction has 4389 states and 5699 transitions. [2018-11-10 06:55:32,879 INFO L442 BuchiCegarLoop]: ======== Iteration 19============ [2018-11-10 06:55:32,879 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4389 states and 5699 transitions. [2018-11-10 06:55:32,890 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4293 [2018-11-10 06:55:32,890 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:55:32,890 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:55:32,891 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:32,891 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:32,891 INFO L793 eck$LassoCheckResult]: Stem: 52196#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 52085#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 52086#L756 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 51897#L336 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 51898#L343 assume ~m_i~0 == 1;~m_st~0 := 0; 51946#L343-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 51949#L348-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 52010#L353-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 51901#L358-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 51902#L363-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 52224#L504 assume !(~M_E~0 == 0); 52273#L504-2 assume !(~T1_E~0 == 0); 52046#L509-1 assume !(~T2_E~0 == 0); 52047#L514-1 assume !(~T3_E~0 == 0); 51961#L519-1 assume !(~T4_E~0 == 0); 51962#L524-1 assume !(~E_M~0 == 0); 52017#L529-1 assume !(~E_1~0 == 0); 51910#L534-1 assume !(~E_2~0 == 0); 51911#L539-1 assume !(~E_3~0 == 0); 51804#L544-1 assume !(~E_4~0 == 0); 51805#L549-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 52112#L240 assume !(~m_pc~0 == 1); 52148#L240-2 is_master_triggered_~__retres1~0 := 0; 52151#L251 is_master_triggered_#res := is_master_triggered_~__retres1~0; 52079#L252 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 52080#L627 assume !(activate_threads_~tmp~1 != 0); 52225#L627-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 51899#L259 assume !(~t1_pc~0 == 1); 51881#L259-2 is_transmit1_triggered_~__retres1~1 := 0; 51882#L270 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 51903#L271 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 52240#L635 assume !(activate_threads_~tmp___0~0 != 0); 52300#L635-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 52043#L278 assume !(~t2_pc~0 == 1); 52028#L278-2 is_transmit2_triggered_~__retres1~2 := 0; 52029#L289 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 51849#L290 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 51791#L643 assume !(activate_threads_~tmp___1~0 != 0); 51792#L643-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 51797#L297 assume !(~t3_pc~0 == 1); 52013#L297-2 is_transmit3_triggered_~__retres1~3 := 0; 52014#L308 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 52011#L309 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 51966#L651 assume !(activate_threads_~tmp___2~0 != 0); 51952#L651-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 51953#L316 assume !(~t4_pc~0 == 1); 52167#L316-2 is_transmit4_triggered_~__retres1~4 := 0; 52298#L327 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 52164#L328 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 52128#L659 assume !(activate_threads_~tmp___3~0 != 0); 52129#L659-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52015#L562 assume !(~M_E~0 == 1); 52016#L562-2 assume !(~T1_E~0 == 1); 51908#L567-1 assume !(~T2_E~0 == 1); 51909#L572-1 assume !(~T3_E~0 == 1); 51802#L577-1 assume !(~T4_E~0 == 1); 51803#L582-1 assume !(~E_M~0 == 1); 51857#L587-1 assume !(~E_1~0 == 1); 51858#L592-1 assume !(~E_2~0 == 1); 52041#L597-1 assume !(~E_3~0 == 1); 52042#L602-1 assume !(~E_4~0 == 1); 51954#L607-1 assume { :end_inline_reset_delta_events } true; 51955#L793-3 assume true; 53237#L793-1 assume !false; 53234#L794 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 53228#L479 [2018-11-10 06:55:32,891 INFO L795 eck$LassoCheckResult]: Loop: 53228#L479 assume true; 53229#L413-1 assume !false; 53222#L414 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 53223#L376 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 53214#L403 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 53215#L404 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 53208#L418 assume eval_~tmp~0 != 0; 53209#L418-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 53200#L426 assume !(eval_~tmp_ndt_1~0 != 0); 53201#L423 assume ~t1_st~0 == 0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 53165#L440 assume !(eval_~tmp_ndt_2~0 != 0); 53278#L437 assume ~t2_st~0 == 0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 53498#L454 assume !(eval_~tmp_ndt_3~0 != 0); 53242#L451 assume !(~t3_st~0 == 0); 53239#L465 assume !(~t4_st~0 == 0); 53228#L479 [2018-11-10 06:55:32,891 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:32,891 INFO L82 PathProgramCache]: Analyzing trace with hash 1231592563, now seen corresponding path program 3 times [2018-11-10 06:55:32,892 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:32,892 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:32,892 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:32,892 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:55:32,892 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:32,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:55:32,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:55:32,908 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:32,908 INFO L82 PathProgramCache]: Analyzing trace with hash -119185070, now seen corresponding path program 1 times [2018-11-10 06:55:32,908 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:32,908 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:32,909 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:32,909 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 06:55:32,909 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:32,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:55:32,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:55:32,913 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:32,913 INFO L82 PathProgramCache]: Analyzing trace with hash 145101472, now seen corresponding path program 1 times [2018-11-10 06:55:32,914 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:32,914 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:32,914 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:32,914 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:55:32,914 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:32,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:55:32,937 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:55:32,937 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:55:32,938 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:55:33,012 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 06:55:33,012 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 06:55:33,012 INFO L87 Difference]: Start difference. First operand 4389 states and 5699 transitions. cyclomatic complexity: 1316 Second operand 3 states. [2018-11-10 06:55:33,223 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:55:33,223 INFO L93 Difference]: Finished difference Result 7857 states and 10151 transitions. [2018-11-10 06:55:33,233 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 06:55:33,233 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7857 states and 10151 transitions. [2018-11-10 06:55:33,262 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 7733 [2018-11-10 06:55:33,284 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7857 states to 7857 states and 10151 transitions. [2018-11-10 06:55:33,284 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7857 [2018-11-10 06:55:33,289 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7857 [2018-11-10 06:55:33,289 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7857 states and 10151 transitions. [2018-11-10 06:55:33,295 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:55:33,295 INFO L705 BuchiCegarLoop]: Abstraction has 7857 states and 10151 transitions. [2018-11-10 06:55:33,300 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7857 states and 10151 transitions. [2018-11-10 06:55:33,358 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7857 to 7569. [2018-11-10 06:55:33,358 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7569 states. [2018-11-10 06:55:33,368 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7569 states to 7569 states and 9791 transitions. [2018-11-10 06:55:33,368 INFO L728 BuchiCegarLoop]: Abstraction has 7569 states and 9791 transitions. [2018-11-10 06:55:33,368 INFO L608 BuchiCegarLoop]: Abstraction has 7569 states and 9791 transitions. [2018-11-10 06:55:33,368 INFO L442 BuchiCegarLoop]: ======== Iteration 20============ [2018-11-10 06:55:33,368 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7569 states and 9791 transitions. [2018-11-10 06:55:33,388 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 7445 [2018-11-10 06:55:33,388 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:55:33,389 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:55:33,389 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:33,389 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:33,390 INFO L793 eck$LassoCheckResult]: Stem: 64471#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 64355#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 64356#L756 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 64153#L336 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 64154#L343 assume ~m_i~0 == 1;~m_st~0 := 0; 64207#L343-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 64211#L348-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 64274#L353-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 64157#L358-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 64158#L363-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 64498#L504 assume !(~M_E~0 == 0); 64560#L504-2 assume !(~T1_E~0 == 0); 64311#L509-1 assume !(~T2_E~0 == 0); 64312#L514-1 assume !(~T3_E~0 == 0); 64221#L519-1 assume !(~T4_E~0 == 0); 64222#L524-1 assume !(~E_M~0 == 0); 64281#L529-1 assume !(~E_1~0 == 0); 64166#L534-1 assume !(~E_2~0 == 0); 64167#L539-1 assume !(~E_3~0 == 0); 64058#L544-1 assume !(~E_4~0 == 0); 64059#L549-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 64382#L240 assume !(~m_pc~0 == 1); 64417#L240-2 is_master_triggered_~__retres1~0 := 0; 64420#L251 is_master_triggered_#res := is_master_triggered_~__retres1~0; 64350#L252 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 64351#L627 assume !(activate_threads_~tmp~1 != 0); 64500#L627-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 64155#L259 assume !(~t1_pc~0 == 1); 64134#L259-2 is_transmit1_triggered_~__retres1~1 := 0; 64135#L270 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 64159#L271 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 64514#L635 assume !(activate_threads_~tmp___0~0 != 0); 64589#L635-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 64308#L278 assume !(~t2_pc~0 == 1); 64295#L278-2 is_transmit2_triggered_~__retres1~2 := 0; 64296#L289 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 64102#L290 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 64043#L643 assume !(activate_threads_~tmp___1~0 != 0); 64044#L643-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 64049#L297 assume !(~t3_pc~0 == 1); 64277#L297-2 is_transmit3_triggered_~__retres1~3 := 0; 64278#L308 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 64275#L309 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 64229#L651 assume !(activate_threads_~tmp___2~0 != 0); 64214#L651-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 64215#L316 assume !(~t4_pc~0 == 1); 64436#L316-2 is_transmit4_triggered_~__retres1~4 := 0; 64586#L327 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 64434#L328 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 64398#L659 assume !(activate_threads_~tmp___3~0 != 0); 64399#L659-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64279#L562 assume !(~M_E~0 == 1); 64280#L562-2 assume !(~T1_E~0 == 1); 64164#L567-1 assume !(~T2_E~0 == 1); 64165#L572-1 assume !(~T3_E~0 == 1); 64052#L577-1 assume !(~T4_E~0 == 1); 64053#L582-1 assume !(~E_M~0 == 1); 64109#L587-1 assume !(~E_1~0 == 1); 64110#L592-1 assume !(~E_2~0 == 1); 64306#L597-1 assume !(~E_3~0 == 1); 64307#L602-1 assume !(~E_4~0 == 1); 64216#L607-1 assume { :end_inline_reset_delta_events } true; 64217#L793-3 assume true; 66257#L793-1 assume !false; 66252#L794 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 66246#L479 [2018-11-10 06:55:33,390 INFO L795 eck$LassoCheckResult]: Loop: 66246#L479 assume true; 66241#L413-1 assume !false; 66238#L414 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 66234#L376 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 66232#L403 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 66226#L404 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 66223#L418 assume eval_~tmp~0 != 0; 66220#L418-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 66216#L426 assume !(eval_~tmp_ndt_1~0 != 0); 66212#L423 assume ~t1_st~0 == 0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 66196#L440 assume !(eval_~tmp_ndt_2~0 != 0); 66209#L437 assume ~t2_st~0 == 0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 66266#L454 assume !(eval_~tmp_ndt_3~0 != 0); 66262#L451 assume ~t3_st~0 == 0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 65759#L468 assume !(eval_~tmp_ndt_4~0 != 0); 66253#L465 assume !(~t4_st~0 == 0); 66246#L479 [2018-11-10 06:55:33,390 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:33,390 INFO L82 PathProgramCache]: Analyzing trace with hash 1231592563, now seen corresponding path program 4 times [2018-11-10 06:55:33,390 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:33,390 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:33,391 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:33,391 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:55:33,391 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:33,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:55:33,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:55:33,412 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:33,412 INFO L82 PathProgramCache]: Analyzing trace with hash 600077289, now seen corresponding path program 1 times [2018-11-10 06:55:33,412 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:33,412 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:33,413 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:33,413 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 06:55:33,413 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:33,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:55:33,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:55:33,420 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:33,420 INFO L82 PathProgramCache]: Analyzing trace with hash 203025499, now seen corresponding path program 1 times [2018-11-10 06:55:33,420 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:33,420 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:33,421 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:33,421 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:55:33,421 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:33,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:55:33,471 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:55:33,471 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:55:33,471 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 06:55:33,563 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 06:55:33,563 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 06:55:33,563 INFO L87 Difference]: Start difference. First operand 7569 states and 9791 transitions. cyclomatic complexity: 2228 Second operand 3 states. [2018-11-10 06:55:33,626 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:55:33,626 INFO L93 Difference]: Finished difference Result 13005 states and 16733 transitions. [2018-11-10 06:55:33,627 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 06:55:33,627 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13005 states and 16733 transitions. [2018-11-10 06:55:33,655 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 12825 [2018-11-10 06:55:33,680 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13005 states to 13005 states and 16733 transitions. [2018-11-10 06:55:33,680 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13005 [2018-11-10 06:55:33,686 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13005 [2018-11-10 06:55:33,686 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13005 states and 16733 transitions. [2018-11-10 06:55:33,692 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:55:33,692 INFO L705 BuchiCegarLoop]: Abstraction has 13005 states and 16733 transitions. [2018-11-10 06:55:33,699 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13005 states and 16733 transitions. [2018-11-10 06:55:33,772 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13005 to 12765. [2018-11-10 06:55:33,772 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12765 states. [2018-11-10 06:55:33,788 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12765 states to 12765 states and 16493 transitions. [2018-11-10 06:55:33,788 INFO L728 BuchiCegarLoop]: Abstraction has 12765 states and 16493 transitions. [2018-11-10 06:55:33,788 INFO L608 BuchiCegarLoop]: Abstraction has 12765 states and 16493 transitions. [2018-11-10 06:55:33,788 INFO L442 BuchiCegarLoop]: ======== Iteration 21============ [2018-11-10 06:55:33,789 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12765 states and 16493 transitions. [2018-11-10 06:55:33,818 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 12585 [2018-11-10 06:55:33,818 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:55:33,818 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:55:33,819 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:33,819 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:55:33,819 INFO L793 eck$LassoCheckResult]: Stem: 85039#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 84923#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 84924#L756 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 84734#L336 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 84735#L343 assume ~m_i~0 == 1;~m_st~0 := 0; 84783#L343-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 84787#L348-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 84846#L353-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 84738#L358-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 84739#L363-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 85062#L504 assume !(~M_E~0 == 0); 85118#L504-2 assume !(~T1_E~0 == 0); 84883#L509-1 assume !(~T2_E~0 == 0); 84884#L514-1 assume !(~T3_E~0 == 0); 84797#L519-1 assume !(~T4_E~0 == 0); 84798#L524-1 assume !(~E_M~0 == 0); 84853#L529-1 assume !(~E_1~0 == 0); 84747#L534-1 assume !(~E_2~0 == 0); 84748#L539-1 assume !(~E_3~0 == 0); 84640#L544-1 assume !(~E_4~0 == 0); 84641#L549-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 84950#L240 assume !(~m_pc~0 == 1); 84987#L240-2 is_master_triggered_~__retres1~0 := 0; 84989#L251 is_master_triggered_#res := is_master_triggered_~__retres1~0; 84917#L252 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 84918#L627 assume !(activate_threads_~tmp~1 != 0); 85063#L627-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 84736#L259 assume !(~t1_pc~0 == 1); 84714#L259-2 is_transmit1_triggered_~__retres1~1 := 0; 84715#L270 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 84740#L271 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 85080#L635 assume !(activate_threads_~tmp___0~0 != 0); 85152#L635-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 84880#L278 assume !(~t2_pc~0 == 1); 84867#L278-2 is_transmit2_triggered_~__retres1~2 := 0; 84868#L289 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 84684#L290 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 84625#L643 assume !(activate_threads_~tmp___1~0 != 0); 84626#L643-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 84631#L297 assume !(~t3_pc~0 == 1); 84849#L297-2 is_transmit3_triggered_~__retres1~3 := 0; 84850#L308 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 84847#L309 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 84804#L651 assume !(activate_threads_~tmp___2~0 != 0); 84790#L651-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 84791#L316 assume !(~t4_pc~0 == 1); 85006#L316-2 is_transmit4_triggered_~__retres1~4 := 0; 85151#L327 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 85004#L328 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 84967#L659 assume !(activate_threads_~tmp___3~0 != 0); 84968#L659-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 84851#L562 assume !(~M_E~0 == 1); 84852#L562-2 assume !(~T1_E~0 == 1); 84745#L567-1 assume !(~T2_E~0 == 1); 84746#L572-1 assume !(~T3_E~0 == 1); 84634#L577-1 assume !(~T4_E~0 == 1); 84635#L582-1 assume !(~E_M~0 == 1); 84689#L587-1 assume !(~E_1~0 == 1); 84690#L592-1 assume !(~E_2~0 == 1); 84878#L597-1 assume !(~E_3~0 == 1); 84879#L602-1 assume !(~E_4~0 == 1); 84792#L607-1 assume { :end_inline_reset_delta_events } true; 84793#L793-3 assume true; 88913#L793-1 assume !false; 88910#L794 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 88654#L479 [2018-11-10 06:55:33,819 INFO L795 eck$LassoCheckResult]: Loop: 88654#L479 assume true; 88904#L413-1 assume !false; 88905#L414 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 88897#L376 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~5 := 1; 88898#L403 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 88891#L404 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 88892#L418 assume eval_~tmp~0 != 0; 88884#L418-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 88885#L426 assume !(eval_~tmp_ndt_1~0 != 0); 88618#L423 assume ~t1_st~0 == 0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 88614#L440 assume !(eval_~tmp_ndt_2~0 != 0); 88612#L437 assume ~t2_st~0 == 0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 88609#L454 assume !(eval_~tmp_ndt_3~0 != 0); 88607#L451 assume ~t3_st~0 == 0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 88592#L468 assume !(eval_~tmp_ndt_4~0 != 0); 88606#L465 assume ~t4_st~0 == 0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 88435#L482 assume !(eval_~tmp_ndt_5~0 != 0); 88654#L479 [2018-11-10 06:55:33,819 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:33,819 INFO L82 PathProgramCache]: Analyzing trace with hash 1231592563, now seen corresponding path program 5 times [2018-11-10 06:55:33,820 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:33,820 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:33,820 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:33,820 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:55:33,821 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:33,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:55:33,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:55:33,837 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:33,837 INFO L82 PathProgramCache]: Analyzing trace with hash 1422523107, now seen corresponding path program 1 times [2018-11-10 06:55:33,837 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:33,837 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:33,838 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:33,838 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 06:55:33,838 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:33,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:55:33,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:55:33,843 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:55:33,843 INFO L82 PathProgramCache]: Analyzing trace with hash 1998819505, now seen corresponding path program 1 times [2018-11-10 06:55:33,844 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:55:33,844 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:55:33,844 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:33,844 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:55:33,845 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:55:33,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:55:33,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:55:33,995 WARN L179 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 41 DAG size of output: 39 [2018-11-10 06:55:34,310 WARN L179 SmtUtils]: Spent 288.00 ms on a formula simplification. DAG size of input: 167 DAG size of output: 112 [2018-11-10 06:55:34,426 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 10.11 06:55:34 BoogieIcfgContainer [2018-11-10 06:55:34,426 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2018-11-10 06:55:34,427 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-10 06:55:34,427 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-10 06:55:34,427 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-10 06:55:34,427 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.11 06:55:29" (3/4) ... [2018-11-10 06:55:34,434 INFO L141 WitnessPrinter]: Generating witness for non-termination counterexample [2018-11-10 06:55:34,488 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_49fa53c9-7f6f-4c3d-8e2d-784bb3e03274/bin-2019/uautomizer/witness.graphml [2018-11-10 06:55:34,488 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-10 06:55:34,489 INFO L168 Benchmark]: Toolchain (without parser) took 6356.26 ms. Allocated memory was 1.0 GB in the beginning and 1.4 GB in the end (delta: 333.4 MB). Free memory was 959.1 MB in the beginning and 1.1 GB in the end (delta: -172.4 MB). Peak memory consumption was 161.1 MB. Max. memory is 11.5 GB. [2018-11-10 06:55:34,489 INFO L168 Benchmark]: CDTParser took 0.12 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-10 06:55:34,489 INFO L168 Benchmark]: CACSL2BoogieTranslator took 240.16 ms. Allocated memory is still 1.0 GB. Free memory was 959.1 MB in the beginning and 940.3 MB in the end (delta: 18.8 MB). Peak memory consumption was 18.8 MB. Max. memory is 11.5 GB. [2018-11-10 06:55:34,489 INFO L168 Benchmark]: Boogie Procedure Inliner took 43.76 ms. Allocated memory is still 1.0 GB. Free memory was 940.3 MB in the beginning and 937.7 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-11-10 06:55:34,490 INFO L168 Benchmark]: Boogie Preprocessor took 87.03 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 157.3 MB). Free memory was 937.7 MB in the beginning and 1.2 GB in the end (delta: -212.6 MB). Peak memory consumption was 19.8 MB. Max. memory is 11.5 GB. [2018-11-10 06:55:34,494 INFO L168 Benchmark]: RCFGBuilder took 876.66 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 103.5 MB). Peak memory consumption was 103.5 MB. Max. memory is 11.5 GB. [2018-11-10 06:55:34,494 INFO L168 Benchmark]: BuchiAutomizer took 5043.18 ms. Allocated memory was 1.2 GB in the beginning and 1.4 GB in the end (delta: 176.2 MB). Free memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: -96.6 MB). Peak memory consumption was 400.9 MB. Max. memory is 11.5 GB. [2018-11-10 06:55:34,494 INFO L168 Benchmark]: Witness Printer took 61.57 ms. Allocated memory is still 1.4 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 8.4 MB). Peak memory consumption was 8.4 MB. Max. memory is 11.5 GB. [2018-11-10 06:55:34,496 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.12 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 240.16 ms. Allocated memory is still 1.0 GB. Free memory was 959.1 MB in the beginning and 940.3 MB in the end (delta: 18.8 MB). Peak memory consumption was 18.8 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 43.76 ms. Allocated memory is still 1.0 GB. Free memory was 940.3 MB in the beginning and 937.7 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 87.03 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 157.3 MB). Free memory was 937.7 MB in the beginning and 1.2 GB in the end (delta: -212.6 MB). Peak memory consumption was 19.8 MB. Max. memory is 11.5 GB. * RCFGBuilder took 876.66 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 103.5 MB). Peak memory consumption was 103.5 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 5043.18 ms. Allocated memory was 1.2 GB in the beginning and 1.4 GB in the end (delta: 176.2 MB). Free memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: -96.6 MB). Peak memory consumption was 400.9 MB. Max. memory is 11.5 GB. * Witness Printer took 61.57 ms. Allocated memory is still 1.4 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 8.4 MB). Peak memory consumption was 8.4 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 20 terminating modules (20 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.20 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 12765 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 4.9s and 21 iterations. TraceHistogramMax:1. Analysis of lassos took 2.3s. Construction of modules took 0.8s. Büchi inclusion checks took 0.5s. Highest rank in rank-based complementation 0. Minimization of det autom 20. Minimization of nondet autom 0. Automata minimization 0.5s AutomataMinimizationTime, 20 MinimizatonAttempts, 2605 StatesRemovedByMinimization, 9 NontrivialMinimizations. Non-live state removal took 0.3s Buchi closure took 0.0s. Biggest automaton had 12765 states and ocurred in iteration 20. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 12722 SDtfs, 13113 SDslu, 7622 SDs, 0 SdLazy, 362 SolverSat, 224 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.8s Time LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc4 concLT0 SILN1 SILU0 SILI11 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 413]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {__retres1=0, t3_st=0, token=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@22d82f86=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6666e88=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@667e7b30=0, tmp=1, __retres1=0, kernel_st=1, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5a824dc4=0, t4_i=1, E_3=2, t4_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3c8862c=0, \result=0, E_1=2, tmp_ndt_2=0, \result=0, __retres1=0, \result=0, tmp_ndt_4=0, m_st=0, tmp___2=0, tmp___0=0, t3_pc=0, tmp=0, \result=0, __retres1=0, m_pc=0, \result=0, __retres1=0, \result=0, T2_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6e854636=0, tmp___0=0, t1_pc=0, E_2=2, E_4=2, __retres1=1, T1_E=2, tmp_ndt_1=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, t2_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@57e757ce=0, T4_E=2, t3_i=1, t4_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@988900f=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@335eb89f=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3c2da583=0, t1_st=0, tmp_ndt_5=0, local=0, t2_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@637f10c=0, tmp___3=0, E_M=2, tmp___1=0, T3_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4b04a303=0, t1_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6528d3d6=0, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 413]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int t4_pc = 0; [L19] int m_st ; [L20] int t1_st ; [L21] int t2_st ; [L22] int t3_st ; [L23] int t4_st ; [L24] int m_i ; [L25] int t1_i ; [L26] int t2_i ; [L27] int t3_i ; [L28] int t4_i ; [L29] int M_E = 2; [L30] int T1_E = 2; [L31] int T2_E = 2; [L32] int T3_E = 2; [L33] int T4_E = 2; [L34] int E_M = 2; [L35] int E_1 = 2; [L36] int E_2 = 2; [L37] int E_3 = 2; [L38] int E_4 = 2; [L45] int token ; [L47] int local ; [L838] int __retres1 ; [L842] CALL init_model() [L750] m_i = 1 [L751] t1_i = 1 [L752] t2_i = 1 [L753] t3_i = 1 [L754] RET t4_i = 1 [L842] init_model() [L843] CALL start_simulation() [L779] int kernel_st ; [L780] int tmp ; [L781] int tmp___0 ; [L785] kernel_st = 0 [L786] FCALL update_channels() [L787] CALL init_threads() [L343] COND TRUE m_i == 1 [L344] m_st = 0 [L348] COND TRUE t1_i == 1 [L349] t1_st = 0 [L353] COND TRUE t2_i == 1 [L354] t2_st = 0 [L358] COND TRUE t3_i == 1 [L359] t3_st = 0 [L363] COND TRUE t4_i == 1 [L364] RET t4_st = 0 [L787] init_threads() [L788] CALL fire_delta_events() [L504] COND FALSE !(M_E == 0) [L509] COND FALSE !(T1_E == 0) [L514] COND FALSE !(T2_E == 0) [L519] COND FALSE !(T3_E == 0) [L524] COND FALSE !(T4_E == 0) [L529] COND FALSE !(E_M == 0) [L534] COND FALSE !(E_1 == 0) [L539] COND FALSE !(E_2 == 0) [L544] COND FALSE !(E_3 == 0) [L549] COND FALSE, RET !(E_4 == 0) [L788] fire_delta_events() [L789] CALL activate_threads() [L617] int tmp ; [L618] int tmp___0 ; [L619] int tmp___1 ; [L620] int tmp___2 ; [L621] int tmp___3 ; [L625] CALL, EXPR is_master_triggered() [L237] int __retres1 ; [L240] COND FALSE !(m_pc == 1) [L250] __retres1 = 0 [L252] RET return (__retres1); [L625] EXPR is_master_triggered() [L625] tmp = is_master_triggered() [L627] COND FALSE !(\read(tmp)) [L633] CALL, EXPR is_transmit1_triggered() [L256] int __retres1 ; [L259] COND FALSE !(t1_pc == 1) [L269] __retres1 = 0 [L271] RET return (__retres1); [L633] EXPR is_transmit1_triggered() [L633] tmp___0 = is_transmit1_triggered() [L635] COND FALSE !(\read(tmp___0)) [L641] CALL, EXPR is_transmit2_triggered() [L275] int __retres1 ; [L278] COND FALSE !(t2_pc == 1) [L288] __retres1 = 0 [L290] RET return (__retres1); [L641] EXPR is_transmit2_triggered() [L641] tmp___1 = is_transmit2_triggered() [L643] COND FALSE !(\read(tmp___1)) [L649] CALL, EXPR is_transmit3_triggered() [L294] int __retres1 ; [L297] COND FALSE !(t3_pc == 1) [L307] __retres1 = 0 [L309] RET return (__retres1); [L649] EXPR is_transmit3_triggered() [L649] tmp___2 = is_transmit3_triggered() [L651] COND FALSE !(\read(tmp___2)) [L657] CALL, EXPR is_transmit4_triggered() [L313] int __retres1 ; [L316] COND FALSE !(t4_pc == 1) [L326] __retres1 = 0 [L328] RET return (__retres1); [L657] EXPR is_transmit4_triggered() [L657] tmp___3 = is_transmit4_triggered() [L659] COND FALSE, RET !(\read(tmp___3)) [L789] activate_threads() [L790] CALL reset_delta_events() [L562] COND FALSE !(M_E == 1) [L567] COND FALSE !(T1_E == 1) [L572] COND FALSE !(T2_E == 1) [L577] COND FALSE !(T3_E == 1) [L582] COND FALSE !(T4_E == 1) [L587] COND FALSE !(E_M == 1) [L592] COND FALSE !(E_1 == 1) [L597] COND FALSE !(E_2 == 1) [L602] COND FALSE !(E_3 == 1) [L607] COND FALSE, RET !(E_4 == 1) [L790] reset_delta_events() [L793] COND TRUE 1 [L796] kernel_st = 1 [L797] CALL eval() [L409] int tmp ; Loop: [L413] COND TRUE 1 [L416] CALL, EXPR exists_runnable_thread() [L373] int __retres1 ; [L376] COND TRUE m_st == 0 [L377] __retres1 = 1 [L404] RET return (__retres1); [L416] EXPR exists_runnable_thread() [L416] tmp = exists_runnable_thread() [L418] COND TRUE \read(tmp) [L423] COND TRUE m_st == 0 [L424] int tmp_ndt_1; [L425] tmp_ndt_1 = __VERIFIER_nondet_int() [L426] COND FALSE !(\read(tmp_ndt_1)) [L437] COND TRUE t1_st == 0 [L438] int tmp_ndt_2; [L439] tmp_ndt_2 = __VERIFIER_nondet_int() [L440] COND FALSE !(\read(tmp_ndt_2)) [L451] COND TRUE t2_st == 0 [L452] int tmp_ndt_3; [L453] tmp_ndt_3 = __VERIFIER_nondet_int() [L454] COND FALSE !(\read(tmp_ndt_3)) [L465] COND TRUE t3_st == 0 [L466] int tmp_ndt_4; [L467] tmp_ndt_4 = __VERIFIER_nondet_int() [L468] COND FALSE !(\read(tmp_ndt_4)) [L479] COND TRUE t4_st == 0 [L480] int tmp_ndt_5; [L481] tmp_ndt_5 = __VERIFIER_nondet_int() [L482] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...