./Ultimate.py --spec ../../sv-benchmarks/c/Termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.05_true-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 1dbac8bc Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_3d1a558d-f364-4c06-b466-4401cb7b363c/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_3d1a558d-f364-4c06-b466-4401cb7b363c/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_3d1a558d-f364-4c06-b466-4401cb7b363c/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_3d1a558d-f364-4c06-b466-4401cb7b363c/bin-2019/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.05_true-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_3d1a558d-f364-4c06-b466-4401cb7b363c/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_3d1a558d-f364-4c06-b466-4401cb7b363c/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 75ee388caeaa04bad2057d2e7044ba2f86479f59 ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.23-1dbac8b [2018-11-10 05:51:03,437 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-10 05:51:03,438 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-10 05:51:03,447 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-10 05:51:03,447 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-10 05:51:03,448 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-10 05:51:03,449 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-10 05:51:03,450 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-10 05:51:03,451 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-10 05:51:03,452 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-10 05:51:03,452 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-10 05:51:03,453 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-10 05:51:03,453 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-10 05:51:03,454 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-10 05:51:03,455 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-10 05:51:03,455 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-10 05:51:03,456 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-10 05:51:03,457 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-10 05:51:03,459 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-10 05:51:03,460 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-10 05:51:03,461 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-10 05:51:03,462 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-10 05:51:03,463 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-10 05:51:03,463 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-10 05:51:03,464 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-10 05:51:03,464 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-10 05:51:03,465 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-10 05:51:03,466 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-10 05:51:03,466 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-10 05:51:03,467 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-10 05:51:03,467 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-10 05:51:03,468 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-10 05:51:03,468 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-10 05:51:03,468 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-10 05:51:03,469 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-10 05:51:03,469 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-10 05:51:03,469 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_3d1a558d-f364-4c06-b466-4401cb7b363c/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2018-11-10 05:51:03,480 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-10 05:51:03,480 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-10 05:51:03,481 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-10 05:51:03,481 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-10 05:51:03,481 INFO L133 SettingsManager]: * Use SBE=true [2018-11-10 05:51:03,482 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2018-11-10 05:51:03,482 INFO L133 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2018-11-10 05:51:03,482 INFO L133 SettingsManager]: * Use old map elimination=false [2018-11-10 05:51:03,482 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false [2018-11-10 05:51:03,482 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true [2018-11-10 05:51:03,482 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2018-11-10 05:51:03,482 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-10 05:51:03,483 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-10 05:51:03,483 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-10 05:51:03,483 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-10 05:51:03,483 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-10 05:51:03,483 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-10 05:51:03,483 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2018-11-10 05:51:03,483 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2018-11-10 05:51:03,484 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2018-11-10 05:51:03,484 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-10 05:51:03,484 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-10 05:51:03,484 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false [2018-11-10 05:51:03,484 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2018-11-10 05:51:03,484 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-10 05:51:03,484 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-10 05:51:03,485 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2018-11-10 05:51:03,485 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-10 05:51:03,485 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-10 05:51:03,485 INFO L133 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2018-11-10 05:51:03,486 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-11-10 05:51:03,486 INFO L133 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_3d1a558d-f364-4c06-b466-4401cb7b363c/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 75ee388caeaa04bad2057d2e7044ba2f86479f59 [2018-11-10 05:51:03,508 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-10 05:51:03,517 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-10 05:51:03,520 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-10 05:51:03,521 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-10 05:51:03,522 INFO L276 PluginConnector]: CDTParser initialized [2018-11-10 05:51:03,522 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_3d1a558d-f364-4c06-b466-4401cb7b363c/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/token_ring.05_true-unreach-call_false-termination.cil.c [2018-11-10 05:51:03,562 INFO L218 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_3d1a558d-f364-4c06-b466-4401cb7b363c/bin-2019/uautomizer/data/7f0103fa5/f2490f4ea1234e6880d49328658daea9/FLAG6fc96b26d [2018-11-10 05:51:03,915 INFO L298 CDTParser]: Found 1 translation units. [2018-11-10 05:51:03,916 INFO L158 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_3d1a558d-f364-4c06-b466-4401cb7b363c/sv-benchmarks/c/systemc/token_ring.05_true-unreach-call_false-termination.cil.c [2018-11-10 05:51:03,924 INFO L346 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_3d1a558d-f364-4c06-b466-4401cb7b363c/bin-2019/uautomizer/data/7f0103fa5/f2490f4ea1234e6880d49328658daea9/FLAG6fc96b26d [2018-11-10 05:51:03,932 INFO L354 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_3d1a558d-f364-4c06-b466-4401cb7b363c/bin-2019/uautomizer/data/7f0103fa5/f2490f4ea1234e6880d49328658daea9 [2018-11-10 05:51:03,934 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-10 05:51:03,935 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-10 05:51:03,936 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-10 05:51:03,936 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-10 05:51:03,938 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-10 05:51:03,939 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.11 05:51:03" (1/1) ... [2018-11-10 05:51:03,940 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7ce791db and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 05:51:03, skipping insertion in model container [2018-11-10 05:51:03,940 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.11 05:51:03" (1/1) ... [2018-11-10 05:51:03,946 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-10 05:51:03,972 INFO L174 MainTranslator]: Built tables and reachable declarations [2018-11-10 05:51:04,115 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-11-10 05:51:04,118 INFO L189 MainTranslator]: Completed pre-run [2018-11-10 05:51:04,148 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-11-10 05:51:04,159 INFO L193 MainTranslator]: Completed translation [2018-11-10 05:51:04,159 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 05:51:04 WrapperNode [2018-11-10 05:51:04,159 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-10 05:51:04,160 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-10 05:51:04,160 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-10 05:51:04,160 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-10 05:51:04,167 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 05:51:04" (1/1) ... [2018-11-10 05:51:04,175 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 05:51:04" (1/1) ... [2018-11-10 05:51:04,213 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-10 05:51:04,214 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-10 05:51:04,214 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-10 05:51:04,214 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-10 05:51:04,269 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 05:51:04" (1/1) ... [2018-11-10 05:51:04,269 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 05:51:04" (1/1) ... [2018-11-10 05:51:04,273 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 05:51:04" (1/1) ... [2018-11-10 05:51:04,273 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 05:51:04" (1/1) ... [2018-11-10 05:51:04,287 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 05:51:04" (1/1) ... [2018-11-10 05:51:04,302 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 05:51:04" (1/1) ... [2018-11-10 05:51:04,304 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 05:51:04" (1/1) ... [2018-11-10 05:51:04,309 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-10 05:51:04,310 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-10 05:51:04,310 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-10 05:51:04,310 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-10 05:51:04,310 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 05:51:04" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3d1a558d-f364-4c06-b466-4401cb7b363c/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-10 05:51:04,356 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-10 05:51:04,356 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-10 05:51:05,394 INFO L341 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-10 05:51:05,394 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.11 05:51:05 BoogieIcfgContainer [2018-11-10 05:51:05,398 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-10 05:51:05,399 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2018-11-10 05:51:05,399 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2018-11-10 05:51:05,402 INFO L276 PluginConnector]: BuchiAutomizer initialized [2018-11-10 05:51:05,403 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-10 05:51:05,403 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 10.11 05:51:03" (1/3) ... [2018-11-10 05:51:05,404 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@38300ab1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 10.11 05:51:05, skipping insertion in model container [2018-11-10 05:51:05,404 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-10 05:51:05,404 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 05:51:04" (2/3) ... [2018-11-10 05:51:05,405 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@38300ab1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 10.11 05:51:05, skipping insertion in model container [2018-11-10 05:51:05,405 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-10 05:51:05,405 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.11 05:51:05" (3/3) ... [2018-11-10 05:51:05,407 INFO L375 chiAutomizerObserver]: Analyzing ICFG token_ring.05_true-unreach-call_false-termination.cil.c [2018-11-10 05:51:05,452 INFO L135 ementStrategyFactory]: Using default assertion order modulation [2018-11-10 05:51:05,452 INFO L374 BuchiCegarLoop]: Interprodecural is true [2018-11-10 05:51:05,452 INFO L375 BuchiCegarLoop]: Hoare is false [2018-11-10 05:51:05,452 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2018-11-10 05:51:05,452 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-10 05:51:05,452 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-10 05:51:05,453 INFO L379 BuchiCegarLoop]: Difference is false [2018-11-10 05:51:05,453 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-10 05:51:05,453 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2018-11-10 05:51:05,476 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 560 states. [2018-11-10 05:51:05,513 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 477 [2018-11-10 05:51:05,513 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:51:05,513 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:51:05,521 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:05,522 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:05,522 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ [2018-11-10 05:51:05,522 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 560 states. [2018-11-10 05:51:05,531 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 477 [2018-11-10 05:51:05,531 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:51:05,531 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:51:05,538 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:05,538 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:05,544 INFO L793 eck$LassoCheckResult]: Stem: 392#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 318#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 391#L881true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 222#L397true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 533#L404true assume !(~m_i~0 == 1);~m_st~0 := 2; 538#L404-2true assume ~t1_i~0 == 1;~t1_st~0 := 0; 162#L409-1true assume !(~t2_i~0 == 1);~t2_st~0 := 2; 447#L414-1true assume !(~t3_i~0 == 1);~t3_st~0 := 2; 223#L419-1true assume !(~t4_i~0 == 1);~t4_st~0 := 2; 112#L424-1true assume !(~t5_i~0 == 1);~t5_st~0 := 2; 397#L429-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 123#L589true assume ~M_E~0 == 0;~M_E~0 := 1; 128#L589-2true assume !(~T1_E~0 == 0); 401#L594-1true assume !(~T2_E~0 == 0); 7#L599-1true assume !(~T3_E~0 == 0); 343#L604-1true assume !(~T4_E~0 == 0); 83#L609-1true assume !(~T5_E~0 == 0); 518#L614-1true assume !(~E_M~0 == 0); 291#L619-1true assume !(~E_1~0 == 0); 561#L624-1true assume ~E_2~0 == 0;~E_2~0 := 1; 170#L629-1true assume !(~E_3~0 == 0); 466#L634-1true assume !(~E_4~0 == 0); 231#L639-1true assume !(~E_5~0 == 0); 121#L644-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 425#L282true assume !(~m_pc~0 == 1); 458#L282-2true is_master_triggered_~__retres1~0 := 0; 426#L293true is_master_triggered_#res := is_master_triggered_~__retres1~0; 532#L294true activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 478#L733true assume !(activate_threads_~tmp~1 != 0); 481#L733-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 72#L301true assume ~t1_pc~0 == 1; 159#L302true assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 48#L312true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 144#L313true activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 90#L741true assume !(activate_threads_~tmp___0~0 != 0); 77#L741-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 228#L320true assume ~t2_pc~0 == 1; 165#L321true assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 227#L331true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 164#L332true activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 386#L749true assume !(activate_threads_~tmp___1~0 != 0); 387#L749-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 371#L339true assume !(~t3_pc~0 == 1); 376#L339-2true is_transmit3_triggered_~__retres1~3 := 0; 370#L350true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 338#L351true activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 524#L757true assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 508#L757-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 116#L358true assume ~t4_pc~0 == 1; 452#L359true assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 114#L369true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 449#L370true activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 132#L765true assume !(activate_threads_~tmp___3~0 != 0); 133#L765-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 266#L377true assume !(~t5_pc~0 == 1); 270#L377-2true is_transmit5_triggered_~__retres1~5 := 0; 264#L388true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 73#L389true activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 295#L773true assume !(activate_threads_~tmp___4~0 != 0); 286#L773-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 557#L657true assume !(~M_E~0 == 1); 562#L657-2true assume !(~T1_E~0 == 1); 184#L662-1true assume !(~T2_E~0 == 1); 482#L667-1true assume !(~T3_E~0 == 1); 389#L672-1true assume !(~T4_E~0 == 1); 120#L677-1true assume !(~T5_E~0 == 1); 399#L682-1true assume !(~E_M~0 == 1); 3#L687-1true assume ~E_1~0 == 1;~E_1~0 := 2; 340#L692-1true assume !(~E_2~0 == 1); 78#L697-1true assume !(~E_3~0 == 1); 510#L702-1true assume !(~E_4~0 == 1); 287#L707-1true assume !(~E_5~0 == 1); 556#L712-1true assume { :end_inline_reset_delta_events } true; 12#L918-3true [2018-11-10 05:51:05,545 INFO L795 eck$LassoCheckResult]: Loop: 12#L918-3true assume true; 25#L918-1true assume !false; 136#L919true start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 277#L564true assume !true; 468#L579true assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 225#L397-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 130#L589-3true assume ~M_E~0 == 0;~M_E~0 := 1; 109#L589-5true assume ~T1_E~0 == 0;~T1_E~0 := 1; 404#L594-3true assume !(~T2_E~0 == 0); 150#L599-3true assume ~T3_E~0 == 0;~T3_E~0 := 1; 332#L604-3true assume ~T4_E~0 == 0;~T4_E~0 := 1; 64#L609-3true assume ~T5_E~0 == 0;~T5_E~0 := 1; 503#L614-3true assume ~E_M~0 == 0;~E_M~0 := 1; 279#L619-3true assume ~E_1~0 == 0;~E_1~0 := 1; 550#L624-3true assume ~E_2~0 == 0;~E_2~0 := 1; 174#L629-3true assume ~E_3~0 == 0;~E_3~0 := 1; 471#L634-3true assume !(~E_4~0 == 0); 235#L639-3true assume ~E_5~0 == 0;~E_5~0 := 1; 127#L644-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 546#L282-21true assume !(~m_pc~0 == 1); 559#L282-23true is_master_triggered_~__retres1~0 := 0; 413#L293-7true is_master_triggered_#res := is_master_triggered_~__retres1~0; 534#L294-7true activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 418#L733-21true assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 420#L733-23true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15#L301-21true assume ~t1_pc~0 == 1; 137#L302-7true assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 39#L312-7true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 142#L313-7true activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 41#L741-21true assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 18#L741-23true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 183#L320-21true assume ~t2_pc~0 == 1; 310#L321-7true assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 193#L331-7true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 309#L332-7true activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 198#L749-21true assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 204#L749-23true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 339#L339-21true assume !(~t3_pc~0 == 1); 341#L339-23true is_transmit3_triggered_~__retres1~3 := 0; 363#L350-7true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 314#L351-7true activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 367#L757-21true assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 350#L757-23true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 480#L358-21true assume !(~t4_pc~0 == 1); 484#L358-23true is_transmit4_triggered_~__retres1~4 := 0; 103#L369-7true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 436#L370-7true activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 497#L765-21true assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 499#L765-23true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 76#L377-21true assume !(~t5_pc~0 == 1); 80#L377-23true is_transmit5_triggered_~__retres1~5 := 0; 258#L388-7true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 30#L389-7true activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 263#L773-21true assume !(activate_threads_~tmp___4~0 != 0); 243#L773-23true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 547#L657-3true assume ~M_E~0 == 1;~M_E~0 := 2; 552#L657-5true assume ~T1_E~0 == 1;~T1_E~0 := 2; 172#L662-3true assume ~T2_E~0 == 1;~T2_E~0 := 2; 470#L667-3true assume ~T3_E~0 == 1;~T3_E~0 := 2; 233#L672-3true assume !(~T4_E~0 == 1); 124#L677-3true assume ~T5_E~0 == 1;~T5_E~0 := 2; 400#L682-3true assume ~E_M~0 == 1;~E_M~0 := 2; 6#L687-3true assume ~E_1~0 == 1;~E_1~0 := 2; 342#L692-3true assume ~E_2~0 == 1;~E_2~0 := 2; 82#L697-3true assume ~E_3~0 == 1;~E_3~0 := 2; 515#L702-3true assume ~E_4~0 == 1;~E_4~0 := 2; 290#L707-3true assume ~E_5~0 == 1;~E_5~0 := 2; 560#L712-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 160#L442-1true assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 220#L474-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 180#L475-1true start_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 186#L937true assume !(start_simulation_~tmp~3 == 0); 189#L937-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 163#L442-2true assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 221#L474-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 161#L475-2true stop_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 390#L892true assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 407#L899true stop_simulation_#res := stop_simulation_~__retres2~0; 520#L900true start_simulation_#t~ret16 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 249#L950true assume !(start_simulation_~tmp___0~1 != 0); 12#L918-3true [2018-11-10 05:51:05,550 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:05,550 INFO L82 PathProgramCache]: Analyzing trace with hash 907431560, now seen corresponding path program 1 times [2018-11-10 05:51:05,552 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:05,552 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:05,583 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:05,583 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:05,584 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:05,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:05,669 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:51:05,671 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:51:05,671 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 05:51:05,676 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 05:51:05,676 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:05,676 INFO L82 PathProgramCache]: Analyzing trace with hash 694094229, now seen corresponding path program 1 times [2018-11-10 05:51:05,676 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:05,676 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:05,677 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:05,677 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:05,678 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:05,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:05,697 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:51:05,697 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:51:05,697 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 05:51:05,699 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 05:51:05,713 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 05:51:05,713 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 05:51:05,715 INFO L87 Difference]: Start difference. First operand 560 states. Second operand 3 states. [2018-11-10 05:51:05,743 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:51:05,743 INFO L93 Difference]: Finished difference Result 559 states and 831 transitions. [2018-11-10 05:51:05,746 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 05:51:05,748 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 559 states and 831 transitions. [2018-11-10 05:51:05,753 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 475 [2018-11-10 05:51:05,760 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 559 states to 554 states and 826 transitions. [2018-11-10 05:51:05,761 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 554 [2018-11-10 05:51:05,762 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 554 [2018-11-10 05:51:05,763 INFO L73 IsDeterministic]: Start isDeterministic. Operand 554 states and 826 transitions. [2018-11-10 05:51:05,765 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 05:51:05,766 INFO L705 BuchiCegarLoop]: Abstraction has 554 states and 826 transitions. [2018-11-10 05:51:05,782 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 554 states and 826 transitions. [2018-11-10 05:51:05,802 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 554 to 554. [2018-11-10 05:51:05,803 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 554 states. [2018-11-10 05:51:05,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 554 states to 554 states and 826 transitions. [2018-11-10 05:51:05,806 INFO L728 BuchiCegarLoop]: Abstraction has 554 states and 826 transitions. [2018-11-10 05:51:05,806 INFO L608 BuchiCegarLoop]: Abstraction has 554 states and 826 transitions. [2018-11-10 05:51:05,806 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ [2018-11-10 05:51:05,806 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 554 states and 826 transitions. [2018-11-10 05:51:05,810 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 475 [2018-11-10 05:51:05,810 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:51:05,810 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:51:05,812 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:05,812 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:05,813 INFO L793 eck$LassoCheckResult]: Stem: 1591#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1539#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1540#L881 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 1461#L397 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1462#L404 assume ~m_i~0 == 1;~m_st~0 := 0; 1677#L404-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 1381#L409-1 assume !(~t2_i~0 == 1);~t2_st~0 := 2; 1382#L414-1 assume !(~t3_i~0 == 1);~t3_st~0 := 2; 1463#L419-1 assume !(~t4_i~0 == 1);~t4_st~0 := 2; 1329#L424-1 assume !(~t5_i~0 == 1);~t5_st~0 := 2; 1330#L429-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1349#L589 assume ~M_E~0 == 0;~M_E~0 := 1; 1350#L589-2 assume !(~T1_E~0 == 0); 1359#L594-1 assume !(~T2_E~0 == 0); 1137#L599-1 assume !(~T3_E~0 == 0); 1138#L604-1 assume !(~T4_E~0 == 0); 1281#L609-1 assume !(~T5_E~0 == 0); 1282#L614-1 assume !(~E_M~0 == 0); 1519#L619-1 assume !(~E_1~0 == 0); 1520#L624-1 assume ~E_2~0 == 0;~E_2~0 := 1; 1398#L629-1 assume !(~E_3~0 == 0); 1399#L634-1 assume !(~E_4~0 == 0); 1469#L639-1 assume !(~E_5~0 == 0); 1345#L644-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1346#L282 assume !(~m_pc~0 == 1); 1620#L282-2 is_master_triggered_~__retres1~0 := 0; 1622#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1623#L294 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1661#L733 assume !(activate_threads_~tmp~1 != 0); 1662#L733-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1263#L301 assume ~t1_pc~0 == 1; 1264#L302 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 1217#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1218#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1288#L741 assume !(activate_threads_~tmp___0~0 != 0); 1272#L741-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1273#L320 assume ~t2_pc~0 == 1; 1385#L321 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 1386#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1383#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1384#L749 assume !(activate_threads_~tmp___1~0 != 0); 1588#L749-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1582#L339 assume !(~t3_pc~0 == 1); 1543#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 1542#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1571#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1572#L757 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 1670#L757-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1337#L358 assume ~t4_pc~0 == 1; 1338#L359 assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 1290#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1334#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1364#L765 assume !(activate_threads_~tmp___3~0 != 0); 1365#L765-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1366#L377 assume !(~t5_pc~0 == 1); 1268#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 1269#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1265#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1266#L773 assume !(activate_threads_~tmp___4~0 != 0); 1511#L773-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1512#L657 assume !(~M_E~0 == 1); 1681#L657-2 assume !(~T1_E~0 == 1); 1419#L662-1 assume !(~T2_E~0 == 1); 1420#L667-1 assume !(~T3_E~0 == 1); 1589#L672-1 assume !(~T4_E~0 == 1); 1343#L677-1 assume !(~T5_E~0 == 1); 1344#L682-1 assume !(~E_M~0 == 1); 1128#L687-1 assume ~E_1~0 == 1;~E_1~0 := 2; 1129#L692-1 assume !(~E_2~0 == 1); 1274#L697-1 assume !(~E_3~0 == 1); 1275#L702-1 assume !(~E_4~0 == 1); 1513#L707-1 assume !(~E_5~0 == 1); 1514#L712-1 assume { :end_inline_reset_delta_events } true; 1150#L918-3 [2018-11-10 05:51:05,813 INFO L795 eck$LassoCheckResult]: Loop: 1150#L918-3 assume true; 1151#L918-1 assume !false; 1174#L919 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 1354#L564 assume true; 1497#L484-1 assume !false; 1475#L485 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1414#L442 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 1319#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1411#L475 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 1370#L489 assume !(eval_~tmp~0 != 0); 1372#L579 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 1465#L397-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 1361#L589-3 assume ~M_E~0 == 0;~M_E~0 := 1; 1323#L589-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 1324#L594-3 assume !(~T2_E~0 == 0); 1368#L599-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 1369#L604-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 1251#L609-3 assume ~T5_E~0 == 0;~T5_E~0 := 1; 1252#L614-3 assume ~E_M~0 == 0;~E_M~0 := 1; 1499#L619-3 assume ~E_1~0 == 0;~E_1~0 := 1; 1500#L624-3 assume ~E_2~0 == 0;~E_2~0 := 1; 1406#L629-3 assume ~E_3~0 == 0;~E_3~0 := 1; 1407#L634-3 assume !(~E_4~0 == 0); 1474#L639-3 assume ~E_5~0 == 0;~E_5~0 := 1; 1357#L644-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1358#L282-21 assume ~m_pc~0 == 1; 1674#L283-7 assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 1605#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1606#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1612#L733-21 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 1613#L733-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1156#L301-21 assume !(~t1_pc~0 == 1); 1154#L301-23 is_transmit1_triggered_~__retres1~1 := 0; 1155#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1202#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1205#L741-21 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 1161#L741-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1162#L320-21 assume !(~t2_pc~0 == 1); 1400#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 1401#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1433#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1438#L749-21 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 1439#L749-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1448#L339-21 assume ~t3_pc~0 == 1; 1531#L340-7 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 1532#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1529#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1530#L757-21 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 1573#L757-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1574#L358-21 assume ~t4_pc~0 == 1; 1634#L359-7 assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 1311#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1312#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1633#L765-21 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 1666#L765-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1271#L377-21 assume ~t5_pc~0 == 1; 1185#L378-7 assume ~E_5~0 == 1;is_transmit5_triggered_~__retres1~5 := 1; 1186#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1183#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1184#L773-21 assume !(activate_threads_~tmp___4~0 != 0); 1481#L773-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1482#L657-3 assume ~M_E~0 == 1;~M_E~0 := 2; 1680#L657-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 1402#L662-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 1403#L667-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 1472#L672-3 assume !(~T4_E~0 == 1); 1351#L677-3 assume ~T5_E~0 == 1;~T5_E~0 := 2; 1352#L682-3 assume ~E_M~0 == 1;~E_M~0 := 2; 1135#L687-3 assume ~E_1~0 == 1;~E_1~0 := 2; 1136#L692-3 assume ~E_2~0 == 1;~E_2~0 := 2; 1279#L697-3 assume ~E_3~0 == 1;~E_3~0 := 2; 1280#L702-3 assume ~E_4~0 == 1;~E_4~0 := 2; 1516#L707-3 assume ~E_5~0 == 1;~E_5~0 := 2; 1517#L712-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1377#L442-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 1326#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1412#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 1413#L937 assume !(start_simulation_~tmp~3 == 0); 1424#L937-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1380#L442-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 1332#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1378#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 1379#L892 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 1590#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 1597#L900 start_simulation_#t~ret16 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 1487#L950 assume !(start_simulation_~tmp___0~1 != 0); 1150#L918-3 [2018-11-10 05:51:05,814 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:05,818 INFO L82 PathProgramCache]: Analyzing trace with hash 1400057734, now seen corresponding path program 1 times [2018-11-10 05:51:05,818 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:05,818 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:05,819 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:05,819 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:05,820 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:05,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:05,863 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:51:05,864 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:51:05,864 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 05:51:05,864 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 05:51:05,864 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:05,865 INFO L82 PathProgramCache]: Analyzing trace with hash -977062792, now seen corresponding path program 1 times [2018-11-10 05:51:05,865 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:05,865 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:05,866 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:05,866 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:05,866 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:05,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:05,938 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:51:05,939 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:51:05,939 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 05:51:05,939 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 05:51:05,939 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 05:51:05,940 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 05:51:05,942 INFO L87 Difference]: Start difference. First operand 554 states and 826 transitions. cyclomatic complexity: 273 Second operand 3 states. [2018-11-10 05:51:05,955 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:51:05,955 INFO L93 Difference]: Finished difference Result 554 states and 825 transitions. [2018-11-10 05:51:05,956 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 05:51:05,957 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 554 states and 825 transitions. [2018-11-10 05:51:05,960 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 475 [2018-11-10 05:51:05,963 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 554 states to 554 states and 825 transitions. [2018-11-10 05:51:05,964 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 554 [2018-11-10 05:51:05,964 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 554 [2018-11-10 05:51:05,964 INFO L73 IsDeterministic]: Start isDeterministic. Operand 554 states and 825 transitions. [2018-11-10 05:51:05,966 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 05:51:05,966 INFO L705 BuchiCegarLoop]: Abstraction has 554 states and 825 transitions. [2018-11-10 05:51:05,967 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 554 states and 825 transitions. [2018-11-10 05:51:05,976 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 554 to 554. [2018-11-10 05:51:05,976 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 554 states. [2018-11-10 05:51:05,978 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 554 states to 554 states and 825 transitions. [2018-11-10 05:51:05,978 INFO L728 BuchiCegarLoop]: Abstraction has 554 states and 825 transitions. [2018-11-10 05:51:05,979 INFO L608 BuchiCegarLoop]: Abstraction has 554 states and 825 transitions. [2018-11-10 05:51:05,979 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ [2018-11-10 05:51:05,979 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 554 states and 825 transitions. [2018-11-10 05:51:05,981 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 475 [2018-11-10 05:51:05,982 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:51:05,982 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:51:05,983 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:05,983 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:05,984 INFO L793 eck$LassoCheckResult]: Stem: 2706#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 2654#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2655#L881 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 2576#L397 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2577#L404 assume ~m_i~0 == 1;~m_st~0 := 0; 2792#L404-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 2496#L409-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 2497#L414-1 assume !(~t3_i~0 == 1);~t3_st~0 := 2; 2578#L419-1 assume !(~t4_i~0 == 1);~t4_st~0 := 2; 2444#L424-1 assume !(~t5_i~0 == 1);~t5_st~0 := 2; 2445#L429-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2464#L589 assume ~M_E~0 == 0;~M_E~0 := 1; 2465#L589-2 assume !(~T1_E~0 == 0); 2474#L594-1 assume !(~T2_E~0 == 0); 2252#L599-1 assume !(~T3_E~0 == 0); 2253#L604-1 assume !(~T4_E~0 == 0); 2396#L609-1 assume !(~T5_E~0 == 0); 2397#L614-1 assume !(~E_M~0 == 0); 2634#L619-1 assume !(~E_1~0 == 0); 2635#L624-1 assume ~E_2~0 == 0;~E_2~0 := 1; 2513#L629-1 assume !(~E_3~0 == 0); 2514#L634-1 assume !(~E_4~0 == 0); 2584#L639-1 assume !(~E_5~0 == 0); 2460#L644-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2461#L282 assume !(~m_pc~0 == 1); 2735#L282-2 is_master_triggered_~__retres1~0 := 0; 2737#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2738#L294 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2776#L733 assume !(activate_threads_~tmp~1 != 0); 2777#L733-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2378#L301 assume ~t1_pc~0 == 1; 2379#L302 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 2335#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2336#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2403#L741 assume !(activate_threads_~tmp___0~0 != 0); 2387#L741-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2388#L320 assume ~t2_pc~0 == 1; 2500#L321 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 2501#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2498#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2499#L749 assume !(activate_threads_~tmp___1~0 != 0); 2703#L749-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2697#L339 assume !(~t3_pc~0 == 1); 2658#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 2657#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2686#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2687#L757 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 2785#L757-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2452#L358 assume ~t4_pc~0 == 1; 2453#L359 assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 2405#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2451#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2479#L765 assume !(activate_threads_~tmp___3~0 != 0); 2480#L765-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2481#L377 assume !(~t5_pc~0 == 1); 2383#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 2384#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2380#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2381#L773 assume !(activate_threads_~tmp___4~0 != 0); 2626#L773-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2627#L657 assume !(~M_E~0 == 1); 2796#L657-2 assume !(~T1_E~0 == 1); 2534#L662-1 assume !(~T2_E~0 == 1); 2535#L667-1 assume !(~T3_E~0 == 1); 2704#L672-1 assume !(~T4_E~0 == 1); 2458#L677-1 assume !(~T5_E~0 == 1); 2459#L682-1 assume !(~E_M~0 == 1); 2243#L687-1 assume ~E_1~0 == 1;~E_1~0 := 2; 2244#L692-1 assume !(~E_2~0 == 1); 2389#L697-1 assume !(~E_3~0 == 1); 2390#L702-1 assume !(~E_4~0 == 1); 2629#L707-1 assume !(~E_5~0 == 1); 2630#L712-1 assume { :end_inline_reset_delta_events } true; 2265#L918-3 [2018-11-10 05:51:05,984 INFO L795 eck$LassoCheckResult]: Loop: 2265#L918-3 assume true; 2266#L918-1 assume !false; 2289#L919 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 2471#L564 assume true; 2612#L484-1 assume !false; 2590#L485 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2529#L442 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 2434#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2526#L475 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 2485#L489 assume !(eval_~tmp~0 != 0); 2487#L579 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 2580#L397-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 2476#L589-3 assume ~M_E~0 == 0;~M_E~0 := 1; 2438#L589-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 2439#L594-3 assume !(~T2_E~0 == 0); 2483#L599-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 2484#L604-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 2366#L609-3 assume ~T5_E~0 == 0;~T5_E~0 := 1; 2367#L614-3 assume ~E_M~0 == 0;~E_M~0 := 1; 2614#L619-3 assume ~E_1~0 == 0;~E_1~0 := 1; 2615#L624-3 assume ~E_2~0 == 0;~E_2~0 := 1; 2521#L629-3 assume ~E_3~0 == 0;~E_3~0 := 1; 2522#L634-3 assume !(~E_4~0 == 0); 2589#L639-3 assume ~E_5~0 == 0;~E_5~0 := 1; 2472#L644-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2473#L282-21 assume ~m_pc~0 == 1; 2789#L283-7 assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 2720#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2721#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2727#L733-21 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 2728#L733-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2271#L301-21 assume ~t1_pc~0 == 1; 2272#L302-7 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 2270#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2317#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2320#L741-21 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 2276#L741-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2277#L320-21 assume !(~t2_pc~0 == 1); 2515#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 2516#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2548#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2553#L749-21 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 2554#L749-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2562#L339-21 assume ~t3_pc~0 == 1; 2646#L340-7 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 2647#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2644#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2645#L757-21 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 2688#L757-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2689#L358-21 assume ~t4_pc~0 == 1; 2749#L359-7 assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 2426#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2427#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2747#L765-21 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 2781#L765-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2386#L377-21 assume ~t5_pc~0 == 1; 2300#L378-7 assume ~E_5~0 == 1;is_transmit5_triggered_~__retres1~5 := 1; 2301#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2298#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2299#L773-21 assume !(activate_threads_~tmp___4~0 != 0); 2596#L773-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2597#L657-3 assume ~M_E~0 == 1;~M_E~0 := 2; 2795#L657-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 2517#L662-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 2518#L667-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 2587#L672-3 assume !(~T4_E~0 == 1); 2466#L677-3 assume ~T5_E~0 == 1;~T5_E~0 := 2; 2467#L682-3 assume ~E_M~0 == 1;~E_M~0 := 2; 2250#L687-3 assume ~E_1~0 == 1;~E_1~0 := 2; 2251#L692-3 assume ~E_2~0 == 1;~E_2~0 := 2; 2394#L697-3 assume ~E_3~0 == 1;~E_3~0 := 2; 2395#L702-3 assume ~E_4~0 == 1;~E_4~0 := 2; 2632#L707-3 assume ~E_5~0 == 1;~E_5~0 := 2; 2633#L712-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2492#L442-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 2441#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2527#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 2528#L937 assume !(start_simulation_~tmp~3 == 0); 2539#L937-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2495#L442-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 2447#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2493#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 2494#L892 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 2705#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 2712#L900 start_simulation_#t~ret16 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 2602#L950 assume !(start_simulation_~tmp___0~1 != 0); 2265#L918-3 [2018-11-10 05:51:05,984 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:05,985 INFO L82 PathProgramCache]: Analyzing trace with hash -1678755836, now seen corresponding path program 1 times [2018-11-10 05:51:05,985 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:05,985 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:05,986 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:05,986 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:05,986 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:05,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:06,011 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:51:06,011 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:51:06,011 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 05:51:06,012 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 05:51:06,012 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:06,012 INFO L82 PathProgramCache]: Analyzing trace with hash 131065847, now seen corresponding path program 1 times [2018-11-10 05:51:06,012 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:06,012 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:06,013 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:06,013 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:06,013 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:06,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:06,059 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:51:06,060 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:51:06,060 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 05:51:06,060 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 05:51:06,060 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 05:51:06,060 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 05:51:06,061 INFO L87 Difference]: Start difference. First operand 554 states and 825 transitions. cyclomatic complexity: 272 Second operand 3 states. [2018-11-10 05:51:06,083 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:51:06,083 INFO L93 Difference]: Finished difference Result 554 states and 824 transitions. [2018-11-10 05:51:06,083 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 05:51:06,084 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 554 states and 824 transitions. [2018-11-10 05:51:06,086 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 475 [2018-11-10 05:51:06,088 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 554 states to 554 states and 824 transitions. [2018-11-10 05:51:06,088 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 554 [2018-11-10 05:51:06,088 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 554 [2018-11-10 05:51:06,088 INFO L73 IsDeterministic]: Start isDeterministic. Operand 554 states and 824 transitions. [2018-11-10 05:51:06,089 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 05:51:06,089 INFO L705 BuchiCegarLoop]: Abstraction has 554 states and 824 transitions. [2018-11-10 05:51:06,090 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 554 states and 824 transitions. [2018-11-10 05:51:06,094 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 554 to 554. [2018-11-10 05:51:06,094 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 554 states. [2018-11-10 05:51:06,095 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 554 states to 554 states and 824 transitions. [2018-11-10 05:51:06,095 INFO L728 BuchiCegarLoop]: Abstraction has 554 states and 824 transitions. [2018-11-10 05:51:06,096 INFO L608 BuchiCegarLoop]: Abstraction has 554 states and 824 transitions. [2018-11-10 05:51:06,096 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ [2018-11-10 05:51:06,096 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 554 states and 824 transitions. [2018-11-10 05:51:06,098 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 475 [2018-11-10 05:51:06,098 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:51:06,098 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:51:06,099 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:06,099 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:06,099 INFO L793 eck$LassoCheckResult]: Stem: 3821#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 3769#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3770#L881 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 3691#L397 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3692#L404 assume ~m_i~0 == 1;~m_st~0 := 0; 3907#L404-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 3611#L409-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 3612#L414-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 3694#L419-1 assume !(~t4_i~0 == 1);~t4_st~0 := 2; 3559#L424-1 assume !(~t5_i~0 == 1);~t5_st~0 := 2; 3560#L429-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3579#L589 assume ~M_E~0 == 0;~M_E~0 := 1; 3580#L589-2 assume !(~T1_E~0 == 0); 3589#L594-1 assume !(~T2_E~0 == 0); 3367#L599-1 assume !(~T3_E~0 == 0); 3368#L604-1 assume !(~T4_E~0 == 0); 3511#L609-1 assume !(~T5_E~0 == 0); 3512#L614-1 assume !(~E_M~0 == 0); 3749#L619-1 assume !(~E_1~0 == 0); 3750#L624-1 assume ~E_2~0 == 0;~E_2~0 := 1; 3628#L629-1 assume !(~E_3~0 == 0); 3629#L634-1 assume !(~E_4~0 == 0); 3699#L639-1 assume !(~E_5~0 == 0); 3575#L644-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3576#L282 assume !(~m_pc~0 == 1); 3850#L282-2 is_master_triggered_~__retres1~0 := 0; 3852#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3853#L294 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3891#L733 assume !(activate_threads_~tmp~1 != 0); 3892#L733-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3493#L301 assume ~t1_pc~0 == 1; 3494#L302 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 3450#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3451#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3518#L741 assume !(activate_threads_~tmp___0~0 != 0); 3502#L741-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3503#L320 assume ~t2_pc~0 == 1; 3615#L321 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 3616#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3613#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3614#L749 assume !(activate_threads_~tmp___1~0 != 0); 3818#L749-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3812#L339 assume !(~t3_pc~0 == 1); 3773#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 3772#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3801#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3802#L757 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 3900#L757-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3567#L358 assume ~t4_pc~0 == 1; 3568#L359 assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 3520#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3566#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3594#L765 assume !(activate_threads_~tmp___3~0 != 0); 3595#L765-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3596#L377 assume !(~t5_pc~0 == 1); 3498#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 3499#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3495#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3496#L773 assume !(activate_threads_~tmp___4~0 != 0); 3741#L773-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3742#L657 assume !(~M_E~0 == 1); 3911#L657-2 assume !(~T1_E~0 == 1); 3649#L662-1 assume !(~T2_E~0 == 1); 3650#L667-1 assume !(~T3_E~0 == 1); 3819#L672-1 assume !(~T4_E~0 == 1); 3573#L677-1 assume !(~T5_E~0 == 1); 3574#L682-1 assume !(~E_M~0 == 1); 3358#L687-1 assume ~E_1~0 == 1;~E_1~0 := 2; 3359#L692-1 assume !(~E_2~0 == 1); 3504#L697-1 assume !(~E_3~0 == 1); 3505#L702-1 assume !(~E_4~0 == 1); 3744#L707-1 assume !(~E_5~0 == 1); 3745#L712-1 assume { :end_inline_reset_delta_events } true; 3380#L918-3 [2018-11-10 05:51:06,100 INFO L795 eck$LassoCheckResult]: Loop: 3380#L918-3 assume true; 3381#L918-1 assume !false; 3404#L919 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 3586#L564 assume true; 3727#L484-1 assume !false; 3706#L485 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3644#L442 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 3549#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3641#L475 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 3600#L489 assume !(eval_~tmp~0 != 0); 3602#L579 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 3695#L397-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 3591#L589-3 assume ~M_E~0 == 0;~M_E~0 := 1; 3553#L589-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 3554#L594-3 assume !(~T2_E~0 == 0); 3598#L599-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 3599#L604-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 3481#L609-3 assume ~T5_E~0 == 0;~T5_E~0 := 1; 3482#L614-3 assume ~E_M~0 == 0;~E_M~0 := 1; 3729#L619-3 assume ~E_1~0 == 0;~E_1~0 := 1; 3730#L624-3 assume ~E_2~0 == 0;~E_2~0 := 1; 3636#L629-3 assume ~E_3~0 == 0;~E_3~0 := 1; 3637#L634-3 assume !(~E_4~0 == 0); 3704#L639-3 assume ~E_5~0 == 0;~E_5~0 := 1; 3587#L644-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3588#L282-21 assume ~m_pc~0 == 1; 3904#L283-7 assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 3835#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3836#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3842#L733-21 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 3843#L733-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3386#L301-21 assume !(~t1_pc~0 == 1); 3384#L301-23 is_transmit1_triggered_~__retres1~1 := 0; 3385#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3430#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3433#L741-21 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 3389#L741-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3390#L320-21 assume ~t2_pc~0 == 1; 3648#L321-7 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 3631#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3663#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3667#L749-21 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 3668#L749-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3677#L339-21 assume ~t3_pc~0 == 1; 3761#L340-7 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 3762#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3759#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3760#L757-21 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 3803#L757-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3804#L358-21 assume ~t4_pc~0 == 1; 3864#L359-7 assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 3541#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3542#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3862#L765-21 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 3896#L765-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3501#L377-21 assume ~t5_pc~0 == 1; 3415#L378-7 assume ~E_5~0 == 1;is_transmit5_triggered_~__retres1~5 := 1; 3416#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3413#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3414#L773-21 assume !(activate_threads_~tmp___4~0 != 0); 3711#L773-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3712#L657-3 assume ~M_E~0 == 1;~M_E~0 := 2; 3910#L657-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 3632#L662-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 3633#L667-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 3702#L672-3 assume !(~T4_E~0 == 1); 3581#L677-3 assume ~T5_E~0 == 1;~T5_E~0 := 2; 3582#L682-3 assume ~E_M~0 == 1;~E_M~0 := 2; 3365#L687-3 assume ~E_1~0 == 1;~E_1~0 := 2; 3366#L692-3 assume ~E_2~0 == 1;~E_2~0 := 2; 3509#L697-3 assume ~E_3~0 == 1;~E_3~0 := 2; 3510#L702-3 assume ~E_4~0 == 1;~E_4~0 := 2; 3747#L707-3 assume ~E_5~0 == 1;~E_5~0 := 2; 3748#L712-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3607#L442-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 3556#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3642#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 3643#L937 assume !(start_simulation_~tmp~3 == 0); 3654#L937-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3610#L442-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 3562#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3608#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 3609#L892 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 3820#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 3827#L900 start_simulation_#t~ret16 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 3717#L950 assume !(start_simulation_~tmp___0~1 != 0); 3380#L918-3 [2018-11-10 05:51:06,100 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:06,100 INFO L82 PathProgramCache]: Analyzing trace with hash -946788410, now seen corresponding path program 1 times [2018-11-10 05:51:06,100 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:06,101 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:06,101 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:06,101 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:06,101 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:06,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:06,131 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:51:06,131 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:51:06,131 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 05:51:06,132 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 05:51:06,132 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:06,132 INFO L82 PathProgramCache]: Analyzing trace with hash 1849701175, now seen corresponding path program 1 times [2018-11-10 05:51:06,132 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:06,132 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:06,133 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:06,133 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:06,133 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:06,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:06,181 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:51:06,181 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:51:06,182 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 05:51:06,182 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 05:51:06,182 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 05:51:06,182 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 05:51:06,183 INFO L87 Difference]: Start difference. First operand 554 states and 824 transitions. cyclomatic complexity: 271 Second operand 3 states. [2018-11-10 05:51:06,191 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:51:06,191 INFO L93 Difference]: Finished difference Result 554 states and 823 transitions. [2018-11-10 05:51:06,192 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 05:51:06,192 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 554 states and 823 transitions. [2018-11-10 05:51:06,194 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 475 [2018-11-10 05:51:06,196 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 554 states to 554 states and 823 transitions. [2018-11-10 05:51:06,196 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 554 [2018-11-10 05:51:06,197 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 554 [2018-11-10 05:51:06,197 INFO L73 IsDeterministic]: Start isDeterministic. Operand 554 states and 823 transitions. [2018-11-10 05:51:06,198 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 05:51:06,198 INFO L705 BuchiCegarLoop]: Abstraction has 554 states and 823 transitions. [2018-11-10 05:51:06,199 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 554 states and 823 transitions. [2018-11-10 05:51:06,204 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 554 to 554. [2018-11-10 05:51:06,204 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 554 states. [2018-11-10 05:51:06,206 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 554 states to 554 states and 823 transitions. [2018-11-10 05:51:06,206 INFO L728 BuchiCegarLoop]: Abstraction has 554 states and 823 transitions. [2018-11-10 05:51:06,206 INFO L608 BuchiCegarLoop]: Abstraction has 554 states and 823 transitions. [2018-11-10 05:51:06,206 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ [2018-11-10 05:51:06,206 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 554 states and 823 transitions. [2018-11-10 05:51:06,208 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 475 [2018-11-10 05:51:06,208 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:51:06,208 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:51:06,210 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:06,210 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:06,210 INFO L793 eck$LassoCheckResult]: Stem: 4936#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 4884#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4885#L881 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 4806#L397 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4807#L404 assume ~m_i~0 == 1;~m_st~0 := 0; 5022#L404-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 4726#L409-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 4727#L414-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 4809#L419-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 4674#L424-1 assume !(~t5_i~0 == 1);~t5_st~0 := 2; 4675#L429-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4694#L589 assume ~M_E~0 == 0;~M_E~0 := 1; 4695#L589-2 assume !(~T1_E~0 == 0); 4704#L594-1 assume !(~T2_E~0 == 0); 4482#L599-1 assume !(~T3_E~0 == 0); 4483#L604-1 assume !(~T4_E~0 == 0); 4627#L609-1 assume !(~T5_E~0 == 0); 4628#L614-1 assume !(~E_M~0 == 0); 4864#L619-1 assume !(~E_1~0 == 0); 4865#L624-1 assume ~E_2~0 == 0;~E_2~0 := 1; 4743#L629-1 assume !(~E_3~0 == 0); 4744#L634-1 assume !(~E_4~0 == 0); 4814#L639-1 assume !(~E_5~0 == 0); 4690#L644-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4691#L282 assume !(~m_pc~0 == 1); 4965#L282-2 is_master_triggered_~__retres1~0 := 0; 4969#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4970#L294 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 5006#L733 assume !(activate_threads_~tmp~1 != 0); 5007#L733-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4608#L301 assume ~t1_pc~0 == 1; 4609#L302 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 4565#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4566#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 4633#L741 assume !(activate_threads_~tmp___0~0 != 0); 4617#L741-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4618#L320 assume ~t2_pc~0 == 1; 4730#L321 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 4731#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4728#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4729#L749 assume !(activate_threads_~tmp___1~0 != 0); 4933#L749-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4927#L339 assume !(~t3_pc~0 == 1); 4888#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 4887#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4916#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4917#L757 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 5015#L757-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4682#L358 assume ~t4_pc~0 == 1; 4683#L359 assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 4635#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4681#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4709#L765 assume !(activate_threads_~tmp___3~0 != 0); 4710#L765-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4711#L377 assume !(~t5_pc~0 == 1); 4614#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 4615#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4610#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4611#L773 assume !(activate_threads_~tmp___4~0 != 0); 4856#L773-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4857#L657 assume !(~M_E~0 == 1); 5026#L657-2 assume !(~T1_E~0 == 1); 4764#L662-1 assume !(~T2_E~0 == 1); 4765#L667-1 assume !(~T3_E~0 == 1); 4934#L672-1 assume !(~T4_E~0 == 1); 4688#L677-1 assume !(~T5_E~0 == 1); 4689#L682-1 assume !(~E_M~0 == 1); 4473#L687-1 assume ~E_1~0 == 1;~E_1~0 := 2; 4474#L692-1 assume !(~E_2~0 == 1); 4619#L697-1 assume !(~E_3~0 == 1); 4620#L702-1 assume !(~E_4~0 == 1); 4859#L707-1 assume !(~E_5~0 == 1); 4860#L712-1 assume { :end_inline_reset_delta_events } true; 4495#L918-3 [2018-11-10 05:51:06,211 INFO L795 eck$LassoCheckResult]: Loop: 4495#L918-3 assume true; 4496#L918-1 assume !false; 4519#L919 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 4701#L564 assume true; 4842#L484-1 assume !false; 4821#L485 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4759#L442 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 4664#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4756#L475 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 4715#L489 assume !(eval_~tmp~0 != 0); 4717#L579 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 4810#L397-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 4706#L589-3 assume ~M_E~0 == 0;~M_E~0 := 1; 4668#L589-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 4669#L594-3 assume !(~T2_E~0 == 0); 4713#L599-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 4714#L604-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 4596#L609-3 assume ~T5_E~0 == 0;~T5_E~0 := 1; 4597#L614-3 assume ~E_M~0 == 0;~E_M~0 := 1; 4844#L619-3 assume ~E_1~0 == 0;~E_1~0 := 1; 4845#L624-3 assume ~E_2~0 == 0;~E_2~0 := 1; 4751#L629-3 assume ~E_3~0 == 0;~E_3~0 := 1; 4752#L634-3 assume !(~E_4~0 == 0); 4819#L639-3 assume ~E_5~0 == 0;~E_5~0 := 1; 4702#L644-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4703#L282-21 assume ~m_pc~0 == 1; 5019#L283-7 assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 4949#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4950#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 4955#L733-21 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 4956#L733-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4501#L301-21 assume !(~t1_pc~0 == 1); 4499#L301-23 is_transmit1_triggered_~__retres1~1 := 0; 4500#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4547#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 4548#L741-21 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 4506#L741-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4507#L320-21 assume !(~t2_pc~0 == 1); 4745#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 4746#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4778#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4782#L749-21 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 4783#L749-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4792#L339-21 assume ~t3_pc~0 == 1; 4876#L340-7 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 4877#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4874#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4875#L757-21 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 4918#L757-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4919#L358-21 assume ~t4_pc~0 == 1; 4979#L359-7 assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 4656#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4657#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4978#L765-21 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 5011#L765-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4616#L377-21 assume ~t5_pc~0 == 1; 4533#L378-7 assume ~E_5~0 == 1;is_transmit5_triggered_~__retres1~5 := 1; 4534#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4528#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4529#L773-21 assume !(activate_threads_~tmp___4~0 != 0); 4826#L773-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4827#L657-3 assume ~M_E~0 == 1;~M_E~0 := 2; 5025#L657-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 4747#L662-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 4748#L667-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 4817#L672-3 assume !(~T4_E~0 == 1); 4696#L677-3 assume ~T5_E~0 == 1;~T5_E~0 := 2; 4697#L682-3 assume ~E_M~0 == 1;~E_M~0 := 2; 4480#L687-3 assume ~E_1~0 == 1;~E_1~0 := 2; 4481#L692-3 assume ~E_2~0 == 1;~E_2~0 := 2; 4624#L697-3 assume ~E_3~0 == 1;~E_3~0 := 2; 4625#L702-3 assume ~E_4~0 == 1;~E_4~0 := 2; 4862#L707-3 assume ~E_5~0 == 1;~E_5~0 := 2; 4863#L712-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4722#L442-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 4671#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4757#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 4758#L937 assume !(start_simulation_~tmp~3 == 0); 4769#L937-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4725#L442-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 4677#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4723#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 4724#L892 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 4935#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 4942#L900 start_simulation_#t~ret16 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 4832#L950 assume !(start_simulation_~tmp___0~1 != 0); 4495#L918-3 [2018-11-10 05:51:06,211 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:06,211 INFO L82 PathProgramCache]: Analyzing trace with hash 739391428, now seen corresponding path program 1 times [2018-11-10 05:51:06,212 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:06,212 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:06,213 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:06,213 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:06,213 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:06,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:06,249 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:51:06,250 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:51:06,250 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 05:51:06,250 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 05:51:06,250 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:06,250 INFO L82 PathProgramCache]: Analyzing trace with hash -977062792, now seen corresponding path program 2 times [2018-11-10 05:51:06,250 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:06,251 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:06,251 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:06,252 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:06,252 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:06,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:06,292 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:51:06,293 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:51:06,293 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 05:51:06,293 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 05:51:06,293 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 05:51:06,293 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 05:51:06,294 INFO L87 Difference]: Start difference. First operand 554 states and 823 transitions. cyclomatic complexity: 270 Second operand 3 states. [2018-11-10 05:51:06,312 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:51:06,312 INFO L93 Difference]: Finished difference Result 554 states and 822 transitions. [2018-11-10 05:51:06,313 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 05:51:06,313 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 554 states and 822 transitions. [2018-11-10 05:51:06,315 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 475 [2018-11-10 05:51:06,317 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 554 states to 554 states and 822 transitions. [2018-11-10 05:51:06,317 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 554 [2018-11-10 05:51:06,318 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 554 [2018-11-10 05:51:06,318 INFO L73 IsDeterministic]: Start isDeterministic. Operand 554 states and 822 transitions. [2018-11-10 05:51:06,319 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 05:51:06,319 INFO L705 BuchiCegarLoop]: Abstraction has 554 states and 822 transitions. [2018-11-10 05:51:06,319 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 554 states and 822 transitions. [2018-11-10 05:51:06,324 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 554 to 554. [2018-11-10 05:51:06,324 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 554 states. [2018-11-10 05:51:06,325 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 554 states to 554 states and 822 transitions. [2018-11-10 05:51:06,325 INFO L728 BuchiCegarLoop]: Abstraction has 554 states and 822 transitions. [2018-11-10 05:51:06,325 INFO L608 BuchiCegarLoop]: Abstraction has 554 states and 822 transitions. [2018-11-10 05:51:06,326 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ [2018-11-10 05:51:06,326 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 554 states and 822 transitions. [2018-11-10 05:51:06,327 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 475 [2018-11-10 05:51:06,328 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:51:06,328 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:51:06,329 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:06,329 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:06,329 INFO L793 eck$LassoCheckResult]: Stem: 6051#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 5999#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 6000#L881 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 5921#L397 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5922#L404 assume ~m_i~0 == 1;~m_st~0 := 0; 6137#L404-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 5841#L409-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 5842#L414-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 5924#L419-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 5789#L424-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 5790#L429-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5809#L589 assume ~M_E~0 == 0;~M_E~0 := 1; 5810#L589-2 assume !(~T1_E~0 == 0); 5819#L594-1 assume !(~T2_E~0 == 0); 5597#L599-1 assume !(~T3_E~0 == 0); 5598#L604-1 assume !(~T4_E~0 == 0); 5742#L609-1 assume !(~T5_E~0 == 0); 5743#L614-1 assume !(~E_M~0 == 0); 5979#L619-1 assume !(~E_1~0 == 0); 5980#L624-1 assume ~E_2~0 == 0;~E_2~0 := 1; 5858#L629-1 assume !(~E_3~0 == 0); 5859#L634-1 assume !(~E_4~0 == 0); 5929#L639-1 assume !(~E_5~0 == 0); 5805#L644-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5806#L282 assume !(~m_pc~0 == 1); 6080#L282-2 is_master_triggered_~__retres1~0 := 0; 6084#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6085#L294 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 6121#L733 assume !(activate_threads_~tmp~1 != 0); 6122#L733-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5723#L301 assume ~t1_pc~0 == 1; 5724#L302 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 5680#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5681#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5748#L741 assume !(activate_threads_~tmp___0~0 != 0); 5732#L741-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5733#L320 assume ~t2_pc~0 == 1; 5845#L321 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 5846#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5843#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5844#L749 assume !(activate_threads_~tmp___1~0 != 0); 6048#L749-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6042#L339 assume !(~t3_pc~0 == 1); 6003#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 6002#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6031#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 6032#L757 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 6130#L757-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5797#L358 assume ~t4_pc~0 == 1; 5798#L359 assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 5750#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5796#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5824#L765 assume !(activate_threads_~tmp___3~0 != 0); 5825#L765-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5826#L377 assume !(~t5_pc~0 == 1); 5729#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 5730#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5725#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5726#L773 assume !(activate_threads_~tmp___4~0 != 0); 5971#L773-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5972#L657 assume !(~M_E~0 == 1); 6141#L657-2 assume !(~T1_E~0 == 1); 5879#L662-1 assume !(~T2_E~0 == 1); 5880#L667-1 assume !(~T3_E~0 == 1); 6049#L672-1 assume !(~T4_E~0 == 1); 5803#L677-1 assume !(~T5_E~0 == 1); 5804#L682-1 assume !(~E_M~0 == 1); 5588#L687-1 assume ~E_1~0 == 1;~E_1~0 := 2; 5589#L692-1 assume !(~E_2~0 == 1); 5734#L697-1 assume !(~E_3~0 == 1); 5735#L702-1 assume !(~E_4~0 == 1); 5974#L707-1 assume !(~E_5~0 == 1); 5975#L712-1 assume { :end_inline_reset_delta_events } true; 5610#L918-3 [2018-11-10 05:51:06,330 INFO L795 eck$LassoCheckResult]: Loop: 5610#L918-3 assume true; 5611#L918-1 assume !false; 5634#L919 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 5814#L564 assume true; 5957#L484-1 assume !false; 5936#L485 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5874#L442 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 5779#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5871#L475 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 5830#L489 assume !(eval_~tmp~0 != 0); 5832#L579 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 5925#L397-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 5821#L589-3 assume ~M_E~0 == 0;~M_E~0 := 1; 5783#L589-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 5784#L594-3 assume !(~T2_E~0 == 0); 5828#L599-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 5829#L604-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 5711#L609-3 assume ~T5_E~0 == 0;~T5_E~0 := 1; 5712#L614-3 assume ~E_M~0 == 0;~E_M~0 := 1; 5959#L619-3 assume ~E_1~0 == 0;~E_1~0 := 1; 5960#L624-3 assume ~E_2~0 == 0;~E_2~0 := 1; 5866#L629-3 assume ~E_3~0 == 0;~E_3~0 := 1; 5867#L634-3 assume !(~E_4~0 == 0); 5934#L639-3 assume ~E_5~0 == 0;~E_5~0 := 1; 5817#L644-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5818#L282-21 assume ~m_pc~0 == 1; 6134#L283-7 assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 6065#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6066#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 6072#L733-21 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 6073#L733-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5616#L301-21 assume ~t1_pc~0 == 1; 5617#L302-7 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 5615#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5662#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5663#L741-21 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 5621#L741-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5622#L320-21 assume !(~t2_pc~0 == 1); 5860#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 5861#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5893#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5898#L749-21 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 5899#L749-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5908#L339-21 assume ~t3_pc~0 == 1; 5991#L340-7 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 5992#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5989#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5990#L757-21 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 6033#L757-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6034#L358-21 assume ~t4_pc~0 == 1; 6094#L359-7 assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 5771#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5772#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6093#L765-21 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 6126#L765-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5731#L377-21 assume ~t5_pc~0 == 1; 5648#L378-7 assume ~E_5~0 == 1;is_transmit5_triggered_~__retres1~5 := 1; 5649#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5643#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5644#L773-21 assume !(activate_threads_~tmp___4~0 != 0); 5942#L773-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5943#L657-3 assume ~M_E~0 == 1;~M_E~0 := 2; 6140#L657-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 5862#L662-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 5863#L667-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 5932#L672-3 assume !(~T4_E~0 == 1); 5811#L677-3 assume ~T5_E~0 == 1;~T5_E~0 := 2; 5812#L682-3 assume ~E_M~0 == 1;~E_M~0 := 2; 5595#L687-3 assume ~E_1~0 == 1;~E_1~0 := 2; 5596#L692-3 assume ~E_2~0 == 1;~E_2~0 := 2; 5739#L697-3 assume ~E_3~0 == 1;~E_3~0 := 2; 5740#L702-3 assume ~E_4~0 == 1;~E_4~0 := 2; 5977#L707-3 assume ~E_5~0 == 1;~E_5~0 := 2; 5978#L712-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5837#L442-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 5786#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5872#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 5873#L937 assume !(start_simulation_~tmp~3 == 0); 5884#L937-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5840#L442-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 5792#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5838#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 5839#L892 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 6050#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 6057#L900 start_simulation_#t~ret16 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 5947#L950 assume !(start_simulation_~tmp___0~1 != 0); 5610#L918-3 [2018-11-10 05:51:06,330 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:06,330 INFO L82 PathProgramCache]: Analyzing trace with hash 793784326, now seen corresponding path program 1 times [2018-11-10 05:51:06,330 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:06,330 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:06,331 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:06,331 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 05:51:06,331 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:06,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:06,375 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:51:06,376 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:51:06,376 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 05:51:06,376 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 05:51:06,378 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:06,378 INFO L82 PathProgramCache]: Analyzing trace with hash 131065847, now seen corresponding path program 2 times [2018-11-10 05:51:06,378 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:06,378 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:06,379 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:06,379 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:06,379 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:06,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:06,411 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:51:06,415 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:51:06,415 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 05:51:06,415 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 05:51:06,415 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 05:51:06,415 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 05:51:06,416 INFO L87 Difference]: Start difference. First operand 554 states and 822 transitions. cyclomatic complexity: 269 Second operand 3 states. [2018-11-10 05:51:06,448 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:51:06,448 INFO L93 Difference]: Finished difference Result 985 states and 1455 transitions. [2018-11-10 05:51:06,449 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 05:51:06,449 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 985 states and 1455 transitions. [2018-11-10 05:51:06,454 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 906 [2018-11-10 05:51:06,458 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 985 states to 985 states and 1455 transitions. [2018-11-10 05:51:06,458 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 985 [2018-11-10 05:51:06,459 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 985 [2018-11-10 05:51:06,459 INFO L73 IsDeterministic]: Start isDeterministic. Operand 985 states and 1455 transitions. [2018-11-10 05:51:06,461 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 05:51:06,461 INFO L705 BuchiCegarLoop]: Abstraction has 985 states and 1455 transitions. [2018-11-10 05:51:06,462 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 985 states and 1455 transitions. [2018-11-10 05:51:06,475 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 985 to 985. [2018-11-10 05:51:06,475 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 985 states. [2018-11-10 05:51:06,478 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 985 states to 985 states and 1455 transitions. [2018-11-10 05:51:06,478 INFO L728 BuchiCegarLoop]: Abstraction has 985 states and 1455 transitions. [2018-11-10 05:51:06,478 INFO L608 BuchiCegarLoop]: Abstraction has 985 states and 1455 transitions. [2018-11-10 05:51:06,478 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ [2018-11-10 05:51:06,478 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 985 states and 1455 transitions. [2018-11-10 05:51:06,482 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 906 [2018-11-10 05:51:06,482 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:51:06,482 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:51:06,483 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:06,483 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:06,483 INFO L793 eck$LassoCheckResult]: Stem: 7651#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 7588#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 7589#L881 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 7493#L397 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7494#L404 assume ~m_i~0 == 1;~m_st~0 := 0; 7752#L404-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 7400#L409-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 7401#L414-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 7495#L419-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 7341#L424-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 7342#L429-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7361#L589 assume !(~M_E~0 == 0); 7362#L589-2 assume !(~T1_E~0 == 0); 7371#L594-1 assume !(~T2_E~0 == 0); 7143#L599-1 assume !(~T3_E~0 == 0); 7144#L604-1 assume !(~T4_E~0 == 0); 7292#L609-1 assume !(~T5_E~0 == 0); 7293#L614-1 assume !(~E_M~0 == 0); 7561#L619-1 assume !(~E_1~0 == 0); 7562#L624-1 assume ~E_2~0 == 0;~E_2~0 := 1; 7418#L629-1 assume !(~E_3~0 == 0); 7419#L634-1 assume !(~E_4~0 == 0); 7502#L639-1 assume !(~E_5~0 == 0); 7357#L644-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7358#L282 assume !(~m_pc~0 == 1); 7690#L282-2 is_master_triggered_~__retres1~0 := 0; 7692#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7693#L294 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 7734#L733 assume !(activate_threads_~tmp~1 != 0); 7735#L733-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7274#L301 assume ~t1_pc~0 == 1; 7275#L302 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 7227#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7228#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 7299#L741 assume !(activate_threads_~tmp___0~0 != 0); 7283#L741-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7284#L320 assume ~t2_pc~0 == 1; 7405#L321 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 7406#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7403#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 7404#L749 assume !(activate_threads_~tmp___1~0 != 0); 7648#L749-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7639#L339 assume !(~t3_pc~0 == 1); 7592#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 7591#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7620#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7621#L757 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 7744#L757-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7349#L358 assume ~t4_pc~0 == 1; 7350#L359 assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 7301#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7346#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7376#L765 assume !(activate_threads_~tmp___3~0 != 0); 7377#L765-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7378#L377 assume !(~t5_pc~0 == 1); 7279#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 7280#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7276#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7277#L773 assume !(activate_threads_~tmp___4~0 != 0); 7553#L773-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7554#L657 assume !(~M_E~0 == 1); 7762#L657-2 assume !(~T1_E~0 == 1); 7443#L662-1 assume !(~T2_E~0 == 1); 7444#L667-1 assume !(~T3_E~0 == 1); 7649#L672-1 assume !(~T4_E~0 == 1); 7355#L677-1 assume !(~T5_E~0 == 1); 7356#L682-1 assume !(~E_M~0 == 1); 7134#L687-1 assume ~E_1~0 == 1;~E_1~0 := 2; 7135#L692-1 assume !(~E_2~0 == 1); 7285#L697-1 assume !(~E_3~0 == 1); 7286#L702-1 assume !(~E_4~0 == 1); 7555#L707-1 assume !(~E_5~0 == 1); 7556#L712-1 assume { :end_inline_reset_delta_events } true; 7761#L918-3 [2018-11-10 05:51:06,484 INFO L795 eck$LassoCheckResult]: Loop: 7761#L918-3 assume true; 7181#L918-1 assume !false; 7182#L919 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 7538#L564 assume true; 7539#L484-1 assume !false; 7508#L485 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7509#L442 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 7777#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7432#L475 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 7433#L489 assume !(eval_~tmp~0 != 0); 7776#L579 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 7775#L397-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 7373#L589-3 assume !(~M_E~0 == 0); 7335#L589-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 7336#L594-3 assume !(~T2_E~0 == 0); 7384#L599-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 7385#L604-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 7262#L609-3 assume ~T5_E~0 == 0;~T5_E~0 := 1; 7263#L614-3 assume ~E_M~0 == 0;~E_M~0 := 1; 7541#L619-3 assume ~E_1~0 == 0;~E_1~0 := 1; 7542#L624-3 assume ~E_2~0 == 0;~E_2~0 := 1; 7426#L629-3 assume ~E_3~0 == 0;~E_3~0 := 1; 7427#L634-3 assume !(~E_4~0 == 0); 7507#L639-3 assume ~E_5~0 == 0;~E_5~0 := 1; 7369#L644-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7370#L282-21 assume ~m_pc~0 == 1; 7748#L283-7 assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 7670#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7671#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 7753#L733-21 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 7681#L733-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7682#L301-21 assume ~t1_pc~0 == 1; 7381#L302-7 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 7161#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7211#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 7212#L741-21 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 7213#L741-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7440#L320-21 assume !(~t2_pc~0 == 1); 7441#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 7459#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7460#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 7465#L749-21 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 7466#L749-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7622#L339-21 assume ~t3_pc~0 == 1; 7623#L340-7 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 7633#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7634#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7636#L757-21 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 7637#L757-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7771#L358-21 assume !(~t4_pc~0 == 1); 7769#L358-23 is_transmit4_triggered_~__retres1~4 := 0; 7322#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7323#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7739#L765-21 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 7740#L765-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7282#L377-21 assume ~t5_pc~0 == 1; 7196#L378-7 assume ~E_5~0 == 1;is_transmit5_triggered_~__retres1~5 := 1; 7197#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7764#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7531#L773-21 assume !(activate_threads_~tmp___4~0 != 0); 7532#L773-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7757#L657-3 assume !(~M_E~0 == 1); 7758#L657-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 7422#L662-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 7423#L667-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 7505#L672-3 assume !(~T4_E~0 == 1); 7363#L677-3 assume ~T5_E~0 == 1;~T5_E~0 := 2; 7364#L682-3 assume ~E_M~0 == 1;~E_M~0 := 2; 7141#L687-3 assume ~E_1~0 == 1;~E_1~0 := 2; 7142#L692-3 assume ~E_2~0 == 1;~E_2~0 := 2; 7290#L697-3 assume ~E_3~0 == 1;~E_3~0 := 2; 7291#L702-3 assume ~E_4~0 == 1;~E_4~0 := 2; 7559#L707-3 assume ~E_5~0 == 1;~E_5~0 := 2; 7560#L712-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7397#L442-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 7338#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7435#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 7436#L937 assume !(start_simulation_~tmp~3 == 0); 7937#L937-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7402#L442-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 7344#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7398#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 7399#L892 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 7650#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 7788#L900 start_simulation_#t~ret16 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 7787#L950 assume !(start_simulation_~tmp___0~1 != 0); 7761#L918-3 [2018-11-10 05:51:06,484 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:06,484 INFO L82 PathProgramCache]: Analyzing trace with hash 1473056580, now seen corresponding path program 1 times [2018-11-10 05:51:06,484 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:06,484 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:06,485 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:06,485 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 05:51:06,485 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:06,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:06,508 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:51:06,508 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:51:06,508 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 05:51:06,509 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 05:51:06,509 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:06,509 INFO L82 PathProgramCache]: Analyzing trace with hash -2010870024, now seen corresponding path program 1 times [2018-11-10 05:51:06,509 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:06,509 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:06,510 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:06,510 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:06,510 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:06,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:06,541 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:51:06,541 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:51:06,541 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 05:51:06,542 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 05:51:06,542 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 05:51:06,542 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 05:51:06,542 INFO L87 Difference]: Start difference. First operand 985 states and 1455 transitions. cyclomatic complexity: 471 Second operand 3 states. [2018-11-10 05:51:06,585 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:51:06,585 INFO L93 Difference]: Finished difference Result 985 states and 1433 transitions. [2018-11-10 05:51:06,586 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 05:51:06,586 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 985 states and 1433 transitions. [2018-11-10 05:51:06,589 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 906 [2018-11-10 05:51:06,591 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 985 states to 985 states and 1433 transitions. [2018-11-10 05:51:06,591 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 985 [2018-11-10 05:51:06,592 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 985 [2018-11-10 05:51:06,592 INFO L73 IsDeterministic]: Start isDeterministic. Operand 985 states and 1433 transitions. [2018-11-10 05:51:06,593 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 05:51:06,593 INFO L705 BuchiCegarLoop]: Abstraction has 985 states and 1433 transitions. [2018-11-10 05:51:06,594 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 985 states and 1433 transitions. [2018-11-10 05:51:06,602 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 985 to 985. [2018-11-10 05:51:06,603 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 985 states. [2018-11-10 05:51:06,604 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 985 states to 985 states and 1433 transitions. [2018-11-10 05:51:06,604 INFO L728 BuchiCegarLoop]: Abstraction has 985 states and 1433 transitions. [2018-11-10 05:51:06,604 INFO L608 BuchiCegarLoop]: Abstraction has 985 states and 1433 transitions. [2018-11-10 05:51:06,604 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ [2018-11-10 05:51:06,605 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 985 states and 1433 transitions. [2018-11-10 05:51:06,607 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 906 [2018-11-10 05:51:06,607 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:51:06,608 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:51:06,609 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:06,609 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:06,609 INFO L793 eck$LassoCheckResult]: Stem: 9611#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 9550#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 9551#L881 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 9460#L397 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9461#L404 assume ~m_i~0 == 1;~m_st~0 := 0; 9713#L404-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 9374#L409-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 9375#L414-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 9463#L419-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 9316#L424-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 9317#L429-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9336#L589 assume !(~M_E~0 == 0); 9337#L589-2 assume !(~T1_E~0 == 0); 9346#L594-1 assume !(~T2_E~0 == 0); 9120#L599-1 assume !(~T3_E~0 == 0); 9121#L604-1 assume !(~T4_E~0 == 0); 9269#L609-1 assume !(~T5_E~0 == 0); 9270#L614-1 assume !(~E_M~0 == 0); 9525#L619-1 assume !(~E_1~0 == 0); 9526#L624-1 assume !(~E_2~0 == 0); 9389#L629-1 assume !(~E_3~0 == 0); 9390#L634-1 assume !(~E_4~0 == 0); 9469#L639-1 assume !(~E_5~0 == 0); 9332#L644-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9333#L282 assume !(~m_pc~0 == 1); 9648#L282-2 is_master_triggered_~__retres1~0 := 0; 9652#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9653#L294 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 9692#L733 assume !(activate_threads_~tmp~1 != 0); 9693#L733-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9250#L301 assume ~t1_pc~0 == 1; 9251#L302 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 9207#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9208#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 9275#L741 assume !(activate_threads_~tmp___0~0 != 0); 9259#L741-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9260#L320 assume !(~t2_pc~0 == 1); 9379#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 9450#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9376#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 9377#L749 assume !(activate_threads_~tmp___1~0 != 0); 9608#L749-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9602#L339 assume !(~t3_pc~0 == 1); 9554#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 9553#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9584#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 9585#L757 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 9703#L757-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9324#L358 assume ~t4_pc~0 == 1; 9325#L359 assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 9277#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9323#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 9351#L765 assume !(activate_threads_~tmp___3~0 != 0); 9352#L765-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9353#L377 assume !(~t5_pc~0 == 1); 9256#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 9257#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9252#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9253#L773 assume !(activate_threads_~tmp___4~0 != 0); 9517#L773-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9518#L657 assume !(~M_E~0 == 1); 9721#L657-2 assume !(~T1_E~0 == 1); 9414#L662-1 assume !(~T2_E~0 == 1); 9415#L667-1 assume !(~T3_E~0 == 1); 9609#L672-1 assume !(~T4_E~0 == 1); 9330#L677-1 assume !(~T5_E~0 == 1); 9331#L682-1 assume !(~E_M~0 == 1); 9111#L687-1 assume ~E_1~0 == 1;~E_1~0 := 2; 9112#L692-1 assume !(~E_2~0 == 1); 9261#L697-1 assume !(~E_3~0 == 1); 9262#L702-1 assume !(~E_4~0 == 1); 9519#L707-1 assume !(~E_5~0 == 1); 9520#L712-1 assume { :end_inline_reset_delta_events } true; 9133#L918-3 [2018-11-10 05:51:06,609 INFO L795 eck$LassoCheckResult]: Loop: 9133#L918-3 assume true; 9134#L918-1 assume !false; 9753#L919 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 9750#L564 assume true; 9613#L484-1 assume !false; 9614#L485 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 9404#L442 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 9306#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 9479#L475 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 9362#L489 assume !(eval_~tmp~0 != 0); 9364#L579 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 9464#L397-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 9465#L589-3 assume !(~M_E~0 == 0); 9740#L589-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 9618#L594-3 assume !(~T2_E~0 == 0); 9619#L599-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 9582#L604-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 9583#L609-3 assume ~T5_E~0 == 0;~T5_E~0 := 1; 9700#L614-3 assume ~E_M~0 == 0;~E_M~0 := 1; 9505#L619-3 assume ~E_1~0 == 0;~E_1~0 := 1; 9506#L624-3 assume !(~E_2~0 == 0); 9720#L629-3 assume ~E_3~0 == 0;~E_3~0 := 1; 9737#L634-3 assume !(~E_4~0 == 0); 9736#L639-3 assume ~E_5~0 == 0;~E_5~0 := 1; 9344#L644-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9345#L282-21 assume !(~m_pc~0 == 1); 9734#L282-23 is_master_triggered_~__retres1~0 := 0; 9630#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9631#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 9712#L733-21 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 9641#L733-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9642#L301-21 assume !(~t1_pc~0 == 1); 9137#L301-23 is_transmit1_triggered_~__retres1~1 := 0; 9138#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9188#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 9189#L741-21 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 9190#L741-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9411#L320-21 assume !(~t2_pc~0 == 1); 9412#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 9428#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9429#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 9434#L749-21 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 9435#L749-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9586#L339-21 assume ~t3_pc~0 == 1; 9587#L340-7 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 9596#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9597#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 9599#L757-21 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 9600#L757-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9730#L358-21 assume !(~t4_pc~0 == 1); 9728#L358-23 is_transmit4_triggered_~__retres1~4 := 0; 9298#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9299#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 9697#L765-21 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 9698#L765-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9258#L377-21 assume ~t5_pc~0 == 1; 9174#L378-7 assume ~E_5~0 == 1;is_transmit5_triggered_~__retres1~5 := 1; 9175#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9723#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9497#L773-21 assume !(activate_threads_~tmp___4~0 != 0); 9498#L773-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9717#L657-3 assume !(~M_E~0 == 1); 9718#L657-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 9393#L662-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 9394#L667-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 9472#L672-3 assume !(~T4_E~0 == 1); 9338#L677-3 assume ~T5_E~0 == 1;~T5_E~0 := 2; 9339#L682-3 assume ~E_M~0 == 1;~E_M~0 := 2; 9118#L687-3 assume ~E_1~0 == 1;~E_1~0 := 2; 9119#L692-3 assume !(~E_2~0 == 1); 9266#L697-3 assume ~E_3~0 == 1;~E_3~0 := 2; 9267#L702-3 assume ~E_4~0 == 1;~E_4~0 := 2; 9523#L707-3 assume ~E_5~0 == 1;~E_5~0 := 2; 9524#L712-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 9370#L442-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 9313#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 9405#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 9406#L937 assume !(start_simulation_~tmp~3 == 0); 9419#L937-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 9373#L442-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 9319#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 9371#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 9372#L892 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 9610#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 9622#L900 start_simulation_#t~ret16 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 9490#L950 assume !(start_simulation_~tmp___0~1 != 0); 9133#L918-3 [2018-11-10 05:51:06,609 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:06,609 INFO L82 PathProgramCache]: Analyzing trace with hash -820631741, now seen corresponding path program 1 times [2018-11-10 05:51:06,609 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:06,610 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:06,610 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:06,610 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:06,610 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:06,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:06,641 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:51:06,641 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:51:06,641 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 05:51:06,641 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 05:51:06,641 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:06,641 INFO L82 PathProgramCache]: Analyzing trace with hash -115814534, now seen corresponding path program 1 times [2018-11-10 05:51:06,642 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:06,642 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:06,642 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:06,642 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:06,642 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:06,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:06,682 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:51:06,683 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:51:06,683 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 05:51:06,683 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 05:51:06,683 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 05:51:06,683 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 05:51:06,683 INFO L87 Difference]: Start difference. First operand 985 states and 1433 transitions. cyclomatic complexity: 449 Second operand 3 states. [2018-11-10 05:51:06,763 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:51:06,763 INFO L93 Difference]: Finished difference Result 1787 states and 2579 transitions. [2018-11-10 05:51:06,764 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 05:51:06,764 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1787 states and 2579 transitions. [2018-11-10 05:51:06,772 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1705 [2018-11-10 05:51:06,779 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1787 states to 1787 states and 2579 transitions. [2018-11-10 05:51:06,779 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1787 [2018-11-10 05:51:06,780 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1787 [2018-11-10 05:51:06,781 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1787 states and 2579 transitions. [2018-11-10 05:51:06,783 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 05:51:06,783 INFO L705 BuchiCegarLoop]: Abstraction has 1787 states and 2579 transitions. [2018-11-10 05:51:06,785 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1787 states and 2579 transitions. [2018-11-10 05:51:06,806 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1787 to 1781. [2018-11-10 05:51:06,807 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1781 states. [2018-11-10 05:51:06,810 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1781 states to 1781 states and 2573 transitions. [2018-11-10 05:51:06,810 INFO L728 BuchiCegarLoop]: Abstraction has 1781 states and 2573 transitions. [2018-11-10 05:51:06,810 INFO L608 BuchiCegarLoop]: Abstraction has 1781 states and 2573 transitions. [2018-11-10 05:51:06,810 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ [2018-11-10 05:51:06,811 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1781 states and 2573 transitions. [2018-11-10 05:51:06,817 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1699 [2018-11-10 05:51:06,817 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:51:06,817 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:51:06,818 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:06,818 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:06,818 INFO L793 eck$LassoCheckResult]: Stem: 12417#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 12355#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 12356#L881 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 12256#L397 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12257#L404 assume ~m_i~0 == 1;~m_st~0 := 0; 12526#L404-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 12165#L409-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 12166#L414-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 12258#L419-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 12090#L424-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 12091#L429-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12110#L589 assume !(~M_E~0 == 0); 12111#L589-2 assume !(~T1_E~0 == 0); 12121#L594-1 assume !(~T2_E~0 == 0); 11898#L599-1 assume !(~T3_E~0 == 0); 11899#L604-1 assume !(~T4_E~0 == 0); 12041#L609-1 assume !(~T5_E~0 == 0); 12042#L614-1 assume !(~E_M~0 == 0); 12326#L619-1 assume !(~E_1~0 == 0); 12327#L624-1 assume !(~E_2~0 == 0); 12181#L629-1 assume !(~E_3~0 == 0); 12182#L634-1 assume !(~E_4~0 == 0); 12264#L639-1 assume !(~E_5~0 == 0); 12106#L644-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12107#L282 assume !(~m_pc~0 == 1); 12448#L282-2 is_master_triggered_~__retres1~0 := 0; 12450#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12451#L294 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 12498#L733 assume !(activate_threads_~tmp~1 != 0); 12499#L733-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12022#L301 assume !(~t1_pc~0 == 1); 12011#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 11976#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11977#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 12048#L741 assume !(activate_threads_~tmp___0~0 != 0); 12030#L741-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12031#L320 assume !(~t2_pc~0 == 1); 12171#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 12243#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12168#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 12169#L749 assume !(activate_threads_~tmp___1~0 != 0); 12414#L749-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12406#L339 assume !(~t3_pc~0 == 1); 12359#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 12358#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12388#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 12389#L757 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 12512#L757-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12098#L358 assume ~t4_pc~0 == 1; 12099#L359 assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 12050#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12095#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 12126#L765 assume !(activate_threads_~tmp___3~0 != 0); 12127#L765-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12128#L377 assume !(~t5_pc~0 == 1); 12026#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 12027#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12023#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12024#L773 assume !(activate_threads_~tmp___4~0 != 0); 12318#L773-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12319#L657 assume !(~M_E~0 == 1); 12533#L657-2 assume !(~T1_E~0 == 1); 12205#L662-1 assume !(~T2_E~0 == 1); 12206#L667-1 assume !(~T3_E~0 == 1); 12415#L672-1 assume !(~T4_E~0 == 1); 12104#L677-1 assume !(~T5_E~0 == 1); 12105#L682-1 assume !(~E_M~0 == 1); 11890#L687-1 assume ~E_1~0 == 1;~E_1~0 := 2; 11891#L692-1 assume !(~E_2~0 == 1); 12032#L697-1 assume !(~E_3~0 == 1); 12033#L702-1 assume !(~E_4~0 == 1); 12320#L707-1 assume !(~E_5~0 == 1); 12321#L712-1 assume { :end_inline_reset_delta_events } true; 11910#L918-3 [2018-11-10 05:51:06,819 INFO L795 eck$LassoCheckResult]: Loop: 11910#L918-3 assume true; 11911#L918-1 assume !false; 11935#L919 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 12132#L564 assume true; 12302#L484-1 assume !false; 12868#L485 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 12866#L442 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 12861#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 12197#L475 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 12144#L489 assume !(eval_~tmp~0 != 0); 12146#L579 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 12858#L397-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 12856#L589-3 assume !(~M_E~0 == 0); 12853#L589-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 12852#L594-3 assume !(~T2_E~0 == 0); 12851#L599-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 12850#L604-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 12849#L609-3 assume ~T5_E~0 == 0;~T5_E~0 := 1; 12848#L614-3 assume ~E_M~0 == 0;~E_M~0 := 1; 12847#L619-3 assume ~E_1~0 == 0;~E_1~0 := 1; 12846#L624-3 assume !(~E_2~0 == 0); 12845#L629-3 assume ~E_3~0 == 0;~E_3~0 := 1; 12844#L634-3 assume !(~E_4~0 == 0); 12843#L639-3 assume ~E_5~0 == 0;~E_5~0 := 1; 12119#L644-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12120#L282-21 assume ~m_pc~0 == 1; 12523#L283-7 assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 12432#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12433#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 12439#L733-21 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 12440#L733-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11916#L301-21 assume !(~t1_pc~0 == 1); 11917#L301-23 is_transmit1_triggered_~__retres1~1 := 0; 13223#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13221#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 13219#L741-21 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 13217#L741-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13213#L320-21 assume !(~t2_pc~0 == 1); 13212#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 13209#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13207#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 13205#L749-21 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 13203#L749-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13201#L339-21 assume ~t3_pc~0 == 1; 13198#L340-7 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 13196#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 13193#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 13192#L757-21 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 13191#L757-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 13190#L358-21 assume !(~t4_pc~0 == 1); 13187#L358-23 is_transmit4_triggered_~__retres1~4 := 0; 13185#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 13183#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 13181#L765-21 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 13179#L765-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 13176#L377-21 assume ~t5_pc~0 == 1; 13173#L378-7 assume ~E_5~0 == 1;is_transmit5_triggered_~__retres1~5 := 1; 13171#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 13169#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 13166#L773-21 assume !(activate_threads_~tmp___4~0 != 0); 13163#L773-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13161#L657-3 assume !(~M_E~0 == 1); 13155#L657-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 13158#L662-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 13156#L667-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 13153#L672-3 assume !(~T4_E~0 == 1); 13151#L677-3 assume ~T5_E~0 == 1;~T5_E~0 := 2; 13149#L682-3 assume ~E_M~0 == 1;~E_M~0 := 2; 13147#L687-3 assume ~E_1~0 == 1;~E_1~0 := 2; 13145#L692-3 assume !(~E_2~0 == 1); 13143#L697-3 assume ~E_3~0 == 1;~E_3~0 := 2; 13141#L702-3 assume ~E_4~0 == 1;~E_4~0 := 2; 13138#L707-3 assume ~E_5~0 == 1;~E_5~0 := 2; 13136#L712-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 13127#L442-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 12829#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 12830#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 12542#L937 assume !(start_simulation_~tmp~3 == 0); 12214#L937-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 12215#L442-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 12255#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 12163#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 12164#L892 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 12416#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 12424#L900 start_simulation_#t~ret16 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 12516#L950 assume !(start_simulation_~tmp___0~1 != 0); 11910#L918-3 [2018-11-10 05:51:06,819 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:06,819 INFO L82 PathProgramCache]: Analyzing trace with hash 1077898564, now seen corresponding path program 1 times [2018-11-10 05:51:06,819 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:06,819 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:06,820 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:06,820 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:06,820 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:06,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:06,866 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:51:06,866 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:51:06,866 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 05:51:06,866 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 05:51:06,867 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:06,867 INFO L82 PathProgramCache]: Analyzing trace with hash -1144346695, now seen corresponding path program 1 times [2018-11-10 05:51:06,867 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:06,867 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:06,867 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:06,868 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:06,868 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:06,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:06,903 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:51:06,903 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:51:06,903 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 05:51:06,903 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 05:51:06,904 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 05:51:06,904 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 05:51:06,904 INFO L87 Difference]: Start difference. First operand 1781 states and 2573 transitions. cyclomatic complexity: 794 Second operand 3 states. [2018-11-10 05:51:06,963 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:51:06,964 INFO L93 Difference]: Finished difference Result 3281 states and 4711 transitions. [2018-11-10 05:51:06,965 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 05:51:06,965 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3281 states and 4711 transitions. [2018-11-10 05:51:06,982 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3188 [2018-11-10 05:51:06,995 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3281 states to 3281 states and 4711 transitions. [2018-11-10 05:51:06,995 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3281 [2018-11-10 05:51:06,998 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3281 [2018-11-10 05:51:06,998 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3281 states and 4711 transitions. [2018-11-10 05:51:07,003 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 05:51:07,003 INFO L705 BuchiCegarLoop]: Abstraction has 3281 states and 4711 transitions. [2018-11-10 05:51:07,006 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3281 states and 4711 transitions. [2018-11-10 05:51:07,048 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3281 to 3269. [2018-11-10 05:51:07,048 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3269 states. [2018-11-10 05:51:07,055 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3269 states to 3269 states and 4699 transitions. [2018-11-10 05:51:07,055 INFO L728 BuchiCegarLoop]: Abstraction has 3269 states and 4699 transitions. [2018-11-10 05:51:07,055 INFO L608 BuchiCegarLoop]: Abstraction has 3269 states and 4699 transitions. [2018-11-10 05:51:07,055 INFO L442 BuchiCegarLoop]: ======== Iteration 10============ [2018-11-10 05:51:07,055 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3269 states and 4699 transitions. [2018-11-10 05:51:07,068 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3176 [2018-11-10 05:51:07,068 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:51:07,068 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:51:07,069 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:07,069 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:07,069 INFO L793 eck$LassoCheckResult]: Stem: 17510#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 17430#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 17431#L881 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 17328#L397 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17329#L404 assume ~m_i~0 == 1;~m_st~0 := 0; 17656#L404-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 17235#L409-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 17236#L414-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 17332#L419-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 17163#L424-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 17164#L429-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17182#L589 assume !(~M_E~0 == 0); 17183#L589-2 assume !(~T1_E~0 == 0); 17192#L594-1 assume !(~T2_E~0 == 0); 16967#L599-1 assume !(~T3_E~0 == 0); 16968#L604-1 assume !(~T4_E~0 == 0); 17115#L609-1 assume !(~T5_E~0 == 0); 17116#L614-1 assume !(~E_M~0 == 0); 17403#L619-1 assume !(~E_1~0 == 0); 17404#L624-1 assume !(~E_2~0 == 0); 17251#L629-1 assume !(~E_3~0 == 0); 17252#L634-1 assume !(~E_4~0 == 0); 17338#L639-1 assume !(~E_5~0 == 0); 17178#L644-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 17179#L282 assume !(~m_pc~0 == 1); 17549#L282-2 is_master_triggered_~__retres1~0 := 0; 17551#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 17552#L294 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 17618#L733 assume !(activate_threads_~tmp~1 != 0); 17619#L733-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 17095#L301 assume !(~t1_pc~0 == 1); 17084#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 17052#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17053#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 17123#L741 assume !(activate_threads_~tmp___0~0 != 0); 17104#L741-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 17105#L320 assume !(~t2_pc~0 == 1); 17241#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 17312#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 17238#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 17239#L749 assume !(activate_threads_~tmp___1~0 != 0); 17505#L749-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 17492#L339 assume !(~t3_pc~0 == 1); 17434#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 17433#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 17463#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 17464#L757 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 17638#L757-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 17171#L358 assume !(~t4_pc~0 == 1); 17124#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 17125#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 17170#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 17197#L765 assume !(activate_threads_~tmp___3~0 != 0); 17198#L765-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 17199#L377 assume !(~t5_pc~0 == 1); 17101#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 17102#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 17096#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 17097#L773 assume !(activate_threads_~tmp___4~0 != 0); 17395#L773-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17396#L657 assume !(~M_E~0 == 1); 17679#L657-2 assume !(~T1_E~0 == 1); 17274#L662-1 assume !(~T2_E~0 == 1); 17275#L667-1 assume !(~T3_E~0 == 1); 17507#L672-1 assume !(~T4_E~0 == 1); 17176#L677-1 assume !(~T5_E~0 == 1); 17177#L682-1 assume !(~E_M~0 == 1); 16959#L687-1 assume ~E_1~0 == 1;~E_1~0 := 2; 16960#L692-1 assume !(~E_2~0 == 1); 17106#L697-1 assume !(~E_3~0 == 1); 17107#L702-1 assume !(~E_4~0 == 1); 17398#L707-1 assume !(~E_5~0 == 1); 17399#L712-1 assume { :end_inline_reset_delta_events } true; 17678#L918-3 [2018-11-10 05:51:07,069 INFO L795 eck$LassoCheckResult]: Loop: 17678#L918-3 assume true; 17005#L918-1 assume !false; 17006#L919 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 17378#L564 assume true; 17379#L484-1 assume !false; 17346#L485 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 17268#L442 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 17153#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 17265#L475 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 17215#L489 assume !(eval_~tmp~0 != 0); 17217#L579 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 18856#L397-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 18854#L589-3 assume !(~M_E~0 == 0); 18852#L589-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 18850#L594-3 assume !(~T2_E~0 == 0); 18848#L599-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 18846#L604-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 18844#L609-3 assume ~T5_E~0 == 0;~T5_E~0 := 1; 18842#L614-3 assume ~E_M~0 == 0;~E_M~0 := 1; 18840#L619-3 assume ~E_1~0 == 0;~E_1~0 := 1; 18838#L624-3 assume !(~E_2~0 == 0); 18836#L629-3 assume ~E_3~0 == 0;~E_3~0 := 1; 18834#L634-3 assume !(~E_4~0 == 0); 18832#L639-3 assume ~E_5~0 == 0;~E_5~0 := 1; 18830#L644-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 18828#L282-21 assume !(~m_pc~0 == 1); 18825#L282-23 is_master_triggered_~__retres1~0 := 0; 18822#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 18820#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 18818#L733-21 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 18816#L733-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 18814#L301-21 assume !(~t1_pc~0 == 1); 18812#L301-23 is_transmit1_triggered_~__retres1~1 := 0; 18810#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 18808#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 18806#L741-21 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 18804#L741-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 18801#L320-21 assume !(~t2_pc~0 == 1); 18798#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 18796#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 18794#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 18792#L749-21 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 18790#L749-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 18788#L339-21 assume ~t3_pc~0 == 1; 18785#L340-7 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 18782#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 18780#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 18778#L757-21 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 18776#L757-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 18774#L358-21 assume !(~t4_pc~0 == 1); 18772#L358-23 is_transmit4_triggered_~__retres1~4 := 0; 18770#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 18768#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 18766#L765-21 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 18764#L765-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 18762#L377-21 assume ~t5_pc~0 == 1; 18759#L378-7 assume ~E_5~0 == 1;is_transmit5_triggered_~__retres1~5 := 1; 18756#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 18754#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 18752#L773-21 assume !(activate_threads_~tmp___4~0 != 0); 18750#L773-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18738#L657-3 assume !(~M_E~0 == 1); 18733#L657-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 18734#L662-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 18727#L667-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 18728#L672-3 assume !(~T4_E~0 == 1); 18721#L677-3 assume ~T5_E~0 == 1;~T5_E~0 := 2; 18722#L682-3 assume ~E_M~0 == 1;~E_M~0 := 2; 16965#L687-3 assume ~E_1~0 == 1;~E_1~0 := 2; 16966#L692-3 assume !(~E_2~0 == 1); 19012#L697-3 assume ~E_3~0 == 1;~E_3~0 := 2; 19011#L702-3 assume ~E_4~0 == 1;~E_4~0 := 2; 17401#L707-3 assume ~E_5~0 == 1;~E_5~0 := 2; 17402#L712-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 17232#L442-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 17160#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 17266#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 17267#L937 assume !(start_simulation_~tmp~3 == 0); 17279#L937-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 18613#L442-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 17327#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 17233#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 17234#L892 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 18880#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 18879#L900 start_simulation_#t~ret16 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 18878#L950 assume !(start_simulation_~tmp___0~1 != 0); 17678#L918-3 [2018-11-10 05:51:07,070 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:07,070 INFO L82 PathProgramCache]: Analyzing trace with hash -979705467, now seen corresponding path program 1 times [2018-11-10 05:51:07,070 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:07,070 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:07,071 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:07,071 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:07,071 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:07,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:07,111 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:51:07,111 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:51:07,111 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 05:51:07,111 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 05:51:07,111 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:07,112 INFO L82 PathProgramCache]: Analyzing trace with hash -115814534, now seen corresponding path program 2 times [2018-11-10 05:51:07,112 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:07,112 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:07,112 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:07,113 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:07,113 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:07,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:07,155 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:51:07,155 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:51:07,156 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 05:51:07,156 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 05:51:07,156 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 05:51:07,156 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 05:51:07,156 INFO L87 Difference]: Start difference. First operand 3269 states and 4699 transitions. cyclomatic complexity: 1434 Second operand 3 states. [2018-11-10 05:51:07,200 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:51:07,200 INFO L93 Difference]: Finished difference Result 3269 states and 4649 transitions. [2018-11-10 05:51:07,201 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 05:51:07,202 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3269 states and 4649 transitions. [2018-11-10 05:51:07,215 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3176 [2018-11-10 05:51:07,229 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3269 states to 3269 states and 4649 transitions. [2018-11-10 05:51:07,230 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3269 [2018-11-10 05:51:07,233 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3269 [2018-11-10 05:51:07,233 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3269 states and 4649 transitions. [2018-11-10 05:51:07,239 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 05:51:07,239 INFO L705 BuchiCegarLoop]: Abstraction has 3269 states and 4649 transitions. [2018-11-10 05:51:07,242 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3269 states and 4649 transitions. [2018-11-10 05:51:07,279 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3269 to 3269. [2018-11-10 05:51:07,280 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3269 states. [2018-11-10 05:51:07,288 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3269 states to 3269 states and 4649 transitions. [2018-11-10 05:51:07,288 INFO L728 BuchiCegarLoop]: Abstraction has 3269 states and 4649 transitions. [2018-11-10 05:51:07,288 INFO L608 BuchiCegarLoop]: Abstraction has 3269 states and 4649 transitions. [2018-11-10 05:51:07,288 INFO L442 BuchiCegarLoop]: ======== Iteration 11============ [2018-11-10 05:51:07,288 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3269 states and 4649 transitions. [2018-11-10 05:51:07,299 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3176 [2018-11-10 05:51:07,299 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:51:07,299 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:51:07,300 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:07,300 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:07,300 INFO L793 eck$LassoCheckResult]: Stem: 24012#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 23950#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 23951#L881 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 23860#L397 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23861#L404 assume ~m_i~0 == 1;~m_st~0 := 0; 24125#L404-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 23768#L409-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 23769#L414-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 23862#L419-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 23702#L424-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 23703#L429-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23721#L589 assume !(~M_E~0 == 0); 23722#L589-2 assume !(~T1_E~0 == 0); 23732#L594-1 assume !(~T2_E~0 == 0); 23512#L599-1 assume !(~T3_E~0 == 0); 23513#L604-1 assume !(~T4_E~0 == 0); 23655#L609-1 assume !(~T5_E~0 == 0); 23656#L614-1 assume !(~E_M~0 == 0); 23927#L619-1 assume !(~E_1~0 == 0); 23928#L624-1 assume !(~E_2~0 == 0); 23784#L629-1 assume !(~E_3~0 == 0); 23785#L634-1 assume !(~E_4~0 == 0); 23869#L639-1 assume !(~E_5~0 == 0); 23717#L644-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 23718#L282 assume !(~m_pc~0 == 1); 24047#L282-2 is_master_triggered_~__retres1~0 := 0; 24049#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 24050#L294 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 24101#L733 assume !(activate_threads_~tmp~1 != 0); 24102#L733-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 23638#L301 assume !(~t1_pc~0 == 1); 23628#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 23594#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 23595#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 23662#L741 assume !(activate_threads_~tmp___0~0 != 0); 23646#L741-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 23647#L320 assume !(~t2_pc~0 == 1); 23774#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 23847#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 23771#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 23772#L749 assume !(activate_threads_~tmp___1~0 != 0); 24009#L749-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 24000#L339 assume !(~t3_pc~0 == 1); 23954#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 23953#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 23983#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 23984#L757 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 24115#L757-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 23710#L358 assume !(~t4_pc~0 == 1); 23663#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 23664#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 23707#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 23738#L765 assume !(activate_threads_~tmp___3~0 != 0); 23739#L765-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 23740#L377 assume !(~t5_pc~0 == 1); 23642#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 23643#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 23639#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 23640#L773 assume !(activate_threads_~tmp___4~0 != 0); 23919#L773-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23920#L657 assume !(~M_E~0 == 1); 24135#L657-2 assume !(~T1_E~0 == 1); 23809#L662-1 assume !(~T2_E~0 == 1); 23810#L667-1 assume !(~T3_E~0 == 1); 24010#L672-1 assume !(~T4_E~0 == 1); 23715#L677-1 assume !(~T5_E~0 == 1); 23716#L682-1 assume !(~E_M~0 == 1); 23504#L687-1 assume !(~E_1~0 == 1); 23505#L692-1 assume !(~E_2~0 == 1); 23648#L697-1 assume !(~E_3~0 == 1); 23649#L702-1 assume !(~E_4~0 == 1); 23921#L707-1 assume !(~E_5~0 == 1); 23922#L712-1 assume { :end_inline_reset_delta_events } true; 24134#L918-3 [2018-11-10 05:51:07,301 INFO L795 eck$LassoCheckResult]: Loop: 24134#L918-3 assume true; 25336#L918-1 assume !false; 25333#L919 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 25328#L564 assume true; 25326#L484-1 assume !false; 25323#L485 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 25318#L442 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 25312#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 25310#L475 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 25308#L489 assume !(eval_~tmp~0 != 0); 25309#L579 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 25517#L397-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 25515#L589-3 assume !(~M_E~0 == 0); 25513#L589-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 25511#L594-3 assume !(~T2_E~0 == 0); 25509#L599-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 25507#L604-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 25505#L609-3 assume ~T5_E~0 == 0;~T5_E~0 := 1; 25503#L614-3 assume ~E_M~0 == 0;~E_M~0 := 1; 25501#L619-3 assume !(~E_1~0 == 0); 25499#L624-3 assume !(~E_2~0 == 0); 25497#L629-3 assume ~E_3~0 == 0;~E_3~0 := 1; 25495#L634-3 assume !(~E_4~0 == 0); 25493#L639-3 assume ~E_5~0 == 0;~E_5~0 := 1; 25491#L644-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 25489#L282-21 assume !(~m_pc~0 == 1); 25486#L282-23 is_master_triggered_~__retres1~0 := 0; 25483#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 25481#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 25479#L733-21 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 25477#L733-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 25475#L301-21 assume !(~t1_pc~0 == 1); 25473#L301-23 is_transmit1_triggered_~__retres1~1 := 0; 25471#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 25469#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 25467#L741-21 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 25465#L741-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 25460#L320-21 assume !(~t2_pc~0 == 1); 25458#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 25456#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 25454#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 25452#L749-21 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 25450#L749-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 25448#L339-21 assume ~t3_pc~0 == 1; 25444#L340-7 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 25442#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 25440#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 25438#L757-21 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 25436#L757-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 25434#L358-21 assume !(~t4_pc~0 == 1); 25432#L358-23 is_transmit4_triggered_~__retres1~4 := 0; 25430#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 25428#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 25426#L765-21 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 25424#L765-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 25422#L377-21 assume ~t5_pc~0 == 1; 25418#L378-7 assume ~E_5~0 == 1;is_transmit5_triggered_~__retres1~5 := 1; 25416#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 25414#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 25412#L773-21 assume !(activate_threads_~tmp___4~0 != 0); 25410#L773-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25409#L657-3 assume !(~M_E~0 == 1); 25406#L657-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 25405#L662-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 25404#L667-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 25401#L672-3 assume !(~T4_E~0 == 1); 25399#L677-3 assume ~T5_E~0 == 1;~T5_E~0 := 2; 25397#L682-3 assume ~E_M~0 == 1;~E_M~0 := 2; 25395#L687-3 assume !(~E_1~0 == 1); 25393#L692-3 assume !(~E_2~0 == 1); 25390#L697-3 assume ~E_3~0 == 1;~E_3~0 := 2; 25388#L702-3 assume ~E_4~0 == 1;~E_4~0 := 2; 25386#L707-3 assume ~E_5~0 == 1;~E_5~0 := 2; 25384#L712-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 25375#L442-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 25371#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 25369#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 25366#L937 assume !(start_simulation_~tmp~3 == 0); 25363#L937-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 25354#L442-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 25349#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 25347#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 25345#L892 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 25343#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 25341#L900 start_simulation_#t~ret16 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 25339#L950 assume !(start_simulation_~tmp___0~1 != 0); 24134#L918-3 [2018-11-10 05:51:07,301 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:07,301 INFO L82 PathProgramCache]: Analyzing trace with hash -922447165, now seen corresponding path program 1 times [2018-11-10 05:51:07,301 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:07,301 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:07,314 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:07,314 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 05:51:07,314 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:07,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:07,390 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:51:07,390 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:51:07,390 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 05:51:07,390 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 05:51:07,390 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:07,391 INFO L82 PathProgramCache]: Analyzing trace with hash 968854330, now seen corresponding path program 1 times [2018-11-10 05:51:07,391 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:07,391 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:07,391 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:07,392 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:07,392 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:07,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:07,417 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:51:07,418 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:51:07,418 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 05:51:07,418 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 05:51:07,418 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 05:51:07,418 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 05:51:07,418 INFO L87 Difference]: Start difference. First operand 3269 states and 4649 transitions. cyclomatic complexity: 1384 Second operand 5 states. [2018-11-10 05:51:07,597 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:51:07,597 INFO L93 Difference]: Finished difference Result 8174 states and 11616 transitions. [2018-11-10 05:51:07,599 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-10 05:51:07,599 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8174 states and 11616 transitions. [2018-11-10 05:51:07,622 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7992 [2018-11-10 05:51:07,647 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8174 states to 8174 states and 11616 transitions. [2018-11-10 05:51:07,647 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8174 [2018-11-10 05:51:07,652 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8174 [2018-11-10 05:51:07,653 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8174 states and 11616 transitions. [2018-11-10 05:51:07,659 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 05:51:07,659 INFO L705 BuchiCegarLoop]: Abstraction has 8174 states and 11616 transitions. [2018-11-10 05:51:07,664 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8174 states and 11616 transitions. [2018-11-10 05:51:07,709 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8174 to 3428. [2018-11-10 05:51:07,709 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3428 states. [2018-11-10 05:51:07,714 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3428 states to 3428 states and 4808 transitions. [2018-11-10 05:51:07,714 INFO L728 BuchiCegarLoop]: Abstraction has 3428 states and 4808 transitions. [2018-11-10 05:51:07,714 INFO L608 BuchiCegarLoop]: Abstraction has 3428 states and 4808 transitions. [2018-11-10 05:51:07,715 INFO L442 BuchiCegarLoop]: ======== Iteration 12============ [2018-11-10 05:51:07,715 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3428 states and 4808 transitions. [2018-11-10 05:51:07,741 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3332 [2018-11-10 05:51:07,741 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:51:07,741 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:51:07,742 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:07,742 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:07,743 INFO L793 eck$LassoCheckResult]: Stem: 35524#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 35425#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 35426#L881 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 35330#L397 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 35331#L404 assume ~m_i~0 == 1;~m_st~0 := 0; 35644#L404-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 35232#L409-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 35233#L414-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 35333#L419-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 35161#L424-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 35162#L429-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35180#L589 assume !(~M_E~0 == 0); 35181#L589-2 assume !(~T1_E~0 == 0); 35190#L594-1 assume !(~T2_E~0 == 0); 34968#L599-1 assume !(~T3_E~0 == 0); 34969#L604-1 assume !(~T4_E~0 == 0); 35113#L609-1 assume !(~T5_E~0 == 0); 35114#L614-1 assume !(~E_M~0 == 0); 35398#L619-1 assume !(~E_1~0 == 0); 35399#L624-1 assume !(~E_2~0 == 0); 35248#L629-1 assume !(~E_3~0 == 0); 35249#L634-1 assume !(~E_4~0 == 0); 35338#L639-1 assume !(~E_5~0 == 0); 35176#L644-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 35177#L282 assume !(~m_pc~0 == 1); 35558#L282-2 is_master_triggered_~__retres1~0 := 0; 35562#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 35563#L294 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 35615#L733 assume !(activate_threads_~tmp~1 != 0); 35616#L733-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 35094#L301 assume !(~t1_pc~0 == 1); 35084#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 35051#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 35052#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 35120#L741 assume !(activate_threads_~tmp___0~0 != 0); 35103#L741-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 35104#L320 assume !(~t2_pc~0 == 1); 35238#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 35311#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 35235#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 35236#L749 assume !(activate_threads_~tmp___1~0 != 0); 35519#L749-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 35504#L339 assume !(~t3_pc~0 == 1); 35429#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 35502#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 35503#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 35637#L757 assume !(activate_threads_~tmp___2~0 != 0); 35629#L757-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 35169#L358 assume !(~t4_pc~0 == 1); 35121#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 35122#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 35168#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 35195#L765 assume !(activate_threads_~tmp___3~0 != 0); 35196#L765-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 35197#L377 assume !(~t5_pc~0 == 1); 35100#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 35101#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 35095#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 35096#L773 assume !(activate_threads_~tmp___4~0 != 0); 35390#L773-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35391#L657 assume !(~M_E~0 == 1); 35661#L657-2 assume !(~T1_E~0 == 1); 35269#L662-1 assume !(~T2_E~0 == 1); 35270#L667-1 assume !(~T3_E~0 == 1); 35522#L672-1 assume !(~T4_E~0 == 1); 35174#L677-1 assume !(~T5_E~0 == 1); 35175#L682-1 assume !(~E_M~0 == 1); 34960#L687-1 assume !(~E_1~0 == 1); 34961#L692-1 assume !(~E_2~0 == 1); 35105#L697-1 assume !(~E_3~0 == 1); 35106#L702-1 assume !(~E_4~0 == 1); 35393#L707-1 assume !(~E_5~0 == 1); 35394#L712-1 assume { :end_inline_reset_delta_events } true; 35660#L918-3 [2018-11-10 05:51:07,743 INFO L795 eck$LassoCheckResult]: Loop: 35660#L918-3 assume true; 37538#L918-1 assume !false; 37535#L919 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 37530#L564 assume true; 37528#L484-1 assume !false; 37505#L485 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 37466#L442 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 37458#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 37454#L475 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 37448#L489 assume !(eval_~tmp~0 != 0); 37449#L579 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 37654#L397-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 37653#L589-3 assume !(~M_E~0 == 0); 37652#L589-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 37651#L594-3 assume !(~T2_E~0 == 0); 37650#L599-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 37649#L604-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 37648#L609-3 assume ~T5_E~0 == 0;~T5_E~0 := 1; 37647#L614-3 assume ~E_M~0 == 0;~E_M~0 := 1; 37646#L619-3 assume !(~E_1~0 == 0); 37645#L624-3 assume !(~E_2~0 == 0); 37644#L629-3 assume ~E_3~0 == 0;~E_3~0 := 1; 37643#L634-3 assume !(~E_4~0 == 0); 37642#L639-3 assume ~E_5~0 == 0;~E_5~0 := 1; 35188#L644-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 35189#L282-21 assume ~m_pc~0 == 1; 35639#L283-7 assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 35540#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 35541#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 35550#L733-21 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 35551#L733-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 34986#L301-21 assume !(~t1_pc~0 == 1); 34987#L301-23 is_transmit1_triggered_~__retres1~1 := 0; 38318#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 38317#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 38316#L741-21 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 38315#L741-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 38313#L320-21 assume !(~t2_pc~0 == 1); 38312#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 38311#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 38310#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 38309#L749-21 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 38308#L749-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 35460#L339-21 assume ~t3_pc~0 == 1; 35417#L340-7 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 35418#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 38341#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 38340#L757-21 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 35473#L757-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 35474#L358-21 assume !(~t4_pc~0 == 1); 35617#L358-23 is_transmit4_triggered_~__retres1~4 := 0; 38335#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 38333#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 38330#L765-21 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 38328#L765-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 38327#L377-21 assume ~t5_pc~0 == 1; 38325#L378-7 assume ~E_5~0 == 1;is_transmit5_triggered_~__retres1~5 := 1; 38324#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 38323#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 38322#L773-21 assume !(activate_threads_~tmp___4~0 != 0); 38321#L773-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37047#L657-3 assume !(~M_E~0 == 1); 36893#L657-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 37046#L662-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 37044#L667-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 37042#L672-3 assume !(~T4_E~0 == 1); 37040#L677-3 assume ~T5_E~0 == 1;~T5_E~0 := 2; 37038#L682-3 assume ~E_M~0 == 1;~E_M~0 := 2; 37036#L687-3 assume !(~E_1~0 == 1); 37034#L692-3 assume !(~E_2~0 == 1); 37032#L697-3 assume ~E_3~0 == 1;~E_3~0 := 2; 37030#L702-3 assume ~E_4~0 == 1;~E_4~0 := 2; 37028#L707-3 assume ~E_5~0 == 1;~E_5~0 := 2; 37025#L712-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 37020#L442-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 35830#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 35831#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 35762#L937 assume !(start_simulation_~tmp~3 == 0); 35763#L937-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 37594#L442-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 37588#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 37585#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 37553#L892 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 37550#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 37547#L900 start_simulation_#t~ret16 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 37543#L950 assume !(start_simulation_~tmp___0~1 != 0); 35660#L918-3 [2018-11-10 05:51:07,743 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:07,743 INFO L82 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 1 times [2018-11-10 05:51:07,743 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:07,743 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:07,744 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:07,744 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:07,744 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:07,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:07,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:07,777 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:07,777 INFO L82 PathProgramCache]: Analyzing trace with hash -59677831, now seen corresponding path program 1 times [2018-11-10 05:51:07,777 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:07,777 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:07,778 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:07,778 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:07,778 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:07,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:07,798 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:51:07,798 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:51:07,798 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 05:51:07,798 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 05:51:07,798 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 05:51:07,798 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 05:51:07,799 INFO L87 Difference]: Start difference. First operand 3428 states and 4808 transitions. cyclomatic complexity: 1384 Second operand 3 states. [2018-11-10 05:51:07,844 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:51:07,844 INFO L93 Difference]: Finished difference Result 3940 states and 5525 transitions. [2018-11-10 05:51:07,845 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 05:51:07,845 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3940 states and 5525 transitions. [2018-11-10 05:51:07,854 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3788 [2018-11-10 05:51:07,866 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3940 states to 3940 states and 5525 transitions. [2018-11-10 05:51:07,866 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3940 [2018-11-10 05:51:07,868 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3940 [2018-11-10 05:51:07,868 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3940 states and 5525 transitions. [2018-11-10 05:51:07,871 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 05:51:07,871 INFO L705 BuchiCegarLoop]: Abstraction has 3940 states and 5525 transitions. [2018-11-10 05:51:07,874 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3940 states and 5525 transitions. [2018-11-10 05:51:07,905 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3940 to 3940. [2018-11-10 05:51:07,906 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3940 states. [2018-11-10 05:51:07,910 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3940 states to 3940 states and 5525 transitions. [2018-11-10 05:51:07,911 INFO L728 BuchiCegarLoop]: Abstraction has 3940 states and 5525 transitions. [2018-11-10 05:51:07,911 INFO L608 BuchiCegarLoop]: Abstraction has 3940 states and 5525 transitions. [2018-11-10 05:51:07,911 INFO L442 BuchiCegarLoop]: ======== Iteration 13============ [2018-11-10 05:51:07,911 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3940 states and 5525 transitions. [2018-11-10 05:51:07,918 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3788 [2018-11-10 05:51:07,918 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:51:07,918 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:51:07,920 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:07,920 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:07,920 INFO L793 eck$LassoCheckResult]: Stem: 42884#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 42807#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 42808#L881 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 42693#L397 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42694#L404 assume ~m_i~0 == 1;~m_st~0 := 0; 43000#L404-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 42605#L409-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 42606#L414-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 42696#L419-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 42531#L424-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 42532#L429-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 42550#L589 assume !(~M_E~0 == 0); 42551#L589-2 assume !(~T1_E~0 == 0); 42561#L594-1 assume !(~T2_E~0 == 0); 42342#L599-1 assume !(~T3_E~0 == 0); 42343#L604-1 assume ~T4_E~0 == 0;~T4_E~0 := 1; 42484#L609-1 assume !(~T5_E~0 == 0); 42485#L614-1 assume !(~E_M~0 == 0); 43068#L619-1 assume !(~E_1~0 == 0); 43013#L624-1 assume !(~E_2~0 == 0); 42621#L629-1 assume !(~E_3~0 == 0); 42622#L634-1 assume !(~E_4~0 == 0); 42702#L639-1 assume !(~E_5~0 == 0); 42546#L644-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 42547#L282 assume !(~m_pc~0 == 1); 42919#L282-2 is_master_triggered_~__retres1~0 := 0; 42923#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 42924#L294 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 43057#L733 assume !(activate_threads_~tmp~1 != 0); 43056#L733-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 42464#L301 assume !(~t1_pc~0 == 1); 42454#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 42421#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 42422#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 43050#L741 assume !(activate_threads_~tmp___0~0 != 0); 43049#L741-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 43048#L320 assume !(~t2_pc~0 == 1); 43046#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 43045#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 43044#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 43043#L749 assume !(activate_threads_~tmp___1~0 != 0); 43042#L749-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 43041#L339 assume !(~t3_pc~0 == 1); 43039#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 43037#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 43035#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 43030#L757 assume !(activate_threads_~tmp___2~0 != 0); 43029#L757-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 43028#L358 assume !(~t4_pc~0 == 1); 43027#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 43026#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 43023#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 42567#L765 assume !(activate_threads_~tmp___3~0 != 0); 42568#L765-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 42744#L377 assume !(~t5_pc~0 == 1); 42745#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 42740#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 42465#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 42466#L773 assume !(activate_threads_~tmp___4~0 != 0); 42768#L773-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42769#L657 assume !(~M_E~0 == 1); 43011#L657-2 assume !(~T1_E~0 == 1); 42645#L662-1 assume !(~T2_E~0 == 1); 42646#L667-1 assume !(~T3_E~0 == 1); 42881#L672-1 assume ~T4_E~0 == 1;~T4_E~0 := 2; 42544#L677-1 assume !(~T5_E~0 == 1); 42545#L682-1 assume !(~E_M~0 == 1); 42334#L687-1 assume !(~E_1~0 == 1); 42335#L692-1 assume !(~E_2~0 == 1); 42474#L697-1 assume !(~E_3~0 == 1); 42475#L702-1 assume !(~E_4~0 == 1); 42772#L707-1 assume !(~E_5~0 == 1); 42773#L712-1 assume { :end_inline_reset_delta_events } true; 42728#L918-3 [2018-11-10 05:51:07,920 INFO L795 eck$LassoCheckResult]: Loop: 42728#L918-3 assume true; 42376#L918-1 assume !false; 42377#L919 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 45005#L564 assume true; 42886#L484-1 assume !false; 42887#L485 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 42639#L442 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 42523#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 42636#L475 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 42588#L489 assume !(eval_~tmp~0 != 0); 42590#L579 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 44997#L397-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 44995#L589-3 assume !(~M_E~0 == 0); 44993#L589-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 44991#L594-3 assume !(~T2_E~0 == 0); 44989#L599-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 44986#L604-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 44983#L609-3 assume ~T5_E~0 == 0;~T5_E~0 := 1; 44981#L614-3 assume ~E_M~0 == 0;~E_M~0 := 1; 44979#L619-3 assume !(~E_1~0 == 0); 44977#L624-3 assume !(~E_2~0 == 0); 44975#L629-3 assume ~E_3~0 == 0;~E_3~0 := 1; 44973#L634-3 assume !(~E_4~0 == 0); 44971#L639-3 assume ~E_5~0 == 0;~E_5~0 := 1; 44969#L644-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 44967#L282-21 assume !(~m_pc~0 == 1); 44964#L282-23 is_master_triggered_~__retres1~0 := 0; 44961#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 44959#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 44957#L733-21 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 44955#L733-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 44953#L301-21 assume !(~t1_pc~0 == 1); 44951#L301-23 is_transmit1_triggered_~__retres1~1 := 0; 44949#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 44947#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 44945#L741-21 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 44943#L741-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 44940#L320-21 assume !(~t2_pc~0 == 1); 44937#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 44935#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 44933#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 44931#L749-21 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 44929#L749-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 44927#L339-21 assume ~t3_pc~0 == 1; 44924#L340-7 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 44920#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 44916#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 44912#L757-21 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 44909#L757-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 44907#L358-21 assume !(~t4_pc~0 == 1); 44905#L358-23 is_transmit4_triggered_~__retres1~4 := 0; 44903#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 44901#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 44899#L765-21 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 44897#L765-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 44895#L377-21 assume ~t5_pc~0 == 1; 44892#L378-7 assume ~E_5~0 == 1;is_transmit5_triggered_~__retres1~5 := 1; 44889#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 44887#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 44885#L773-21 assume !(activate_threads_~tmp___4~0 != 0); 44883#L773-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44881#L657-3 assume !(~M_E~0 == 1); 44880#L657-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 45210#L662-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 45209#L667-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 45208#L672-3 assume ~T4_E~0 == 1;~T4_E~0 := 2; 45206#L677-3 assume ~T5_E~0 == 1;~T5_E~0 := 2; 45205#L682-3 assume ~E_M~0 == 1;~E_M~0 := 2; 45204#L687-3 assume !(~E_1~0 == 1); 45203#L692-3 assume !(~E_2~0 == 1); 45202#L697-3 assume ~E_3~0 == 1;~E_3~0 := 2; 45201#L702-3 assume ~E_4~0 == 1;~E_4~0 := 2; 45200#L707-3 assume ~E_5~0 == 1;~E_5~0 := 2; 45199#L712-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 45195#L442-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 43864#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 43862#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 43860#L937 assume !(start_simulation_~tmp~3 == 0); 43859#L937-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 43773#L442-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 43769#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 43767#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 42882#L892 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 42883#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 43753#L900 start_simulation_#t~ret16 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 42727#L950 assume !(start_simulation_~tmp___0~1 != 0); 42728#L918-3 [2018-11-10 05:51:07,920 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:07,920 INFO L82 PathProgramCache]: Analyzing trace with hash -113006587, now seen corresponding path program 1 times [2018-11-10 05:51:07,921 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:07,921 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:07,921 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:07,921 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:07,921 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:07,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:07,948 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:51:07,948 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:51:07,948 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 05:51:07,948 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 05:51:07,948 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:07,948 INFO L82 PathProgramCache]: Analyzing trace with hash 546152504, now seen corresponding path program 1 times [2018-11-10 05:51:07,948 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:07,949 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:07,949 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:07,949 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:07,949 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:07,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:07,988 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:51:07,988 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:51:07,988 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 05:51:07,988 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 05:51:07,988 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 05:51:07,988 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 05:51:07,989 INFO L87 Difference]: Start difference. First operand 3940 states and 5525 transitions. cyclomatic complexity: 1589 Second operand 3 states. [2018-11-10 05:51:08,005 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:51:08,005 INFO L93 Difference]: Finished difference Result 3428 states and 4782 transitions. [2018-11-10 05:51:08,006 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 05:51:08,006 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3428 states and 4782 transitions. [2018-11-10 05:51:08,013 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3332 [2018-11-10 05:51:08,023 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3428 states to 3428 states and 4782 transitions. [2018-11-10 05:51:08,023 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3428 [2018-11-10 05:51:08,025 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3428 [2018-11-10 05:51:08,025 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3428 states and 4782 transitions. [2018-11-10 05:51:08,027 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 05:51:08,028 INFO L705 BuchiCegarLoop]: Abstraction has 3428 states and 4782 transitions. [2018-11-10 05:51:08,030 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3428 states and 4782 transitions. [2018-11-10 05:51:08,049 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3428 to 3428. [2018-11-10 05:51:08,049 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3428 states. [2018-11-10 05:51:08,054 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3428 states to 3428 states and 4782 transitions. [2018-11-10 05:51:08,054 INFO L728 BuchiCegarLoop]: Abstraction has 3428 states and 4782 transitions. [2018-11-10 05:51:08,054 INFO L608 BuchiCegarLoop]: Abstraction has 3428 states and 4782 transitions. [2018-11-10 05:51:08,054 INFO L442 BuchiCegarLoop]: ======== Iteration 14============ [2018-11-10 05:51:08,054 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3428 states and 4782 transitions. [2018-11-10 05:51:08,061 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3332 [2018-11-10 05:51:08,061 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:51:08,061 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:51:08,062 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:08,062 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:08,063 INFO L793 eck$LassoCheckResult]: Stem: 50240#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 50166#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 50167#L881 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 50067#L397 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50068#L404 assume ~m_i~0 == 1;~m_st~0 := 0; 50360#L404-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 49981#L409-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 49982#L414-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 50070#L419-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 49909#L424-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 49910#L429-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49930#L589 assume !(~M_E~0 == 0); 49931#L589-2 assume !(~T1_E~0 == 0); 49941#L594-1 assume !(~T2_E~0 == 0); 49719#L599-1 assume !(~T3_E~0 == 0); 49720#L604-1 assume !(~T4_E~0 == 0); 49861#L609-1 assume !(~T5_E~0 == 0); 49862#L614-1 assume !(~E_M~0 == 0); 50143#L619-1 assume !(~E_1~0 == 0); 50144#L624-1 assume !(~E_2~0 == 0); 49997#L629-1 assume !(~E_3~0 == 0); 49998#L634-1 assume !(~E_4~0 == 0); 50076#L639-1 assume !(~E_5~0 == 0); 49926#L644-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 49927#L282 assume !(~m_pc~0 == 1); 50275#L282-2 is_master_triggered_~__retres1~0 := 0; 50277#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 50278#L294 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 50329#L733 assume !(activate_threads_~tmp~1 != 0); 50330#L733-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 49842#L301 assume !(~t1_pc~0 == 1); 49831#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 49800#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 49801#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 49868#L741 assume !(activate_threads_~tmp___0~0 != 0); 49850#L741-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 49851#L320 assume !(~t2_pc~0 == 1); 49987#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 50055#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 49984#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 49985#L749 assume !(activate_threads_~tmp___1~0 != 0); 50236#L749-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 50224#L339 assume !(~t3_pc~0 == 1); 50170#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 50227#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 50378#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 50353#L757 assume !(activate_threads_~tmp___2~0 != 0); 50345#L757-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 49917#L358 assume !(~t4_pc~0 == 1); 49869#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 49870#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 49916#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 49948#L765 assume !(activate_threads_~tmp___3~0 != 0); 49949#L765-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 49950#L377 assume !(~t5_pc~0 == 1); 49846#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 49847#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 49843#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 49844#L773 assume !(activate_threads_~tmp___4~0 != 0); 50135#L773-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50136#L657 assume !(~M_E~0 == 1); 50376#L657-2 assume !(~T1_E~0 == 1); 50019#L662-1 assume !(~T2_E~0 == 1); 50020#L667-1 assume !(~T3_E~0 == 1); 50238#L672-1 assume !(~T4_E~0 == 1); 49924#L677-1 assume !(~T5_E~0 == 1); 49925#L682-1 assume !(~E_M~0 == 1); 49711#L687-1 assume !(~E_1~0 == 1); 49712#L692-1 assume !(~E_2~0 == 1); 49852#L697-1 assume !(~E_3~0 == 1); 49853#L702-1 assume !(~E_4~0 == 1); 50138#L707-1 assume !(~E_5~0 == 1); 50139#L712-1 assume { :end_inline_reset_delta_events } true; 50375#L918-3 [2018-11-10 05:51:08,063 INFO L795 eck$LassoCheckResult]: Loop: 50375#L918-3 assume true; 51541#L918-1 assume !false; 51533#L919 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 51524#L564 assume true; 51518#L484-1 assume !false; 51516#L485 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 51512#L442 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 51501#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 51499#L475 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 51497#L489 assume !(eval_~tmp~0 != 0); 51494#L579 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 51492#L397-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 51490#L589-3 assume !(~M_E~0 == 0); 51488#L589-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 51486#L594-3 assume !(~T2_E~0 == 0); 51484#L599-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 51482#L604-3 assume !(~T4_E~0 == 0); 51480#L609-3 assume ~T5_E~0 == 0;~T5_E~0 := 1; 51478#L614-3 assume ~E_M~0 == 0;~E_M~0 := 1; 51476#L619-3 assume !(~E_1~0 == 0); 51474#L624-3 assume !(~E_2~0 == 0); 51472#L629-3 assume ~E_3~0 == 0;~E_3~0 := 1; 51470#L634-3 assume !(~E_4~0 == 0); 51468#L639-3 assume ~E_5~0 == 0;~E_5~0 := 1; 51466#L644-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 51464#L282-21 assume !(~m_pc~0 == 1); 51461#L282-23 is_master_triggered_~__retres1~0 := 0; 51458#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 51456#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 51454#L733-21 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 51452#L733-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 51450#L301-21 assume !(~t1_pc~0 == 1); 51448#L301-23 is_transmit1_triggered_~__retres1~1 := 0; 51446#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 51444#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 51442#L741-21 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 51440#L741-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 51437#L320-21 assume !(~t2_pc~0 == 1); 51434#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 51432#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 51430#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 51428#L749-21 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 51426#L749-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 51424#L339-21 assume ~t3_pc~0 == 1; 51421#L340-7 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 51417#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 51413#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 51409#L757-21 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 51406#L757-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 51404#L358-21 assume !(~t4_pc~0 == 1); 51402#L358-23 is_transmit4_triggered_~__retres1~4 := 0; 51400#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 51398#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 51396#L765-21 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 51394#L765-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 51392#L377-21 assume ~t5_pc~0 == 1; 51389#L378-7 assume ~E_5~0 == 1;is_transmit5_triggered_~__retres1~5 := 1; 51386#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 51384#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 51382#L773-21 assume !(activate_threads_~tmp___4~0 != 0); 51380#L773-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51378#L657-3 assume !(~M_E~0 == 1); 51377#L657-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 51696#L662-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 51695#L667-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 51694#L672-3 assume !(~T4_E~0 == 1); 51693#L677-3 assume ~T5_E~0 == 1;~T5_E~0 := 2; 51692#L682-3 assume ~E_M~0 == 1;~E_M~0 := 2; 51691#L687-3 assume !(~E_1~0 == 1); 51690#L692-3 assume !(~E_2~0 == 1); 51689#L697-3 assume ~E_3~0 == 1;~E_3~0 := 2; 51688#L702-3 assume ~E_4~0 == 1;~E_4~0 := 2; 51687#L707-3 assume ~E_5~0 == 1;~E_5~0 := 2; 51686#L712-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 51681#L442-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 51677#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 51674#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 51672#L937 assume !(start_simulation_~tmp~3 == 0); 51669#L937-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 51652#L442-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 51648#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 51646#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 51644#L892 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 51642#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 51640#L900 start_simulation_#t~ret16 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 51556#L950 assume !(start_simulation_~tmp___0~1 != 0); 50375#L918-3 [2018-11-10 05:51:08,063 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:08,063 INFO L82 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 2 times [2018-11-10 05:51:08,063 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:08,063 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:08,064 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:08,064 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:08,064 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:08,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:08,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:08,086 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:08,086 INFO L82 PathProgramCache]: Analyzing trace with hash -1417655176, now seen corresponding path program 1 times [2018-11-10 05:51:08,086 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:08,086 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:08,087 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:08,087 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 05:51:08,087 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:08,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:08,126 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:51:08,126 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:51:08,126 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 05:51:08,126 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 05:51:08,127 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 05:51:08,127 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 05:51:08,127 INFO L87 Difference]: Start difference. First operand 3428 states and 4782 transitions. cyclomatic complexity: 1358 Second operand 5 states. [2018-11-10 05:51:08,199 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:51:08,200 INFO L93 Difference]: Finished difference Result 6160 states and 8482 transitions. [2018-11-10 05:51:08,201 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-10 05:51:08,201 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6160 states and 8482 transitions. [2018-11-10 05:51:08,215 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6048 [2018-11-10 05:51:08,225 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6160 states to 6160 states and 8482 transitions. [2018-11-10 05:51:08,225 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6160 [2018-11-10 05:51:08,228 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6160 [2018-11-10 05:51:08,228 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6160 states and 8482 transitions. [2018-11-10 05:51:08,233 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 05:51:08,233 INFO L705 BuchiCegarLoop]: Abstraction has 6160 states and 8482 transitions. [2018-11-10 05:51:08,237 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6160 states and 8482 transitions. [2018-11-10 05:51:08,263 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6160 to 3452. [2018-11-10 05:51:08,263 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3452 states. [2018-11-10 05:51:08,267 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3452 states to 3452 states and 4806 transitions. [2018-11-10 05:51:08,267 INFO L728 BuchiCegarLoop]: Abstraction has 3452 states and 4806 transitions. [2018-11-10 05:51:08,268 INFO L608 BuchiCegarLoop]: Abstraction has 3452 states and 4806 transitions. [2018-11-10 05:51:08,268 INFO L442 BuchiCegarLoop]: ======== Iteration 15============ [2018-11-10 05:51:08,268 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3452 states and 4806 transitions. [2018-11-10 05:51:08,276 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3356 [2018-11-10 05:51:08,276 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:51:08,276 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:51:08,277 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:08,277 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:08,278 INFO L793 eck$LassoCheckResult]: Stem: 59818#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 59749#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 59750#L881 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 59659#L397 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 59660#L404 assume ~m_i~0 == 1;~m_st~0 := 0; 59928#L404-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 59573#L409-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 59574#L414-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 59661#L419-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 59513#L424-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 59514#L429-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 59532#L589 assume !(~M_E~0 == 0); 59533#L589-2 assume !(~T1_E~0 == 0); 59542#L594-1 assume !(~T2_E~0 == 0); 59323#L599-1 assume !(~T3_E~0 == 0); 59324#L604-1 assume !(~T4_E~0 == 0); 59466#L609-1 assume !(~T5_E~0 == 0); 59467#L614-1 assume !(~E_M~0 == 0); 59728#L619-1 assume !(~E_1~0 == 0); 59729#L624-1 assume !(~E_2~0 == 0); 59589#L629-1 assume !(~E_3~0 == 0); 59590#L634-1 assume !(~E_4~0 == 0); 59668#L639-1 assume !(~E_5~0 == 0); 59528#L644-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 59529#L282 assume !(~m_pc~0 == 1); 59852#L282-2 is_master_triggered_~__retres1~0 := 0; 59854#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 59855#L294 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 59905#L733 assume !(activate_threads_~tmp~1 != 0); 59906#L733-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 59447#L301 assume !(~t1_pc~0 == 1); 59437#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 59402#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 59403#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 59473#L741 assume !(activate_threads_~tmp___0~0 != 0); 59457#L741-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 59458#L320 assume !(~t2_pc~0 == 1); 59579#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 59646#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 59576#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 59577#L749 assume !(activate_threads_~tmp___1~0 != 0); 59815#L749-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 59808#L339 assume !(~t3_pc~0 == 1); 59753#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 59806#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 59807#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 59923#L757 assume !(activate_threads_~tmp___2~0 != 0); 59918#L757-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 59521#L358 assume !(~t4_pc~0 == 1); 59474#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 59475#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 59518#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 59548#L765 assume !(activate_threads_~tmp___3~0 != 0); 59549#L765-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 59550#L377 assume !(~t5_pc~0 == 1); 59451#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 59452#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 59448#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 59449#L773 assume !(activate_threads_~tmp___4~0 != 0); 59720#L773-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59721#L657 assume !(~M_E~0 == 1); 59936#L657-2 assume !(~T1_E~0 == 1); 59612#L662-1 assume !(~T2_E~0 == 1); 59613#L667-1 assume !(~T3_E~0 == 1); 59816#L672-1 assume !(~T4_E~0 == 1); 59526#L677-1 assume !(~T5_E~0 == 1); 59527#L682-1 assume !(~E_M~0 == 1); 59315#L687-1 assume !(~E_1~0 == 1); 59316#L692-1 assume !(~E_2~0 == 1); 59459#L697-1 assume !(~E_3~0 == 1); 59460#L702-1 assume !(~E_4~0 == 1); 59722#L707-1 assume !(~E_5~0 == 1); 59723#L712-1 assume { :end_inline_reset_delta_events } true; 59335#L918-3 [2018-11-10 05:51:08,278 INFO L795 eck$LassoCheckResult]: Loop: 59335#L918-3 assume true; 59336#L918-1 assume !false; 59359#L919 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 59537#L564 assume true; 59704#L484-1 assume !false; 59676#L485 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 59604#L442 assume !(~m_st~0 == 0); 59502#L446 assume !(~t1_st~0 == 0); 59504#L450 assume !(~t2_st~0 == 0); 59713#L454 assume !(~t3_st~0 == 0); 59714#L458 assume !(~t4_st~0 == 0); 59819#L462 assume !(~t5_st~0 == 0);exists_runnable_thread_~__retres1~6 := 0; 59820#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 61285#L475 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 61286#L489 assume !(eval_~tmp~0 != 0); 59898#L579 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 59899#L397-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 59544#L589-3 assume !(~M_E~0 == 0); 59545#L589-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 62703#L594-3 assume !(~T2_E~0 == 0); 59559#L599-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 59560#L604-3 assume !(~T4_E~0 == 0); 59781#L609-3 assume ~T5_E~0 == 0;~T5_E~0 := 1; 59915#L614-3 assume ~E_M~0 == 0;~E_M~0 := 1; 59708#L619-3 assume !(~E_1~0 == 0); 59709#L624-3 assume !(~E_2~0 == 0); 59597#L629-3 assume ~E_3~0 == 0;~E_3~0 := 1; 59598#L634-3 assume !(~E_4~0 == 0); 59901#L639-3 assume ~E_5~0 == 0;~E_5~0 := 1; 59540#L644-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 59541#L282-21 assume ~m_pc~0 == 1; 59924#L283-7 assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 59835#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 59836#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 59929#L733-21 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 62684#L733-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 59341#L301-21 assume !(~t1_pc~0 == 1); 59342#L301-23 is_transmit1_triggered_~__retres1~1 := 0; 62683#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 62682#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 62681#L741-21 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 59344#L741-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 59345#L320-21 assume !(~t2_pc~0 == 1); 62679#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 59626#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 59627#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 59632#L749-21 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 59633#L749-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 62676#L339-21 assume ~t3_pc~0 == 1; 62674#L340-7 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 62669#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 62667#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 62665#L757-21 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 62663#L757-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 62661#L358-21 assume !(~t4_pc~0 == 1); 62660#L358-23 is_transmit4_triggered_~__retres1~4 := 0; 62658#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 62656#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 62654#L765-21 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 59914#L765-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 59454#L377-21 assume ~t5_pc~0 == 1; 59456#L378-7 assume ~E_5~0 == 1;is_transmit5_triggered_~__retres1~5 := 1; 62651#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 59368#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 59369#L773-21 assume !(activate_threads_~tmp___4~0 != 0); 59685#L773-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59686#L657-3 assume !(~M_E~0 == 1); 59932#L657-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 59593#L662-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 59594#L667-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 59671#L672-3 assume !(~T4_E~0 == 1); 59672#L677-3 assume ~T5_E~0 == 1;~T5_E~0 := 2; 59823#L682-3 assume ~E_M~0 == 1;~E_M~0 := 2; 59321#L687-3 assume !(~E_1~0 == 1); 59322#L692-3 assume !(~E_2~0 == 1); 59464#L697-3 assume ~E_3~0 == 1;~E_3~0 := 2; 59465#L702-3 assume ~E_4~0 == 1;~E_4~0 := 2; 59726#L707-3 assume ~E_5~0 == 1;~E_5~0 := 2; 59727#L712-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 59570#L442-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 59510#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 59605#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 59606#L937 assume !(start_simulation_~tmp~3 == 0); 59617#L937-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 59575#L442-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 59516#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 59571#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 59572#L892 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 59817#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 59827#L900 start_simulation_#t~ret16 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 59691#L950 assume !(start_simulation_~tmp___0~1 != 0); 59335#L918-3 [2018-11-10 05:51:08,278 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:08,278 INFO L82 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 3 times [2018-11-10 05:51:08,278 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:08,278 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:08,279 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:08,279 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:08,279 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:08,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:08,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:08,299 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:08,300 INFO L82 PathProgramCache]: Analyzing trace with hash 1919581108, now seen corresponding path program 1 times [2018-11-10 05:51:08,300 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:08,300 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:08,300 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:08,301 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 05:51:08,301 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:08,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:08,336 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:51:08,336 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:51:08,336 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 05:51:08,337 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 05:51:08,337 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 05:51:08,337 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 05:51:08,337 INFO L87 Difference]: Start difference. First operand 3452 states and 4806 transitions. cyclomatic complexity: 1358 Second operand 5 states. [2018-11-10 05:51:08,463 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:51:08,463 INFO L93 Difference]: Finished difference Result 6685 states and 9215 transitions. [2018-11-10 05:51:08,465 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-10 05:51:08,465 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6685 states and 9215 transitions. [2018-11-10 05:51:08,483 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6556 [2018-11-10 05:51:08,497 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6685 states to 6685 states and 9215 transitions. [2018-11-10 05:51:08,497 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6685 [2018-11-10 05:51:08,500 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6685 [2018-11-10 05:51:08,500 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6685 states and 9215 transitions. [2018-11-10 05:51:08,505 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 05:51:08,505 INFO L705 BuchiCegarLoop]: Abstraction has 6685 states and 9215 transitions. [2018-11-10 05:51:08,509 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6685 states and 9215 transitions. [2018-11-10 05:51:08,542 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6685 to 3611. [2018-11-10 05:51:08,542 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3611 states. [2018-11-10 05:51:08,547 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3611 states to 3611 states and 4965 transitions. [2018-11-10 05:51:08,547 INFO L728 BuchiCegarLoop]: Abstraction has 3611 states and 4965 transitions. [2018-11-10 05:51:08,547 INFO L608 BuchiCegarLoop]: Abstraction has 3611 states and 4965 transitions. [2018-11-10 05:51:08,547 INFO L442 BuchiCegarLoop]: ======== Iteration 16============ [2018-11-10 05:51:08,547 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3611 states and 4965 transitions. [2018-11-10 05:51:08,555 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3512 [2018-11-10 05:51:08,555 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:51:08,555 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:51:08,557 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:08,557 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:08,557 INFO L793 eck$LassoCheckResult]: Stem: 69999#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 69928#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 69929#L881 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 69820#L397 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 69821#L404 assume ~m_i~0 == 1;~m_st~0 := 0; 70122#L404-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 69736#L409-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 69737#L414-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 69823#L419-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 69671#L424-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 69672#L429-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 69690#L589 assume !(~M_E~0 == 0); 69691#L589-2 assume !(~T1_E~0 == 0); 69700#L594-1 assume !(~T2_E~0 == 0); 69474#L599-1 assume !(~T3_E~0 == 0); 69475#L604-1 assume !(~T4_E~0 == 0); 69618#L609-1 assume !(~T5_E~0 == 0); 69619#L614-1 assume !(~E_M~0 == 0); 69904#L619-1 assume !(~E_1~0 == 0); 69905#L624-1 assume !(~E_2~0 == 0); 69751#L629-1 assume !(~E_3~0 == 0); 69752#L634-1 assume !(~E_4~0 == 0); 69828#L639-1 assume !(~E_5~0 == 0); 69686#L644-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 69687#L282 assume !(~m_pc~0 == 1); 70035#L282-2 is_master_triggered_~__retres1~0 := 0; 70039#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 70040#L294 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 70088#L733 assume !(activate_threads_~tmp~1 != 0); 70089#L733-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 69599#L301 assume !(~t1_pc~0 == 1); 69590#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 69557#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 69558#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 69630#L741 assume !(activate_threads_~tmp___0~0 != 0); 69607#L741-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 69608#L320 assume !(~t2_pc~0 == 1); 69741#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 69809#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 69738#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 69739#L749 assume !(activate_threads_~tmp___1~0 != 0); 69995#L749-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 69982#L339 assume !(~t3_pc~0 == 1); 69932#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 69987#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 70139#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 70116#L757 assume !(activate_threads_~tmp___2~0 != 0); 70108#L757-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 69679#L358 assume !(~t4_pc~0 == 1); 69631#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 69632#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 69678#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 69705#L765 assume !(activate_threads_~tmp___3~0 != 0); 69706#L765-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 69707#L377 assume !(~t5_pc~0 == 1); 69604#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 69869#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 69870#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 70140#L773 assume !(activate_threads_~tmp___4~0 != 0); 69895#L773-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69896#L657 assume !(~M_E~0 == 1); 70137#L657-2 assume !(~T1_E~0 == 1); 69774#L662-1 assume !(~T2_E~0 == 1); 69775#L667-1 assume !(~T3_E~0 == 1); 69997#L672-1 assume !(~T4_E~0 == 1); 69684#L677-1 assume !(~T5_E~0 == 1); 69685#L682-1 assume !(~E_M~0 == 1); 69466#L687-1 assume !(~E_1~0 == 1); 69467#L692-1 assume !(~E_2~0 == 1); 69609#L697-1 assume !(~E_3~0 == 1); 69610#L702-1 assume !(~E_4~0 == 1); 69899#L707-1 assume !(~E_5~0 == 1); 69900#L712-1 assume { :end_inline_reset_delta_events } true; 70134#L918-3 [2018-11-10 05:51:08,557 INFO L795 eck$LassoCheckResult]: Loop: 70134#L918-3 assume true; 72704#L918-1 assume !false; 72702#L919 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 72698#L564 assume true; 72697#L484-1 assume !false; 72696#L485 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 72694#L442 assume !(~m_st~0 == 0); 72695#L446 assume !(~t1_st~0 == 0); 72689#L450 assume !(~t2_st~0 == 0); 72690#L454 assume !(~t3_st~0 == 0); 72693#L458 assume !(~t4_st~0 == 0); 72691#L462 assume !(~t5_st~0 == 0);exists_runnable_thread_~__retres1~6 := 0; 72692#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 72864#L475 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 72863#L489 assume !(eval_~tmp~0 != 0); 72862#L579 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 72842#L397-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 72784#L589-3 assume !(~M_E~0 == 0); 72780#L589-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 72777#L594-3 assume !(~T2_E~0 == 0); 72776#L599-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 72774#L604-3 assume !(~T4_E~0 == 0); 72772#L609-3 assume ~T5_E~0 == 0;~T5_E~0 := 1; 72770#L614-3 assume ~E_M~0 == 0;~E_M~0 := 1; 72768#L619-3 assume !(~E_1~0 == 0); 72765#L624-3 assume !(~E_2~0 == 0); 69760#L629-3 assume ~E_3~0 == 0;~E_3~0 := 1; 69761#L634-3 assume !(~E_4~0 == 0); 69833#L639-3 assume ~E_5~0 == 0;~E_5~0 := 1; 69698#L644-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 69699#L282-21 assume ~m_pc~0 == 1; 70117#L283-7 assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 70016#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 70017#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 70022#L733-21 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 70023#L733-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 72973#L301-21 assume !(~t1_pc~0 == 1); 72972#L301-23 is_transmit1_triggered_~__retres1~1 := 0; 72971#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 72970#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 72969#L741-21 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 72968#L741-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 72966#L320-21 assume !(~t2_pc~0 == 1); 72965#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 72957#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 72955#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 72954#L749-21 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 72953#L749-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 72952#L339-21 assume ~t3_pc~0 == 1; 72951#L340-7 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 72949#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 72947#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 72944#L757-21 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 72943#L757-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 72942#L358-21 assume !(~t4_pc~0 == 1); 72941#L358-23 is_transmit4_triggered_~__retres1~4 := 0; 72940#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 72939#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 72938#L765-21 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 72937#L765-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 72936#L377-21 assume ~t5_pc~0 == 1; 72935#L378-7 assume ~E_5~0 == 1;is_transmit5_triggered_~__retres1~5 := 1; 72933#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 72931#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 72929#L773-21 assume activate_threads_~tmp___4~0 != 0;~t5_st~0 := 0; 72926#L773-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 72925#L657-3 assume !(~M_E~0 == 1); 72922#L657-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 72921#L662-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 72920#L667-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 72919#L672-3 assume !(~T4_E~0 == 1); 72918#L677-3 assume ~T5_E~0 == 1;~T5_E~0 := 2; 72917#L682-3 assume ~E_M~0 == 1;~E_M~0 := 2; 72916#L687-3 assume !(~E_1~0 == 1); 72915#L692-3 assume !(~E_2~0 == 1); 72913#L697-3 assume ~E_3~0 == 1;~E_3~0 := 2; 72911#L702-3 assume ~E_4~0 == 1;~E_4~0 := 2; 72909#L707-3 assume ~E_5~0 == 1;~E_5~0 := 2; 72907#L712-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 72898#L442-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 72894#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 72893#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 72892#L937 assume !(start_simulation_~tmp~3 == 0); 72890#L937-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 72731#L442-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 72727#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 72725#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 72715#L892 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 72712#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 72710#L900 start_simulation_#t~ret16 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 72707#L950 assume !(start_simulation_~tmp___0~1 != 0); 70134#L918-3 [2018-11-10 05:51:08,557 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:08,558 INFO L82 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 4 times [2018-11-10 05:51:08,558 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:08,558 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:08,558 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:08,558 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:08,559 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:08,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:08,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:08,580 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:08,581 INFO L82 PathProgramCache]: Analyzing trace with hash -3646926, now seen corresponding path program 1 times [2018-11-10 05:51:08,581 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:08,581 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:08,581 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:08,582 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 05:51:08,582 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:08,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:08,646 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:51:08,646 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:51:08,646 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 05:51:08,646 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 05:51:08,646 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 05:51:08,647 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 05:51:08,647 INFO L87 Difference]: Start difference. First operand 3611 states and 4965 transitions. cyclomatic complexity: 1358 Second operand 5 states. [2018-11-10 05:51:08,751 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:51:08,752 INFO L93 Difference]: Finished difference Result 4741 states and 6516 transitions. [2018-11-10 05:51:08,753 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-10 05:51:08,753 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4741 states and 6516 transitions. [2018-11-10 05:51:08,764 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4634 [2018-11-10 05:51:08,772 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4741 states to 4741 states and 6516 transitions. [2018-11-10 05:51:08,772 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4741 [2018-11-10 05:51:08,775 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4741 [2018-11-10 05:51:08,775 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4741 states and 6516 transitions. [2018-11-10 05:51:08,778 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 05:51:08,778 INFO L705 BuchiCegarLoop]: Abstraction has 4741 states and 6516 transitions. [2018-11-10 05:51:08,781 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4741 states and 6516 transitions. [2018-11-10 05:51:08,809 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4741 to 3623. [2018-11-10 05:51:08,809 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3623 states. [2018-11-10 05:51:08,815 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3623 states to 3623 states and 4928 transitions. [2018-11-10 05:51:08,816 INFO L728 BuchiCegarLoop]: Abstraction has 3623 states and 4928 transitions. [2018-11-10 05:51:08,816 INFO L608 BuchiCegarLoop]: Abstraction has 3623 states and 4928 transitions. [2018-11-10 05:51:08,816 INFO L442 BuchiCegarLoop]: ======== Iteration 17============ [2018-11-10 05:51:08,816 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3623 states and 4928 transitions. [2018-11-10 05:51:08,825 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3524 [2018-11-10 05:51:08,825 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:51:08,825 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:51:08,826 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:08,826 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:08,827 INFO L793 eck$LassoCheckResult]: Stem: 78404#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 78316#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 78317#L881 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 78208#L397 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 78209#L404 assume ~m_i~0 == 1;~m_st~0 := 0; 78532#L404-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 78114#L409-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 78115#L414-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 78211#L419-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 78039#L424-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 78040#L429-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 78058#L589 assume !(~M_E~0 == 0); 78059#L589-2 assume !(~T1_E~0 == 0); 78068#L594-1 assume !(~T2_E~0 == 0); 77840#L599-1 assume !(~T3_E~0 == 0); 77841#L604-1 assume !(~T4_E~0 == 0); 77991#L609-1 assume !(~T5_E~0 == 0); 77992#L614-1 assume !(~E_M~0 == 0); 78285#L619-1 assume !(~E_1~0 == 0); 78286#L624-1 assume !(~E_2~0 == 0); 78129#L629-1 assume !(~E_3~0 == 0); 78130#L634-1 assume !(~E_4~0 == 0); 78217#L639-1 assume !(~E_5~0 == 0); 78054#L644-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 78055#L282 assume !(~m_pc~0 == 1); 78441#L282-2 is_master_triggered_~__retres1~0 := 0; 78445#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 78446#L294 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 78498#L733 assume !(activate_threads_~tmp~1 != 0); 78499#L733-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 77970#L301 assume !(~t1_pc~0 == 1); 77961#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 77927#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 77928#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 78000#L741 assume !(activate_threads_~tmp___0~0 != 0); 77978#L741-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 77979#L320 assume !(~t2_pc~0 == 1); 78119#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 78195#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 78116#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 78117#L749 assume !(activate_threads_~tmp___1~0 != 0); 78401#L749-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 78391#L339 assume !(~t3_pc~0 == 1); 78320#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 78389#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 78390#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 78526#L757 assume !(activate_threads_~tmp___2~0 != 0); 78516#L757-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 78047#L358 assume !(~t4_pc~0 == 1); 78001#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 78002#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 78046#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 78073#L765 assume !(activate_threads_~tmp___3~0 != 0); 78074#L765-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 78075#L377 assume !(~t5_pc~0 == 1); 77975#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 78258#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 78547#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 78546#L773 assume !(activate_threads_~tmp___4~0 != 0); 78276#L773-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 78277#L657 assume !(~M_E~0 == 1); 78544#L657-2 assume !(~T1_E~0 == 1); 78154#L662-1 assume !(~T2_E~0 == 1); 78155#L667-1 assume !(~T3_E~0 == 1); 78402#L672-1 assume !(~T4_E~0 == 1); 78052#L677-1 assume !(~T5_E~0 == 1); 78053#L682-1 assume !(~E_M~0 == 1); 77832#L687-1 assume !(~E_1~0 == 1); 77833#L692-1 assume !(~E_2~0 == 1); 77980#L697-1 assume !(~E_3~0 == 1); 77981#L702-1 assume !(~E_4~0 == 1); 78280#L707-1 assume !(~E_5~0 == 1); 78281#L712-1 assume { :end_inline_reset_delta_events } true; 78540#L918-3 [2018-11-10 05:51:08,827 INFO L795 eck$LassoCheckResult]: Loop: 78540#L918-3 assume true; 78997#L918-1 assume !false; 78990#L919 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 78981#L564 assume true; 78979#L484-1 assume !false; 78977#L485 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 78975#L442 assume !(~m_st~0 == 0); 78973#L446 assume !(~t1_st~0 == 0); 78971#L450 assume !(~t2_st~0 == 0); 78969#L454 assume !(~t3_st~0 == 0); 78967#L458 assume !(~t4_st~0 == 0); 78964#L462 assume !(~t5_st~0 == 0);exists_runnable_thread_~__retres1~6 := 0; 78961#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 78959#L475 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 78956#L489 assume !(eval_~tmp~0 != 0); 78953#L579 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 78951#L397-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 78949#L589-3 assume !(~M_E~0 == 0); 78947#L589-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 78945#L594-3 assume !(~T2_E~0 == 0); 78943#L599-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 78941#L604-3 assume !(~T4_E~0 == 0); 78939#L609-3 assume ~T5_E~0 == 0;~T5_E~0 := 1; 78937#L614-3 assume ~E_M~0 == 0;~E_M~0 := 1; 78935#L619-3 assume !(~E_1~0 == 0); 78933#L624-3 assume !(~E_2~0 == 0); 78931#L629-3 assume ~E_3~0 == 0;~E_3~0 := 1; 78929#L634-3 assume !(~E_4~0 == 0); 78927#L639-3 assume ~E_5~0 == 0;~E_5~0 := 1; 78925#L644-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 78923#L282-21 assume ~m_pc~0 == 1; 78921#L283-7 assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 78917#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 78915#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 78913#L733-21 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 78911#L733-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 78909#L301-21 assume !(~t1_pc~0 == 1); 78907#L301-23 is_transmit1_triggered_~__retres1~1 := 0; 78905#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 78903#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 78901#L741-21 assume !(activate_threads_~tmp___0~0 != 0); 78899#L741-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 78896#L320-21 assume !(~t2_pc~0 == 1); 78893#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 78891#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 78889#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 78887#L749-21 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 78885#L749-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 78883#L339-21 assume !(~t3_pc~0 == 1); 78881#L339-23 is_transmit3_triggered_~__retres1~3 := 0; 78877#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 78873#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 78869#L757-21 assume !(activate_threads_~tmp___2~0 != 0); 78865#L757-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 78863#L358-21 assume !(~t4_pc~0 == 1); 78861#L358-23 is_transmit4_triggered_~__retres1~4 := 0; 78859#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 78857#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 78855#L765-21 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 78853#L765-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 78851#L377-21 assume ~t5_pc~0 == 1; 78849#L378-7 assume ~E_5~0 == 1;is_transmit5_triggered_~__retres1~5 := 1; 78845#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 78841#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 78837#L773-21 assume activate_threads_~tmp___4~0 != 0;~t5_st~0 := 0; 78833#L773-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 78831#L657-3 assume !(~M_E~0 == 1); 78830#L657-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 79352#L662-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 79351#L667-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 79350#L672-3 assume !(~T4_E~0 == 1); 79349#L677-3 assume ~T5_E~0 == 1;~T5_E~0 := 2; 79348#L682-3 assume ~E_M~0 == 1;~E_M~0 := 2; 79347#L687-3 assume !(~E_1~0 == 1); 79346#L692-3 assume !(~E_2~0 == 1); 79345#L697-3 assume ~E_3~0 == 1;~E_3~0 := 2; 78687#L702-3 assume ~E_4~0 == 1;~E_4~0 := 2; 78684#L707-3 assume ~E_5~0 == 1;~E_5~0 := 2; 78677#L712-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 78678#L442-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 78662#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 78663#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 78656#L937 assume !(start_simulation_~tmp~3 == 0); 78657#L937-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 79376#L442-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 79050#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 79045#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 79041#L892 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 79039#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 79037#L900 start_simulation_#t~ret16 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 79035#L950 assume !(start_simulation_~tmp___0~1 != 0); 78540#L918-3 [2018-11-10 05:51:08,827 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:08,827 INFO L82 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 5 times [2018-11-10 05:51:08,828 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:08,828 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:08,828 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:08,828 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:08,828 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:08,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:08,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:08,854 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:08,854 INFO L82 PathProgramCache]: Analyzing trace with hash -1979069897, now seen corresponding path program 1 times [2018-11-10 05:51:08,854 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:08,854 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:08,855 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:08,855 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 05:51:08,855 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:08,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:08,920 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:51:08,920 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:51:08,920 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 05:51:08,920 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 05:51:08,921 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 05:51:08,921 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 05:51:08,921 INFO L87 Difference]: Start difference. First operand 3623 states and 4928 transitions. cyclomatic complexity: 1309 Second operand 5 states. [2018-11-10 05:51:09,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:51:09,017 INFO L93 Difference]: Finished difference Result 4883 states and 6627 transitions. [2018-11-10 05:51:09,018 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-10 05:51:09,018 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4883 states and 6627 transitions. [2018-11-10 05:51:09,031 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4776 [2018-11-10 05:51:09,041 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4883 states to 4883 states and 6627 transitions. [2018-11-10 05:51:09,041 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4883 [2018-11-10 05:51:09,044 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4883 [2018-11-10 05:51:09,044 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4883 states and 6627 transitions. [2018-11-10 05:51:09,047 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 05:51:09,047 INFO L705 BuchiCegarLoop]: Abstraction has 4883 states and 6627 transitions. [2018-11-10 05:51:09,085 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4883 states and 6627 transitions. [2018-11-10 05:51:09,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4883 to 3635. [2018-11-10 05:51:09,110 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3635 states. [2018-11-10 05:51:09,114 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3635 states to 3635 states and 4891 transitions. [2018-11-10 05:51:09,115 INFO L728 BuchiCegarLoop]: Abstraction has 3635 states and 4891 transitions. [2018-11-10 05:51:09,115 INFO L608 BuchiCegarLoop]: Abstraction has 3635 states and 4891 transitions. [2018-11-10 05:51:09,115 INFO L442 BuchiCegarLoop]: ======== Iteration 18============ [2018-11-10 05:51:09,115 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3635 states and 4891 transitions. [2018-11-10 05:51:09,122 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3536 [2018-11-10 05:51:09,122 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:51:09,122 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:51:09,123 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:09,123 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:09,124 INFO L793 eck$LassoCheckResult]: Stem: 86902#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 86821#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 86822#L881 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 86716#L397 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 86717#L404 assume ~m_i~0 == 1;~m_st~0 := 0; 87030#L404-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 86626#L409-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 86627#L414-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 86720#L419-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 86561#L424-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 86562#L429-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 86580#L589 assume !(~M_E~0 == 0); 86581#L589-2 assume !(~T1_E~0 == 0); 86590#L594-1 assume !(~T2_E~0 == 0); 86361#L599-1 assume !(~T3_E~0 == 0); 86362#L604-1 assume !(~T4_E~0 == 0); 86510#L609-1 assume !(~T5_E~0 == 0); 86511#L614-1 assume !(~E_M~0 == 0); 86794#L619-1 assume !(~E_1~0 == 0); 86795#L624-1 assume !(~E_2~0 == 0); 86641#L629-1 assume !(~E_3~0 == 0); 86642#L634-1 assume !(~E_4~0 == 0); 86725#L639-1 assume !(~E_5~0 == 0); 86576#L644-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 86577#L282 assume !(~m_pc~0 == 1); 86939#L282-2 is_master_triggered_~__retres1~0 := 0; 86943#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 86944#L294 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 86993#L733 assume !(activate_threads_~tmp~1 != 0); 86994#L733-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 86487#L301 assume !(~t1_pc~0 == 1); 86479#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 86443#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 86444#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 86520#L741 assume !(activate_threads_~tmp___0~0 != 0); 86498#L741-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 86499#L320 assume !(~t2_pc~0 == 1); 86631#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 86704#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 86628#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 86629#L749 assume !(activate_threads_~tmp___1~0 != 0); 86898#L749-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 86889#L339 assume !(~t3_pc~0 == 1); 86825#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 86887#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 86888#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 87025#L757 assume !(activate_threads_~tmp___2~0 != 0); 87014#L757-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 86569#L358 assume !(~t4_pc~0 == 1); 86521#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 86522#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 86568#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 86595#L765 assume !(activate_threads_~tmp___3~0 != 0); 86596#L765-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 86597#L377 assume !(~t5_pc~0 == 1); 86493#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 86767#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 87044#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 87043#L773 assume !(activate_threads_~tmp___4~0 != 0); 86786#L773-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 86787#L657 assume !(~M_E~0 == 1); 87042#L657-2 assume !(~T1_E~0 == 1); 86664#L662-1 assume !(~T2_E~0 == 1); 86665#L667-1 assume !(~T3_E~0 == 1); 86899#L672-1 assume !(~T4_E~0 == 1); 86574#L677-1 assume !(~T5_E~0 == 1); 86575#L682-1 assume !(~E_M~0 == 1); 86352#L687-1 assume !(~E_1~0 == 1); 86353#L692-1 assume !(~E_2~0 == 1); 86500#L697-1 assume !(~E_3~0 == 1); 86501#L702-1 assume !(~E_4~0 == 1); 86789#L707-1 assume !(~E_5~0 == 1); 86790#L712-1 assume { :end_inline_reset_delta_events } true; 87038#L918-3 [2018-11-10 05:51:09,124 INFO L795 eck$LassoCheckResult]: Loop: 87038#L918-3 assume true; 87594#L918-1 assume !false; 87586#L919 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 87577#L564 assume true; 87575#L484-1 assume !false; 87573#L485 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 87571#L442 assume !(~m_st~0 == 0); 87569#L446 assume !(~t1_st~0 == 0); 87567#L450 assume !(~t2_st~0 == 0); 87565#L454 assume !(~t3_st~0 == 0); 87563#L458 assume !(~t4_st~0 == 0); 87560#L462 assume !(~t5_st~0 == 0);exists_runnable_thread_~__retres1~6 := 0; 87557#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 87555#L475 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 87552#L489 assume !(eval_~tmp~0 != 0); 87549#L579 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 87547#L397-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 87545#L589-3 assume !(~M_E~0 == 0); 87543#L589-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 87541#L594-3 assume !(~T2_E~0 == 0); 87539#L599-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 87537#L604-3 assume !(~T4_E~0 == 0); 87535#L609-3 assume ~T5_E~0 == 0;~T5_E~0 := 1; 87533#L614-3 assume ~E_M~0 == 0;~E_M~0 := 1; 87531#L619-3 assume !(~E_1~0 == 0); 87529#L624-3 assume !(~E_2~0 == 0); 87527#L629-3 assume ~E_3~0 == 0;~E_3~0 := 1; 87525#L634-3 assume !(~E_4~0 == 0); 87523#L639-3 assume ~E_5~0 == 0;~E_5~0 := 1; 87521#L644-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 87519#L282-21 assume ~m_pc~0 == 1; 87517#L283-7 assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 87513#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 87511#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 87509#L733-21 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 87507#L733-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 87505#L301-21 assume !(~t1_pc~0 == 1); 87503#L301-23 is_transmit1_triggered_~__retres1~1 := 0; 87501#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 87499#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 87497#L741-21 assume !(activate_threads_~tmp___0~0 != 0); 87495#L741-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 87492#L320-21 assume !(~t2_pc~0 == 1); 87489#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 87487#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 87485#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 87483#L749-21 assume !(activate_threads_~tmp___1~0 != 0); 87481#L749-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 87479#L339-21 assume !(~t3_pc~0 == 1); 87477#L339-23 is_transmit3_triggered_~__retres1~3 := 0; 87473#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 87469#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 87465#L757-21 assume !(activate_threads_~tmp___2~0 != 0); 87461#L757-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 87459#L358-21 assume !(~t4_pc~0 == 1); 87457#L358-23 is_transmit4_triggered_~__retres1~4 := 0; 87455#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 87453#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 87451#L765-21 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 87449#L765-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 87447#L377-21 assume ~t5_pc~0 == 1; 87445#L378-7 assume ~E_5~0 == 1;is_transmit5_triggered_~__retres1~5 := 1; 87441#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 87437#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 87433#L773-21 assume activate_threads_~tmp___4~0 != 0;~t5_st~0 := 0; 87429#L773-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 87427#L657-3 assume !(~M_E~0 == 1); 87422#L657-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 87401#L662-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 87395#L667-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 87228#L672-3 assume !(~T4_E~0 == 1); 87225#L677-3 assume ~T5_E~0 == 1;~T5_E~0 := 2; 87222#L682-3 assume ~E_M~0 == 1;~E_M~0 := 2; 87219#L687-3 assume !(~E_1~0 == 1); 87216#L692-3 assume !(~E_2~0 == 1); 87213#L697-3 assume ~E_3~0 == 1;~E_3~0 := 2; 87210#L702-3 assume ~E_4~0 == 1;~E_4~0 := 2; 87207#L707-3 assume ~E_5~0 == 1;~E_5~0 := 2; 87204#L712-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 87192#L442-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 87189#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 87158#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 87147#L937 assume !(start_simulation_~tmp~3 == 0); 87148#L937-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 87937#L442-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 87864#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 87860#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 87858#L892 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 87856#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 87854#L900 start_simulation_#t~ret16 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 87643#L950 assume !(start_simulation_~tmp___0~1 != 0); 87038#L918-3 [2018-11-10 05:51:09,124 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:09,124 INFO L82 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 6 times [2018-11-10 05:51:09,124 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:09,125 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:09,125 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:09,125 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:09,125 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:09,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:09,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:09,153 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:09,153 INFO L82 PathProgramCache]: Analyzing trace with hash -1085583559, now seen corresponding path program 1 times [2018-11-10 05:51:09,153 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:09,153 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:09,154 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:09,154 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 05:51:09,154 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:09,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:09,208 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:51:09,208 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:51:09,209 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 05:51:09,209 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 05:51:09,209 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 05:51:09,209 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 05:51:09,209 INFO L87 Difference]: Start difference. First operand 3635 states and 4891 transitions. cyclomatic complexity: 1260 Second operand 5 states. [2018-11-10 05:51:09,346 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:51:09,346 INFO L93 Difference]: Finished difference Result 6306 states and 8484 transitions. [2018-11-10 05:51:09,347 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-10 05:51:09,347 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6306 states and 8484 transitions. [2018-11-10 05:51:09,362 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6199 [2018-11-10 05:51:09,374 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6306 states to 6306 states and 8484 transitions. [2018-11-10 05:51:09,374 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6306 [2018-11-10 05:51:09,377 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6306 [2018-11-10 05:51:09,377 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6306 states and 8484 transitions. [2018-11-10 05:51:09,381 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 05:51:09,381 INFO L705 BuchiCegarLoop]: Abstraction has 6306 states and 8484 transitions. [2018-11-10 05:51:09,386 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6306 states and 8484 transitions. [2018-11-10 05:51:09,415 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6306 to 3719. [2018-11-10 05:51:09,415 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3719 states. [2018-11-10 05:51:09,420 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3719 states to 3719 states and 4950 transitions. [2018-11-10 05:51:09,421 INFO L728 BuchiCegarLoop]: Abstraction has 3719 states and 4950 transitions. [2018-11-10 05:51:09,421 INFO L608 BuchiCegarLoop]: Abstraction has 3719 states and 4950 transitions. [2018-11-10 05:51:09,421 INFO L442 BuchiCegarLoop]: ======== Iteration 19============ [2018-11-10 05:51:09,421 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3719 states and 4950 transitions. [2018-11-10 05:51:09,429 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3620 [2018-11-10 05:51:09,429 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:51:09,429 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:51:09,430 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:09,430 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:09,430 INFO L793 eck$LassoCheckResult]: Stem: 96908#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 96812#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 96813#L881 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 96706#L397 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 96707#L404 assume ~m_i~0 == 1;~m_st~0 := 0; 97070#L404-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 96605#L409-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 96606#L414-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 96708#L419-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 96524#L424-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 96525#L429-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 96544#L589 assume !(~M_E~0 == 0); 96545#L589-2 assume !(~T1_E~0 == 0); 96554#L594-1 assume !(~T2_E~0 == 0); 96315#L599-1 assume !(~T3_E~0 == 0); 96316#L604-1 assume !(~T4_E~0 == 0); 96471#L609-1 assume !(~T5_E~0 == 0); 96472#L614-1 assume !(~E_M~0 == 0); 96784#L619-1 assume !(~E_1~0 == 0); 96785#L624-1 assume !(~E_2~0 == 0); 96621#L629-1 assume !(~E_3~0 == 0); 96622#L634-1 assume !(~E_4~0 == 0); 96718#L639-1 assume !(~E_5~0 == 0); 96540#L644-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 96541#L282 assume !(~m_pc~0 == 1); 96948#L282-2 is_master_triggered_~__retres1~0 := 0; 96950#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 96951#L294 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 97024#L733 assume !(activate_threads_~tmp~1 != 0); 97025#L733-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 96450#L301 assume !(~t1_pc~0 == 1); 96439#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 96402#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 96403#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 96482#L741 assume !(activate_threads_~tmp___0~0 != 0); 96459#L741-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 96460#L320 assume !(~t2_pc~0 == 1); 96611#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 96688#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 96608#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 96609#L749 assume !(activate_threads_~tmp___1~0 != 0); 96903#L749-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 96888#L339 assume !(~t3_pc~0 == 1); 96816#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 96886#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 96887#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 97063#L757 assume !(activate_threads_~tmp___2~0 != 0); 97056#L757-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 96532#L358 assume !(~t4_pc~0 == 1); 96484#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 96485#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 96529#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 96560#L765 assume !(activate_threads_~tmp___3~0 != 0); 96561#L765-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 96562#L377 assume !(~t5_pc~0 == 1); 96454#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 96758#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 97091#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 97090#L773 assume !(activate_threads_~tmp___4~0 != 0); 96776#L773-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 96777#L657 assume !(~M_E~0 == 1); 97087#L657-2 assume !(~T1_E~0 == 1); 96647#L662-1 assume !(~T2_E~0 == 1); 96648#L667-1 assume !(~T3_E~0 == 1); 96906#L672-1 assume !(~T4_E~0 == 1); 96538#L677-1 assume !(~T5_E~0 == 1); 96539#L682-1 assume !(~E_M~0 == 1); 96307#L687-1 assume !(~E_1~0 == 1); 96308#L692-1 assume !(~E_2~0 == 1); 96461#L697-1 assume !(~E_3~0 == 1); 96462#L702-1 assume !(~E_4~0 == 1); 96778#L707-1 assume !(~E_5~0 == 1); 96779#L712-1 assume { :end_inline_reset_delta_events } true; 97086#L918-3 [2018-11-10 05:51:09,431 INFO L795 eck$LassoCheckResult]: Loop: 97086#L918-3 assume true; 98440#L918-1 assume !false; 98437#L919 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 98395#L564 assume true; 98428#L484-1 assume !false; 98424#L485 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 98422#L442 assume !(~m_st~0 == 0); 98423#L446 assume !(~t1_st~0 == 0); 98417#L450 assume !(~t2_st~0 == 0); 98418#L454 assume !(~t3_st~0 == 0); 98421#L458 assume !(~t4_st~0 == 0); 98419#L462 assume !(~t5_st~0 == 0);exists_runnable_thread_~__retres1~6 := 0; 98420#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 97892#L475 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 97893#L489 assume !(eval_~tmp~0 != 0); 99269#L579 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 99268#L397-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 99267#L589-3 assume !(~M_E~0 == 0); 99266#L589-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 99265#L594-3 assume !(~T2_E~0 == 0); 99264#L599-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 99263#L604-3 assume !(~T4_E~0 == 0); 99262#L609-3 assume ~T5_E~0 == 0;~T5_E~0 := 1; 99261#L614-3 assume ~E_M~0 == 0;~E_M~0 := 1; 99260#L619-3 assume !(~E_1~0 == 0); 99259#L624-3 assume !(~E_2~0 == 0); 99258#L629-3 assume ~E_3~0 == 0;~E_3~0 := 1; 99257#L634-3 assume !(~E_4~0 == 0); 99256#L639-3 assume ~E_5~0 == 0;~E_5~0 := 1; 99255#L644-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 99254#L282-21 assume ~m_pc~0 == 1; 99253#L283-7 assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 99251#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 99250#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 99249#L733-21 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 99248#L733-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 96333#L301-21 assume !(~t1_pc~0 == 1); 96334#L301-23 is_transmit1_triggered_~__retres1~1 := 0; 99408#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 99407#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 99406#L741-21 assume !(activate_threads_~tmp___0~0 != 0); 99405#L741-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 99403#L320-21 assume !(~t2_pc~0 == 1); 99402#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 99401#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 99400#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 99399#L749-21 assume !(activate_threads_~tmp___1~0 != 0); 99398#L749-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 99397#L339-21 assume ~t3_pc~0 == 1; 99395#L340-7 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 99393#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 99391#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 99389#L757-21 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 96858#L757-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 96859#L358-21 assume !(~t4_pc~0 == 1); 97027#L358-23 is_transmit4_triggered_~__retres1~4 := 0; 97983#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 97978#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 97973#L765-21 assume !(activate_threads_~tmp___3~0 != 0); 97969#L765-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 97965#L377-21 assume ~t5_pc~0 == 1; 97961#L378-7 assume ~E_5~0 == 1;is_transmit5_triggered_~__retres1~5 := 1; 97955#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 97949#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 97942#L773-21 assume activate_threads_~tmp___4~0 != 0;~t5_st~0 := 0; 97935#L773-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 97926#L657-3 assume !(~M_E~0 == 1); 97925#L657-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 97281#L662-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 97282#L667-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 97270#L672-3 assume !(~T4_E~0 == 1); 97271#L677-3 assume ~T5_E~0 == 1;~T5_E~0 := 2; 97258#L682-3 assume ~E_M~0 == 1;~E_M~0 := 2; 97259#L687-3 assume !(~E_1~0 == 1); 97250#L692-3 assume !(~E_2~0 == 1); 97245#L697-3 assume ~E_3~0 == 1;~E_3~0 := 2; 97241#L702-3 assume ~E_4~0 == 1;~E_4~0 := 2; 97242#L707-3 assume ~E_5~0 == 1;~E_5~0 := 2; 97229#L712-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 97230#L442-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 97209#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 97210#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 97197#L937 assume !(start_simulation_~tmp~3 == 0); 97198#L937-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 98467#L442-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 98462#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 98459#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 98453#L892 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 98450#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 98447#L900 start_simulation_#t~ret16 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 98444#L950 assume !(start_simulation_~tmp___0~1 != 0); 97086#L918-3 [2018-11-10 05:51:09,431 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:09,431 INFO L82 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 7 times [2018-11-10 05:51:09,431 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:09,431 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:09,432 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:09,432 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:09,432 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:09,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:09,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:09,451 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:09,451 INFO L82 PathProgramCache]: Analyzing trace with hash -1211133256, now seen corresponding path program 1 times [2018-11-10 05:51:09,451 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:09,451 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:09,452 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:09,452 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:09,452 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:09,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:09,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:09,469 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:09,469 INFO L82 PathProgramCache]: Analyzing trace with hash 2004251636, now seen corresponding path program 1 times [2018-11-10 05:51:09,469 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:09,469 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:09,469 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:09,470 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:09,470 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:09,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:09,507 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:51:09,507 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:51:09,507 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 05:51:10,004 WARN L179 SmtUtils]: Spent 490.00 ms on a formula simplification. DAG size of input: 193 DAG size of output: 174 [2018-11-10 05:51:10,218 WARN L179 SmtUtils]: Spent 204.00 ms on a formula simplification that was a NOOP. DAG size: 150 [2018-11-10 05:51:10,228 INFO L214 LassoAnalysis]: Preferences: [2018-11-10 05:51:10,229 INFO L124 ssoRankerPreferences]: Compute integeral hull: false [2018-11-10 05:51:10,229 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true [2018-11-10 05:51:10,229 INFO L126 ssoRankerPreferences]: Term annotations enabled: false [2018-11-10 05:51:10,229 INFO L127 ssoRankerPreferences]: Use exernal solver: true [2018-11-10 05:51:10,229 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-10 05:51:10,229 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false [2018-11-10 05:51:10,229 INFO L130 ssoRankerPreferences]: Path of dumped script: [2018-11-10 05:51:10,230 INFO L131 ssoRankerPreferences]: Filename of dumped script: token_ring.05_true-unreach-call_false-termination.cil.c_Iteration19_Loop [2018-11-10 05:51:10,230 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank [2018-11-10 05:51:10,236 INFO L280 LassoAnalysis]: Starting lasso preprocessing... [2018-11-10 05:51:10,257 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,263 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,266 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,277 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,283 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,291 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,293 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,298 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,303 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,309 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,312 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,317 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,320 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,323 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,326 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,330 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,332 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,334 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,340 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,344 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,349 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,351 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,355 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,358 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,363 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,366 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,370 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,375 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,380 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,383 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,385 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,388 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,390 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,393 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,396 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,402 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,407 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,414 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,416 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,421 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,427 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,430 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,433 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,436 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,439 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,442 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,449 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,466 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,470 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,472 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,479 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,488 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,492 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,502 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,504 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,508 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,511 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:10,514 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,097 INFO L298 LassoAnalysis]: Preprocessing complete. [2018-11-10 05:51:11,098 INFO L410 LassoAnalysis]: Checking for nontermination... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3d1a558d-f364-4c06-b466-4401cb7b363c/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-10 05:51:11,108 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-10 05:51:11,108 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-10 05:51:11,122 INFO L443 LassoAnalysis]: Proved nontermination for one component. [2018-11-10 05:51:11,122 INFO L446 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~ret1=0} Honda state: {ULTIMATE.start_eval_#t~ret1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3d1a558d-f364-4c06-b466-4401cb7b363c/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-10 05:51:11,161 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-10 05:51:11,161 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-10 05:51:11,165 INFO L443 LassoAnalysis]: Proved nontermination for one component. [2018-11-10 05:51:11,166 INFO L446 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_#t~ret16=0} Honda state: {ULTIMATE.start_start_simulation_#t~ret16=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3d1a558d-f364-4c06-b466-4401cb7b363c/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-10 05:51:11,200 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-10 05:51:11,200 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-10 05:51:11,219 INFO L443 LassoAnalysis]: Proved nontermination for one component. [2018-11-10 05:51:11,219 INFO L446 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~__retres2~0=0, ULTIMATE.start_start_simulation_~tmp___0~1=0, ULTIMATE.start_stop_simulation_#res=0} Honda state: {ULTIMATE.start_stop_simulation_~__retres2~0=0, ULTIMATE.start_start_simulation_~tmp___0~1=0, ULTIMATE.start_stop_simulation_#res=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3d1a558d-f364-4c06-b466-4401cb7b363c/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-10 05:51:11,257 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-10 05:51:11,257 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-10 05:51:11,274 INFO L443 LassoAnalysis]: Proved nontermination for one component. [2018-11-10 05:51:11,275 INFO L446 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit3_triggered_#res=1, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=1, ULTIMATE.start_activate_threads_~tmp___2~0=1} Honda state: {ULTIMATE.start_is_transmit3_triggered_#res=1, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=1, ULTIMATE.start_activate_threads_~tmp___2~0=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3d1a558d-f364-4c06-b466-4401cb7b363c/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-10 05:51:11,307 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-10 05:51:11,308 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-10 05:51:11,311 INFO L443 LassoAnalysis]: Proved nontermination for one component. [2018-11-10 05:51:11,311 INFO L446 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_st~0=-8} Honda state: {~t4_st~0=-8} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3d1a558d-f364-4c06-b466-4401cb7b363c/bin-2019/uautomizer/z3 Starting monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-10 05:51:11,333 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-10 05:51:11,333 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-10 05:51:11,362 INFO L443 LassoAnalysis]: Proved nontermination for one component. [2018-11-10 05:51:11,362 INFO L446 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~m_pc~0=1} Honda state: {~m_pc~0=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3d1a558d-f364-4c06-b466-4401cb7b363c/bin-2019/uautomizer/z3 Starting monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-10 05:51:11,368 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-10 05:51:11,368 INFO L163 nArgumentSynthesizer]: Using integer mode. No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3d1a558d-f364-4c06-b466-4401cb7b363c/bin-2019/uautomizer/z3 Starting monitored process 9 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-10 05:51:11,403 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2018-11-10 05:51:11,404 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-10 05:51:11,414 INFO L450 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2018-11-10 05:51:11,440 INFO L214 LassoAnalysis]: Preferences: [2018-11-10 05:51:11,441 INFO L124 ssoRankerPreferences]: Compute integeral hull: false [2018-11-10 05:51:11,441 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true [2018-11-10 05:51:11,441 INFO L126 ssoRankerPreferences]: Term annotations enabled: false [2018-11-10 05:51:11,441 INFO L127 ssoRankerPreferences]: Use exernal solver: false [2018-11-10 05:51:11,441 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-10 05:51:11,441 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false [2018-11-10 05:51:11,441 INFO L130 ssoRankerPreferences]: Path of dumped script: [2018-11-10 05:51:11,441 INFO L131 ssoRankerPreferences]: Filename of dumped script: token_ring.05_true-unreach-call_false-termination.cil.c_Iteration19_Loop [2018-11-10 05:51:11,441 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank [2018-11-10 05:51:11,441 INFO L280 LassoAnalysis]: Starting lasso preprocessing... [2018-11-10 05:51:11,444 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,452 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,466 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,476 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,479 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,480 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,488 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,498 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,583 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,607 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,641 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,655 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,658 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,661 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,670 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,675 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,678 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,686 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,692 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,698 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,705 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,716 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,721 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,731 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,743 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,750 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,753 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,779 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,786 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,790 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,792 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,794 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,797 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,800 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,804 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,809 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,814 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,822 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,828 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,834 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,843 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,846 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,848 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,854 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,857 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,862 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,875 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,878 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,886 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,888 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,891 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,897 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,899 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,903 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,914 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,917 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,921 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:11,925 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:51:12,409 INFO L298 LassoAnalysis]: Preprocessing complete. [2018-11-10 05:51:12,413 INFO L496 LassoAnalysis]: Using template 'affine'. [2018-11-10 05:51:12,414 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-10 05:51:12,415 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-10 05:51:12,416 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-10 05:51:12,416 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-10 05:51:12,416 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-10 05:51:12,416 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-10 05:51:12,418 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-10 05:51:12,418 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-10 05:51:12,420 INFO L529 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-10 05:51:12,420 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-10 05:51:12,421 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-10 05:51:12,421 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-10 05:51:12,421 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-10 05:51:12,421 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-10 05:51:12,421 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-10 05:51:12,421 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-10 05:51:12,422 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-10 05:51:12,422 INFO L529 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-10 05:51:12,422 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-10 05:51:12,423 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-10 05:51:12,423 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-10 05:51:12,423 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-10 05:51:12,423 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-10 05:51:12,423 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-10 05:51:12,424 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-10 05:51:12,424 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-10 05:51:12,427 INFO L529 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-10 05:51:12,428 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-10 05:51:12,428 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-10 05:51:12,428 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-10 05:51:12,428 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-10 05:51:12,428 INFO L206 nArgumentSynthesizer]: 2 loop disjuncts [2018-11-10 05:51:12,429 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-10 05:51:12,429 INFO L402 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2018-11-10 05:51:12,429 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-10 05:51:12,430 INFO L529 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-10 05:51:12,430 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-10 05:51:12,430 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-10 05:51:12,430 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-10 05:51:12,430 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-10 05:51:12,431 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-10 05:51:12,431 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-10 05:51:12,431 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-10 05:51:12,431 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-10 05:51:12,432 INFO L529 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-10 05:51:12,432 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-10 05:51:12,433 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-10 05:51:12,433 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-10 05:51:12,433 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-10 05:51:12,433 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-10 05:51:12,433 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-10 05:51:12,433 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-10 05:51:12,434 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-10 05:51:12,443 INFO L421 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2018-11-10 05:51:12,445 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2018-11-10 05:51:12,445 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2018-11-10 05:51:12,447 INFO L437 nArgumentSynthesizer]: Simplifying supporting invariants... [2018-11-10 05:51:12,447 INFO L440 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2018-11-10 05:51:12,447 INFO L517 LassoAnalysis]: Proved termination. [2018-11-10 05:51:12,448 INFO L519 LassoAnalysis]: Termination argument consisting of: Ranking function f(~E_3~0) = -1*~E_3~0 + 1 Supporting invariants [] [2018-11-10 05:51:12,449 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2018-11-10 05:51:12,498 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:12,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:12,526 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 05:51:12,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:12,570 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 05:51:12,604 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:51:12,608 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2018-11-10 05:51:12,609 INFO L72 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 3719 states and 4950 transitions. cyclomatic complexity: 1235 Second operand 5 states. [2018-11-10 05:51:12,768 INFO L76 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 3719 states and 4950 transitions. cyclomatic complexity: 1235. Second operand 5 states. Result 10249 states and 13761 transitions. Complement of second has 5 states. [2018-11-10 05:51:12,769 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2018-11-10 05:51:12,770 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. [2018-11-10 05:51:12,771 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 716 transitions. [2018-11-10 05:51:12,772 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 716 transitions. Stem has 73 letters. Loop has 91 letters. [2018-11-10 05:51:12,775 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-10 05:51:12,775 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 716 transitions. Stem has 164 letters. Loop has 91 letters. [2018-11-10 05:51:12,776 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-10 05:51:12,776 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 716 transitions. Stem has 73 letters. Loop has 182 letters. [2018-11-10 05:51:12,778 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-10 05:51:12,778 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10249 states and 13761 transitions. [2018-11-10 05:51:12,814 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6836 [2018-11-10 05:51:12,836 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10249 states to 10241 states and 13753 transitions. [2018-11-10 05:51:12,836 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6960 [2018-11-10 05:51:12,843 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6985 [2018-11-10 05:51:12,843 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10241 states and 13753 transitions. [2018-11-10 05:51:12,843 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-10 05:51:12,843 INFO L705 BuchiCegarLoop]: Abstraction has 10241 states and 13753 transitions. [2018-11-10 05:51:12,849 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10241 states and 13753 transitions. [2018-11-10 05:51:12,929 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10241 to 10208. [2018-11-10 05:51:12,929 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10208 states. [2018-11-10 05:51:12,942 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10208 states to 10208 states and 13696 transitions. [2018-11-10 05:51:12,943 INFO L728 BuchiCegarLoop]: Abstraction has 10208 states and 13696 transitions. [2018-11-10 05:51:12,943 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 05:51:12,943 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 05:51:12,943 INFO L87 Difference]: Start difference. First operand 10208 states and 13696 transitions. Second operand 3 states. [2018-11-10 05:51:13,066 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:51:13,066 INFO L93 Difference]: Finished difference Result 19052 states and 25084 transitions. [2018-11-10 05:51:13,066 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 05:51:13,067 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19052 states and 25084 transitions. [2018-11-10 05:51:13,131 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 12824 [2018-11-10 05:51:13,178 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19052 states to 19052 states and 25084 transitions. [2018-11-10 05:51:13,178 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12972 [2018-11-10 05:51:13,186 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12972 [2018-11-10 05:51:13,187 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19052 states and 25084 transitions. [2018-11-10 05:51:13,189 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-10 05:51:13,189 INFO L705 BuchiCegarLoop]: Abstraction has 19052 states and 25084 transitions. [2018-11-10 05:51:13,199 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19052 states and 25084 transitions. [2018-11-10 05:51:13,430 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19052 to 17972. [2018-11-10 05:51:13,430 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17972 states. [2018-11-10 05:51:13,454 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17972 states to 17972 states and 23764 transitions. [2018-11-10 05:51:13,454 INFO L728 BuchiCegarLoop]: Abstraction has 17972 states and 23764 transitions. [2018-11-10 05:51:13,455 INFO L608 BuchiCegarLoop]: Abstraction has 17972 states and 23764 transitions. [2018-11-10 05:51:13,455 INFO L442 BuchiCegarLoop]: ======== Iteration 20============ [2018-11-10 05:51:13,455 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17972 states and 23764 transitions. [2018-11-10 05:51:13,496 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 12104 [2018-11-10 05:51:13,496 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:51:13,497 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:51:13,499 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:13,499 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:13,499 INFO L793 eck$LassoCheckResult]: Stem: 141033#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 140908#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 140909#L881 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 140704#L397 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 140705#L404 assume ~m_i~0 == 1;~m_st~0 := 0; 141278#L404-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 140541#L409-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 140542#L414-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 140707#L419-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 140413#L424-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 140414#L429-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 140446#L589 assume !(~M_E~0 == 0); 140447#L589-2 assume !(~T1_E~0 == 0); 140465#L594-1 assume !(~T2_E~0 == 0); 140064#L599-1 assume !(~T3_E~0 == 0); 140065#L604-1 assume !(~T4_E~0 == 0); 140323#L609-1 assume !(~T5_E~0 == 0); 140324#L614-1 assume !(~E_M~0 == 0); 140857#L619-1 assume !(~E_1~0 == 0); 140858#L624-1 assume !(~E_2~0 == 0); 140565#L629-1 assume !(~E_3~0 == 0); 140566#L634-1 assume !(~E_4~0 == 0); 140718#L639-1 assume !(~E_5~0 == 0); 140440#L644-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 140441#L282 assume !(~m_pc~0 == 1); 141101#L282-2 is_master_triggered_~__retres1~0 := 0; 141108#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 141109#L294 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 141215#L733 assume !(activate_threads_~tmp~1 != 0); 141216#L733-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 140292#L301 assume !(~t1_pc~0 == 1); 140278#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 140217#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 140218#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 140339#L741 assume !(activate_threads_~tmp___0~0 != 0); 140302#L741-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 140303#L320 assume !(~t2_pc~0 == 1); 140546#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 140684#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 140543#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 140544#L749 assume !(activate_threads_~tmp___1~0 != 0); 141029#L749-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 141013#L339 assume !(~t3_pc~0 == 1); 140912#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 141020#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 141296#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 141266#L757 assume !(activate_threads_~tmp___2~0 != 0); 141254#L757-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 140426#L358 assume !(~t4_pc~0 == 1); 140340#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 140341#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 140425#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 140476#L765 assume !(activate_threads_~tmp___3~0 != 0); 140477#L765-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 140478#L377 assume !(~t5_pc~0 == 1); 140298#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 140808#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 140293#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 140294#L773 assume !(activate_threads_~tmp___4~0 != 0); 140844#L773-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 140845#L657 assume !(~M_E~0 == 1); 141294#L657-2 assume !(~T1_E~0 == 1); 140611#L662-1 assume !(~T2_E~0 == 1); 140612#L667-1 assume !(~T3_E~0 == 1); 141030#L672-1 assume !(~T4_E~0 == 1); 140438#L677-1 assume !(~T5_E~0 == 1); 140439#L682-1 assume !(~E_M~0 == 1); 140050#L687-1 assume !(~E_1~0 == 1); 140051#L692-1 assume !(~E_2~0 == 1); 140304#L697-1 assume !(~E_3~0 == 1); 140305#L702-1 assume !(~E_4~0 == 1); 140849#L707-1 assume !(~E_5~0 == 1); 140850#L712-1 assume { :end_inline_reset_delta_events } true; 141293#L918-3 assume true; 143769#L918-1 [2018-11-10 05:51:13,500 INFO L795 eck$LassoCheckResult]: Loop: 143769#L918-1 assume !false; 149464#L919 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 149460#L564 assume true; 149459#L484-1 assume !false; 149458#L485 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 149457#L442 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 147792#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 149456#L475 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 149455#L489 assume eval_~tmp~0 != 0; 149454#L489-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 147276#L497 assume eval_~tmp_ndt_1~0 != 0;~m_st~0 := 1;assume { :begin_inline_master } true;havoc master_#t~nondet0; 149450#L58 assume ~m_pc~0 == 0; 149449#L83-1 assume true; 149448#L69 assume !false; 149447#L70 ~token~0 := master_#t~nondet0;havoc master_#t~nondet0;~local~0 := ~token~0;~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 149446#L282-3 assume !(~m_pc~0 == 1); 149444#L282-5 is_master_triggered_~__retres1~0 := 0; 149443#L293-1 is_master_triggered_#res := is_master_triggered_~__retres1~0; 149442#L294-1 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 149441#L733-3 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 149439#L733-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 149437#L301-3 assume !(~t1_pc~0 == 1); 149425#L301-5 is_transmit1_triggered_~__retres1~1 := 0; 149141#L312-1 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 148694#L313-1 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 148685#L741-3 assume !(activate_threads_~tmp___0~0 != 0); 148679#L741-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 148673#L320-3 assume !(~t2_pc~0 == 1); 148667#L320-5 is_transmit2_triggered_~__retres1~2 := 0; 147931#L331-1 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 147929#L332-1 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 147927#L749-3 assume !(activate_threads_~tmp___1~0 != 0); 147924#L749-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 147922#L339-3 assume ~t3_pc~0 == 1; 147920#L340-1 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 147921#L350-1 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 148056#L351-1 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 147907#L757-3 assume !(activate_threads_~tmp___2~0 != 0); 147903#L757-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 147901#L358-3 assume !(~t4_pc~0 == 1); 147899#L358-5 is_transmit4_triggered_~__retres1~4 := 0; 147896#L369-1 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 147894#L370-1 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 147892#L765-3 assume !(activate_threads_~tmp___3~0 != 0); 147890#L765-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 147888#L377-3 assume !(~t5_pc~0 == 1); 147886#L377-5 is_transmit5_triggered_~__retres1~5 := 0; 147909#L388-1 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 147580#L389-1 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 147500#L773-3 assume activate_threads_~tmp___4~0 != 0;~t5_st~0 := 0; 147461#L773-5 assume { :end_inline_activate_threads } true; 147278#L790 assume { :end_inline_immediate_notify } true;~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 147274#L91 assume { :end_inline_master } true; 147273#L494 assume !(~t1_st~0 == 0); 147272#L508 assume !(~t2_st~0 == 0); 147810#L522 assume !(~t3_st~0 == 0); 147802#L536 assume !(~t4_st~0 == 0); 147799#L550 assume !(~t5_st~0 == 0); 147795#L564 assume true; 147794#L484-1 assume !false; 147793#L485 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 147791#L442 assume !(~m_st~0 == 0); 147790#L446 assume !(~t1_st~0 == 0); 147785#L450 assume !(~t2_st~0 == 0); 147786#L454 assume !(~t3_st~0 == 0); 147789#L458 assume !(~t4_st~0 == 0); 147787#L462 assume !(~t5_st~0 == 0);exists_runnable_thread_~__retres1~6 := 0; 147788#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 147462#L475 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 147463#L489 assume !(eval_~tmp~0 != 0); 148626#L579 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 148622#L397-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 148619#L589-3 assume !(~M_E~0 == 0); 148614#L589-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 148610#L594-3 assume !(~T2_E~0 == 0); 148606#L599-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 148602#L604-3 assume !(~T4_E~0 == 0); 148598#L609-3 assume ~T5_E~0 == 0;~T5_E~0 := 1; 148597#L614-3 assume ~E_M~0 == 0;~E_M~0 := 1; 148593#L619-3 assume !(~E_1~0 == 0); 148587#L624-3 assume !(~E_2~0 == 0); 148581#L629-3 assume !(~E_3~0 == 0); 148576#L634-3 assume !(~E_4~0 == 0); 148570#L639-3 assume ~E_5~0 == 0;~E_5~0 := 1; 148561#L644-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 148554#L282-21 assume !(~m_pc~0 == 1); 148548#L282-23 is_master_triggered_~__retres1~0 := 0; 148540#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 148534#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 148354#L733-21 assume !(activate_threads_~tmp~1 != 0); 148338#L733-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 148329#L301-21 assume !(~t1_pc~0 == 1); 148322#L301-23 is_transmit1_triggered_~__retres1~1 := 0; 148315#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 148309#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 148303#L741-21 assume !(activate_threads_~tmp___0~0 != 0); 148262#L741-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 148252#L320-21 assume !(~t2_pc~0 == 1); 148244#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 148235#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 148229#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 148221#L749-21 assume !(activate_threads_~tmp___1~0 != 0); 148176#L749-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 148173#L339-21 assume ~t3_pc~0 == 1; 148171#L340-7 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 148172#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 148216#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 148161#L757-21 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 148147#L757-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 148138#L358-21 assume !(~t4_pc~0 == 1); 148129#L358-23 is_transmit4_triggered_~__retres1~4 := 0; 148125#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 148120#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 148115#L765-21 assume !(activate_threads_~tmp___3~0 != 0); 148109#L765-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 148104#L377-21 assume !(~t5_pc~0 == 1); 148098#L377-23 is_transmit5_triggered_~__retres1~5 := 0; 148091#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 148084#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 148077#L773-21 assume !(activate_threads_~tmp___4~0 != 0); 148071#L773-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 148044#L657-3 assume !(~M_E~0 == 1); 148037#L657-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 148033#L662-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 148027#L667-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 148021#L672-3 assume !(~T4_E~0 == 1); 148015#L677-3 assume ~T5_E~0 == 1;~T5_E~0 := 2; 148010#L682-3 assume ~E_M~0 == 1;~E_M~0 := 2; 148004#L687-3 assume !(~E_1~0 == 1); 147999#L692-3 assume !(~E_2~0 == 1); 147994#L697-3 assume !(~E_3~0 == 1); 147986#L702-3 assume ~E_4~0 == 1;~E_4~0 := 2; 147953#L707-3 assume ~E_5~0 == 1;~E_5~0 := 2; 147946#L712-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 147939#L442-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 147940#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 149528#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 149523#L937 assume !(start_simulation_~tmp~3 == 0); 149517#L937-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 149511#L442-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 147863#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 149503#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 149497#L892 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 149492#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 149486#L900 start_simulation_#t~ret16 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 149477#L950 assume !(start_simulation_~tmp___0~1 != 0); 149471#L918-3 assume true; 143769#L918-1 [2018-11-10 05:51:13,500 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:13,500 INFO L82 PathProgramCache]: Analyzing trace with hash 959436202, now seen corresponding path program 1 times [2018-11-10 05:51:13,501 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:13,501 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:13,501 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:13,502 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:13,502 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:13,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:13,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:13,533 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:13,533 INFO L82 PathProgramCache]: Analyzing trace with hash 2019982266, now seen corresponding path program 1 times [2018-11-10 05:51:13,533 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:13,533 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:13,534 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:13,534 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:13,534 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:13,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:13,580 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:51:13,580 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:51:13,580 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 05:51:13,581 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 05:51:13,581 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 05:51:13,581 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 05:51:13,581 INFO L87 Difference]: Start difference. First operand 17972 states and 23764 transitions. cyclomatic complexity: 5804 Second operand 5 states. [2018-11-10 05:51:13,808 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:51:13,808 INFO L93 Difference]: Finished difference Result 42727 states and 55947 transitions. [2018-11-10 05:51:13,810 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-10 05:51:13,810 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 42727 states and 55947 transitions. [2018-11-10 05:51:13,929 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 28748 [2018-11-10 05:51:14,015 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 42727 states to 42727 states and 55947 transitions. [2018-11-10 05:51:14,015 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29135 [2018-11-10 05:51:14,032 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29135 [2018-11-10 05:51:14,032 INFO L73 IsDeterministic]: Start isDeterministic. Operand 42727 states and 55947 transitions. [2018-11-10 05:51:14,032 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-10 05:51:14,032 INFO L705 BuchiCegarLoop]: Abstraction has 42727 states and 55947 transitions. [2018-11-10 05:51:14,053 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42727 states and 55947 transitions. [2018-11-10 05:51:14,225 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42727 to 18671. [2018-11-10 05:51:14,225 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18671 states. [2018-11-10 05:51:14,247 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18671 states to 18671 states and 24463 transitions. [2018-11-10 05:51:14,247 INFO L728 BuchiCegarLoop]: Abstraction has 18671 states and 24463 transitions. [2018-11-10 05:51:14,247 INFO L608 BuchiCegarLoop]: Abstraction has 18671 states and 24463 transitions. [2018-11-10 05:51:14,247 INFO L442 BuchiCegarLoop]: ======== Iteration 21============ [2018-11-10 05:51:14,247 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18671 states and 24463 transitions. [2018-11-10 05:51:14,281 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 12584 [2018-11-10 05:51:14,281 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:51:14,282 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:51:14,284 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:14,284 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:14,284 INFO L793 eck$LassoCheckResult]: Stem: 201704#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 201586#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 201587#L881 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 201410#L397 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 201411#L404 assume ~m_i~0 == 1;~m_st~0 := 0; 201965#L404-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 201244#L409-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 201245#L414-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 201412#L419-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 201126#L424-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 201127#L429-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 201156#L589 assume !(~M_E~0 == 0); 201157#L589-2 assume !(~T1_E~0 == 0); 201174#L594-1 assume !(~T2_E~0 == 0); 200776#L599-1 assume !(~T3_E~0 == 0); 200777#L604-1 assume !(~T4_E~0 == 0); 201037#L609-1 assume !(~T5_E~0 == 0); 201038#L614-1 assume !(~E_M~0 == 0); 201541#L619-1 assume !(~E_1~0 == 0); 201542#L624-1 assume !(~E_2~0 == 0); 201272#L629-1 assume !(~E_3~0 == 0); 201273#L634-1 assume !(~E_4~0 == 0); 201422#L639-1 assume !(~E_5~0 == 0); 201150#L644-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 201151#L282 assume !(~m_pc~0 == 1); 201775#L282-2 is_master_triggered_~__retres1~0 := 0; 201781#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 201782#L294 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 201896#L733 assume !(activate_threads_~tmp~1 != 0); 201897#L733-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 201009#L301 assume !(~t1_pc~0 == 1); 200996#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 200935#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 200936#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 201054#L741 assume !(activate_threads_~tmp___0~0 != 0); 201018#L741-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 201019#L320 assume !(~t2_pc~0 == 1); 201253#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 201392#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 201250#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 201251#L749 assume !(activate_threads_~tmp___1~0 != 0); 201700#L749-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 201684#L339 assume !(~t3_pc~0 == 1); 201590#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 201690#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 202036#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 201938#L757 assume !(activate_threads_~tmp___2~0 != 0); 201925#L757-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 201139#L358 assume !(~t4_pc~0 == 1); 201055#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 201056#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 201138#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 201183#L765 assume !(activate_threads_~tmp___3~0 != 0); 201184#L765-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 201185#L377 assume !(~t5_pc~0 == 1); 201013#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 201499#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 201010#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 201011#L773 assume !(activate_threads_~tmp___4~0 != 0); 201529#L773-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 201530#L657 assume !(~M_E~0 == 1); 202028#L657-2 assume !(~T1_E~0 == 1); 201320#L662-1 assume !(~T2_E~0 == 1); 201321#L667-1 assume !(~T3_E~0 == 1); 201701#L672-1 assume !(~T4_E~0 == 1); 201148#L677-1 assume !(~T5_E~0 == 1); 201149#L682-1 assume !(~E_M~0 == 1); 200762#L687-1 assume !(~E_1~0 == 1); 200763#L692-1 assume !(~E_2~0 == 1); 201020#L697-1 assume !(~E_3~0 == 1); 201021#L702-1 assume !(~E_4~0 == 1); 201533#L707-1 assume !(~E_5~0 == 1); 201534#L712-1 assume { :end_inline_reset_delta_events } true; 202027#L918-3 assume true; 200797#L918-1 [2018-11-10 05:51:14,284 INFO L795 eck$LassoCheckResult]: Loop: 200797#L918-1 assume !false; 200844#L919 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 201167#L564 assume true; 201500#L484-1 assume !false; 201436#L485 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 201437#L442 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 211754#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 211752#L475 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 211750#L489 assume eval_~tmp~0 != 0; 211748#L489-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 210140#L497 assume eval_~tmp_ndt_1~0 != 0;~m_st~0 := 1;assume { :begin_inline_master } true;havoc master_#t~nondet0; 211738#L58 assume ~m_pc~0 == 0; 211736#L83-1 assume true; 211733#L69 assume !false; 211503#L70 ~token~0 := master_#t~nondet0;havoc master_#t~nondet0;~local~0 := ~token~0;~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 211502#L282-3 assume !(~m_pc~0 == 1); 211501#L282-5 is_master_triggered_~__retres1~0 := 0; 211499#L293-1 is_master_triggered_#res := is_master_triggered_~__retres1~0; 211497#L294-1 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 211495#L733-3 assume !(activate_threads_~tmp~1 != 0); 211492#L733-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 211490#L301-3 assume !(~t1_pc~0 == 1); 211483#L301-5 is_transmit1_triggered_~__retres1~1 := 0; 211481#L312-1 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 211479#L313-1 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 211477#L741-3 assume !(activate_threads_~tmp___0~0 != 0); 211476#L741-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 211473#L320-3 assume !(~t2_pc~0 == 1); 211470#L320-5 is_transmit2_triggered_~__retres1~2 := 0; 211468#L331-1 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 211466#L332-1 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 211464#L749-3 assume !(activate_threads_~tmp___1~0 != 0); 211462#L749-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 211461#L339-3 assume ~t3_pc~0 == 1; 211459#L340-1 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 211457#L350-1 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 211441#L351-1 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 211426#L757-3 assume !(activate_threads_~tmp___2~0 != 0); 211414#L757-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 211410#L358-3 assume !(~t4_pc~0 == 1); 211408#L358-5 is_transmit4_triggered_~__retres1~4 := 0; 210168#L369-1 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 210167#L370-1 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 210165#L765-3 assume !(activate_threads_~tmp___3~0 != 0); 210161#L765-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 210159#L377-3 assume !(~t5_pc~0 == 1); 210155#L377-5 is_transmit5_triggered_~__retres1~5 := 0; 210154#L388-1 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 210152#L389-1 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 210150#L773-3 assume activate_threads_~tmp___4~0 != 0;~t5_st~0 := 0; 210147#L773-5 assume { :end_inline_activate_threads } true; 210145#L790 assume { :end_inline_immediate_notify } true;~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 210138#L91 assume { :end_inline_master } true; 210137#L494 assume !(~t1_st~0 == 0); 210136#L508 assume !(~t2_st~0 == 0); 214144#L522 assume !(~t3_st~0 == 0); 214140#L536 assume !(~t4_st~0 == 0); 214139#L550 assume !(~t5_st~0 == 0); 216817#L564 assume true; 216537#L484-1 assume !false; 216536#L485 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 216531#L442 assume !(~m_st~0 == 0); 216529#L446 assume !(~t1_st~0 == 0); 216524#L450 assume !(~t2_st~0 == 0); 216526#L454 assume !(~t3_st~0 == 0); 216528#L458 assume !(~t4_st~0 == 0); 216527#L462 assume !(~t5_st~0 == 0);exists_runnable_thread_~__retres1~6 := 0; 216522#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 216518#L475 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 216519#L489 assume !(eval_~tmp~0 != 0); 217479#L579 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 217477#L397-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 217475#L589-3 assume !(~M_E~0 == 0); 217473#L589-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 217471#L594-3 assume !(~T2_E~0 == 0); 217469#L599-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 217467#L604-3 assume !(~T4_E~0 == 0); 217465#L609-3 assume ~T5_E~0 == 0;~T5_E~0 := 1; 217462#L614-3 assume ~E_M~0 == 0;~E_M~0 := 1; 217460#L619-3 assume !(~E_1~0 == 0); 217458#L624-3 assume !(~E_2~0 == 0); 217456#L629-3 assume !(~E_3~0 == 0); 217454#L634-3 assume !(~E_4~0 == 0); 217414#L639-3 assume ~E_5~0 == 0;~E_5~0 := 1; 217172#L644-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 217171#L282-21 assume ~m_pc~0 == 1; 217169#L283-7 assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 217170#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 217156#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 217157#L733-21 assume !(activate_threads_~tmp~1 != 0); 217148#L733-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 217141#L301-21 assume !(~t1_pc~0 == 1); 217138#L301-23 is_transmit1_triggered_~__retres1~1 := 0; 217135#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 217131#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 217128#L741-21 assume !(activate_threads_~tmp___0~0 != 0); 217125#L741-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 217121#L320-21 assume !(~t2_pc~0 == 1); 217117#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 217114#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 217111#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 217108#L749-21 assume !(activate_threads_~tmp___1~0 != 0); 217105#L749-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 217101#L339-21 assume !(~t3_pc~0 == 1); 217098#L339-23 is_transmit3_triggered_~__retres1~3 := 0; 217093#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 217088#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 217083#L757-21 assume !(activate_threads_~tmp___2~0 != 0); 217078#L757-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 217075#L358-21 assume !(~t4_pc~0 == 1); 217071#L358-23 is_transmit4_triggered_~__retres1~4 := 0; 217067#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 217063#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 217059#L765-21 assume !(activate_threads_~tmp___3~0 != 0); 217056#L765-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 217053#L377-21 assume ~t5_pc~0 == 1; 217050#L378-7 assume ~E_5~0 == 1;is_transmit5_triggered_~__retres1~5 := 1; 217045#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 217040#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 217035#L773-21 assume activate_threads_~tmp___4~0 != 0;~t5_st~0 := 0; 217030#L773-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 217025#L657-3 assume !(~M_E~0 == 1); 217021#L657-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 217019#L662-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 217017#L667-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 217014#L672-3 assume !(~T4_E~0 == 1); 217012#L677-3 assume ~T5_E~0 == 1;~T5_E~0 := 2; 217009#L682-3 assume ~E_M~0 == 1;~E_M~0 := 2; 217007#L687-3 assume !(~E_1~0 == 1); 217005#L692-3 assume !(~E_2~0 == 1); 217003#L697-3 assume !(~E_3~0 == 1); 217001#L702-3 assume ~E_4~0 == 1;~E_4~0 := 2; 216999#L707-3 assume ~E_5~0 == 1;~E_5~0 := 2; 216997#L712-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 216995#L442-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 201237#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 201304#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 201305#L937 assume !(start_simulation_~tmp~3 == 0); 201328#L937-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 201246#L442-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 201247#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 201240#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 201241#L892 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 201702#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 201721#L900 start_simulation_#t~ret16 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 201466#L950 assume !(start_simulation_~tmp___0~1 != 0); 200796#L918-3 assume true; 200797#L918-1 [2018-11-10 05:51:14,285 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:14,285 INFO L82 PathProgramCache]: Analyzing trace with hash 959436202, now seen corresponding path program 2 times [2018-11-10 05:51:14,285 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:14,285 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:14,286 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:14,286 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:14,286 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:14,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:14,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:14,305 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:14,305 INFO L82 PathProgramCache]: Analyzing trace with hash 854040473, now seen corresponding path program 1 times [2018-11-10 05:51:14,305 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:14,305 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:14,306 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:14,306 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 05:51:14,306 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:14,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:14,376 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:51:14,377 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:51:14,377 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-10 05:51:14,377 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 05:51:14,377 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-10 05:51:14,377 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-10 05:51:14,378 INFO L87 Difference]: Start difference. First operand 18671 states and 24463 transitions. cyclomatic complexity: 5804 Second operand 6 states. [2018-11-10 05:51:14,823 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:51:14,823 INFO L93 Difference]: Finished difference Result 42084 states and 54088 transitions. [2018-11-10 05:51:14,824 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-10 05:51:14,824 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 42084 states and 54088 transitions. [2018-11-10 05:51:15,072 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 28388 [2018-11-10 05:51:15,141 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 42084 states to 42084 states and 54088 transitions. [2018-11-10 05:51:15,141 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28682 [2018-11-10 05:51:15,153 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28682 [2018-11-10 05:51:15,153 INFO L73 IsDeterministic]: Start isDeterministic. Operand 42084 states and 54088 transitions. [2018-11-10 05:51:15,155 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-10 05:51:15,155 INFO L705 BuchiCegarLoop]: Abstraction has 42084 states and 54088 transitions. [2018-11-10 05:51:15,172 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42084 states and 54088 transitions. [2018-11-10 05:51:15,357 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42084 to 21332. [2018-11-10 05:51:15,357 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21332 states. [2018-11-10 05:51:15,382 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21332 states to 21332 states and 27444 transitions. [2018-11-10 05:51:15,383 INFO L728 BuchiCegarLoop]: Abstraction has 21332 states and 27444 transitions. [2018-11-10 05:51:15,383 INFO L608 BuchiCegarLoop]: Abstraction has 21332 states and 27444 transitions. [2018-11-10 05:51:15,383 INFO L442 BuchiCegarLoop]: ======== Iteration 22============ [2018-11-10 05:51:15,383 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21332 states and 27444 transitions. [2018-11-10 05:51:15,423 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14400 [2018-11-10 05:51:15,423 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:51:15,423 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:51:15,424 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:15,424 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:15,424 INFO L793 eck$LassoCheckResult]: Stem: 262533#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 262373#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 262374#L881 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 262188#L397 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 262189#L404 assume ~m_i~0 == 1;~m_st~0 := 0; 262779#L404-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 262022#L409-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 262023#L414-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 262190#L419-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 261904#L424-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 261905#L429-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 261935#L589 assume !(~M_E~0 == 0); 261936#L589-2 assume !(~T1_E~0 == 0); 261954#L594-1 assume !(~T2_E~0 == 0); 261555#L599-1 assume !(~T3_E~0 == 0); 261556#L604-1 assume !(~T4_E~0 == 0); 261810#L609-1 assume !(~T5_E~0 == 0); 261811#L614-1 assume !(~E_M~0 == 0); 262326#L619-1 assume !(~E_1~0 == 0); 262327#L624-1 assume !(~E_2~0 == 0); 262050#L629-1 assume !(~E_3~0 == 0); 262051#L634-1 assume !(~E_4~0 == 0); 262203#L639-1 assume !(~E_5~0 == 0); 261929#L644-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 261930#L282 assume !(~m_pc~0 == 1); 262600#L282-2 is_master_triggered_~__retres1~0 := 0; 262601#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 262602#L294 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 262714#L733 assume !(activate_threads_~tmp~1 != 0); 262715#L733-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 261784#L301 assume !(~t1_pc~0 == 1); 261767#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 261705#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 261706#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 261827#L741 assume !(activate_threads_~tmp___0~0 != 0); 261793#L741-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 261794#L320 assume !(~t2_pc~0 == 1); 262031#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 262165#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 262028#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 262029#L749 assume !(activate_threads_~tmp___1~0 != 0); 262527#L749-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 262507#L339 assume !(~t3_pc~0 == 1); 262377#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 262514#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 262429#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 262430#L757 assume !(activate_threads_~tmp___2~0 != 0); 262748#L757-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 261917#L358 assume !(~t4_pc~0 == 1); 261831#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 261832#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 261912#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 261963#L765 assume !(activate_threads_~tmp___3~0 != 0); 261964#L765-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 261965#L377 assume !(~t5_pc~0 == 1); 261788#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 262279#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 261785#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 261786#L773 assume !(activate_threads_~tmp___4~0 != 0); 262314#L773-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 262315#L657 assume !(~M_E~0 == 1); 262819#L657-2 assume !(~T1_E~0 == 1); 262098#L662-1 assume !(~T2_E~0 == 1); 262099#L667-1 assume !(~T3_E~0 == 1); 262530#L672-1 assume !(~T4_E~0 == 1); 261927#L677-1 assume !(~T5_E~0 == 1); 261928#L682-1 assume !(~E_M~0 == 1); 261540#L687-1 assume !(~E_1~0 == 1); 261541#L692-1 assume !(~E_2~0 == 1); 261795#L697-1 assume !(~E_3~0 == 1); 261796#L702-1 assume !(~E_4~0 == 1); 262316#L707-1 assume !(~E_5~0 == 1); 262317#L712-1 assume { :end_inline_reset_delta_events } true; 262818#L918-3 assume true; 266507#L918-1 assume !false; 272644#L919 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 272645#L564 [2018-11-10 05:51:15,424 INFO L795 eck$LassoCheckResult]: Loop: 272645#L564 assume true; 275522#L484-1 assume !false; 272633#L485 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 272634#L442 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 272626#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 272627#L475 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 272618#L489 assume eval_~tmp~0 != 0; 272619#L489-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 272611#L497 assume !(eval_~tmp_ndt_1~0 != 0); 272613#L494 assume !(~t1_st~0 == 0); 272664#L508 assume !(~t2_st~0 == 0); 272661#L522 assume !(~t3_st~0 == 0); 272650#L536 assume !(~t4_st~0 == 0); 272651#L550 assume !(~t5_st~0 == 0); 272645#L564 [2018-11-10 05:51:15,425 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:15,425 INFO L82 PathProgramCache]: Analyzing trace with hash -1399767604, now seen corresponding path program 1 times [2018-11-10 05:51:15,425 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:15,425 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:15,426 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:15,430 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:15,430 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:15,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:15,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:15,452 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:15,452 INFO L82 PathProgramCache]: Analyzing trace with hash 976158679, now seen corresponding path program 1 times [2018-11-10 05:51:15,452 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:15,452 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:15,453 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:15,453 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:15,453 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:15,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:15,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:15,458 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:15,458 INFO L82 PathProgramCache]: Analyzing trace with hash -1639006622, now seen corresponding path program 1 times [2018-11-10 05:51:15,458 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:15,458 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:15,458 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:15,459 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:15,459 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:15,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:15,486 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:51:15,486 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:51:15,486 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 05:51:15,544 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 05:51:15,545 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 05:51:15,545 INFO L87 Difference]: Start difference. First operand 21332 states and 27444 transitions. cyclomatic complexity: 6136 Second operand 3 states. [2018-11-10 05:51:15,611 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:51:15,611 INFO L93 Difference]: Finished difference Result 36784 states and 46826 transitions. [2018-11-10 05:51:15,613 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 05:51:15,614 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 36784 states and 46826 transitions. [2018-11-10 05:51:15,694 INFO L131 ngComponentsAnalysis]: Automaton has 28 accepting balls. 24156 [2018-11-10 05:51:15,752 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 36784 states to 36784 states and 46826 transitions. [2018-11-10 05:51:15,753 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25240 [2018-11-10 05:51:15,764 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25240 [2018-11-10 05:51:15,764 INFO L73 IsDeterministic]: Start isDeterministic. Operand 36784 states and 46826 transitions. [2018-11-10 05:51:15,766 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-10 05:51:15,766 INFO L705 BuchiCegarLoop]: Abstraction has 36784 states and 46826 transitions. [2018-11-10 05:51:15,781 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36784 states and 46826 transitions. [2018-11-10 05:51:15,949 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36784 to 36784. [2018-11-10 05:51:15,949 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36784 states. [2018-11-10 05:51:15,984 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36784 states to 36784 states and 46826 transitions. [2018-11-10 05:51:15,984 INFO L728 BuchiCegarLoop]: Abstraction has 36784 states and 46826 transitions. [2018-11-10 05:51:15,985 INFO L608 BuchiCegarLoop]: Abstraction has 36784 states and 46826 transitions. [2018-11-10 05:51:15,985 INFO L442 BuchiCegarLoop]: ======== Iteration 23============ [2018-11-10 05:51:15,985 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36784 states and 46826 transitions. [2018-11-10 05:51:16,047 INFO L131 ngComponentsAnalysis]: Automaton has 28 accepting balls. 24156 [2018-11-10 05:51:16,047 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:51:16,047 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:51:16,048 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:16,048 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:16,049 INFO L793 eck$LassoCheckResult]: Stem: 320639#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 320493#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 320494#L881 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 320311#L397 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 320312#L404 assume ~m_i~0 == 1;~m_st~0 := 0; 320873#L404-2 assume !(~t1_i~0 == 1);~t1_st~0 := 2; 320886#L409-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 322167#L414-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 322166#L419-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 322165#L424-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 322164#L429-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 322163#L589 assume !(~M_E~0 == 0); 322162#L589-2 assume !(~T1_E~0 == 0); 322161#L594-1 assume !(~T2_E~0 == 0); 322160#L599-1 assume !(~T3_E~0 == 0); 322159#L604-1 assume !(~T4_E~0 == 0); 322158#L609-1 assume !(~T5_E~0 == 0); 322157#L614-1 assume !(~E_M~0 == 0); 322156#L619-1 assume !(~E_1~0 == 0); 322155#L624-1 assume !(~E_2~0 == 0); 322154#L629-1 assume !(~E_3~0 == 0); 322153#L634-1 assume !(~E_4~0 == 0); 322152#L639-1 assume !(~E_5~0 == 0); 322151#L644-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 322150#L282 assume !(~m_pc~0 == 1); 322149#L282-2 is_master_triggered_~__retres1~0 := 0; 322148#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 322147#L294 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 322146#L733 assume !(activate_threads_~tmp~1 != 0); 322145#L733-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 322144#L301 assume !(~t1_pc~0 == 1); 322143#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 322142#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 322141#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 322140#L741 assume !(activate_threads_~tmp___0~0 != 0); 322139#L741-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 322138#L320 assume !(~t2_pc~0 == 1); 322136#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 322135#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 322134#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 322133#L749 assume !(activate_threads_~tmp___1~0 != 0); 322132#L749-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 322131#L339 assume !(~t3_pc~0 == 1); 320622#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 320612#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 320557#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 320558#L757 assume !(activate_threads_~tmp___2~0 != 0); 320845#L757-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 320035#L358 assume !(~t4_pc~0 == 1); 319952#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 319953#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 320030#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 320081#L765 assume !(activate_threads_~tmp___3~0 != 0); 320082#L765-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 320083#L377 assume !(~t5_pc~0 == 1); 319907#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 320400#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 319904#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 319905#L773 assume !(activate_threads_~tmp___4~0 != 0); 320435#L773-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 320436#L657 assume !(~M_E~0 == 1); 320916#L657-2 assume !(~T1_E~0 == 1); 320220#L662-1 assume !(~T2_E~0 == 1); 320221#L667-1 assume !(~T3_E~0 == 1); 320636#L672-1 assume !(~T4_E~0 == 1); 320044#L677-1 assume !(~T5_E~0 == 1); 320045#L682-1 assume !(~E_M~0 == 1); 319664#L687-1 assume !(~E_1~0 == 1); 319665#L692-1 assume !(~E_2~0 == 1); 319914#L697-1 assume !(~E_3~0 == 1); 319915#L702-1 assume !(~E_4~0 == 1); 320846#L707-1 assume !(~E_5~0 == 1); 322092#L712-1 assume { :end_inline_reset_delta_events } true; 322089#L918-3 assume true; 322090#L918-1 assume !false; 344083#L919 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 344077#L564 [2018-11-10 05:51:16,049 INFO L795 eck$LassoCheckResult]: Loop: 344077#L564 assume true; 344072#L484-1 assume !false; 344067#L485 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 344063#L442 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 344059#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 344056#L475 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 344051#L489 assume eval_~tmp~0 != 0; 344047#L489-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 344043#L497 assume !(eval_~tmp_ndt_1~0 != 0); 344044#L494 assume !(~t1_st~0 == 0); 344041#L508 assume !(~t2_st~0 == 0); 344034#L522 assume !(~t3_st~0 == 0); 344028#L536 assume !(~t4_st~0 == 0); 344023#L550 assume !(~t5_st~0 == 0); 344077#L564 [2018-11-10 05:51:16,049 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:16,049 INFO L82 PathProgramCache]: Analyzing trace with hash 1927849038, now seen corresponding path program 1 times [2018-11-10 05:51:16,049 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:16,049 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:16,050 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:16,050 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:16,050 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:16,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:16,084 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:51:16,084 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:51:16,084 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 05:51:16,084 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 05:51:16,084 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:16,085 INFO L82 PathProgramCache]: Analyzing trace with hash 976158679, now seen corresponding path program 2 times [2018-11-10 05:51:16,085 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:16,085 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:16,086 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:16,086 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:16,086 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:16,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:16,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:16,137 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 05:51:16,137 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 05:51:16,138 INFO L87 Difference]: Start difference. First operand 36784 states and 46826 transitions. cyclomatic complexity: 10084 Second operand 3 states. [2018-11-10 05:51:16,177 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:51:16,177 INFO L93 Difference]: Finished difference Result 23266 states and 29546 transitions. [2018-11-10 05:51:16,180 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 05:51:16,180 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23266 states and 29546 transitions. [2018-11-10 05:51:16,230 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 15804 [2018-11-10 05:51:16,270 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23266 states to 23266 states and 29546 transitions. [2018-11-10 05:51:16,270 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15977 [2018-11-10 05:51:16,278 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15977 [2018-11-10 05:51:16,278 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23266 states and 29546 transitions. [2018-11-10 05:51:16,281 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-10 05:51:16,281 INFO L705 BuchiCegarLoop]: Abstraction has 23266 states and 29546 transitions. [2018-11-10 05:51:16,291 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23266 states and 29546 transitions. [2018-11-10 05:51:16,416 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23266 to 23266. [2018-11-10 05:51:16,417 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23266 states. [2018-11-10 05:51:16,444 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23266 states to 23266 states and 29546 transitions. [2018-11-10 05:51:16,444 INFO L728 BuchiCegarLoop]: Abstraction has 23266 states and 29546 transitions. [2018-11-10 05:51:16,444 INFO L608 BuchiCegarLoop]: Abstraction has 23266 states and 29546 transitions. [2018-11-10 05:51:16,444 INFO L442 BuchiCegarLoop]: ======== Iteration 24============ [2018-11-10 05:51:16,444 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23266 states and 29546 transitions. [2018-11-10 05:51:16,578 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 15804 [2018-11-10 05:51:16,578 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:51:16,578 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:51:16,579 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:16,579 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:16,579 INFO L793 eck$LassoCheckResult]: Stem: 380677#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 380552#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 380553#L881 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 380361#L397 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 380362#L404 assume ~m_i~0 == 1;~m_st~0 := 0; 380932#L404-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 380199#L409-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 380200#L414-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 380364#L419-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 380093#L424-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 380094#L429-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 380121#L589 assume !(~M_E~0 == 0); 380122#L589-2 assume !(~T1_E~0 == 0); 380140#L594-1 assume !(~T2_E~0 == 0); 379734#L599-1 assume !(~T3_E~0 == 0); 379735#L604-1 assume !(~T4_E~0 == 0); 379999#L609-1 assume !(~T5_E~0 == 0); 380000#L614-1 assume !(~E_M~0 == 0); 380503#L619-1 assume !(~E_1~0 == 0); 380504#L624-1 assume !(~E_2~0 == 0); 380223#L629-1 assume !(~E_3~0 == 0); 380224#L634-1 assume !(~E_4~0 == 0); 380375#L639-1 assume !(~E_5~0 == 0); 380115#L644-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 380116#L282 assume !(~m_pc~0 == 1); 380749#L282-2 is_master_triggered_~__retres1~0 := 0; 380755#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 380756#L294 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 380867#L733 assume !(activate_threads_~tmp~1 != 0); 380868#L733-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 379971#L301 assume !(~t1_pc~0 == 1); 379957#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 379897#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 379898#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 380020#L741 assume !(activate_threads_~tmp___0~0 != 0); 379980#L741-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 379981#L320 assume !(~t2_pc~0 == 1); 380204#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 380342#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 380201#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 380202#L749 assume !(activate_threads_~tmp___1~0 != 0); 380673#L749-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 380659#L339 assume !(~t3_pc~0 == 1); 380556#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 380658#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 380614#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 380615#L757 assume !(activate_threads_~tmp___2~0 != 0); 380901#L757-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 380104#L358 assume !(~t4_pc~0 == 1); 380021#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 380022#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 380103#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 380151#L765 assume !(activate_threads_~tmp___3~0 != 0); 380152#L765-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 380153#L377 assume !(~t5_pc~0 == 1); 379976#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 380454#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 379972#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 379973#L773 assume !(activate_threads_~tmp___4~0 != 0); 380490#L773-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 380491#L657 assume !(~M_E~0 == 1); 380973#L657-2 assume !(~T1_E~0 == 1); 380270#L662-1 assume !(~T2_E~0 == 1); 380271#L667-1 assume !(~T3_E~0 == 1); 380674#L672-1 assume !(~T4_E~0 == 1); 380113#L677-1 assume !(~T5_E~0 == 1); 380114#L682-1 assume !(~E_M~0 == 1); 379720#L687-1 assume !(~E_1~0 == 1); 379721#L692-1 assume !(~E_2~0 == 1); 379982#L697-1 assume !(~E_3~0 == 1); 379983#L702-1 assume !(~E_4~0 == 1); 380495#L707-1 assume !(~E_5~0 == 1); 380496#L712-1 assume { :end_inline_reset_delta_events } true; 380972#L918-3 assume true; 382189#L918-1 assume !false; 393746#L919 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 393741#L564 [2018-11-10 05:51:16,580 INFO L795 eck$LassoCheckResult]: Loop: 393741#L564 assume true; 393738#L484-1 assume !false; 393736#L485 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 393735#L442 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 393734#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 393730#L475 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 393728#L489 assume eval_~tmp~0 != 0; 393726#L489-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 393723#L497 assume !(eval_~tmp_ndt_1~0 != 0); 393722#L494 assume ~t1_st~0 == 0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 393720#L511 assume !(eval_~tmp_ndt_2~0 != 0); 393721#L508 assume !(~t2_st~0 == 0); 394448#L522 assume !(~t3_st~0 == 0); 394441#L536 assume !(~t4_st~0 == 0); 393747#L550 assume !(~t5_st~0 == 0); 393741#L564 [2018-11-10 05:51:16,580 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:16,580 INFO L82 PathProgramCache]: Analyzing trace with hash -1399767604, now seen corresponding path program 2 times [2018-11-10 05:51:16,580 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:16,580 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:16,581 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:16,581 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 05:51:16,581 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:16,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:16,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:16,604 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:16,604 INFO L82 PathProgramCache]: Analyzing trace with hash -781326001, now seen corresponding path program 1 times [2018-11-10 05:51:16,604 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:16,604 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:16,605 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:16,605 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 05:51:16,605 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:16,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:16,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:16,609 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:16,610 INFO L82 PathProgramCache]: Analyzing trace with hash -247071708, now seen corresponding path program 1 times [2018-11-10 05:51:16,610 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:16,610 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:16,611 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:16,611 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:16,611 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:16,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:16,652 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:51:16,652 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:51:16,652 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 05:51:16,715 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 05:51:16,715 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 05:51:16,715 INFO L87 Difference]: Start difference. First operand 23266 states and 29546 transitions. cyclomatic complexity: 6304 Second operand 3 states. [2018-11-10 05:51:16,828 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:51:16,828 INFO L93 Difference]: Finished difference Result 41505 states and 52325 transitions. [2018-11-10 05:51:16,829 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 05:51:16,829 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41505 states and 52325 transitions. [2018-11-10 05:51:16,924 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 27870 [2018-11-10 05:51:16,982 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41505 states to 41505 states and 52325 transitions. [2018-11-10 05:51:16,982 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28131 [2018-11-10 05:51:16,994 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28131 [2018-11-10 05:51:16,994 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41505 states and 52325 transitions. [2018-11-10 05:51:16,995 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-10 05:51:16,995 INFO L705 BuchiCegarLoop]: Abstraction has 41505 states and 52325 transitions. [2018-11-10 05:51:17,015 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41505 states and 52325 transitions. [2018-11-10 05:51:17,214 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41505 to 41505. [2018-11-10 05:51:17,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41505 states. [2018-11-10 05:51:17,258 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41505 states to 41505 states and 52325 transitions. [2018-11-10 05:51:17,258 INFO L728 BuchiCegarLoop]: Abstraction has 41505 states and 52325 transitions. [2018-11-10 05:51:17,258 INFO L608 BuchiCegarLoop]: Abstraction has 41505 states and 52325 transitions. [2018-11-10 05:51:17,258 INFO L442 BuchiCegarLoop]: ======== Iteration 25============ [2018-11-10 05:51:17,259 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41505 states and 52325 transitions. [2018-11-10 05:51:17,340 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 27870 [2018-11-10 05:51:17,340 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:51:17,340 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:51:17,341 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:17,341 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:17,341 INFO L793 eck$LassoCheckResult]: Stem: 445469#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 445328#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 445329#L881 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 445135#L397 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 445136#L404 assume ~m_i~0 == 1;~m_st~0 := 0; 445702#L404-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 444971#L409-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 444972#L414-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 445137#L419-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 444874#L424-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 444875#L429-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 444904#L589 assume !(~M_E~0 == 0); 444905#L589-2 assume !(~T1_E~0 == 0); 444922#L594-1 assume !(~T2_E~0 == 0); 444515#L599-1 assume !(~T3_E~0 == 0); 444516#L604-1 assume !(~T4_E~0 == 0); 444780#L609-1 assume !(~T5_E~0 == 0); 444781#L614-1 assume !(~E_M~0 == 0); 445281#L619-1 assume !(~E_1~0 == 0); 445282#L624-1 assume !(~E_2~0 == 0); 444999#L629-1 assume !(~E_3~0 == 0); 445000#L634-1 assume !(~E_4~0 == 0); 445149#L639-1 assume !(~E_5~0 == 0); 444898#L644-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 444899#L282 assume !(~m_pc~0 == 1); 445535#L282-2 is_master_triggered_~__retres1~0 := 0; 445536#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 445537#L294 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 445641#L733 assume !(activate_threads_~tmp~1 != 0); 445642#L733-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 444752#L301 assume !(~t1_pc~0 == 1); 444734#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 444671#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 444672#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 444797#L741 assume !(activate_threads_~tmp___0~0 != 0); 444761#L741-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 444762#L320 assume !(~t2_pc~0 == 1); 444980#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 445113#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 444977#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 444978#L749 assume !(activate_threads_~tmp___1~0 != 0); 445465#L749-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 445447#L339 assume !(~t3_pc~0 == 1); 445332#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 445446#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 445395#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 445396#L757 assume !(activate_threads_~tmp___2~0 != 0); 445668#L757-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 444886#L358 assume !(~t4_pc~0 == 1); 444801#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 444802#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 444881#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 444933#L765 assume !(activate_threads_~tmp___3~0 != 0); 444934#L765-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 444935#L377 assume !(~t5_pc~0 == 1); 444756#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 445228#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 444753#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 444754#L773 assume !(activate_threads_~tmp___4~0 != 0); 445269#L773-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 445270#L657 assume !(~M_E~0 == 1); 445747#L657-2 assume !(~T1_E~0 == 1); 445048#L662-1 assume !(~T2_E~0 == 1); 445049#L667-1 assume !(~T3_E~0 == 1); 445466#L672-1 assume !(~T4_E~0 == 1); 444896#L677-1 assume !(~T5_E~0 == 1); 444897#L682-1 assume !(~E_M~0 == 1); 444499#L687-1 assume !(~E_1~0 == 1); 444500#L692-1 assume !(~E_2~0 == 1); 444763#L697-1 assume !(~E_3~0 == 1); 444764#L702-1 assume !(~E_4~0 == 1); 445271#L707-1 assume !(~E_5~0 == 1); 445272#L712-1 assume { :end_inline_reset_delta_events } true; 445746#L918-3 assume true; 453117#L918-1 assume !false; 484618#L919 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 484610#L564 [2018-11-10 05:51:17,342 INFO L795 eck$LassoCheckResult]: Loop: 484610#L564 assume true; 484602#L484-1 assume !false; 484593#L485 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 484586#L442 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 484578#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 484577#L475 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 484566#L489 assume eval_~tmp~0 != 0; 484560#L489-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 484551#L497 assume !(eval_~tmp_ndt_1~0 != 0); 484552#L494 assume ~t1_st~0 == 0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 484962#L511 assume !(eval_~tmp_ndt_2~0 != 0); 474606#L508 assume ~t2_st~0 == 0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 474603#L525 assume !(eval_~tmp_ndt_3~0 != 0); 474604#L522 assume !(~t3_st~0 == 0); 481927#L536 assume !(~t4_st~0 == 0); 481924#L550 assume !(~t5_st~0 == 0); 484610#L564 [2018-11-10 05:51:17,342 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:17,342 INFO L82 PathProgramCache]: Analyzing trace with hash -1399767604, now seen corresponding path program 3 times [2018-11-10 05:51:17,342 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:17,342 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:17,343 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:17,343 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:17,343 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:17,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:17,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:17,367 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:17,367 INFO L82 PathProgramCache]: Analyzing trace with hash 1378620623, now seen corresponding path program 1 times [2018-11-10 05:51:17,367 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:17,367 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:17,368 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:17,368 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 05:51:17,368 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:17,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:17,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:17,373 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:17,373 INFO L82 PathProgramCache]: Analyzing trace with hash 760634522, now seen corresponding path program 1 times [2018-11-10 05:51:17,373 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:17,373 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:17,374 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:17,374 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:17,374 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:17,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:17,405 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:51:17,405 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:51:17,406 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 05:51:17,485 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 05:51:17,485 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 05:51:17,485 INFO L87 Difference]: Start difference. First operand 41505 states and 52325 transitions. cyclomatic complexity: 10844 Second operand 3 states. [2018-11-10 05:51:17,619 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:51:17,619 INFO L93 Difference]: Finished difference Result 76199 states and 95882 transitions. [2018-11-10 05:51:17,620 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 05:51:17,620 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 76199 states and 95882 transitions. [2018-11-10 05:51:17,787 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 51260 [2018-11-10 05:51:17,897 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 76199 states to 76199 states and 95882 transitions. [2018-11-10 05:51:17,897 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51697 [2018-11-10 05:51:17,919 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51697 [2018-11-10 05:51:17,919 INFO L73 IsDeterministic]: Start isDeterministic. Operand 76199 states and 95882 transitions. [2018-11-10 05:51:17,922 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-10 05:51:17,922 INFO L705 BuchiCegarLoop]: Abstraction has 76199 states and 95882 transitions. [2018-11-10 05:51:17,952 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76199 states and 95882 transitions. [2018-11-10 05:51:18,508 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76199 to 71363. [2018-11-10 05:51:18,509 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 71363 states. [2018-11-10 05:51:18,590 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71363 states to 71363 states and 90344 transitions. [2018-11-10 05:51:18,591 INFO L728 BuchiCegarLoop]: Abstraction has 71363 states and 90344 transitions. [2018-11-10 05:51:18,591 INFO L608 BuchiCegarLoop]: Abstraction has 71363 states and 90344 transitions. [2018-11-10 05:51:18,591 INFO L442 BuchiCegarLoop]: ======== Iteration 26============ [2018-11-10 05:51:18,591 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 71363 states and 90344 transitions. [2018-11-10 05:51:18,712 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 48010 [2018-11-10 05:51:18,713 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:51:18,713 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:51:18,714 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:18,714 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:18,714 INFO L793 eck$LassoCheckResult]: Stem: 563217#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 563060#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 563061#L881 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 562869#L397 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 562870#L404 assume ~m_i~0 == 1;~m_st~0 := 0; 563498#L404-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 562704#L409-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 562705#L414-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 562872#L419-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 562588#L424-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 562589#L429-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 562618#L589 assume !(~M_E~0 == 0); 562619#L589-2 assume !(~T1_E~0 == 0); 562636#L594-1 assume !(~T2_E~0 == 0); 562226#L599-1 assume !(~T3_E~0 == 0); 562227#L604-1 assume !(~T4_E~0 == 0); 562496#L609-1 assume !(~T5_E~0 == 0); 562497#L614-1 assume !(~E_M~0 == 0); 563011#L619-1 assume !(~E_1~0 == 0); 563012#L624-1 assume !(~E_2~0 == 0); 562728#L629-1 assume !(~E_3~0 == 0); 562729#L634-1 assume !(~E_4~0 == 0); 562884#L639-1 assume !(~E_5~0 == 0); 562612#L644-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 562613#L282 assume !(~m_pc~0 == 1); 563297#L282-2 is_master_triggered_~__retres1~0 := 0; 563302#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 563303#L294 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 563426#L733 assume !(activate_threads_~tmp~1 != 0); 563427#L733-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 562468#L301 assume !(~t1_pc~0 == 1); 562452#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 562387#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 562388#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 562515#L741 assume !(activate_threads_~tmp___0~0 != 0); 562477#L741-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 562478#L320 assume !(~t2_pc~0 == 1); 562709#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 562848#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 562706#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 562707#L749 assume !(activate_threads_~tmp___1~0 != 0); 563212#L749-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 563187#L339 assume !(~t3_pc~0 == 1); 563064#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 563186#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 563127#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 563128#L757 assume !(activate_threads_~tmp___2~0 != 0); 563461#L757-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 562601#L358 assume !(~t4_pc~0 == 1); 562516#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 562517#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 562600#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 562648#L765 assume !(activate_threads_~tmp___3~0 != 0); 562649#L765-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 562650#L377 assume !(~t5_pc~0 == 1); 562473#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 562966#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 562469#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 562470#L773 assume !(activate_threads_~tmp___4~0 != 0); 562999#L773-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 563000#L657 assume !(~M_E~0 == 1); 563542#L657-2 assume !(~T1_E~0 == 1); 562774#L662-1 assume !(~T2_E~0 == 1); 562775#L667-1 assume !(~T3_E~0 == 1); 563213#L672-1 assume !(~T4_E~0 == 1); 562610#L677-1 assume !(~T5_E~0 == 1); 562611#L682-1 assume !(~E_M~0 == 1); 562211#L687-1 assume !(~E_1~0 == 1); 562212#L692-1 assume !(~E_2~0 == 1); 562479#L697-1 assume !(~E_3~0 == 1); 562480#L702-1 assume !(~E_4~0 == 1); 563003#L707-1 assume !(~E_5~0 == 1); 563004#L712-1 assume { :end_inline_reset_delta_events } true; 563541#L918-3 assume true; 572994#L918-1 assume !false; 599985#L919 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 599981#L564 [2018-11-10 05:51:18,714 INFO L795 eck$LassoCheckResult]: Loop: 599981#L564 assume true; 599980#L484-1 assume !false; 599979#L485 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 599977#L442 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 599976#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 599975#L475 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 599973#L489 assume eval_~tmp~0 != 0; 599971#L489-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 599968#L497 assume !(eval_~tmp_ndt_1~0 != 0); 599969#L494 assume ~t1_st~0 == 0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 603655#L511 assume !(eval_~tmp_ndt_2~0 != 0); 599996#L508 assume ~t2_st~0 == 0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 599993#L525 assume !(eval_~tmp_ndt_3~0 != 0); 599991#L522 assume ~t3_st~0 == 0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 598375#L539 assume !(eval_~tmp_ndt_4~0 != 0); 599987#L536 assume !(~t4_st~0 == 0); 599986#L550 assume !(~t5_st~0 == 0); 599981#L564 [2018-11-10 05:51:18,714 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:18,714 INFO L82 PathProgramCache]: Analyzing trace with hash -1399767604, now seen corresponding path program 4 times [2018-11-10 05:51:18,714 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:18,715 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:18,715 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:18,715 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:18,715 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:18,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:18,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:18,736 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:18,736 INFO L82 PathProgramCache]: Analyzing trace with hash -217918377, now seen corresponding path program 1 times [2018-11-10 05:51:18,736 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:18,736 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:18,737 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:18,737 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 05:51:18,737 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:18,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:18,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:18,741 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:18,742 INFO L82 PathProgramCache]: Analyzing trace with hash 2099348972, now seen corresponding path program 1 times [2018-11-10 05:51:18,742 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:18,742 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:18,742 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:18,743 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:18,743 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:18,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:18,774 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:51:18,774 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:51:18,774 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 05:51:18,843 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 05:51:18,844 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 05:51:18,844 INFO L87 Difference]: Start difference. First operand 71363 states and 90344 transitions. cyclomatic complexity: 19005 Second operand 3 states. [2018-11-10 05:51:19,024 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:51:19,024 INFO L93 Difference]: Finished difference Result 91037 states and 114970 transitions. [2018-11-10 05:51:19,026 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 05:51:19,026 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 91037 states and 114970 transitions. [2018-11-10 05:51:19,229 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 61447 [2018-11-10 05:51:19,360 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 91037 states to 91037 states and 114970 transitions. [2018-11-10 05:51:19,360 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 61892 [2018-11-10 05:51:19,387 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 61892 [2018-11-10 05:51:19,387 INFO L73 IsDeterministic]: Start isDeterministic. Operand 91037 states and 114970 transitions. [2018-11-10 05:51:19,396 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-10 05:51:19,396 INFO L705 BuchiCegarLoop]: Abstraction has 91037 states and 114970 transitions. [2018-11-10 05:51:19,432 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91037 states and 114970 transitions. [2018-11-10 05:51:20,299 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91037 to 88697. [2018-11-10 05:51:20,299 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 88697 states. [2018-11-10 05:51:20,386 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88697 states to 88697 states and 112162 transitions. [2018-11-10 05:51:20,386 INFO L728 BuchiCegarLoop]: Abstraction has 88697 states and 112162 transitions. [2018-11-10 05:51:20,386 INFO L608 BuchiCegarLoop]: Abstraction has 88697 states and 112162 transitions. [2018-11-10 05:51:20,386 INFO L442 BuchiCegarLoop]: ======== Iteration 27============ [2018-11-10 05:51:20,386 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 88697 states and 112162 transitions. [2018-11-10 05:51:20,531 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 59887 [2018-11-10 05:51:20,531 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:51:20,531 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:51:20,532 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:20,532 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:20,532 INFO L793 eck$LassoCheckResult]: Stem: 725592#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 725455#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 725456#L881 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 725266#L397 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 725267#L404 assume ~m_i~0 == 1;~m_st~0 := 0; 725866#L404-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 725100#L409-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 725101#L414-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 725269#L419-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 724992#L424-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 724993#L429-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 725023#L589 assume !(~M_E~0 == 0); 725024#L589-2 assume !(~T1_E~0 == 0); 725042#L594-1 assume !(~T2_E~0 == 0); 724634#L599-1 assume !(~T3_E~0 == 0); 724635#L604-1 assume !(~T4_E~0 == 0); 724897#L609-1 assume !(~T5_E~0 == 0); 724898#L614-1 assume !(~E_M~0 == 0); 725406#L619-1 assume !(~E_1~0 == 0); 725407#L624-1 assume !(~E_2~0 == 0); 725124#L629-1 assume !(~E_3~0 == 0); 725125#L634-1 assume !(~E_4~0 == 0); 725279#L639-1 assume !(~E_5~0 == 0); 725017#L644-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 725018#L282 assume !(~m_pc~0 == 1); 725672#L282-2 is_master_triggered_~__retres1~0 := 0; 725679#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 725680#L294 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 725801#L733 assume !(activate_threads_~tmp~1 != 0); 725802#L733-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 724869#L301 assume !(~t1_pc~0 == 1); 724855#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 724792#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 724793#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 724916#L741 assume !(activate_threads_~tmp___0~0 != 0); 724878#L741-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 724879#L320 assume !(~t2_pc~0 == 1); 725105#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 725246#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 725102#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 725103#L749 assume !(activate_threads_~tmp___1~0 != 0); 725587#L749-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 725572#L339 assume !(~t3_pc~0 == 1); 725459#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 725570#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 725571#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 725916#L757 assume !(activate_threads_~tmp___2~0 != 0); 725835#L757-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 725005#L358 assume !(~t4_pc~0 == 1); 724917#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 724918#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 725004#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 725052#L765 assume !(activate_threads_~tmp___3~0 != 0); 725053#L765-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 725054#L377 assume !(~t5_pc~0 == 1); 724874#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 725360#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 724870#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 724871#L773 assume !(activate_threads_~tmp___4~0 != 0); 725393#L773-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 725394#L657 assume !(~M_E~0 == 1); 725913#L657-2 assume !(~T1_E~0 == 1); 725172#L662-1 assume !(~T2_E~0 == 1); 725173#L667-1 assume !(~T3_E~0 == 1); 725589#L672-1 assume !(~T4_E~0 == 1); 725015#L677-1 assume !(~T5_E~0 == 1); 725016#L682-1 assume !(~E_M~0 == 1); 724619#L687-1 assume !(~E_1~0 == 1); 724620#L692-1 assume !(~E_2~0 == 1); 724880#L697-1 assume !(~E_3~0 == 1); 724881#L702-1 assume !(~E_4~0 == 1); 725397#L707-1 assume !(~E_5~0 == 1); 725398#L712-1 assume { :end_inline_reset_delta_events } true; 725912#L918-3 assume true; 735209#L918-1 assume !false; 778671#L919 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 778666#L564 [2018-11-10 05:51:20,532 INFO L795 eck$LassoCheckResult]: Loop: 778666#L564 assume true; 778664#L484-1 assume !false; 778662#L485 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 778660#L442 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 778658#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 778655#L475 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 778653#L489 assume eval_~tmp~0 != 0; 778651#L489-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 778648#L497 assume !(eval_~tmp_ndt_1~0 != 0); 778646#L494 assume ~t1_st~0 == 0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 778644#L511 assume !(eval_~tmp_ndt_2~0 != 0); 771185#L508 assume ~t2_st~0 == 0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 771181#L525 assume !(eval_~tmp_ndt_3~0 != 0); 771182#L522 assume ~t3_st~0 == 0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 778679#L539 assume !(eval_~tmp_ndt_4~0 != 0); 778677#L536 assume ~t4_st~0 == 0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 778674#L553 assume !(eval_~tmp_ndt_5~0 != 0); 778672#L550 assume !(~t5_st~0 == 0); 778666#L564 [2018-11-10 05:51:20,532 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:20,532 INFO L82 PathProgramCache]: Analyzing trace with hash -1399767604, now seen corresponding path program 5 times [2018-11-10 05:51:20,533 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:20,533 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:20,533 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:20,533 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:20,533 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:20,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:20,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:20,558 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:20,558 INFO L82 PathProgramCache]: Analyzing trace with hash 1834289607, now seen corresponding path program 1 times [2018-11-10 05:51:20,558 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:20,558 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:20,559 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:20,559 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 05:51:20,559 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:20,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:20,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:20,563 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:20,564 INFO L82 PathProgramCache]: Analyzing trace with hash 655133394, now seen corresponding path program 1 times [2018-11-10 05:51:20,564 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:20,564 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:20,564 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:20,565 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:20,565 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:20,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:51:20,602 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:51:20,602 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:51:20,602 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 05:51:20,704 WARN L179 SmtUtils]: Spent 100.00 ms on a formula simplification. DAG size of input: 44 DAG size of output: 42 [2018-11-10 05:51:20,724 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 05:51:20,724 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 05:51:20,724 INFO L87 Difference]: Start difference. First operand 88697 states and 112162 transitions. cyclomatic complexity: 23489 Second operand 3 states. [2018-11-10 05:51:21,035 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:51:21,035 INFO L93 Difference]: Finished difference Result 153359 states and 193521 transitions. [2018-11-10 05:51:21,036 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 05:51:21,036 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 153359 states and 193521 transitions. [2018-11-10 05:51:21,395 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 103810 [2018-11-10 05:51:21,629 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 153359 states to 153359 states and 193521 transitions. [2018-11-10 05:51:21,629 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 104615 [2018-11-10 05:51:21,675 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 104615 [2018-11-10 05:51:21,675 INFO L73 IsDeterministic]: Start isDeterministic. Operand 153359 states and 193521 transitions. [2018-11-10 05:51:21,676 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-10 05:51:21,676 INFO L705 BuchiCegarLoop]: Abstraction has 153359 states and 193521 transitions. [2018-11-10 05:51:21,735 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 153359 states and 193521 transitions. [2018-11-10 05:51:24,665 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 153359 to 148799. [2018-11-10 05:51:24,665 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 148799 states. [2018-11-10 05:51:24,825 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148799 states to 148799 states and 188961 transitions. [2018-11-10 05:51:24,826 INFO L728 BuchiCegarLoop]: Abstraction has 148799 states and 188961 transitions. [2018-11-10 05:51:24,826 INFO L608 BuchiCegarLoop]: Abstraction has 148799 states and 188961 transitions. [2018-11-10 05:51:24,826 INFO L442 BuchiCegarLoop]: ======== Iteration 28============ [2018-11-10 05:51:24,826 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 148799 states and 188961 transitions. [2018-11-10 05:51:25,098 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 100700 [2018-11-10 05:51:25,098 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:51:25,098 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:51:25,098 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:25,099 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:51:25,099 INFO L793 eck$LassoCheckResult]: Stem: 967751#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 967591#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 967592#L881 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 967362#L397 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 967363#L404 assume ~m_i~0 == 1;~m_st~0 := 0; 968027#L404-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 967177#L409-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 967178#L414-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 967364#L419-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 967064#L424-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 967065#L429-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 967092#L589 assume !(~M_E~0 == 0); 967093#L589-2 assume !(~T1_E~0 == 0); 967111#L594-1 assume !(~T2_E~0 == 0); 966698#L599-1 assume !(~T3_E~0 == 0); 966699#L604-1 assume !(~T4_E~0 == 0); 966965#L609-1 assume !(~T5_E~0 == 0); 966966#L614-1 assume !(~E_M~0 == 0); 967535#L619-1 assume !(~E_1~0 == 0); 967536#L624-1 assume !(~E_2~0 == 0); 967205#L629-1 assume !(~E_3~0 == 0); 967206#L634-1 assume !(~E_4~0 == 0); 967380#L639-1 assume !(~E_5~0 == 0); 967086#L644-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 967087#L282 assume !(~m_pc~0 == 1); 967828#L282-2 is_master_triggered_~__retres1~0 := 0; 967829#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 967830#L294 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 967956#L733 assume !(activate_threads_~tmp~1 != 0); 967957#L733-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 966938#L301 assume !(~t1_pc~0 == 1); 966919#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 966854#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 966855#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 966985#L741 assume !(activate_threads_~tmp___0~0 != 0); 966948#L741-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 966949#L320 assume !(~t2_pc~0 == 1); 967186#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 967334#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 967183#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 967184#L749 assume !(activate_threads_~tmp___1~0 != 0); 967746#L749-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 967724#L339 assume !(~t3_pc~0 == 1); 967595#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 967722#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 967723#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 968079#L757 assume !(activate_threads_~tmp___2~0 != 0); 967991#L757-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 967075#L358 assume !(~t4_pc~0 == 1); 966989#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 966990#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 967070#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 967122#L765 assume !(activate_threads_~tmp___3~0 != 0); 967123#L765-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 967124#L377 assume !(~t5_pc~0 == 1); 966942#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 967478#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 966939#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 966940#L773 assume !(activate_threads_~tmp___4~0 != 0); 967521#L773-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 967522#L657 assume !(~M_E~0 == 1); 968075#L657-2 assume !(~T1_E~0 == 1); 967259#L662-1 assume !(~T2_E~0 == 1); 967260#L667-1 assume !(~T3_E~0 == 1); 967748#L672-1 assume !(~T4_E~0 == 1); 967084#L677-1 assume !(~T5_E~0 == 1); 967085#L682-1 assume !(~E_M~0 == 1); 966683#L687-1 assume !(~E_1~0 == 1); 966684#L692-1 assume !(~E_2~0 == 1); 966950#L697-1 assume !(~E_3~0 == 1); 966951#L702-1 assume !(~E_4~0 == 1); 967523#L707-1 assume !(~E_5~0 == 1); 967524#L712-1 assume { :end_inline_reset_delta_events } true; 968074#L918-3 assume true; 990216#L918-1 assume !false; 1064033#L919 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 1064034#L564 [2018-11-10 05:51:25,099 INFO L795 eck$LassoCheckResult]: Loop: 1064034#L564 assume true; 1071380#L484-1 assume !false; 1071379#L485 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1071378#L442 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~6 := 1; 1071377#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1071376#L475 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 1071375#L489 assume eval_~tmp~0 != 0; 1071374#L489-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 1071373#L497 assume !(eval_~tmp_ndt_1~0 != 0); 1071372#L494 assume ~t1_st~0 == 0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 1071370#L511 assume !(eval_~tmp_ndt_2~0 != 0); 1071368#L508 assume ~t2_st~0 == 0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 1071347#L525 assume !(eval_~tmp_ndt_3~0 != 0); 1071366#L522 assume ~t3_st~0 == 0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 1071385#L539 assume !(eval_~tmp_ndt_4~0 != 0); 1071384#L536 assume ~t4_st~0 == 0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 1071382#L553 assume !(eval_~tmp_ndt_5~0 != 0); 1071381#L550 assume ~t5_st~0 == 0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 1062305#L567 assume !(eval_~tmp_ndt_6~0 != 0); 1064034#L564 [2018-11-10 05:51:25,099 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:25,099 INFO L82 PathProgramCache]: Analyzing trace with hash -1399767604, now seen corresponding path program 6 times [2018-11-10 05:51:25,100 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:25,100 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:25,100 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:25,100 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:25,101 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:25,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:25,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:25,121 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:25,121 INFO L82 PathProgramCache]: Analyzing trace with hash 1028398943, now seen corresponding path program 1 times [2018-11-10 05:51:25,121 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:25,121 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:25,122 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:25,122 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 05:51:25,122 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:25,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:25,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:25,127 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:51:25,127 INFO L82 PathProgramCache]: Analyzing trace with hash -1165705292, now seen corresponding path program 1 times [2018-11-10 05:51:25,127 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:51:25,127 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:51:25,128 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:25,128 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:51:25,128 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:51:25,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:25,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:51:25,586 WARN L179 SmtUtils]: Spent 332.00 ms on a formula simplification. DAG size of input: 198 DAG size of output: 132 [2018-11-10 05:51:25,706 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 10.11 05:51:25 BoogieIcfgContainer [2018-11-10 05:51:25,706 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2018-11-10 05:51:25,707 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-10 05:51:25,707 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-10 05:51:25,712 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-10 05:51:25,712 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.11 05:51:05" (3/4) ... [2018-11-10 05:51:25,718 INFO L141 WitnessPrinter]: Generating witness for non-termination counterexample [2018-11-10 05:51:25,781 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_3d1a558d-f364-4c06-b466-4401cb7b363c/bin-2019/uautomizer/witness.graphml [2018-11-10 05:51:25,781 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-10 05:51:25,782 INFO L168 Benchmark]: Toolchain (without parser) took 21847.57 ms. Allocated memory was 1.0 GB in the beginning and 3.2 GB in the end (delta: 2.2 GB). Free memory was 952.7 MB in the beginning and 1.9 GB in the end (delta: -940.1 MB). Peak memory consumption was 1.3 GB. Max. memory is 11.5 GB. [2018-11-10 05:51:25,783 INFO L168 Benchmark]: CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 980.1 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-10 05:51:25,783 INFO L168 Benchmark]: CACSL2BoogieTranslator took 223.85 ms. Allocated memory is still 1.0 GB. Free memory was 952.7 MB in the beginning and 933.9 MB in the end (delta: 18.8 MB). Peak memory consumption was 18.8 MB. Max. memory is 11.5 GB. [2018-11-10 05:51:25,783 INFO L168 Benchmark]: Boogie Procedure Inliner took 53.70 ms. Allocated memory is still 1.0 GB. Free memory was 933.9 MB in the beginning and 928.5 MB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2018-11-10 05:51:25,783 INFO L168 Benchmark]: Boogie Preprocessor took 95.49 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 166.2 MB). Free memory was 928.5 MB in the beginning and 1.2 GB in the end (delta: -227.1 MB). Peak memory consumption was 18.0 MB. Max. memory is 11.5 GB. [2018-11-10 05:51:25,784 INFO L168 Benchmark]: RCFGBuilder took 1088.57 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.0 GB in the end (delta: 124.3 MB). Peak memory consumption was 124.3 MB. Max. memory is 11.5 GB. [2018-11-10 05:51:25,784 INFO L168 Benchmark]: BuchiAutomizer took 20307.68 ms. Allocated memory was 1.2 GB in the beginning and 3.2 GB in the end (delta: 2.1 GB). Free memory was 1.0 GB in the beginning and 1.9 GB in the end (delta: -861.8 MB). Peak memory consumption was 1.2 GB. Max. memory is 11.5 GB. [2018-11-10 05:51:25,784 INFO L168 Benchmark]: Witness Printer took 74.96 ms. Allocated memory is still 3.2 GB. Free memory was 1.9 GB in the beginning and 1.9 GB in the end (delta: 273.9 kB). Peak memory consumption was 273.9 kB. Max. memory is 11.5 GB. [2018-11-10 05:51:25,786 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 980.1 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 223.85 ms. Allocated memory is still 1.0 GB. Free memory was 952.7 MB in the beginning and 933.9 MB in the end (delta: 18.8 MB). Peak memory consumption was 18.8 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 53.70 ms. Allocated memory is still 1.0 GB. Free memory was 933.9 MB in the beginning and 928.5 MB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 95.49 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 166.2 MB). Free memory was 928.5 MB in the beginning and 1.2 GB in the end (delta: -227.1 MB). Peak memory consumption was 18.0 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1088.57 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.0 GB in the end (delta: 124.3 MB). Peak memory consumption was 124.3 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 20307.68 ms. Allocated memory was 1.2 GB in the beginning and 3.2 GB in the end (delta: 2.1 GB). Free memory was 1.0 GB in the beginning and 1.9 GB in the end (delta: -861.8 MB). Peak memory consumption was 1.2 GB. Max. memory is 11.5 GB. * Witness Printer took 74.96 ms. Allocated memory is still 3.2 GB. Free memory was 1.9 GB in the beginning and 1.9 GB in the end (delta: 273.9 kB). Peak memory consumption was 273.9 kB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 28 terminating modules (27 trivial, 1 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function -1 * E_3 + 1 and consists of 3 locations. 27 modules have a trivial ranking function, the largest among these consists of 6 locations. The remainder module has 148799 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 20.2s and 28 iterations. TraceHistogramMax:2. Analysis of lassos took 6.1s. Construction of modules took 1.1s. Büchi inclusion checks took 1.9s. Highest rank in rank-based complementation 3. Minimization of det autom 18. Minimization of nondet autom 10. Automata minimization 6.8s AutomataMinimizationTime, 28 MinimizatonAttempts, 73156 StatesRemovedByMinimization, 15 NontrivialMinimizations. Non-live state removal took 2.6s Buchi closure took 0.2s. Biggest automaton had 148799 states and ocurred in iteration 27. Nontrivial modules had stage [1, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 24387 SDtfs, 29765 SDslu, 27717 SDs, 0 SdLazy, 1174 SolverSat, 459 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.1s Time LassoAnalysisResults: nont1 unkn0 SFLI8 SFLT0 conc5 concLT1 SILN1 SILU0 SILI12 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital217 mio100 ax100 hnf100 lsp5 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq209 hnf86 smp100 dnf189 smp63 tf108 neg92 sie116 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 1ms VariablesStem: 0 VariablesLoop: 1 DisjunctsStem: 1 DisjunctsLoop: 2 SupportingInvariants: 0 MotzkinApplications: 4 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 6 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 1 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.1s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 484]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {__retres1=0, t3_st=0, token=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2bc1a65=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@27215064=0, tmp=1, t5_i=1, __retres1=0, kernel_st=1, t2_st=0, t4_i=1, E_3=2, t4_pc=0, E_5=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4507f843=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7c165aa6=0, E_1=2, tmp_ndt_2=0, \result=0, __retres1=0, \result=0, tmp_ndt_4=0, tmp_ndt_6=0, m_st=0, tmp___2=0, tmp___0=0, t3_pc=0, tmp=0, \result=0, __retres1=0, m_pc=0, tmp___4=0, \result=0, __retres1=0, \result=0, __retres1=0, \result=0, T2_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4c4e3577=0, tmp___0=0, t1_pc=0, t5_st=0, __retres1=1, E_2=2, E_4=2, T1_E=2, tmp_ndt_1=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, T5_E=2, t2_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3a92a885=0, T4_E=2, t3_i=1, t4_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@9649dec=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7a78f279=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@22cea100=0, t1_st=0, tmp_ndt_5=0, t5_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@50550485=0, local=0, t2_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6d83d876=0, tmp___3=0, E_M=2, tmp___1=0, T3_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@22750e0e=0, t1_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@f5232e=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2d4bd35b=0, \result=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@73371db6=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 484]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int t4_pc = 0; [L19] int t5_pc = 0; [L20] int m_st ; [L21] int t1_st ; [L22] int t2_st ; [L23] int t3_st ; [L24] int t4_st ; [L25] int t5_st ; [L26] int m_i ; [L27] int t1_i ; [L28] int t2_i ; [L29] int t3_i ; [L30] int t4_i ; [L31] int t5_i ; [L32] int M_E = 2; [L33] int T1_E = 2; [L34] int T2_E = 2; [L35] int T3_E = 2; [L36] int T4_E = 2; [L37] int T5_E = 2; [L38] int E_M = 2; [L39] int E_1 = 2; [L40] int E_2 = 2; [L41] int E_3 = 2; [L42] int E_4 = 2; [L43] int E_5 = 2; [L51] int token ; [L53] int local ; [L963] int __retres1 ; [L967] CALL init_model() [L874] m_i = 1 [L875] t1_i = 1 [L876] t2_i = 1 [L877] t3_i = 1 [L878] t4_i = 1 [L879] RET t5_i = 1 [L967] init_model() [L968] CALL start_simulation() [L904] int kernel_st ; [L905] int tmp ; [L906] int tmp___0 ; [L910] kernel_st = 0 [L911] FCALL update_channels() [L912] CALL init_threads() [L404] COND TRUE m_i == 1 [L405] m_st = 0 [L409] COND TRUE t1_i == 1 [L410] t1_st = 0 [L414] COND TRUE t2_i == 1 [L415] t2_st = 0 [L419] COND TRUE t3_i == 1 [L420] t3_st = 0 [L424] COND TRUE t4_i == 1 [L425] t4_st = 0 [L429] COND TRUE t5_i == 1 [L430] RET t5_st = 0 [L912] init_threads() [L913] CALL fire_delta_events() [L589] COND FALSE !(M_E == 0) [L594] COND FALSE !(T1_E == 0) [L599] COND FALSE !(T2_E == 0) [L604] COND FALSE !(T3_E == 0) [L609] COND FALSE !(T4_E == 0) [L614] COND FALSE !(T5_E == 0) [L619] COND FALSE !(E_M == 0) [L624] COND FALSE !(E_1 == 0) [L629] COND FALSE !(E_2 == 0) [L634] COND FALSE !(E_3 == 0) [L639] COND FALSE !(E_4 == 0) [L644] COND FALSE, RET !(E_5 == 0) [L913] fire_delta_events() [L914] CALL activate_threads() [L722] int tmp ; [L723] int tmp___0 ; [L724] int tmp___1 ; [L725] int tmp___2 ; [L726] int tmp___3 ; [L727] int tmp___4 ; [L731] CALL, EXPR is_master_triggered() [L279] int __retres1 ; [L282] COND FALSE !(m_pc == 1) [L292] __retres1 = 0 [L294] RET return (__retres1); [L731] EXPR is_master_triggered() [L731] tmp = is_master_triggered() [L733] COND FALSE !(\read(tmp)) [L739] CALL, EXPR is_transmit1_triggered() [L298] int __retres1 ; [L301] COND FALSE !(t1_pc == 1) [L311] __retres1 = 0 [L313] RET return (__retres1); [L739] EXPR is_transmit1_triggered() [L739] tmp___0 = is_transmit1_triggered() [L741] COND FALSE !(\read(tmp___0)) [L747] CALL, EXPR is_transmit2_triggered() [L317] int __retres1 ; [L320] COND FALSE !(t2_pc == 1) [L330] __retres1 = 0 [L332] RET return (__retres1); [L747] EXPR is_transmit2_triggered() [L747] tmp___1 = is_transmit2_triggered() [L749] COND FALSE !(\read(tmp___1)) [L755] CALL, EXPR is_transmit3_triggered() [L336] int __retres1 ; [L339] COND FALSE !(t3_pc == 1) [L349] __retres1 = 0 [L351] RET return (__retres1); [L755] EXPR is_transmit3_triggered() [L755] tmp___2 = is_transmit3_triggered() [L757] COND FALSE !(\read(tmp___2)) [L763] CALL, EXPR is_transmit4_triggered() [L355] int __retres1 ; [L358] COND FALSE !(t4_pc == 1) [L368] __retres1 = 0 [L370] RET return (__retres1); [L763] EXPR is_transmit4_triggered() [L763] tmp___3 = is_transmit4_triggered() [L765] COND FALSE !(\read(tmp___3)) [L771] CALL, EXPR is_transmit5_triggered() [L374] int __retres1 ; [L377] COND FALSE !(t5_pc == 1) [L387] __retres1 = 0 [L389] RET return (__retres1); [L771] EXPR is_transmit5_triggered() [L771] tmp___4 = is_transmit5_triggered() [L773] COND FALSE, RET !(\read(tmp___4)) [L914] activate_threads() [L915] CALL reset_delta_events() [L657] COND FALSE !(M_E == 1) [L662] COND FALSE !(T1_E == 1) [L667] COND FALSE !(T2_E == 1) [L672] COND FALSE !(T3_E == 1) [L677] COND FALSE !(T4_E == 1) [L682] COND FALSE !(T5_E == 1) [L687] COND FALSE !(E_M == 1) [L692] COND FALSE !(E_1 == 1) [L697] COND FALSE !(E_2 == 1) [L702] COND FALSE !(E_3 == 1) [L707] COND FALSE !(E_4 == 1) [L712] COND FALSE, RET !(E_5 == 1) [L915] reset_delta_events() [L918] COND TRUE 1 [L921] kernel_st = 1 [L922] CALL eval() [L480] int tmp ; Loop: [L484] COND TRUE 1 [L487] CALL, EXPR exists_runnable_thread() [L439] int __retres1 ; [L442] COND TRUE m_st == 0 [L443] __retres1 = 1 [L475] RET return (__retres1); [L487] EXPR exists_runnable_thread() [L487] tmp = exists_runnable_thread() [L489] COND TRUE \read(tmp) [L494] COND TRUE m_st == 0 [L495] int tmp_ndt_1; [L496] tmp_ndt_1 = __VERIFIER_nondet_int() [L497] COND FALSE !(\read(tmp_ndt_1)) [L508] COND TRUE t1_st == 0 [L509] int tmp_ndt_2; [L510] tmp_ndt_2 = __VERIFIER_nondet_int() [L511] COND FALSE !(\read(tmp_ndt_2)) [L522] COND TRUE t2_st == 0 [L523] int tmp_ndt_3; [L524] tmp_ndt_3 = __VERIFIER_nondet_int() [L525] COND FALSE !(\read(tmp_ndt_3)) [L536] COND TRUE t3_st == 0 [L537] int tmp_ndt_4; [L538] tmp_ndt_4 = __VERIFIER_nondet_int() [L539] COND FALSE !(\read(tmp_ndt_4)) [L550] COND TRUE t4_st == 0 [L551] int tmp_ndt_5; [L552] tmp_ndt_5 = __VERIFIER_nondet_int() [L553] COND FALSE !(\read(tmp_ndt_5)) [L564] COND TRUE t5_st == 0 [L565] int tmp_ndt_6; [L566] tmp_ndt_6 = __VERIFIER_nondet_int() [L567] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...