./Ultimate.py --spec ../../sv-benchmarks/c/Termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.06_true-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 1dbac8bc Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_5f1fc94c-9998-450d-a117-8df28255ba1f/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_5f1fc94c-9998-450d-a117-8df28255ba1f/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_5f1fc94c-9998-450d-a117-8df28255ba1f/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_5f1fc94c-9998-450d-a117-8df28255ba1f/bin-2019/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.06_true-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_5f1fc94c-9998-450d-a117-8df28255ba1f/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_5f1fc94c-9998-450d-a117-8df28255ba1f/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 1a4f705a2aeda6c2b85d5987770b408257af07ab ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.23-1dbac8b [2018-11-10 06:54:00,418 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-10 06:54:00,420 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-10 06:54:00,427 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-10 06:54:00,427 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-10 06:54:00,428 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-10 06:54:00,428 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-10 06:54:00,430 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-10 06:54:00,431 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-10 06:54:00,431 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-10 06:54:00,432 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-10 06:54:00,432 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-10 06:54:00,433 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-10 06:54:00,434 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-10 06:54:00,435 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-10 06:54:00,435 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-10 06:54:00,436 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-10 06:54:00,437 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-10 06:54:00,439 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-10 06:54:00,440 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-10 06:54:00,441 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-10 06:54:00,441 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-10 06:54:00,443 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-10 06:54:00,443 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-10 06:54:00,443 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-10 06:54:00,444 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-10 06:54:00,445 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-10 06:54:00,446 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-10 06:54:00,446 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-10 06:54:00,447 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-10 06:54:00,447 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-10 06:54:00,448 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-10 06:54:00,448 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-10 06:54:00,448 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-10 06:54:00,449 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-10 06:54:00,449 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-10 06:54:00,450 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_5f1fc94c-9998-450d-a117-8df28255ba1f/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2018-11-10 06:54:00,461 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-10 06:54:00,461 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-10 06:54:00,462 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-10 06:54:00,462 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-10 06:54:00,463 INFO L133 SettingsManager]: * Use SBE=true [2018-11-10 06:54:00,463 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2018-11-10 06:54:00,463 INFO L133 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2018-11-10 06:54:00,463 INFO L133 SettingsManager]: * Use old map elimination=false [2018-11-10 06:54:00,463 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false [2018-11-10 06:54:00,463 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true [2018-11-10 06:54:00,464 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2018-11-10 06:54:00,464 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-10 06:54:00,464 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-10 06:54:00,464 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-10 06:54:00,464 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-10 06:54:00,464 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-10 06:54:00,464 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-10 06:54:00,465 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2018-11-10 06:54:00,465 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2018-11-10 06:54:00,465 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2018-11-10 06:54:00,465 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-10 06:54:00,465 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-10 06:54:00,465 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false [2018-11-10 06:54:00,465 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2018-11-10 06:54:00,465 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-10 06:54:00,466 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-10 06:54:00,466 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2018-11-10 06:54:00,466 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-10 06:54:00,466 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-10 06:54:00,466 INFO L133 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2018-11-10 06:54:00,467 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-11-10 06:54:00,467 INFO L133 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_5f1fc94c-9998-450d-a117-8df28255ba1f/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 1a4f705a2aeda6c2b85d5987770b408257af07ab [2018-11-10 06:54:00,489 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-10 06:54:00,497 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-10 06:54:00,499 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-10 06:54:00,500 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-10 06:54:00,501 INFO L276 PluginConnector]: CDTParser initialized [2018-11-10 06:54:00,501 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_5f1fc94c-9998-450d-a117-8df28255ba1f/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/token_ring.06_true-unreach-call_false-termination.cil.c [2018-11-10 06:54:00,544 INFO L218 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_5f1fc94c-9998-450d-a117-8df28255ba1f/bin-2019/uautomizer/data/4e828022f/7edf61ca7aa14cf59492d2ad5233fc69/FLAGfd4812bb8 [2018-11-10 06:54:00,881 INFO L298 CDTParser]: Found 1 translation units. [2018-11-10 06:54:00,881 INFO L158 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_5f1fc94c-9998-450d-a117-8df28255ba1f/sv-benchmarks/c/systemc/token_ring.06_true-unreach-call_false-termination.cil.c [2018-11-10 06:54:00,887 INFO L346 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_5f1fc94c-9998-450d-a117-8df28255ba1f/bin-2019/uautomizer/data/4e828022f/7edf61ca7aa14cf59492d2ad5233fc69/FLAGfd4812bb8 [2018-11-10 06:54:00,896 INFO L354 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_5f1fc94c-9998-450d-a117-8df28255ba1f/bin-2019/uautomizer/data/4e828022f/7edf61ca7aa14cf59492d2ad5233fc69 [2018-11-10 06:54:00,897 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-10 06:54:00,898 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-10 06:54:00,899 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-10 06:54:00,899 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-10 06:54:00,901 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-10 06:54:00,902 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.11 06:54:00" (1/1) ... [2018-11-10 06:54:00,903 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@27d14c9b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 06:54:00, skipping insertion in model container [2018-11-10 06:54:00,903 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.11 06:54:00" (1/1) ... [2018-11-10 06:54:00,909 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-10 06:54:00,936 INFO L174 MainTranslator]: Built tables and reachable declarations [2018-11-10 06:54:01,075 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-11-10 06:54:01,079 INFO L189 MainTranslator]: Completed pre-run [2018-11-10 06:54:01,115 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-11-10 06:54:01,128 INFO L193 MainTranslator]: Completed translation [2018-11-10 06:54:01,128 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 06:54:01 WrapperNode [2018-11-10 06:54:01,128 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-10 06:54:01,129 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-10 06:54:01,129 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-10 06:54:01,129 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-10 06:54:01,137 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 06:54:01" (1/1) ... [2018-11-10 06:54:01,143 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 06:54:01" (1/1) ... [2018-11-10 06:54:01,192 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-10 06:54:01,193 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-10 06:54:01,193 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-10 06:54:01,193 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-10 06:54:01,259 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 06:54:01" (1/1) ... [2018-11-10 06:54:01,259 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 06:54:01" (1/1) ... [2018-11-10 06:54:01,265 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 06:54:01" (1/1) ... [2018-11-10 06:54:01,265 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 06:54:01" (1/1) ... [2018-11-10 06:54:01,280 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 06:54:01" (1/1) ... [2018-11-10 06:54:01,301 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 06:54:01" (1/1) ... [2018-11-10 06:54:01,305 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 06:54:01" (1/1) ... [2018-11-10 06:54:01,311 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-10 06:54:01,311 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-10 06:54:01,311 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-10 06:54:01,312 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-10 06:54:01,312 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 06:54:01" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_5f1fc94c-9998-450d-a117-8df28255ba1f/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-10 06:54:01,364 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-10 06:54:01,364 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-10 06:54:02,495 INFO L341 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-10 06:54:02,495 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.11 06:54:02 BoogieIcfgContainer [2018-11-10 06:54:02,496 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-10 06:54:02,496 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2018-11-10 06:54:02,496 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2018-11-10 06:54:02,499 INFO L276 PluginConnector]: BuchiAutomizer initialized [2018-11-10 06:54:02,500 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-10 06:54:02,500 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 10.11 06:54:00" (1/3) ... [2018-11-10 06:54:02,501 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1ffbff10 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 10.11 06:54:02, skipping insertion in model container [2018-11-10 06:54:02,501 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-10 06:54:02,501 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 06:54:01" (2/3) ... [2018-11-10 06:54:02,502 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1ffbff10 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 10.11 06:54:02, skipping insertion in model container [2018-11-10 06:54:02,502 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-10 06:54:02,502 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.11 06:54:02" (3/3) ... [2018-11-10 06:54:02,504 INFO L375 chiAutomizerObserver]: Analyzing ICFG token_ring.06_true-unreach-call_false-termination.cil.c [2018-11-10 06:54:02,548 INFO L135 ementStrategyFactory]: Using default assertion order modulation [2018-11-10 06:54:02,548 INFO L374 BuchiCegarLoop]: Interprodecural is true [2018-11-10 06:54:02,548 INFO L375 BuchiCegarLoop]: Hoare is false [2018-11-10 06:54:02,548 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2018-11-10 06:54:02,549 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-10 06:54:02,549 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-10 06:54:02,549 INFO L379 BuchiCegarLoop]: Difference is false [2018-11-10 06:54:02,549 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-10 06:54:02,549 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2018-11-10 06:54:02,574 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 696 states. [2018-11-10 06:54:02,612 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 601 [2018-11-10 06:54:02,613 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:54:02,613 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:54:02,623 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:02,623 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:02,623 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ [2018-11-10 06:54:02,623 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 696 states. [2018-11-10 06:54:02,632 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 601 [2018-11-10 06:54:02,632 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:54:02,632 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:54:02,638 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:02,638 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:02,645 INFO L793 eck$LassoCheckResult]: Stem: 496#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 382#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 25#L1006true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 606#L458true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 302#L465true assume !(~m_i~0 == 1);~m_st~0 := 2; 306#L465-2true assume ~t1_i~0 == 1;~t1_st~0 := 0; 683#L470-1true assume !(~t2_i~0 == 1);~t2_st~0 := 2; 201#L475-1true assume !(~t3_i~0 == 1);~t3_st~0 := 2; 608#L480-1true assume !(~t4_i~0 == 1);~t4_st~0 := 2; 251#L485-1true assume !(~t5_i~0 == 1);~t5_st~0 := 2; 78#L490-1true assume !(~t6_i~0 == 1);~t6_st~0 := 2; 511#L495-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 312#L674true assume !(~M_E~0 == 0); 319#L674-2true assume !(~T1_E~0 == 0); 692#L679-1true assume !(~T2_E~0 == 0); 215#L684-1true assume !(~T3_E~0 == 0); 614#L689-1true assume !(~T4_E~0 == 0); 477#L694-1true assume !(~T5_E~0 == 0); 101#L699-1true assume !(~T6_E~0 == 0); 542#L704-1true assume ~E_M~0 == 0;~E_M~0 := 1; 3#L709-1true assume !(~E_1~0 == 0); 427#L714-1true assume !(~E_2~0 == 0); 58#L719-1true assume !(~E_3~0 == 0); 634#L724-1true assume !(~E_4~0 == 0); 311#L729-1true assume !(~E_5~0 == 0); 688#L734-1true assume !(~E_6~0 == 0); 209#L739-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 128#L324true assume !(~m_pc~0 == 1); 138#L324-2true is_master_triggered_~__retres1~0 := 0; 164#L335true is_master_triggered_#res := is_master_triggered_~__retres1~0; 82#L336true activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 326#L839true assume !(activate_threads_~tmp~1 != 0); 329#L839-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 174#L343true assume ~t1_pc~0 == 1; 282#L344true assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 172#L354true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 281#L355true activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 550#L847true assume !(activate_threads_~tmp___0~0 != 0); 535#L847-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 425#L362true assume !(~t2_pc~0 == 1); 390#L362-2true is_transmit2_triggered_~__retres1~2 := 0; 423#L373true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 516#L374true activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 553#L855true assume !(activate_threads_~tmp___1~0 != 0); 556#L855-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 582#L381true assume ~t3_pc~0 == 1; 662#L382true assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 580#L392true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 660#L393true activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 32#L863true assume !(activate_threads_~tmp___2~0 != 0); 16#L863-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 55#L400true assume ~t4_pc~0 == 1; 157#L401true assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 54#L411true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 156#L412true activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 224#L871true assume !(activate_threads_~tmp___3~0 != 0); 228#L871-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 253#L419true assume !(~t5_pc~0 == 1); 256#L419-2true is_transmit5_triggered_~__retres1~5 := 0; 252#L430true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 203#L431true activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 453#L879true assume activate_threads_~tmp___4~0 != 0;~t5_st~0 := 0; 440#L879-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 629#L438true assume ~t6_pc~0 == 1; 417#L439true assume ~E_6~0 == 1;is_transmit6_triggered_~__retres1~6 := 1; 628#L449true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 415#L450true activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 618#L887true assume !(activate_threads_~tmp___5~0 != 0); 620#L887-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 66#L752true assume !(~M_E~0 == 1); 59#L752-2true assume !(~T1_E~0 == 1); 632#L757-1true assume !(~T2_E~0 == 1); 308#L762-1true assume ~T3_E~0 == 1;~T3_E~0 := 2; 686#L767-1true assume !(~T4_E~0 == 1); 207#L772-1true assume !(~T5_E~0 == 1); 610#L777-1true assume !(~T6_E~0 == 1); 475#L782-1true assume !(~E_M~0 == 1); 97#L787-1true assume !(~E_1~0 == 1); 536#L792-1true assume !(~E_2~0 == 1); 17#L797-1true assume !(~E_3~0 == 1); 443#L802-1true assume ~E_4~0 == 1;~E_4~0 := 2; 65#L807-1true assume !(~E_5~0 == 1); 639#L812-1true assume !(~E_6~0 == 1); 328#L817-1true assume { :end_inline_reset_delta_events } true; 643#L1043-3true [2018-11-10 06:54:02,647 INFO L795 eck$LassoCheckResult]: Loop: 643#L1043-3true assume true; 641#L1043-1true assume !false; 448#L1044true start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 521#L649true assume !true; 60#L664true assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 578#L458-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 321#L674-3true assume ~M_E~0 == 0;~M_E~0 := 1; 296#L674-5true assume ~T1_E~0 == 0;~T1_E~0 := 1; 676#L679-3true assume !(~T2_E~0 == 0); 189#L684-3true assume ~T3_E~0 == 0;~T3_E~0 := 1; 595#L689-3true assume ~T4_E~0 == 0;~T4_E~0 := 1; 260#L694-3true assume ~T5_E~0 == 0;~T5_E~0 := 1; 86#L699-3true assume ~T6_E~0 == 0;~T6_E~0 := 1; 525#L704-3true assume ~E_M~0 == 0;~E_M~0 := 1; 9#L709-3true assume ~E_1~0 == 0;~E_1~0 := 1; 430#L714-3true assume ~E_2~0 == 0;~E_2~0 := 1; 62#L719-3true assume !(~E_3~0 == 0); 637#L724-3true assume ~E_4~0 == 0;~E_4~0 := 1; 318#L729-3true assume ~E_5~0 == 0;~E_5~0 := 1; 695#L734-3true assume ~E_6~0 == 0;~E_6~0 := 1; 217#L739-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 89#L324-24true assume ~m_pc~0 == 1; 625#L325-8true assume ~E_M~0 == 1;is_master_triggered_~__retres1~0 := 1; 121#L335-8true is_master_triggered_#res := is_master_triggered_~__retres1~0; 623#L336-8true activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 278#L839-24true assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 261#L839-26true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 323#L343-24true assume ~t1_pc~0 == 1; 276#L344-8true assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 361#L354-8true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 274#L355-8true activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 489#L847-24true assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 491#L847-26true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 526#L362-24true assume !(~t2_pc~0 == 1); 530#L362-26true is_transmit2_triggered_~__retres1~2 := 0; 372#L373-8true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 483#L374-8true activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 659#L855-24true assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 640#L855-26true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 697#L381-24true assume !(~t3_pc~0 == 1); 678#L381-26true is_transmit3_triggered_~__retres1~3 := 0; 573#L392-8true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 654#L393-8true activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 122#L863-24true assume !(activate_threads_~tmp___2~0 != 0); 127#L863-26true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6#L400-24true assume ~t4_pc~0 == 1; 115#L401-8true assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 36#L411-8true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 113#L412-8true activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 364#L871-24true assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 335#L871-26true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 216#L419-24true assume ~t5_pc~0 == 1; 355#L420-8true assume ~E_5~0 == 1;is_transmit5_triggered_~__retres1~5 := 1; 244#L430-8true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 353#L431-8true activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 376#L879-24true assume activate_threads_~tmp___4~0 != 0;~t5_st~0 := 0; 380#L879-26true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 429#L438-24true assume !(~t6_pc~0 == 1); 432#L438-26true is_transmit6_triggered_~__retres1~6 := 0; 454#L449-8true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 407#L450-8true activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 576#L887-24true assume activate_threads_~tmp___5~0 != 0;~t6_st~0 := 0; 559#L887-26true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 61#L752-3true assume ~M_E~0 == 1;~M_E~0 := 2; 63#L752-5true assume ~T1_E~0 == 1;~T1_E~0 := 2; 635#L757-3true assume ~T2_E~0 == 1;~T2_E~0 := 2; 315#L762-3true assume ~T3_E~0 == 1;~T3_E~0 := 2; 690#L767-3true assume ~T4_E~0 == 1;~T4_E~0 := 2; 214#L772-3true assume ~T5_E~0 == 1;~T5_E~0 := 2; 613#L777-3true assume !(~T6_E~0 == 1); 476#L782-3true assume ~E_M~0 == 1;~E_M~0 := 2; 100#L787-3true assume ~E_1~0 == 1;~E_1~0 := 2; 540#L792-3true assume ~E_2~0 == 1;~E_2~0 := 2; 22#L797-3true assume ~E_3~0 == 1;~E_3~0 := 2; 447#L802-3true assume ~E_4~0 == 1;~E_4~0 := 2; 57#L807-3true assume ~E_5~0 == 1;~E_5~0 := 2; 633#L812-3true assume ~E_6~0 == 1;~E_6~0 := 2; 309#L817-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 200#L508-1true assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 92#L545-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 602#L546-1true start_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 126#L1062true assume !(start_simulation_~tmp~3 == 0); 105#L1062-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 202#L508-2true assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 95#L545-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 605#L546-2true stop_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 24#L1017true assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 492#L1024true stop_simulation_#res := stop_simulation_~__retres2~0; 237#L1025true start_simulation_#t~ret18 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 558#L1075true assume !(start_simulation_~tmp___0~1 != 0); 643#L1043-3true [2018-11-10 06:54:02,652 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:02,653 INFO L82 PathProgramCache]: Analyzing trace with hash -376834623, now seen corresponding path program 1 times [2018-11-10 06:54:02,655 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:02,655 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:02,688 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:02,689 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:02,689 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:02,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:02,781 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:02,783 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:02,783 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:54:02,786 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 06:54:02,786 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:02,786 INFO L82 PathProgramCache]: Analyzing trace with hash -756512174, now seen corresponding path program 1 times [2018-11-10 06:54:02,786 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:02,787 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:02,787 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:02,788 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:02,788 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:02,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:02,808 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:02,808 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:02,808 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 06:54:02,809 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 06:54:02,819 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 06:54:02,819 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 06:54:02,821 INFO L87 Difference]: Start difference. First operand 696 states. Second operand 3 states. [2018-11-10 06:54:02,871 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:54:02,871 INFO L93 Difference]: Finished difference Result 695 states and 1033 transitions. [2018-11-10 06:54:02,872 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 06:54:02,874 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 695 states and 1033 transitions. [2018-11-10 06:54:02,878 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 599 [2018-11-10 06:54:02,886 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 695 states to 690 states and 1028 transitions. [2018-11-10 06:54:02,887 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 690 [2018-11-10 06:54:02,888 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 690 [2018-11-10 06:54:02,888 INFO L73 IsDeterministic]: Start isDeterministic. Operand 690 states and 1028 transitions. [2018-11-10 06:54:02,891 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:54:02,892 INFO L705 BuchiCegarLoop]: Abstraction has 690 states and 1028 transitions. [2018-11-10 06:54:02,905 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 690 states and 1028 transitions. [2018-11-10 06:54:02,930 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 690 to 690. [2018-11-10 06:54:02,931 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 690 states. [2018-11-10 06:54:02,933 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 690 states to 690 states and 1028 transitions. [2018-11-10 06:54:02,934 INFO L728 BuchiCegarLoop]: Abstraction has 690 states and 1028 transitions. [2018-11-10 06:54:02,934 INFO L608 BuchiCegarLoop]: Abstraction has 690 states and 1028 transitions. [2018-11-10 06:54:02,934 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ [2018-11-10 06:54:02,934 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 690 states and 1028 transitions. [2018-11-10 06:54:02,936 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 599 [2018-11-10 06:54:02,937 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:54:02,937 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:54:02,938 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:02,939 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:02,940 INFO L793 eck$LassoCheckResult]: Stem: 1987#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1880#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1446#L1006 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 1447#L458 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1813#L465 assume ~m_i~0 == 1;~m_st~0 := 0; 1814#L465-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 1817#L470-1 assume !(~t2_i~0 == 1);~t2_st~0 := 2; 1690#L475-1 assume !(~t3_i~0 == 1);~t3_st~0 := 2; 1691#L480-1 assume !(~t4_i~0 == 1);~t4_st~0 := 2; 1746#L485-1 assume !(~t5_i~0 == 1);~t5_st~0 := 2; 1545#L490-1 assume !(~t6_i~0 == 1);~t6_st~0 := 2; 1546#L495-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1824#L674 assume !(~M_E~0 == 0); 1825#L674-2 assume !(~T1_E~0 == 0); 1833#L679-1 assume !(~T2_E~0 == 0); 1712#L684-1 assume !(~T3_E~0 == 0); 1713#L689-1 assume !(~T4_E~0 == 0); 1967#L694-1 assume !(~T5_E~0 == 0); 1580#L699-1 assume !(~T6_E~0 == 0); 1581#L704-1 assume ~E_M~0 == 0;~E_M~0 := 1; 1400#L709-1 assume !(~E_1~0 == 0); 1401#L714-1 assume !(~E_2~0 == 0); 1497#L719-1 assume !(~E_3~0 == 0); 1498#L724-1 assume !(~E_4~0 == 0); 1822#L729-1 assume !(~E_5~0 == 0); 1823#L734-1 assume !(~E_6~0 == 0); 1705#L739-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1604#L324 assume !(~m_pc~0 == 1); 1553#L324-2 is_master_triggered_~__retres1~0 := 0; 1554#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1550#L336 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1551#L839 assume !(activate_threads_~tmp~1 != 0); 1836#L839-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1644#L343 assume ~t1_pc~0 == 1; 1645#L344 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 1642#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1643#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1791#L847 assume !(activate_threads_~tmp___0~0 != 0); 2010#L847-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1947#L362 assume !(~t2_pc~0 == 1); 1891#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 1892#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1946#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2005#L855 assume !(activate_threads_~tmp___1~0 != 0); 2016#L855-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2021#L381 assume ~t3_pc~0 == 1; 2055#L382 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 2053#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2054#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1462#L863 assume !(activate_threads_~tmp___2~0 != 0); 1429#L863-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1430#L400 assume ~t4_pc~0 == 1; 1493#L401 assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 1476#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1492#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1620#L871 assume !(activate_threads_~tmp___3~0 != 0); 1723#L871-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1729#L419 assume !(~t5_pc~0 == 1); 1628#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 1627#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1692#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1693#L879 assume activate_threads_~tmp___4~0 != 0;~t5_st~0 := 0; 1958#L879-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1959#L438 assume ~t6_pc~0 == 1; 1932#L439 assume ~E_6~0 == 1;is_transmit6_triggered_~__retres1~6 := 1; 1933#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1930#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1931#L887 assume !(activate_threads_~tmp___5~0 != 0); 2070#L887-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1513#L752 assume !(~M_E~0 == 1); 1499#L752-2 assume !(~T1_E~0 == 1); 1500#L757-1 assume !(~T2_E~0 == 1); 1819#L762-1 assume ~T3_E~0 == 1;~T3_E~0 := 2; 1820#L767-1 assume !(~T4_E~0 == 1); 1701#L772-1 assume !(~T5_E~0 == 1); 1702#L777-1 assume !(~T6_E~0 == 1); 1965#L782-1 assume !(~E_M~0 == 1); 1575#L787-1 assume !(~E_1~0 == 1); 1576#L792-1 assume !(~E_2~0 == 1); 1434#L797-1 assume !(~E_3~0 == 1); 1435#L802-1 assume ~E_4~0 == 1;~E_4~0 := 2; 1511#L807-1 assume !(~E_5~0 == 1); 1512#L812-1 assume !(~E_6~0 == 1); 1837#L817-1 assume { :end_inline_reset_delta_events } true; 1838#L1043-3 [2018-11-10 06:54:02,941 INFO L795 eck$LassoCheckResult]: Loop: 1838#L1043-3 assume true; 2073#L1043-1 assume !false; 1962#L1044 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 1607#L649 assume true; 1424#L555-1 assume !false; 1425#L556 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 1563#L508 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 1486#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 1567#L546 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 1955#L560 assume !(eval_~tmp~0 != 0); 1501#L664 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 1502#L458-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 1834#L674-3 assume ~M_E~0 == 0;~M_E~0 := 1; 1808#L674-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 1809#L679-3 assume !(~T2_E~0 == 0); 1677#L684-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 1678#L689-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 1747#L694-3 assume ~T5_E~0 == 0;~T5_E~0 := 1; 1559#L699-3 assume ~T6_E~0 == 0;~T6_E~0 := 1; 1560#L704-3 assume ~E_M~0 == 0;~E_M~0 := 1; 1415#L709-3 assume ~E_1~0 == 0;~E_1~0 := 1; 1416#L714-3 assume ~E_2~0 == 0;~E_2~0 := 1; 1505#L719-3 assume !(~E_3~0 == 0); 1506#L724-3 assume ~E_4~0 == 0;~E_4~0 := 1; 1831#L729-3 assume ~E_5~0 == 0;~E_5~0 := 1; 1832#L734-3 assume ~E_6~0 == 0;~E_6~0 := 1; 1714#L739-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1564#L324-24 assume !(~m_pc~0 == 1); 1565#L324-26 is_master_triggered_~__retres1~0 := 0; 1571#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1600#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1788#L839-24 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 1748#L839-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1749#L343-24 assume ~t1_pc~0 == 1; 1779#L344-8 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 1780#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1777#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1778#L847-24 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 1982#L847-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1983#L362-24 assume ~t2_pc~0 == 1; 1975#L363-8 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 1863#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1864#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1974#L855-24 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 2071#L855-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2072#L381-24 assume ~t3_pc~0 == 1; 2080#L382-8 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 2046#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2047#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1598#L863-24 assume !(activate_threads_~tmp___2~0 != 0); 1599#L863-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1406#L400-24 assume !(~t4_pc~0 == 1); 1408#L400-26 is_transmit4_triggered_~__retres1~4 := 0; 1420#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1465#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1593#L871-24 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 1839#L871-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1710#L419-24 assume !(~t5_pc~0 == 1); 1675#L419-26 is_transmit5_triggered_~__retres1~5 := 0; 1676#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1740#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1846#L879-24 assume activate_threads_~tmp___4~0 != 0;~t5_st~0 := 0; 1867#L879-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1875#L438-24 assume ~t6_pc~0 == 1; 1924#L439-8 assume ~E_6~0 == 1;is_transmit6_triggered_~__retres1~6 := 1; 1925#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1920#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1921#L887-24 assume activate_threads_~tmp___5~0 != 0;~t6_st~0 := 0; 2025#L887-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1503#L752-3 assume ~M_E~0 == 1;~M_E~0 := 2; 1504#L752-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 1507#L757-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 1827#L762-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 1828#L767-3 assume ~T4_E~0 == 1;~T4_E~0 := 2; 1708#L772-3 assume ~T5_E~0 == 1;~T5_E~0 := 2; 1709#L777-3 assume !(~T6_E~0 == 1); 1966#L782-3 assume ~E_M~0 == 1;~E_M~0 := 2; 1578#L787-3 assume ~E_1~0 == 1;~E_1~0 := 2; 1579#L792-3 assume ~E_2~0 == 1;~E_2~0 := 2; 1439#L797-3 assume ~E_3~0 == 1;~E_3~0 := 2; 1440#L802-3 assume ~E_4~0 == 1;~E_4~0 := 2; 1495#L807-3 assume ~E_5~0 == 1;~E_5~0 := 2; 1496#L812-3 assume ~E_6~0 == 1;~E_6~0 := 2; 1821#L817-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 1689#L508-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 1489#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 1568#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 1602#L1062 assume !(start_simulation_~tmp~3 == 0); 1585#L1062-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 1586#L508-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 1491#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 1574#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 1444#L1017 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 1445#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 1736#L1025 start_simulation_#t~ret18 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 1737#L1075 assume !(start_simulation_~tmp___0~1 != 0); 1838#L1043-3 [2018-11-10 06:54:02,941 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:02,941 INFO L82 PathProgramCache]: Analyzing trace with hash 765667843, now seen corresponding path program 1 times [2018-11-10 06:54:02,941 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:02,941 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:02,942 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:02,942 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:02,942 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:02,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:02,989 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:02,989 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:02,989 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:54:02,989 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 06:54:02,990 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:02,990 INFO L82 PathProgramCache]: Analyzing trace with hash 582958304, now seen corresponding path program 1 times [2018-11-10 06:54:02,990 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:02,990 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:02,991 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:02,991 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:02,991 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:03,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:03,060 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:03,060 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:03,061 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:54:03,061 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 06:54:03,061 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 06:54:03,061 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 06:54:03,062 INFO L87 Difference]: Start difference. First operand 690 states and 1028 transitions. cyclomatic complexity: 339 Second operand 3 states. [2018-11-10 06:54:03,087 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:54:03,087 INFO L93 Difference]: Finished difference Result 690 states and 1027 transitions. [2018-11-10 06:54:03,088 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 06:54:03,088 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 690 states and 1027 transitions. [2018-11-10 06:54:03,093 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 599 [2018-11-10 06:54:03,097 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 690 states to 690 states and 1027 transitions. [2018-11-10 06:54:03,097 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 690 [2018-11-10 06:54:03,098 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 690 [2018-11-10 06:54:03,098 INFO L73 IsDeterministic]: Start isDeterministic. Operand 690 states and 1027 transitions. [2018-11-10 06:54:03,099 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:54:03,099 INFO L705 BuchiCegarLoop]: Abstraction has 690 states and 1027 transitions. [2018-11-10 06:54:03,100 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 690 states and 1027 transitions. [2018-11-10 06:54:03,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 690 to 690. [2018-11-10 06:54:03,110 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 690 states. [2018-11-10 06:54:03,112 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 690 states to 690 states and 1027 transitions. [2018-11-10 06:54:03,112 INFO L728 BuchiCegarLoop]: Abstraction has 690 states and 1027 transitions. [2018-11-10 06:54:03,113 INFO L608 BuchiCegarLoop]: Abstraction has 690 states and 1027 transitions. [2018-11-10 06:54:03,113 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ [2018-11-10 06:54:03,113 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 690 states and 1027 transitions. [2018-11-10 06:54:03,116 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 599 [2018-11-10 06:54:03,116 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:54:03,116 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:54:03,118 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:03,118 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:03,119 INFO L793 eck$LassoCheckResult]: Stem: 3374#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 3264#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 2833#L1006 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 2834#L458 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3200#L465 assume ~m_i~0 == 1;~m_st~0 := 0; 3201#L465-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 3204#L470-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 3077#L475-1 assume !(~t3_i~0 == 1);~t3_st~0 := 2; 3078#L480-1 assume !(~t4_i~0 == 1);~t4_st~0 := 2; 3133#L485-1 assume !(~t5_i~0 == 1);~t5_st~0 := 2; 2929#L490-1 assume !(~t6_i~0 == 1);~t6_st~0 := 2; 2930#L495-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3211#L674 assume !(~M_E~0 == 0); 3212#L674-2 assume !(~T1_E~0 == 0); 3220#L679-1 assume !(~T2_E~0 == 0); 3097#L684-1 assume !(~T3_E~0 == 0); 3098#L689-1 assume !(~T4_E~0 == 0); 3354#L694-1 assume !(~T5_E~0 == 0); 2967#L699-1 assume !(~T6_E~0 == 0); 2968#L704-1 assume ~E_M~0 == 0;~E_M~0 := 1; 2787#L709-1 assume !(~E_1~0 == 0); 2788#L714-1 assume !(~E_2~0 == 0); 2884#L719-1 assume !(~E_3~0 == 0); 2885#L724-1 assume !(~E_4~0 == 0); 3209#L729-1 assume !(~E_5~0 == 0); 3210#L734-1 assume !(~E_6~0 == 0); 3090#L739-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2991#L324 assume !(~m_pc~0 == 1); 2940#L324-2 is_master_triggered_~__retres1~0 := 0; 2941#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2937#L336 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2938#L839 assume !(activate_threads_~tmp~1 != 0); 3223#L839-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3031#L343 assume ~t1_pc~0 == 1; 3032#L344 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 3026#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3027#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3178#L847 assume !(activate_threads_~tmp___0~0 != 0); 3397#L847-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3334#L362 assume !(~t2_pc~0 == 1); 3278#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 3279#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3330#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3392#L855 assume !(activate_threads_~tmp___1~0 != 0); 3403#L855-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3408#L381 assume ~t3_pc~0 == 1; 3442#L382 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 3439#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3440#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2848#L863 assume !(activate_threads_~tmp___2~0 != 0); 2816#L863-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2817#L400 assume ~t4_pc~0 == 1; 2880#L401 assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 2863#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2879#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3007#L871 assume !(activate_threads_~tmp___3~0 != 0); 3108#L871-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3115#L419 assume !(~t5_pc~0 == 1); 3015#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 3014#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3079#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3080#L879 assume activate_threads_~tmp___4~0 != 0;~t5_st~0 := 0; 3345#L879-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 3346#L438 assume ~t6_pc~0 == 1; 3319#L439 assume ~E_6~0 == 1;is_transmit6_triggered_~__retres1~6 := 1; 3320#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 3317#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3318#L887 assume !(activate_threads_~tmp___5~0 != 0); 3457#L887-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2900#L752 assume !(~M_E~0 == 1); 2886#L752-2 assume !(~T1_E~0 == 1); 2887#L757-1 assume !(~T2_E~0 == 1); 3206#L762-1 assume ~T3_E~0 == 1;~T3_E~0 := 2; 3207#L767-1 assume !(~T4_E~0 == 1); 3087#L772-1 assume !(~T5_E~0 == 1); 3088#L777-1 assume !(~T6_E~0 == 1); 3352#L782-1 assume !(~E_M~0 == 1); 2962#L787-1 assume !(~E_1~0 == 1); 2963#L792-1 assume !(~E_2~0 == 1); 2818#L797-1 assume !(~E_3~0 == 1); 2819#L802-1 assume ~E_4~0 == 1;~E_4~0 := 2; 2898#L807-1 assume !(~E_5~0 == 1); 2899#L812-1 assume !(~E_6~0 == 1); 3224#L817-1 assume { :end_inline_reset_delta_events } true; 3225#L1043-3 [2018-11-10 06:54:03,119 INFO L795 eck$LassoCheckResult]: Loop: 3225#L1043-3 assume true; 3460#L1043-1 assume !false; 3349#L1044 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 2993#L649 assume true; 2811#L555-1 assume !false; 2812#L556 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 2950#L508 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 2873#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 2954#L546 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 3342#L560 assume !(eval_~tmp~0 != 0); 2888#L664 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 2889#L458-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 3221#L674-3 assume ~M_E~0 == 0;~M_E~0 := 1; 3195#L674-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 3196#L679-3 assume !(~T2_E~0 == 0); 3062#L684-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 3063#L689-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 3134#L694-3 assume ~T5_E~0 == 0;~T5_E~0 := 1; 2946#L699-3 assume ~T6_E~0 == 0;~T6_E~0 := 1; 2947#L704-3 assume ~E_M~0 == 0;~E_M~0 := 1; 2802#L709-3 assume ~E_1~0 == 0;~E_1~0 := 1; 2803#L714-3 assume ~E_2~0 == 0;~E_2~0 := 1; 2892#L719-3 assume !(~E_3~0 == 0); 2893#L724-3 assume ~E_4~0 == 0;~E_4~0 := 1; 3218#L729-3 assume ~E_5~0 == 0;~E_5~0 := 1; 3219#L734-3 assume ~E_6~0 == 0;~E_6~0 := 1; 3101#L739-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2951#L324-24 assume !(~m_pc~0 == 1); 2952#L324-26 is_master_triggered_~__retres1~0 := 0; 2958#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2985#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3172#L839-24 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 3135#L839-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3136#L343-24 assume !(~t1_pc~0 == 1); 3169#L343-26 is_transmit1_triggered_~__retres1~1 := 0; 3168#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3164#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3165#L847-24 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 3369#L847-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3370#L362-24 assume ~t2_pc~0 == 1; 3362#L363-8 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 3250#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3251#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3361#L855-24 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 3458#L855-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3459#L381-24 assume ~t3_pc~0 == 1; 3467#L382-8 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 3433#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3434#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2986#L863-24 assume !(activate_threads_~tmp___2~0 != 0); 2987#L863-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2793#L400-24 assume ~t4_pc~0 == 1; 2794#L401-8 assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 2807#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2852#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2980#L871-24 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 3226#L871-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3099#L419-24 assume !(~t5_pc~0 == 1); 3064#L419-26 is_transmit5_triggered_~__retres1~5 := 0; 3065#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3127#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3233#L879-24 assume activate_threads_~tmp___4~0 != 0;~t5_st~0 := 0; 3255#L879-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 3262#L438-24 assume !(~t6_pc~0 == 1); 3313#L438-26 is_transmit6_triggered_~__retres1~6 := 0; 3312#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 3307#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3308#L887-24 assume activate_threads_~tmp___5~0 != 0;~t6_st~0 := 0; 3412#L887-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2890#L752-3 assume ~M_E~0 == 1;~M_E~0 := 2; 2891#L752-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 2894#L757-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 3214#L762-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 3215#L767-3 assume ~T4_E~0 == 1;~T4_E~0 := 2; 3095#L772-3 assume ~T5_E~0 == 1;~T5_E~0 := 2; 3096#L777-3 assume !(~T6_E~0 == 1); 3353#L782-3 assume ~E_M~0 == 1;~E_M~0 := 2; 2965#L787-3 assume ~E_1~0 == 1;~E_1~0 := 2; 2966#L792-3 assume ~E_2~0 == 1;~E_2~0 := 2; 2826#L797-3 assume ~E_3~0 == 1;~E_3~0 := 2; 2827#L802-3 assume ~E_4~0 == 1;~E_4~0 := 2; 2882#L807-3 assume ~E_5~0 == 1;~E_5~0 := 2; 2883#L812-3 assume ~E_6~0 == 1;~E_6~0 := 2; 3208#L817-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 3076#L508-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 2876#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 2957#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 2989#L1062 assume !(start_simulation_~tmp~3 == 0); 2972#L1062-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 2973#L508-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 2878#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 2961#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 2831#L1017 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 2832#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 3123#L1025 start_simulation_#t~ret18 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 3124#L1075 assume !(start_simulation_~tmp___0~1 != 0); 3225#L1043-3 [2018-11-10 06:54:03,119 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:03,120 INFO L82 PathProgramCache]: Analyzing trace with hash -73365819, now seen corresponding path program 1 times [2018-11-10 06:54:03,120 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:03,120 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:03,121 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:03,121 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:03,121 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:03,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:03,143 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:03,143 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:03,144 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:54:03,144 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 06:54:03,144 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:03,144 INFO L82 PathProgramCache]: Analyzing trace with hash 456806881, now seen corresponding path program 1 times [2018-11-10 06:54:03,144 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:03,144 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:03,145 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:03,145 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:03,145 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:03,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:03,205 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:03,205 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:03,205 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:54:03,206 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 06:54:03,206 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 06:54:03,206 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 06:54:03,206 INFO L87 Difference]: Start difference. First operand 690 states and 1027 transitions. cyclomatic complexity: 338 Second operand 3 states. [2018-11-10 06:54:03,220 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:54:03,220 INFO L93 Difference]: Finished difference Result 690 states and 1026 transitions. [2018-11-10 06:54:03,221 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 06:54:03,221 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 690 states and 1026 transitions. [2018-11-10 06:54:03,224 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 599 [2018-11-10 06:54:03,227 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 690 states to 690 states and 1026 transitions. [2018-11-10 06:54:03,228 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 690 [2018-11-10 06:54:03,228 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 690 [2018-11-10 06:54:03,228 INFO L73 IsDeterministic]: Start isDeterministic. Operand 690 states and 1026 transitions. [2018-11-10 06:54:03,230 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:54:03,230 INFO L705 BuchiCegarLoop]: Abstraction has 690 states and 1026 transitions. [2018-11-10 06:54:03,231 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 690 states and 1026 transitions. [2018-11-10 06:54:03,238 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 690 to 690. [2018-11-10 06:54:03,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 690 states. [2018-11-10 06:54:03,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 690 states to 690 states and 1026 transitions. [2018-11-10 06:54:03,240 INFO L728 BuchiCegarLoop]: Abstraction has 690 states and 1026 transitions. [2018-11-10 06:54:03,240 INFO L608 BuchiCegarLoop]: Abstraction has 690 states and 1026 transitions. [2018-11-10 06:54:03,241 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ [2018-11-10 06:54:03,241 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 690 states and 1026 transitions. [2018-11-10 06:54:03,243 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 599 [2018-11-10 06:54:03,243 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:54:03,244 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:54:03,245 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:03,245 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:03,245 INFO L793 eck$LassoCheckResult]: Stem: 4761#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 4651#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 4220#L1006 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 4221#L458 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4587#L465 assume ~m_i~0 == 1;~m_st~0 := 0; 4588#L465-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 4591#L470-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 4464#L475-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 4465#L480-1 assume !(~t4_i~0 == 1);~t4_st~0 := 2; 4520#L485-1 assume !(~t5_i~0 == 1);~t5_st~0 := 2; 4319#L490-1 assume !(~t6_i~0 == 1);~t6_st~0 := 2; 4320#L495-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4598#L674 assume !(~M_E~0 == 0); 4599#L674-2 assume !(~T1_E~0 == 0); 4607#L679-1 assume !(~T2_E~0 == 0); 4484#L684-1 assume !(~T3_E~0 == 0); 4485#L689-1 assume !(~T4_E~0 == 0); 4741#L694-1 assume !(~T5_E~0 == 0); 4354#L699-1 assume !(~T6_E~0 == 0); 4355#L704-1 assume ~E_M~0 == 0;~E_M~0 := 1; 4174#L709-1 assume !(~E_1~0 == 0); 4175#L714-1 assume !(~E_2~0 == 0); 4271#L719-1 assume !(~E_3~0 == 0); 4272#L724-1 assume !(~E_4~0 == 0); 4596#L729-1 assume !(~E_5~0 == 0); 4597#L734-1 assume !(~E_6~0 == 0); 4477#L739-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4378#L324 assume !(~m_pc~0 == 1); 4327#L324-2 is_master_triggered_~__retres1~0 := 0; 4328#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4324#L336 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 4325#L839 assume !(activate_threads_~tmp~1 != 0); 4610#L839-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4418#L343 assume ~t1_pc~0 == 1; 4419#L344 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 4413#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4414#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4565#L847 assume !(activate_threads_~tmp___0~0 != 0); 4784#L847-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4721#L362 assume !(~t2_pc~0 == 1); 4665#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 4666#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4717#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4779#L855 assume !(activate_threads_~tmp___1~0 != 0); 4790#L855-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4795#L381 assume ~t3_pc~0 == 1; 4829#L382 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 4826#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4827#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4235#L863 assume !(activate_threads_~tmp___2~0 != 0); 4203#L863-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4204#L400 assume ~t4_pc~0 == 1; 4267#L401 assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 4250#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4266#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4394#L871 assume !(activate_threads_~tmp___3~0 != 0); 4495#L871-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4502#L419 assume !(~t5_pc~0 == 1); 4402#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 4401#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4466#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4467#L879 assume activate_threads_~tmp___4~0 != 0;~t5_st~0 := 0; 4732#L879-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4733#L438 assume ~t6_pc~0 == 1; 4706#L439 assume ~E_6~0 == 1;is_transmit6_triggered_~__retres1~6 := 1; 4707#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4704#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4705#L887 assume !(activate_threads_~tmp___5~0 != 0); 4844#L887-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4287#L752 assume !(~M_E~0 == 1); 4273#L752-2 assume !(~T1_E~0 == 1); 4274#L757-1 assume !(~T2_E~0 == 1); 4593#L762-1 assume ~T3_E~0 == 1;~T3_E~0 := 2; 4594#L767-1 assume !(~T4_E~0 == 1); 4474#L772-1 assume !(~T5_E~0 == 1); 4475#L777-1 assume !(~T6_E~0 == 1); 4739#L782-1 assume !(~E_M~0 == 1); 4349#L787-1 assume !(~E_1~0 == 1); 4350#L792-1 assume !(~E_2~0 == 1); 4205#L797-1 assume !(~E_3~0 == 1); 4206#L802-1 assume ~E_4~0 == 1;~E_4~0 := 2; 4285#L807-1 assume !(~E_5~0 == 1); 4286#L812-1 assume !(~E_6~0 == 1); 4611#L817-1 assume { :end_inline_reset_delta_events } true; 4612#L1043-3 [2018-11-10 06:54:03,246 INFO L795 eck$LassoCheckResult]: Loop: 4612#L1043-3 assume true; 4847#L1043-1 assume !false; 4736#L1044 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 4380#L649 assume true; 4198#L555-1 assume !false; 4199#L556 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 4337#L508 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 4260#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 4341#L546 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 4729#L560 assume !(eval_~tmp~0 != 0); 4275#L664 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 4276#L458-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 4608#L674-3 assume ~M_E~0 == 0;~M_E~0 := 1; 4582#L674-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 4583#L679-3 assume !(~T2_E~0 == 0); 4449#L684-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 4450#L689-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 4521#L694-3 assume ~T5_E~0 == 0;~T5_E~0 := 1; 4333#L699-3 assume ~T6_E~0 == 0;~T6_E~0 := 1; 4334#L704-3 assume ~E_M~0 == 0;~E_M~0 := 1; 4189#L709-3 assume ~E_1~0 == 0;~E_1~0 := 1; 4190#L714-3 assume ~E_2~0 == 0;~E_2~0 := 1; 4279#L719-3 assume !(~E_3~0 == 0); 4280#L724-3 assume ~E_4~0 == 0;~E_4~0 := 1; 4605#L729-3 assume ~E_5~0 == 0;~E_5~0 := 1; 4606#L734-3 assume ~E_6~0 == 0;~E_6~0 := 1; 4488#L739-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4338#L324-24 assume !(~m_pc~0 == 1); 4339#L324-26 is_master_triggered_~__retres1~0 := 0; 4345#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4372#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 4562#L839-24 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 4522#L839-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4523#L343-24 assume ~t1_pc~0 == 1; 4554#L344-8 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 4555#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4551#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4552#L847-24 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 4756#L847-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4757#L362-24 assume ~t2_pc~0 == 1; 4749#L363-8 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 4637#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4638#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4748#L855-24 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 4845#L855-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4846#L381-24 assume ~t3_pc~0 == 1; 4854#L382-8 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 4820#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4821#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4373#L863-24 assume !(activate_threads_~tmp___2~0 != 0); 4374#L863-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4180#L400-24 assume ~t4_pc~0 == 1; 4181#L401-8 assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 4194#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4239#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4367#L871-24 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 4613#L871-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4486#L419-24 assume !(~t5_pc~0 == 1); 4451#L419-26 is_transmit5_triggered_~__retres1~5 := 0; 4452#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4514#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4620#L879-24 assume activate_threads_~tmp___4~0 != 0;~t5_st~0 := 0; 4642#L879-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4649#L438-24 assume ~t6_pc~0 == 1; 4698#L439-8 assume ~E_6~0 == 1;is_transmit6_triggered_~__retres1~6 := 1; 4699#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4694#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4695#L887-24 assume activate_threads_~tmp___5~0 != 0;~t6_st~0 := 0; 4799#L887-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4277#L752-3 assume ~M_E~0 == 1;~M_E~0 := 2; 4278#L752-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 4281#L757-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 4601#L762-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 4602#L767-3 assume ~T4_E~0 == 1;~T4_E~0 := 2; 4482#L772-3 assume ~T5_E~0 == 1;~T5_E~0 := 2; 4483#L777-3 assume !(~T6_E~0 == 1); 4740#L782-3 assume ~E_M~0 == 1;~E_M~0 := 2; 4352#L787-3 assume ~E_1~0 == 1;~E_1~0 := 2; 4353#L792-3 assume ~E_2~0 == 1;~E_2~0 := 2; 4213#L797-3 assume ~E_3~0 == 1;~E_3~0 := 2; 4214#L802-3 assume ~E_4~0 == 1;~E_4~0 := 2; 4269#L807-3 assume ~E_5~0 == 1;~E_5~0 := 2; 4270#L812-3 assume ~E_6~0 == 1;~E_6~0 := 2; 4595#L817-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 4463#L508-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 4263#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 4344#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 4376#L1062 assume !(start_simulation_~tmp~3 == 0); 4359#L1062-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 4360#L508-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 4265#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 4346#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 4215#L1017 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 4216#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 4510#L1025 start_simulation_#t~ret18 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 4511#L1075 assume !(start_simulation_~tmp___0~1 != 0); 4612#L1043-3 [2018-11-10 06:54:03,246 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:03,246 INFO L82 PathProgramCache]: Analyzing trace with hash -100431421, now seen corresponding path program 1 times [2018-11-10 06:54:03,246 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:03,246 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:03,247 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:03,247 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:03,247 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:03,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:03,275 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:03,275 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:03,275 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:54:03,275 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 06:54:03,275 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:03,276 INFO L82 PathProgramCache]: Analyzing trace with hash 1456435999, now seen corresponding path program 1 times [2018-11-10 06:54:03,276 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:03,276 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:03,277 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:03,277 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:03,277 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:03,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:03,316 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:03,316 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:03,316 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:54:03,316 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 06:54:03,317 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 06:54:03,317 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 06:54:03,317 INFO L87 Difference]: Start difference. First operand 690 states and 1026 transitions. cyclomatic complexity: 337 Second operand 3 states. [2018-11-10 06:54:03,330 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:54:03,330 INFO L93 Difference]: Finished difference Result 690 states and 1025 transitions. [2018-11-10 06:54:03,331 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 06:54:03,331 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 690 states and 1025 transitions. [2018-11-10 06:54:03,335 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 599 [2018-11-10 06:54:03,350 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 690 states to 690 states and 1025 transitions. [2018-11-10 06:54:03,351 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 690 [2018-11-10 06:54:03,351 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 690 [2018-11-10 06:54:03,351 INFO L73 IsDeterministic]: Start isDeterministic. Operand 690 states and 1025 transitions. [2018-11-10 06:54:03,352 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:54:03,352 INFO L705 BuchiCegarLoop]: Abstraction has 690 states and 1025 transitions. [2018-11-10 06:54:03,353 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 690 states and 1025 transitions. [2018-11-10 06:54:03,356 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 690 to 690. [2018-11-10 06:54:03,357 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 690 states. [2018-11-10 06:54:03,357 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 690 states to 690 states and 1025 transitions. [2018-11-10 06:54:03,358 INFO L728 BuchiCegarLoop]: Abstraction has 690 states and 1025 transitions. [2018-11-10 06:54:03,358 INFO L608 BuchiCegarLoop]: Abstraction has 690 states and 1025 transitions. [2018-11-10 06:54:03,358 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ [2018-11-10 06:54:03,358 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 690 states and 1025 transitions. [2018-11-10 06:54:03,359 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 599 [2018-11-10 06:54:03,359 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:54:03,359 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:54:03,360 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:03,360 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:03,361 INFO L793 eck$LassoCheckResult]: Stem: 6149#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 6043#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 5607#L1006 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 5608#L458 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5974#L465 assume ~m_i~0 == 1;~m_st~0 := 0; 5975#L465-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 5978#L470-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 5851#L475-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 5852#L480-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 5907#L485-1 assume !(~t5_i~0 == 1);~t5_st~0 := 2; 5706#L490-1 assume !(~t6_i~0 == 1);~t6_st~0 := 2; 5707#L495-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5985#L674 assume !(~M_E~0 == 0); 5986#L674-2 assume !(~T1_E~0 == 0); 5994#L679-1 assume !(~T2_E~0 == 0); 5873#L684-1 assume !(~T3_E~0 == 0); 5874#L689-1 assume !(~T4_E~0 == 0); 6128#L694-1 assume !(~T5_E~0 == 0); 5741#L699-1 assume !(~T6_E~0 == 0); 5742#L704-1 assume ~E_M~0 == 0;~E_M~0 := 1; 5561#L709-1 assume !(~E_1~0 == 0); 5562#L714-1 assume !(~E_2~0 == 0); 5658#L719-1 assume !(~E_3~0 == 0); 5659#L724-1 assume !(~E_4~0 == 0); 5983#L729-1 assume !(~E_5~0 == 0); 5984#L734-1 assume !(~E_6~0 == 0); 5866#L739-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5765#L324 assume !(~m_pc~0 == 1); 5714#L324-2 is_master_triggered_~__retres1~0 := 0; 5715#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5711#L336 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5712#L839 assume !(activate_threads_~tmp~1 != 0); 5997#L839-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5805#L343 assume ~t1_pc~0 == 1; 5806#L344 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 5803#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5804#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5952#L847 assume !(activate_threads_~tmp___0~0 != 0); 6171#L847-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6108#L362 assume !(~t2_pc~0 == 1); 6052#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 6053#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6107#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 6166#L855 assume !(activate_threads_~tmp___1~0 != 0); 6177#L855-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6182#L381 assume ~t3_pc~0 == 1; 6216#L382 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 6214#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6215#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5623#L863 assume !(activate_threads_~tmp___2~0 != 0); 5590#L863-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5591#L400 assume ~t4_pc~0 == 1; 5654#L401 assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 5637#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5653#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5781#L871 assume !(activate_threads_~tmp___3~0 != 0); 5884#L871-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5890#L419 assume !(~t5_pc~0 == 1); 5789#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 5788#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5853#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5854#L879 assume activate_threads_~tmp___4~0 != 0;~t5_st~0 := 0; 6119#L879-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 6120#L438 assume ~t6_pc~0 == 1; 6093#L439 assume ~E_6~0 == 1;is_transmit6_triggered_~__retres1~6 := 1; 6094#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 6091#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6092#L887 assume !(activate_threads_~tmp___5~0 != 0); 6231#L887-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5674#L752 assume !(~M_E~0 == 1); 5660#L752-2 assume !(~T1_E~0 == 1); 5661#L757-1 assume !(~T2_E~0 == 1); 5980#L762-1 assume ~T3_E~0 == 1;~T3_E~0 := 2; 5981#L767-1 assume !(~T4_E~0 == 1); 5862#L772-1 assume !(~T5_E~0 == 1); 5863#L777-1 assume !(~T6_E~0 == 1); 6126#L782-1 assume !(~E_M~0 == 1); 5736#L787-1 assume !(~E_1~0 == 1); 5737#L792-1 assume !(~E_2~0 == 1); 5595#L797-1 assume !(~E_3~0 == 1); 5596#L802-1 assume ~E_4~0 == 1;~E_4~0 := 2; 5672#L807-1 assume !(~E_5~0 == 1); 5673#L812-1 assume !(~E_6~0 == 1); 5998#L817-1 assume { :end_inline_reset_delta_events } true; 5999#L1043-3 [2018-11-10 06:54:03,361 INFO L795 eck$LassoCheckResult]: Loop: 5999#L1043-3 assume true; 6234#L1043-1 assume !false; 6123#L1044 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 5768#L649 assume true; 5585#L555-1 assume !false; 5586#L556 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 5727#L508 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 5647#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 5728#L546 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 6116#L560 assume !(eval_~tmp~0 != 0); 5662#L664 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 5663#L458-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 5995#L674-3 assume ~M_E~0 == 0;~M_E~0 := 1; 5969#L674-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 5970#L679-3 assume !(~T2_E~0 == 0); 5838#L684-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 5839#L689-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 5908#L694-3 assume ~T5_E~0 == 0;~T5_E~0 := 1; 5720#L699-3 assume ~T6_E~0 == 0;~T6_E~0 := 1; 5721#L704-3 assume ~E_M~0 == 0;~E_M~0 := 1; 5576#L709-3 assume ~E_1~0 == 0;~E_1~0 := 1; 5577#L714-3 assume ~E_2~0 == 0;~E_2~0 := 1; 5666#L719-3 assume !(~E_3~0 == 0); 5667#L724-3 assume ~E_4~0 == 0;~E_4~0 := 1; 5992#L729-3 assume ~E_5~0 == 0;~E_5~0 := 1; 5993#L734-3 assume ~E_6~0 == 0;~E_6~0 := 1; 5875#L739-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5724#L324-24 assume !(~m_pc~0 == 1); 5725#L324-26 is_master_triggered_~__retres1~0 := 0; 5732#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5759#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5946#L839-24 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 5909#L839-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5910#L343-24 assume ~t1_pc~0 == 1; 5941#L344-8 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 5942#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5938#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5939#L847-24 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 6143#L847-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6144#L362-24 assume ~t2_pc~0 == 1; 6136#L363-8 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 6024#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6025#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 6135#L855-24 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 6232#L855-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6233#L381-24 assume ~t3_pc~0 == 1; 6241#L382-8 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 6207#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6208#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5760#L863-24 assume !(activate_threads_~tmp___2~0 != 0); 5761#L863-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5567#L400-24 assume ~t4_pc~0 == 1; 5568#L401-8 assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 5581#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5626#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5754#L871-24 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 6000#L871-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5871#L419-24 assume ~t5_pc~0 == 1; 5872#L420-8 assume ~E_5~0 == 1;is_transmit5_triggered_~__retres1~5 := 1; 5837#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5901#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 6007#L879-24 assume activate_threads_~tmp___4~0 != 0;~t5_st~0 := 0; 6028#L879-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 6036#L438-24 assume ~t6_pc~0 == 1; 6085#L439-8 assume ~E_6~0 == 1;is_transmit6_triggered_~__retres1~6 := 1; 6086#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 6081#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6082#L887-24 assume activate_threads_~tmp___5~0 != 0;~t6_st~0 := 0; 6186#L887-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5664#L752-3 assume ~M_E~0 == 1;~M_E~0 := 2; 5665#L752-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 5668#L757-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 5988#L762-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 5989#L767-3 assume ~T4_E~0 == 1;~T4_E~0 := 2; 5869#L772-3 assume ~T5_E~0 == 1;~T5_E~0 := 2; 5870#L777-3 assume !(~T6_E~0 == 1); 6127#L782-3 assume ~E_M~0 == 1;~E_M~0 := 2; 5739#L787-3 assume ~E_1~0 == 1;~E_1~0 := 2; 5740#L792-3 assume ~E_2~0 == 1;~E_2~0 := 2; 5600#L797-3 assume ~E_3~0 == 1;~E_3~0 := 2; 5601#L802-3 assume ~E_4~0 == 1;~E_4~0 := 2; 5656#L807-3 assume ~E_5~0 == 1;~E_5~0 := 2; 5657#L812-3 assume ~E_6~0 == 1;~E_6~0 := 2; 5982#L817-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 5850#L508-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 5650#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 5729#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 5763#L1062 assume !(start_simulation_~tmp~3 == 0); 5746#L1062-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 5747#L508-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 5652#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 5735#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 5605#L1017 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 5606#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 5897#L1025 start_simulation_#t~ret18 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 5898#L1075 assume !(start_simulation_~tmp___0~1 != 0); 5999#L1043-3 [2018-11-10 06:54:03,362 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:03,362 INFO L82 PathProgramCache]: Analyzing trace with hash 1976905477, now seen corresponding path program 1 times [2018-11-10 06:54:03,362 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:03,362 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:03,363 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:03,363 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:03,363 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:03,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:03,390 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:03,391 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:03,391 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:54:03,391 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 06:54:03,391 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:03,391 INFO L82 PathProgramCache]: Analyzing trace with hash -1881602914, now seen corresponding path program 1 times [2018-11-10 06:54:03,391 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:03,392 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:03,392 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:03,396 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:03,396 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:03,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:03,436 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:03,436 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:03,436 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:54:03,436 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 06:54:03,437 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 06:54:03,437 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 06:54:03,437 INFO L87 Difference]: Start difference. First operand 690 states and 1025 transitions. cyclomatic complexity: 336 Second operand 3 states. [2018-11-10 06:54:03,444 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:54:03,444 INFO L93 Difference]: Finished difference Result 690 states and 1024 transitions. [2018-11-10 06:54:03,445 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 06:54:03,445 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 690 states and 1024 transitions. [2018-11-10 06:54:03,447 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 599 [2018-11-10 06:54:03,448 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 690 states to 690 states and 1024 transitions. [2018-11-10 06:54:03,449 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 690 [2018-11-10 06:54:03,449 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 690 [2018-11-10 06:54:03,449 INFO L73 IsDeterministic]: Start isDeterministic. Operand 690 states and 1024 transitions. [2018-11-10 06:54:03,450 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:54:03,450 INFO L705 BuchiCegarLoop]: Abstraction has 690 states and 1024 transitions. [2018-11-10 06:54:03,451 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 690 states and 1024 transitions. [2018-11-10 06:54:03,455 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 690 to 690. [2018-11-10 06:54:03,455 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 690 states. [2018-11-10 06:54:03,456 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 690 states to 690 states and 1024 transitions. [2018-11-10 06:54:03,456 INFO L728 BuchiCegarLoop]: Abstraction has 690 states and 1024 transitions. [2018-11-10 06:54:03,456 INFO L608 BuchiCegarLoop]: Abstraction has 690 states and 1024 transitions. [2018-11-10 06:54:03,456 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ [2018-11-10 06:54:03,456 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 690 states and 1024 transitions. [2018-11-10 06:54:03,458 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 599 [2018-11-10 06:54:03,458 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:54:03,458 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:54:03,459 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:03,459 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:03,459 INFO L793 eck$LassoCheckResult]: Stem: 7535#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 7425#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 6994#L1006 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 6995#L458 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7361#L465 assume ~m_i~0 == 1;~m_st~0 := 0; 7362#L465-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 7365#L470-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 7238#L475-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 7239#L480-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 7294#L485-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 7090#L490-1 assume !(~t6_i~0 == 1);~t6_st~0 := 2; 7091#L495-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7372#L674 assume !(~M_E~0 == 0); 7373#L674-2 assume !(~T1_E~0 == 0); 7381#L679-1 assume !(~T2_E~0 == 0); 7258#L684-1 assume !(~T3_E~0 == 0); 7259#L689-1 assume !(~T4_E~0 == 0); 7515#L694-1 assume !(~T5_E~0 == 0); 7128#L699-1 assume !(~T6_E~0 == 0); 7129#L704-1 assume ~E_M~0 == 0;~E_M~0 := 1; 6948#L709-1 assume !(~E_1~0 == 0); 6949#L714-1 assume !(~E_2~0 == 0); 7045#L719-1 assume !(~E_3~0 == 0); 7046#L724-1 assume !(~E_4~0 == 0); 7370#L729-1 assume !(~E_5~0 == 0); 7371#L734-1 assume !(~E_6~0 == 0); 7251#L739-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7152#L324 assume !(~m_pc~0 == 1); 7101#L324-2 is_master_triggered_~__retres1~0 := 0; 7102#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7098#L336 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 7099#L839 assume !(activate_threads_~tmp~1 != 0); 7384#L839-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7192#L343 assume ~t1_pc~0 == 1; 7193#L344 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 7187#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7188#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 7339#L847 assume !(activate_threads_~tmp___0~0 != 0); 7558#L847-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7495#L362 assume !(~t2_pc~0 == 1); 7439#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 7440#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7491#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7553#L855 assume !(activate_threads_~tmp___1~0 != 0); 7564#L855-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7569#L381 assume ~t3_pc~0 == 1; 7603#L382 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 7600#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7601#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7009#L863 assume !(activate_threads_~tmp___2~0 != 0); 6977#L863-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6978#L400 assume ~t4_pc~0 == 1; 7041#L401 assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 7024#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7040#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7168#L871 assume !(activate_threads_~tmp___3~0 != 0); 7269#L871-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7276#L419 assume !(~t5_pc~0 == 1); 7176#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 7175#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7240#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7241#L879 assume activate_threads_~tmp___4~0 != 0;~t5_st~0 := 0; 7506#L879-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7507#L438 assume ~t6_pc~0 == 1; 7480#L439 assume ~E_6~0 == 1;is_transmit6_triggered_~__retres1~6 := 1; 7481#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 7478#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7479#L887 assume !(activate_threads_~tmp___5~0 != 0); 7618#L887-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7061#L752 assume !(~M_E~0 == 1); 7047#L752-2 assume !(~T1_E~0 == 1); 7048#L757-1 assume !(~T2_E~0 == 1); 7367#L762-1 assume ~T3_E~0 == 1;~T3_E~0 := 2; 7368#L767-1 assume !(~T4_E~0 == 1); 7248#L772-1 assume !(~T5_E~0 == 1); 7249#L777-1 assume !(~T6_E~0 == 1); 7513#L782-1 assume !(~E_M~0 == 1); 7123#L787-1 assume !(~E_1~0 == 1); 7124#L792-1 assume !(~E_2~0 == 1); 6979#L797-1 assume !(~E_3~0 == 1); 6980#L802-1 assume ~E_4~0 == 1;~E_4~0 := 2; 7059#L807-1 assume !(~E_5~0 == 1); 7060#L812-1 assume !(~E_6~0 == 1); 7385#L817-1 assume { :end_inline_reset_delta_events } true; 7386#L1043-3 [2018-11-10 06:54:03,459 INFO L795 eck$LassoCheckResult]: Loop: 7386#L1043-3 assume true; 7621#L1043-1 assume !false; 7510#L1044 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 7154#L649 assume true; 6972#L555-1 assume !false; 6973#L556 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 7111#L508 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 7034#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 7115#L546 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 7503#L560 assume !(eval_~tmp~0 != 0); 7049#L664 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 7050#L458-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 7382#L674-3 assume ~M_E~0 == 0;~M_E~0 := 1; 7356#L674-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 7357#L679-3 assume !(~T2_E~0 == 0); 7223#L684-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 7224#L689-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 7295#L694-3 assume ~T5_E~0 == 0;~T5_E~0 := 1; 7107#L699-3 assume ~T6_E~0 == 0;~T6_E~0 := 1; 7108#L704-3 assume ~E_M~0 == 0;~E_M~0 := 1; 6963#L709-3 assume ~E_1~0 == 0;~E_1~0 := 1; 6964#L714-3 assume ~E_2~0 == 0;~E_2~0 := 1; 7053#L719-3 assume !(~E_3~0 == 0); 7054#L724-3 assume ~E_4~0 == 0;~E_4~0 := 1; 7379#L729-3 assume ~E_5~0 == 0;~E_5~0 := 1; 7380#L734-3 assume ~E_6~0 == 0;~E_6~0 := 1; 7262#L739-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7112#L324-24 assume !(~m_pc~0 == 1); 7113#L324-26 is_master_triggered_~__retres1~0 := 0; 7119#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7146#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 7333#L839-24 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 7296#L839-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7297#L343-24 assume ~t1_pc~0 == 1; 7328#L344-8 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 7329#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7325#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 7326#L847-24 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 7530#L847-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7531#L362-24 assume ~t2_pc~0 == 1; 7523#L363-8 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 7411#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7412#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7522#L855-24 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 7619#L855-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7620#L381-24 assume ~t3_pc~0 == 1; 7628#L382-8 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 7594#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7595#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7147#L863-24 assume !(activate_threads_~tmp___2~0 != 0); 7148#L863-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6954#L400-24 assume ~t4_pc~0 == 1; 6955#L401-8 assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 6968#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7013#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7141#L871-24 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 7387#L871-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7260#L419-24 assume !(~t5_pc~0 == 1); 7225#L419-26 is_transmit5_triggered_~__retres1~5 := 0; 7226#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7288#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7394#L879-24 assume activate_threads_~tmp___4~0 != 0;~t5_st~0 := 0; 7416#L879-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7423#L438-24 assume ~t6_pc~0 == 1; 7472#L439-8 assume ~E_6~0 == 1;is_transmit6_triggered_~__retres1~6 := 1; 7473#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 7468#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7469#L887-24 assume activate_threads_~tmp___5~0 != 0;~t6_st~0 := 0; 7573#L887-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7051#L752-3 assume ~M_E~0 == 1;~M_E~0 := 2; 7052#L752-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 7055#L757-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 7375#L762-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 7376#L767-3 assume ~T4_E~0 == 1;~T4_E~0 := 2; 7256#L772-3 assume ~T5_E~0 == 1;~T5_E~0 := 2; 7257#L777-3 assume !(~T6_E~0 == 1); 7514#L782-3 assume ~E_M~0 == 1;~E_M~0 := 2; 7126#L787-3 assume ~E_1~0 == 1;~E_1~0 := 2; 7127#L792-3 assume ~E_2~0 == 1;~E_2~0 := 2; 6987#L797-3 assume ~E_3~0 == 1;~E_3~0 := 2; 6988#L802-3 assume ~E_4~0 == 1;~E_4~0 := 2; 7043#L807-3 assume ~E_5~0 == 1;~E_5~0 := 2; 7044#L812-3 assume ~E_6~0 == 1;~E_6~0 := 2; 7369#L817-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 7237#L508-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 7037#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 7118#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 7150#L1062 assume !(start_simulation_~tmp~3 == 0); 7133#L1062-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 7134#L508-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 7039#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 7122#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 6992#L1017 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 6993#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 7284#L1025 start_simulation_#t~ret18 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 7285#L1075 assume !(start_simulation_~tmp___0~1 != 0); 7386#L1043-3 [2018-11-10 06:54:03,460 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:03,460 INFO L82 PathProgramCache]: Analyzing trace with hash 242801027, now seen corresponding path program 1 times [2018-11-10 06:54:03,460 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:03,460 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:03,460 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:03,461 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:03,461 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:03,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:03,490 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:03,490 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:03,490 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:54:03,491 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 06:54:03,491 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:03,491 INFO L82 PathProgramCache]: Analyzing trace with hash 1456435999, now seen corresponding path program 2 times [2018-11-10 06:54:03,491 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:03,491 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:03,492 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:03,492 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:03,492 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:03,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:03,524 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:03,524 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:03,524 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:54:03,524 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 06:54:03,524 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 06:54:03,525 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 06:54:03,525 INFO L87 Difference]: Start difference. First operand 690 states and 1024 transitions. cyclomatic complexity: 335 Second operand 3 states. [2018-11-10 06:54:03,533 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:54:03,533 INFO L93 Difference]: Finished difference Result 690 states and 1023 transitions. [2018-11-10 06:54:03,534 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 06:54:03,534 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 690 states and 1023 transitions. [2018-11-10 06:54:03,536 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 599 [2018-11-10 06:54:03,537 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 690 states to 690 states and 1023 transitions. [2018-11-10 06:54:03,537 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 690 [2018-11-10 06:54:03,538 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 690 [2018-11-10 06:54:03,538 INFO L73 IsDeterministic]: Start isDeterministic. Operand 690 states and 1023 transitions. [2018-11-10 06:54:03,539 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:54:03,539 INFO L705 BuchiCegarLoop]: Abstraction has 690 states and 1023 transitions. [2018-11-10 06:54:03,540 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 690 states and 1023 transitions. [2018-11-10 06:54:03,543 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 690 to 690. [2018-11-10 06:54:03,544 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 690 states. [2018-11-10 06:54:03,545 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 690 states to 690 states and 1023 transitions. [2018-11-10 06:54:03,545 INFO L728 BuchiCegarLoop]: Abstraction has 690 states and 1023 transitions. [2018-11-10 06:54:03,545 INFO L608 BuchiCegarLoop]: Abstraction has 690 states and 1023 transitions. [2018-11-10 06:54:03,545 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ [2018-11-10 06:54:03,545 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 690 states and 1023 transitions. [2018-11-10 06:54:03,547 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 599 [2018-11-10 06:54:03,547 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:54:03,547 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:54:03,548 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:03,548 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:03,548 INFO L793 eck$LassoCheckResult]: Stem: 8922#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 8812#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 8381#L1006 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 8382#L458 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8748#L465 assume ~m_i~0 == 1;~m_st~0 := 0; 8749#L465-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 8752#L470-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 8625#L475-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 8626#L480-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 8681#L485-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 8480#L490-1 assume ~t6_i~0 == 1;~t6_st~0 := 0; 8481#L495-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8759#L674 assume !(~M_E~0 == 0); 8760#L674-2 assume !(~T1_E~0 == 0); 8768#L679-1 assume !(~T2_E~0 == 0); 8647#L684-1 assume !(~T3_E~0 == 0); 8648#L689-1 assume !(~T4_E~0 == 0); 8902#L694-1 assume !(~T5_E~0 == 0); 8515#L699-1 assume !(~T6_E~0 == 0); 8516#L704-1 assume ~E_M~0 == 0;~E_M~0 := 1; 8335#L709-1 assume !(~E_1~0 == 0); 8336#L714-1 assume !(~E_2~0 == 0); 8432#L719-1 assume !(~E_3~0 == 0); 8433#L724-1 assume !(~E_4~0 == 0); 8757#L729-1 assume !(~E_5~0 == 0); 8758#L734-1 assume !(~E_6~0 == 0); 8639#L739-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8539#L324 assume !(~m_pc~0 == 1); 8488#L324-2 is_master_triggered_~__retres1~0 := 0; 8489#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8485#L336 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 8486#L839 assume !(activate_threads_~tmp~1 != 0); 8771#L839-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8579#L343 assume ~t1_pc~0 == 1; 8580#L344 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 8574#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8575#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 8726#L847 assume !(activate_threads_~tmp___0~0 != 0); 8945#L847-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8882#L362 assume !(~t2_pc~0 == 1); 8826#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 8827#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8878#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 8940#L855 assume !(activate_threads_~tmp___1~0 != 0); 8951#L855-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8956#L381 assume ~t3_pc~0 == 1; 8990#L382 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 8988#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8989#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 8396#L863 assume !(activate_threads_~tmp___2~0 != 0); 8364#L863-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8365#L400 assume ~t4_pc~0 == 1; 8428#L401 assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 8411#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8427#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 8555#L871 assume !(activate_threads_~tmp___3~0 != 0); 8658#L871-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8664#L419 assume !(~t5_pc~0 == 1); 8563#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 8562#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8627#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 8628#L879 assume activate_threads_~tmp___4~0 != 0;~t5_st~0 := 0; 8893#L879-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 8894#L438 assume ~t6_pc~0 == 1; 8867#L439 assume ~E_6~0 == 1;is_transmit6_triggered_~__retres1~6 := 1; 8868#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 8865#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 8866#L887 assume !(activate_threads_~tmp___5~0 != 0); 9005#L887-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8448#L752 assume !(~M_E~0 == 1); 8434#L752-2 assume !(~T1_E~0 == 1); 8435#L757-1 assume !(~T2_E~0 == 1); 8754#L762-1 assume ~T3_E~0 == 1;~T3_E~0 := 2; 8755#L767-1 assume !(~T4_E~0 == 1); 8636#L772-1 assume !(~T5_E~0 == 1); 8637#L777-1 assume !(~T6_E~0 == 1); 8900#L782-1 assume !(~E_M~0 == 1); 8510#L787-1 assume !(~E_1~0 == 1); 8511#L792-1 assume !(~E_2~0 == 1); 8366#L797-1 assume !(~E_3~0 == 1); 8367#L802-1 assume ~E_4~0 == 1;~E_4~0 := 2; 8446#L807-1 assume !(~E_5~0 == 1); 8447#L812-1 assume !(~E_6~0 == 1); 8772#L817-1 assume { :end_inline_reset_delta_events } true; 8773#L1043-3 [2018-11-10 06:54:03,548 INFO L795 eck$LassoCheckResult]: Loop: 8773#L1043-3 assume true; 9008#L1043-1 assume !false; 8897#L1044 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 8541#L649 assume true; 8359#L555-1 assume !false; 8360#L556 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 8498#L508 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 8421#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 8502#L546 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 8890#L560 assume !(eval_~tmp~0 != 0); 8436#L664 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 8437#L458-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 8769#L674-3 assume ~M_E~0 == 0;~M_E~0 := 1; 8743#L674-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 8744#L679-3 assume !(~T2_E~0 == 0); 8612#L684-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 8613#L689-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 8682#L694-3 assume ~T5_E~0 == 0;~T5_E~0 := 1; 8494#L699-3 assume ~T6_E~0 == 0;~T6_E~0 := 1; 8495#L704-3 assume ~E_M~0 == 0;~E_M~0 := 1; 8350#L709-3 assume ~E_1~0 == 0;~E_1~0 := 1; 8351#L714-3 assume ~E_2~0 == 0;~E_2~0 := 1; 8440#L719-3 assume !(~E_3~0 == 0); 8441#L724-3 assume ~E_4~0 == 0;~E_4~0 := 1; 8766#L729-3 assume ~E_5~0 == 0;~E_5~0 := 1; 8767#L734-3 assume ~E_6~0 == 0;~E_6~0 := 1; 8649#L739-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8499#L324-24 assume !(~m_pc~0 == 1); 8500#L324-26 is_master_triggered_~__retres1~0 := 0; 8506#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8533#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 8723#L839-24 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 8683#L839-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8684#L343-24 assume ~t1_pc~0 == 1; 8715#L344-8 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 8716#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8712#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 8713#L847-24 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 8917#L847-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8918#L362-24 assume ~t2_pc~0 == 1; 8910#L363-8 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 8798#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8799#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 8909#L855-24 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 9006#L855-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9007#L381-24 assume ~t3_pc~0 == 1; 9015#L382-8 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 8981#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8982#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 8534#L863-24 assume !(activate_threads_~tmp___2~0 != 0); 8535#L863-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8341#L400-24 assume ~t4_pc~0 == 1; 8342#L401-8 assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 8355#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8400#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 8528#L871-24 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 8774#L871-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8645#L419-24 assume !(~t5_pc~0 == 1); 8610#L419-26 is_transmit5_triggered_~__retres1~5 := 0; 8611#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8675#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 8781#L879-24 assume activate_threads_~tmp___4~0 != 0;~t5_st~0 := 0; 8802#L879-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 8810#L438-24 assume ~t6_pc~0 == 1; 8857#L439-8 assume ~E_6~0 == 1;is_transmit6_triggered_~__retres1~6 := 1; 8858#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 8855#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 8856#L887-24 assume activate_threads_~tmp___5~0 != 0;~t6_st~0 := 0; 8960#L887-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8438#L752-3 assume ~M_E~0 == 1;~M_E~0 := 2; 8439#L752-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 8442#L757-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 8762#L762-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 8763#L767-3 assume ~T4_E~0 == 1;~T4_E~0 := 2; 8642#L772-3 assume ~T5_E~0 == 1;~T5_E~0 := 2; 8643#L777-3 assume !(~T6_E~0 == 1); 8901#L782-3 assume ~E_M~0 == 1;~E_M~0 := 2; 8513#L787-3 assume ~E_1~0 == 1;~E_1~0 := 2; 8514#L792-3 assume ~E_2~0 == 1;~E_2~0 := 2; 8373#L797-3 assume ~E_3~0 == 1;~E_3~0 := 2; 8374#L802-3 assume ~E_4~0 == 1;~E_4~0 := 2; 8430#L807-3 assume ~E_5~0 == 1;~E_5~0 := 2; 8431#L812-3 assume ~E_6~0 == 1;~E_6~0 := 2; 8756#L817-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 8624#L508-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 8424#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 8503#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 8537#L1062 assume !(start_simulation_~tmp~3 == 0); 8520#L1062-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 8521#L508-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 8426#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 8509#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 8376#L1017 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 8377#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 8671#L1025 start_simulation_#t~ret18 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 8672#L1075 assume !(start_simulation_~tmp___0~1 != 0); 8773#L1043-3 [2018-11-10 06:54:03,549 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:03,549 INFO L82 PathProgramCache]: Analyzing trace with hash -644421819, now seen corresponding path program 1 times [2018-11-10 06:54:03,549 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:03,549 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:03,550 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:03,550 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 06:54:03,550 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:03,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:03,581 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:03,581 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:03,581 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 06:54:03,581 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 06:54:03,581 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:03,582 INFO L82 PathProgramCache]: Analyzing trace with hash 1456435999, now seen corresponding path program 3 times [2018-11-10 06:54:03,582 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:03,582 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:03,582 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:03,583 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:03,583 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:03,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:03,615 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:03,616 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:03,616 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:54:03,617 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 06:54:03,617 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 06:54:03,617 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 06:54:03,617 INFO L87 Difference]: Start difference. First operand 690 states and 1023 transitions. cyclomatic complexity: 334 Second operand 3 states. [2018-11-10 06:54:03,676 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:54:03,676 INFO L93 Difference]: Finished difference Result 690 states and 1009 transitions. [2018-11-10 06:54:03,677 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 06:54:03,678 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 690 states and 1009 transitions. [2018-11-10 06:54:03,681 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 599 [2018-11-10 06:54:03,683 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 690 states to 690 states and 1009 transitions. [2018-11-10 06:54:03,683 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 690 [2018-11-10 06:54:03,684 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 690 [2018-11-10 06:54:03,684 INFO L73 IsDeterministic]: Start isDeterministic. Operand 690 states and 1009 transitions. [2018-11-10 06:54:03,685 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:54:03,685 INFO L705 BuchiCegarLoop]: Abstraction has 690 states and 1009 transitions. [2018-11-10 06:54:03,686 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 690 states and 1009 transitions. [2018-11-10 06:54:03,692 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 690 to 690. [2018-11-10 06:54:03,692 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 690 states. [2018-11-10 06:54:03,694 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 690 states to 690 states and 1009 transitions. [2018-11-10 06:54:03,694 INFO L728 BuchiCegarLoop]: Abstraction has 690 states and 1009 transitions. [2018-11-10 06:54:03,694 INFO L608 BuchiCegarLoop]: Abstraction has 690 states and 1009 transitions. [2018-11-10 06:54:03,694 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ [2018-11-10 06:54:03,694 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 690 states and 1009 transitions. [2018-11-10 06:54:03,696 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 599 [2018-11-10 06:54:03,696 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:54:03,697 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:54:03,698 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:03,698 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:03,698 INFO L793 eck$LassoCheckResult]: Stem: 10310#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 10204#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 9768#L1006 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 9769#L458 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10135#L465 assume ~m_i~0 == 1;~m_st~0 := 0; 10136#L465-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 10139#L470-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 10012#L475-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 10013#L480-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 10068#L485-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 9861#L490-1 assume ~t6_i~0 == 1;~t6_st~0 := 0; 9862#L495-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10147#L674 assume !(~M_E~0 == 0); 10148#L674-2 assume !(~T1_E~0 == 0); 10155#L679-1 assume !(~T2_E~0 == 0); 10034#L684-1 assume !(~T3_E~0 == 0); 10035#L689-1 assume !(~T4_E~0 == 0); 10289#L694-1 assume !(~T5_E~0 == 0); 9897#L699-1 assume !(~T6_E~0 == 0); 9898#L704-1 assume !(~E_M~0 == 0); 9722#L709-1 assume !(~E_1~0 == 0); 9723#L714-1 assume !(~E_2~0 == 0); 9819#L719-1 assume !(~E_3~0 == 0); 9820#L724-1 assume !(~E_4~0 == 0); 10144#L729-1 assume !(~E_5~0 == 0); 10145#L734-1 assume !(~E_6~0 == 0); 10027#L739-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9924#L324 assume !(~m_pc~0 == 1); 9869#L324-2 is_master_triggered_~__retres1~0 := 0; 9933#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9866#L336 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 9867#L839 assume !(activate_threads_~tmp~1 != 0); 10158#L839-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9966#L343 assume ~t1_pc~0 == 1; 9967#L344 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 9964#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9965#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 10113#L847 assume !(activate_threads_~tmp___0~0 != 0); 10332#L847-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10269#L362 assume !(~t2_pc~0 == 1); 10213#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 10214#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10268#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 10327#L855 assume !(activate_threads_~tmp___1~0 != 0); 10338#L855-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10343#L381 assume ~t3_pc~0 == 1; 10377#L382 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 10375#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10376#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 9784#L863 assume !(activate_threads_~tmp___2~0 != 0); 9751#L863-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9752#L400 assume ~t4_pc~0 == 1; 9815#L401 assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 9798#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9814#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9942#L871 assume !(activate_threads_~tmp___3~0 != 0); 10045#L871-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10051#L419 assume !(~t5_pc~0 == 1); 9950#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 9949#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 10014#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 10015#L879 assume activate_threads_~tmp___4~0 != 0;~t5_st~0 := 0; 10280#L879-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 10281#L438 assume ~t6_pc~0 == 1; 10254#L439 assume ~E_6~0 == 1;is_transmit6_triggered_~__retres1~6 := 1; 10255#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 10252#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 10253#L887 assume !(activate_threads_~tmp___5~0 != 0); 10392#L887-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9835#L752 assume !(~M_E~0 == 1); 9821#L752-2 assume !(~T1_E~0 == 1); 9822#L757-1 assume !(~T2_E~0 == 1); 10141#L762-1 assume ~T3_E~0 == 1;~T3_E~0 := 2; 10142#L767-1 assume !(~T4_E~0 == 1); 10023#L772-1 assume !(~T5_E~0 == 1); 10024#L777-1 assume !(~T6_E~0 == 1); 10287#L782-1 assume !(~E_M~0 == 1); 9892#L787-1 assume !(~E_1~0 == 1); 9893#L792-1 assume !(~E_2~0 == 1); 9756#L797-1 assume !(~E_3~0 == 1); 9757#L802-1 assume ~E_4~0 == 1;~E_4~0 := 2; 9833#L807-1 assume !(~E_5~0 == 1); 9834#L812-1 assume !(~E_6~0 == 1); 10159#L817-1 assume { :end_inline_reset_delta_events } true; 10160#L1043-3 [2018-11-10 06:54:03,698 INFO L795 eck$LassoCheckResult]: Loop: 10160#L1043-3 assume true; 10395#L1043-1 assume !false; 10284#L1044 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 9926#L649 assume true; 9746#L555-1 assume !false; 9747#L556 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 9881#L508 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 9808#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 9882#L546 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 10277#L560 assume !(eval_~tmp~0 != 0); 9823#L664 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 9824#L458-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 10157#L674-3 assume ~M_E~0 == 0;~M_E~0 := 1; 10130#L674-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 10131#L679-3 assume !(~T2_E~0 == 0); 9999#L684-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 10000#L689-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 10069#L694-3 assume ~T5_E~0 == 0;~T5_E~0 := 1; 9874#L699-3 assume ~T6_E~0 == 0;~T6_E~0 := 1; 9875#L704-3 assume !(~E_M~0 == 0); 9734#L709-3 assume ~E_1~0 == 0;~E_1~0 := 1; 9735#L714-3 assume ~E_2~0 == 0;~E_2~0 := 1; 9827#L719-3 assume !(~E_3~0 == 0); 9828#L724-3 assume ~E_4~0 == 0;~E_4~0 := 1; 10153#L729-3 assume ~E_5~0 == 0;~E_5~0 := 1; 10154#L734-3 assume ~E_6~0 == 0;~E_6~0 := 1; 10036#L739-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9878#L324-24 assume !(~m_pc~0 == 1); 9879#L324-26 is_master_triggered_~__retres1~0 := 0; 9886#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9917#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 10107#L839-24 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 10070#L839-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10071#L343-24 assume ~t1_pc~0 == 1; 10102#L344-8 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 10103#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10099#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 10100#L847-24 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 10304#L847-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10305#L362-24 assume ~t2_pc~0 == 1; 10297#L363-8 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 10185#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10186#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 10296#L855-24 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 10393#L855-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10394#L381-24 assume ~t3_pc~0 == 1; 10402#L382-8 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 10368#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10369#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 9918#L863-24 assume !(activate_threads_~tmp___2~0 != 0); 9919#L863-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9728#L400-24 assume ~t4_pc~0 == 1; 9729#L401-8 assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 9742#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9787#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9912#L871-24 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 10161#L871-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10032#L419-24 assume ~t5_pc~0 == 1; 10033#L420-8 assume ~E_5~0 == 1;is_transmit5_triggered_~__retres1~5 := 1; 9998#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 10062#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 10168#L879-24 assume activate_threads_~tmp___4~0 != 0;~t5_st~0 := 0; 10189#L879-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 10197#L438-24 assume ~t6_pc~0 == 1; 10246#L439-8 assume ~E_6~0 == 1;is_transmit6_triggered_~__retres1~6 := 1; 10247#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 10242#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 10243#L887-24 assume activate_threads_~tmp___5~0 != 0;~t6_st~0 := 0; 10347#L887-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9825#L752-3 assume ~M_E~0 == 1;~M_E~0 := 2; 9826#L752-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 9829#L757-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 10149#L762-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 10150#L767-3 assume ~T4_E~0 == 1;~T4_E~0 := 2; 10030#L772-3 assume ~T5_E~0 == 1;~T5_E~0 := 2; 10031#L777-3 assume !(~T6_E~0 == 1); 10288#L782-3 assume !(~E_M~0 == 1); 9895#L787-3 assume ~E_1~0 == 1;~E_1~0 := 2; 9896#L792-3 assume ~E_2~0 == 1;~E_2~0 := 2; 9761#L797-3 assume ~E_3~0 == 1;~E_3~0 := 2; 9762#L802-3 assume ~E_4~0 == 1;~E_4~0 := 2; 9817#L807-3 assume ~E_5~0 == 1;~E_5~0 := 2; 9818#L812-3 assume ~E_6~0 == 1;~E_6~0 := 2; 10143#L817-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 10011#L508-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 9811#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 9883#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 9922#L1062 assume !(start_simulation_~tmp~3 == 0); 9902#L1062-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 9903#L508-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 9813#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 9889#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 9766#L1017 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 9767#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 10058#L1025 start_simulation_#t~ret18 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 10059#L1075 assume !(start_simulation_~tmp___0~1 != 0); 10160#L1043-3 [2018-11-10 06:54:03,698 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:03,698 INFO L82 PathProgramCache]: Analyzing trace with hash 1964365639, now seen corresponding path program 1 times [2018-11-10 06:54:03,698 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:03,699 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:03,699 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:03,699 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 06:54:03,699 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:03,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:03,736 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:03,737 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:03,737 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 06:54:03,738 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 06:54:03,738 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:03,738 INFO L82 PathProgramCache]: Analyzing trace with hash 1622781534, now seen corresponding path program 1 times [2018-11-10 06:54:03,738 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:03,738 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:03,741 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:03,741 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:03,741 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:03,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:03,779 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:03,779 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:03,779 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:54:03,779 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 06:54:03,779 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 06:54:03,779 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 06:54:03,780 INFO L87 Difference]: Start difference. First operand 690 states and 1009 transitions. cyclomatic complexity: 320 Second operand 3 states. [2018-11-10 06:54:03,850 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:54:03,851 INFO L93 Difference]: Finished difference Result 1228 states and 1780 transitions. [2018-11-10 06:54:03,851 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 06:54:03,852 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1228 states and 1780 transitions. [2018-11-10 06:54:03,857 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1136 [2018-11-10 06:54:03,862 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1228 states to 1228 states and 1780 transitions. [2018-11-10 06:54:03,862 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1228 [2018-11-10 06:54:03,864 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1228 [2018-11-10 06:54:03,864 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1228 states and 1780 transitions. [2018-11-10 06:54:03,866 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:54:03,866 INFO L705 BuchiCegarLoop]: Abstraction has 1228 states and 1780 transitions. [2018-11-10 06:54:03,867 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1228 states and 1780 transitions. [2018-11-10 06:54:03,880 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1228 to 1225. [2018-11-10 06:54:03,880 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1225 states. [2018-11-10 06:54:03,883 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1225 states to 1225 states and 1777 transitions. [2018-11-10 06:54:03,883 INFO L728 BuchiCegarLoop]: Abstraction has 1225 states and 1777 transitions. [2018-11-10 06:54:03,883 INFO L608 BuchiCegarLoop]: Abstraction has 1225 states and 1777 transitions. [2018-11-10 06:54:03,883 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ [2018-11-10 06:54:03,883 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1225 states and 1777 transitions. [2018-11-10 06:54:03,887 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1133 [2018-11-10 06:54:03,887 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:54:03,887 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:54:03,888 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:03,888 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:03,888 INFO L793 eck$LassoCheckResult]: Stem: 12253#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 12142#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 11693#L1006 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 11694#L458 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12066#L465 assume ~m_i~0 == 1;~m_st~0 := 0; 12067#L465-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 12071#L470-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 11937#L475-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 11938#L480-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 11994#L485-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 11783#L490-1 assume ~t6_i~0 == 1;~t6_st~0 := 0; 11784#L495-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12078#L674 assume !(~M_E~0 == 0); 12079#L674-2 assume !(~T1_E~0 == 0); 12088#L679-1 assume !(~T2_E~0 == 0); 11958#L684-1 assume !(~T3_E~0 == 0); 11959#L689-1 assume !(~T4_E~0 == 0); 12233#L694-1 assume !(~T5_E~0 == 0); 11822#L699-1 assume !(~T6_E~0 == 0); 11823#L704-1 assume !(~E_M~0 == 0); 11647#L709-1 assume !(~E_1~0 == 0); 11648#L714-1 assume !(~E_2~0 == 0); 11744#L719-1 assume !(~E_3~0 == 0); 11745#L724-1 assume !(~E_4~0 == 0); 12076#L729-1 assume !(~E_5~0 == 0); 12077#L734-1 assume !(~E_6~0 == 0); 11950#L739-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11849#L324 assume !(~m_pc~0 == 1); 11794#L324-2 is_master_triggered_~__retres1~0 := 0; 11858#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11791#L336 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 11792#L839 assume !(activate_threads_~tmp~1 != 0); 12094#L839-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11892#L343 assume !(~t1_pc~0 == 1); 11893#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 11887#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11888#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 12039#L847 assume !(activate_threads_~tmp___0~0 != 0); 12276#L847-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12212#L362 assume !(~t2_pc~0 == 1); 12156#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 12157#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12208#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 12271#L855 assume !(activate_threads_~tmp___1~0 != 0); 12282#L855-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12287#L381 assume ~t3_pc~0 == 1; 12322#L382 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 12319#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12320#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 11708#L863 assume !(activate_threads_~tmp___2~0 != 0); 11676#L863-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11677#L400 assume ~t4_pc~0 == 1; 11740#L401 assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 11723#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11739#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 11868#L871 assume !(activate_threads_~tmp___3~0 != 0); 11969#L871-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 11976#L419 assume !(~t5_pc~0 == 1); 11876#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 11875#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 11939#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 11940#L879 assume activate_threads_~tmp___4~0 != 0;~t5_st~0 := 0; 12223#L879-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 12224#L438 assume ~t6_pc~0 == 1; 12197#L439 assume ~E_6~0 == 1;is_transmit6_triggered_~__retres1~6 := 1; 12198#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 12195#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 12196#L887 assume !(activate_threads_~tmp___5~0 != 0); 12337#L887-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11760#L752 assume !(~M_E~0 == 1); 11746#L752-2 assume !(~T1_E~0 == 1); 11747#L757-1 assume !(~T2_E~0 == 1); 12073#L762-1 assume ~T3_E~0 == 1;~T3_E~0 := 2; 12074#L767-1 assume !(~T4_E~0 == 1); 11947#L772-1 assume !(~T5_E~0 == 1); 11948#L777-1 assume !(~T6_E~0 == 1); 12231#L782-1 assume !(~E_M~0 == 1); 11816#L787-1 assume !(~E_1~0 == 1); 11817#L792-1 assume !(~E_2~0 == 1); 11678#L797-1 assume !(~E_3~0 == 1); 11679#L802-1 assume ~E_4~0 == 1;~E_4~0 := 2; 11758#L807-1 assume !(~E_5~0 == 1); 11759#L812-1 assume !(~E_6~0 == 1); 12096#L817-1 assume { :end_inline_reset_delta_events } true; 12097#L1043-3 [2018-11-10 06:54:03,888 INFO L795 eck$LassoCheckResult]: Loop: 12097#L1043-3 assume true; 12340#L1043-1 assume !false; 12228#L1044 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 11851#L649 assume true; 11671#L555-1 assume !false; 11672#L556 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 11803#L508 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 11733#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 11807#L546 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 12220#L560 assume !(eval_~tmp~0 != 0); 11748#L664 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 11749#L458-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 12089#L674-3 assume ~M_E~0 == 0;~M_E~0 := 1; 12058#L674-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 12059#L679-3 assume !(~T2_E~0 == 0); 11922#L684-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 11923#L689-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 11995#L694-3 assume ~T5_E~0 == 0;~T5_E~0 := 1; 11799#L699-3 assume ~T6_E~0 == 0;~T6_E~0 := 1; 11800#L704-3 assume !(~E_M~0 == 0); 11662#L709-3 assume ~E_1~0 == 0;~E_1~0 := 1; 11663#L714-3 assume ~E_2~0 == 0;~E_2~0 := 1; 11752#L719-3 assume !(~E_3~0 == 0); 11753#L724-3 assume ~E_4~0 == 0;~E_4~0 := 1; 12086#L729-3 assume ~E_5~0 == 0;~E_5~0 := 1; 12087#L734-3 assume ~E_6~0 == 0;~E_6~0 := 1; 11962#L739-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11804#L324-24 assume !(~m_pc~0 == 1); 11805#L324-26 is_master_triggered_~__retres1~0 := 0; 11811#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11842#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 12033#L839-24 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 11996#L839-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11997#L343-24 assume !(~t1_pc~0 == 1); 12060#L343-26 is_transmit1_triggered_~__retres1~1 := 0; 12061#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12025#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 12026#L847-24 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 12248#L847-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12249#L362-24 assume ~t2_pc~0 == 1; 12241#L363-8 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 12128#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12129#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 12240#L855-24 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 12338#L855-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12339#L381-24 assume ~t3_pc~0 == 1; 12347#L382-8 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 12313#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12314#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 11843#L863-24 assume !(activate_threads_~tmp___2~0 != 0); 11844#L863-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11653#L400-24 assume ~t4_pc~0 == 1; 11654#L401-8 assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 11667#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11712#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 11837#L871-24 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 12101#L871-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 11960#L419-24 assume !(~t5_pc~0 == 1); 11924#L419-26 is_transmit5_triggered_~__retres1~5 := 0; 11925#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 11988#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 12111#L879-24 assume activate_threads_~tmp___4~0 != 0;~t5_st~0 := 0; 12133#L879-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 12140#L438-24 assume ~t6_pc~0 == 1; 12189#L439-8 assume ~E_6~0 == 1;is_transmit6_triggered_~__retres1~6 := 1; 12190#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 12185#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 12186#L887-24 assume activate_threads_~tmp___5~0 != 0;~t6_st~0 := 0; 12291#L887-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11750#L752-3 assume ~M_E~0 == 1;~M_E~0 := 2; 11751#L752-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 11754#L757-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 12082#L762-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 12083#L767-3 assume ~T4_E~0 == 1;~T4_E~0 := 2; 11956#L772-3 assume ~T5_E~0 == 1;~T5_E~0 := 2; 11957#L777-3 assume !(~T6_E~0 == 1); 12232#L782-3 assume !(~E_M~0 == 1); 11820#L787-3 assume ~E_1~0 == 1;~E_1~0 := 2; 11821#L792-3 assume ~E_2~0 == 1;~E_2~0 := 2; 11686#L797-3 assume ~E_3~0 == 1;~E_3~0 := 2; 11687#L802-3 assume ~E_4~0 == 1;~E_4~0 := 2; 11742#L807-3 assume ~E_5~0 == 1;~E_5~0 := 2; 11743#L812-3 assume ~E_6~0 == 1;~E_6~0 := 2; 12075#L817-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 11936#L508-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 11736#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 11810#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 11847#L1062 assume !(start_simulation_~tmp~3 == 0); 11828#L1062-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 11829#L508-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 11738#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 11814#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 11691#L1017 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 11692#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 11984#L1025 start_simulation_#t~ret18 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 11985#L1075 assume !(start_simulation_~tmp___0~1 != 0); 12097#L1043-3 [2018-11-10 06:54:03,889 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:03,889 INFO L82 PathProgramCache]: Analyzing trace with hash -136475576, now seen corresponding path program 1 times [2018-11-10 06:54:03,889 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:03,889 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:03,889 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:03,889 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:03,890 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:03,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:03,921 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:03,921 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:03,921 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 06:54:03,921 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 06:54:03,922 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:03,922 INFO L82 PathProgramCache]: Analyzing trace with hash 1242781792, now seen corresponding path program 1 times [2018-11-10 06:54:03,922 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:03,922 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:03,922 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:03,923 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:03,923 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:03,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:03,954 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:03,955 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:03,955 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:54:03,955 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 06:54:03,955 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 06:54:03,955 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 06:54:03,955 INFO L87 Difference]: Start difference. First operand 1225 states and 1777 transitions. cyclomatic complexity: 554 Second operand 3 states. [2018-11-10 06:54:04,034 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:54:04,034 INFO L93 Difference]: Finished difference Result 2241 states and 3228 transitions. [2018-11-10 06:54:04,034 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 06:54:04,035 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2241 states and 3228 transitions. [2018-11-10 06:54:04,043 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2144 [2018-11-10 06:54:04,051 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2241 states to 2241 states and 3228 transitions. [2018-11-10 06:54:04,051 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2241 [2018-11-10 06:54:04,053 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2241 [2018-11-10 06:54:04,053 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2241 states and 3228 transitions. [2018-11-10 06:54:04,056 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:54:04,056 INFO L705 BuchiCegarLoop]: Abstraction has 2241 states and 3228 transitions. [2018-11-10 06:54:04,058 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2241 states and 3228 transitions. [2018-11-10 06:54:04,080 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2241 to 2235. [2018-11-10 06:54:04,081 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2235 states. [2018-11-10 06:54:04,085 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2235 states to 2235 states and 3222 transitions. [2018-11-10 06:54:04,085 INFO L728 BuchiCegarLoop]: Abstraction has 2235 states and 3222 transitions. [2018-11-10 06:54:04,085 INFO L608 BuchiCegarLoop]: Abstraction has 2235 states and 3222 transitions. [2018-11-10 06:54:04,085 INFO L442 BuchiCegarLoop]: ======== Iteration 10============ [2018-11-10 06:54:04,086 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2235 states and 3222 transitions. [2018-11-10 06:54:04,092 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2138 [2018-11-10 06:54:04,092 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:54:04,092 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:54:04,093 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:04,093 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:04,094 INFO L793 eck$LassoCheckResult]: Stem: 15738#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 15622#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 15166#L1006 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 15167#L458 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15546#L465 assume ~m_i~0 == 1;~m_st~0 := 0; 15547#L465-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 15550#L470-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 15419#L475-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 15420#L480-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 15477#L485-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 15258#L490-1 assume ~t6_i~0 == 1;~t6_st~0 := 0; 15259#L495-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15557#L674 assume !(~M_E~0 == 0); 15558#L674-2 assume !(~T1_E~0 == 0); 15567#L679-1 assume !(~T2_E~0 == 0); 15439#L684-1 assume !(~T3_E~0 == 0); 15440#L689-1 assume !(~T4_E~0 == 0); 15717#L694-1 assume !(~T5_E~0 == 0); 15297#L699-1 assume !(~T6_E~0 == 0); 15298#L704-1 assume !(~E_M~0 == 0); 15120#L709-1 assume !(~E_1~0 == 0); 15121#L714-1 assume !(~E_2~0 == 0); 15219#L719-1 assume !(~E_3~0 == 0); 15220#L724-1 assume !(~E_4~0 == 0); 15555#L729-1 assume !(~E_5~0 == 0); 15556#L734-1 assume !(~E_6~0 == 0); 15432#L739-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15327#L324 assume !(~m_pc~0 == 1); 15269#L324-2 is_master_triggered_~__retres1~0 := 0; 15338#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15266#L336 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 15267#L839 assume !(activate_threads_~tmp~1 != 0); 15572#L839-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15374#L343 assume !(~t1_pc~0 == 1); 15375#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 15369#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15370#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 15522#L847 assume !(activate_threads_~tmp___0~0 != 0); 15763#L847-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15692#L362 assume !(~t2_pc~0 == 1); 15636#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 15637#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15688#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 15756#L855 assume !(activate_threads_~tmp___1~0 != 0); 15768#L855-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15774#L381 assume !(~t3_pc~0 == 1); 15810#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 15807#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15808#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 15181#L863 assume !(activate_threads_~tmp___2~0 != 0); 15149#L863-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 15150#L400 assume ~t4_pc~0 == 1; 15214#L401 assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 15196#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 15213#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 15347#L871 assume !(activate_threads_~tmp___3~0 != 0); 15452#L871-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 15459#L419 assume !(~t5_pc~0 == 1); 15358#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 15357#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 15421#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 15422#L879 assume activate_threads_~tmp___4~0 != 0;~t5_st~0 := 0; 15705#L879-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 15706#L438 assume ~t6_pc~0 == 1; 15677#L439 assume ~E_6~0 == 1;is_transmit6_triggered_~__retres1~6 := 1; 15678#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 15675#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 15676#L887 assume !(activate_threads_~tmp___5~0 != 0); 15826#L887-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15235#L752 assume !(~M_E~0 == 1); 15221#L752-2 assume !(~T1_E~0 == 1); 15222#L757-1 assume !(~T2_E~0 == 1); 15552#L762-1 assume ~T3_E~0 == 1;~T3_E~0 := 2; 15553#L767-1 assume !(~T4_E~0 == 1); 15429#L772-1 assume !(~T5_E~0 == 1); 15430#L777-1 assume !(~T6_E~0 == 1); 15715#L782-1 assume !(~E_M~0 == 1); 15291#L787-1 assume !(~E_1~0 == 1); 15292#L792-1 assume !(~E_2~0 == 1); 15151#L797-1 assume !(~E_3~0 == 1); 15152#L802-1 assume ~E_4~0 == 1;~E_4~0 := 2; 15233#L807-1 assume !(~E_5~0 == 1); 15234#L812-1 assume !(~E_6~0 == 1); 15573#L817-1 assume { :end_inline_reset_delta_events } true; 15574#L1043-3 [2018-11-10 06:54:04,094 INFO L795 eck$LassoCheckResult]: Loop: 15574#L1043-3 assume true; 16033#L1043-1 assume !false; 16027#L1044 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 16022#L649 assume true; 16021#L555-1 assume !false; 16020#L556 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 16019#L508 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 16012#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 15822#L546 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 15700#L560 assume !(eval_~tmp~0 != 0); 15702#L664 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 16376#L458-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 16374#L674-3 assume ~M_E~0 == 0;~M_E~0 := 1; 16372#L674-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 16370#L679-3 assume !(~T2_E~0 == 0); 16368#L684-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 16366#L689-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 16363#L694-3 assume ~T5_E~0 == 0;~T5_E~0 := 1; 16361#L699-3 assume ~T6_E~0 == 0;~T6_E~0 := 1; 16359#L704-3 assume !(~E_M~0 == 0); 16357#L709-3 assume ~E_1~0 == 0;~E_1~0 := 1; 16355#L714-3 assume ~E_2~0 == 0;~E_2~0 := 1; 16353#L719-3 assume !(~E_3~0 == 0); 16351#L724-3 assume ~E_4~0 == 0;~E_4~0 := 1; 16349#L729-3 assume ~E_5~0 == 0;~E_5~0 := 1; 16347#L734-3 assume ~E_6~0 == 0;~E_6~0 := 1; 16345#L739-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16341#L324-24 assume !(~m_pc~0 == 1); 16339#L324-26 is_master_triggered_~__retres1~0 := 0; 16337#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16335#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 16333#L839-24 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 16331#L839-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16329#L343-24 assume !(~t1_pc~0 == 1); 16327#L343-26 is_transmit1_triggered_~__retres1~1 := 0; 16326#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16325#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 16324#L847-24 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 16323#L847-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16322#L362-24 assume !(~t2_pc~0 == 1); 16320#L362-26 is_transmit2_triggered_~__retres1~2 := 0; 16319#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16318#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 16317#L855-24 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 16316#L855-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 16313#L381-24 assume !(~t3_pc~0 == 1); 16311#L381-26 is_transmit3_triggered_~__retres1~3 := 0; 16309#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 16307#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 16305#L863-24 assume !(activate_threads_~tmp___2~0 != 0); 16303#L863-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 16301#L400-24 assume ~t4_pc~0 == 1; 16298#L401-8 assume ~E_4~0 == 1;is_transmit4_triggered_~__retres1~4 := 1; 16296#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 16294#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 16292#L871-24 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 16290#L871-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 16288#L419-24 assume !(~t5_pc~0 == 1); 16284#L419-26 is_transmit5_triggered_~__retres1~5 := 0; 16282#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 16280#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 16278#L879-24 assume activate_threads_~tmp___4~0 != 0;~t5_st~0 := 0; 16276#L879-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 16274#L438-24 assume ~t6_pc~0 == 1; 16246#L439-8 assume ~E_6~0 == 1;is_transmit6_triggered_~__retres1~6 := 1; 16244#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 16242#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 16240#L887-24 assume activate_threads_~tmp___5~0 != 0;~t6_st~0 := 0; 16238#L887-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16235#L752-3 assume ~M_E~0 == 1;~M_E~0 := 2; 16233#L752-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 16231#L757-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 16229#L762-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 16227#L767-3 assume ~T4_E~0 == 1;~T4_E~0 := 2; 16225#L772-3 assume ~T5_E~0 == 1;~T5_E~0 := 2; 16223#L777-3 assume !(~T6_E~0 == 1); 16221#L782-3 assume !(~E_M~0 == 1); 16219#L787-3 assume ~E_1~0 == 1;~E_1~0 := 2; 16217#L792-3 assume ~E_2~0 == 1;~E_2~0 := 2; 16215#L797-3 assume ~E_3~0 == 1;~E_3~0 := 2; 16213#L802-3 assume ~E_4~0 == 1;~E_4~0 := 2; 16210#L807-3 assume ~E_5~0 == 1;~E_5~0 := 2; 16208#L812-3 assume ~E_6~0 == 1;~E_6~0 := 2; 16206#L817-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 16197#L508-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 16193#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 16191#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 16188#L1062 assume !(start_simulation_~tmp~3 == 0); 16185#L1062-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 16094#L508-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 16082#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 16076#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 16071#L1017 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 16064#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 16056#L1025 start_simulation_#t~ret18 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 16046#L1075 assume !(start_simulation_~tmp___0~1 != 0); 15574#L1043-3 [2018-11-10 06:54:04,094 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:04,094 INFO L82 PathProgramCache]: Analyzing trace with hash -1093403959, now seen corresponding path program 1 times [2018-11-10 06:54:04,094 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:04,094 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:04,095 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:04,095 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:04,095 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:04,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:04,118 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:04,118 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:04,118 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 06:54:04,119 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 06:54:04,119 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:04,119 INFO L82 PathProgramCache]: Analyzing trace with hash -617792094, now seen corresponding path program 1 times [2018-11-10 06:54:04,119 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:04,119 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:04,119 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:04,120 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:04,120 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:04,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:04,140 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:04,140 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:04,140 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:54:04,140 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 06:54:04,141 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 06:54:04,141 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 06:54:04,141 INFO L87 Difference]: Start difference. First operand 2235 states and 3222 transitions. cyclomatic complexity: 991 Second operand 3 states. [2018-11-10 06:54:04,198 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:54:04,198 INFO L93 Difference]: Finished difference Result 4148 states and 5945 transitions. [2018-11-10 06:54:04,200 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 06:54:04,200 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4148 states and 5945 transitions. [2018-11-10 06:54:04,215 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4036 [2018-11-10 06:54:04,231 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4148 states to 4148 states and 5945 transitions. [2018-11-10 06:54:04,231 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4148 [2018-11-10 06:54:04,234 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4148 [2018-11-10 06:54:04,234 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4148 states and 5945 transitions. [2018-11-10 06:54:04,239 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:54:04,239 INFO L705 BuchiCegarLoop]: Abstraction has 4148 states and 5945 transitions. [2018-11-10 06:54:04,242 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4148 states and 5945 transitions. [2018-11-10 06:54:04,280 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4148 to 4136. [2018-11-10 06:54:04,281 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4136 states. [2018-11-10 06:54:04,290 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4136 states to 4136 states and 5933 transitions. [2018-11-10 06:54:04,290 INFO L728 BuchiCegarLoop]: Abstraction has 4136 states and 5933 transitions. [2018-11-10 06:54:04,291 INFO L608 BuchiCegarLoop]: Abstraction has 4136 states and 5933 transitions. [2018-11-10 06:54:04,291 INFO L442 BuchiCegarLoop]: ======== Iteration 11============ [2018-11-10 06:54:04,291 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4136 states and 5933 transitions. [2018-11-10 06:54:04,303 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4024 [2018-11-10 06:54:04,303 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:54:04,303 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:54:04,304 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:04,304 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:04,304 INFO L793 eck$LassoCheckResult]: Stem: 22132#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 22011#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 21554#L1006 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 21555#L458 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21941#L465 assume ~m_i~0 == 1;~m_st~0 := 0; 21942#L465-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 21945#L470-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 21815#L475-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 21816#L480-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 21872#L485-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 21641#L490-1 assume ~t6_i~0 == 1;~t6_st~0 := 0; 21642#L495-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21952#L674 assume !(~M_E~0 == 0); 21953#L674-2 assume !(~T1_E~0 == 0); 21961#L679-1 assume !(~T2_E~0 == 0); 21835#L684-1 assume !(~T3_E~0 == 0); 21836#L689-1 assume !(~T4_E~0 == 0); 22110#L694-1 assume !(~T5_E~0 == 0); 21681#L699-1 assume !(~T6_E~0 == 0); 21682#L704-1 assume !(~E_M~0 == 0); 21510#L709-1 assume !(~E_1~0 == 0); 21511#L714-1 assume !(~E_2~0 == 0); 21602#L719-1 assume !(~E_3~0 == 0); 21603#L724-1 assume !(~E_4~0 == 0); 21950#L729-1 assume !(~E_5~0 == 0); 21951#L734-1 assume !(~E_6~0 == 0); 21828#L739-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 21711#L324 assume !(~m_pc~0 == 1); 21652#L324-2 is_master_triggered_~__retres1~0 := 0; 21726#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 21649#L336 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 21650#L839 assume !(activate_threads_~tmp~1 != 0); 21965#L839-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 21770#L343 assume !(~t1_pc~0 == 1); 21771#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 21765#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 21766#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 21917#L847 assume !(activate_threads_~tmp___0~0 != 0); 22158#L847-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22082#L362 assume !(~t2_pc~0 == 1); 22025#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 22026#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22078#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 22150#L855 assume !(activate_threads_~tmp___1~0 != 0); 22165#L855-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22169#L381 assume !(~t3_pc~0 == 1); 22203#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 22200#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 22201#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 21569#L863 assume !(activate_threads_~tmp___2~0 != 0); 21538#L863-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 21539#L400 assume !(~t4_pc~0 == 1); 21583#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 21584#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 21598#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 21739#L871 assume !(activate_threads_~tmp___3~0 != 0); 21847#L871-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 21854#L419 assume !(~t5_pc~0 == 1); 21754#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 21753#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 21817#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 21818#L879 assume activate_threads_~tmp___4~0 != 0;~t5_st~0 := 0; 22097#L879-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 22098#L438 assume ~t6_pc~0 == 1; 22067#L439 assume ~E_6~0 == 1;is_transmit6_triggered_~__retres1~6 := 1; 22068#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 22065#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 22066#L887 assume !(activate_threads_~tmp___5~0 != 0); 22218#L887-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21618#L752 assume !(~M_E~0 == 1); 21604#L752-2 assume !(~T1_E~0 == 1); 21605#L757-1 assume !(~T2_E~0 == 1); 21947#L762-1 assume ~T3_E~0 == 1;~T3_E~0 := 2; 21948#L767-1 assume !(~T4_E~0 == 1); 21825#L772-1 assume !(~T5_E~0 == 1); 21826#L777-1 assume !(~T6_E~0 == 1); 22108#L782-1 assume !(~E_M~0 == 1); 21674#L787-1 assume !(~E_1~0 == 1); 21675#L792-1 assume !(~E_2~0 == 1); 21540#L797-1 assume !(~E_3~0 == 1); 21541#L802-1 assume ~E_4~0 == 1;~E_4~0 := 2; 21616#L807-1 assume !(~E_5~0 == 1); 21617#L812-1 assume !(~E_6~0 == 1); 21966#L817-1 assume { :end_inline_reset_delta_events } true; 21967#L1043-3 [2018-11-10 06:54:04,305 INFO L795 eck$LassoCheckResult]: Loop: 21967#L1043-3 assume true; 22221#L1043-1 assume !false; 22101#L1044 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 21713#L649 assume true; 21534#L555-1 assume !false; 21535#L556 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 21661#L508 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 21592#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 21665#L546 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 22093#L560 assume !(eval_~tmp~0 != 0); 22095#L664 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 25464#L458-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 25462#L674-3 assume ~M_E~0 == 0;~M_E~0 := 1; 25460#L674-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 25458#L679-3 assume !(~T2_E~0 == 0); 25456#L684-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 25454#L689-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 25452#L694-3 assume ~T5_E~0 == 0;~T5_E~0 := 1; 25451#L699-3 assume ~T6_E~0 == 0;~T6_E~0 := 1; 25450#L704-3 assume !(~E_M~0 == 0); 25448#L709-3 assume ~E_1~0 == 0;~E_1~0 := 1; 25446#L714-3 assume ~E_2~0 == 0;~E_2~0 := 1; 25445#L719-3 assume !(~E_3~0 == 0); 25443#L724-3 assume ~E_4~0 == 0;~E_4~0 := 1; 25441#L729-3 assume ~E_5~0 == 0;~E_5~0 := 1; 25438#L734-3 assume ~E_6~0 == 0;~E_6~0 := 1; 25436#L739-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 25434#L324-24 assume !(~m_pc~0 == 1); 25433#L324-26 is_master_triggered_~__retres1~0 := 0; 25431#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 25429#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 25427#L839-24 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 25426#L839-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 25152#L343-24 assume !(~t1_pc~0 == 1); 25151#L343-26 is_transmit1_triggered_~__retres1~1 := 0; 25149#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 25147#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 25145#L847-24 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 25131#L847-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 25128#L362-24 assume !(~t2_pc~0 == 1); 25125#L362-26 is_transmit2_triggered_~__retres1~2 := 0; 25123#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 25121#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 25119#L855-24 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 25117#L855-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 25114#L381-24 assume !(~t3_pc~0 == 1); 25112#L381-26 is_transmit3_triggered_~__retres1~3 := 0; 25110#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 25108#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 25106#L863-24 assume !(activate_threads_~tmp___2~0 != 0); 25104#L863-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 25101#L400-24 assume !(~t4_pc~0 == 1); 25099#L400-26 is_transmit4_triggered_~__retres1~4 := 0; 25097#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 25095#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 25093#L871-24 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 25039#L871-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 25034#L419-24 assume !(~t5_pc~0 == 1); 25028#L419-26 is_transmit5_triggered_~__retres1~5 := 0; 25026#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 25024#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 25022#L879-24 assume activate_threads_~tmp___4~0 != 0;~t5_st~0 := 0; 25020#L879-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 25018#L438-24 assume ~t6_pc~0 == 1; 25014#L439-8 assume ~E_6~0 == 1;is_transmit6_triggered_~__retres1~6 := 1; 25012#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 25010#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 25008#L887-24 assume activate_threads_~tmp___5~0 != 0;~t6_st~0 := 0; 25006#L887-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25004#L752-3 assume ~M_E~0 == 1;~M_E~0 := 2; 25001#L752-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 24999#L757-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 24997#L762-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 24995#L767-3 assume ~T4_E~0 == 1;~T4_E~0 := 2; 24993#L772-3 assume ~T5_E~0 == 1;~T5_E~0 := 2; 24991#L777-3 assume !(~T6_E~0 == 1); 24990#L782-3 assume !(~E_M~0 == 1); 24989#L787-3 assume ~E_1~0 == 1;~E_1~0 := 2; 24988#L792-3 assume ~E_2~0 == 1;~E_2~0 := 2; 24984#L797-3 assume ~E_3~0 == 1;~E_3~0 := 2; 24980#L802-3 assume ~E_4~0 == 1;~E_4~0 := 2; 24975#L807-3 assume ~E_5~0 == 1;~E_5~0 := 2; 24968#L812-3 assume ~E_6~0 == 1;~E_6~0 := 2; 24965#L817-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 24943#L508-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 24914#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 24910#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 24894#L1062 assume !(start_simulation_~tmp~3 == 0); 24890#L1062-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 24868#L508-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 24855#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 22214#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 21552#L1017 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 21553#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 21862#L1025 start_simulation_#t~ret18 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 21863#L1075 assume !(start_simulation_~tmp___0~1 != 0); 21967#L1043-3 [2018-11-10 06:54:04,305 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:04,305 INFO L82 PathProgramCache]: Analyzing trace with hash 1625005578, now seen corresponding path program 1 times [2018-11-10 06:54:04,305 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:04,305 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:04,306 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:04,306 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:04,306 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:04,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:04,353 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:04,353 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:04,353 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 06:54:04,353 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 06:54:04,353 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:04,354 INFO L82 PathProgramCache]: Analyzing trace with hash -1491269789, now seen corresponding path program 1 times [2018-11-10 06:54:04,354 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:04,354 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:04,354 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:04,355 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:04,355 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:04,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:04,406 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:04,406 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:04,406 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:54:04,406 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 06:54:04,407 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 06:54:04,407 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 06:54:04,407 INFO L87 Difference]: Start difference. First operand 4136 states and 5933 transitions. cyclomatic complexity: 1805 Second operand 3 states. [2018-11-10 06:54:04,510 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:54:04,510 INFO L93 Difference]: Finished difference Result 7727 states and 11022 transitions. [2018-11-10 06:54:04,512 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 06:54:04,512 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7727 states and 11022 transitions. [2018-11-10 06:54:04,582 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7576 [2018-11-10 06:54:04,611 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7727 states to 7727 states and 11022 transitions. [2018-11-10 06:54:04,612 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7727 [2018-11-10 06:54:04,617 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7727 [2018-11-10 06:54:04,617 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7727 states and 11022 transitions. [2018-11-10 06:54:04,626 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:54:04,626 INFO L705 BuchiCegarLoop]: Abstraction has 7727 states and 11022 transitions. [2018-11-10 06:54:04,631 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7727 states and 11022 transitions. [2018-11-10 06:54:04,712 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7727 to 7703. [2018-11-10 06:54:04,713 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7703 states. [2018-11-10 06:54:04,726 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7703 states to 7703 states and 10998 transitions. [2018-11-10 06:54:04,726 INFO L728 BuchiCegarLoop]: Abstraction has 7703 states and 10998 transitions. [2018-11-10 06:54:04,726 INFO L608 BuchiCegarLoop]: Abstraction has 7703 states and 10998 transitions. [2018-11-10 06:54:04,726 INFO L442 BuchiCegarLoop]: ======== Iteration 12============ [2018-11-10 06:54:04,726 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7703 states and 10998 transitions. [2018-11-10 06:54:04,748 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7552 [2018-11-10 06:54:04,748 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:54:04,748 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:54:04,750 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:04,750 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:04,750 INFO L793 eck$LassoCheckResult]: Stem: 34030#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 33897#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 33422#L1006 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 33423#L458 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33819#L465 assume ~m_i~0 == 1;~m_st~0 := 0; 33820#L465-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 33824#L470-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 33689#L475-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 33690#L480-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 33745#L485-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 33510#L490-1 assume ~t6_i~0 == 1;~t6_st~0 := 0; 33511#L495-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33833#L674 assume !(~M_E~0 == 0); 33834#L674-2 assume !(~T1_E~0 == 0); 33845#L679-1 assume !(~T2_E~0 == 0); 33709#L684-1 assume !(~T3_E~0 == 0); 33710#L689-1 assume !(~T4_E~0 == 0); 34008#L694-1 assume !(~T5_E~0 == 0); 33550#L699-1 assume !(~T6_E~0 == 0); 33551#L704-1 assume !(~E_M~0 == 0); 33380#L709-1 assume !(~E_1~0 == 0); 33381#L714-1 assume !(~E_2~0 == 0); 33471#L719-1 assume !(~E_3~0 == 0); 33472#L724-1 assume !(~E_4~0 == 0); 33831#L729-1 assume !(~E_5~0 == 0); 33832#L734-1 assume !(~E_6~0 == 0); 33702#L739-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 33582#L324 assume !(~m_pc~0 == 1); 33521#L324-2 is_master_triggered_~__retres1~0 := 0; 33595#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 33518#L336 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 33519#L839 assume !(activate_threads_~tmp~1 != 0); 33849#L839-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 33644#L343 assume !(~t1_pc~0 == 1); 33645#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 33639#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 33640#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 33791#L847 assume !(activate_threads_~tmp___0~0 != 0); 34054#L847-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 33967#L362 assume !(~t2_pc~0 == 1); 33911#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 33912#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 33963#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 34048#L855 assume !(activate_threads_~tmp___1~0 != 0); 34061#L855-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 34065#L381 assume !(~t3_pc~0 == 1); 34098#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 34095#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 34096#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 33437#L863 assume !(activate_threads_~tmp___2~0 != 0); 33407#L863-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 33408#L400 assume !(~t4_pc~0 == 1); 33451#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 33452#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 33467#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 33614#L871 assume !(activate_threads_~tmp___3~0 != 0); 33720#L871-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 33727#L419 assume !(~t5_pc~0 == 1); 33628#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 33627#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 33691#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 33692#L879 assume activate_threads_~tmp___4~0 != 0;~t5_st~0 := 0; 33981#L879-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 33982#L438 assume !(~t6_pc~0 == 1); 33997#L438-2 is_transmit6_triggered_~__retres1~6 := 0; 33998#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 33953#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 33954#L887 assume !(activate_threads_~tmp___5~0 != 0); 34113#L887-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33487#L752 assume !(~M_E~0 == 1); 33473#L752-2 assume !(~T1_E~0 == 1); 33474#L757-1 assume !(~T2_E~0 == 1); 33826#L762-1 assume ~T3_E~0 == 1;~T3_E~0 := 2; 33827#L767-1 assume !(~T4_E~0 == 1); 33699#L772-1 assume !(~T5_E~0 == 1); 33700#L777-1 assume !(~T6_E~0 == 1); 34005#L782-1 assume !(~E_M~0 == 1); 33544#L787-1 assume !(~E_1~0 == 1); 33545#L792-1 assume !(~E_2~0 == 1); 33409#L797-1 assume !(~E_3~0 == 1); 33410#L802-1 assume ~E_4~0 == 1;~E_4~0 := 2; 33485#L807-1 assume !(~E_5~0 == 1); 33486#L812-1 assume !(~E_6~0 == 1); 33851#L817-1 assume { :end_inline_reset_delta_events } true; 33852#L1043-3 [2018-11-10 06:54:04,750 INFO L795 eck$LassoCheckResult]: Loop: 33852#L1043-3 assume true; 34116#L1043-1 assume !false; 33987#L1044 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 33841#L649 assume true; 33403#L555-1 assume !false; 33404#L556 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 33530#L508 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 33461#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 33534#L546 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 33977#L560 assume !(eval_~tmp~0 != 0); 33475#L664 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 33476#L458-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 33846#L674-3 assume ~M_E~0 == 0;~M_E~0 := 1; 33810#L674-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 33811#L679-3 assume !(~T2_E~0 == 0); 33674#L684-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 33675#L689-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 33747#L694-3 assume ~T5_E~0 == 0;~T5_E~0 := 1; 33526#L699-3 assume ~T6_E~0 == 0;~T6_E~0 := 1; 33527#L704-3 assume !(~E_M~0 == 0); 33394#L709-3 assume ~E_1~0 == 0;~E_1~0 := 1; 33395#L714-3 assume ~E_2~0 == 0;~E_2~0 := 1; 33479#L719-3 assume !(~E_3~0 == 0); 33480#L724-3 assume ~E_4~0 == 0;~E_4~0 := 1; 33843#L729-3 assume ~E_5~0 == 0;~E_5~0 := 1; 33844#L734-3 assume ~E_6~0 == 0;~E_6~0 := 1; 33713#L739-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 33531#L324-24 assume !(~m_pc~0 == 1); 33532#L324-26 is_master_triggered_~__retres1~0 := 0; 33538#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 33575#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 33785#L839-24 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 33748#L839-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 33749#L343-24 assume !(~t1_pc~0 == 1); 33812#L343-26 is_transmit1_triggered_~__retres1~1 := 0; 33813#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 33777#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 33778#L847-24 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 34024#L847-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 34026#L362-24 assume ~t2_pc~0 == 1; 34017#L363-8 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 33881#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 33882#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 34016#L855-24 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 34114#L855-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 34115#L381-24 assume !(~t3_pc~0 == 1); 34152#L381-26 is_transmit3_triggered_~__retres1~3 := 0; 34089#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 34090#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 33576#L863-24 assume !(activate_threads_~tmp___2~0 != 0); 33577#L863-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 33386#L400-24 assume !(~t4_pc~0 == 1); 33387#L400-26 is_transmit4_triggered_~__retres1~4 := 0; 40837#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 40838#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 40928#L871-24 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 40926#L871-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 40924#L419-24 assume !(~t5_pc~0 == 1); 40919#L419-26 is_transmit5_triggered_~__retres1~5 := 0; 40918#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 40917#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 40916#L879-24 assume activate_threads_~tmp___4~0 != 0;~t5_st~0 := 0; 40915#L879-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 40727#L438-24 assume !(~t6_pc~0 == 1); 40726#L438-26 is_transmit6_triggered_~__retres1~6 := 0; 40725#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 40724#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 40723#L887-24 assume activate_threads_~tmp___5~0 != 0;~t6_st~0 := 0; 40722#L887-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40721#L752-3 assume ~M_E~0 == 1;~M_E~0 := 2; 40720#L752-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 40719#L757-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 40718#L762-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 40717#L767-3 assume ~T4_E~0 == 1;~T4_E~0 := 2; 40716#L772-3 assume ~T5_E~0 == 1;~T5_E~0 := 2; 40715#L777-3 assume !(~T6_E~0 == 1); 40714#L782-3 assume !(~E_M~0 == 1); 33548#L787-3 assume ~E_1~0 == 1;~E_1~0 := 2; 33549#L792-3 assume ~E_2~0 == 1;~E_2~0 := 2; 33416#L797-3 assume ~E_3~0 == 1;~E_3~0 := 2; 33417#L802-3 assume ~E_4~0 == 1;~E_4~0 := 2; 33986#L807-3 assume ~E_5~0 == 1;~E_5~0 := 2; 40596#L812-3 assume ~E_6~0 == 1;~E_6~0 := 2; 40595#L817-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 40590#L508-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 40587#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 40586#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 40581#L1062 assume !(start_simulation_~tmp~3 == 0); 33556#L1062-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 33557#L508-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 33466#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 33541#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 33420#L1017 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 33421#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 33735#L1025 start_simulation_#t~ret18 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 33736#L1075 assume !(start_simulation_~tmp___0~1 != 0); 33852#L1043-3 [2018-11-10 06:54:04,750 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:04,751 INFO L82 PathProgramCache]: Analyzing trace with hash 651516619, now seen corresponding path program 1 times [2018-11-10 06:54:04,751 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:04,751 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:04,751 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:04,751 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:04,752 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:04,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:04,789 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:04,789 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:04,789 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 06:54:04,790 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 06:54:04,790 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:04,790 INFO L82 PathProgramCache]: Analyzing trace with hash 986872419, now seen corresponding path program 1 times [2018-11-10 06:54:04,790 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:04,790 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:04,791 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:04,791 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:04,791 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:04,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:04,814 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:04,814 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:04,814 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:54:04,815 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 06:54:04,815 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 06:54:04,815 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 06:54:04,815 INFO L87 Difference]: Start difference. First operand 7703 states and 10998 transitions. cyclomatic complexity: 3311 Second operand 3 states. [2018-11-10 06:54:04,853 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:54:04,854 INFO L93 Difference]: Finished difference Result 7703 states and 10948 transitions. [2018-11-10 06:54:04,855 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 06:54:04,856 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7703 states and 10948 transitions. [2018-11-10 06:54:04,885 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7552 [2018-11-10 06:54:04,912 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7703 states to 7703 states and 10948 transitions. [2018-11-10 06:54:04,912 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7703 [2018-11-10 06:54:04,916 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7703 [2018-11-10 06:54:04,916 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7703 states and 10948 transitions. [2018-11-10 06:54:04,926 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:54:04,926 INFO L705 BuchiCegarLoop]: Abstraction has 7703 states and 10948 transitions. [2018-11-10 06:54:04,931 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7703 states and 10948 transitions. [2018-11-10 06:54:04,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7703 to 7703. [2018-11-10 06:54:04,992 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7703 states. [2018-11-10 06:54:05,004 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7703 states to 7703 states and 10948 transitions. [2018-11-10 06:54:05,005 INFO L728 BuchiCegarLoop]: Abstraction has 7703 states and 10948 transitions. [2018-11-10 06:54:05,005 INFO L608 BuchiCegarLoop]: Abstraction has 7703 states and 10948 transitions. [2018-11-10 06:54:05,005 INFO L442 BuchiCegarLoop]: ======== Iteration 13============ [2018-11-10 06:54:05,005 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7703 states and 10948 transitions. [2018-11-10 06:54:05,024 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7552 [2018-11-10 06:54:05,025 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:54:05,025 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:54:05,026 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:05,026 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:05,026 INFO L793 eck$LassoCheckResult]: Stem: 49430#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 49300#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 48835#L1006 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 48836#L458 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49226#L465 assume ~m_i~0 == 1;~m_st~0 := 0; 49227#L465-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 49231#L470-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 49096#L475-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 49097#L480-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 49153#L485-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 48924#L490-1 assume ~t6_i~0 == 1;~t6_st~0 := 0; 48925#L495-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49238#L674 assume !(~M_E~0 == 0); 49239#L674-2 assume !(~T1_E~0 == 0); 49250#L679-1 assume !(~T2_E~0 == 0); 49117#L684-1 assume !(~T3_E~0 == 0); 49118#L689-1 assume !(~T4_E~0 == 0); 49408#L694-1 assume !(~T5_E~0 == 0); 48963#L699-1 assume !(~T6_E~0 == 0); 48964#L704-1 assume !(~E_M~0 == 0); 48793#L709-1 assume !(~E_1~0 == 0); 48794#L714-1 assume !(~E_2~0 == 0); 48885#L719-1 assume !(~E_3~0 == 0); 48886#L724-1 assume !(~E_4~0 == 0); 49236#L729-1 assume !(~E_5~0 == 0); 49237#L734-1 assume !(~E_6~0 == 0); 49110#L739-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 48995#L324 assume !(~m_pc~0 == 1); 48935#L324-2 is_master_triggered_~__retres1~0 := 0; 49008#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 48932#L336 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 48933#L839 assume !(activate_threads_~tmp~1 != 0); 49256#L839-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 49051#L343 assume !(~t1_pc~0 == 1); 49052#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 49046#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 49047#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 49198#L847 assume !(activate_threads_~tmp___0~0 != 0); 49454#L847-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 49369#L362 assume !(~t2_pc~0 == 1); 49314#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 49315#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 49365#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 49448#L855 assume !(activate_threads_~tmp___1~0 != 0); 49464#L855-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 49468#L381 assume !(~t3_pc~0 == 1); 49504#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 49501#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 49502#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 48850#L863 assume !(activate_threads_~tmp___2~0 != 0); 48820#L863-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 48821#L400 assume !(~t4_pc~0 == 1); 48864#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 48865#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 48881#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 49024#L871 assume !(activate_threads_~tmp___3~0 != 0); 49128#L871-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 49135#L419 assume !(~t5_pc~0 == 1); 49035#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 49034#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 49099#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 49100#L879 assume activate_threads_~tmp___4~0 != 0;~t5_st~0 := 0; 49384#L879-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 49385#L438 assume !(~t6_pc~0 == 1); 49400#L438-2 is_transmit6_triggered_~__retres1~6 := 0; 49401#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 49354#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 49355#L887 assume !(activate_threads_~tmp___5~0 != 0); 49522#L887-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48901#L752 assume !(~M_E~0 == 1); 48887#L752-2 assume !(~T1_E~0 == 1); 48888#L757-1 assume !(~T2_E~0 == 1); 49233#L762-1 assume !(~T3_E~0 == 1); 49234#L767-1 assume !(~T4_E~0 == 1); 49107#L772-1 assume !(~T5_E~0 == 1); 49108#L777-1 assume !(~T6_E~0 == 1); 49406#L782-1 assume !(~E_M~0 == 1); 48957#L787-1 assume !(~E_1~0 == 1); 48958#L792-1 assume !(~E_2~0 == 1); 48822#L797-1 assume !(~E_3~0 == 1); 48823#L802-1 assume ~E_4~0 == 1;~E_4~0 := 2; 48899#L807-1 assume !(~E_5~0 == 1); 48900#L812-1 assume !(~E_6~0 == 1); 49258#L817-1 assume { :end_inline_reset_delta_events } true; 49259#L1043-3 [2018-11-10 06:54:05,026 INFO L795 eck$LassoCheckResult]: Loop: 49259#L1043-3 assume true; 53590#L1043-1 assume !false; 53588#L1044 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 53584#L649 assume true; 53582#L555-1 assume !false; 53580#L556 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 53577#L508 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 53569#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 53567#L546 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 53565#L560 assume !(eval_~tmp~0 != 0); 53566#L664 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 53786#L458-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 53784#L674-3 assume ~M_E~0 == 0;~M_E~0 := 1; 53782#L674-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 53780#L679-3 assume !(~T2_E~0 == 0); 53778#L684-3 assume !(~T3_E~0 == 0); 53776#L689-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 53774#L694-3 assume ~T5_E~0 == 0;~T5_E~0 := 1; 53771#L699-3 assume ~T6_E~0 == 0;~T6_E~0 := 1; 53769#L704-3 assume !(~E_M~0 == 0); 53767#L709-3 assume ~E_1~0 == 0;~E_1~0 := 1; 53765#L714-3 assume ~E_2~0 == 0;~E_2~0 := 1; 53763#L719-3 assume !(~E_3~0 == 0); 53761#L724-3 assume ~E_4~0 == 0;~E_4~0 := 1; 53759#L729-3 assume ~E_5~0 == 0;~E_5~0 := 1; 53757#L734-3 assume ~E_6~0 == 0;~E_6~0 := 1; 53755#L739-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 53751#L324-24 assume !(~m_pc~0 == 1); 53749#L324-26 is_master_triggered_~__retres1~0 := 0; 53747#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 53745#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 53743#L839-24 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 53741#L839-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 53739#L343-24 assume !(~t1_pc~0 == 1); 53737#L343-26 is_transmit1_triggered_~__retres1~1 := 0; 53734#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 53732#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 53730#L847-24 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 53728#L847-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 53726#L362-24 assume !(~t2_pc~0 == 1); 53723#L362-26 is_transmit2_triggered_~__retres1~2 := 0; 53721#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 53719#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 53717#L855-24 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 53715#L855-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 53713#L381-24 assume !(~t3_pc~0 == 1); 53711#L381-26 is_transmit3_triggered_~__retres1~3 := 0; 53709#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 53707#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 53705#L863-24 assume !(activate_threads_~tmp___2~0 != 0); 53703#L863-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 53701#L400-24 assume !(~t4_pc~0 == 1); 53699#L400-26 is_transmit4_triggered_~__retres1~4 := 0; 53697#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 53695#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 53693#L871-24 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 53691#L871-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 53689#L419-24 assume !(~t5_pc~0 == 1); 53686#L419-26 is_transmit5_triggered_~__retres1~5 := 0; 53684#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 53683#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 53682#L879-24 assume activate_threads_~tmp___4~0 != 0;~t5_st~0 := 0; 53681#L879-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 53680#L438-24 assume !(~t6_pc~0 == 1); 53679#L438-26 is_transmit6_triggered_~__retres1~6 := 0; 53678#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 53675#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 53673#L887-24 assume activate_threads_~tmp___5~0 != 0;~t6_st~0 := 0; 53671#L887-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53669#L752-3 assume ~M_E~0 == 1;~M_E~0 := 2; 53666#L752-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 53664#L757-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 53662#L762-3 assume !(~T3_E~0 == 1); 53660#L767-3 assume ~T4_E~0 == 1;~T4_E~0 := 2; 53658#L772-3 assume ~T5_E~0 == 1;~T5_E~0 := 2; 53656#L777-3 assume !(~T6_E~0 == 1); 53654#L782-3 assume !(~E_M~0 == 1); 53652#L787-3 assume ~E_1~0 == 1;~E_1~0 := 2; 53650#L792-3 assume ~E_2~0 == 1;~E_2~0 := 2; 53648#L797-3 assume ~E_3~0 == 1;~E_3~0 := 2; 53646#L802-3 assume ~E_4~0 == 1;~E_4~0 := 2; 53644#L807-3 assume ~E_5~0 == 1;~E_5~0 := 2; 53642#L812-3 assume ~E_6~0 == 1;~E_6~0 := 2; 53639#L817-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 53628#L508-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 53624#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 53622#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 53619#L1062 assume !(start_simulation_~tmp~3 == 0); 53616#L1062-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 53611#L508-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 53604#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 53602#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 53600#L1017 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 53598#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 53595#L1025 start_simulation_#t~ret18 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 53593#L1075 assume !(start_simulation_~tmp___0~1 != 0); 49259#L1043-3 [2018-11-10 06:54:05,026 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:05,026 INFO L82 PathProgramCache]: Analyzing trace with hash 909682057, now seen corresponding path program 1 times [2018-11-10 06:54:05,026 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:05,027 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:05,027 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:05,027 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:05,027 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:05,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:05,065 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:05,065 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:05,065 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 06:54:05,066 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 06:54:05,066 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:05,066 INFO L82 PathProgramCache]: Analyzing trace with hash 35288164, now seen corresponding path program 1 times [2018-11-10 06:54:05,066 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:05,066 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:05,067 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:05,067 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:05,067 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:05,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:05,091 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:05,091 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:05,091 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:54:05,091 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 06:54:05,091 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 06:54:05,091 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 06:54:05,092 INFO L87 Difference]: Start difference. First operand 7703 states and 10948 transitions. cyclomatic complexity: 3261 Second operand 3 states. [2018-11-10 06:54:05,178 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:54:05,178 INFO L93 Difference]: Finished difference Result 7703 states and 10842 transitions. [2018-11-10 06:54:05,178 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 06:54:05,178 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7703 states and 10842 transitions. [2018-11-10 06:54:05,203 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7552 [2018-11-10 06:54:05,221 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7703 states to 7703 states and 10842 transitions. [2018-11-10 06:54:05,222 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7703 [2018-11-10 06:54:05,226 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7703 [2018-11-10 06:54:05,226 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7703 states and 10842 transitions. [2018-11-10 06:54:05,234 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:54:05,234 INFO L705 BuchiCegarLoop]: Abstraction has 7703 states and 10842 transitions. [2018-11-10 06:54:05,239 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7703 states and 10842 transitions. [2018-11-10 06:54:05,299 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7703 to 7703. [2018-11-10 06:54:05,299 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7703 states. [2018-11-10 06:54:05,311 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7703 states to 7703 states and 10842 transitions. [2018-11-10 06:54:05,311 INFO L728 BuchiCegarLoop]: Abstraction has 7703 states and 10842 transitions. [2018-11-10 06:54:05,311 INFO L608 BuchiCegarLoop]: Abstraction has 7703 states and 10842 transitions. [2018-11-10 06:54:05,311 INFO L442 BuchiCegarLoop]: ======== Iteration 14============ [2018-11-10 06:54:05,311 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7703 states and 10842 transitions. [2018-11-10 06:54:05,330 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7552 [2018-11-10 06:54:05,330 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:54:05,330 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:54:05,331 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:05,331 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:05,331 INFO L793 eck$LassoCheckResult]: Stem: 64849#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 64726#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 64248#L1006 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 64249#L458 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 64645#L465 assume ~m_i~0 == 1;~m_st~0 := 0; 64646#L465-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 64651#L470-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 64508#L475-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 64509#L480-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 64570#L485-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 64338#L490-1 assume ~t6_i~0 == 1;~t6_st~0 := 0; 64339#L495-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 64658#L674 assume !(~M_E~0 == 0); 64659#L674-2 assume !(~T1_E~0 == 0); 64670#L679-1 assume !(~T2_E~0 == 0); 64530#L684-1 assume !(~T3_E~0 == 0); 64531#L689-1 assume !(~T4_E~0 == 0); 64827#L694-1 assume !(~T5_E~0 == 0); 64377#L699-1 assume !(~T6_E~0 == 0); 64378#L704-1 assume !(~E_M~0 == 0); 64206#L709-1 assume !(~E_1~0 == 0); 64207#L714-1 assume !(~E_2~0 == 0); 64299#L719-1 assume !(~E_3~0 == 0); 64300#L724-1 assume !(~E_4~0 == 0); 64656#L729-1 assume !(~E_5~0 == 0); 64657#L734-1 assume !(~E_6~0 == 0); 64523#L739-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 64411#L324 assume !(~m_pc~0 == 1); 64349#L324-2 is_master_triggered_~__retres1~0 := 0; 64423#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 64346#L336 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 64347#L839 assume !(activate_threads_~tmp~1 != 0); 64677#L839-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 64463#L343 assume !(~t1_pc~0 == 1); 64464#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 64458#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 64459#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 64615#L847 assume !(activate_threads_~tmp___0~0 != 0); 64873#L847-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 64794#L362 assume !(~t2_pc~0 == 1); 64740#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 64741#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 64790#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 64867#L855 assume !(activate_threads_~tmp___1~0 != 0); 64882#L855-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 64886#L381 assume !(~t3_pc~0 == 1); 64922#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 64919#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 64920#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 64263#L863 assume !(activate_threads_~tmp___2~0 != 0); 64233#L863-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 64234#L400 assume !(~t4_pc~0 == 1); 64278#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 64279#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 64295#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 64438#L871 assume !(activate_threads_~tmp___3~0 != 0); 64544#L871-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 64551#L419 assume !(~t5_pc~0 == 1); 64447#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 64446#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 64511#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 64512#L879 assume activate_threads_~tmp___4~0 != 0;~t5_st~0 := 0; 64809#L879-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 64810#L438 assume !(~t6_pc~0 == 1); 64820#L438-2 is_transmit6_triggered_~__retres1~6 := 0; 64821#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 64780#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 64781#L887 assume !(activate_threads_~tmp___5~0 != 0); 64939#L887-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64315#L752 assume !(~M_E~0 == 1); 64301#L752-2 assume !(~T1_E~0 == 1); 64302#L757-1 assume !(~T2_E~0 == 1); 64653#L762-1 assume !(~T3_E~0 == 1); 64654#L767-1 assume !(~T4_E~0 == 1); 64519#L772-1 assume !(~T5_E~0 == 1); 64520#L777-1 assume !(~T6_E~0 == 1); 64824#L782-1 assume !(~E_M~0 == 1); 64371#L787-1 assume !(~E_1~0 == 1); 64372#L792-1 assume !(~E_2~0 == 1); 64235#L797-1 assume !(~E_3~0 == 1); 64236#L802-1 assume !(~E_4~0 == 1); 64313#L807-1 assume !(~E_5~0 == 1); 64314#L812-1 assume !(~E_6~0 == 1); 64679#L817-1 assume { :end_inline_reset_delta_events } true; 64680#L1043-3 [2018-11-10 06:54:05,331 INFO L795 eck$LassoCheckResult]: Loop: 64680#L1043-3 assume true; 68997#L1043-1 assume !false; 68994#L1044 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 68989#L649 assume true; 68987#L555-1 assume !false; 68985#L556 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 68982#L508 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 68973#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 68971#L546 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 68968#L560 assume !(eval_~tmp~0 != 0); 68969#L664 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 69192#L458-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 69191#L674-3 assume ~M_E~0 == 0;~M_E~0 := 1; 69190#L674-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 69189#L679-3 assume !(~T2_E~0 == 0); 69188#L684-3 assume !(~T3_E~0 == 0); 69185#L689-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 69183#L694-3 assume ~T5_E~0 == 0;~T5_E~0 := 1; 69181#L699-3 assume ~T6_E~0 == 0;~T6_E~0 := 1; 69179#L704-3 assume !(~E_M~0 == 0); 69177#L709-3 assume ~E_1~0 == 0;~E_1~0 := 1; 69175#L714-3 assume ~E_2~0 == 0;~E_2~0 := 1; 69173#L719-3 assume !(~E_3~0 == 0); 69171#L724-3 assume !(~E_4~0 == 0); 69169#L729-3 assume ~E_5~0 == 0;~E_5~0 := 1; 69167#L734-3 assume ~E_6~0 == 0;~E_6~0 := 1; 69165#L739-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 69159#L324-24 assume !(~m_pc~0 == 1); 69157#L324-26 is_master_triggered_~__retres1~0 := 0; 69155#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 69153#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 69151#L839-24 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 69149#L839-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 69147#L343-24 assume !(~t1_pc~0 == 1); 69145#L343-26 is_transmit1_triggered_~__retres1~1 := 0; 69143#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 69141#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 69139#L847-24 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 69137#L847-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 69135#L362-24 assume ~t2_pc~0 == 1; 69133#L363-8 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 69130#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 69128#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 69126#L855-24 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 69124#L855-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 69121#L381-24 assume !(~t3_pc~0 == 1); 69119#L381-26 is_transmit3_triggered_~__retres1~3 := 0; 69117#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 69115#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 69113#L863-24 assume !(activate_threads_~tmp___2~0 != 0); 69111#L863-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 69109#L400-24 assume !(~t4_pc~0 == 1); 69107#L400-26 is_transmit4_triggered_~__retres1~4 := 0; 69105#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 69103#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 69101#L871-24 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 69099#L871-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 69097#L419-24 assume ~t5_pc~0 == 1; 69095#L420-8 assume ~E_5~0 == 1;is_transmit5_triggered_~__retres1~5 := 1; 69092#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 69090#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 69088#L879-24 assume activate_threads_~tmp___4~0 != 0;~t5_st~0 := 0; 69086#L879-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 69084#L438-24 assume !(~t6_pc~0 == 1); 69082#L438-26 is_transmit6_triggered_~__retres1~6 := 0; 69080#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 69078#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 69076#L887-24 assume activate_threads_~tmp___5~0 != 0;~t6_st~0 := 0; 69074#L887-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69072#L752-3 assume ~M_E~0 == 1;~M_E~0 := 2; 69071#L752-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 69070#L757-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 69069#L762-3 assume !(~T3_E~0 == 1); 69068#L767-3 assume ~T4_E~0 == 1;~T4_E~0 := 2; 69067#L772-3 assume ~T5_E~0 == 1;~T5_E~0 := 2; 69064#L777-3 assume !(~T6_E~0 == 1); 69062#L782-3 assume !(~E_M~0 == 1); 69060#L787-3 assume ~E_1~0 == 1;~E_1~0 := 2; 69058#L792-3 assume ~E_2~0 == 1;~E_2~0 := 2; 69056#L797-3 assume ~E_3~0 == 1;~E_3~0 := 2; 69054#L802-3 assume !(~E_4~0 == 1); 69052#L807-3 assume ~E_5~0 == 1;~E_5~0 := 2; 69049#L812-3 assume ~E_6~0 == 1;~E_6~0 := 2; 69047#L817-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 69034#L508-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 69030#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 69028#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 69025#L1062 assume !(start_simulation_~tmp~3 == 0); 69022#L1062-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 69017#L508-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 69010#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 69008#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 69006#L1017 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 69004#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 69002#L1025 start_simulation_#t~ret18 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 69000#L1075 assume !(start_simulation_~tmp___0~1 != 0); 64680#L1043-3 [2018-11-10 06:54:05,331 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:05,332 INFO L82 PathProgramCache]: Analyzing trace with hash 909741639, now seen corresponding path program 1 times [2018-11-10 06:54:05,332 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:05,332 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:05,332 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:05,332 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:05,333 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:05,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:05,379 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:05,379 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:05,379 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 06:54:05,379 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 06:54:05,380 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:05,380 INFO L82 PathProgramCache]: Analyzing trace with hash 2114805602, now seen corresponding path program 1 times [2018-11-10 06:54:05,380 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:05,380 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:05,380 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:05,381 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:05,381 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:05,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:05,405 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:05,405 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:05,405 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:54:05,405 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 06:54:05,405 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 06:54:05,406 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 06:54:05,406 INFO L87 Difference]: Start difference. First operand 7703 states and 10842 transitions. cyclomatic complexity: 3155 Second operand 5 states. [2018-11-10 06:54:05,646 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:54:05,646 INFO L93 Difference]: Finished difference Result 18210 states and 25701 transitions. [2018-11-10 06:54:05,648 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-10 06:54:05,648 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18210 states and 25701 transitions. [2018-11-10 06:54:05,709 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 17884 [2018-11-10 06:54:05,768 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18210 states to 18210 states and 25701 transitions. [2018-11-10 06:54:05,768 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18210 [2018-11-10 06:54:05,779 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18210 [2018-11-10 06:54:05,779 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18210 states and 25701 transitions. [2018-11-10 06:54:05,800 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:54:05,800 INFO L705 BuchiCegarLoop]: Abstraction has 18210 states and 25701 transitions. [2018-11-10 06:54:05,813 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18210 states and 25701 transitions. [2018-11-10 06:54:05,922 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18210 to 8042. [2018-11-10 06:54:05,922 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8042 states. [2018-11-10 06:54:06,002 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8042 states to 8042 states and 11181 transitions. [2018-11-10 06:54:06,002 INFO L728 BuchiCegarLoop]: Abstraction has 8042 states and 11181 transitions. [2018-11-10 06:54:06,002 INFO L608 BuchiCegarLoop]: Abstraction has 8042 states and 11181 transitions. [2018-11-10 06:54:06,002 INFO L442 BuchiCegarLoop]: ======== Iteration 15============ [2018-11-10 06:54:06,002 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8042 states and 11181 transitions. [2018-11-10 06:54:06,018 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7888 [2018-11-10 06:54:06,018 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:54:06,018 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:54:06,019 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:06,019 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:06,019 INFO L793 eck$LassoCheckResult]: Stem: 90808#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 90681#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 90174#L1006 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 90175#L458 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 90594#L465 assume ~m_i~0 == 1;~m_st~0 := 0; 90595#L465-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 90598#L470-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 90437#L475-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 90438#L480-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 90512#L485-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 90264#L490-1 assume ~t6_i~0 == 1;~t6_st~0 := 0; 90265#L495-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 90607#L674 assume !(~M_E~0 == 0); 90608#L674-2 assume !(~T1_E~0 == 0); 90618#L679-1 assume !(~T2_E~0 == 0); 90459#L684-1 assume !(~T3_E~0 == 0); 90460#L689-1 assume !(~T4_E~0 == 0); 90784#L694-1 assume !(~T5_E~0 == 0); 90306#L699-1 assume !(~T6_E~0 == 0); 90307#L704-1 assume !(~E_M~0 == 0); 90132#L709-1 assume !(~E_1~0 == 0); 90133#L714-1 assume !(~E_2~0 == 0); 90225#L719-1 assume !(~E_3~0 == 0); 90226#L724-1 assume !(~E_4~0 == 0); 90605#L729-1 assume !(~E_5~0 == 0); 90606#L734-1 assume !(~E_6~0 == 0); 90451#L739-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 90340#L324 assume !(~m_pc~0 == 1); 90276#L324-2 is_master_triggered_~__retres1~0 := 0; 90352#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 90273#L336 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 90274#L839 assume !(activate_threads_~tmp~1 != 0); 90625#L839-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 90391#L343 assume !(~t1_pc~0 == 1); 90392#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 90386#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 90387#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 90567#L847 assume !(activate_threads_~tmp___0~0 != 0); 90834#L847-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 90752#L362 assume !(~t2_pc~0 == 1); 90695#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 90696#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 90748#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 90826#L855 assume !(activate_threads_~tmp___1~0 != 0); 90842#L855-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 90846#L381 assume !(~t3_pc~0 == 1); 90880#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 90877#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 90878#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 90190#L863 assume !(activate_threads_~tmp___2~0 != 0); 90159#L863-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 90160#L400 assume !(~t4_pc~0 == 1); 90205#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 90206#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 90221#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 90364#L871 assume !(activate_threads_~tmp___3~0 != 0); 90475#L871-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 90482#L419 assume !(~t5_pc~0 == 1); 90375#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 90513#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 90514#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 90774#L879 assume !(activate_threads_~tmp___4~0 != 0); 90766#L879-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 90767#L438 assume !(~t6_pc~0 == 1); 90776#L438-2 is_transmit6_triggered_~__retres1~6 := 0; 90777#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 90737#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 90738#L887 assume !(activate_threads_~tmp___5~0 != 0); 90897#L887-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 90241#L752 assume !(~M_E~0 == 1); 90227#L752-2 assume !(~T1_E~0 == 1); 90228#L757-1 assume !(~T2_E~0 == 1); 90600#L762-1 assume !(~T3_E~0 == 1); 90601#L767-1 assume !(~T4_E~0 == 1); 90447#L772-1 assume !(~T5_E~0 == 1); 90448#L777-1 assume !(~T6_E~0 == 1); 90782#L782-1 assume !(~E_M~0 == 1); 90300#L787-1 assume !(~E_1~0 == 1); 90301#L792-1 assume !(~E_2~0 == 1); 90161#L797-1 assume !(~E_3~0 == 1); 90162#L802-1 assume !(~E_4~0 == 1); 90239#L807-1 assume !(~E_5~0 == 1); 90240#L812-1 assume !(~E_6~0 == 1); 90626#L817-1 assume { :end_inline_reset_delta_events } true; 90627#L1043-3 [2018-11-10 06:54:06,020 INFO L795 eck$LassoCheckResult]: Loop: 90627#L1043-3 assume true; 94784#L1043-1 assume !false; 94686#L1044 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 94674#L649 assume true; 94665#L555-1 assume !false; 94657#L556 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 94482#L508 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 94474#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 94419#L546 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 94416#L560 assume !(eval_~tmp~0 != 0); 94417#L664 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 96417#L458-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 95932#L674-3 assume ~M_E~0 == 0;~M_E~0 := 1; 95931#L674-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 95930#L679-3 assume !(~T2_E~0 == 0); 95925#L684-3 assume !(~T3_E~0 == 0); 95923#L689-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 95918#L694-3 assume ~T5_E~0 == 0;~T5_E~0 := 1; 95917#L699-3 assume ~T6_E~0 == 0;~T6_E~0 := 1; 95914#L704-3 assume !(~E_M~0 == 0); 95717#L709-3 assume ~E_1~0 == 0;~E_1~0 := 1; 95711#L714-3 assume ~E_2~0 == 0;~E_2~0 := 1; 95706#L719-3 assume !(~E_3~0 == 0); 95701#L724-3 assume !(~E_4~0 == 0); 95696#L729-3 assume ~E_5~0 == 0;~E_5~0 := 1; 95692#L734-3 assume ~E_6~0 == 0;~E_6~0 := 1; 95691#L739-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 95689#L324-24 assume !(~m_pc~0 == 1); 95688#L324-26 is_master_triggered_~__retres1~0 := 0; 95687#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 95686#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 95685#L839-24 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 95684#L839-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 95683#L343-24 assume !(~t1_pc~0 == 1); 95682#L343-26 is_transmit1_triggered_~__retres1~1 := 0; 95681#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 95680#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 95679#L847-24 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 95678#L847-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 95677#L362-24 assume !(~t2_pc~0 == 1); 95675#L362-26 is_transmit2_triggered_~__retres1~2 := 0; 95674#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 95673#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 95672#L855-24 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 95671#L855-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 95670#L381-24 assume !(~t3_pc~0 == 1); 95669#L381-26 is_transmit3_triggered_~__retres1~3 := 0; 95668#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 95667#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 95666#L863-24 assume !(activate_threads_~tmp___2~0 != 0); 95665#L863-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 95664#L400-24 assume !(~t4_pc~0 == 1); 95663#L400-26 is_transmit4_triggered_~__retres1~4 := 0; 95662#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 95661#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 95660#L871-24 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 95659#L871-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 95658#L419-24 assume !(~t5_pc~0 == 1); 95657#L419-26 is_transmit5_triggered_~__retres1~5 := 0; 95655#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 95653#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 95651#L879-24 assume !(activate_threads_~tmp___4~0 != 0); 95648#L879-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 95646#L438-24 assume !(~t6_pc~0 == 1); 95644#L438-26 is_transmit6_triggered_~__retres1~6 := 0; 95638#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 95561#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 95560#L887-24 assume activate_threads_~tmp___5~0 != 0;~t6_st~0 := 0; 95559#L887-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 95558#L752-3 assume ~M_E~0 == 1;~M_E~0 := 2; 95454#L752-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 95452#L757-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 95450#L762-3 assume !(~T3_E~0 == 1); 95448#L767-3 assume ~T4_E~0 == 1;~T4_E~0 := 2; 95446#L772-3 assume ~T5_E~0 == 1;~T5_E~0 := 2; 95444#L777-3 assume !(~T6_E~0 == 1); 95442#L782-3 assume !(~E_M~0 == 1); 95440#L787-3 assume ~E_1~0 == 1;~E_1~0 := 2; 95438#L792-3 assume ~E_2~0 == 1;~E_2~0 := 2; 95436#L797-3 assume ~E_3~0 == 1;~E_3~0 := 2; 95434#L802-3 assume !(~E_4~0 == 1); 95432#L807-3 assume ~E_5~0 == 1;~E_5~0 := 2; 95430#L812-3 assume ~E_6~0 == 1;~E_6~0 := 2; 95428#L817-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 95417#L508-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 95413#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 95411#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 95409#L1062 assume !(start_simulation_~tmp~3 == 0); 95407#L1062-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 95405#L508-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 95390#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 94829#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 94820#L1017 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 94814#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 94807#L1025 start_simulation_#t~ret18 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 94799#L1075 assume !(start_simulation_~tmp___0~1 != 0); 90627#L1043-3 [2018-11-10 06:54:06,020 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:06,020 INFO L82 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 1 times [2018-11-10 06:54:06,020 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:06,021 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:06,021 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:06,021 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:06,021 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:06,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:54:06,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:54:06,068 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:06,068 INFO L82 PathProgramCache]: Analyzing trace with hash 554139046, now seen corresponding path program 1 times [2018-11-10 06:54:06,068 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:06,068 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:06,069 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:06,069 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:06,069 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:06,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:06,098 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:06,098 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:06,099 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:54:06,099 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 06:54:06,099 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 06:54:06,099 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 06:54:06,099 INFO L87 Difference]: Start difference. First operand 8042 states and 11181 transitions. cyclomatic complexity: 3155 Second operand 3 states. [2018-11-10 06:54:06,165 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:54:06,165 INFO L93 Difference]: Finished difference Result 9145 states and 12714 transitions. [2018-11-10 06:54:06,165 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 06:54:06,165 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9145 states and 12714 transitions. [2018-11-10 06:54:06,191 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8928 [2018-11-10 06:54:06,213 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9145 states to 9145 states and 12714 transitions. [2018-11-10 06:54:06,213 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9145 [2018-11-10 06:54:06,218 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9145 [2018-11-10 06:54:06,219 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9145 states and 12714 transitions. [2018-11-10 06:54:06,225 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:54:06,225 INFO L705 BuchiCegarLoop]: Abstraction has 9145 states and 12714 transitions. [2018-11-10 06:54:06,231 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9145 states and 12714 transitions. [2018-11-10 06:54:06,287 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9145 to 9145. [2018-11-10 06:54:06,287 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9145 states. [2018-11-10 06:54:06,300 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9145 states to 9145 states and 12714 transitions. [2018-11-10 06:54:06,300 INFO L728 BuchiCegarLoop]: Abstraction has 9145 states and 12714 transitions. [2018-11-10 06:54:06,300 INFO L608 BuchiCegarLoop]: Abstraction has 9145 states and 12714 transitions. [2018-11-10 06:54:06,300 INFO L442 BuchiCegarLoop]: ======== Iteration 16============ [2018-11-10 06:54:06,300 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9145 states and 12714 transitions. [2018-11-10 06:54:06,320 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8928 [2018-11-10 06:54:06,320 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:54:06,320 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:54:06,321 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:06,321 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:06,322 INFO L793 eck$LassoCheckResult]: Stem: 107993#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 107870#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 107370#L1006 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 107371#L458 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 107779#L465 assume ~m_i~0 == 1;~m_st~0 := 0; 107780#L465-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 107783#L470-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 107643#L475-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 107644#L480-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 107707#L485-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 107465#L490-1 assume ~t6_i~0 == 1;~t6_st~0 := 0; 107466#L495-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 107794#L674 assume !(~M_E~0 == 0); 107795#L674-2 assume !(~T1_E~0 == 0); 107804#L679-1 assume !(~T2_E~0 == 0); 107666#L684-1 assume !(~T3_E~0 == 0); 107667#L689-1 assume !(~T4_E~0 == 0); 107970#L694-1 assume !(~T5_E~0 == 0); 107502#L699-1 assume ~T6_E~0 == 0;~T6_E~0 := 1; 107503#L704-1 assume !(~E_M~0 == 0); 107325#L709-1 assume !(~E_1~0 == 0); 107326#L714-1 assume !(~E_2~0 == 0); 108182#L719-1 assume !(~E_3~0 == 0); 108099#L724-1 assume !(~E_4~0 == 0); 108100#L729-1 assume !(~E_5~0 == 0); 108145#L734-1 assume !(~E_6~0 == 0); 107658#L739-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 107532#L324 assume !(~m_pc~0 == 1); 107473#L324-2 is_master_triggered_~__retres1~0 := 0; 107574#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 107575#L336 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 107810#L839 assume !(activate_threads_~tmp~1 != 0); 107811#L839-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 107594#L343 assume !(~t1_pc~0 == 1); 107595#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 107592#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 107593#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 108024#L847 assume !(activate_threads_~tmp___0~0 != 0); 108025#L847-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 108176#L362 assume !(~t2_pc~0 == 1); 108174#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 108173#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 108172#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 108028#L855 assume !(activate_threads_~tmp___1~0 != 0); 108029#L855-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 108068#L381 assume !(~t3_pc~0 == 1); 108069#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 108066#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 108067#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 107388#L863 assume !(activate_threads_~tmp___2~0 != 0); 107354#L863-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 107355#L400 assume !(~t4_pc~0 == 1); 107401#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 107402#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 107418#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 108167#L871 assume !(activate_threads_~tmp___3~0 != 0); 108166#L871-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 108165#L419 assume !(~t5_pc~0 == 1); 108163#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 108161#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 108159#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 108157#L879 assume !(activate_threads_~tmp___4~0 != 0); 108156#L879-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 108098#L438 assume !(~t6_pc~0 == 1); 107961#L438-2 is_transmit6_triggered_~__retres1~6 := 0; 107962#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 108154#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 108089#L887 assume !(activate_threads_~tmp___5~0 != 0); 108090#L887-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 107439#L752 assume !(~M_E~0 == 1); 107422#L752-2 assume !(~T1_E~0 == 1); 107423#L757-1 assume !(~T2_E~0 == 1); 107785#L762-1 assume !(~T3_E~0 == 1); 107786#L767-1 assume !(~T4_E~0 == 1); 107653#L772-1 assume !(~T5_E~0 == 1); 107654#L777-1 assume ~T6_E~0 == 1;~T6_E~0 := 2; 107968#L782-1 assume !(~E_M~0 == 1); 107496#L787-1 assume !(~E_1~0 == 1); 107497#L792-1 assume !(~E_2~0 == 1); 107356#L797-1 assume !(~E_3~0 == 1); 107357#L802-1 assume !(~E_4~0 == 1); 107437#L807-1 assume !(~E_5~0 == 1); 107438#L812-1 assume !(~E_6~0 == 1); 107812#L817-1 assume { :end_inline_reset_delta_events } true; 107813#L1043-3 [2018-11-10 06:54:06,322 INFO L795 eck$LassoCheckResult]: Loop: 107813#L1043-3 assume true; 111710#L1043-1 assume !false; 111708#L1044 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 111704#L649 assume true; 111702#L555-1 assume !false; 111700#L556 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 111697#L508 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 111689#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 111687#L546 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 111685#L560 assume !(eval_~tmp~0 != 0); 111686#L664 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 111917#L458-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 111915#L674-3 assume ~M_E~0 == 0;~M_E~0 := 1; 111913#L674-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 111911#L679-3 assume !(~T2_E~0 == 0); 111910#L684-3 assume !(~T3_E~0 == 0); 111907#L689-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 111905#L694-3 assume ~T5_E~0 == 0;~T5_E~0 := 1; 111902#L699-3 assume ~T6_E~0 == 0;~T6_E~0 := 1; 111900#L704-3 assume !(~E_M~0 == 0); 111898#L709-3 assume ~E_1~0 == 0;~E_1~0 := 1; 111896#L714-3 assume ~E_2~0 == 0;~E_2~0 := 1; 111894#L719-3 assume !(~E_3~0 == 0); 111892#L724-3 assume !(~E_4~0 == 0); 111890#L729-3 assume ~E_5~0 == 0;~E_5~0 := 1; 111888#L734-3 assume ~E_6~0 == 0;~E_6~0 := 1; 111886#L739-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 111880#L324-24 assume !(~m_pc~0 == 1); 111878#L324-26 is_master_triggered_~__retres1~0 := 0; 111876#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 111874#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 111872#L839-24 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 111870#L839-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 111868#L343-24 assume !(~t1_pc~0 == 1); 111866#L343-26 is_transmit1_triggered_~__retres1~1 := 0; 111864#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 111862#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 111860#L847-24 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 111858#L847-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 111856#L362-24 assume !(~t2_pc~0 == 1); 111853#L362-26 is_transmit2_triggered_~__retres1~2 := 0; 111851#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 111849#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 111847#L855-24 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 111843#L855-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 111841#L381-24 assume !(~t3_pc~0 == 1); 111839#L381-26 is_transmit3_triggered_~__retres1~3 := 0; 111837#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 111834#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 111832#L863-24 assume !(activate_threads_~tmp___2~0 != 0); 111830#L863-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 111828#L400-24 assume !(~t4_pc~0 == 1); 111826#L400-26 is_transmit4_triggered_~__retres1~4 := 0; 111824#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 111822#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 111820#L871-24 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 111818#L871-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 111816#L419-24 assume !(~t5_pc~0 == 1); 111812#L419-26 is_transmit5_triggered_~__retres1~5 := 0; 111810#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 111808#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 111806#L879-24 assume !(activate_threads_~tmp___4~0 != 0); 111804#L879-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 111803#L438-24 assume !(~t6_pc~0 == 1); 111802#L438-26 is_transmit6_triggered_~__retres1~6 := 0; 111801#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 111798#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 111796#L887-24 assume activate_threads_~tmp___5~0 != 0;~t6_st~0 := 0; 111794#L887-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 111792#L752-3 assume ~M_E~0 == 1;~M_E~0 := 2; 111789#L752-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 111787#L757-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 111785#L762-3 assume !(~T3_E~0 == 1); 111783#L767-3 assume ~T4_E~0 == 1;~T4_E~0 := 2; 111781#L772-3 assume ~T5_E~0 == 1;~T5_E~0 := 2; 111779#L777-3 assume ~T6_E~0 == 1;~T6_E~0 := 2; 111776#L782-3 assume !(~E_M~0 == 1); 111774#L787-3 assume ~E_1~0 == 1;~E_1~0 := 2; 111772#L792-3 assume ~E_2~0 == 1;~E_2~0 := 2; 111770#L797-3 assume ~E_3~0 == 1;~E_3~0 := 2; 111768#L802-3 assume !(~E_4~0 == 1); 111766#L807-3 assume ~E_5~0 == 1;~E_5~0 := 2; 111764#L812-3 assume ~E_6~0 == 1;~E_6~0 := 2; 111761#L817-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 111750#L508-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 111746#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 111744#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 111741#L1062 assume !(start_simulation_~tmp~3 == 0); 111738#L1062-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 111733#L508-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 111726#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 111724#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 111722#L1017 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 111718#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 111716#L1025 start_simulation_#t~ret18 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 111714#L1075 assume !(start_simulation_~tmp___0~1 != 0); 107813#L1043-3 [2018-11-10 06:54:06,322 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:06,322 INFO L82 PathProgramCache]: Analyzing trace with hash -843787639, now seen corresponding path program 1 times [2018-11-10 06:54:06,322 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:06,322 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:06,323 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:06,323 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:06,323 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:06,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:06,345 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:06,345 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:06,345 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 06:54:06,345 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 06:54:06,346 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:06,346 INFO L82 PathProgramCache]: Analyzing trace with hash 131437220, now seen corresponding path program 1 times [2018-11-10 06:54:06,346 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:06,346 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:06,346 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:06,347 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:06,347 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:06,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:06,369 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:06,369 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:06,369 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 06:54:06,369 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 06:54:06,370 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 06:54:06,370 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 06:54:06,370 INFO L87 Difference]: Start difference. First operand 9145 states and 12714 transitions. cyclomatic complexity: 3585 Second operand 3 states. [2018-11-10 06:54:06,416 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:54:06,416 INFO L93 Difference]: Finished difference Result 8042 states and 11131 transitions. [2018-11-10 06:54:06,418 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 06:54:06,418 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8042 states and 11131 transitions. [2018-11-10 06:54:06,441 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7888 [2018-11-10 06:54:06,462 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8042 states to 8042 states and 11131 transitions. [2018-11-10 06:54:06,462 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8042 [2018-11-10 06:54:06,466 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8042 [2018-11-10 06:54:06,466 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8042 states and 11131 transitions. [2018-11-10 06:54:06,473 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:54:06,473 INFO L705 BuchiCegarLoop]: Abstraction has 8042 states and 11131 transitions. [2018-11-10 06:54:06,478 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8042 states and 11131 transitions. [2018-11-10 06:54:06,531 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8042 to 8042. [2018-11-10 06:54:06,532 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8042 states. [2018-11-10 06:54:06,543 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8042 states to 8042 states and 11131 transitions. [2018-11-10 06:54:06,543 INFO L728 BuchiCegarLoop]: Abstraction has 8042 states and 11131 transitions. [2018-11-10 06:54:06,543 INFO L608 BuchiCegarLoop]: Abstraction has 8042 states and 11131 transitions. [2018-11-10 06:54:06,543 INFO L442 BuchiCegarLoop]: ======== Iteration 17============ [2018-11-10 06:54:06,543 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8042 states and 11131 transitions. [2018-11-10 06:54:06,562 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7888 [2018-11-10 06:54:06,562 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:54:06,562 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:54:06,563 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:06,563 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:06,564 INFO L793 eck$LassoCheckResult]: Stem: 125181#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 125055#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 124564#L1006 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 124565#L458 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 124971#L465 assume ~m_i~0 == 1;~m_st~0 := 0; 124972#L465-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 124976#L470-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 124829#L475-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 124830#L480-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 124895#L485-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 124651#L490-1 assume ~t6_i~0 == 1;~t6_st~0 := 0; 124652#L495-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 124985#L674 assume !(~M_E~0 == 0); 124986#L674-2 assume !(~T1_E~0 == 0); 124997#L679-1 assume !(~T2_E~0 == 0); 124851#L684-1 assume !(~T3_E~0 == 0); 124852#L689-1 assume !(~T4_E~0 == 0); 125158#L694-1 assume !(~T5_E~0 == 0); 124691#L699-1 assume !(~T6_E~0 == 0); 124692#L704-1 assume !(~E_M~0 == 0); 124521#L709-1 assume !(~E_1~0 == 0); 124522#L714-1 assume !(~E_2~0 == 0); 124612#L719-1 assume !(~E_3~0 == 0); 124613#L724-1 assume !(~E_4~0 == 0); 124983#L729-1 assume !(~E_5~0 == 0); 124984#L734-1 assume !(~E_6~0 == 0); 124844#L739-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 124724#L324 assume !(~m_pc~0 == 1); 124662#L324-2 is_master_triggered_~__retres1~0 := 0; 124738#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 124659#L336 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 124660#L839 assume !(activate_threads_~tmp~1 != 0); 125001#L839-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 124782#L343 assume !(~t1_pc~0 == 1); 124783#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 124777#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 124778#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 124944#L847 assume !(activate_threads_~tmp___0~0 != 0); 125205#L847-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 125123#L362 assume !(~t2_pc~0 == 1); 125069#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 125070#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 125119#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 125199#L855 assume !(activate_threads_~tmp___1~0 != 0); 125212#L855-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 125216#L381 assume !(~t3_pc~0 == 1); 125253#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 125250#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 125251#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 124579#L863 assume !(activate_threads_~tmp___2~0 != 0); 124547#L863-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 124548#L400 assume !(~t4_pc~0 == 1); 124593#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 124594#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 124608#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 124753#L871 assume !(activate_threads_~tmp___3~0 != 0); 124865#L871-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 124872#L419 assume !(~t5_pc~0 == 1); 124766#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 124896#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 124832#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 124833#L879 assume !(activate_threads_~tmp___4~0 != 0); 125137#L879-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 125138#L438 assume !(~t6_pc~0 == 1); 125148#L438-2 is_transmit6_triggered_~__retres1~6 := 0; 125149#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 125109#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 125110#L887 assume !(activate_threads_~tmp___5~0 != 0); 125273#L887-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 124628#L752 assume !(~M_E~0 == 1); 124614#L752-2 assume !(~T1_E~0 == 1); 124615#L757-1 assume !(~T2_E~0 == 1); 124978#L762-1 assume !(~T3_E~0 == 1); 124979#L767-1 assume !(~T4_E~0 == 1); 124840#L772-1 assume !(~T5_E~0 == 1); 124841#L777-1 assume !(~T6_E~0 == 1); 125156#L782-1 assume !(~E_M~0 == 1); 124685#L787-1 assume !(~E_1~0 == 1); 124686#L792-1 assume !(~E_2~0 == 1); 124549#L797-1 assume !(~E_3~0 == 1); 124550#L802-1 assume !(~E_4~0 == 1); 124626#L807-1 assume !(~E_5~0 == 1); 124627#L812-1 assume !(~E_6~0 == 1); 125004#L817-1 assume { :end_inline_reset_delta_events } true; 125005#L1043-3 [2018-11-10 06:54:06,564 INFO L795 eck$LassoCheckResult]: Loop: 125005#L1043-3 assume true; 129507#L1043-1 assume !false; 129498#L1044 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 129489#L649 assume true; 129483#L555-1 assume !false; 129476#L556 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 129321#L508 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 129314#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 129289#L546 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 129277#L560 assume !(eval_~tmp~0 != 0); 129278#L664 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 130068#L458-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 130066#L674-3 assume ~M_E~0 == 0;~M_E~0 := 1; 130064#L674-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 130062#L679-3 assume !(~T2_E~0 == 0); 130060#L684-3 assume !(~T3_E~0 == 0); 130058#L689-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 130056#L694-3 assume ~T5_E~0 == 0;~T5_E~0 := 1; 130054#L699-3 assume !(~T6_E~0 == 0); 130052#L704-3 assume !(~E_M~0 == 0); 130050#L709-3 assume ~E_1~0 == 0;~E_1~0 := 1; 130048#L714-3 assume ~E_2~0 == 0;~E_2~0 := 1; 130046#L719-3 assume !(~E_3~0 == 0); 130044#L724-3 assume !(~E_4~0 == 0); 130042#L729-3 assume ~E_5~0 == 0;~E_5~0 := 1; 130040#L734-3 assume ~E_6~0 == 0;~E_6~0 := 1; 130038#L739-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 130034#L324-24 assume !(~m_pc~0 == 1); 130032#L324-26 is_master_triggered_~__retres1~0 := 0; 130030#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 130028#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 130026#L839-24 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 130024#L839-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 130022#L343-24 assume !(~t1_pc~0 == 1); 130020#L343-26 is_transmit1_triggered_~__retres1~1 := 0; 130018#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 130016#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 130014#L847-24 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 130012#L847-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 130010#L362-24 assume !(~t2_pc~0 == 1); 130007#L362-26 is_transmit2_triggered_~__retres1~2 := 0; 130005#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 130004#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 130001#L855-24 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 130000#L855-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 129999#L381-24 assume !(~t3_pc~0 == 1); 129998#L381-26 is_transmit3_triggered_~__retres1~3 := 0; 129995#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 129993#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 129991#L863-24 assume !(activate_threads_~tmp___2~0 != 0); 129989#L863-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 129987#L400-24 assume !(~t4_pc~0 == 1); 129985#L400-26 is_transmit4_triggered_~__retres1~4 := 0; 129983#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 129981#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 129979#L871-24 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 129978#L871-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 129977#L419-24 assume ~t5_pc~0 == 1; 129975#L420-8 assume ~E_5~0 == 1;is_transmit5_triggered_~__retres1~5 := 1; 129962#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 129956#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 129948#L879-24 assume activate_threads_~tmp___4~0 != 0;~t5_st~0 := 0; 129918#L879-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 129876#L438-24 assume !(~t6_pc~0 == 1); 129870#L438-26 is_transmit6_triggered_~__retres1~6 := 0; 129864#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 129857#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 129851#L887-24 assume activate_threads_~tmp___5~0 != 0;~t6_st~0 := 0; 129844#L887-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 129784#L752-3 assume ~M_E~0 == 1;~M_E~0 := 2; 129781#L752-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 129779#L757-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 129777#L762-3 assume !(~T3_E~0 == 1); 129775#L767-3 assume ~T4_E~0 == 1;~T4_E~0 := 2; 129773#L772-3 assume ~T5_E~0 == 1;~T5_E~0 := 2; 129771#L777-3 assume !(~T6_E~0 == 1); 129769#L782-3 assume !(~E_M~0 == 1); 129746#L787-3 assume ~E_1~0 == 1;~E_1~0 := 2; 129738#L792-3 assume ~E_2~0 == 1;~E_2~0 := 2; 129732#L797-3 assume ~E_3~0 == 1;~E_3~0 := 2; 129726#L802-3 assume !(~E_4~0 == 1); 129721#L807-3 assume ~E_5~0 == 1;~E_5~0 := 2; 129717#L812-3 assume ~E_6~0 == 1;~E_6~0 := 2; 129715#L817-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 129629#L508-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 129619#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 129611#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 129602#L1062 assume !(start_simulation_~tmp~3 == 0); 129594#L1062-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 129579#L508-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 129565#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 129558#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 129552#L1017 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 129546#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 129533#L1025 start_simulation_#t~ret18 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 129523#L1075 assume !(start_simulation_~tmp___0~1 != 0); 125005#L1043-3 [2018-11-10 06:54:06,564 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:06,564 INFO L82 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 2 times [2018-11-10 06:54:06,564 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:06,564 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:06,565 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:06,565 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:06,565 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:06,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:54:06,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:54:06,591 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:06,591 INFO L82 PathProgramCache]: Analyzing trace with hash -1100860703, now seen corresponding path program 1 times [2018-11-10 06:54:06,591 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:06,591 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:06,592 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:06,592 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 06:54:06,592 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:06,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:06,618 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:06,618 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:06,618 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 06:54:06,618 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 06:54:06,619 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 06:54:06,619 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 06:54:06,619 INFO L87 Difference]: Start difference. First operand 8042 states and 11131 transitions. cyclomatic complexity: 3105 Second operand 5 states. [2018-11-10 06:54:06,758 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:54:06,758 INFO L93 Difference]: Finished difference Result 14570 states and 19907 transitions. [2018-11-10 06:54:06,760 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-10 06:54:06,760 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14570 states and 19907 transitions. [2018-11-10 06:54:06,805 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14352 [2018-11-10 06:54:06,841 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14570 states to 14570 states and 19907 transitions. [2018-11-10 06:54:06,841 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14570 [2018-11-10 06:54:06,848 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14570 [2018-11-10 06:54:06,849 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14570 states and 19907 transitions. [2018-11-10 06:54:06,857 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:54:06,857 INFO L705 BuchiCegarLoop]: Abstraction has 14570 states and 19907 transitions. [2018-11-10 06:54:06,864 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14570 states and 19907 transitions. [2018-11-10 06:54:06,930 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14570 to 8090. [2018-11-10 06:54:06,930 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8090 states. [2018-11-10 06:54:06,939 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8090 states to 8090 states and 11179 transitions. [2018-11-10 06:54:06,939 INFO L728 BuchiCegarLoop]: Abstraction has 8090 states and 11179 transitions. [2018-11-10 06:54:06,939 INFO L608 BuchiCegarLoop]: Abstraction has 8090 states and 11179 transitions. [2018-11-10 06:54:06,940 INFO L442 BuchiCegarLoop]: ======== Iteration 18============ [2018-11-10 06:54:06,940 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8090 states and 11179 transitions. [2018-11-10 06:54:06,958 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7936 [2018-11-10 06:54:06,958 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:54:06,958 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:54:06,959 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:06,959 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:06,959 INFO L793 eck$LassoCheckResult]: Stem: 147820#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 147680#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 147193#L1006 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 147194#L458 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 147589#L465 assume ~m_i~0 == 1;~m_st~0 := 0; 147590#L465-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 147593#L470-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 147451#L475-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 147452#L480-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 147515#L485-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 147286#L490-1 assume ~t6_i~0 == 1;~t6_st~0 := 0; 147287#L495-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 147602#L674 assume !(~M_E~0 == 0); 147603#L674-2 assume !(~T1_E~0 == 0); 147614#L679-1 assume !(~T2_E~0 == 0); 147471#L684-1 assume !(~T3_E~0 == 0); 147472#L689-1 assume !(~T4_E~0 == 0); 147797#L694-1 assume !(~T5_E~0 == 0); 147327#L699-1 assume !(~T6_E~0 == 0); 147328#L704-1 assume !(~E_M~0 == 0); 147149#L709-1 assume !(~E_1~0 == 0); 147150#L714-1 assume !(~E_2~0 == 0); 147247#L719-1 assume !(~E_3~0 == 0); 147248#L724-1 assume !(~E_4~0 == 0); 147600#L729-1 assume !(~E_5~0 == 0); 147601#L734-1 assume !(~E_6~0 == 0); 147464#L739-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 147358#L324 assume !(~m_pc~0 == 1); 147297#L324-2 is_master_triggered_~__retres1~0 := 0; 147368#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 147294#L336 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 147295#L839 assume !(activate_threads_~tmp~1 != 0); 147623#L839-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 147406#L343 assume !(~t1_pc~0 == 1); 147407#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 147401#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 147402#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 147564#L847 assume !(activate_threads_~tmp___0~0 != 0); 147852#L847-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 147749#L362 assume !(~t2_pc~0 == 1); 147694#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 147695#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 147745#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 147841#L855 assume !(activate_threads_~tmp___1~0 != 0); 147860#L855-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 147865#L381 assume !(~t3_pc~0 == 1); 147903#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 147900#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 147901#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 147209#L863 assume !(activate_threads_~tmp___2~0 != 0); 147176#L863-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 147177#L400 assume !(~t4_pc~0 == 1); 147224#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 147225#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 147243#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 147381#L871 assume !(activate_threads_~tmp___3~0 != 0); 147486#L871-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 147493#L419 assume !(~t5_pc~0 == 1); 147390#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 147516#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 147453#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 147454#L879 assume !(activate_threads_~tmp___4~0 != 0); 147768#L879-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 147769#L438 assume !(~t6_pc~0 == 1); 147787#L438-2 is_transmit6_triggered_~__retres1~6 := 0; 147788#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 147735#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 147736#L887 assume !(activate_threads_~tmp___5~0 != 0); 147924#L887-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 147263#L752 assume !(~M_E~0 == 1); 147249#L752-2 assume !(~T1_E~0 == 1); 147250#L757-1 assume !(~T2_E~0 == 1); 147595#L762-1 assume !(~T3_E~0 == 1); 147596#L767-1 assume !(~T4_E~0 == 1); 147461#L772-1 assume !(~T5_E~0 == 1); 147462#L777-1 assume !(~T6_E~0 == 1); 147794#L782-1 assume !(~E_M~0 == 1); 147321#L787-1 assume !(~E_1~0 == 1); 147322#L792-1 assume !(~E_2~0 == 1); 147178#L797-1 assume !(~E_3~0 == 1); 147179#L802-1 assume !(~E_4~0 == 1); 147261#L807-1 assume !(~E_5~0 == 1); 147262#L812-1 assume !(~E_6~0 == 1); 147624#L817-1 assume { :end_inline_reset_delta_events } true; 147625#L1043-3 [2018-11-10 06:54:06,959 INFO L795 eck$LassoCheckResult]: Loop: 147625#L1043-3 assume true; 152414#L1043-1 assume !false; 152409#L1044 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 151756#L649 assume true; 152376#L555-1 assume !false; 152367#L556 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 152364#L508 assume !(~m_st~0 == 0); 152357#L512 assume !(~t1_st~0 == 0); 152358#L516 assume !(~t2_st~0 == 0); 152361#L520 assume !(~t3_st~0 == 0); 152363#L524 assume !(~t4_st~0 == 0); 152359#L528 assume !(~t5_st~0 == 0); 152360#L532 assume !(~t6_st~0 == 0);exists_runnable_thread_~__retres1~7 := 0; 152362#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 151836#L546 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 151837#L560 assume !(eval_~tmp~0 != 0); 152577#L664 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 152576#L458-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 152575#L674-3 assume ~M_E~0 == 0;~M_E~0 := 1; 152574#L674-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 152573#L679-3 assume !(~T2_E~0 == 0); 152572#L684-3 assume !(~T3_E~0 == 0); 152571#L689-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 152570#L694-3 assume ~T5_E~0 == 0;~T5_E~0 := 1; 152569#L699-3 assume !(~T6_E~0 == 0); 152568#L704-3 assume !(~E_M~0 == 0); 152567#L709-3 assume ~E_1~0 == 0;~E_1~0 := 1; 152566#L714-3 assume ~E_2~0 == 0;~E_2~0 := 1; 152565#L719-3 assume !(~E_3~0 == 0); 152564#L724-3 assume !(~E_4~0 == 0); 152563#L729-3 assume ~E_5~0 == 0;~E_5~0 := 1; 152562#L734-3 assume ~E_6~0 == 0;~E_6~0 := 1; 152561#L739-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 152559#L324-24 assume !(~m_pc~0 == 1); 152558#L324-26 is_master_triggered_~__retres1~0 := 0; 152557#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 152556#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 152555#L839-24 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 152554#L839-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 152553#L343-24 assume !(~t1_pc~0 == 1); 152552#L343-26 is_transmit1_triggered_~__retres1~1 := 0; 152551#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 152550#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 152549#L847-24 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 152548#L847-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 152547#L362-24 assume ~t2_pc~0 == 1; 152546#L363-8 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 152544#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 152543#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 152542#L855-24 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 152541#L855-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 152540#L381-24 assume !(~t3_pc~0 == 1); 152539#L381-26 is_transmit3_triggered_~__retres1~3 := 0; 152538#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 152537#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 152536#L863-24 assume !(activate_threads_~tmp___2~0 != 0); 152535#L863-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 152534#L400-24 assume !(~t4_pc~0 == 1); 152533#L400-26 is_transmit4_triggered_~__retres1~4 := 0; 152532#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 152531#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 152530#L871-24 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 152529#L871-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 152528#L419-24 assume ~t5_pc~0 == 1; 152526#L420-8 assume ~E_5~0 == 1;is_transmit5_triggered_~__retres1~5 := 1; 152524#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 152522#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 152520#L879-24 assume activate_threads_~tmp___4~0 != 0;~t5_st~0 := 0; 152519#L879-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 152518#L438-24 assume !(~t6_pc~0 == 1); 152517#L438-26 is_transmit6_triggered_~__retres1~6 := 0; 152516#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 152515#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 152514#L887-24 assume activate_threads_~tmp___5~0 != 0;~t6_st~0 := 0; 152513#L887-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 152512#L752-3 assume ~M_E~0 == 1;~M_E~0 := 2; 152511#L752-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 152510#L757-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 152509#L762-3 assume !(~T3_E~0 == 1); 152508#L767-3 assume ~T4_E~0 == 1;~T4_E~0 := 2; 152507#L772-3 assume ~T5_E~0 == 1;~T5_E~0 := 2; 152506#L777-3 assume !(~T6_E~0 == 1); 152505#L782-3 assume !(~E_M~0 == 1); 152504#L787-3 assume ~E_1~0 == 1;~E_1~0 := 2; 152503#L792-3 assume ~E_2~0 == 1;~E_2~0 := 2; 152502#L797-3 assume ~E_3~0 == 1;~E_3~0 := 2; 152501#L802-3 assume !(~E_4~0 == 1); 152500#L807-3 assume ~E_5~0 == 1;~E_5~0 := 2; 152499#L812-3 assume ~E_6~0 == 1;~E_6~0 := 2; 152498#L817-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 152494#L508-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 152486#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 152478#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 152469#L1062 assume !(start_simulation_~tmp~3 == 0); 152463#L1062-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 152461#L508-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 152451#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 152445#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 152439#L1017 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 152434#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 152429#L1025 start_simulation_#t~ret18 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 152423#L1075 assume !(start_simulation_~tmp___0~1 != 0); 147625#L1043-3 [2018-11-10 06:54:06,959 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:06,960 INFO L82 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 3 times [2018-11-10 06:54:06,960 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:06,960 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:06,960 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:06,960 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:06,960 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:06,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:54:06,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:54:06,983 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:06,983 INFO L82 PathProgramCache]: Analyzing trace with hash -957488401, now seen corresponding path program 1 times [2018-11-10 06:54:06,984 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:06,984 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:06,984 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:06,984 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 06:54:06,984 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:06,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:07,035 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:07,035 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:07,035 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 06:54:07,036 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 06:54:07,036 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 06:54:07,036 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 06:54:07,036 INFO L87 Difference]: Start difference. First operand 8090 states and 11179 transitions. cyclomatic complexity: 3105 Second operand 5 states. [2018-11-10 06:54:07,140 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:54:07,141 INFO L93 Difference]: Finished difference Result 10242 states and 14170 transitions. [2018-11-10 06:54:07,141 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-10 06:54:07,141 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10242 states and 14170 transitions. [2018-11-10 06:54:07,161 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 10040 [2018-11-10 06:54:07,226 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10242 states to 10242 states and 14170 transitions. [2018-11-10 06:54:07,226 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10242 [2018-11-10 06:54:07,230 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10242 [2018-11-10 06:54:07,230 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10242 states and 14170 transitions. [2018-11-10 06:54:07,234 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:54:07,235 INFO L705 BuchiCegarLoop]: Abstraction has 10242 states and 14170 transitions. [2018-11-10 06:54:07,238 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10242 states and 14170 transitions. [2018-11-10 06:54:07,291 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10242 to 8114. [2018-11-10 06:54:07,291 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8114 states. [2018-11-10 06:54:07,301 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8114 states to 8114 states and 11098 transitions. [2018-11-10 06:54:07,301 INFO L728 BuchiCegarLoop]: Abstraction has 8114 states and 11098 transitions. [2018-11-10 06:54:07,301 INFO L608 BuchiCegarLoop]: Abstraction has 8114 states and 11098 transitions. [2018-11-10 06:54:07,301 INFO L442 BuchiCegarLoop]: ======== Iteration 19============ [2018-11-10 06:54:07,301 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8114 states and 11098 transitions. [2018-11-10 06:54:07,318 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7960 [2018-11-10 06:54:07,318 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:54:07,318 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:54:07,319 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:07,319 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:07,319 INFO L793 eck$LassoCheckResult]: Stem: 166228#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 166081#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 165536#L1006 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 165537#L458 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 165987#L465 assume ~m_i~0 == 1;~m_st~0 := 0; 165988#L465-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 165991#L470-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 165832#L475-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 165833#L480-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 165903#L485-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 165632#L490-1 assume ~t6_i~0 == 1;~t6_st~0 := 0; 165633#L495-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 166000#L674 assume !(~M_E~0 == 0); 166001#L674-2 assume !(~T1_E~0 == 0); 166011#L679-1 assume !(~T2_E~0 == 0); 165854#L684-1 assume !(~T3_E~0 == 0); 165855#L689-1 assume !(~T4_E~0 == 0); 166201#L694-1 assume !(~T5_E~0 == 0); 165672#L699-1 assume !(~T6_E~0 == 0); 165673#L704-1 assume !(~E_M~0 == 0); 165494#L709-1 assume !(~E_1~0 == 0); 165495#L714-1 assume !(~E_2~0 == 0); 165590#L719-1 assume !(~E_3~0 == 0); 165591#L724-1 assume !(~E_4~0 == 0); 165998#L729-1 assume !(~E_5~0 == 0); 165999#L734-1 assume !(~E_6~0 == 0); 165846#L739-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 165711#L324 assume !(~m_pc~0 == 1); 165641#L324-2 is_master_triggered_~__retres1~0 := 0; 165728#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 165638#L336 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 165639#L839 assume !(activate_threads_~tmp~1 != 0); 166018#L839-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 165782#L343 assume !(~t1_pc~0 == 1); 165783#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 165777#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 165778#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 165958#L847 assume !(activate_threads_~tmp___0~0 != 0); 166269#L847-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 166154#L362 assume !(~t2_pc~0 == 1); 166095#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 166096#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 166150#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 166258#L855 assume !(activate_threads_~tmp___1~0 != 0); 166281#L855-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 166286#L381 assume !(~t3_pc~0 == 1); 166329#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 166325#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 166326#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 165552#L863 assume !(activate_threads_~tmp___2~0 != 0); 165521#L863-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 165522#L400 assume !(~t4_pc~0 == 1); 165567#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 165568#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 165585#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 165750#L871 assume !(activate_threads_~tmp___3~0 != 0); 165868#L871-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 165876#L419 assume !(~t5_pc~0 == 1); 165765#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 165904#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 165834#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 165835#L879 assume !(activate_threads_~tmp___4~0 != 0); 166171#L879-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 166172#L438 assume !(~t6_pc~0 == 1); 166186#L438-2 is_transmit6_triggered_~__retres1~6 := 0; 166187#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 166139#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 166140#L887 assume !(activate_threads_~tmp___5~0 != 0); 166354#L887-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 165606#L752 assume !(~M_E~0 == 1); 165592#L752-2 assume !(~T1_E~0 == 1); 165593#L757-1 assume !(~T2_E~0 == 1); 165993#L762-1 assume !(~T3_E~0 == 1); 165994#L767-1 assume !(~T4_E~0 == 1); 165842#L772-1 assume !(~T5_E~0 == 1); 165843#L777-1 assume !(~T6_E~0 == 1); 166199#L782-1 assume !(~E_M~0 == 1); 165666#L787-1 assume !(~E_1~0 == 1); 165667#L792-1 assume !(~E_2~0 == 1); 165523#L797-1 assume !(~E_3~0 == 1); 165524#L802-1 assume !(~E_4~0 == 1); 165604#L807-1 assume !(~E_5~0 == 1); 165605#L812-1 assume !(~E_6~0 == 1); 166019#L817-1 assume { :end_inline_reset_delta_events } true; 166020#L1043-3 [2018-11-10 06:54:07,320 INFO L795 eck$LassoCheckResult]: Loop: 166020#L1043-3 assume true; 168628#L1043-1 assume !false; 168547#L1044 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 168541#L649 assume true; 168538#L555-1 assume !false; 168535#L556 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 168531#L508 assume !(~m_st~0 == 0); 168524#L512 assume !(~t1_st~0 == 0); 168525#L516 assume !(~t2_st~0 == 0); 168528#L520 assume !(~t3_st~0 == 0); 168530#L524 assume !(~t4_st~0 == 0); 168526#L528 assume !(~t5_st~0 == 0); 168527#L532 assume !(~t6_st~0 == 0);exists_runnable_thread_~__retres1~7 := 0; 168529#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 168518#L546 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 168519#L560 assume !(eval_~tmp~0 != 0); 169525#L664 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 169523#L458-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 169521#L674-3 assume ~M_E~0 == 0;~M_E~0 := 1; 169519#L674-5 assume ~T1_E~0 == 0;~T1_E~0 := 1; 169517#L679-3 assume !(~T2_E~0 == 0); 169515#L684-3 assume !(~T3_E~0 == 0); 169513#L689-3 assume ~T4_E~0 == 0;~T4_E~0 := 1; 169511#L694-3 assume ~T5_E~0 == 0;~T5_E~0 := 1; 169509#L699-3 assume !(~T6_E~0 == 0); 169507#L704-3 assume !(~E_M~0 == 0); 169505#L709-3 assume ~E_1~0 == 0;~E_1~0 := 1; 169503#L714-3 assume ~E_2~0 == 0;~E_2~0 := 1; 169501#L719-3 assume !(~E_3~0 == 0); 169498#L724-3 assume !(~E_4~0 == 0); 169496#L729-3 assume ~E_5~0 == 0;~E_5~0 := 1; 169494#L734-3 assume ~E_6~0 == 0;~E_6~0 := 1; 169492#L739-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 169489#L324-24 assume !(~m_pc~0 == 1); 169487#L324-26 is_master_triggered_~__retres1~0 := 0; 169484#L335-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 169482#L336-8 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 169480#L839-24 assume !(activate_threads_~tmp~1 != 0); 169478#L839-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 169476#L343-24 assume !(~t1_pc~0 == 1); 169472#L343-26 is_transmit1_triggered_~__retres1~1 := 0; 169469#L354-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 169466#L355-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 169463#L847-24 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 169460#L847-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 169457#L362-24 assume ~t2_pc~0 == 1; 169454#L363-8 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 169449#L373-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 169445#L374-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 169441#L855-24 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 169437#L855-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 169434#L381-24 assume !(~t3_pc~0 == 1); 169431#L381-26 is_transmit3_triggered_~__retres1~3 := 0; 169426#L392-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 169422#L393-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 169417#L863-24 assume !(activate_threads_~tmp___2~0 != 0); 169412#L863-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 169407#L400-24 assume !(~t4_pc~0 == 1); 169400#L400-26 is_transmit4_triggered_~__retres1~4 := 0; 169394#L411-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 169390#L412-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 169386#L871-24 assume activate_threads_~tmp___3~0 != 0;~t4_st~0 := 0; 168840#L871-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 168782#L419-24 assume ~t5_pc~0 == 1; 168779#L420-8 assume ~E_5~0 == 1;is_transmit5_triggered_~__retres1~5 := 1; 168776#L430-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 168771#L431-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 168767#L879-24 assume activate_threads_~tmp___4~0 != 0;~t5_st~0 := 0; 168764#L879-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 168760#L438-24 assume !(~t6_pc~0 == 1); 168756#L438-26 is_transmit6_triggered_~__retres1~6 := 0; 168752#L449-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 168748#L450-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 168745#L887-24 assume activate_threads_~tmp___5~0 != 0;~t6_st~0 := 0; 168742#L887-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 168739#L752-3 assume ~M_E~0 == 1;~M_E~0 := 2; 168736#L752-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 168733#L757-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 168730#L762-3 assume !(~T3_E~0 == 1); 168726#L767-3 assume ~T4_E~0 == 1;~T4_E~0 := 2; 168723#L772-3 assume ~T5_E~0 == 1;~T5_E~0 := 2; 168720#L777-3 assume !(~T6_E~0 == 1); 168717#L782-3 assume !(~E_M~0 == 1); 168714#L787-3 assume ~E_1~0 == 1;~E_1~0 := 2; 168711#L792-3 assume ~E_2~0 == 1;~E_2~0 := 2; 168708#L797-3 assume ~E_3~0 == 1;~E_3~0 := 2; 168705#L802-3 assume !(~E_4~0 == 1); 168700#L807-3 assume ~E_5~0 == 1;~E_5~0 := 2; 168696#L812-3 assume ~E_6~0 == 1;~E_6~0 := 2; 168692#L817-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 168684#L508-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 168677#L545-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 168673#L546-1 start_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 168668#L1062 assume !(start_simulation_~tmp~3 == 0); 168664#L1062-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret16, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 168660#L508-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 168652#L545-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 168648#L546-2 stop_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret16;havoc stop_simulation_#t~ret16; 168644#L1017 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 168640#L1024 stop_simulation_#res := stop_simulation_~__retres2~0; 168636#L1025 start_simulation_#t~ret18 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 168633#L1075 assume !(start_simulation_~tmp___0~1 != 0); 166020#L1043-3 [2018-11-10 06:54:07,320 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:07,320 INFO L82 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 4 times [2018-11-10 06:54:07,320 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:07,320 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:07,321 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:07,321 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:07,321 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:07,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:54:07,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:54:07,345 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:07,345 INFO L82 PathProgramCache]: Analyzing trace with hash 1651299057, now seen corresponding path program 1 times [2018-11-10 06:54:07,345 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:07,345 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:07,346 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:07,346 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 06:54:07,346 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:07,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:07,390 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:07,390 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:07,390 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:54:07,390 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 06:54:07,391 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 06:54:07,391 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 06:54:07,391 INFO L87 Difference]: Start difference. First operand 8114 states and 11098 transitions. cyclomatic complexity: 3000 Second operand 3 states. [2018-11-10 06:54:07,434 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:54:07,434 INFO L93 Difference]: Finished difference Result 12253 states and 16533 transitions. [2018-11-10 06:54:07,434 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 06:54:07,435 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12253 states and 16533 transitions. [2018-11-10 06:54:07,469 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 11572 [2018-11-10 06:54:07,496 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12253 states to 12253 states and 16533 transitions. [2018-11-10 06:54:07,496 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12253 [2018-11-10 06:54:07,502 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12253 [2018-11-10 06:54:07,502 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12253 states and 16533 transitions. [2018-11-10 06:54:07,509 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:54:07,509 INFO L705 BuchiCegarLoop]: Abstraction has 12253 states and 16533 transitions. [2018-11-10 06:54:07,515 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12253 states and 16533 transitions. [2018-11-10 06:54:07,583 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12253 to 12253. [2018-11-10 06:54:07,583 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12253 states. [2018-11-10 06:54:07,597 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12253 states to 12253 states and 16533 transitions. [2018-11-10 06:54:07,597 INFO L728 BuchiCegarLoop]: Abstraction has 12253 states and 16533 transitions. [2018-11-10 06:54:07,597 INFO L608 BuchiCegarLoop]: Abstraction has 12253 states and 16533 transitions. [2018-11-10 06:54:07,597 INFO L442 BuchiCegarLoop]: ======== Iteration 20============ [2018-11-10 06:54:07,597 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12253 states and 16533 transitions. [2018-11-10 06:54:07,623 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 11572 [2018-11-10 06:54:07,623 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:54:07,623 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:54:07,624 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:07,624 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:07,624 INFO L793 eck$LassoCheckResult]: Stem: 186542#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 186404#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 185908#L1006 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 185909#L458 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 186311#L465 assume ~m_i~0 == 1;~m_st~0 := 0; 186312#L465-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 186315#L470-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 186175#L475-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 186176#L480-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 186236#L485-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 185998#L490-1 assume ~t6_i~0 == 1;~t6_st~0 := 0; 185999#L495-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 186324#L674 assume !(~M_E~0 == 0); 186325#L674-2 assume !(~T1_E~0 == 0); 186336#L679-1 assume !(~T2_E~0 == 0); 186197#L684-1 assume !(~T3_E~0 == 0); 186198#L689-1 assume !(~T4_E~0 == 0); 186515#L694-1 assume !(~T5_E~0 == 0); 186035#L699-1 assume !(~T6_E~0 == 0); 186036#L704-1 assume !(~E_M~0 == 0); 185867#L709-1 assume !(~E_1~0 == 0); 185868#L714-1 assume !(~E_2~0 == 0); 185956#L719-1 assume !(~E_3~0 == 0); 185957#L724-1 assume !(~E_4~0 == 0); 186322#L729-1 assume !(~E_5~0 == 0); 186323#L734-1 assume !(~E_6~0 == 0); 186190#L739-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 186069#L324 assume !(~m_pc~0 == 1); 186007#L324-2 is_master_triggered_~__retres1~0 := 0; 186083#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 186004#L336 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 186005#L839 assume !(activate_threads_~tmp~1 != 0); 186342#L839-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 186126#L343 assume !(~t1_pc~0 == 1); 186127#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 186124#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 186125#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 186284#L847 assume !(activate_threads_~tmp___0~0 != 0); 186566#L847-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 186470#L362 assume !(~t2_pc~0 == 1); 186413#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 186414#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 186469#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 186559#L855 assume !(activate_threads_~tmp___1~0 != 0); 186573#L855-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 186577#L381 assume !(~t3_pc~0 == 1); 186613#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 186611#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 186612#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 185924#L863 assume !(activate_threads_~tmp___2~0 != 0); 185893#L863-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 185894#L400 assume !(~t4_pc~0 == 1); 185936#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 185937#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 185952#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 186097#L871 assume !(activate_threads_~tmp___3~0 != 0); 186210#L871-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 186216#L419 assume !(~t5_pc~0 == 1); 186110#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 186237#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 186177#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 186178#L879 assume !(activate_threads_~tmp___4~0 != 0); 186485#L879-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 186486#L438 assume !(~t6_pc~0 == 1); 186501#L438-2 is_transmit6_triggered_~__retres1~6 := 0; 186502#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 186456#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 186457#L887 assume !(activate_threads_~tmp___5~0 != 0); 186636#L887-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 185972#L752 assume !(~M_E~0 == 1); 185958#L752-2 assume !(~T1_E~0 == 1); 185959#L757-1 assume !(~T2_E~0 == 1); 186317#L762-1 assume !(~T3_E~0 == 1); 186318#L767-1 assume !(~T4_E~0 == 1); 186186#L772-1 assume !(~T5_E~0 == 1); 186187#L777-1 assume !(~T6_E~0 == 1); 186513#L782-1 assume !(~E_M~0 == 1); 186029#L787-1 assume !(~E_1~0 == 1); 186030#L792-1 assume !(~E_2~0 == 1); 185898#L797-1 assume !(~E_3~0 == 1); 185899#L802-1 assume !(~E_4~0 == 1); 185970#L807-1 assume !(~E_5~0 == 1); 185971#L812-1 assume !(~E_6~0 == 1); 186343#L817-1 assume { :end_inline_reset_delta_events } true; 186344#L1043-3 assume true; 190273#L1043-1 assume !false; 190261#L1044 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 190250#L649 [2018-11-10 06:54:07,624 INFO L795 eck$LassoCheckResult]: Loop: 190250#L649 assume true; 190245#L555-1 assume !false; 190240#L556 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 190234#L508 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 190227#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 190220#L546 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 190213#L560 assume eval_~tmp~0 != 0; 190206#L560-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 190198#L568 assume !(eval_~tmp_ndt_1~0 != 0); 190192#L565 assume !(~t1_st~0 == 0); 190188#L579 assume !(~t2_st~0 == 0); 190195#L593 assume !(~t3_st~0 == 0); 190191#L607 assume !(~t4_st~0 == 0); 190186#L621 assume !(~t5_st~0 == 0); 190260#L635 assume !(~t6_st~0 == 0); 190250#L649 [2018-11-10 06:54:07,624 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:07,624 INFO L82 PathProgramCache]: Analyzing trace with hash 931954781, now seen corresponding path program 1 times [2018-11-10 06:54:07,625 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:07,625 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:07,625 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:07,625 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:07,625 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:07,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:54:07,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:54:07,649 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:07,649 INFO L82 PathProgramCache]: Analyzing trace with hash 209649836, now seen corresponding path program 1 times [2018-11-10 06:54:07,650 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:07,650 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:07,650 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:07,650 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:07,650 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:07,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:54:07,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:54:07,655 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:07,655 INFO L82 PathProgramCache]: Analyzing trace with hash 1255029968, now seen corresponding path program 1 times [2018-11-10 06:54:07,655 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:07,655 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:07,656 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:07,656 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:07,656 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:07,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:07,693 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:07,693 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:07,694 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:54:07,811 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 06:54:07,812 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 06:54:07,812 INFO L87 Difference]: Start difference. First operand 12253 states and 16533 transitions. cyclomatic complexity: 4304 Second operand 3 states. [2018-11-10 06:54:07,955 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:54:07,955 INFO L93 Difference]: Finished difference Result 23404 states and 31275 transitions. [2018-11-10 06:54:07,957 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 06:54:07,957 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23404 states and 31275 transitions. [2018-11-10 06:54:08,017 INFO L131 ngComponentsAnalysis]: Automaton has 36 accepting balls. 21000 [2018-11-10 06:54:08,049 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23404 states to 23404 states and 31275 transitions. [2018-11-10 06:54:08,050 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23404 [2018-11-10 06:54:08,059 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23404 [2018-11-10 06:54:08,059 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23404 states and 31275 transitions. [2018-11-10 06:54:08,069 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:54:08,069 INFO L705 BuchiCegarLoop]: Abstraction has 23404 states and 31275 transitions. [2018-11-10 06:54:08,079 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23404 states and 31275 transitions. [2018-11-10 06:54:08,168 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23404 to 22740. [2018-11-10 06:54:08,168 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22740 states. [2018-11-10 06:54:08,188 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22740 states to 22740 states and 30427 transitions. [2018-11-10 06:54:08,188 INFO L728 BuchiCegarLoop]: Abstraction has 22740 states and 30427 transitions. [2018-11-10 06:54:08,188 INFO L608 BuchiCegarLoop]: Abstraction has 22740 states and 30427 transitions. [2018-11-10 06:54:08,188 INFO L442 BuchiCegarLoop]: ======== Iteration 21============ [2018-11-10 06:54:08,188 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22740 states and 30427 transitions. [2018-11-10 06:54:08,226 INFO L131 ngComponentsAnalysis]: Automaton has 36 accepting balls. 20336 [2018-11-10 06:54:08,226 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:54:08,226 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:54:08,227 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:08,227 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:08,228 INFO L793 eck$LassoCheckResult]: Stem: 222227#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 222079#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 221578#L1006 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 221579#L458 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 221989#L465 assume ~m_i~0 == 1;~m_st~0 := 0; 221990#L465-2 assume !(~t1_i~0 == 1);~t1_st~0 := 2; 221994#L470-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 221837#L475-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 221838#L480-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 221904#L485-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 221676#L490-1 assume ~t6_i~0 == 1;~t6_st~0 := 0; 221677#L495-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 222005#L674 assume !(~M_E~0 == 0); 222006#L674-2 assume !(~T1_E~0 == 0); 222017#L679-1 assume !(~T2_E~0 == 0); 221857#L684-1 assume !(~T3_E~0 == 0); 221858#L689-1 assume !(~T4_E~0 == 0); 222201#L694-1 assume !(~T5_E~0 == 0); 221715#L699-1 assume !(~T6_E~0 == 0); 221716#L704-1 assume !(~E_M~0 == 0); 221532#L709-1 assume !(~E_1~0 == 0); 221533#L714-1 assume !(~E_2~0 == 0); 221637#L719-1 assume !(~E_3~0 == 0); 221638#L724-1 assume !(~E_4~0 == 0); 222003#L729-1 assume !(~E_5~0 == 0); 222004#L734-1 assume !(~E_6~0 == 0); 221850#L739-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 221744#L324 assume !(~m_pc~0 == 1); 221687#L324-2 is_master_triggered_~__retres1~0 := 0; 221755#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 221684#L336 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 221685#L839 assume !(activate_threads_~tmp~1 != 0); 222026#L839-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 221791#L343 assume !(~t1_pc~0 == 1); 221792#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 221786#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 221787#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 221959#L847 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 222252#L847-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 222155#L362 assume !(~t2_pc~0 == 1); 222093#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 222094#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 222151#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 222247#L855 assume !(activate_threads_~tmp___1~0 != 0); 222266#L855-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 222271#L381 assume !(~t3_pc~0 == 1); 222307#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 222304#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 222305#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 221594#L863 assume !(activate_threads_~tmp___2~0 != 0); 221595#L863-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 221632#L400 assume !(~t4_pc~0 == 1); 221633#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 221630#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 221631#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 221870#L871 assume !(activate_threads_~tmp___3~0 != 0); 221871#L871-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 221907#L419 assume !(~t5_pc~0 == 1); 221908#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 221905#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 221906#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 222185#L879 assume !(activate_threads_~tmp___4~0 != 0); 222186#L879-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 222336#L438 assume !(~t6_pc~0 == 1); 222337#L438-2 is_transmit6_triggered_~__retres1~6 := 0; 222334#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 222335#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 222329#L887 assume !(activate_threads_~tmp___5~0 != 0); 222330#L887-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 221652#L752 assume !(~M_E~0 == 1); 221653#L752-2 assume !(~T1_E~0 == 1); 222338#L757-1 assume !(~T2_E~0 == 1); 222339#L762-1 assume !(~T3_E~0 == 1); 222375#L767-1 assume !(~T4_E~0 == 1); 222376#L772-1 assume !(~T5_E~0 == 1); 222325#L777-1 assume !(~T6_E~0 == 1); 222326#L782-1 assume !(~E_M~0 == 1); 221709#L787-1 assume !(~E_1~0 == 1); 221710#L792-1 assume !(~E_2~0 == 1); 221563#L797-1 assume !(~E_3~0 == 1); 221564#L802-1 assume !(~E_4~0 == 1); 221650#L807-1 assume !(~E_5~0 == 1); 221651#L812-1 assume !(~E_6~0 == 1); 222028#L817-1 assume { :end_inline_reset_delta_events } true; 222029#L1043-3 assume true; 228469#L1043-1 assume !false; 228467#L1044 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 228463#L649 [2018-11-10 06:54:08,228 INFO L795 eck$LassoCheckResult]: Loop: 228463#L649 assume true; 228462#L555-1 assume !false; 228461#L556 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 228459#L508 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 228458#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 228457#L546 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 228456#L560 assume eval_~tmp~0 != 0; 228455#L560-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 228454#L568 assume !(eval_~tmp_ndt_1~0 != 0); 228258#L565 assume ~t1_st~0 == 0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 225435#L582 assume !(eval_~tmp_ndt_2~0 != 0); 225437#L579 assume !(~t2_st~0 == 0); 228477#L593 assume !(~t3_st~0 == 0); 228476#L607 assume !(~t4_st~0 == 0); 228473#L621 assume !(~t5_st~0 == 0); 228466#L635 assume !(~t6_st~0 == 0); 228463#L649 [2018-11-10 06:54:08,228 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:08,228 INFO L82 PathProgramCache]: Analyzing trace with hash -1315174307, now seen corresponding path program 1 times [2018-11-10 06:54:08,228 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:08,228 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:08,229 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:08,229 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:08,229 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:08,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:08,258 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:08,258 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:08,259 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:54:08,259 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 06:54:08,259 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:08,259 INFO L82 PathProgramCache]: Analyzing trace with hash -1945929661, now seen corresponding path program 1 times [2018-11-10 06:54:08,259 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:08,259 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:08,260 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:08,260 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:08,260 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:08,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:54:08,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:54:08,334 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 06:54:08,334 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 06:54:08,334 INFO L87 Difference]: Start difference. First operand 22740 states and 30427 transitions. cyclomatic complexity: 7723 Second operand 3 states. [2018-11-10 06:54:08,363 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:54:08,363 INFO L93 Difference]: Finished difference Result 16033 states and 21432 transitions. [2018-11-10 06:54:08,363 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 06:54:08,363 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16033 states and 21432 transitions. [2018-11-10 06:54:08,403 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 15072 [2018-11-10 06:54:08,433 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16033 states to 16033 states and 21432 transitions. [2018-11-10 06:54:08,433 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16033 [2018-11-10 06:54:08,441 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16033 [2018-11-10 06:54:08,441 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16033 states and 21432 transitions. [2018-11-10 06:54:08,448 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:54:08,448 INFO L705 BuchiCegarLoop]: Abstraction has 16033 states and 21432 transitions. [2018-11-10 06:54:08,456 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16033 states and 21432 transitions. [2018-11-10 06:54:08,543 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16033 to 16033. [2018-11-10 06:54:08,543 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16033 states. [2018-11-10 06:54:08,560 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16033 states to 16033 states and 21432 transitions. [2018-11-10 06:54:08,560 INFO L728 BuchiCegarLoop]: Abstraction has 16033 states and 21432 transitions. [2018-11-10 06:54:08,560 INFO L608 BuchiCegarLoop]: Abstraction has 16033 states and 21432 transitions. [2018-11-10 06:54:08,560 INFO L442 BuchiCegarLoop]: ======== Iteration 22============ [2018-11-10 06:54:08,561 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16033 states and 21432 transitions. [2018-11-10 06:54:08,636 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 15072 [2018-11-10 06:54:08,636 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:54:08,636 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:54:08,638 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:08,638 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:08,638 INFO L793 eck$LassoCheckResult]: Stem: 260975#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 260838#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 260352#L1006 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 260353#L458 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 260758#L465 assume ~m_i~0 == 1;~m_st~0 := 0; 260759#L465-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 260762#L470-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 260618#L475-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 260619#L480-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 260685#L485-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 260439#L490-1 assume ~t6_i~0 == 1;~t6_st~0 := 0; 260440#L495-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 260769#L674 assume !(~M_E~0 == 0); 260770#L674-2 assume !(~T1_E~0 == 0); 260780#L679-1 assume !(~T2_E~0 == 0); 260639#L684-1 assume !(~T3_E~0 == 0); 260640#L689-1 assume !(~T4_E~0 == 0); 260952#L694-1 assume !(~T5_E~0 == 0); 260479#L699-1 assume !(~T6_E~0 == 0); 260480#L704-1 assume !(~E_M~0 == 0); 260311#L709-1 assume !(~E_1~0 == 0); 260312#L714-1 assume !(~E_2~0 == 0); 260401#L719-1 assume !(~E_3~0 == 0); 260402#L724-1 assume !(~E_4~0 == 0); 260767#L729-1 assume !(~E_5~0 == 0); 260768#L734-1 assume !(~E_6~0 == 0); 260632#L739-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 260514#L324 assume !(~m_pc~0 == 1); 260450#L324-2 is_master_triggered_~__retres1~0 := 0; 260529#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 260447#L336 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 260448#L839 assume !(activate_threads_~tmp~1 != 0); 260786#L839-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 260572#L343 assume !(~t1_pc~0 == 1); 260573#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 260567#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 260568#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 260732#L847 assume !(activate_threads_~tmp___0~0 != 0); 261000#L847-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 260912#L362 assume !(~t2_pc~0 == 1); 260852#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 260853#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 260908#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 260994#L855 assume !(activate_threads_~tmp___1~0 != 0); 261008#L855-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 261014#L381 assume !(~t3_pc~0 == 1); 261050#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 261047#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 261048#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 260367#L863 assume !(activate_threads_~tmp___2~0 != 0); 260337#L863-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 260338#L400 assume !(~t4_pc~0 == 1); 260381#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 260382#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 260397#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 260544#L871 assume !(activate_threads_~tmp___3~0 != 0); 260653#L871-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 260660#L419 assume !(~t5_pc~0 == 1); 260556#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 260686#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 260620#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 260621#L879 assume !(activate_threads_~tmp___4~0 != 0); 260928#L879-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 260929#L438 assume !(~t6_pc~0 == 1); 260943#L438-2 is_transmit6_triggered_~__retres1~6 := 0; 260944#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 260896#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 260897#L887 assume !(activate_threads_~tmp___5~0 != 0); 261067#L887-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 260416#L752 assume !(~M_E~0 == 1); 260403#L752-2 assume !(~T1_E~0 == 1); 260404#L757-1 assume !(~T2_E~0 == 1); 260764#L762-1 assume !(~T3_E~0 == 1); 260765#L767-1 assume !(~T4_E~0 == 1); 260629#L772-1 assume !(~T5_E~0 == 1); 260630#L777-1 assume !(~T6_E~0 == 1); 260950#L782-1 assume !(~E_M~0 == 1); 260473#L787-1 assume !(~E_1~0 == 1); 260474#L792-1 assume !(~E_2~0 == 1); 260339#L797-1 assume !(~E_3~0 == 1); 260340#L802-1 assume !(~E_4~0 == 1); 260414#L807-1 assume !(~E_5~0 == 1); 260415#L812-1 assume !(~E_6~0 == 1); 260787#L817-1 assume { :end_inline_reset_delta_events } true; 260788#L1043-3 assume true; 264282#L1043-1 assume !false; 264280#L1044 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 264275#L649 [2018-11-10 06:54:08,639 INFO L795 eck$LassoCheckResult]: Loop: 264275#L649 assume true; 264273#L555-1 assume !false; 264272#L556 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 264270#L508 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 264269#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 264268#L546 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 264267#L560 assume eval_~tmp~0 != 0; 264263#L560-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 264261#L568 assume !(eval_~tmp_ndt_1~0 != 0); 264260#L565 assume ~t1_st~0 == 0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 264258#L582 assume !(eval_~tmp_ndt_2~0 != 0); 264259#L579 assume !(~t2_st~0 == 0); 264295#L593 assume !(~t3_st~0 == 0); 264293#L607 assume !(~t4_st~0 == 0); 264290#L621 assume !(~t5_st~0 == 0); 264279#L635 assume !(~t6_st~0 == 0); 264275#L649 [2018-11-10 06:54:08,639 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:08,639 INFO L82 PathProgramCache]: Analyzing trace with hash 931954781, now seen corresponding path program 2 times [2018-11-10 06:54:08,639 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:08,639 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:08,640 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:08,640 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:08,640 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:08,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:54:08,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:54:08,662 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:08,662 INFO L82 PathProgramCache]: Analyzing trace with hash -1945929661, now seen corresponding path program 2 times [2018-11-10 06:54:08,662 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:08,663 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:08,663 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:08,663 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 06:54:08,663 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:08,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:54:08,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:54:08,667 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:08,668 INFO L82 PathProgramCache]: Analyzing trace with hash 396083359, now seen corresponding path program 1 times [2018-11-10 06:54:08,668 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:08,668 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:08,668 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:08,668 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 06:54:08,668 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:08,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:08,697 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:08,697 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:08,697 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:54:08,767 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 06:54:08,767 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 06:54:08,767 INFO L87 Difference]: Start difference. First operand 16033 states and 21432 transitions. cyclomatic complexity: 5423 Second operand 3 states. [2018-11-10 06:54:08,855 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:54:08,856 INFO L93 Difference]: Finished difference Result 30317 states and 40300 transitions. [2018-11-10 06:54:08,858 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 06:54:08,858 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30317 states and 40300 transitions. [2018-11-10 06:54:08,949 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 28488 [2018-11-10 06:54:09,009 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30317 states to 30317 states and 40300 transitions. [2018-11-10 06:54:09,009 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30317 [2018-11-10 06:54:09,024 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30317 [2018-11-10 06:54:09,024 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30317 states and 40300 transitions. [2018-11-10 06:54:09,039 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:54:09,039 INFO L705 BuchiCegarLoop]: Abstraction has 30317 states and 40300 transitions. [2018-11-10 06:54:09,052 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30317 states and 40300 transitions. [2018-11-10 06:54:09,199 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30317 to 28661. [2018-11-10 06:54:09,199 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28661 states. [2018-11-10 06:54:09,223 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28661 states to 28661 states and 38236 transitions. [2018-11-10 06:54:09,223 INFO L728 BuchiCegarLoop]: Abstraction has 28661 states and 38236 transitions. [2018-11-10 06:54:09,223 INFO L608 BuchiCegarLoop]: Abstraction has 28661 states and 38236 transitions. [2018-11-10 06:54:09,223 INFO L442 BuchiCegarLoop]: ======== Iteration 23============ [2018-11-10 06:54:09,223 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28661 states and 38236 transitions. [2018-11-10 06:54:09,269 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 26832 [2018-11-10 06:54:09,269 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:54:09,269 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:54:09,269 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:09,270 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:09,270 INFO L793 eck$LassoCheckResult]: Stem: 307324#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 307192#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 306715#L1006 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 306716#L458 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 307106#L465 assume ~m_i~0 == 1;~m_st~0 := 0; 307107#L465-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 307111#L470-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 306969#L475-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 306970#L480-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 307035#L485-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 306807#L490-1 assume ~t6_i~0 == 1;~t6_st~0 := 0; 306808#L495-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 307118#L674 assume !(~M_E~0 == 0); 307119#L674-2 assume !(~T1_E~0 == 0); 307131#L679-1 assume !(~T2_E~0 == 0); 306990#L684-1 assume !(~T3_E~0 == 0); 306991#L689-1 assume !(~T4_E~0 == 0); 307299#L694-1 assume !(~T5_E~0 == 0); 306847#L699-1 assume !(~T6_E~0 == 0); 306848#L704-1 assume !(~E_M~0 == 0); 306669#L709-1 assume !(~E_1~0 == 0); 306670#L714-1 assume !(~E_2~0 == 0); 306769#L719-1 assume !(~E_3~0 == 0); 306770#L724-1 assume !(~E_4~0 == 0); 307116#L729-1 assume !(~E_5~0 == 0); 307117#L734-1 assume !(~E_6~0 == 0); 306983#L739-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 306877#L324 assume !(~m_pc~0 == 1); 306818#L324-2 is_master_triggered_~__retres1~0 := 0; 306887#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 306815#L336 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 306816#L839 assume !(activate_threads_~tmp~1 != 0); 307135#L839-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 306921#L343 assume !(~t1_pc~0 == 1); 306922#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 306916#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 306917#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 307082#L847 assume !(activate_threads_~tmp___0~0 != 0); 307359#L847-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 307266#L362 assume !(~t2_pc~0 == 1); 307206#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 307207#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 307262#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 307348#L855 assume !(activate_threads_~tmp___1~0 != 0); 307369#L855-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 307373#L381 assume !(~t3_pc~0 == 1); 307408#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 307405#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 307406#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 306730#L863 assume !(activate_threads_~tmp___2~0 != 0); 306698#L863-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 306699#L400 assume !(~t4_pc~0 == 1); 306746#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 306747#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 306765#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 306897#L871 assume !(activate_threads_~tmp___3~0 != 0); 307002#L871-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 307009#L419 assume !(~t5_pc~0 == 1); 306905#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 307036#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 306971#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 306972#L879 assume !(activate_threads_~tmp___4~0 != 0); 307281#L879-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 307282#L438 assume !(~t6_pc~0 == 1); 307290#L438-2 is_transmit6_triggered_~__retres1~6 := 0; 307291#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 307251#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 307252#L887 assume !(activate_threads_~tmp___5~0 != 0); 307425#L887-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 306784#L752 assume !(~M_E~0 == 1); 306771#L752-2 assume !(~T1_E~0 == 1); 306772#L757-1 assume !(~T2_E~0 == 1); 307113#L762-1 assume !(~T3_E~0 == 1); 307114#L767-1 assume !(~T4_E~0 == 1); 306979#L772-1 assume !(~T5_E~0 == 1); 306980#L777-1 assume !(~T6_E~0 == 1); 307297#L782-1 assume !(~E_M~0 == 1); 306841#L787-1 assume !(~E_1~0 == 1); 306842#L792-1 assume !(~E_2~0 == 1); 306700#L797-1 assume !(~E_3~0 == 1); 306701#L802-1 assume !(~E_4~0 == 1); 306782#L807-1 assume !(~E_5~0 == 1); 306783#L812-1 assume !(~E_6~0 == 1); 307137#L817-1 assume { :end_inline_reset_delta_events } true; 307138#L1043-3 assume true; 313912#L1043-1 assume !false; 313909#L1044 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 313904#L649 [2018-11-10 06:54:09,270 INFO L795 eck$LassoCheckResult]: Loop: 313904#L649 assume true; 313902#L555-1 assume !false; 313900#L556 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 313897#L508 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 313896#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 313895#L546 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 313894#L560 assume eval_~tmp~0 != 0; 313891#L560-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 313888#L568 assume !(eval_~tmp_ndt_1~0 != 0); 313886#L565 assume ~t1_st~0 == 0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 313883#L582 assume !(eval_~tmp_ndt_2~0 != 0); 313881#L579 assume ~t2_st~0 == 0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 310388#L596 assume !(eval_~tmp_ndt_3~0 != 0); 313811#L593 assume !(~t3_st~0 == 0); 313802#L607 assume !(~t4_st~0 == 0); 313794#L621 assume !(~t5_st~0 == 0); 313908#L635 assume !(~t6_st~0 == 0); 313904#L649 [2018-11-10 06:54:09,270 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:09,270 INFO L82 PathProgramCache]: Analyzing trace with hash 931954781, now seen corresponding path program 3 times [2018-11-10 06:54:09,270 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:09,270 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:09,271 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:09,271 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:09,271 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:09,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:54:09,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:54:09,294 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:09,294 INFO L82 PathProgramCache]: Analyzing trace with hash -1852170389, now seen corresponding path program 1 times [2018-11-10 06:54:09,294 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:09,294 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:09,294 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:09,294 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 06:54:09,295 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:09,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:54:09,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:54:09,298 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:09,299 INFO L82 PathProgramCache]: Analyzing trace with hash 2030756495, now seen corresponding path program 1 times [2018-11-10 06:54:09,299 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:09,299 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:09,299 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:09,299 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:09,299 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:09,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:09,329 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:09,329 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:09,329 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:54:09,443 WARN L179 SmtUtils]: Spent 112.00 ms on a formula simplification. DAG size of input: 41 DAG size of output: 39 [2018-11-10 06:54:09,512 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 06:54:09,512 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 06:54:09,512 INFO L87 Difference]: Start difference. First operand 28661 states and 38236 transitions. cyclomatic complexity: 9599 Second operand 3 states. [2018-11-10 06:54:09,609 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:54:09,609 INFO L93 Difference]: Finished difference Result 40249 states and 53476 transitions. [2018-11-10 06:54:09,609 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 06:54:09,609 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40249 states and 53476 transitions. [2018-11-10 06:54:09,690 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 37594 [2018-11-10 06:54:09,742 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40249 states to 40249 states and 53476 transitions. [2018-11-10 06:54:09,742 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 40249 [2018-11-10 06:54:09,758 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 40249 [2018-11-10 06:54:09,758 INFO L73 IsDeterministic]: Start isDeterministic. Operand 40249 states and 53476 transitions. [2018-11-10 06:54:09,772 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:54:09,772 INFO L705 BuchiCegarLoop]: Abstraction has 40249 states and 53476 transitions. [2018-11-10 06:54:09,786 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40249 states and 53476 transitions. [2018-11-10 06:54:10,045 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40249 to 38905. [2018-11-10 06:54:10,045 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 38905 states. [2018-11-10 06:54:10,077 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38905 states to 38905 states and 51796 transitions. [2018-11-10 06:54:10,077 INFO L728 BuchiCegarLoop]: Abstraction has 38905 states and 51796 transitions. [2018-11-10 06:54:10,077 INFO L608 BuchiCegarLoop]: Abstraction has 38905 states and 51796 transitions. [2018-11-10 06:54:10,077 INFO L442 BuchiCegarLoop]: ======== Iteration 24============ [2018-11-10 06:54:10,077 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38905 states and 51796 transitions. [2018-11-10 06:54:10,138 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 36250 [2018-11-10 06:54:10,139 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:54:10,139 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:54:10,139 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:10,139 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:10,139 INFO L793 eck$LassoCheckResult]: Stem: 376291#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 376147#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 375630#L1006 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 375631#L458 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 376060#L465 assume ~m_i~0 == 1;~m_st~0 := 0; 376061#L465-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 376064#L470-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 375909#L475-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 375910#L480-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 375987#L485-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 375726#L490-1 assume ~t6_i~0 == 1;~t6_st~0 := 0; 375727#L495-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 376073#L674 assume !(~M_E~0 == 0); 376074#L674-2 assume !(~T1_E~0 == 0); 376087#L679-1 assume !(~T2_E~0 == 0); 375931#L684-1 assume !(~T3_E~0 == 0); 375932#L689-1 assume !(~T4_E~0 == 0); 376267#L694-1 assume !(~T5_E~0 == 0); 375767#L699-1 assume !(~T6_E~0 == 0); 375768#L704-1 assume !(~E_M~0 == 0); 375587#L709-1 assume !(~E_1~0 == 0); 375588#L714-1 assume !(~E_2~0 == 0); 375688#L719-1 assume !(~E_3~0 == 0); 375689#L724-1 assume !(~E_4~0 == 0); 376071#L729-1 assume !(~E_5~0 == 0); 376072#L734-1 assume !(~E_6~0 == 0); 375923#L739-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 375805#L324 assume !(~m_pc~0 == 1); 375737#L324-2 is_master_triggered_~__retres1~0 := 0; 375819#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 375734#L336 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 375735#L839 assume !(activate_threads_~tmp~1 != 0); 376092#L839-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 375861#L343 assume !(~t1_pc~0 == 1); 375862#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 375856#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 375857#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 376036#L847 assume !(activate_threads_~tmp___0~0 != 0); 376321#L847-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 376227#L362 assume !(~t2_pc~0 == 1); 376161#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 376162#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 376223#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 376312#L855 assume !(activate_threads_~tmp___1~0 != 0); 376331#L855-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 376336#L381 assume !(~t3_pc~0 == 1); 376378#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 376374#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 376375#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 375645#L863 assume !(activate_threads_~tmp___2~0 != 0); 375614#L863-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 375615#L400 assume !(~t4_pc~0 == 1); 375662#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 375663#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 375683#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 375835#L871 assume !(activate_threads_~tmp___3~0 != 0); 375949#L871-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 375956#L419 assume !(~t5_pc~0 == 1); 375844#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 375988#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 375911#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 375912#L879 assume !(activate_threads_~tmp___4~0 != 0); 376244#L879-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 376245#L438 assume !(~t6_pc~0 == 1); 376256#L438-2 is_transmit6_triggered_~__retres1~6 := 0; 376257#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 376209#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 376210#L887 assume !(activate_threads_~tmp___5~0 != 0); 376406#L887-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 375703#L752 assume !(~M_E~0 == 1); 375690#L752-2 assume !(~T1_E~0 == 1); 375691#L757-1 assume !(~T2_E~0 == 1); 376066#L762-1 assume !(~T3_E~0 == 1); 376067#L767-1 assume !(~T4_E~0 == 1); 375919#L772-1 assume !(~T5_E~0 == 1); 375920#L777-1 assume !(~T6_E~0 == 1); 376265#L782-1 assume !(~E_M~0 == 1); 375760#L787-1 assume !(~E_1~0 == 1); 375761#L792-1 assume !(~E_2~0 == 1); 375616#L797-1 assume !(~E_3~0 == 1); 375617#L802-1 assume !(~E_4~0 == 1); 375701#L807-1 assume !(~E_5~0 == 1); 375702#L812-1 assume !(~E_6~0 == 1); 376094#L817-1 assume { :end_inline_reset_delta_events } true; 376095#L1043-3 assume true; 387493#L1043-1 assume !false; 384091#L1044 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 384086#L649 [2018-11-10 06:54:10,140 INFO L795 eck$LassoCheckResult]: Loop: 384086#L649 assume true; 384084#L555-1 assume !false; 384081#L556 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 384078#L508 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 384076#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 384074#L546 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 384072#L560 assume eval_~tmp~0 != 0; 384070#L560-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 384064#L568 assume !(eval_~tmp_ndt_1~0 != 0); 384062#L565 assume ~t1_st~0 == 0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 384061#L582 assume !(eval_~tmp_ndt_2~0 != 0); 384057#L579 assume ~t2_st~0 == 0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 381873#L596 assume !(eval_~tmp_ndt_3~0 != 0); 384053#L593 assume ~t3_st~0 == 0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 384050#L610 assume !(eval_~tmp_ndt_4~0 != 0); 384051#L607 assume !(~t4_st~0 == 0); 403009#L621 assume !(~t5_st~0 == 0); 384090#L635 assume !(~t6_st~0 == 0); 384086#L649 [2018-11-10 06:54:10,140 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:10,140 INFO L82 PathProgramCache]: Analyzing trace with hash 931954781, now seen corresponding path program 4 times [2018-11-10 06:54:10,140 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:10,140 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:10,141 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:10,141 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:10,141 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:10,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:54:10,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:54:10,162 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:10,163 INFO L82 PathProgramCache]: Analyzing trace with hash -1774732924, now seen corresponding path program 1 times [2018-11-10 06:54:10,163 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:10,163 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:10,163 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:10,163 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 06:54:10,163 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:10,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:54:10,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:54:10,168 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:10,168 INFO L82 PathProgramCache]: Analyzing trace with hash -1663083808, now seen corresponding path program 1 times [2018-11-10 06:54:10,168 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:10,168 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:10,169 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:10,169 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:10,169 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:10,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:10,197 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:10,197 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:10,197 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:54:10,290 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 06:54:10,290 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 06:54:10,290 INFO L87 Difference]: Start difference. First operand 38905 states and 51796 transitions. cyclomatic complexity: 12915 Second operand 3 states. [2018-11-10 06:54:10,434 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:54:10,434 INFO L93 Difference]: Finished difference Result 55311 states and 73314 transitions. [2018-11-10 06:54:10,435 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 06:54:10,435 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55311 states and 73314 transitions. [2018-11-10 06:54:10,560 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 51438 [2018-11-10 06:54:10,639 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55311 states to 55311 states and 73314 transitions. [2018-11-10 06:54:10,639 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 55311 [2018-11-10 06:54:10,662 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 55311 [2018-11-10 06:54:10,662 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55311 states and 73314 transitions. [2018-11-10 06:54:10,680 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:54:10,680 INFO L705 BuchiCegarLoop]: Abstraction has 55311 states and 73314 transitions. [2018-11-10 06:54:10,699 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55311 states and 73314 transitions. [2018-11-10 06:54:10,907 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55311 to 53763. [2018-11-10 06:54:10,907 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 53763 states. [2018-11-10 06:54:10,955 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53763 states to 53763 states and 71406 transitions. [2018-11-10 06:54:10,955 INFO L728 BuchiCegarLoop]: Abstraction has 53763 states and 71406 transitions. [2018-11-10 06:54:10,955 INFO L608 BuchiCegarLoop]: Abstraction has 53763 states and 71406 transitions. [2018-11-10 06:54:10,955 INFO L442 BuchiCegarLoop]: ======== Iteration 25============ [2018-11-10 06:54:10,955 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 53763 states and 71406 transitions. [2018-11-10 06:54:11,046 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 49890 [2018-11-10 06:54:11,046 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:54:11,047 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:54:11,047 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:11,047 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:11,047 INFO L793 eck$LassoCheckResult]: Stem: 470496#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 470354#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 469856#L1006 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 469857#L458 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 470267#L465 assume ~m_i~0 == 1;~m_st~0 := 0; 470268#L465-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 470271#L470-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 470121#L475-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 470122#L480-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 470194#L485-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 469946#L490-1 assume ~t6_i~0 == 1;~t6_st~0 := 0; 469947#L495-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 470278#L674 assume !(~M_E~0 == 0); 470279#L674-2 assume !(~T1_E~0 == 0); 470290#L679-1 assume !(~T2_E~0 == 0); 470143#L684-1 assume !(~T3_E~0 == 0); 470144#L689-1 assume !(~T4_E~0 == 0); 470472#L694-1 assume !(~T5_E~0 == 0); 469986#L699-1 assume !(~T6_E~0 == 0); 469987#L704-1 assume !(~E_M~0 == 0); 469811#L709-1 assume !(~E_1~0 == 0); 469812#L714-1 assume !(~E_2~0 == 0); 469908#L719-1 assume !(~E_3~0 == 0); 469909#L724-1 assume !(~E_4~0 == 0); 470276#L729-1 assume !(~E_5~0 == 0); 470277#L734-1 assume !(~E_6~0 == 0); 470135#L739-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 470019#L324 assume !(~m_pc~0 == 1); 469957#L324-2 is_master_triggered_~__retres1~0 := 0; 470031#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 469954#L336 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 469955#L839 assume !(activate_threads_~tmp~1 != 0); 470298#L839-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 470074#L343 assume !(~t1_pc~0 == 1); 470075#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 470069#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 470070#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 470243#L847 assume !(activate_threads_~tmp___0~0 != 0); 470526#L847-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 470431#L362 assume !(~t2_pc~0 == 1); 470368#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 470369#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 470427#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 470514#L855 assume !(activate_threads_~tmp___1~0 != 0); 470533#L855-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 470537#L381 assume !(~t3_pc~0 == 1); 470576#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 470573#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 470574#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 469872#L863 assume !(activate_threads_~tmp___2~0 != 0); 469839#L863-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 469840#L400 assume !(~t4_pc~0 == 1); 469887#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 469888#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 469904#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 470045#L871 assume !(activate_threads_~tmp___3~0 != 0); 470157#L871-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 470165#L419 assume !(~t5_pc~0 == 1); 470058#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 470195#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 470123#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 470124#L879 assume !(activate_threads_~tmp___4~0 != 0); 470447#L879-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 470448#L438 assume !(~t6_pc~0 == 1); 470460#L438-2 is_transmit6_triggered_~__retres1~6 := 0; 470461#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 470415#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 470416#L887 assume !(activate_threads_~tmp___5~0 != 0); 470610#L887-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 469923#L752 assume !(~M_E~0 == 1); 469910#L752-2 assume !(~T1_E~0 == 1); 469911#L757-1 assume !(~T2_E~0 == 1); 470273#L762-1 assume !(~T3_E~0 == 1); 470274#L767-1 assume !(~T4_E~0 == 1); 470131#L772-1 assume !(~T5_E~0 == 1); 470132#L777-1 assume !(~T6_E~0 == 1); 470470#L782-1 assume !(~E_M~0 == 1); 469980#L787-1 assume !(~E_1~0 == 1); 469981#L792-1 assume !(~E_2~0 == 1); 469841#L797-1 assume !(~E_3~0 == 1); 469842#L802-1 assume !(~E_4~0 == 1); 469921#L807-1 assume !(~E_5~0 == 1); 469922#L812-1 assume !(~E_6~0 == 1); 470299#L817-1 assume { :end_inline_reset_delta_events } true; 470300#L1043-3 assume true; 479395#L1043-1 assume !false; 479386#L1044 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 479378#L649 [2018-11-10 06:54:11,047 INFO L795 eck$LassoCheckResult]: Loop: 479378#L649 assume true; 479373#L555-1 assume !false; 479367#L556 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 479361#L508 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 479356#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 479351#L546 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 479347#L560 assume eval_~tmp~0 != 0; 479340#L560-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 479333#L568 assume !(eval_~tmp_ndt_1~0 != 0); 479329#L565 assume ~t1_st~0 == 0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 479325#L582 assume !(eval_~tmp_ndt_2~0 != 0); 477455#L579 assume ~t2_st~0 == 0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 477453#L596 assume !(eval_~tmp_ndt_3~0 != 0); 477452#L593 assume ~t3_st~0 == 0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 477450#L610 assume !(eval_~tmp_ndt_4~0 != 0); 477449#L607 assume ~t4_st~0 == 0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 476433#L624 assume !(eval_~tmp_ndt_5~0 != 0); 476435#L621 assume !(~t5_st~0 == 0); 479385#L635 assume !(~t6_st~0 == 0); 479378#L649 [2018-11-10 06:54:11,047 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:11,047 INFO L82 PathProgramCache]: Analyzing trace with hash 931954781, now seen corresponding path program 5 times [2018-11-10 06:54:11,047 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:11,048 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:11,048 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:11,048 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:11,048 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:11,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:54:11,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:54:11,071 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:11,072 INFO L82 PathProgramCache]: Analyzing trace with hash 811661866, now seen corresponding path program 1 times [2018-11-10 06:54:11,072 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:11,072 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:11,072 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:11,072 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 06:54:11,073 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:11,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:54:11,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:54:11,077 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:11,077 INFO L82 PathProgramCache]: Analyzing trace with hash -22182834, now seen corresponding path program 1 times [2018-11-10 06:54:11,078 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:11,078 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:11,078 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:11,078 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:11,078 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:11,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:11,111 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:11,111 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:11,111 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 06:54:11,237 WARN L179 SmtUtils]: Spent 125.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 45 [2018-11-10 06:54:11,295 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 06:54:11,295 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 06:54:11,295 INFO L87 Difference]: Start difference. First operand 53763 states and 71406 transitions. cyclomatic complexity: 17667 Second operand 3 states. [2018-11-10 06:54:11,567 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:54:11,567 INFO L93 Difference]: Finished difference Result 96477 states and 127782 transitions. [2018-11-10 06:54:11,567 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 06:54:11,568 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 96477 states and 127782 transitions. [2018-11-10 06:54:11,931 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 88824 [2018-11-10 06:54:12,030 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 96477 states to 96477 states and 127782 transitions. [2018-11-10 06:54:12,030 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 96477 [2018-11-10 06:54:12,056 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 96477 [2018-11-10 06:54:12,056 INFO L73 IsDeterministic]: Start isDeterministic. Operand 96477 states and 127782 transitions. [2018-11-10 06:54:12,079 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:54:12,079 INFO L705 BuchiCegarLoop]: Abstraction has 96477 states and 127782 transitions. [2018-11-10 06:54:12,103 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96477 states and 127782 transitions. [2018-11-10 06:54:12,458 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96477 to 93993. [2018-11-10 06:54:12,458 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 93993 states. [2018-11-10 06:54:12,540 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93993 states to 93993 states and 124866 transitions. [2018-11-10 06:54:12,540 INFO L728 BuchiCegarLoop]: Abstraction has 93993 states and 124866 transitions. [2018-11-10 06:54:12,540 INFO L608 BuchiCegarLoop]: Abstraction has 93993 states and 124866 transitions. [2018-11-10 06:54:12,540 INFO L442 BuchiCegarLoop]: ======== Iteration 26============ [2018-11-10 06:54:12,540 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 93993 states and 124866 transitions. [2018-11-10 06:54:12,700 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 86340 [2018-11-10 06:54:12,700 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:54:12,700 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:54:12,701 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:12,701 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:12,701 INFO L793 eck$LassoCheckResult]: Stem: 620786#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 620634#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 620104#L1006 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 620105#L458 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 620531#L465 assume ~m_i~0 == 1;~m_st~0 := 0; 620532#L465-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 620536#L470-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 620378#L475-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 620379#L480-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 620453#L485-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 620200#L490-1 assume ~t6_i~0 == 1;~t6_st~0 := 0; 620201#L495-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 620548#L674 assume !(~M_E~0 == 0); 620549#L674-2 assume !(~T1_E~0 == 0); 620560#L679-1 assume !(~T2_E~0 == 0); 620403#L684-1 assume !(~T3_E~0 == 0); 620404#L689-1 assume !(~T4_E~0 == 0); 620756#L694-1 assume !(~T5_E~0 == 0); 620238#L699-1 assume !(~T6_E~0 == 0); 620239#L704-1 assume !(~E_M~0 == 0); 620059#L709-1 assume !(~E_1~0 == 0); 620060#L714-1 assume !(~E_2~0 == 0); 620159#L719-1 assume !(~E_3~0 == 0); 620160#L724-1 assume !(~E_4~0 == 0); 620543#L729-1 assume !(~E_5~0 == 0); 620544#L734-1 assume !(~E_6~0 == 0); 620394#L739-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 620272#L324 assume !(~m_pc~0 == 1); 620208#L324-2 is_master_triggered_~__retres1~0 := 0; 620284#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 620205#L336 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 620206#L839 assume !(activate_threads_~tmp~1 != 0); 620570#L839-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 620329#L343 assume !(~t1_pc~0 == 1); 620330#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 620327#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 620328#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 620506#L847 assume !(activate_threads_~tmp___0~0 != 0); 620823#L847-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 620708#L362 assume !(~t2_pc~0 == 1); 620643#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 620644#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 620707#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 620810#L855 assume !(activate_threads_~tmp___1~0 != 0); 620833#L855-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 620838#L381 assume !(~t3_pc~0 == 1); 620876#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 620874#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 620875#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 620124#L863 assume !(activate_threads_~tmp___2~0 != 0); 620086#L863-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 620087#L400 assume !(~t4_pc~0 == 1); 620136#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 620137#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 620155#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 620299#L871 assume !(activate_threads_~tmp___3~0 != 0); 620418#L871-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 620425#L419 assume !(~t5_pc~0 == 1); 620313#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 620454#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 620380#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 620381#L879 assume !(activate_threads_~tmp___4~0 != 0); 620727#L879-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 620728#L438 assume !(~t6_pc~0 == 1); 620743#L438-2 is_transmit6_triggered_~__retres1~6 := 0; 620744#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 620693#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 620694#L887 assume !(activate_threads_~tmp___5~0 != 0); 620903#L887-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 620174#L752 assume !(~M_E~0 == 1); 620161#L752-2 assume !(~T1_E~0 == 1); 620162#L757-1 assume !(~T2_E~0 == 1); 620538#L762-1 assume !(~T3_E~0 == 1); 620539#L767-1 assume !(~T4_E~0 == 1); 620390#L772-1 assume !(~T5_E~0 == 1); 620391#L777-1 assume !(~T6_E~0 == 1); 620753#L782-1 assume !(~E_M~0 == 1); 620233#L787-1 assume !(~E_1~0 == 1); 620234#L792-1 assume !(~E_2~0 == 1); 620092#L797-1 assume !(~E_3~0 == 1); 620093#L802-1 assume !(~E_4~0 == 1); 620172#L807-1 assume !(~E_5~0 == 1); 620173#L812-1 assume !(~E_6~0 == 1); 620572#L817-1 assume { :end_inline_reset_delta_events } true; 620573#L1043-3 assume true; 646741#L1043-1 assume !false; 646739#L1044 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 646734#L649 [2018-11-10 06:54:12,701 INFO L795 eck$LassoCheckResult]: Loop: 646734#L649 assume true; 646729#L555-1 assume !false; 646727#L556 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 646724#L508 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 646722#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 646720#L546 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 646718#L560 assume eval_~tmp~0 != 0; 646715#L560-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 646712#L568 assume !(eval_~tmp_ndt_1~0 != 0); 646710#L565 assume ~t1_st~0 == 0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 646707#L582 assume !(eval_~tmp_ndt_2~0 != 0); 646708#L579 assume ~t2_st~0 == 0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 665497#L596 assume !(eval_~tmp_ndt_3~0 != 0); 665611#L593 assume ~t3_st~0 == 0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 677024#L610 assume !(eval_~tmp_ndt_4~0 != 0); 677023#L607 assume ~t4_st~0 == 0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 677022#L624 assume !(eval_~tmp_ndt_5~0 != 0); 646749#L621 assume ~t5_st~0 == 0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 646746#L638 assume !(eval_~tmp_ndt_6~0 != 0); 646738#L635 assume !(~t6_st~0 == 0); 646734#L649 [2018-11-10 06:54:12,701 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:12,701 INFO L82 PathProgramCache]: Analyzing trace with hash 931954781, now seen corresponding path program 6 times [2018-11-10 06:54:12,702 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:12,702 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:12,702 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:12,702 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:12,702 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:12,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:54:12,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:54:12,725 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:12,725 INFO L82 PathProgramCache]: Analyzing trace with hash -608483643, now seen corresponding path program 1 times [2018-11-10 06:54:12,725 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:12,725 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:12,725 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:12,726 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 06:54:12,726 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:12,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:54:12,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:54:12,733 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:12,733 INFO L82 PathProgramCache]: Analyzing trace with hash -687865567, now seen corresponding path program 1 times [2018-11-10 06:54:12,733 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:12,733 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:12,733 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:12,734 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:12,734 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:12,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 06:54:12,769 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 06:54:12,769 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 06:54:12,769 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 06:54:12,870 WARN L179 SmtUtils]: Spent 100.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 48 [2018-11-10 06:54:12,906 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 06:54:12,906 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 06:54:12,906 INFO L87 Difference]: Start difference. First operand 93993 states and 124866 transitions. cyclomatic complexity: 30897 Second operand 3 states. [2018-11-10 06:54:13,504 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 06:54:13,504 INFO L93 Difference]: Finished difference Result 130934 states and 173274 transitions. [2018-11-10 06:54:13,504 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 06:54:13,504 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 130934 states and 173274 transitions. [2018-11-10 06:54:13,811 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 122849 [2018-11-10 06:54:14,002 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 130934 states to 130934 states and 173274 transitions. [2018-11-10 06:54:14,002 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 130934 [2018-11-10 06:54:14,052 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 130934 [2018-11-10 06:54:14,053 INFO L73 IsDeterministic]: Start isDeterministic. Operand 130934 states and 173274 transitions. [2018-11-10 06:54:14,095 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 06:54:14,096 INFO L705 BuchiCegarLoop]: Abstraction has 130934 states and 173274 transitions. [2018-11-10 06:54:14,140 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 130934 states and 173274 transitions. [2018-11-10 06:54:14,693 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 130934 to 129854. [2018-11-10 06:54:14,693 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 129854 states. [2018-11-10 06:54:14,830 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 129854 states to 129854 states and 172194 transitions. [2018-11-10 06:54:14,830 INFO L728 BuchiCegarLoop]: Abstraction has 129854 states and 172194 transitions. [2018-11-10 06:54:14,830 INFO L608 BuchiCegarLoop]: Abstraction has 129854 states and 172194 transitions. [2018-11-10 06:54:14,830 INFO L442 BuchiCegarLoop]: ======== Iteration 27============ [2018-11-10 06:54:14,830 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 129854 states and 172194 transitions. [2018-11-10 06:54:15,377 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 121769 [2018-11-10 06:54:15,378 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 06:54:15,378 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 06:54:15,378 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:15,378 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 06:54:15,378 INFO L793 eck$LassoCheckResult]: Stem: 845725#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 845573#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 845042#L1006 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17, start_simulation_#t~ret18, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 845043#L458 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 845465#L465 assume ~m_i~0 == 1;~m_st~0 := 0; 845466#L465-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 845469#L470-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 845313#L475-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 845314#L480-1 assume ~t4_i~0 == 1;~t4_st~0 := 0; 845388#L485-1 assume ~t5_i~0 == 1;~t5_st~0 := 0; 845134#L490-1 assume ~t6_i~0 == 1;~t6_st~0 := 0; 845135#L495-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 845478#L674 assume !(~M_E~0 == 0); 845479#L674-2 assume !(~T1_E~0 == 0); 845489#L679-1 assume !(~T2_E~0 == 0); 845338#L684-1 assume !(~T3_E~0 == 0); 845339#L689-1 assume !(~T4_E~0 == 0); 845695#L694-1 assume !(~T5_E~0 == 0); 845171#L699-1 assume !(~T6_E~0 == 0); 845172#L704-1 assume !(~E_M~0 == 0); 844994#L709-1 assume !(~E_1~0 == 0); 844995#L714-1 assume !(~E_2~0 == 0); 845093#L719-1 assume !(~E_3~0 == 0); 845094#L724-1 assume !(~E_4~0 == 0); 845475#L729-1 assume !(~E_5~0 == 0); 845476#L734-1 assume !(~E_6~0 == 0); 845329#L739-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 845208#L324 assume !(~m_pc~0 == 1); 845142#L324-2 is_master_triggered_~__retres1~0 := 0; 845219#L335 is_master_triggered_#res := is_master_triggered_~__retres1~0; 845139#L336 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 845140#L839 assume !(activate_threads_~tmp~1 != 0); 845495#L839-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 845263#L343 assume !(~t1_pc~0 == 1); 845264#L343-2 is_transmit1_triggered_~__retres1~1 := 0; 845261#L354 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 845262#L355 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 845439#L847 assume !(activate_threads_~tmp___0~0 != 0); 845762#L847-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 845649#L362 assume !(~t2_pc~0 == 1); 845583#L362-2 is_transmit2_triggered_~__retres1~2 := 0; 845584#L373 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 845648#L374 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 845745#L855 assume !(activate_threads_~tmp___1~0 != 0); 845776#L855-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 845781#L381 assume !(~t3_pc~0 == 1); 845821#L381-2 is_transmit3_triggered_~__retres1~3 := 0; 845819#L392 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 845820#L393 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 845058#L863 assume !(activate_threads_~tmp___2~0 != 0); 845022#L863-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 845023#L400 assume !(~t4_pc~0 == 1); 845072#L400-2 is_transmit4_triggered_~__retres1~4 := 0; 845073#L411 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 845089#L412 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 845235#L871 assume !(activate_threads_~tmp___3~0 != 0); 845353#L871-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 845360#L419 assume !(~t5_pc~0 == 1); 845247#L419-2 is_transmit5_triggered_~__retres1~5 := 0; 845389#L430 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 845315#L431 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 845316#L879 assume !(activate_threads_~tmp___4~0 != 0); 845668#L879-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 845669#L438 assume !(~t6_pc~0 == 1); 845683#L438-2 is_transmit6_triggered_~__retres1~6 := 0; 845684#L449 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 845634#L450 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 845635#L887 assume !(activate_threads_~tmp___5~0 != 0); 845854#L887-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 845108#L752 assume !(~M_E~0 == 1); 845095#L752-2 assume !(~T1_E~0 == 1); 845096#L757-1 assume !(~T2_E~0 == 1); 845472#L762-1 assume !(~T3_E~0 == 1); 845473#L767-1 assume !(~T4_E~0 == 1); 845325#L772-1 assume !(~T5_E~0 == 1); 845326#L777-1 assume !(~T6_E~0 == 1); 845693#L782-1 assume !(~E_M~0 == 1); 845166#L787-1 assume !(~E_1~0 == 1); 845167#L792-1 assume !(~E_2~0 == 1); 845028#L797-1 assume !(~E_3~0 == 1); 845029#L802-1 assume !(~E_4~0 == 1); 845106#L807-1 assume !(~E_5~0 == 1); 845107#L812-1 assume !(~E_6~0 == 1); 845498#L817-1 assume { :end_inline_reset_delta_events } true; 845499#L1043-3 assume true; 919997#L1043-1 assume !false; 919408#L1044 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 919404#L649 [2018-11-10 06:54:15,378 INFO L795 eck$LassoCheckResult]: Loop: 919404#L649 assume true; 919402#L555-1 assume !false; 919400#L556 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 919397#L508 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~7 := 1; 919395#L545 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 919393#L546 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 919391#L560 assume eval_~tmp~0 != 0; 919388#L560-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 919385#L568 assume !(eval_~tmp_ndt_1~0 != 0); 919383#L565 assume ~t1_st~0 == 0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 919380#L582 assume !(eval_~tmp_ndt_2~0 != 0); 919205#L579 assume ~t2_st~0 == 0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 919201#L596 assume !(eval_~tmp_ndt_3~0 != 0); 919199#L593 assume ~t3_st~0 == 0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 919196#L610 assume !(eval_~tmp_ndt_4~0 != 0); 919194#L607 assume ~t4_st~0 == 0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 919192#L624 assume !(eval_~tmp_ndt_5~0 != 0); 919190#L621 assume ~t5_st~0 == 0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 919164#L638 assume !(eval_~tmp_ndt_6~0 != 0); 919188#L635 assume ~t6_st~0 == 0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 919406#L652 assume !(eval_~tmp_ndt_7~0 != 0); 919404#L649 [2018-11-10 06:54:15,379 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:15,379 INFO L82 PathProgramCache]: Analyzing trace with hash 931954781, now seen corresponding path program 7 times [2018-11-10 06:54:15,379 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:15,379 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:15,379 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:15,379 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:15,379 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:15,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:54:15,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:54:15,404 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:15,404 INFO L82 PathProgramCache]: Analyzing trace with hash -1683128087, now seen corresponding path program 1 times [2018-11-10 06:54:15,404 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:15,404 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:15,405 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:15,405 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:15,405 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:15,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:54:15,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:54:15,409 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 06:54:15,409 INFO L82 PathProgramCache]: Analyzing trace with hash 150999565, now seen corresponding path program 1 times [2018-11-10 06:54:15,409 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 06:54:15,409 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 06:54:15,410 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:15,410 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 06:54:15,410 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 06:54:15,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:54:15,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 06:54:16,062 WARN L179 SmtUtils]: Spent 509.00 ms on a formula simplification. DAG size of input: 229 DAG size of output: 152 [2018-11-10 06:54:16,195 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 10.11 06:54:16 BoogieIcfgContainer [2018-11-10 06:54:16,196 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2018-11-10 06:54:16,196 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-10 06:54:16,196 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-10 06:54:16,196 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-10 06:54:16,196 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.11 06:54:02" (3/4) ... [2018-11-10 06:54:16,202 INFO L141 WitnessPrinter]: Generating witness for non-termination counterexample [2018-11-10 06:54:16,251 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_5f1fc94c-9998-450d-a117-8df28255ba1f/bin-2019/uautomizer/witness.graphml [2018-11-10 06:54:16,251 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-10 06:54:16,251 INFO L168 Benchmark]: Toolchain (without parser) took 15353.58 ms. Allocated memory was 1.0 GB in the beginning and 2.3 GB in the end (delta: 1.2 GB). Free memory was 957.5 MB in the beginning and 1.2 GB in the end (delta: -205.8 MB). Peak memory consumption was 1.0 GB. Max. memory is 11.5 GB. [2018-11-10 06:54:16,252 INFO L168 Benchmark]: CDTParser took 0.12 ms. Allocated memory is still 1.0 GB. Free memory is still 977.4 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-10 06:54:16,252 INFO L168 Benchmark]: CACSL2BoogieTranslator took 229.74 ms. Allocated memory is still 1.0 GB. Free memory was 957.5 MB in the beginning and 936.1 MB in the end (delta: 21.5 MB). Peak memory consumption was 21.5 MB. Max. memory is 11.5 GB. [2018-11-10 06:54:16,252 INFO L168 Benchmark]: Boogie Procedure Inliner took 63.55 ms. Allocated memory is still 1.0 GB. Free memory was 936.1 MB in the beginning and 930.7 MB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2018-11-10 06:54:16,253 INFO L168 Benchmark]: Boogie Preprocessor took 118.36 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 174.1 MB). Free memory was 930.7 MB in the beginning and 1.2 GB in the end (delta: -232.2 MB). Peak memory consumption was 18.8 MB. Max. memory is 11.5 GB. [2018-11-10 06:54:16,253 INFO L168 Benchmark]: RCFGBuilder took 1184.34 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.0 GB in the end (delta: 154.9 MB). Peak memory consumption was 154.9 MB. Max. memory is 11.5 GB. [2018-11-10 06:54:16,253 INFO L168 Benchmark]: BuchiAutomizer took 13699.52 ms. Allocated memory was 1.2 GB in the beginning and 2.3 GB in the end (delta: 1.1 GB). Free memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: -155.3 MB). Peak memory consumption was 909.0 MB. Max. memory is 11.5 GB. [2018-11-10 06:54:16,253 INFO L168 Benchmark]: Witness Printer took 55.03 ms. Allocated memory is still 2.3 GB. Free memory is still 1.2 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-10 06:54:16,255 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.12 ms. Allocated memory is still 1.0 GB. Free memory is still 977.4 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 229.74 ms. Allocated memory is still 1.0 GB. Free memory was 957.5 MB in the beginning and 936.1 MB in the end (delta: 21.5 MB). Peak memory consumption was 21.5 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 63.55 ms. Allocated memory is still 1.0 GB. Free memory was 936.1 MB in the beginning and 930.7 MB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 118.36 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 174.1 MB). Free memory was 930.7 MB in the beginning and 1.2 GB in the end (delta: -232.2 MB). Peak memory consumption was 18.8 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1184.34 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.0 GB in the end (delta: 154.9 MB). Peak memory consumption was 154.9 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 13699.52 ms. Allocated memory was 1.2 GB in the beginning and 2.3 GB in the end (delta: 1.1 GB). Free memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: -155.3 MB). Peak memory consumption was 909.0 MB. Max. memory is 11.5 GB. * Witness Printer took 55.03 ms. Allocated memory is still 2.3 GB. Free memory is still 1.2 GB. There was no memory consumed. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 26 terminating modules (26 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.26 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 129854 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 13.6s and 27 iterations. TraceHistogramMax:1. Analysis of lassos took 3.5s. Construction of modules took 0.8s. Büchi inclusion checks took 1.7s. Highest rank in rank-based complementation 0. Minimization of det autom 26. Minimization of nondet autom 0. Automata minimization 3.2s AutomataMinimizationTime, 26 MinimizatonAttempts, 27597 StatesRemovedByMinimization, 13 NontrivialMinimizations. Non-live state removal took 2.3s Buchi closure took 0.2s. Biggest automaton had 129854 states and ocurred in iteration 26. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 26269 SDtfs, 26378 SDslu, 17446 SDs, 0 SdLazy, 530 SolverSat, 331 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.8s Time LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc6 concLT0 SILN1 SILU0 SILI15 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 555]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {__retres1=0, t3_st=0, token=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@c7a35f5=0, tmp=1, t5_i=1, __retres1=0, kernel_st=1, \result=0, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5b9061bd=0, t4_i=1, E_3=2, t4_pc=0, E_5=2, T6_E=2, \result=0, E_1=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4f76ed11=0, tmp_ndt_2=0, \result=0, __retres1=0, \result=0, tmp_ndt_4=0, tmp_ndt_6=0, m_st=0, t6_pc=0, tmp___2=0, tmp___0=0, t3_pc=0, tmp=0, __retres1=0, \result=0, t6_i=1, m_pc=0, tmp___4=0, \result=0, __retres1=0, t6_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@78985d02=0, E_6=2, \result=0, __retres1=0, \result=0, T2_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1144a28d=0, tmp___0=0, t1_pc=0, __retres1=1, t5_st=0, E_2=2, E_4=2, T1_E=2, tmp_ndt_1=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, T5_E=2, t2_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@73f3afb9=0, T4_E=2, t3_i=1, t4_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5a8201f2=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1ab1311d=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@35aaf3f6=0, t1_st=0, tmp_ndt_5=0, t5_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@48c939b0=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@20e2592=0, local=0, t2_pc=0, tmp_ndt_7=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1124c772=0, tmp___3=0, E_M=2, tmp___1=0, T3_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@514b4084=0, t1_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@d224c8=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1b85422a=0, \result=1, tmp___5=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@38373033=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5c0cdeec=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 555]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int t4_pc = 0; [L19] int t5_pc = 0; [L20] int t6_pc = 0; [L21] int m_st ; [L22] int t1_st ; [L23] int t2_st ; [L24] int t3_st ; [L25] int t4_st ; [L26] int t5_st ; [L27] int t6_st ; [L28] int m_i ; [L29] int t1_i ; [L30] int t2_i ; [L31] int t3_i ; [L32] int t4_i ; [L33] int t5_i ; [L34] int t6_i ; [L35] int M_E = 2; [L36] int T1_E = 2; [L37] int T2_E = 2; [L38] int T3_E = 2; [L39] int T4_E = 2; [L40] int T5_E = 2; [L41] int T6_E = 2; [L42] int E_M = 2; [L43] int E_1 = 2; [L44] int E_2 = 2; [L45] int E_3 = 2; [L46] int E_4 = 2; [L47] int E_5 = 2; [L48] int E_6 = 2; [L57] int token ; [L59] int local ; [L1088] int __retres1 ; [L1092] CALL init_model() [L998] m_i = 1 [L999] t1_i = 1 [L1000] t2_i = 1 [L1001] t3_i = 1 [L1002] t4_i = 1 [L1003] t5_i = 1 [L1004] RET t6_i = 1 [L1092] init_model() [L1093] CALL start_simulation() [L1029] int kernel_st ; [L1030] int tmp ; [L1031] int tmp___0 ; [L1035] kernel_st = 0 [L1036] FCALL update_channels() [L1037] CALL init_threads() [L465] COND TRUE m_i == 1 [L466] m_st = 0 [L470] COND TRUE t1_i == 1 [L471] t1_st = 0 [L475] COND TRUE t2_i == 1 [L476] t2_st = 0 [L480] COND TRUE t3_i == 1 [L481] t3_st = 0 [L485] COND TRUE t4_i == 1 [L486] t4_st = 0 [L490] COND TRUE t5_i == 1 [L491] t5_st = 0 [L495] COND TRUE t6_i == 1 [L496] RET t6_st = 0 [L1037] init_threads() [L1038] CALL fire_delta_events() [L674] COND FALSE !(M_E == 0) [L679] COND FALSE !(T1_E == 0) [L684] COND FALSE !(T2_E == 0) [L689] COND FALSE !(T3_E == 0) [L694] COND FALSE !(T4_E == 0) [L699] COND FALSE !(T5_E == 0) [L704] COND FALSE !(T6_E == 0) [L709] COND FALSE !(E_M == 0) [L714] COND FALSE !(E_1 == 0) [L719] COND FALSE !(E_2 == 0) [L724] COND FALSE !(E_3 == 0) [L729] COND FALSE !(E_4 == 0) [L734] COND FALSE !(E_5 == 0) [L739] COND FALSE, RET !(E_6 == 0) [L1038] fire_delta_events() [L1039] CALL activate_threads() [L827] int tmp ; [L828] int tmp___0 ; [L829] int tmp___1 ; [L830] int tmp___2 ; [L831] int tmp___3 ; [L832] int tmp___4 ; [L833] int tmp___5 ; [L837] CALL, EXPR is_master_triggered() [L321] int __retres1 ; [L324] COND FALSE !(m_pc == 1) [L334] __retres1 = 0 [L336] RET return (__retres1); [L837] EXPR is_master_triggered() [L837] tmp = is_master_triggered() [L839] COND FALSE !(\read(tmp)) [L845] CALL, EXPR is_transmit1_triggered() [L340] int __retres1 ; [L343] COND FALSE !(t1_pc == 1) [L353] __retres1 = 0 [L355] RET return (__retres1); [L845] EXPR is_transmit1_triggered() [L845] tmp___0 = is_transmit1_triggered() [L847] COND FALSE !(\read(tmp___0)) [L853] CALL, EXPR is_transmit2_triggered() [L359] int __retres1 ; [L362] COND FALSE !(t2_pc == 1) [L372] __retres1 = 0 [L374] RET return (__retres1); [L853] EXPR is_transmit2_triggered() [L853] tmp___1 = is_transmit2_triggered() [L855] COND FALSE !(\read(tmp___1)) [L861] CALL, EXPR is_transmit3_triggered() [L378] int __retres1 ; [L381] COND FALSE !(t3_pc == 1) [L391] __retres1 = 0 [L393] RET return (__retres1); [L861] EXPR is_transmit3_triggered() [L861] tmp___2 = is_transmit3_triggered() [L863] COND FALSE !(\read(tmp___2)) [L869] CALL, EXPR is_transmit4_triggered() [L397] int __retres1 ; [L400] COND FALSE !(t4_pc == 1) [L410] __retres1 = 0 [L412] RET return (__retres1); [L869] EXPR is_transmit4_triggered() [L869] tmp___3 = is_transmit4_triggered() [L871] COND FALSE !(\read(tmp___3)) [L877] CALL, EXPR is_transmit5_triggered() [L416] int __retres1 ; [L419] COND FALSE !(t5_pc == 1) [L429] __retres1 = 0 [L431] RET return (__retres1); [L877] EXPR is_transmit5_triggered() [L877] tmp___4 = is_transmit5_triggered() [L879] COND FALSE !(\read(tmp___4)) [L885] CALL, EXPR is_transmit6_triggered() [L435] int __retres1 ; [L438] COND FALSE !(t6_pc == 1) [L448] __retres1 = 0 [L450] RET return (__retres1); [L885] EXPR is_transmit6_triggered() [L885] tmp___5 = is_transmit6_triggered() [L887] COND FALSE, RET !(\read(tmp___5)) [L1039] activate_threads() [L1040] CALL reset_delta_events() [L752] COND FALSE !(M_E == 1) [L757] COND FALSE !(T1_E == 1) [L762] COND FALSE !(T2_E == 1) [L767] COND FALSE !(T3_E == 1) [L772] COND FALSE !(T4_E == 1) [L777] COND FALSE !(T5_E == 1) [L782] COND FALSE !(T6_E == 1) [L787] COND FALSE !(E_M == 1) [L792] COND FALSE !(E_1 == 1) [L797] COND FALSE !(E_2 == 1) [L802] COND FALSE !(E_3 == 1) [L807] COND FALSE !(E_4 == 1) [L812] COND FALSE !(E_5 == 1) [L817] COND FALSE, RET !(E_6 == 1) [L1040] reset_delta_events() [L1043] COND TRUE 1 [L1046] kernel_st = 1 [L1047] CALL eval() [L551] int tmp ; Loop: [L555] COND TRUE 1 [L558] CALL, EXPR exists_runnable_thread() [L505] int __retres1 ; [L508] COND TRUE m_st == 0 [L509] __retres1 = 1 [L546] RET return (__retres1); [L558] EXPR exists_runnable_thread() [L558] tmp = exists_runnable_thread() [L560] COND TRUE \read(tmp) [L565] COND TRUE m_st == 0 [L566] int tmp_ndt_1; [L567] tmp_ndt_1 = __VERIFIER_nondet_int() [L568] COND FALSE !(\read(tmp_ndt_1)) [L579] COND TRUE t1_st == 0 [L580] int tmp_ndt_2; [L581] tmp_ndt_2 = __VERIFIER_nondet_int() [L582] COND FALSE !(\read(tmp_ndt_2)) [L593] COND TRUE t2_st == 0 [L594] int tmp_ndt_3; [L595] tmp_ndt_3 = __VERIFIER_nondet_int() [L596] COND FALSE !(\read(tmp_ndt_3)) [L607] COND TRUE t3_st == 0 [L608] int tmp_ndt_4; [L609] tmp_ndt_4 = __VERIFIER_nondet_int() [L610] COND FALSE !(\read(tmp_ndt_4)) [L621] COND TRUE t4_st == 0 [L622] int tmp_ndt_5; [L623] tmp_ndt_5 = __VERIFIER_nondet_int() [L624] COND FALSE !(\read(tmp_ndt_5)) [L635] COND TRUE t5_st == 0 [L636] int tmp_ndt_6; [L637] tmp_ndt_6 = __VERIFIER_nondet_int() [L638] COND FALSE !(\read(tmp_ndt_6)) [L649] COND TRUE t6_st == 0 [L650] int tmp_ndt_7; [L651] tmp_ndt_7 = __VERIFIER_nondet_int() [L652] COND FALSE !(\read(tmp_ndt_7)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...