./Ultimate.py --spec ../../sv-benchmarks/c/Termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.03_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 1dbac8bc Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_336a3a10-29f9-4018-bc2b-dd0bc6bf9d7c/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_336a3a10-29f9-4018-bc2b-dd0bc6bf9d7c/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_336a3a10-29f9-4018-bc2b-dd0bc6bf9d7c/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_336a3a10-29f9-4018-bc2b-dd0bc6bf9d7c/bin-2019/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.03_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_336a3a10-29f9-4018-bc2b-dd0bc6bf9d7c/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_336a3a10-29f9-4018-bc2b-dd0bc6bf9d7c/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 447c919af4e106e36f468570351956f4c77293d2 .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.23-1dbac8b [2018-11-10 05:48:16,298 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-10 05:48:16,299 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-10 05:48:16,307 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-10 05:48:16,308 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-10 05:48:16,308 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-10 05:48:16,309 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-10 05:48:16,310 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-10 05:48:16,311 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-10 05:48:16,312 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-10 05:48:16,313 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-10 05:48:16,313 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-10 05:48:16,313 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-10 05:48:16,314 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-10 05:48:16,315 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-10 05:48:16,315 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-10 05:48:16,316 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-10 05:48:16,317 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-10 05:48:16,318 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-10 05:48:16,319 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-10 05:48:16,320 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-10 05:48:16,321 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-10 05:48:16,323 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-10 05:48:16,323 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-10 05:48:16,323 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-10 05:48:16,323 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-10 05:48:16,324 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-10 05:48:16,325 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-10 05:48:16,325 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-10 05:48:16,326 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-10 05:48:16,326 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-10 05:48:16,327 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-10 05:48:16,327 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-10 05:48:16,327 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-10 05:48:16,327 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-10 05:48:16,328 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-10 05:48:16,328 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_336a3a10-29f9-4018-bc2b-dd0bc6bf9d7c/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2018-11-10 05:48:16,339 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-10 05:48:16,339 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-10 05:48:16,340 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-10 05:48:16,340 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-10 05:48:16,340 INFO L133 SettingsManager]: * Use SBE=true [2018-11-10 05:48:16,340 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2018-11-10 05:48:16,340 INFO L133 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2018-11-10 05:48:16,340 INFO L133 SettingsManager]: * Use old map elimination=false [2018-11-10 05:48:16,341 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false [2018-11-10 05:48:16,341 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true [2018-11-10 05:48:16,341 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2018-11-10 05:48:16,341 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-10 05:48:16,341 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-10 05:48:16,341 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-10 05:48:16,341 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-10 05:48:16,342 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-10 05:48:16,342 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-10 05:48:16,342 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2018-11-10 05:48:16,342 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2018-11-10 05:48:16,342 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2018-11-10 05:48:16,342 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-10 05:48:16,342 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-10 05:48:16,342 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false [2018-11-10 05:48:16,342 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2018-11-10 05:48:16,343 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-10 05:48:16,343 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-10 05:48:16,343 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2018-11-10 05:48:16,343 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-10 05:48:16,343 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-10 05:48:16,343 INFO L133 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2018-11-10 05:48:16,344 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-11-10 05:48:16,344 INFO L133 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_336a3a10-29f9-4018-bc2b-dd0bc6bf9d7c/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 447c919af4e106e36f468570351956f4c77293d2 [2018-11-10 05:48:16,367 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-10 05:48:16,377 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-10 05:48:16,380 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-10 05:48:16,381 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-10 05:48:16,381 INFO L276 PluginConnector]: CDTParser initialized [2018-11-10 05:48:16,382 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_336a3a10-29f9-4018-bc2b-dd0bc6bf9d7c/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/transmitter.03_false-unreach-call_false-termination.cil.c [2018-11-10 05:48:16,425 INFO L218 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_336a3a10-29f9-4018-bc2b-dd0bc6bf9d7c/bin-2019/uautomizer/data/e339bb8f4/97d38ee6e51841118b487d59f03e8498/FLAGe2643e1f2 [2018-11-10 05:48:16,762 INFO L298 CDTParser]: Found 1 translation units. [2018-11-10 05:48:16,763 INFO L158 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_336a3a10-29f9-4018-bc2b-dd0bc6bf9d7c/sv-benchmarks/c/systemc/transmitter.03_false-unreach-call_false-termination.cil.c [2018-11-10 05:48:16,771 INFO L346 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_336a3a10-29f9-4018-bc2b-dd0bc6bf9d7c/bin-2019/uautomizer/data/e339bb8f4/97d38ee6e51841118b487d59f03e8498/FLAGe2643e1f2 [2018-11-10 05:48:16,782 INFO L354 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_336a3a10-29f9-4018-bc2b-dd0bc6bf9d7c/bin-2019/uautomizer/data/e339bb8f4/97d38ee6e51841118b487d59f03e8498 [2018-11-10 05:48:16,785 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-10 05:48:16,786 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-10 05:48:16,787 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-10 05:48:16,787 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-10 05:48:16,790 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-10 05:48:16,790 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.11 05:48:16" (1/1) ... [2018-11-10 05:48:16,793 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@60ce7209 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 05:48:16, skipping insertion in model container [2018-11-10 05:48:16,793 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.11 05:48:16" (1/1) ... [2018-11-10 05:48:16,801 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-10 05:48:16,827 INFO L174 MainTranslator]: Built tables and reachable declarations [2018-11-10 05:48:16,968 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-11-10 05:48:16,972 INFO L189 MainTranslator]: Completed pre-run [2018-11-10 05:48:17,004 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-11-10 05:48:17,018 INFO L193 MainTranslator]: Completed translation [2018-11-10 05:48:17,018 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 05:48:17 WrapperNode [2018-11-10 05:48:17,018 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-10 05:48:17,018 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-10 05:48:17,019 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-10 05:48:17,019 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-10 05:48:17,024 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 05:48:17" (1/1) ... [2018-11-10 05:48:17,029 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 05:48:17" (1/1) ... [2018-11-10 05:48:17,056 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-10 05:48:17,056 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-10 05:48:17,056 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-10 05:48:17,056 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-10 05:48:17,107 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 05:48:17" (1/1) ... [2018-11-10 05:48:17,107 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 05:48:17" (1/1) ... [2018-11-10 05:48:17,111 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 05:48:17" (1/1) ... [2018-11-10 05:48:17,111 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 05:48:17" (1/1) ... [2018-11-10 05:48:17,118 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 05:48:17" (1/1) ... [2018-11-10 05:48:17,127 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 05:48:17" (1/1) ... [2018-11-10 05:48:17,129 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 05:48:17" (1/1) ... [2018-11-10 05:48:17,132 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-10 05:48:17,132 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-10 05:48:17,132 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-10 05:48:17,132 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-10 05:48:17,133 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 05:48:17" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_336a3a10-29f9-4018-bc2b-dd0bc6bf9d7c/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-10 05:48:17,169 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-10 05:48:17,169 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-10 05:48:17,762 INFO L341 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-10 05:48:17,763 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.11 05:48:17 BoogieIcfgContainer [2018-11-10 05:48:17,763 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-10 05:48:17,763 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2018-11-10 05:48:17,763 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2018-11-10 05:48:17,766 INFO L276 PluginConnector]: BuchiAutomizer initialized [2018-11-10 05:48:17,767 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-10 05:48:17,767 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 10.11 05:48:16" (1/3) ... [2018-11-10 05:48:17,768 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@e109a03 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 10.11 05:48:17, skipping insertion in model container [2018-11-10 05:48:17,768 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-10 05:48:17,768 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 05:48:17" (2/3) ... [2018-11-10 05:48:17,769 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@e109a03 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 10.11 05:48:17, skipping insertion in model container [2018-11-10 05:48:17,769 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-10 05:48:17,769 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.11 05:48:17" (3/3) ... [2018-11-10 05:48:17,770 INFO L375 chiAutomizerObserver]: Analyzing ICFG transmitter.03_false-unreach-call_false-termination.cil.c [2018-11-10 05:48:17,800 INFO L135 ementStrategyFactory]: Using default assertion order modulation [2018-11-10 05:48:17,801 INFO L374 BuchiCegarLoop]: Interprodecural is true [2018-11-10 05:48:17,801 INFO L375 BuchiCegarLoop]: Hoare is false [2018-11-10 05:48:17,801 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2018-11-10 05:48:17,801 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-10 05:48:17,801 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-10 05:48:17,801 INFO L379 BuchiCegarLoop]: Difference is false [2018-11-10 05:48:17,801 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-10 05:48:17,801 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2018-11-10 05:48:17,817 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 298 states. [2018-11-10 05:48:17,839 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 241 [2018-11-10 05:48:17,840 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:48:17,840 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:48:17,846 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:17,846 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:17,847 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ [2018-11-10 05:48:17,847 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 298 states. [2018-11-10 05:48:17,852 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 241 [2018-11-10 05:48:17,852 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:48:17,852 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:48:17,853 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:17,853 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:17,858 INFO L793 eck$LassoCheckResult]: Stem: 99#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 9#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 128#L605true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 95#L264true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 176#L271true assume !(~m_i~0 == 1);~m_st~0 := 2; 185#L271-2true assume ~t1_i~0 == 1;~t1_st~0 := 0; 198#L276-1true assume !(~t2_i~0 == 1);~t2_st~0 := 2; 78#L281-1true assume !(~t3_i~0 == 1);~t3_st~0 := 2; 93#L286-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 209#L408true assume !(~M_E~0 == 0); 211#L408-2true assume !(~T1_E~0 == 0); 71#L413-1true assume ~T2_E~0 == 0;~T2_E~0 := 1; 116#L418-1true assume !(~T3_E~0 == 0); 150#L423-1true assume !(~E_1~0 == 0); 26#L428-1true assume !(~E_2~0 == 0); 33#L433-1true assume !(~E_3~0 == 0); 231#L438-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 89#L187true assume !(~m_pc~0 == 1); 109#L187-2true is_master_triggered_~__retres1~0 := 0; 90#L198true is_master_triggered_#res := is_master_triggered_~__retres1~0; 195#L199true activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 140#L500true assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 145#L500-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 275#L206true assume ~t1_pc~0 == 1; 35#L207true assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 276#L217true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 36#L218true activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 171#L508true assume !(activate_threads_~tmp___0~0 != 0); 175#L508-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 146#L225true assume !(~t2_pc~0 == 1); 141#L225-2true is_transmit2_triggered_~__retres1~2 := 0; 147#L236true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 74#L237true activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 21#L516true assume !(activate_threads_~tmp___1~0 != 0); 23#L516-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 291#L244true assume ~t3_pc~0 == 1; 254#L245true assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 165#L255true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 255#L256true activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 196#L524true assume !(activate_threads_~tmp___2~0 != 0); 199#L524-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 111#L451true assume !(~M_E~0 == 1); 117#L451-2true assume !(~T1_E~0 == 1); 148#L456-1true assume !(~T2_E~0 == 1); 24#L461-1true assume ~T3_E~0 == 1;~T3_E~0 := 2; 32#L466-1true assume !(~E_1~0 == 1); 226#L471-1true assume !(~E_2~0 == 1); 258#L476-1true assume !(~E_3~0 == 1); 288#L481-1true assume { :end_inline_reset_delta_events } true; 39#L642-3true [2018-11-10 05:48:17,860 INFO L795 eck$LassoCheckResult]: Loop: 39#L642-3true assume true; 37#L642-1true assume !false; 4#L643true start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 233#L383true assume !true; 154#L398true assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 91#L264-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 214#L408-3true assume ~M_E~0 == 0;~M_E~0 := 1; 200#L408-5true assume !(~T1_E~0 == 0); 81#L413-3true assume ~T2_E~0 == 0;~T2_E~0 := 1; 123#L418-3true assume ~T3_E~0 == 0;~T3_E~0 := 1; 136#L423-3true assume ~E_1~0 == 0;~E_1~0 := 1; 10#L428-3true assume ~E_2~0 == 0;~E_2~0 := 1; 31#L433-3true assume ~E_3~0 == 0;~E_3~0 := 1; 44#L438-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 58#L187-12true assume ~m_pc~0 == 1; 204#L188-4true assume ~M_E~0 == 1;is_master_triggered_~__retres1~0 := 1; 104#L198-4true is_master_triggered_#res := is_master_triggered_~__retres1~0; 205#L199-4true activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 126#L500-12true assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 130#L500-14true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 257#L206-12true assume !(~t1_pc~0 == 1); 256#L206-14true is_transmit1_triggered_~__retres1~1 := 0; 266#L217-4true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 47#L218-4true activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 297#L508-12true assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 279#L508-14true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 125#L225-12true assume !(~t2_pc~0 == 1); 96#L225-14true is_transmit2_triggered_~__retres1~2 := 0; 118#L236-4true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 217#L237-4true activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 5#L516-12true assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 6#L516-14true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 263#L244-12true assume !(~t3_pc~0 == 1); 261#L244-14true is_transmit3_triggered_~__retres1~3 := 0; 281#L255-4true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 224#L256-4true activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 181#L524-12true assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 167#L524-14true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 119#L451-3true assume ~M_E~0 == 1;~M_E~0 := 2; 98#L451-5true assume ~T1_E~0 == 1;~T1_E~0 := 2; 151#L456-3true assume ~T2_E~0 == 1;~T2_E~0 := 2; 28#L461-3true assume ~T3_E~0 == 1;~T3_E~0 := 2; 34#L466-3true assume ~E_1~0 == 1;~E_1~0 := 2; 41#L471-3true assume !(~E_2~0 == 1); 238#L476-3true assume ~E_3~0 == 1;~E_3~0 := 2; 267#L481-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 166#L299-1true assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 161#L321-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 245#L322-1true start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 62#L661true assume !(start_simulation_~tmp~3 == 0); 218#L661-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 290#L299-2true assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 164#L321-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 248#L322-2true stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 127#L616true assume !(stop_simulation_~tmp~2 != 0);stop_simulation_~__retres2~0 := 1; 208#L623true stop_simulation_#res := stop_simulation_~__retres2~0; 298#L624true start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 262#L674true assume !(start_simulation_~tmp___0~1 != 0); 39#L642-3true [2018-11-10 05:48:17,864 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:17,865 INFO L82 PathProgramCache]: Analyzing trace with hash -1773697160, now seen corresponding path program 1 times [2018-11-10 05:48:17,866 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:17,867 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:17,897 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:17,897 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:48:17,897 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:17,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:48:17,959 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:48:17,961 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:48:17,961 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 05:48:17,964 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 05:48:17,964 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:17,964 INFO L82 PathProgramCache]: Analyzing trace with hash 812904875, now seen corresponding path program 1 times [2018-11-10 05:48:17,965 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:17,965 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:17,965 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:17,966 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:48:17,966 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:17,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:48:17,978 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:48:17,979 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:48:17,979 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 05:48:17,980 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 05:48:17,990 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 05:48:17,990 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 05:48:17,992 INFO L87 Difference]: Start difference. First operand 298 states. Second operand 3 states. [2018-11-10 05:48:18,022 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:48:18,023 INFO L93 Difference]: Finished difference Result 297 states and 437 transitions. [2018-11-10 05:48:18,023 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 05:48:18,025 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 297 states and 437 transitions. [2018-11-10 05:48:18,029 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 238 [2018-11-10 05:48:18,036 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 297 states to 291 states and 431 transitions. [2018-11-10 05:48:18,037 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 291 [2018-11-10 05:48:18,038 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 291 [2018-11-10 05:48:18,038 INFO L73 IsDeterministic]: Start isDeterministic. Operand 291 states and 431 transitions. [2018-11-10 05:48:18,040 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 05:48:18,040 INFO L705 BuchiCegarLoop]: Abstraction has 291 states and 431 transitions. [2018-11-10 05:48:18,051 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 291 states and 431 transitions. [2018-11-10 05:48:18,066 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 291 to 291. [2018-11-10 05:48:18,067 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 291 states. [2018-11-10 05:48:18,068 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 291 states to 291 states and 431 transitions. [2018-11-10 05:48:18,069 INFO L728 BuchiCegarLoop]: Abstraction has 291 states and 431 transitions. [2018-11-10 05:48:18,069 INFO L608 BuchiCegarLoop]: Abstraction has 291 states and 431 transitions. [2018-11-10 05:48:18,069 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ [2018-11-10 05:48:18,069 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 291 states and 431 transitions. [2018-11-10 05:48:18,071 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 238 [2018-11-10 05:48:18,072 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:48:18,072 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:48:18,073 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:18,073 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:18,074 INFO L793 eck$LassoCheckResult]: Stem: 780#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 615#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 616#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 772#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 773#L271 assume ~m_i~0 == 1;~m_st~0 := 0; 847#L271-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 855#L276-1 assume !(~t2_i~0 == 1);~t2_st~0 := 2; 740#L281-1 assume !(~t3_i~0 == 1);~t3_st~0 := 2; 741#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 771#L408 assume !(~M_E~0 == 0); 863#L408-2 assume !(~T1_E~0 == 0); 729#L413-1 assume ~T2_E~0 == 0;~T2_E~0 := 1; 730#L418-1 assume !(~T3_E~0 == 0); 794#L423-1 assume !(~E_1~0 == 0); 649#L428-1 assume !(~E_2~0 == 0); 650#L433-1 assume !(~E_3~0 == 0); 657#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 760#L187 assume !(~m_pc~0 == 1); 761#L187-2 is_master_triggered_~__retres1~0 := 0; 763#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 764#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 815#L500 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 816#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 818#L206 assume ~t1_pc~0 == 1; 659#L207 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 660#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 662#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 663#L508 assume !(activate_threads_~tmp___0~0 != 0); 843#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 819#L225 assume !(~t2_pc~0 == 1); 733#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 732#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 736#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 642#L516 assume !(activate_threads_~tmp___1~0 != 0); 643#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 644#L244 assume ~t3_pc~0 == 1; 888#L245 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 834#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 835#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 858#L524 assume !(activate_threads_~tmp___2~0 != 0); 859#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 790#L451 assume !(~M_E~0 == 1); 791#L451-2 assume !(~T1_E~0 == 1); 795#L456-1 assume !(~T2_E~0 == 1); 645#L461-1 assume ~T3_E~0 == 1;~T3_E~0 := 2; 646#L466-1 assume !(~E_1~0 == 1); 656#L471-1 assume !(~E_2~0 == 1); 878#L476-1 assume !(~E_3~0 == 1); 890#L481-1 assume { :end_inline_reset_delta_events } true; 666#L642-3 [2018-11-10 05:48:18,074 INFO L795 eck$LassoCheckResult]: Loop: 666#L642-3 assume true; 664#L642-1 assume !false; 606#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 607#L383 assume true; 864#L331-1 assume !false; 824#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 825#L299 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 622#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 826#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 742#L336 assume !(eval_~tmp~0 != 0); 744#L398 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 765#L264-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 766#L408-3 assume ~M_E~0 == 0;~M_E~0 := 1; 861#L408-5 assume !(~T1_E~0 == 0); 746#L413-3 assume ~T2_E~0 == 0;~T2_E~0 := 1; 747#L418-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 799#L423-3 assume ~E_1~0 == 0;~E_1~0 := 1; 617#L428-3 assume ~E_2~0 == 0;~E_2~0 := 1; 618#L433-3 assume ~E_3~0 == 0;~E_3~0 := 1; 655#L438-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 678#L187-12 assume !(~m_pc~0 == 1); 704#L187-14 is_master_triggered_~__retres1~0 := 0; 739#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 784#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 806#L500-12 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 807#L500-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 808#L206-12 assume ~t1_pc~0 == 1; 679#L207-4 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 681#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 682#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 683#L508-12 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 892#L508-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 802#L225-12 assume ~t2_pc~0 == 1; 803#L226-4 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 775#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 796#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 608#L516-12 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 609#L516-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 610#L244-12 assume ~t3_pc~0 == 1; 870#L245-4 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 871#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 873#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 850#L524-12 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 837#L524-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 797#L451-3 assume ~M_E~0 == 1;~M_E~0 := 2; 776#L451-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 777#L456-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 651#L461-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 652#L466-3 assume ~E_1~0 == 1;~E_1~0 := 2; 658#L471-3 assume !(~E_2~0 == 1); 667#L476-3 assume ~E_3~0 == 1;~E_3~0 := 2; 886#L481-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 836#L299-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 630#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 831#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 711#L661 assume !(start_simulation_~tmp~3 == 0); 665#L661-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 865#L299-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 637#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 833#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 804#L616 assume !(stop_simulation_~tmp~2 != 0);stop_simulation_~__retres2~0 := 1; 805#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 862#L624 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 891#L674 assume !(start_simulation_~tmp___0~1 != 0); 666#L642-3 [2018-11-10 05:48:18,074 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:18,074 INFO L82 PathProgramCache]: Analyzing trace with hash 1627783798, now seen corresponding path program 1 times [2018-11-10 05:48:18,074 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:18,075 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:18,075 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:18,075 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:48:18,075 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:18,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:48:18,109 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:48:18,109 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:48:18,109 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 05:48:18,110 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 05:48:18,110 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:18,110 INFO L82 PathProgramCache]: Analyzing trace with hash 1082341580, now seen corresponding path program 1 times [2018-11-10 05:48:18,110 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:18,110 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:18,111 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:18,111 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:48:18,111 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:18,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:48:18,168 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:48:18,168 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:48:18,168 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 05:48:18,168 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 05:48:18,168 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 05:48:18,169 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 05:48:18,169 INFO L87 Difference]: Start difference. First operand 291 states and 431 transitions. cyclomatic complexity: 141 Second operand 3 states. [2018-11-10 05:48:18,186 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:48:18,186 INFO L93 Difference]: Finished difference Result 291 states and 430 transitions. [2018-11-10 05:48:18,187 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 05:48:18,187 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 291 states and 430 transitions. [2018-11-10 05:48:18,189 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 238 [2018-11-10 05:48:18,191 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 291 states to 291 states and 430 transitions. [2018-11-10 05:48:18,191 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 291 [2018-11-10 05:48:18,192 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 291 [2018-11-10 05:48:18,192 INFO L73 IsDeterministic]: Start isDeterministic. Operand 291 states and 430 transitions. [2018-11-10 05:48:18,193 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 05:48:18,193 INFO L705 BuchiCegarLoop]: Abstraction has 291 states and 430 transitions. [2018-11-10 05:48:18,194 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 291 states and 430 transitions. [2018-11-10 05:48:18,201 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 291 to 291. [2018-11-10 05:48:18,201 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 291 states. [2018-11-10 05:48:18,202 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 291 states to 291 states and 430 transitions. [2018-11-10 05:48:18,202 INFO L728 BuchiCegarLoop]: Abstraction has 291 states and 430 transitions. [2018-11-10 05:48:18,202 INFO L608 BuchiCegarLoop]: Abstraction has 291 states and 430 transitions. [2018-11-10 05:48:18,202 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ [2018-11-10 05:48:18,202 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 291 states and 430 transitions. [2018-11-10 05:48:18,204 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 238 [2018-11-10 05:48:18,204 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:48:18,204 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:48:18,206 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:18,206 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:18,206 INFO L793 eck$LassoCheckResult]: Stem: 1369#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 1204#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1205#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 1361#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1362#L271 assume ~m_i~0 == 1;~m_st~0 := 0; 1436#L271-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 1444#L276-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 1329#L281-1 assume !(~t3_i~0 == 1);~t3_st~0 := 2; 1330#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1360#L408 assume !(~M_E~0 == 0); 1452#L408-2 assume !(~T1_E~0 == 0); 1318#L413-1 assume ~T2_E~0 == 0;~T2_E~0 := 1; 1319#L418-1 assume !(~T3_E~0 == 0); 1383#L423-1 assume !(~E_1~0 == 0); 1238#L428-1 assume !(~E_2~0 == 0); 1239#L433-1 assume !(~E_3~0 == 0); 1246#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1349#L187 assume !(~m_pc~0 == 1); 1350#L187-2 is_master_triggered_~__retres1~0 := 0; 1352#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1353#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 1404#L500 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 1405#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1407#L206 assume ~t1_pc~0 == 1; 1248#L207 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 1249#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1251#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1252#L508 assume !(activate_threads_~tmp___0~0 != 0); 1432#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1408#L225 assume !(~t2_pc~0 == 1); 1322#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 1321#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1326#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1231#L516 assume !(activate_threads_~tmp___1~0 != 0); 1232#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1233#L244 assume ~t3_pc~0 == 1; 1477#L245 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 1423#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1424#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1447#L524 assume !(activate_threads_~tmp___2~0 != 0); 1448#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1379#L451 assume !(~M_E~0 == 1); 1380#L451-2 assume !(~T1_E~0 == 1); 1384#L456-1 assume !(~T2_E~0 == 1); 1234#L461-1 assume ~T3_E~0 == 1;~T3_E~0 := 2; 1235#L466-1 assume !(~E_1~0 == 1); 1245#L471-1 assume !(~E_2~0 == 1); 1467#L476-1 assume !(~E_3~0 == 1); 1479#L481-1 assume { :end_inline_reset_delta_events } true; 1255#L642-3 [2018-11-10 05:48:18,206 INFO L795 eck$LassoCheckResult]: Loop: 1255#L642-3 assume true; 1253#L642-1 assume !false; 1195#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 1196#L383 assume true; 1453#L331-1 assume !false; 1413#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1414#L299 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 1211#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1415#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1331#L336 assume !(eval_~tmp~0 != 0); 1333#L398 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 1354#L264-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 1355#L408-3 assume ~M_E~0 == 0;~M_E~0 := 1; 1450#L408-5 assume !(~T1_E~0 == 0); 1335#L413-3 assume ~T2_E~0 == 0;~T2_E~0 := 1; 1336#L418-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 1388#L423-3 assume ~E_1~0 == 0;~E_1~0 := 1; 1206#L428-3 assume ~E_2~0 == 0;~E_2~0 := 1; 1207#L433-3 assume ~E_3~0 == 0;~E_3~0 := 1; 1244#L438-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1265#L187-12 assume ~m_pc~0 == 1; 1291#L188-4 assume ~M_E~0 == 1;is_master_triggered_~__retres1~0 := 1; 1324#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1373#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 1393#L500-12 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 1394#L500-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1397#L206-12 assume ~t1_pc~0 == 1; 1268#L207-4 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 1270#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1271#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1272#L508-12 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 1481#L508-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1391#L225-12 assume ~t2_pc~0 == 1; 1392#L226-4 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 1364#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1385#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1197#L516-12 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 1198#L516-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1199#L244-12 assume ~t3_pc~0 == 1; 1459#L245-4 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 1460#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1462#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1439#L524-12 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 1426#L524-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1386#L451-3 assume ~M_E~0 == 1;~M_E~0 := 2; 1365#L451-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 1366#L456-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 1240#L461-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 1241#L466-3 assume ~E_1~0 == 1;~E_1~0 := 2; 1247#L471-3 assume !(~E_2~0 == 1); 1256#L476-3 assume ~E_3~0 == 1;~E_3~0 := 2; 1475#L481-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1425#L299-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 1219#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1420#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 1300#L661 assume !(start_simulation_~tmp~3 == 0); 1254#L661-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1454#L299-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 1226#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1422#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 1395#L616 assume !(stop_simulation_~tmp~2 != 0);stop_simulation_~__retres2~0 := 1; 1396#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 1451#L624 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 1480#L674 assume !(start_simulation_~tmp___0~1 != 0); 1255#L642-3 [2018-11-10 05:48:18,207 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:18,207 INFO L82 PathProgramCache]: Analyzing trace with hash -1769790220, now seen corresponding path program 1 times [2018-11-10 05:48:18,207 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:18,207 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:18,208 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:18,208 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:48:18,208 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:18,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:48:18,239 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:48:18,239 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:48:18,239 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 05:48:18,239 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 05:48:18,239 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:18,239 INFO L82 PathProgramCache]: Analyzing trace with hash -1937523027, now seen corresponding path program 1 times [2018-11-10 05:48:18,239 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:18,240 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:18,240 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:18,240 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:48:18,240 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:18,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:48:18,274 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:48:18,274 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:48:18,274 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 05:48:18,274 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 05:48:18,274 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 05:48:18,274 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 05:48:18,275 INFO L87 Difference]: Start difference. First operand 291 states and 430 transitions. cyclomatic complexity: 140 Second operand 3 states. [2018-11-10 05:48:18,283 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:48:18,283 INFO L93 Difference]: Finished difference Result 291 states and 429 transitions. [2018-11-10 05:48:18,283 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 05:48:18,283 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 291 states and 429 transitions. [2018-11-10 05:48:18,285 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 238 [2018-11-10 05:48:18,287 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 291 states to 291 states and 429 transitions. [2018-11-10 05:48:18,287 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 291 [2018-11-10 05:48:18,287 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 291 [2018-11-10 05:48:18,287 INFO L73 IsDeterministic]: Start isDeterministic. Operand 291 states and 429 transitions. [2018-11-10 05:48:18,288 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 05:48:18,289 INFO L705 BuchiCegarLoop]: Abstraction has 291 states and 429 transitions. [2018-11-10 05:48:18,289 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 291 states and 429 transitions. [2018-11-10 05:48:18,295 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 291 to 291. [2018-11-10 05:48:18,295 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 291 states. [2018-11-10 05:48:18,296 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 291 states to 291 states and 429 transitions. [2018-11-10 05:48:18,296 INFO L728 BuchiCegarLoop]: Abstraction has 291 states and 429 transitions. [2018-11-10 05:48:18,297 INFO L608 BuchiCegarLoop]: Abstraction has 291 states and 429 transitions. [2018-11-10 05:48:18,297 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ [2018-11-10 05:48:18,297 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 291 states and 429 transitions. [2018-11-10 05:48:18,298 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 238 [2018-11-10 05:48:18,298 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:48:18,299 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:48:18,300 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:18,300 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:18,300 INFO L793 eck$LassoCheckResult]: Stem: 1958#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 1793#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1794#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 1950#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1951#L271 assume ~m_i~0 == 1;~m_st~0 := 0; 2025#L271-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 2033#L276-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 1918#L281-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 1919#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1949#L408 assume !(~M_E~0 == 0); 2041#L408-2 assume !(~T1_E~0 == 0); 1907#L413-1 assume ~T2_E~0 == 0;~T2_E~0 := 1; 1908#L418-1 assume !(~T3_E~0 == 0); 1973#L423-1 assume !(~E_1~0 == 0); 1827#L428-1 assume !(~E_2~0 == 0); 1828#L433-1 assume !(~E_3~0 == 0); 1835#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1938#L187 assume !(~m_pc~0 == 1); 1939#L187-2 is_master_triggered_~__retres1~0 := 0; 1941#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1942#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 1993#L500 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 1994#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1996#L206 assume ~t1_pc~0 == 1; 1837#L207 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 1838#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1840#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1841#L508 assume !(activate_threads_~tmp___0~0 != 0); 2021#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1997#L225 assume !(~t2_pc~0 == 1); 1912#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 1911#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1917#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1820#L516 assume !(activate_threads_~tmp___1~0 != 0); 1821#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1822#L244 assume ~t3_pc~0 == 1; 2066#L245 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 2012#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2013#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2036#L524 assume !(activate_threads_~tmp___2~0 != 0); 2037#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1966#L451 assume !(~M_E~0 == 1); 1967#L451-2 assume !(~T1_E~0 == 1); 1972#L456-1 assume !(~T2_E~0 == 1); 1823#L461-1 assume ~T3_E~0 == 1;~T3_E~0 := 2; 1824#L466-1 assume !(~E_1~0 == 1); 1834#L471-1 assume !(~E_2~0 == 1); 2055#L476-1 assume !(~E_3~0 == 1); 2068#L481-1 assume { :end_inline_reset_delta_events } true; 1844#L642-3 [2018-11-10 05:48:18,300 INFO L795 eck$LassoCheckResult]: Loop: 1844#L642-3 assume true; 1842#L642-1 assume !false; 1784#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 1785#L383 assume true; 2042#L331-1 assume !false; 2002#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2003#L299 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 1800#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2004#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1920#L336 assume !(eval_~tmp~0 != 0); 1922#L398 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 1943#L264-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 1944#L408-3 assume ~M_E~0 == 0;~M_E~0 := 1; 2039#L408-5 assume !(~T1_E~0 == 0); 1924#L413-3 assume ~T2_E~0 == 0;~T2_E~0 := 1; 1925#L418-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 1977#L423-3 assume ~E_1~0 == 0;~E_1~0 := 1; 1795#L428-3 assume ~E_2~0 == 0;~E_2~0 := 1; 1796#L433-3 assume ~E_3~0 == 0;~E_3~0 := 1; 1833#L438-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1856#L187-12 assume ~m_pc~0 == 1; 1881#L188-4 assume ~M_E~0 == 1;is_master_triggered_~__retres1~0 := 1; 1915#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1962#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 1982#L500-12 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 1983#L500-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1986#L206-12 assume ~t1_pc~0 == 1; 1857#L207-4 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 1859#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1860#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1861#L508-12 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 2070#L508-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1980#L225-12 assume !(~t2_pc~0 == 1); 1952#L225-14 is_transmit2_triggered_~__retres1~2 := 0; 1953#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1974#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1786#L516-12 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 1787#L516-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1788#L244-12 assume ~t3_pc~0 == 1; 2048#L245-4 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 2049#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2051#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2028#L524-12 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 2015#L524-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1975#L451-3 assume ~M_E~0 == 1;~M_E~0 := 2; 1956#L451-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 1957#L456-3 assume ~T2_E~0 == 1;~T2_E~0 := 2; 1829#L461-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 1830#L466-3 assume ~E_1~0 == 1;~E_1~0 := 2; 1836#L471-3 assume !(~E_2~0 == 1); 1848#L476-3 assume ~E_3~0 == 1;~E_3~0 := 2; 2064#L481-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2014#L299-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 1808#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2009#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 1889#L661 assume !(start_simulation_~tmp~3 == 0); 1843#L661-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2043#L299-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 1815#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2011#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 1984#L616 assume !(stop_simulation_~tmp~2 != 0);stop_simulation_~__retres2~0 := 1; 1985#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 2040#L624 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 2069#L674 assume !(start_simulation_~tmp___0~1 != 0); 1844#L642-3 [2018-11-10 05:48:18,301 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:18,301 INFO L82 PathProgramCache]: Analyzing trace with hash -2017936714, now seen corresponding path program 1 times [2018-11-10 05:48:18,301 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:18,301 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:18,302 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:18,302 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:48:18,302 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:18,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:48:18,325 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:48:18,325 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:48:18,326 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 05:48:18,326 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 05:48:18,326 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:18,326 INFO L82 PathProgramCache]: Analyzing trace with hash -1018548404, now seen corresponding path program 1 times [2018-11-10 05:48:18,326 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:18,326 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:18,327 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:18,327 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:48:18,327 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:18,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:48:18,364 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:48:18,364 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:48:18,364 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 05:48:18,364 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 05:48:18,365 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 05:48:18,365 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 05:48:18,365 INFO L87 Difference]: Start difference. First operand 291 states and 429 transitions. cyclomatic complexity: 139 Second operand 3 states. [2018-11-10 05:48:18,397 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:48:18,397 INFO L93 Difference]: Finished difference Result 291 states and 424 transitions. [2018-11-10 05:48:18,397 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 05:48:18,397 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 291 states and 424 transitions. [2018-11-10 05:48:18,399 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 238 [2018-11-10 05:48:18,400 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 291 states to 291 states and 424 transitions. [2018-11-10 05:48:18,400 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 291 [2018-11-10 05:48:18,400 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 291 [2018-11-10 05:48:18,400 INFO L73 IsDeterministic]: Start isDeterministic. Operand 291 states and 424 transitions. [2018-11-10 05:48:18,401 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 05:48:18,401 INFO L705 BuchiCegarLoop]: Abstraction has 291 states and 424 transitions. [2018-11-10 05:48:18,401 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 291 states and 424 transitions. [2018-11-10 05:48:18,406 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 291 to 291. [2018-11-10 05:48:18,406 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 291 states. [2018-11-10 05:48:18,407 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 291 states to 291 states and 424 transitions. [2018-11-10 05:48:18,408 INFO L728 BuchiCegarLoop]: Abstraction has 291 states and 424 transitions. [2018-11-10 05:48:18,408 INFO L608 BuchiCegarLoop]: Abstraction has 291 states and 424 transitions. [2018-11-10 05:48:18,408 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ [2018-11-10 05:48:18,408 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 291 states and 424 transitions. [2018-11-10 05:48:18,409 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 238 [2018-11-10 05:48:18,410 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:48:18,410 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:48:18,411 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:18,411 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:18,411 INFO L793 eck$LassoCheckResult]: Stem: 2547#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 2382#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2383#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 2539#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2540#L271 assume ~m_i~0 == 1;~m_st~0 := 0; 2613#L271-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 2621#L276-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 2507#L281-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 2508#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2536#L408 assume !(~M_E~0 == 0); 2630#L408-2 assume !(~T1_E~0 == 0); 2496#L413-1 assume !(~T2_E~0 == 0); 2497#L418-1 assume !(~T3_E~0 == 0); 2561#L423-1 assume !(~E_1~0 == 0); 2416#L428-1 assume !(~E_2~0 == 0); 2417#L433-1 assume !(~E_3~0 == 0); 2424#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2527#L187 assume !(~m_pc~0 == 1); 2528#L187-2 is_master_triggered_~__retres1~0 := 0; 2530#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2531#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 2582#L500 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 2583#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2585#L206 assume ~t1_pc~0 == 1; 2426#L207 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 2427#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2429#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2430#L508 assume !(activate_threads_~tmp___0~0 != 0); 2609#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2586#L225 assume !(~t2_pc~0 == 1); 2500#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 2499#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2502#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2409#L516 assume !(activate_threads_~tmp___1~0 != 0); 2410#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2411#L244 assume ~t3_pc~0 == 1; 2655#L245 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 2601#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2602#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2625#L524 assume !(activate_threads_~tmp___2~0 != 0); 2626#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2555#L451 assume !(~M_E~0 == 1); 2556#L451-2 assume !(~T1_E~0 == 1); 2562#L456-1 assume !(~T2_E~0 == 1); 2412#L461-1 assume ~T3_E~0 == 1;~T3_E~0 := 2; 2413#L466-1 assume !(~E_1~0 == 1); 2423#L471-1 assume !(~E_2~0 == 1); 2644#L476-1 assume !(~E_3~0 == 1); 2657#L481-1 assume { :end_inline_reset_delta_events } true; 2433#L642-3 [2018-11-10 05:48:18,411 INFO L795 eck$LassoCheckResult]: Loop: 2433#L642-3 assume true; 2431#L642-1 assume !false; 2373#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 2374#L383 assume true; 2631#L331-1 assume !false; 2591#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2592#L299 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 2389#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2593#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 2509#L336 assume !(eval_~tmp~0 != 0); 2511#L398 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 2532#L264-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 2533#L408-3 assume ~M_E~0 == 0;~M_E~0 := 1; 2628#L408-5 assume !(~T1_E~0 == 0); 2513#L413-3 assume !(~T2_E~0 == 0); 2514#L418-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 2566#L423-3 assume ~E_1~0 == 0;~E_1~0 := 1; 2384#L428-3 assume ~E_2~0 == 0;~E_2~0 := 1; 2385#L433-3 assume ~E_3~0 == 0;~E_3~0 := 1; 2422#L438-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2445#L187-12 assume ~m_pc~0 == 1; 2470#L188-4 assume ~M_E~0 == 1;is_master_triggered_~__retres1~0 := 1; 2505#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2551#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 2571#L500-12 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 2572#L500-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2575#L206-12 assume ~t1_pc~0 == 1; 2446#L207-4 assume ~E_1~0 == 1;is_transmit1_triggered_~__retres1~1 := 1; 2448#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2449#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2450#L508-12 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 2659#L508-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2569#L225-12 assume ~t2_pc~0 == 1; 2570#L226-4 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 2542#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2563#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2375#L516-12 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 2376#L516-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2377#L244-12 assume ~t3_pc~0 == 1; 2637#L245-4 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 2638#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2640#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2617#L524-12 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 2604#L524-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2564#L451-3 assume ~M_E~0 == 1;~M_E~0 := 2; 2545#L451-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 2546#L456-3 assume !(~T2_E~0 == 1); 2418#L461-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 2419#L466-3 assume ~E_1~0 == 1;~E_1~0 := 2; 2425#L471-3 assume !(~E_2~0 == 1); 2437#L476-3 assume ~E_3~0 == 1;~E_3~0 := 2; 2653#L481-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2603#L299-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 2397#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2598#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 2478#L661 assume !(start_simulation_~tmp~3 == 0); 2432#L661-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2632#L299-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 2404#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2600#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 2573#L616 assume !(stop_simulation_~tmp~2 != 0);stop_simulation_~__retres2~0 := 1; 2574#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 2629#L624 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 2658#L674 assume !(start_simulation_~tmp___0~1 != 0); 2433#L642-3 [2018-11-10 05:48:18,415 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:18,415 INFO L82 PathProgramCache]: Analyzing trace with hash 1247671284, now seen corresponding path program 1 times [2018-11-10 05:48:18,416 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:18,416 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:18,417 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:18,418 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:48:18,418 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:18,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:48:18,459 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:48:18,460 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:48:18,460 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 05:48:18,460 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 05:48:18,460 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:18,461 INFO L82 PathProgramCache]: Analyzing trace with hash -117780695, now seen corresponding path program 1 times [2018-11-10 05:48:18,461 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:18,461 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:18,462 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:18,462 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:48:18,462 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:18,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:48:18,509 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:48:18,510 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:48:18,510 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 05:48:18,510 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 05:48:18,510 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 05:48:18,510 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 05:48:18,511 INFO L87 Difference]: Start difference. First operand 291 states and 424 transitions. cyclomatic complexity: 134 Second operand 3 states. [2018-11-10 05:48:18,559 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:48:18,559 INFO L93 Difference]: Finished difference Result 493 states and 711 transitions. [2018-11-10 05:48:18,559 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 05:48:18,560 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 493 states and 711 transitions. [2018-11-10 05:48:18,562 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 439 [2018-11-10 05:48:18,563 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 493 states to 493 states and 711 transitions. [2018-11-10 05:48:18,564 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 493 [2018-11-10 05:48:18,564 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 493 [2018-11-10 05:48:18,564 INFO L73 IsDeterministic]: Start isDeterministic. Operand 493 states and 711 transitions. [2018-11-10 05:48:18,565 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 05:48:18,565 INFO L705 BuchiCegarLoop]: Abstraction has 493 states and 711 transitions. [2018-11-10 05:48:18,565 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 493 states and 711 transitions. [2018-11-10 05:48:18,570 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 493 to 490. [2018-11-10 05:48:18,570 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 490 states. [2018-11-10 05:48:18,571 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 490 states to 490 states and 708 transitions. [2018-11-10 05:48:18,571 INFO L728 BuchiCegarLoop]: Abstraction has 490 states and 708 transitions. [2018-11-10 05:48:18,571 INFO L608 BuchiCegarLoop]: Abstraction has 490 states and 708 transitions. [2018-11-10 05:48:18,571 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ [2018-11-10 05:48:18,571 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 490 states and 708 transitions. [2018-11-10 05:48:18,573 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 436 [2018-11-10 05:48:18,573 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:48:18,573 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:48:18,574 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:18,574 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:18,574 INFO L793 eck$LassoCheckResult]: Stem: 3338#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 3173#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 3174#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 3330#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3331#L271 assume ~m_i~0 == 1;~m_st~0 := 0; 3406#L271-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 3414#L276-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 3298#L281-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 3299#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3329#L408 assume !(~M_E~0 == 0); 3423#L408-2 assume !(~T1_E~0 == 0); 3285#L413-1 assume !(~T2_E~0 == 0); 3286#L418-1 assume !(~T3_E~0 == 0); 3353#L423-1 assume !(~E_1~0 == 0); 3206#L428-1 assume !(~E_2~0 == 0); 3207#L433-1 assume !(~E_3~0 == 0); 3214#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3318#L187 assume !(~m_pc~0 == 1); 3319#L187-2 is_master_triggered_~__retres1~0 := 0; 3321#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3322#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 3374#L500 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 3375#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3377#L206 assume !(~t1_pc~0 == 1); 3461#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 3462#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3216#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 3217#L508 assume !(activate_threads_~tmp___0~0 != 0); 3402#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3378#L225 assume !(~t2_pc~0 == 1); 3289#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 3288#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3293#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 3199#L516 assume !(activate_threads_~tmp___1~0 != 0); 3200#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3201#L244 assume ~t3_pc~0 == 1; 3455#L245 assume ~E_3~0 == 1;is_transmit3_triggered_~__retres1~3 := 1; 3394#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3395#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3418#L524 assume !(activate_threads_~tmp___2~0 != 0); 3419#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3349#L451 assume !(~M_E~0 == 1); 3350#L451-2 assume !(~T1_E~0 == 1); 3354#L456-1 assume !(~T2_E~0 == 1); 3202#L461-1 assume ~T3_E~0 == 1;~T3_E~0 := 2; 3203#L466-1 assume !(~E_1~0 == 1); 3213#L471-1 assume !(~E_2~0 == 1); 3439#L476-1 assume !(~E_3~0 == 1); 3458#L481-1 assume { :end_inline_reset_delta_events } true; 3220#L642-3 [2018-11-10 05:48:18,574 INFO L795 eck$LassoCheckResult]: Loop: 3220#L642-3 assume true; 3218#L642-1 assume !false; 3164#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 3165#L383 assume true; 3424#L331-1 assume !false; 3384#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 3385#L299 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 3180#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 3386#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 3300#L336 assume !(eval_~tmp~0 != 0); 3302#L398 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 3651#L264-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 3650#L408-3 assume ~M_E~0 == 0;~M_E~0 := 1; 3649#L408-5 assume !(~T1_E~0 == 0); 3648#L413-3 assume !(~T2_E~0 == 0); 3647#L418-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 3646#L423-3 assume ~E_1~0 == 0;~E_1~0 := 1; 3645#L428-3 assume ~E_2~0 == 0;~E_2~0 := 1; 3644#L433-3 assume ~E_3~0 == 0;~E_3~0 := 1; 3232#L438-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3233#L187-12 assume ~m_pc~0 == 1; 3259#L188-4 assume ~M_E~0 == 1;is_master_triggered_~__retres1~0 := 1; 3297#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3342#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 3365#L500-12 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 3366#L500-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3367#L206-12 assume !(~t1_pc~0 == 1); 3457#L206-14 is_transmit1_triggered_~__retres1~1 := 0; 3643#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3642#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 3640#L508-12 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 3638#L508-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3636#L225-12 assume ~t2_pc~0 == 1; 3633#L226-4 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 3630#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3628#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 3626#L516-12 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 3624#L516-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3622#L244-12 assume !(~t3_pc~0 == 1); 3619#L244-14 is_transmit3_triggered_~__retres1~3 := 0; 3616#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3614#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3612#L524-12 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 3610#L524-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3608#L451-3 assume ~M_E~0 == 1;~M_E~0 := 2; 3606#L451-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 3604#L456-3 assume !(~T2_E~0 == 1); 3602#L461-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 3600#L466-3 assume ~E_1~0 == 1;~E_1~0 := 2; 3598#L471-3 assume !(~E_2~0 == 1); 3596#L476-3 assume ~E_3~0 == 1;~E_3~0 := 2; 3594#L481-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 3592#L299-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 3588#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 3587#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 3267#L661 assume !(start_simulation_~tmp~3 == 0); 3219#L661-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 3425#L299-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 3194#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 3393#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 3363#L616 assume !(stop_simulation_~tmp~2 != 0);stop_simulation_~__retres2~0 := 1; 3364#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 3422#L624 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 3460#L674 assume !(start_simulation_~tmp___0~1 != 0); 3220#L642-3 [2018-11-10 05:48:18,574 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:18,575 INFO L82 PathProgramCache]: Analyzing trace with hash 1886455763, now seen corresponding path program 1 times [2018-11-10 05:48:18,575 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:18,575 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:18,576 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:18,576 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:48:18,576 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:18,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:48:18,608 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:48:18,608 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:48:18,608 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 05:48:18,608 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 05:48:18,608 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:18,609 INFO L82 PathProgramCache]: Analyzing trace with hash 1044324455, now seen corresponding path program 1 times [2018-11-10 05:48:18,609 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:18,609 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:18,610 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:18,610 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:48:18,610 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:18,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:48:18,636 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:48:18,636 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:48:18,636 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 05:48:18,636 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 05:48:18,637 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 05:48:18,637 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 05:48:18,637 INFO L87 Difference]: Start difference. First operand 490 states and 708 transitions. cyclomatic complexity: 220 Second operand 3 states. [2018-11-10 05:48:18,679 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:48:18,680 INFO L93 Difference]: Finished difference Result 916 states and 1309 transitions. [2018-11-10 05:48:18,680 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 05:48:18,680 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 916 states and 1309 transitions. [2018-11-10 05:48:18,683 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 857 [2018-11-10 05:48:18,686 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 916 states to 916 states and 1309 transitions. [2018-11-10 05:48:18,686 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 916 [2018-11-10 05:48:18,687 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 916 [2018-11-10 05:48:18,687 INFO L73 IsDeterministic]: Start isDeterministic. Operand 916 states and 1309 transitions. [2018-11-10 05:48:18,688 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 05:48:18,688 INFO L705 BuchiCegarLoop]: Abstraction has 916 states and 1309 transitions. [2018-11-10 05:48:18,689 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 916 states and 1309 transitions. [2018-11-10 05:48:18,697 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 916 to 906. [2018-11-10 05:48:18,698 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 906 states. [2018-11-10 05:48:18,699 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 906 states to 906 states and 1297 transitions. [2018-11-10 05:48:18,699 INFO L728 BuchiCegarLoop]: Abstraction has 906 states and 1297 transitions. [2018-11-10 05:48:18,700 INFO L608 BuchiCegarLoop]: Abstraction has 906 states and 1297 transitions. [2018-11-10 05:48:18,700 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ [2018-11-10 05:48:18,700 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 906 states and 1297 transitions. [2018-11-10 05:48:18,702 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 851 [2018-11-10 05:48:18,702 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:48:18,702 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:48:18,703 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:18,703 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:18,704 INFO L793 eck$LassoCheckResult]: Stem: 4752#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 4586#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 4587#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 4744#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4745#L271 assume ~m_i~0 == 1;~m_st~0 := 0; 4829#L271-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 4839#L276-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 4711#L281-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 4712#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4743#L408 assume !(~M_E~0 == 0); 4851#L408-2 assume !(~T1_E~0 == 0); 4699#L413-1 assume !(~T2_E~0 == 0); 4700#L418-1 assume !(~T3_E~0 == 0); 4770#L423-1 assume !(~E_1~0 == 0); 4620#L428-1 assume !(~E_2~0 == 0); 4621#L433-1 assume !(~E_3~0 == 0); 4629#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4731#L187 assume !(~m_pc~0 == 1); 4732#L187-2 is_master_triggered_~__retres1~0 := 0; 4734#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4735#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 4794#L500 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 4795#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4798#L206 assume !(~t1_pc~0 == 1); 4891#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 4892#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4631#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 4632#L508 assume !(activate_threads_~tmp___0~0 != 0); 4824#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4799#L225 assume !(~t2_pc~0 == 1); 4703#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 4702#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4707#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 4612#L516 assume !(activate_threads_~tmp___1~0 != 0); 4613#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4615#L244 assume !(~t3_pc~0 == 1); 4901#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 4815#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4816#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 4845#L524 assume !(activate_threads_~tmp___2~0 != 0); 4846#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4765#L451 assume !(~M_E~0 == 1); 4766#L451-2 assume !(~T1_E~0 == 1); 4771#L456-1 assume !(~T2_E~0 == 1); 4616#L461-1 assume ~T3_E~0 == 1;~T3_E~0 := 2; 4617#L466-1 assume !(~E_1~0 == 1); 4628#L471-1 assume !(~E_2~0 == 1); 4870#L476-1 assume !(~E_3~0 == 1); 4883#L481-1 assume { :end_inline_reset_delta_events } true; 4902#L642-3 [2018-11-10 05:48:18,704 INFO L795 eck$LassoCheckResult]: Loop: 4902#L642-3 assume true; 5210#L642-1 assume !false; 5204#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 5201#L383 assume true; 5198#L331-1 assume !false; 5179#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 5172#L299 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 5169#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 5165#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 5161#L336 assume !(eval_~tmp~0 != 0); 5162#L398 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 5478#L264-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 5477#L408-3 assume ~M_E~0 == 0;~M_E~0 := 1; 5476#L408-5 assume !(~T1_E~0 == 0); 5475#L413-3 assume !(~T2_E~0 == 0); 5474#L418-3 assume ~T3_E~0 == 0;~T3_E~0 := 1; 5473#L423-3 assume ~E_1~0 == 0;~E_1~0 := 1; 5472#L428-3 assume ~E_2~0 == 0;~E_2~0 := 1; 4626#L433-3 assume ~E_3~0 == 0;~E_3~0 := 1; 4627#L438-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5447#L187-12 assume ~m_pc~0 == 1; 5445#L188-4 assume ~M_E~0 == 1;is_master_triggered_~__retres1~0 := 1; 5444#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5443#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 5442#L500-12 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 5440#L500-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5438#L206-12 assume !(~t1_pc~0 == 1); 5436#L206-14 is_transmit1_triggered_~__retres1~1 := 0; 5434#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5432#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 5430#L508-12 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 4897#L508-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4778#L225-12 assume !(~t2_pc~0 == 1); 4746#L225-14 is_transmit2_triggered_~__retres1~2 := 0; 4747#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4772#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 4579#L516-12 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 4580#L516-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4581#L244-12 assume !(~t3_pc~0 == 1); 4885#L244-14 is_transmit3_triggered_~__retres1~3 := 0; 4886#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4898#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 5295#L524-12 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 5292#L524-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5289#L451-3 assume ~M_E~0 == 1;~M_E~0 := 2; 5286#L451-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 5283#L456-3 assume !(~T2_E~0 == 1); 5280#L461-3 assume ~T3_E~0 == 1;~T3_E~0 := 2; 5277#L466-3 assume ~E_1~0 == 1;~E_1~0 := 2; 5274#L471-3 assume !(~E_2~0 == 1); 5270#L476-3 assume ~E_3~0 == 1;~E_3~0 := 2; 5267#L481-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 5264#L299-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 5258#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 5255#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 5252#L661 assume !(start_simulation_~tmp~3 == 0); 5248#L661-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 5244#L299-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 5239#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 5235#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 5232#L616 assume !(stop_simulation_~tmp~2 != 0);stop_simulation_~__retres2~0 := 1; 5227#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 5223#L624 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 5219#L674 assume !(start_simulation_~tmp___0~1 != 0); 4902#L642-3 [2018-11-10 05:48:18,704 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:18,704 INFO L82 PathProgramCache]: Analyzing trace with hash 882094642, now seen corresponding path program 1 times [2018-11-10 05:48:18,705 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:18,705 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:18,705 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:18,705 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:48:18,706 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:18,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:48:18,731 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:48:18,731 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:48:18,731 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 05:48:18,731 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 05:48:18,731 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:18,732 INFO L82 PathProgramCache]: Analyzing trace with hash 1963299078, now seen corresponding path program 1 times [2018-11-10 05:48:18,732 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:18,732 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:18,732 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:18,733 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:48:18,733 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:18,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:48:18,751 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:48:18,752 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:48:18,752 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 05:48:18,752 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 05:48:18,752 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 05:48:18,752 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 05:48:18,753 INFO L87 Difference]: Start difference. First operand 906 states and 1297 transitions. cyclomatic complexity: 395 Second operand 3 states. [2018-11-10 05:48:18,776 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:48:18,776 INFO L93 Difference]: Finished difference Result 906 states and 1283 transitions. [2018-11-10 05:48:18,777 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 05:48:18,777 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 906 states and 1283 transitions. [2018-11-10 05:48:18,780 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 851 [2018-11-10 05:48:18,782 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 906 states to 906 states and 1283 transitions. [2018-11-10 05:48:18,782 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 906 [2018-11-10 05:48:18,783 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 906 [2018-11-10 05:48:18,783 INFO L73 IsDeterministic]: Start isDeterministic. Operand 906 states and 1283 transitions. [2018-11-10 05:48:18,784 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 05:48:18,784 INFO L705 BuchiCegarLoop]: Abstraction has 906 states and 1283 transitions. [2018-11-10 05:48:18,785 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 906 states and 1283 transitions. [2018-11-10 05:48:18,792 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 906 to 906. [2018-11-10 05:48:18,792 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 906 states. [2018-11-10 05:48:18,794 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 906 states to 906 states and 1283 transitions. [2018-11-10 05:48:18,794 INFO L728 BuchiCegarLoop]: Abstraction has 906 states and 1283 transitions. [2018-11-10 05:48:18,794 INFO L608 BuchiCegarLoop]: Abstraction has 906 states and 1283 transitions. [2018-11-10 05:48:18,794 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ [2018-11-10 05:48:18,794 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 906 states and 1283 transitions. [2018-11-10 05:48:18,796 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 851 [2018-11-10 05:48:18,796 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:48:18,796 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:48:18,797 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:18,797 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:18,797 INFO L793 eck$LassoCheckResult]: Stem: 6571#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 6405#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 6406#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 6562#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6563#L271 assume ~m_i~0 == 1;~m_st~0 := 0; 6649#L271-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 6657#L276-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 6530#L281-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 6531#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6561#L408 assume !(~M_E~0 == 0); 6674#L408-2 assume !(~T1_E~0 == 0); 6517#L413-1 assume !(~T2_E~0 == 0); 6518#L418-1 assume !(~T3_E~0 == 0); 6590#L423-1 assume !(~E_1~0 == 0); 6438#L428-1 assume !(~E_2~0 == 0); 6439#L433-1 assume !(~E_3~0 == 0); 6446#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6550#L187 assume !(~m_pc~0 == 1); 6551#L187-2 is_master_triggered_~__retres1~0 := 0; 6553#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6554#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 6613#L500 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 6614#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6616#L206 assume !(~t1_pc~0 == 1); 6717#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 6718#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6448#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 6449#L508 assume !(activate_threads_~tmp___0~0 != 0); 6644#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6617#L225 assume !(~t2_pc~0 == 1); 6521#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 6520#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6525#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 6431#L516 assume !(activate_threads_~tmp___1~0 != 0); 6432#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6433#L244 assume !(~t3_pc~0 == 1); 6725#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 6635#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6636#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 6666#L524 assume !(activate_threads_~tmp___2~0 != 0); 6667#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6586#L451 assume !(~M_E~0 == 1); 6587#L451-2 assume !(~T1_E~0 == 1); 6591#L456-1 assume !(~T2_E~0 == 1); 6434#L461-1 assume !(~T3_E~0 == 1); 6435#L466-1 assume !(~E_1~0 == 1); 6445#L471-1 assume !(~E_2~0 == 1); 6689#L476-1 assume !(~E_3~0 == 1); 6708#L481-1 assume { :end_inline_reset_delta_events } true; 6727#L642-3 [2018-11-10 05:48:18,798 INFO L795 eck$LassoCheckResult]: Loop: 6727#L642-3 assume true; 6924#L642-1 assume !false; 6861#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 6859#L383 assume true; 6857#L331-1 assume !false; 6855#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 6851#L299 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 6847#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 6845#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 6842#L336 assume !(eval_~tmp~0 != 0); 6843#L398 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 7033#L264-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 7031#L408-3 assume ~M_E~0 == 0;~M_E~0 := 1; 7029#L408-5 assume !(~T1_E~0 == 0); 7027#L413-3 assume !(~T2_E~0 == 0); 7026#L418-3 assume !(~T3_E~0 == 0); 7025#L423-3 assume ~E_1~0 == 0;~E_1~0 := 1; 7024#L428-3 assume ~E_2~0 == 0;~E_2~0 := 1; 7023#L433-3 assume ~E_3~0 == 0;~E_3~0 := 1; 7022#L438-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7021#L187-12 assume ~m_pc~0 == 1; 7019#L188-4 assume ~M_E~0 == 1;is_master_triggered_~__retres1~0 := 1; 7018#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7017#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 7015#L500-12 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 7012#L500-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7010#L206-12 assume !(~t1_pc~0 == 1); 7008#L206-14 is_transmit1_triggered_~__retres1~1 := 0; 7006#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7004#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 7002#L508-12 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 7000#L508-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6998#L225-12 assume ~t2_pc~0 == 1; 6995#L226-4 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 6993#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6991#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 6989#L516-12 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 6986#L516-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6984#L244-12 assume !(~t3_pc~0 == 1); 6982#L244-14 is_transmit3_triggered_~__retres1~3 := 0; 6980#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6978#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 6976#L524-12 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 6974#L524-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6972#L451-3 assume ~M_E~0 == 1;~M_E~0 := 2; 6970#L451-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 6968#L456-3 assume !(~T2_E~0 == 1); 6966#L461-3 assume !(~T3_E~0 == 1); 6964#L466-3 assume ~E_1~0 == 1;~E_1~0 := 2; 6962#L471-3 assume !(~E_2~0 == 1); 6960#L476-3 assume ~E_3~0 == 1;~E_3~0 := 2; 6958#L481-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 6956#L299-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 6951#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 6949#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 6947#L661 assume !(start_simulation_~tmp~3 == 0); 6942#L661-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 6938#L299-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 6934#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 6933#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 6929#L616 assume !(stop_simulation_~tmp~2 != 0);stop_simulation_~__retres2~0 := 1; 6927#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 6926#L624 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 6925#L674 assume !(start_simulation_~tmp___0~1 != 0); 6727#L642-3 [2018-11-10 05:48:18,798 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:18,798 INFO L82 PathProgramCache]: Analyzing trace with hash 883941684, now seen corresponding path program 1 times [2018-11-10 05:48:18,798 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:18,798 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:18,799 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:18,799 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:48:18,799 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:18,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:48:18,860 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:48:18,860 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:48:18,861 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 05:48:18,861 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 05:48:18,861 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:18,861 INFO L82 PathProgramCache]: Analyzing trace with hash -559542165, now seen corresponding path program 1 times [2018-11-10 05:48:18,861 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:18,861 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:18,862 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:18,862 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:48:18,862 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:18,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:48:18,900 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:48:18,901 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:48:18,901 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 05:48:18,901 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 05:48:18,901 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 05:48:18,901 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 05:48:18,902 INFO L87 Difference]: Start difference. First operand 906 states and 1283 transitions. cyclomatic complexity: 381 Second operand 5 states. [2018-11-10 05:48:19,076 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:48:19,076 INFO L93 Difference]: Finished difference Result 2513 states and 3518 transitions. [2018-11-10 05:48:19,078 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-10 05:48:19,078 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2513 states and 3518 transitions. [2018-11-10 05:48:19,091 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2391 [2018-11-10 05:48:19,102 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2513 states to 2513 states and 3518 transitions. [2018-11-10 05:48:19,102 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2513 [2018-11-10 05:48:19,104 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2513 [2018-11-10 05:48:19,104 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2513 states and 3518 transitions. [2018-11-10 05:48:19,109 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 05:48:19,109 INFO L705 BuchiCegarLoop]: Abstraction has 2513 states and 3518 transitions. [2018-11-10 05:48:19,111 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2513 states and 3518 transitions. [2018-11-10 05:48:19,143 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2513 to 963. [2018-11-10 05:48:19,143 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 963 states. [2018-11-10 05:48:19,145 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 963 states to 963 states and 1340 transitions. [2018-11-10 05:48:19,145 INFO L728 BuchiCegarLoop]: Abstraction has 963 states and 1340 transitions. [2018-11-10 05:48:19,145 INFO L608 BuchiCegarLoop]: Abstraction has 963 states and 1340 transitions. [2018-11-10 05:48:19,145 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ [2018-11-10 05:48:19,145 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 963 states and 1340 transitions. [2018-11-10 05:48:19,149 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 905 [2018-11-10 05:48:19,149 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:48:19,149 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:48:19,150 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:19,150 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:19,150 INFO L793 eck$LassoCheckResult]: Stem: 10006#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 9837#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 9838#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 9997#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9998#L271 assume ~m_i~0 == 1;~m_st~0 := 0; 10085#L271-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 10095#L276-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 9964#L281-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 9965#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9996#L408 assume !(~M_E~0 == 0); 10119#L408-2 assume !(~T1_E~0 == 0); 9951#L413-1 assume !(~T2_E~0 == 0); 9952#L418-1 assume !(~T3_E~0 == 0); 10027#L423-1 assume !(~E_1~0 == 0); 9871#L428-1 assume !(~E_2~0 == 0); 9872#L433-1 assume !(~E_3~0 == 0); 9880#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9985#L187 assume !(~m_pc~0 == 1); 9986#L187-2 is_master_triggered_~__retres1~0 := 0; 9988#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9989#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 10050#L500 assume !(activate_threads_~tmp~1 != 0); 10051#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10053#L206 assume !(~t1_pc~0 == 1); 10159#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 10160#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9882#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 9883#L508 assume !(activate_threads_~tmp___0~0 != 0); 10080#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10054#L225 assume !(~t2_pc~0 == 1); 9956#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 9955#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9960#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 9863#L516 assume !(activate_threads_~tmp___1~0 != 0); 9864#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9866#L244 assume !(~t3_pc~0 == 1); 10167#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 10071#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10072#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 10105#L524 assume !(activate_threads_~tmp___2~0 != 0); 10106#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10023#L451 assume !(~M_E~0 == 1); 10024#L451-2 assume !(~T1_E~0 == 1); 10028#L456-1 assume !(~T2_E~0 == 1); 9867#L461-1 assume !(~T3_E~0 == 1); 9868#L466-1 assume !(~E_1~0 == 1); 9879#L471-1 assume !(~E_2~0 == 1); 10137#L476-1 assume !(~E_3~0 == 1); 10153#L481-1 assume { :end_inline_reset_delta_events } true; 9886#L642-3 [2018-11-10 05:48:19,151 INFO L795 eck$LassoCheckResult]: Loop: 9886#L642-3 assume true; 9884#L642-1 assume !false; 9828#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 9829#L383 assume true; 10120#L331-1 assume !false; 10061#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 10062#L299 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 9844#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 10063#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 9966#L336 assume !(eval_~tmp~0 != 0); 9968#L398 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 10788#L264-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 10787#L408-3 assume ~M_E~0 == 0;~M_E~0 := 1; 10785#L408-5 assume !(~T1_E~0 == 0); 10783#L413-3 assume !(~T2_E~0 == 0); 10781#L418-3 assume !(~T3_E~0 == 0); 10779#L423-3 assume ~E_1~0 == 0;~E_1~0 := 1; 10771#L428-3 assume ~E_2~0 == 0;~E_2~0 := 1; 9877#L433-3 assume ~E_3~0 == 0;~E_3~0 := 1; 9878#L438-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9896#L187-12 assume ~m_pc~0 == 1; 10112#L188-4 assume ~M_E~0 == 1;is_master_triggered_~__retres1~0 := 1; 10113#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10114#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 10115#L500-12 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 10039#L500-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10042#L206-12 assume !(~t1_pc~0 == 1); 10151#L206-14 is_transmit1_triggered_~__retres1~1 := 0; 10152#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9902#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 9903#L508-12 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 10164#L508-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10036#L225-12 assume ~t2_pc~0 == 1; 10037#L226-4 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 10000#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10029#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 9830#L516-12 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 9831#L516-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9832#L244-12 assume !(~t3_pc~0 == 1); 10156#L244-14 is_transmit3_triggered_~__retres1~3 := 0; 10776#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10775#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 10774#L524-12 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 10773#L524-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10772#L451-3 assume ~M_E~0 == 1;~M_E~0 := 2; 10004#L451-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 10005#L456-3 assume !(~T2_E~0 == 1); 10769#L461-3 assume !(~T3_E~0 == 1); 10735#L466-3 assume ~E_1~0 == 1;~E_1~0 := 2; 10682#L471-3 assume !(~E_2~0 == 1); 10681#L476-3 assume ~E_3~0 == 1;~E_3~0 := 2; 10680#L481-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 10073#L299-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 9852#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 10068#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 9933#L661 assume !(start_simulation_~tmp~3 == 0); 9885#L661-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 10121#L299-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 9858#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 10070#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 10040#L616 assume !(stop_simulation_~tmp~2 != 0);stop_simulation_~__retres2~0 := 1; 10041#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 10118#L624 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 10155#L674 assume !(start_simulation_~tmp___0~1 != 0); 9886#L642-3 [2018-11-10 05:48:19,151 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:19,151 INFO L82 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 1 times [2018-11-10 05:48:19,151 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:19,152 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:19,152 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:19,152 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:48:19,152 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:19,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:48:19,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:48:19,179 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:19,179 INFO L82 PathProgramCache]: Analyzing trace with hash -559542165, now seen corresponding path program 2 times [2018-11-10 05:48:19,179 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:19,179 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:19,180 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:19,181 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:48:19,181 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:19,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:48:19,196 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:48:19,196 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:48:19,197 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 05:48:19,197 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 05:48:19,197 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 05:48:19,197 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 05:48:19,197 INFO L87 Difference]: Start difference. First operand 963 states and 1340 transitions. cyclomatic complexity: 381 Second operand 3 states. [2018-11-10 05:48:19,238 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:48:19,238 INFO L93 Difference]: Finished difference Result 1664 states and 2286 transitions. [2018-11-10 05:48:19,239 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 05:48:19,239 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1664 states and 2286 transitions. [2018-11-10 05:48:19,245 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1565 [2018-11-10 05:48:19,251 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1664 states to 1664 states and 2286 transitions. [2018-11-10 05:48:19,251 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1664 [2018-11-10 05:48:19,253 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1664 [2018-11-10 05:48:19,253 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1664 states and 2286 transitions. [2018-11-10 05:48:19,255 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 05:48:19,255 INFO L705 BuchiCegarLoop]: Abstraction has 1664 states and 2286 transitions. [2018-11-10 05:48:19,256 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1664 states and 2286 transitions. [2018-11-10 05:48:19,274 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1664 to 1662. [2018-11-10 05:48:19,274 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1662 states. [2018-11-10 05:48:19,277 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1662 states to 1662 states and 2284 transitions. [2018-11-10 05:48:19,277 INFO L728 BuchiCegarLoop]: Abstraction has 1662 states and 2284 transitions. [2018-11-10 05:48:19,277 INFO L608 BuchiCegarLoop]: Abstraction has 1662 states and 2284 transitions. [2018-11-10 05:48:19,277 INFO L442 BuchiCegarLoop]: ======== Iteration 10============ [2018-11-10 05:48:19,278 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1662 states and 2284 transitions. [2018-11-10 05:48:19,283 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1563 [2018-11-10 05:48:19,283 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:48:19,283 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:48:19,284 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:19,284 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:19,284 INFO L793 eck$LassoCheckResult]: Stem: 12633#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 12470#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 12471#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 12625#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12626#L271 assume ~m_i~0 == 1;~m_st~0 := 0; 12721#L271-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 12732#L276-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 12593#L281-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 12594#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12624#L408 assume !(~M_E~0 == 0); 12752#L408-2 assume !(~T1_E~0 == 0); 12581#L413-1 assume !(~T2_E~0 == 0); 12582#L418-1 assume !(~T3_E~0 == 0); 12654#L423-1 assume !(~E_1~0 == 0); 12504#L428-1 assume ~E_2~0 == 0;~E_2~0 := 1; 12505#L433-1 assume !(~E_3~0 == 0); 12773#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12774#L187 assume !(~m_pc~0 == 1); 12642#L187-2 is_master_triggered_~__retres1~0 := 0; 12616#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12617#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 12681#L500 assume !(activate_threads_~tmp~1 != 0); 12682#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12799#L206 assume !(~t1_pc~0 == 1); 12800#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 12801#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12802#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 12714#L508 assume !(activate_threads_~tmp___0~0 != 0); 12715#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12857#L225 assume !(~t2_pc~0 == 1); 12856#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 12584#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12587#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 12496#L516 assume !(activate_threads_~tmp___1~0 != 0); 12497#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12499#L244 assume !(~t3_pc~0 == 1); 12809#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 12706#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12707#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 12744#L524 assume !(activate_threads_~tmp___2~0 != 0); 12745#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12646#L451 assume !(~M_E~0 == 1); 12647#L451-2 assume !(~T1_E~0 == 1); 12655#L456-1 assume !(~T2_E~0 == 1); 12500#L461-1 assume !(~T3_E~0 == 1); 12501#L466-1 assume !(~E_1~0 == 1); 12512#L471-1 assume ~E_2~0 == 1;~E_2~0 := 2; 12767#L476-1 assume !(~E_3~0 == 1); 12789#L481-1 assume { :end_inline_reset_delta_events } true; 12810#L642-3 [2018-11-10 05:48:19,284 INFO L795 eck$LassoCheckResult]: Loop: 12810#L642-3 assume true; 13686#L642-1 assume !false; 12461#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 12462#L383 assume true; 13614#L331-1 assume !false; 13612#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 13608#L299 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 13607#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 13606#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 13603#L336 assume !(eval_~tmp~0 != 0); 13604#L398 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 14012#L264-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 14009#L408-3 assume ~M_E~0 == 0;~M_E~0 := 1; 14007#L408-5 assume !(~T1_E~0 == 0); 14005#L413-3 assume !(~T2_E~0 == 0); 14003#L418-3 assume !(~T3_E~0 == 0); 14001#L423-3 assume ~E_1~0 == 0;~E_1~0 := 1; 13981#L428-3 assume ~E_2~0 == 0;~E_2~0 := 1; 13979#L433-3 assume ~E_3~0 == 0;~E_3~0 := 1; 13977#L438-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13975#L187-12 assume !(~m_pc~0 == 1); 13971#L187-14 is_master_triggered_~__retres1~0 := 0; 13969#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13967#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 13965#L500-12 assume !(activate_threads_~tmp~1 != 0); 13962#L500-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13960#L206-12 assume !(~t1_pc~0 == 1); 13958#L206-14 is_transmit1_triggered_~__retres1~1 := 0; 13957#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13956#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 13955#L508-12 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 13953#L508-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13952#L225-12 assume ~t2_pc~0 == 1; 13950#L226-4 assume ~E_2~0 == 1;is_transmit2_triggered_~__retres1~2 := 1; 13949#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13947#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 13945#L516-12 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 13944#L516-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13940#L244-12 assume !(~t3_pc~0 == 1); 13938#L244-14 is_transmit3_triggered_~__retres1~3 := 0; 13936#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 13934#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 13931#L524-12 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 13929#L524-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13927#L451-3 assume ~M_E~0 == 1;~M_E~0 := 2; 13924#L451-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 13922#L456-3 assume !(~T2_E~0 == 1); 13920#L461-3 assume !(~T3_E~0 == 1); 13918#L466-3 assume ~E_1~0 == 1;~E_1~0 := 2; 13916#L471-3 assume ~E_2~0 == 1;~E_2~0 := 2; 12780#L476-3 assume ~E_3~0 == 1;~E_3~0 := 2; 12781#L481-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 12978#L299-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 12973#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 12971#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 12968#L661 assume !(start_simulation_~tmp~3 == 0); 12969#L661-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 13703#L299-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 13699#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 13697#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 13694#L616 assume !(stop_simulation_~tmp~2 != 0);stop_simulation_~__retres2~0 := 1; 13693#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 13691#L624 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 13689#L674 assume !(start_simulation_~tmp___0~1 != 0); 12810#L642-3 [2018-11-10 05:48:19,284 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:19,284 INFO L82 PathProgramCache]: Analyzing trace with hash 1218472174, now seen corresponding path program 1 times [2018-11-10 05:48:19,284 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:19,285 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:19,285 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:19,285 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 05:48:19,285 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:19,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:48:19,303 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:48:19,303 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:48:19,303 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 05:48:19,304 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 05:48:19,304 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:19,304 INFO L82 PathProgramCache]: Analyzing trace with hash -1926588474, now seen corresponding path program 1 times [2018-11-10 05:48:19,304 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:19,304 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:19,305 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:19,305 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:48:19,305 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:19,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:48:19,327 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:48:19,327 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:48:19,327 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 05:48:19,327 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 05:48:19,327 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 05:48:19,327 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 05:48:19,328 INFO L87 Difference]: Start difference. First operand 1662 states and 2284 transitions. cyclomatic complexity: 626 Second operand 3 states. [2018-11-10 05:48:19,385 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:48:19,385 INFO L93 Difference]: Finished difference Result 963 states and 1307 transitions. [2018-11-10 05:48:19,386 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 05:48:19,386 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 963 states and 1307 transitions. [2018-11-10 05:48:19,390 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 905 [2018-11-10 05:48:19,393 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 963 states to 963 states and 1307 transitions. [2018-11-10 05:48:19,393 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 963 [2018-11-10 05:48:19,394 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 963 [2018-11-10 05:48:19,394 INFO L73 IsDeterministic]: Start isDeterministic. Operand 963 states and 1307 transitions. [2018-11-10 05:48:19,395 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 05:48:19,395 INFO L705 BuchiCegarLoop]: Abstraction has 963 states and 1307 transitions. [2018-11-10 05:48:19,396 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 963 states and 1307 transitions. [2018-11-10 05:48:19,404 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 963 to 963. [2018-11-10 05:48:19,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 963 states. [2018-11-10 05:48:19,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 963 states to 963 states and 1307 transitions. [2018-11-10 05:48:19,406 INFO L728 BuchiCegarLoop]: Abstraction has 963 states and 1307 transitions. [2018-11-10 05:48:19,406 INFO L608 BuchiCegarLoop]: Abstraction has 963 states and 1307 transitions. [2018-11-10 05:48:19,406 INFO L442 BuchiCegarLoop]: ======== Iteration 11============ [2018-11-10 05:48:19,407 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 963 states and 1307 transitions. [2018-11-10 05:48:19,409 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 905 [2018-11-10 05:48:19,409 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:48:19,409 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:48:19,410 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:19,410 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:19,410 INFO L793 eck$LassoCheckResult]: Stem: 15264#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 15104#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 15105#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 15255#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15256#L271 assume ~m_i~0 == 1;~m_st~0 := 0; 15350#L271-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 15360#L276-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 15223#L281-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 15224#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15254#L408 assume !(~M_E~0 == 0); 15378#L408-2 assume !(~T1_E~0 == 0); 15212#L413-1 assume !(~T2_E~0 == 0); 15213#L418-1 assume !(~T3_E~0 == 0); 15288#L423-1 assume !(~E_1~0 == 0); 15138#L428-1 assume !(~E_2~0 == 0); 15139#L433-1 assume !(~E_3~0 == 0); 15146#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15243#L187 assume !(~m_pc~0 == 1); 15244#L187-2 is_master_triggered_~__retres1~0 := 0; 15246#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15247#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 15313#L500 assume !(activate_threads_~tmp~1 != 0); 15314#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15317#L206 assume !(~t1_pc~0 == 1); 15424#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 15425#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15148#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 15149#L508 assume !(activate_threads_~tmp___0~0 != 0); 15346#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15318#L225 assume !(~t2_pc~0 == 1); 15216#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 15315#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15222#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 15130#L516 assume !(activate_threads_~tmp___1~0 != 0); 15131#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15133#L244 assume !(~t3_pc~0 == 1); 15428#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 15337#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15338#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 15368#L524 assume !(activate_threads_~tmp___2~0 != 0); 15369#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15281#L451 assume !(~M_E~0 == 1); 15282#L451-2 assume !(~T1_E~0 == 1); 15289#L456-1 assume !(~T2_E~0 == 1); 15134#L461-1 assume !(~T3_E~0 == 1); 15135#L466-1 assume !(~E_1~0 == 1); 15145#L471-1 assume !(~E_2~0 == 1); 15396#L476-1 assume !(~E_3~0 == 1); 15415#L481-1 assume { :end_inline_reset_delta_events } true; 15429#L642-3 [2018-11-10 05:48:19,411 INFO L795 eck$LassoCheckResult]: Loop: 15429#L642-3 assume true; 15601#L642-1 assume !false; 15593#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 15591#L383 assume true; 15583#L331-1 assume !false; 15578#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 15539#L299 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 15535#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 15533#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 15530#L336 assume !(eval_~tmp~0 != 0); 15531#L398 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 15790#L264-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 15788#L408-3 assume ~M_E~0 == 0;~M_E~0 := 1; 15786#L408-5 assume !(~T1_E~0 == 0); 15784#L413-3 assume !(~T2_E~0 == 0); 15782#L418-3 assume !(~T3_E~0 == 0); 15780#L423-3 assume ~E_1~0 == 0;~E_1~0 := 1; 15778#L428-3 assume !(~E_2~0 == 0); 15776#L433-3 assume ~E_3~0 == 0;~E_3~0 := 1; 15775#L438-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15774#L187-12 assume !(~m_pc~0 == 1); 15772#L187-14 is_master_triggered_~__retres1~0 := 0; 15770#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15768#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 15767#L500-12 assume !(activate_threads_~tmp~1 != 0); 15765#L500-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15763#L206-12 assume !(~t1_pc~0 == 1); 15762#L206-14 is_transmit1_triggered_~__retres1~1 := 0; 15761#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15760#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 15759#L508-12 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 15755#L508-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15753#L225-12 assume !(~t2_pc~0 == 1); 15750#L225-14 is_transmit2_triggered_~__retres1~2 := 0; 15748#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15745#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 15743#L516-12 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 15741#L516-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15739#L244-12 assume !(~t3_pc~0 == 1); 15737#L244-14 is_transmit3_triggered_~__retres1~3 := 0; 15735#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15733#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 15731#L524-12 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 15728#L524-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15726#L451-3 assume ~M_E~0 == 1;~M_E~0 := 2; 15724#L451-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 15722#L456-3 assume !(~T2_E~0 == 1); 15720#L461-3 assume !(~T3_E~0 == 1); 15718#L466-3 assume ~E_1~0 == 1;~E_1~0 := 2; 15716#L471-3 assume !(~E_2~0 == 1); 15714#L476-3 assume ~E_3~0 == 1;~E_3~0 := 2; 15712#L481-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 15711#L299-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 15701#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 15690#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 15688#L661 assume !(start_simulation_~tmp~3 == 0); 15686#L661-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 15635#L299-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 15630#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 15628#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 15626#L616 assume !(stop_simulation_~tmp~2 != 0);stop_simulation_~__retres2~0 := 1; 15624#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 15622#L624 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 15613#L674 assume !(start_simulation_~tmp___0~1 != 0); 15429#L642-3 [2018-11-10 05:48:19,411 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:19,411 INFO L82 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 2 times [2018-11-10 05:48:19,411 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:19,411 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:19,412 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:19,412 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:48:19,412 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:19,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:48:19,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:48:19,424 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:19,424 INFO L82 PathProgramCache]: Analyzing trace with hash 1654401385, now seen corresponding path program 1 times [2018-11-10 05:48:19,424 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:19,424 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:19,424 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:19,425 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 05:48:19,425 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:19,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:48:19,456 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:48:19,456 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:48:19,456 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 05:48:19,456 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 05:48:19,457 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 05:48:19,457 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 05:48:19,457 INFO L87 Difference]: Start difference. First operand 963 states and 1307 transitions. cyclomatic complexity: 348 Second operand 5 states. [2018-11-10 05:48:19,561 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:48:19,561 INFO L93 Difference]: Finished difference Result 1676 states and 2244 transitions. [2018-11-10 05:48:19,562 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-10 05:48:19,562 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1676 states and 2244 transitions. [2018-11-10 05:48:19,570 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1614 [2018-11-10 05:48:19,576 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1676 states to 1676 states and 2244 transitions. [2018-11-10 05:48:19,576 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1676 [2018-11-10 05:48:19,577 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1676 [2018-11-10 05:48:19,577 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1676 states and 2244 transitions. [2018-11-10 05:48:19,579 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 05:48:19,579 INFO L705 BuchiCegarLoop]: Abstraction has 1676 states and 2244 transitions. [2018-11-10 05:48:19,580 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1676 states and 2244 transitions. [2018-11-10 05:48:19,592 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1676 to 975. [2018-11-10 05:48:19,592 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 975 states. [2018-11-10 05:48:19,595 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 975 states to 975 states and 1319 transitions. [2018-11-10 05:48:19,595 INFO L728 BuchiCegarLoop]: Abstraction has 975 states and 1319 transitions. [2018-11-10 05:48:19,595 INFO L608 BuchiCegarLoop]: Abstraction has 975 states and 1319 transitions. [2018-11-10 05:48:19,595 INFO L442 BuchiCegarLoop]: ======== Iteration 12============ [2018-11-10 05:48:19,595 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 975 states and 1319 transitions. [2018-11-10 05:48:19,598 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 917 [2018-11-10 05:48:19,598 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:48:19,598 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:48:19,599 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:19,599 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:19,599 INFO L793 eck$LassoCheckResult]: Stem: 17922#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 17760#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 17761#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 17914#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17915#L271 assume ~m_i~0 == 1;~m_st~0 := 0; 18007#L271-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 18016#L276-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 17882#L281-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 17883#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17913#L408 assume !(~M_E~0 == 0); 18036#L408-2 assume !(~T1_E~0 == 0); 17870#L413-1 assume !(~T2_E~0 == 0); 17871#L418-1 assume !(~T3_E~0 == 0); 17944#L423-1 assume !(~E_1~0 == 0); 17793#L428-1 assume !(~E_2~0 == 0); 17794#L433-1 assume !(~E_3~0 == 0); 17802#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 17902#L187 assume !(~m_pc~0 == 1); 17903#L187-2 is_master_triggered_~__retres1~0 := 0; 17934#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 18098#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 17970#L500 assume !(activate_threads_~tmp~1 != 0); 17971#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 17975#L206 assume !(~t1_pc~0 == 1); 18086#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 18087#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17804#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 17805#L508 assume !(activate_threads_~tmp___0~0 != 0); 18002#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 17976#L225 assume !(~t2_pc~0 == 1); 17874#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 17972#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 17881#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 17786#L516 assume !(activate_threads_~tmp___1~0 != 0); 17787#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 17788#L244 assume !(~t3_pc~0 == 1); 18092#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 17993#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 17994#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 18023#L524 assume !(activate_threads_~tmp___2~0 != 0); 18024#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17938#L451 assume !(~M_E~0 == 1); 17939#L451-2 assume !(~T1_E~0 == 1); 17945#L456-1 assume !(~T2_E~0 == 1); 17789#L461-1 assume !(~T3_E~0 == 1); 17790#L466-1 assume !(~E_1~0 == 1); 17801#L471-1 assume !(~E_2~0 == 1); 18056#L476-1 assume !(~E_3~0 == 1); 18075#L481-1 assume { :end_inline_reset_delta_events } true; 17808#L642-3 [2018-11-10 05:48:19,599 INFO L795 eck$LassoCheckResult]: Loop: 17808#L642-3 assume true; 17806#L642-1 assume !false; 17750#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 17751#L383 assume true; 18039#L331-1 assume !false; 17982#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 17983#L299 assume !(~m_st~0 == 0); 17845#L303 assume !(~t1_st~0 == 0); 17766#L307 assume !(~t2_st~0 == 0); 17768#L311 assume !(~t3_st~0 == 0);exists_runnable_thread_~__retres1~4 := 0; 18067#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 18486#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 18124#L336 assume !(eval_~tmp~0 != 0); 18125#L398 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 18652#L264-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 18651#L408-3 assume ~M_E~0 == 0;~M_E~0 := 1; 18650#L408-5 assume !(~T1_E~0 == 0); 18649#L413-3 assume !(~T2_E~0 == 0); 18648#L418-3 assume !(~T3_E~0 == 0); 17964#L423-3 assume ~E_1~0 == 0;~E_1~0 := 1; 17965#L428-3 assume !(~E_2~0 == 0); 17799#L433-3 assume ~E_3~0 == 0;~E_3~0 := 1; 17800#L438-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 18647#L187-12 assume ~m_pc~0 == 1; 18646#L188-4 assume ~M_E~0 == 1;is_master_triggered_~__retres1~0 := 1; 18644#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 18642#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 18109#L500-12 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 18110#L500-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 18073#L206-12 assume !(~t1_pc~0 == 1); 18074#L206-14 is_transmit1_triggered_~__retres1~1 := 0; 18371#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 18157#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 18158#L508-12 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 18153#L508-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 18154#L225-12 assume !(~t2_pc~0 == 1); 17916#L225-14 is_transmit2_triggered_~__retres1~2 := 0; 17917#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 17946#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 17752#L516-12 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 17753#L516-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 18368#L244-12 assume !(~t3_pc~0 == 1); 18367#L244-14 is_transmit3_triggered_~__retres1~3 := 0; 18366#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 18365#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 18364#L524-12 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 18363#L524-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18362#L451-3 assume ~M_E~0 == 1;~M_E~0 := 2; 18361#L451-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 18360#L456-3 assume !(~T2_E~0 == 1); 18359#L461-3 assume !(~T3_E~0 == 1); 18358#L466-3 assume ~E_1~0 == 1;~E_1~0 := 2; 18357#L471-3 assume !(~E_2~0 == 1); 18356#L476-3 assume ~E_3~0 == 1;~E_3~0 := 2; 18355#L481-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 18354#L299-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 18350#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 18349#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 18347#L661 assume !(start_simulation_~tmp~3 == 0); 18348#L661-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 18093#L299-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 17781#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 17992#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 17958#L616 assume !(stop_simulation_~tmp~2 != 0);stop_simulation_~__retres2~0 := 1; 17959#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 18035#L624 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 18080#L674 assume !(start_simulation_~tmp___0~1 != 0); 17808#L642-3 [2018-11-10 05:48:19,599 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:19,599 INFO L82 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 3 times [2018-11-10 05:48:19,599 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:19,600 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:19,600 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:19,600 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:48:19,600 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:19,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:48:19,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:48:19,611 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:19,612 INFO L82 PathProgramCache]: Analyzing trace with hash -880731976, now seen corresponding path program 1 times [2018-11-10 05:48:19,612 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:19,612 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:19,612 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:19,613 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 05:48:19,613 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:19,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:48:19,651 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:48:19,652 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:48:19,652 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 05:48:19,652 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 05:48:19,652 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 05:48:19,652 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 05:48:19,652 INFO L87 Difference]: Start difference. First operand 975 states and 1319 transitions. cyclomatic complexity: 348 Second operand 5 states. [2018-11-10 05:48:19,761 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:48:19,761 INFO L93 Difference]: Finished difference Result 3122 states and 4182 transitions. [2018-11-10 05:48:19,762 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-10 05:48:19,762 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3122 states and 4182 transitions. [2018-11-10 05:48:19,772 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3052 [2018-11-10 05:48:19,784 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3122 states to 3122 states and 4182 transitions. [2018-11-10 05:48:19,784 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3122 [2018-11-10 05:48:19,786 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3122 [2018-11-10 05:48:19,786 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3122 states and 4182 transitions. [2018-11-10 05:48:19,789 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 05:48:19,789 INFO L705 BuchiCegarLoop]: Abstraction has 3122 states and 4182 transitions. [2018-11-10 05:48:19,791 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3122 states and 4182 transitions. [2018-11-10 05:48:19,808 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3122 to 987. [2018-11-10 05:48:19,808 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 987 states. [2018-11-10 05:48:19,810 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 987 states to 987 states and 1331 transitions. [2018-11-10 05:48:19,810 INFO L728 BuchiCegarLoop]: Abstraction has 987 states and 1331 transitions. [2018-11-10 05:48:19,810 INFO L608 BuchiCegarLoop]: Abstraction has 987 states and 1331 transitions. [2018-11-10 05:48:19,810 INFO L442 BuchiCegarLoop]: ======== Iteration 13============ [2018-11-10 05:48:19,810 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 987 states and 1331 transitions. [2018-11-10 05:48:19,813 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 929 [2018-11-10 05:48:19,813 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:48:19,813 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:48:19,813 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:19,813 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:19,814 INFO L793 eck$LassoCheckResult]: Stem: 22032#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 21873#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 21874#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 22024#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22025#L271 assume ~m_i~0 == 1;~m_st~0 := 0; 22119#L271-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 22128#L276-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 21993#L281-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 21994#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22021#L408 assume !(~M_E~0 == 0); 22143#L408-2 assume !(~T1_E~0 == 0); 21982#L413-1 assume !(~T2_E~0 == 0); 21983#L418-1 assume !(~T3_E~0 == 0); 22051#L423-1 assume !(~E_1~0 == 0); 21906#L428-1 assume !(~E_2~0 == 0); 21907#L433-1 assume !(~E_3~0 == 0); 21914#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 22012#L187 assume !(~m_pc~0 == 1); 22013#L187-2 is_master_triggered_~__retres1~0 := 0; 22041#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 22211#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 22081#L500 assume !(activate_threads_~tmp~1 != 0); 22082#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22086#L206 assume !(~t1_pc~0 == 1); 22191#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 22192#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 21916#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 21917#L508 assume !(activate_threads_~tmp___0~0 != 0); 22115#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22087#L225 assume !(~t2_pc~0 == 1); 21985#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 22083#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 21987#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 21899#L516 assume !(activate_threads_~tmp___1~0 != 0); 21900#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 21901#L244 assume !(~t3_pc~0 == 1); 22200#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 22107#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 22108#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 22135#L524 assume !(activate_threads_~tmp___2~0 != 0); 22136#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22043#L451 assume !(~M_E~0 == 1); 22044#L451-2 assume !(~T1_E~0 == 1); 22052#L456-1 assume !(~T2_E~0 == 1); 21902#L461-1 assume !(~T3_E~0 == 1); 21903#L466-1 assume !(~E_1~0 == 1); 21913#L471-1 assume !(~E_2~0 == 1); 22164#L476-1 assume !(~E_3~0 == 1); 22186#L481-1 assume { :end_inline_reset_delta_events } true; 22202#L642-3 [2018-11-10 05:48:19,814 INFO L795 eck$LassoCheckResult]: Loop: 22202#L642-3 assume true; 22556#L642-1 assume !false; 22553#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 22530#L383 assume true; 22527#L331-1 assume !false; 22396#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 22394#L299 assume !(~m_st~0 == 0); 22391#L303 assume !(~t1_st~0 == 0); 22390#L307 assume !(~t2_st~0 == 0); 22389#L311 assume !(~t3_st~0 == 0);exists_runnable_thread_~__retres1~4 := 0; 22388#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 22387#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 22386#L336 assume !(eval_~tmp~0 != 0); 22385#L398 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 22383#L264-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 22381#L408-3 assume ~M_E~0 == 0;~M_E~0 := 1; 22379#L408-5 assume !(~T1_E~0 == 0); 22377#L413-3 assume !(~T2_E~0 == 0); 22375#L418-3 assume !(~T3_E~0 == 0); 22373#L423-3 assume ~E_1~0 == 0;~E_1~0 := 1; 22371#L428-3 assume !(~E_2~0 == 0); 22368#L433-3 assume ~E_3~0 == 0;~E_3~0 := 1; 22366#L438-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 22364#L187-12 assume ~m_pc~0 == 1; 22361#L188-4 assume ~M_E~0 == 1;is_master_triggered_~__retres1~0 := 1; 22362#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 22395#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 22348#L500-12 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 22349#L500-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22184#L206-12 assume !(~t1_pc~0 == 1); 22185#L206-14 is_transmit1_triggered_~__retres1~1 := 0; 22617#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22616#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 22615#L508-12 assume activate_threads_~tmp___0~0 != 0;~t1_st~0 := 0; 22195#L508-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22062#L225-12 assume !(~t2_pc~0 == 1); 22026#L225-14 is_transmit2_triggered_~__retres1~2 := 0; 22027#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22146#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 22147#L516-12 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 22611#L516-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22610#L244-12 assume !(~t3_pc~0 == 1); 22609#L244-14 is_transmit3_triggered_~__retres1~3 := 0; 22608#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 22607#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 22606#L524-12 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 22605#L524-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22604#L451-3 assume ~M_E~0 == 1;~M_E~0 := 2; 22603#L451-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 22602#L456-3 assume !(~T2_E~0 == 1); 22601#L461-3 assume !(~T3_E~0 == 1); 22600#L466-3 assume ~E_1~0 == 1;~E_1~0 := 2; 22599#L471-3 assume !(~E_2~0 == 1); 22598#L476-3 assume ~E_3~0 == 1;~E_3~0 := 2; 22597#L481-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 22596#L299-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 22589#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 22587#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 22584#L661 assume !(start_simulation_~tmp~3 == 0); 22574#L661-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 22572#L299-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 22569#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 22567#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 22565#L616 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 22563#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 22562#L624 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 22557#L674 assume !(start_simulation_~tmp___0~1 != 0); 22202#L642-3 [2018-11-10 05:48:19,814 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:19,814 INFO L82 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 4 times [2018-11-10 05:48:19,814 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:19,814 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:19,815 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:19,815 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:48:19,815 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:19,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:48:19,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:48:19,825 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:19,825 INFO L82 PathProgramCache]: Analyzing trace with hash -880791558, now seen corresponding path program 1 times [2018-11-10 05:48:19,825 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:19,825 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:19,826 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:19,826 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 05:48:19,826 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:19,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:48:19,866 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:48:19,866 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:48:19,866 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 05:48:19,866 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 05:48:19,866 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 05:48:19,866 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 05:48:19,867 INFO L87 Difference]: Start difference. First operand 987 states and 1331 transitions. cyclomatic complexity: 348 Second operand 5 states. [2018-11-10 05:48:20,002 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:48:20,003 INFO L93 Difference]: Finished difference Result 1811 states and 2422 transitions. [2018-11-10 05:48:20,004 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-10 05:48:20,004 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1811 states and 2422 transitions. [2018-11-10 05:48:20,011 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1753 [2018-11-10 05:48:20,018 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1811 states to 1811 states and 2422 transitions. [2018-11-10 05:48:20,018 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1811 [2018-11-10 05:48:20,019 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1811 [2018-11-10 05:48:20,020 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1811 states and 2422 transitions. [2018-11-10 05:48:20,023 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 05:48:20,024 INFO L705 BuchiCegarLoop]: Abstraction has 1811 states and 2422 transitions. [2018-11-10 05:48:20,025 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1811 states and 2422 transitions. [2018-11-10 05:48:20,038 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1811 to 1017. [2018-11-10 05:48:20,038 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1017 states. [2018-11-10 05:48:20,040 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1017 states to 1017 states and 1352 transitions. [2018-11-10 05:48:20,041 INFO L728 BuchiCegarLoop]: Abstraction has 1017 states and 1352 transitions. [2018-11-10 05:48:20,041 INFO L608 BuchiCegarLoop]: Abstraction has 1017 states and 1352 transitions. [2018-11-10 05:48:20,041 INFO L442 BuchiCegarLoop]: ======== Iteration 14============ [2018-11-10 05:48:20,041 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1017 states and 1352 transitions. [2018-11-10 05:48:20,043 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 959 [2018-11-10 05:48:20,044 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:48:20,044 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:48:20,044 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:20,044 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:20,044 INFO L793 eck$LassoCheckResult]: Stem: 24844#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 24685#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 24686#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 24836#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24837#L271 assume ~m_i~0 == 1;~m_st~0 := 0; 24932#L271-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 24940#L276-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 24804#L281-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 24805#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24835#L408 assume !(~M_E~0 == 0); 24958#L408-2 assume !(~T1_E~0 == 0); 24794#L413-1 assume !(~T2_E~0 == 0); 24795#L418-1 assume !(~T3_E~0 == 0); 24864#L423-1 assume !(~E_1~0 == 0); 24718#L428-1 assume !(~E_2~0 == 0); 24719#L433-1 assume !(~E_3~0 == 0); 24726#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 24824#L187 assume !(~m_pc~0 == 1); 24825#L187-2 is_master_triggered_~__retres1~0 := 0; 24854#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 25033#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 24891#L500 assume !(activate_threads_~tmp~1 != 0); 24892#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 24895#L206 assume !(~t1_pc~0 == 1); 25015#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 25016#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 24728#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 24729#L508 assume !(activate_threads_~tmp___0~0 != 0); 24928#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 24896#L225 assume !(~t2_pc~0 == 1); 24797#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 24893#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 24799#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 24711#L516 assume !(activate_threads_~tmp___1~0 != 0); 24712#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 24713#L244 assume !(~t3_pc~0 == 1); 25025#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 24918#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 24919#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 24948#L524 assume !(activate_threads_~tmp___2~0 != 0); 24949#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24856#L451 assume !(~M_E~0 == 1); 24857#L451-2 assume !(~T1_E~0 == 1); 24865#L456-1 assume !(~T2_E~0 == 1); 24714#L461-1 assume !(~T3_E~0 == 1); 24715#L466-1 assume !(~E_1~0 == 1); 24725#L471-1 assume !(~E_2~0 == 1); 24974#L476-1 assume !(~E_3~0 == 1); 25003#L481-1 assume { :end_inline_reset_delta_events } true; 25027#L642-3 [2018-11-10 05:48:20,045 INFO L795 eck$LassoCheckResult]: Loop: 25027#L642-3 assume true; 25239#L642-1 assume !false; 25231#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 25223#L383 assume true; 25224#L331-1 assume !false; 25187#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 25188#L299 assume !(~m_st~0 == 0); 25226#L303 assume !(~t1_st~0 == 0); 25227#L307 assume !(~t2_st~0 == 0); 25225#L311 assume !(~t3_st~0 == 0);exists_runnable_thread_~__retres1~4 := 0; 25174#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 25175#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 25131#L336 assume !(eval_~tmp~0 != 0); 25132#L398 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 25125#L264-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 25126#L408-3 assume ~M_E~0 == 0;~M_E~0 := 1; 25112#L408-5 assume !(~T1_E~0 == 0); 25113#L413-3 assume !(~T2_E~0 == 0); 25104#L418-3 assume !(~T3_E~0 == 0); 25105#L423-3 assume ~E_1~0 == 0;~E_1~0 := 1; 25096#L428-3 assume !(~E_2~0 == 0); 25097#L433-3 assume ~E_3~0 == 0;~E_3~0 := 1; 25088#L438-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 25089#L187-12 assume ~m_pc~0 == 1; 25074#L188-4 assume ~M_E~0 == 1;is_master_triggered_~__retres1~0 := 1; 25075#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 25058#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 25059#L500-12 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 25047#L500-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 25048#L206-12 assume !(~t1_pc~0 == 1); 25481#L206-14 is_transmit1_triggered_~__retres1~1 := 0; 25479#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 25477#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 25474#L508-12 assume !(activate_threads_~tmp___0~0 != 0); 25472#L508-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 25470#L225-12 assume !(~t2_pc~0 == 1); 25467#L225-14 is_transmit2_triggered_~__retres1~2 := 0; 25465#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 25463#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 25461#L516-12 assume activate_threads_~tmp___1~0 != 0;~t2_st~0 := 0; 25458#L516-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 25456#L244-12 assume !(~t3_pc~0 == 1); 25454#L244-14 is_transmit3_triggered_~__retres1~3 := 0; 25452#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 25450#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 25448#L524-12 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 25446#L524-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25444#L451-3 assume ~M_E~0 == 1;~M_E~0 := 2; 25441#L451-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 25438#L456-3 assume !(~T2_E~0 == 1); 25435#L461-3 assume !(~T3_E~0 == 1); 25431#L466-3 assume ~E_1~0 == 1;~E_1~0 := 2; 25427#L471-3 assume !(~E_2~0 == 1); 25420#L476-3 assume ~E_3~0 == 1;~E_3~0 := 2; 25308#L481-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 25306#L299-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 25299#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 25297#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 25294#L661 assume !(start_simulation_~tmp~3 == 0); 25291#L661-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 25285#L299-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 25280#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 25278#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 25276#L616 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 25274#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 25272#L624 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 25270#L674 assume !(start_simulation_~tmp___0~1 != 0); 25027#L642-3 [2018-11-10 05:48:20,045 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:20,045 INFO L82 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 5 times [2018-11-10 05:48:20,045 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:20,045 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:20,046 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:20,046 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:48:20,046 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:20,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:48:20,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:48:20,057 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:20,057 INFO L82 PathProgramCache]: Analyzing trace with hash 1170192440, now seen corresponding path program 1 times [2018-11-10 05:48:20,057 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:20,057 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:20,058 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:20,058 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 05:48:20,058 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:20,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:48:20,096 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:48:20,096 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:48:20,096 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 05:48:20,097 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 05:48:20,097 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 05:48:20,097 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 05:48:20,097 INFO L87 Difference]: Start difference. First operand 1017 states and 1352 transitions. cyclomatic complexity: 339 Second operand 5 states. [2018-11-10 05:48:20,206 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:48:20,206 INFO L93 Difference]: Finished difference Result 1445 states and 1913 transitions. [2018-11-10 05:48:20,206 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-10 05:48:20,207 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1445 states and 1913 transitions. [2018-11-10 05:48:20,211 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1387 [2018-11-10 05:48:20,216 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1445 states to 1445 states and 1913 transitions. [2018-11-10 05:48:20,216 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1445 [2018-11-10 05:48:20,217 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1445 [2018-11-10 05:48:20,217 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1445 states and 1913 transitions. [2018-11-10 05:48:20,219 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 05:48:20,219 INFO L705 BuchiCegarLoop]: Abstraction has 1445 states and 1913 transitions. [2018-11-10 05:48:20,220 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1445 states and 1913 transitions. [2018-11-10 05:48:20,232 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1445 to 1023. [2018-11-10 05:48:20,232 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1023 states. [2018-11-10 05:48:20,234 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1023 states to 1023 states and 1341 transitions. [2018-11-10 05:48:20,235 INFO L728 BuchiCegarLoop]: Abstraction has 1023 states and 1341 transitions. [2018-11-10 05:48:20,235 INFO L608 BuchiCegarLoop]: Abstraction has 1023 states and 1341 transitions. [2018-11-10 05:48:20,235 INFO L442 BuchiCegarLoop]: ======== Iteration 15============ [2018-11-10 05:48:20,235 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1023 states and 1341 transitions. [2018-11-10 05:48:20,237 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 965 [2018-11-10 05:48:20,237 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:48:20,238 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:48:20,238 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:20,238 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:20,238 INFO L793 eck$LassoCheckResult]: Stem: 27330#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 27161#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 27162#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 27322#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27323#L271 assume ~m_i~0 == 1;~m_st~0 := 0; 27420#L271-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 27432#L276-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 27290#L281-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 27291#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27321#L408 assume !(~M_E~0 == 0); 27454#L408-2 assume !(~T1_E~0 == 0); 27278#L413-1 assume !(~T2_E~0 == 0); 27279#L418-1 assume !(~T3_E~0 == 0); 27350#L423-1 assume !(~E_1~0 == 0); 27195#L428-1 assume !(~E_2~0 == 0); 27196#L433-1 assume !(~E_3~0 == 0); 27204#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 27310#L187 assume !(~m_pc~0 == 1); 27311#L187-2 is_master_triggered_~__retres1~0 := 0; 27313#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 27314#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 27380#L500 assume !(activate_threads_~tmp~1 != 0); 27381#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 27385#L206 assume !(~t1_pc~0 == 1); 27507#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 27508#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 27206#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 27207#L508 assume !(activate_threads_~tmp___0~0 != 0); 27415#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 27386#L225 assume !(~t2_pc~0 == 1); 27281#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 27382#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 27289#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 27188#L516 assume !(activate_threads_~tmp___1~0 != 0); 27189#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 27190#L244 assume !(~t3_pc~0 == 1); 27515#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 27407#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 27408#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 27440#L524 assume !(activate_threads_~tmp___2~0 != 0); 27441#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27343#L451 assume !(~M_E~0 == 1); 27344#L451-2 assume !(~T1_E~0 == 1); 27351#L456-1 assume !(~T2_E~0 == 1); 27191#L461-1 assume !(~T3_E~0 == 1); 27192#L466-1 assume !(~E_1~0 == 1); 27203#L471-1 assume !(~E_2~0 == 1); 27474#L476-1 assume !(~E_3~0 == 1); 27498#L481-1 assume { :end_inline_reset_delta_events } true; 27517#L642-3 [2018-11-10 05:48:20,239 INFO L795 eck$LassoCheckResult]: Loop: 27517#L642-3 assume true; 28032#L642-1 assume !false; 28031#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 27766#L383 assume true; 28029#L331-1 assume !false; 28028#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 28023#L299 assume !(~m_st~0 == 0); 28024#L303 assume !(~t1_st~0 == 0); 28027#L307 assume !(~t2_st~0 == 0); 28025#L311 assume !(~t3_st~0 == 0);exists_runnable_thread_~__retres1~4 := 0; 28026#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 28018#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 28019#L336 assume !(eval_~tmp~0 != 0); 28138#L398 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 28137#L264-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 28136#L408-3 assume ~M_E~0 == 0;~M_E~0 := 1; 28135#L408-5 assume !(~T1_E~0 == 0); 28098#L413-3 assume !(~T2_E~0 == 0); 28057#L418-3 assume !(~T3_E~0 == 0); 28056#L423-3 assume ~E_1~0 == 0;~E_1~0 := 1; 28054#L428-3 assume !(~E_2~0 == 0); 28053#L433-3 assume ~E_3~0 == 0;~E_3~0 := 1; 27225#L438-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 27226#L187-12 assume ~m_pc~0 == 1; 27253#L188-4 assume ~M_E~0 == 1;is_master_triggered_~__retres1~0 := 1; 27448#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 27449#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 27450#L500-12 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 27367#L500-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 27369#L206-12 assume !(~t1_pc~0 == 1); 27496#L206-14 is_transmit1_triggered_~__retres1~1 := 0; 27497#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 27230#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 27231#L508-12 assume !(activate_threads_~tmp___0~0 != 0); 27511#L508-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 27362#L225-12 assume !(~t2_pc~0 == 1); 27324#L225-14 is_transmit2_triggered_~__retres1~2 := 0; 27325#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 27352#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 27154#L516-12 assume !(activate_threads_~tmp___1~0 != 0); 27155#L516-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 27156#L244-12 assume !(~t3_pc~0 == 1); 27502#L244-14 is_transmit3_triggered_~__retres1~3 := 0; 27503#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 27468#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 27426#L524-12 assume activate_threads_~tmp___2~0 != 0;~t3_st~0 := 0; 27410#L524-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27353#L451-3 assume ~M_E~0 == 1;~M_E~0 := 2; 27326#L451-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 27327#L456-3 assume !(~T2_E~0 == 1); 27197#L461-3 assume !(~T3_E~0 == 1); 27198#L466-3 assume ~E_1~0 == 1;~E_1~0 := 2; 27205#L471-3 assume !(~E_2~0 == 1); 27214#L476-3 assume ~E_3~0 == 1;~E_3~0 := 2; 27484#L481-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 27409#L299-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 27176#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 27402#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 27261#L661 assume !(start_simulation_~tmp~3 == 0); 27262#L661-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 28045#L299-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 28041#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 28039#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 28038#L616 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 28036#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 28035#L624 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 28034#L674 assume !(start_simulation_~tmp___0~1 != 0); 27517#L642-3 [2018-11-10 05:48:20,239 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:20,239 INFO L82 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 6 times [2018-11-10 05:48:20,239 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:20,239 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:20,240 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:20,240 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:48:20,240 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:20,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:48:20,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:48:20,250 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:20,250 INFO L82 PathProgramCache]: Analyzing trace with hash 660719350, now seen corresponding path program 1 times [2018-11-10 05:48:20,250 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:20,251 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:20,251 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:20,251 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 05:48:20,251 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:20,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:48:20,298 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:48:20,298 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:48:20,298 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-10 05:48:20,298 INFO L810 eck$LassoCheckResult]: loop already infeasible [2018-11-10 05:48:20,298 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-10 05:48:20,298 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-10 05:48:20,299 INFO L87 Difference]: Start difference. First operand 1023 states and 1341 transitions. cyclomatic complexity: 322 Second operand 5 states. [2018-11-10 05:48:20,409 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:48:20,410 INFO L93 Difference]: Finished difference Result 1702 states and 2228 transitions. [2018-11-10 05:48:20,411 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-10 05:48:20,411 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1702 states and 2228 transitions. [2018-11-10 05:48:20,416 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1640 [2018-11-10 05:48:20,421 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1702 states to 1702 states and 2228 transitions. [2018-11-10 05:48:20,421 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1702 [2018-11-10 05:48:20,422 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1702 [2018-11-10 05:48:20,423 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1702 states and 2228 transitions. [2018-11-10 05:48:20,425 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-10 05:48:20,425 INFO L705 BuchiCegarLoop]: Abstraction has 1702 states and 2228 transitions. [2018-11-10 05:48:20,426 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1702 states and 2228 transitions. [2018-11-10 05:48:20,438 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1702 to 1050. [2018-11-10 05:48:20,438 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1050 states. [2018-11-10 05:48:20,440 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1050 states to 1050 states and 1358 transitions. [2018-11-10 05:48:20,440 INFO L728 BuchiCegarLoop]: Abstraction has 1050 states and 1358 transitions. [2018-11-10 05:48:20,440 INFO L608 BuchiCegarLoop]: Abstraction has 1050 states and 1358 transitions. [2018-11-10 05:48:20,440 INFO L442 BuchiCegarLoop]: ======== Iteration 16============ [2018-11-10 05:48:20,440 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1050 states and 1358 transitions. [2018-11-10 05:48:20,442 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 992 [2018-11-10 05:48:20,442 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:48:20,442 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:48:20,443 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:20,443 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:20,443 INFO L793 eck$LassoCheckResult]: Stem: 30064#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 29900#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 29901#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 30056#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30057#L271 assume ~m_i~0 == 1;~m_st~0 := 0; 30145#L271-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 30153#L276-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 30024#L281-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 30025#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30055#L408 assume !(~M_E~0 == 0); 30167#L408-2 assume !(~T1_E~0 == 0); 30014#L413-1 assume !(~T2_E~0 == 0); 30015#L418-1 assume !(~T3_E~0 == 0); 30084#L423-1 assume !(~E_1~0 == 0); 29935#L428-1 assume !(~E_2~0 == 0); 29936#L433-1 assume !(~E_3~0 == 0); 29945#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 30043#L187 assume !(~m_pc~0 == 1); 30044#L187-2 is_master_triggered_~__retres1~0 := 0; 30074#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 30232#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 30108#L500 assume !(activate_threads_~tmp~1 != 0); 30109#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 30113#L206 assume !(~t1_pc~0 == 1); 30215#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 30216#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 29947#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 29948#L508 assume !(activate_threads_~tmp___0~0 != 0); 30141#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 30114#L225 assume !(~t2_pc~0 == 1); 30018#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 30110#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 30023#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 29928#L516 assume !(activate_threads_~tmp___1~0 != 0); 29929#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 29930#L244 assume !(~t3_pc~0 == 1); 30224#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 30132#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 30133#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 30159#L524 assume !(activate_threads_~tmp___2~0 != 0); 30160#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30078#L451 assume !(~M_E~0 == 1); 30079#L451-2 assume !(~T1_E~0 == 1); 30085#L456-1 assume !(~T2_E~0 == 1); 29931#L461-1 assume !(~T3_E~0 == 1); 29932#L466-1 assume !(~E_1~0 == 1); 29944#L471-1 assume !(~E_2~0 == 1); 30187#L476-1 assume !(~E_3~0 == 1); 30206#L481-1 assume { :end_inline_reset_delta_events } true; 30227#L642-3 [2018-11-10 05:48:20,443 INFO L795 eck$LassoCheckResult]: Loop: 30227#L642-3 assume true; 30613#L642-1 assume !false; 30610#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 30609#L383 assume true; 30608#L331-1 assume !false; 30607#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 30606#L299 assume !(~m_st~0 == 0); 30605#L303 assume !(~t1_st~0 == 0); 30604#L307 assume !(~t2_st~0 == 0); 30602#L311 assume !(~t3_st~0 == 0);exists_runnable_thread_~__retres1~4 := 0; 30601#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 30600#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 30599#L336 assume !(eval_~tmp~0 != 0); 30598#L398 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 30597#L264-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 30596#L408-3 assume ~M_E~0 == 0;~M_E~0 := 1; 30595#L408-5 assume !(~T1_E~0 == 0); 30594#L413-3 assume !(~T2_E~0 == 0); 30593#L418-3 assume !(~T3_E~0 == 0); 30592#L423-3 assume ~E_1~0 == 0;~E_1~0 := 1; 30591#L428-3 assume !(~E_2~0 == 0); 30590#L433-3 assume ~E_3~0 == 0;~E_3~0 := 1; 30589#L438-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 30588#L187-12 assume ~m_pc~0 == 1; 30585#L188-4 assume ~M_E~0 == 1;is_master_triggered_~__retres1~0 := 1; 30582#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 30579#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 30576#L500-12 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 30574#L500-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 30572#L206-12 assume !(~t1_pc~0 == 1); 30570#L206-14 is_transmit1_triggered_~__retres1~1 := 0; 30567#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 30563#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 30559#L508-12 assume !(activate_threads_~tmp___0~0 != 0); 30555#L508-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 30550#L225-12 assume !(~t2_pc~0 == 1); 30545#L225-14 is_transmit2_triggered_~__retres1~2 := 0; 30541#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 30536#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 30532#L516-12 assume !(activate_threads_~tmp___1~0 != 0); 30528#L516-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 30211#L244-12 assume !(~t3_pc~0 == 1); 30212#L244-14 is_transmit3_triggered_~__retres1~3 := 0; 30731#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 30730#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 30729#L524-12 assume !(activate_threads_~tmp___2~0 != 0); 30728#L524-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30727#L451-3 assume ~M_E~0 == 1;~M_E~0 := 2; 30725#L451-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 30722#L456-3 assume !(~T2_E~0 == 1); 30719#L461-3 assume !(~T3_E~0 == 1); 30716#L466-3 assume ~E_1~0 == 1;~E_1~0 := 2; 30712#L471-3 assume !(~E_2~0 == 1); 30708#L476-3 assume ~E_3~0 == 1;~E_3~0 := 2; 30704#L481-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 30700#L299-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 30694#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 30690#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 30685#L661 assume !(start_simulation_~tmp~3 == 0); 30681#L661-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 30677#L299-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 30672#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 30669#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 30664#L616 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 30661#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 30659#L624 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 30657#L674 assume !(start_simulation_~tmp___0~1 != 0); 30227#L642-3 [2018-11-10 05:48:20,444 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:20,444 INFO L82 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 7 times [2018-11-10 05:48:20,444 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:20,444 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:20,444 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:20,445 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:48:20,445 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:20,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:48:20,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:48:20,455 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:20,455 INFO L82 PathProgramCache]: Analyzing trace with hash 879574068, now seen corresponding path program 1 times [2018-11-10 05:48:20,455 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:20,455 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:20,456 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:20,456 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:48:20,456 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:20,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:48:20,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:48:20,470 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:20,471 INFO L82 PathProgramCache]: Analyzing trace with hash 715358883, now seen corresponding path program 1 times [2018-11-10 05:48:20,471 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:20,471 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:20,471 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:20,471 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:48:20,472 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:20,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:48:20,510 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:48:20,510 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:48:20,510 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 05:48:20,885 WARN L179 SmtUtils]: Spent 366.00 ms on a formula simplification. DAG size of input: 134 DAG size of output: 121 [2018-11-10 05:48:21,001 INFO L214 LassoAnalysis]: Preferences: [2018-11-10 05:48:21,001 INFO L124 ssoRankerPreferences]: Compute integeral hull: false [2018-11-10 05:48:21,002 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true [2018-11-10 05:48:21,002 INFO L126 ssoRankerPreferences]: Term annotations enabled: false [2018-11-10 05:48:21,002 INFO L127 ssoRankerPreferences]: Use exernal solver: true [2018-11-10 05:48:21,002 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-10 05:48:21,002 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false [2018-11-10 05:48:21,002 INFO L130 ssoRankerPreferences]: Path of dumped script: [2018-11-10 05:48:21,002 INFO L131 ssoRankerPreferences]: Filename of dumped script: transmitter.03_false-unreach-call_false-termination.cil.c_Iteration16_Loop [2018-11-10 05:48:21,002 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank [2018-11-10 05:48:21,002 INFO L280 LassoAnalysis]: Starting lasso preprocessing... [2018-11-10 05:48:21,020 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,024 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,025 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,028 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,029 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,030 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,031 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,035 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,044 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,045 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,047 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,049 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,050 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,051 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,053 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,054 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,057 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,061 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,062 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,063 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,069 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,081 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,082 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,086 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,089 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,091 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,100 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,101 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,106 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,111 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,112 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,114 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,115 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,117 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,119 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,123 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,125 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,127 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,129 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,131 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,132 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,364 INFO L298 LassoAnalysis]: Preprocessing complete. [2018-11-10 05:48:21,365 INFO L410 LassoAnalysis]: Checking for nontermination... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_336a3a10-29f9-4018-bc2b-dd0bc6bf9d7c/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-10 05:48:21,378 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-10 05:48:21,379 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-10 05:48:21,387 INFO L443 LassoAnalysis]: Proved nontermination for one component. [2018-11-10 05:48:21,387 INFO L446 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___1~0=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___1~0=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_336a3a10-29f9-4018-bc2b-dd0bc6bf9d7c/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-10 05:48:21,406 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-10 05:48:21,406 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-10 05:48:21,409 INFO L443 LassoAnalysis]: Proved nontermination for one component. [2018-11-10 05:48:21,409 INFO L446 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t2_st~0=7} Honda state: {~t2_st~0=7} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_336a3a10-29f9-4018-bc2b-dd0bc6bf9d7c/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-10 05:48:21,446 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-10 05:48:21,446 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-10 05:48:21,453 INFO L443 LassoAnalysis]: Proved nontermination for one component. [2018-11-10 05:48:21,453 INFO L446 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~__retres2~0=0, ULTIMATE.start_start_simulation_~tmp___0~1=0, ULTIMATE.start_stop_simulation_#res=0} Honda state: {ULTIMATE.start_stop_simulation_~__retres2~0=0, ULTIMATE.start_start_simulation_~tmp___0~1=0, ULTIMATE.start_stop_simulation_#res=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_336a3a10-29f9-4018-bc2b-dd0bc6bf9d7c/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-10 05:48:21,478 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-10 05:48:21,478 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-10 05:48:21,480 INFO L443 LassoAnalysis]: Proved nontermination for one component. [2018-11-10 05:48:21,480 INFO L446 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret5=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret5=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_336a3a10-29f9-4018-bc2b-dd0bc6bf9d7c/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-10 05:48:21,498 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-10 05:48:21,498 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-10 05:48:21,500 INFO L443 LassoAnalysis]: Proved nontermination for one component. [2018-11-10 05:48:21,500 INFO L446 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_3~0=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_3~0=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_336a3a10-29f9-4018-bc2b-dd0bc6bf9d7c/bin-2019/uautomizer/z3 Starting monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-10 05:48:21,517 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-10 05:48:21,518 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-10 05:48:21,520 INFO L443 LassoAnalysis]: Proved nontermination for one component. [2018-11-10 05:48:21,520 INFO L446 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_#t~ret10=0} Honda state: {ULTIMATE.start_start_simulation_#t~ret10=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_336a3a10-29f9-4018-bc2b-dd0bc6bf9d7c/bin-2019/uautomizer/z3 Starting monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-10 05:48:21,542 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-10 05:48:21,542 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-10 05:48:21,549 INFO L443 LassoAnalysis]: Proved nontermination for one component. [2018-11-10 05:48:21,549 INFO L446 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit3_triggered_#res=0, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=0, ULTIMATE.start_activate_threads_~tmp___2~0=0} Honda state: {ULTIMATE.start_is_transmit3_triggered_#res=0, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=0, ULTIMATE.start_activate_threads_~tmp___2~0=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_336a3a10-29f9-4018-bc2b-dd0bc6bf9d7c/bin-2019/uautomizer/z3 Starting monitored process 9 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-10 05:48:21,577 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-10 05:48:21,577 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-10 05:48:21,580 INFO L443 LassoAnalysis]: Proved nontermination for one component. [2018-11-10 05:48:21,580 INFO L446 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t1_pc~0=-8} Honda state: {~t1_pc~0=-8} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_336a3a10-29f9-4018-bc2b-dd0bc6bf9d7c/bin-2019/uautomizer/z3 Starting monitored process 10 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-10 05:48:21,597 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-10 05:48:21,597 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-10 05:48:21,599 INFO L443 LassoAnalysis]: Proved nontermination for one component. [2018-11-10 05:48:21,599 INFO L446 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_#t~ret11=0} Honda state: {ULTIMATE.start_start_simulation_#t~ret11=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_336a3a10-29f9-4018-bc2b-dd0bc6bf9d7c/bin-2019/uautomizer/z3 Starting monitored process 11 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-10 05:48:21,615 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-10 05:48:21,615 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-10 05:48:21,617 INFO L443 LassoAnalysis]: Proved nontermination for one component. [2018-11-10 05:48:21,617 INFO L446 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t3_pc~0=-8} Honda state: {~t3_pc~0=-8} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_336a3a10-29f9-4018-bc2b-dd0bc6bf9d7c/bin-2019/uautomizer/z3 Starting monitored process 12 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-10 05:48:21,634 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-10 05:48:21,634 INFO L163 nArgumentSynthesizer]: Using integer mode. No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_336a3a10-29f9-4018-bc2b-dd0bc6bf9d7c/bin-2019/uautomizer/z3 Starting monitored process 13 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-10 05:48:21,657 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2018-11-10 05:48:21,657 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-10 05:48:21,660 INFO L450 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2018-11-10 05:48:21,675 INFO L214 LassoAnalysis]: Preferences: [2018-11-10 05:48:21,675 INFO L124 ssoRankerPreferences]: Compute integeral hull: false [2018-11-10 05:48:21,675 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true [2018-11-10 05:48:21,675 INFO L126 ssoRankerPreferences]: Term annotations enabled: false [2018-11-10 05:48:21,675 INFO L127 ssoRankerPreferences]: Use exernal solver: false [2018-11-10 05:48:21,675 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-10 05:48:21,675 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false [2018-11-10 05:48:21,675 INFO L130 ssoRankerPreferences]: Path of dumped script: [2018-11-10 05:48:21,675 INFO L131 ssoRankerPreferences]: Filename of dumped script: transmitter.03_false-unreach-call_false-termination.cil.c_Iteration16_Loop [2018-11-10 05:48:21,675 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank [2018-11-10 05:48:21,675 INFO L280 LassoAnalysis]: Starting lasso preprocessing... [2018-11-10 05:48:21,678 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,683 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,686 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,688 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,690 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,691 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,693 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,694 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,697 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,700 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,705 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,707 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,713 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,714 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,717 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,720 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,721 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,722 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,724 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,727 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,729 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,733 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,734 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,741 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,742 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,745 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,747 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,750 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,752 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,753 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,755 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,758 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,767 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,768 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,770 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,771 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,772 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,775 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,778 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,780 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:21,783 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:22,102 INFO L298 LassoAnalysis]: Preprocessing complete. [2018-11-10 05:48:22,106 INFO L496 LassoAnalysis]: Using template 'affine'. [2018-11-10 05:48:22,107 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-10 05:48:22,109 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-10 05:48:22,109 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-10 05:48:22,109 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-10 05:48:22,109 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-10 05:48:22,110 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-10 05:48:22,111 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-10 05:48:22,111 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-10 05:48:22,113 INFO L529 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-10 05:48:22,113 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-10 05:48:22,114 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-10 05:48:22,114 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-10 05:48:22,114 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-10 05:48:22,114 INFO L206 nArgumentSynthesizer]: 2 loop disjuncts [2018-11-10 05:48:22,114 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-10 05:48:22,115 INFO L402 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2018-11-10 05:48:22,115 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-10 05:48:22,116 INFO L529 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-10 05:48:22,116 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-10 05:48:22,116 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-10 05:48:22,116 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-10 05:48:22,117 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-10 05:48:22,117 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-10 05:48:22,117 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-10 05:48:22,117 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-10 05:48:22,117 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-10 05:48:22,118 INFO L529 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-10 05:48:22,118 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-10 05:48:22,118 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-10 05:48:22,119 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-10 05:48:22,119 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-10 05:48:22,119 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-10 05:48:22,119 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-10 05:48:22,119 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-10 05:48:22,119 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-10 05:48:22,120 INFO L529 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-10 05:48:22,120 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-10 05:48:22,120 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-10 05:48:22,120 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-10 05:48:22,121 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-10 05:48:22,121 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-10 05:48:22,121 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-10 05:48:22,121 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-10 05:48:22,121 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-10 05:48:22,121 INFO L529 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-10 05:48:22,122 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-10 05:48:22,122 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-10 05:48:22,122 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-10 05:48:22,122 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-10 05:48:22,122 INFO L206 nArgumentSynthesizer]: 2 loop disjuncts [2018-11-10 05:48:22,122 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-10 05:48:22,123 INFO L402 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2018-11-10 05:48:22,123 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-10 05:48:22,124 INFO L529 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-10 05:48:22,124 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-10 05:48:22,125 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-10 05:48:22,125 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-10 05:48:22,125 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-10 05:48:22,125 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-10 05:48:22,125 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-10 05:48:22,125 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-10 05:48:22,125 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-10 05:48:22,126 INFO L529 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-10 05:48:22,126 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-10 05:48:22,127 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-10 05:48:22,127 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-10 05:48:22,127 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-10 05:48:22,127 INFO L206 nArgumentSynthesizer]: 2 loop disjuncts [2018-11-10 05:48:22,127 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-10 05:48:22,127 INFO L402 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2018-11-10 05:48:22,127 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-10 05:48:22,128 INFO L529 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-10 05:48:22,128 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-10 05:48:22,129 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-10 05:48:22,129 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-10 05:48:22,129 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-10 05:48:22,129 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-10 05:48:22,129 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-10 05:48:22,130 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-10 05:48:22,130 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-10 05:48:22,131 INFO L421 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2018-11-10 05:48:22,133 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2018-11-10 05:48:22,133 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2018-11-10 05:48:22,135 INFO L437 nArgumentSynthesizer]: Simplifying supporting invariants... [2018-11-10 05:48:22,135 INFO L440 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2018-11-10 05:48:22,135 INFO L517 LassoAnalysis]: Proved termination. [2018-11-10 05:48:22,136 INFO L519 LassoAnalysis]: Termination argument consisting of: Ranking function f(~E_3~0) = -1*~E_3~0 + 1 Supporting invariants [] [2018-11-10 05:48:22,136 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2018-11-10 05:48:22,184 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:22,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:48:22,202 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 05:48:22,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:48:22,226 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 05:48:22,258 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:48:22,263 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2018-11-10 05:48:22,264 INFO L72 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 1050 states and 1358 transitions. cyclomatic complexity: 312 Second operand 5 states. [2018-11-10 05:48:22,367 INFO L76 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 1050 states and 1358 transitions. cyclomatic complexity: 312. Second operand 5 states. Result 2796 states and 3643 transitions. Complement of second has 5 states. [2018-11-10 05:48:22,368 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2018-11-10 05:48:22,368 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. [2018-11-10 05:48:22,369 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 359 transitions. [2018-11-10 05:48:22,370 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 359 transitions. Stem has 49 letters. Loop has 67 letters. [2018-11-10 05:48:22,372 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-10 05:48:22,372 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 359 transitions. Stem has 116 letters. Loop has 67 letters. [2018-11-10 05:48:22,373 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-10 05:48:22,373 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 359 transitions. Stem has 49 letters. Loop has 134 letters. [2018-11-10 05:48:22,375 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-10 05:48:22,375 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2796 states and 3643 transitions. [2018-11-10 05:48:22,384 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1844 [2018-11-10 05:48:22,392 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2796 states to 2792 states and 3639 transitions. [2018-11-10 05:48:22,392 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1911 [2018-11-10 05:48:22,393 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1924 [2018-11-10 05:48:22,393 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2792 states and 3639 transitions. [2018-11-10 05:48:22,394 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-10 05:48:22,394 INFO L705 BuchiCegarLoop]: Abstraction has 2792 states and 3639 transitions. [2018-11-10 05:48:22,396 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2792 states and 3639 transitions. [2018-11-10 05:48:22,422 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2792 to 2775. [2018-11-10 05:48:22,422 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2775 states. [2018-11-10 05:48:22,427 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2775 states to 2775 states and 3614 transitions. [2018-11-10 05:48:22,427 INFO L728 BuchiCegarLoop]: Abstraction has 2775 states and 3614 transitions. [2018-11-10 05:48:22,427 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 05:48:22,427 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 05:48:22,427 INFO L87 Difference]: Start difference. First operand 2775 states and 3614 transitions. Second operand 3 states. [2018-11-10 05:48:22,483 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:48:22,483 INFO L93 Difference]: Finished difference Result 4891 states and 6219 transitions. [2018-11-10 05:48:22,485 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 05:48:22,485 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4891 states and 6219 transitions. [2018-11-10 05:48:22,497 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3288 [2018-11-10 05:48:22,511 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4891 states to 4891 states and 6219 transitions. [2018-11-10 05:48:22,511 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3359 [2018-11-10 05:48:22,513 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3359 [2018-11-10 05:48:22,513 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4891 states and 6219 transitions. [2018-11-10 05:48:22,514 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-10 05:48:22,514 INFO L705 BuchiCegarLoop]: Abstraction has 4891 states and 6219 transitions. [2018-11-10 05:48:22,517 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4891 states and 6219 transitions. [2018-11-10 05:48:22,578 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4891 to 4555. [2018-11-10 05:48:22,578 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4555 states. [2018-11-10 05:48:22,588 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4555 states to 4555 states and 5835 transitions. [2018-11-10 05:48:22,588 INFO L728 BuchiCegarLoop]: Abstraction has 4555 states and 5835 transitions. [2018-11-10 05:48:22,588 INFO L608 BuchiCegarLoop]: Abstraction has 4555 states and 5835 transitions. [2018-11-10 05:48:22,588 INFO L442 BuchiCegarLoop]: ======== Iteration 17============ [2018-11-10 05:48:22,588 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4555 states and 5835 transitions. [2018-11-10 05:48:22,598 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3064 [2018-11-10 05:48:22,598 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:48:22,598 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:48:22,599 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:22,599 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:22,599 INFO L793 eck$LassoCheckResult]: Stem: 42088#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 41792#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 41793#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 42072#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42073#L271 assume ~m_i~0 == 1;~m_st~0 := 0; 42249#L271-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 42263#L276-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 42017#L281-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 42018#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 42071#L408 assume !(~M_E~0 == 0); 42301#L408-2 assume !(~T1_E~0 == 0); 41997#L413-1 assume !(~T2_E~0 == 0); 41998#L418-1 assume !(~T3_E~0 == 0); 42128#L423-1 assume !(~E_1~0 == 0); 41854#L428-1 assume !(~E_2~0 == 0); 41855#L433-1 assume !(~E_3~0 == 0); 41872#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 42053#L187 assume !(~m_pc~0 == 1); 42054#L187-2 is_master_triggered_~__retres1~0 := 0; 42110#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 42438#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 42175#L500 assume !(activate_threads_~tmp~1 != 0); 42176#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 42180#L206 assume !(~t1_pc~0 == 1); 42406#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 42407#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 41875#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 41876#L508 assume !(activate_threads_~tmp___0~0 != 0); 42244#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 42181#L225 assume !(~t2_pc~0 == 1); 42000#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 42177#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 42007#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 41842#L516 assume !(activate_threads_~tmp___1~0 != 0); 41843#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 41847#L244 assume !(~t3_pc~0 == 1); 42422#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 42225#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 42226#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 42283#L524 assume !(activate_threads_~tmp___2~0 != 0); 42284#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42117#L451 assume !(~M_E~0 == 1); 42118#L451-2 assume !(~T1_E~0 == 1); 42129#L456-1 assume !(~T2_E~0 == 1); 41848#L461-1 assume !(~T3_E~0 == 1); 41849#L466-1 assume !(~E_1~0 == 1); 41871#L471-1 assume !(~E_2~0 == 1); 42336#L476-1 assume !(~E_3~0 == 1); 42392#L481-1 assume { :end_inline_reset_delta_events } true; 42426#L642-3 assume true; 43069#L642-1 [2018-11-10 05:48:22,599 INFO L795 eck$LassoCheckResult]: Loop: 43069#L642-1 assume !false; 44626#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 44625#L383 assume true; 44624#L331-1 assume !false; 44623#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 44622#L299 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 44378#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 44621#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 44620#L336 assume eval_~tmp~0 != 0; 44619#L336-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 43781#L344 assume eval_~tmp_ndt_1~0 != 0;~m_st~0 := 1;assume { :begin_inline_master } true; 41808#L43 assume !(~m_pc~0 == 0); 41810#L46 assume ~m_pc~0 == 1; 42239#L47 assume true; 42311#L62-1 assume !false; 43788#L63 ~m_pc~0 := 1;~m_st~0 := 2; 43782#L73 assume { :end_inline_master } true; 43780#L341 assume !(~t1_st~0 == 0); 43731#L355 assume !(~t2_st~0 == 0); 44353#L369 assume !(~t3_st~0 == 0); 44381#L383 assume true; 44380#L331-1 assume !false; 44379#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 44377#L299 assume !(~m_st~0 == 0); 44375#L303 assume !(~t1_st~0 == 0); 44376#L307 assume !(~t2_st~0 == 0); 44373#L311 assume !(~t3_st~0 == 0);exists_runnable_thread_~__retres1~4 := 0; 44374#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 44736#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 44735#L336 assume !(eval_~tmp~0 != 0); 44734#L398 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 44733#L264-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 44731#L408-3 assume ~M_E~0 == 0;~M_E~0 := 1; 44728#L408-5 assume !(~T1_E~0 == 0); 44726#L413-3 assume !(~T2_E~0 == 0); 44724#L418-3 assume !(~T3_E~0 == 0); 44723#L423-3 assume ~E_1~0 == 0;~E_1~0 := 1; 44722#L428-3 assume !(~E_2~0 == 0); 44720#L433-3 assume !(~E_3~0 == 0); 44719#L438-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 44718#L187-12 assume ~m_pc~0 == 1; 44716#L188-4 assume ~M_E~0 == 1;is_master_triggered_~__retres1~0 := 1; 44715#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 44714#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 44710#L500-12 assume activate_threads_~tmp~1 != 0;~m_st~0 := 0; 44708#L500-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 44706#L206-12 assume !(~t1_pc~0 == 1); 44704#L206-14 is_transmit1_triggered_~__retres1~1 := 0; 44700#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 44698#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 44696#L508-12 assume !(activate_threads_~tmp___0~0 != 0); 44694#L508-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 44692#L225-12 assume !(~t2_pc~0 == 1); 44689#L225-14 is_transmit2_triggered_~__retres1~2 := 0; 44687#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 44685#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 44682#L516-12 assume !(activate_threads_~tmp___1~0 != 0); 44680#L516-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 44678#L244-12 assume !(~t3_pc~0 == 1); 44676#L244-14 is_transmit3_triggered_~__retres1~3 := 0; 44674#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 44672#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 44670#L524-12 assume !(activate_threads_~tmp___2~0 != 0); 44668#L524-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44666#L451-3 assume ~M_E~0 == 1;~M_E~0 := 2; 44664#L451-5 assume ~T1_E~0 == 1;~T1_E~0 := 2; 44662#L456-3 assume !(~T2_E~0 == 1); 44660#L461-3 assume !(~T3_E~0 == 1); 44658#L466-3 assume ~E_1~0 == 1;~E_1~0 := 2; 44656#L471-3 assume !(~E_2~0 == 1); 44654#L476-3 assume !(~E_3~0 == 1); 44650#L481-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 44648#L299-1 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 44418#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 44647#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 44645#L661 assume !(start_simulation_~tmp~3 == 0); 44643#L661-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 44642#L299-2 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 44403#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 44641#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 44640#L616 assume stop_simulation_~tmp~2 != 0;stop_simulation_~__retres2~0 := 0; 44639#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 44638#L624 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 44637#L674 assume !(start_simulation_~tmp___0~1 != 0); 44635#L642-3 assume true; 43069#L642-1 [2018-11-10 05:48:22,600 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:22,600 INFO L82 PathProgramCache]: Analyzing trace with hash -1276375257, now seen corresponding path program 1 times [2018-11-10 05:48:22,600 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:22,600 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:22,600 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:22,600 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:48:22,601 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:22,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:48:22,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:48:22,611 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:22,612 INFO L82 PathProgramCache]: Analyzing trace with hash -1047158819, now seen corresponding path program 1 times [2018-11-10 05:48:22,612 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:22,612 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:22,612 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:22,612 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:48:22,612 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:22,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:48:22,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:48:22,630 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:22,630 INFO L82 PathProgramCache]: Analyzing trace with hash 570479735, now seen corresponding path program 1 times [2018-11-10 05:48:22,630 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:22,630 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:22,631 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:22,631 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:48:22,631 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:22,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:48:22,671 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:48:22,672 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:48:22,672 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 05:48:22,990 WARN L179 SmtUtils]: Spent 312.00 ms on a formula simplification. DAG size of input: 155 DAG size of output: 136 [2018-11-10 05:48:23,072 INFO L214 LassoAnalysis]: Preferences: [2018-11-10 05:48:23,072 INFO L124 ssoRankerPreferences]: Compute integeral hull: false [2018-11-10 05:48:23,072 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true [2018-11-10 05:48:23,072 INFO L126 ssoRankerPreferences]: Term annotations enabled: false [2018-11-10 05:48:23,072 INFO L127 ssoRankerPreferences]: Use exernal solver: true [2018-11-10 05:48:23,072 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-10 05:48:23,072 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false [2018-11-10 05:48:23,072 INFO L130 ssoRankerPreferences]: Path of dumped script: [2018-11-10 05:48:23,073 INFO L131 ssoRankerPreferences]: Filename of dumped script: transmitter.03_false-unreach-call_false-termination.cil.c_Iteration17_Loop [2018-11-10 05:48:23,073 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank [2018-11-10 05:48:23,073 INFO L280 LassoAnalysis]: Starting lasso preprocessing... [2018-11-10 05:48:23,074 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,075 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,080 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,082 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,084 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,085 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,086 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,087 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,088 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,090 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,092 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,094 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,095 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,098 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,100 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,103 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,106 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,107 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,108 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,109 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,110 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,111 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,112 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,114 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,117 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,118 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,120 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,121 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,124 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,126 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,129 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,132 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,133 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,134 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,136 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,140 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,141 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,169 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,174 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,177 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,181 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,185 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,415 INFO L298 LassoAnalysis]: Preprocessing complete. [2018-11-10 05:48:23,415 INFO L410 LassoAnalysis]: Checking for nontermination... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_336a3a10-29f9-4018-bc2b-dd0bc6bf9d7c/bin-2019/uautomizer/z3 Starting monitored process 14 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-10 05:48:23,419 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-10 05:48:23,419 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-10 05:48:23,425 INFO L443 LassoAnalysis]: Proved nontermination for one component. [2018-11-10 05:48:23,425 INFO L446 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_#t~ret11=0} Honda state: {ULTIMATE.start_start_simulation_#t~ret11=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_336a3a10-29f9-4018-bc2b-dd0bc6bf9d7c/bin-2019/uautomizer/z3 Starting monitored process 15 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-10 05:48:23,442 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-10 05:48:23,442 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-10 05:48:23,445 INFO L443 LassoAnalysis]: Proved nontermination for one component. [2018-11-10 05:48:23,445 INFO L446 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~E_3~0=7} Honda state: {~E_3~0=7} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_336a3a10-29f9-4018-bc2b-dd0bc6bf9d7c/bin-2019/uautomizer/z3 Starting monitored process 16 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-10 05:48:23,463 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-10 05:48:23,463 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-10 05:48:23,465 INFO L443 LassoAnalysis]: Proved nontermination for one component. [2018-11-10 05:48:23,465 INFO L446 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t2_st~0=7} Honda state: {~t2_st~0=7} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_336a3a10-29f9-4018-bc2b-dd0bc6bf9d7c/bin-2019/uautomizer/z3 Starting monitored process 17 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-10 05:48:23,484 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-10 05:48:23,484 INFO L163 nArgumentSynthesizer]: Using integer mode. No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_336a3a10-29f9-4018-bc2b-dd0bc6bf9d7c/bin-2019/uautomizer/z3 Starting monitored process 18 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-10 05:48:23,504 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2018-11-10 05:48:23,505 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-10 05:48:23,508 INFO L450 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2018-11-10 05:48:23,525 INFO L214 LassoAnalysis]: Preferences: [2018-11-10 05:48:23,525 INFO L124 ssoRankerPreferences]: Compute integeral hull: false [2018-11-10 05:48:23,525 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true [2018-11-10 05:48:23,525 INFO L126 ssoRankerPreferences]: Term annotations enabled: false [2018-11-10 05:48:23,525 INFO L127 ssoRankerPreferences]: Use exernal solver: false [2018-11-10 05:48:23,525 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-10 05:48:23,525 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false [2018-11-10 05:48:23,526 INFO L130 ssoRankerPreferences]: Path of dumped script: [2018-11-10 05:48:23,526 INFO L131 ssoRankerPreferences]: Filename of dumped script: transmitter.03_false-unreach-call_false-termination.cil.c_Iteration17_Loop [2018-11-10 05:48:23,526 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank [2018-11-10 05:48:23,526 INFO L280 LassoAnalysis]: Starting lasso preprocessing... [2018-11-10 05:48:23,528 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,537 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,540 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,544 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,553 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,565 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,566 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,568 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,569 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,570 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,572 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,575 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,577 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,579 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,580 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,581 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,584 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,584 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,588 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,589 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,589 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,590 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,591 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,592 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,594 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,597 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,598 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,601 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,605 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,608 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,609 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,613 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,614 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,615 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,617 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,620 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,622 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,623 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,627 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,630 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,631 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,632 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-10 05:48:23,841 INFO L298 LassoAnalysis]: Preprocessing complete. [2018-11-10 05:48:23,841 INFO L496 LassoAnalysis]: Using template 'affine'. [2018-11-10 05:48:23,842 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-10 05:48:23,842 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-10 05:48:23,842 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-10 05:48:23,842 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-10 05:48:23,842 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-10 05:48:23,842 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-10 05:48:23,843 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-10 05:48:23,843 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-10 05:48:23,843 INFO L529 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-10 05:48:23,843 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-10 05:48:23,844 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-10 05:48:23,844 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-10 05:48:23,844 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-10 05:48:23,844 INFO L206 nArgumentSynthesizer]: 2 loop disjuncts [2018-11-10 05:48:23,844 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-10 05:48:23,844 INFO L402 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2018-11-10 05:48:23,844 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-10 05:48:23,844 INFO L529 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-10 05:48:23,845 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-10 05:48:23,845 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-10 05:48:23,845 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-10 05:48:23,845 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-10 05:48:23,845 INFO L206 nArgumentSynthesizer]: 2 loop disjuncts [2018-11-10 05:48:23,845 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-10 05:48:23,846 INFO L402 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2018-11-10 05:48:23,846 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-10 05:48:23,846 INFO L529 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-10 05:48:23,847 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-10 05:48:23,847 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-10 05:48:23,847 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-10 05:48:23,847 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-10 05:48:23,847 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-10 05:48:23,847 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-10 05:48:23,848 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-10 05:48:23,848 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-10 05:48:23,848 INFO L529 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-10 05:48:23,848 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-10 05:48:23,849 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-10 05:48:23,849 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-10 05:48:23,849 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-10 05:48:23,849 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-10 05:48:23,849 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-10 05:48:23,849 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-10 05:48:23,849 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-10 05:48:23,851 INFO L421 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2018-11-10 05:48:23,852 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2018-11-10 05:48:23,852 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2018-11-10 05:48:23,852 INFO L437 nArgumentSynthesizer]: Simplifying supporting invariants... [2018-11-10 05:48:23,852 INFO L440 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2018-11-10 05:48:23,853 INFO L517 LassoAnalysis]: Proved termination. [2018-11-10 05:48:23,853 INFO L519 LassoAnalysis]: Termination argument consisting of: Ranking function f(~T1_E~0) = -2*~T1_E~0 + 3 Supporting invariants [] [2018-11-10 05:48:23,853 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2018-11-10 05:48:23,903 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:23,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:48:23,918 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 05:48:23,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:48:23,933 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-10 05:48:23,968 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-11-10 05:48:23,969 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2018-11-10 05:48:23,969 INFO L72 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 4555 states and 5835 transitions. cyclomatic complexity: 1292 Second operand 4 states. [2018-11-10 05:48:24,047 INFO L76 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 4555 states and 5835 transitions. cyclomatic complexity: 1292. Second operand 4 states. Result 9178 states and 11734 transitions. Complement of second has 4 states. [2018-11-10 05:48:24,048 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2018-11-10 05:48:24,048 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2018-11-10 05:48:24,048 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 400 transitions. [2018-11-10 05:48:24,048 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 400 transitions. Stem has 50 letters. Loop has 85 letters. [2018-11-10 05:48:24,049 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-10 05:48:24,049 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 400 transitions. Stem has 135 letters. Loop has 85 letters. [2018-11-10 05:48:24,049 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-10 05:48:24,049 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 400 transitions. Stem has 50 letters. Loop has 170 letters. [2018-11-10 05:48:24,050 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-10 05:48:24,050 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9178 states and 11734 transitions. [2018-11-10 05:48:24,069 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3064 [2018-11-10 05:48:24,086 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9178 states to 9178 states and 11734 transitions. [2018-11-10 05:48:24,086 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3156 [2018-11-10 05:48:24,088 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3197 [2018-11-10 05:48:24,088 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9178 states and 11734 transitions. [2018-11-10 05:48:24,088 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-10 05:48:24,088 INFO L705 BuchiCegarLoop]: Abstraction has 9178 states and 11734 transitions. [2018-11-10 05:48:24,093 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9178 states and 11734 transitions. [2018-11-10 05:48:24,148 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9178 to 9137. [2018-11-10 05:48:24,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9137 states. [2018-11-10 05:48:24,158 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9137 states to 9137 states and 11693 transitions. [2018-11-10 05:48:24,158 INFO L728 BuchiCegarLoop]: Abstraction has 9137 states and 11693 transitions. [2018-11-10 05:48:24,158 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 05:48:24,158 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 05:48:24,158 INFO L87 Difference]: Start difference. First operand 9137 states and 11693 transitions. Second operand 3 states. [2018-11-10 05:48:24,211 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:48:24,211 INFO L93 Difference]: Finished difference Result 11377 states and 14392 transitions. [2018-11-10 05:48:24,212 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 05:48:24,212 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11377 states and 14392 transitions. [2018-11-10 05:48:24,234 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 3836 [2018-11-10 05:48:24,254 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11377 states to 11377 states and 14392 transitions. [2018-11-10 05:48:24,254 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3941 [2018-11-10 05:48:24,257 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3941 [2018-11-10 05:48:24,257 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11377 states and 14392 transitions. [2018-11-10 05:48:24,258 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-10 05:48:24,259 INFO L705 BuchiCegarLoop]: Abstraction has 11377 states and 14392 transitions. [2018-11-10 05:48:24,264 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11377 states and 14392 transitions. [2018-11-10 05:48:24,323 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11377 to 10609. [2018-11-10 05:48:24,323 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10609 states. [2018-11-10 05:48:24,334 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10609 states to 10609 states and 13528 transitions. [2018-11-10 05:48:24,334 INFO L728 BuchiCegarLoop]: Abstraction has 10609 states and 13528 transitions. [2018-11-10 05:48:24,334 INFO L608 BuchiCegarLoop]: Abstraction has 10609 states and 13528 transitions. [2018-11-10 05:48:24,334 INFO L442 BuchiCegarLoop]: ======== Iteration 18============ [2018-11-10 05:48:24,334 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10609 states and 13528 transitions. [2018-11-10 05:48:24,349 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 3580 [2018-11-10 05:48:24,349 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:48:24,349 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:48:24,349 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:24,349 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:24,350 INFO L793 eck$LassoCheckResult]: Stem: 76773#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 76468#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 76469#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 76759#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 76760#L271 assume ~m_i~0 == 1;~m_st~0 := 0; 76945#L271-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 76960#L276-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 76703#L281-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 76704#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 76758#L408 assume !(~M_E~0 == 0); 77004#L408-2 assume !(~T1_E~0 == 0); 76684#L413-1 assume !(~T2_E~0 == 0); 76685#L418-1 assume !(~T3_E~0 == 0); 76806#L423-1 assume !(~E_1~0 == 0); 76528#L428-1 assume !(~E_2~0 == 0); 76529#L433-1 assume !(~E_3~0 == 0); 76543#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 76741#L187 assume !(~m_pc~0 == 1); 76742#L187-2 is_master_triggered_~__retres1~0 := 0; 76743#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 76744#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 76862#L500 assume !(activate_threads_~tmp~1 != 0); 76863#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 76868#L206 assume !(~t1_pc~0 == 1); 77125#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 77126#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 76548#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 76549#L508 assume !(activate_threads_~tmp___0~0 != 0); 76936#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 76869#L225 assume !(~t2_pc~0 == 1); 76690#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 76864#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 76702#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 76518#L516 assume !(activate_threads_~tmp___1~0 != 0); 76519#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 76521#L244 assume !(~t3_pc~0 == 1); 77144#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 76915#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 76916#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 76972#L524 assume !(activate_threads_~tmp___2~0 != 0); 76973#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76796#L451 assume !(~M_E~0 == 1); 76797#L451-2 assume !(~T1_E~0 == 1); 76807#L456-1 assume !(~T2_E~0 == 1); 76522#L461-1 assume !(~T3_E~0 == 1); 76523#L466-1 assume !(~E_1~0 == 1); 76542#L471-1 assume !(~E_2~0 == 1); 77046#L476-1 assume !(~E_3~0 == 1); 77103#L481-1 assume { :end_inline_reset_delta_events } true; 77149#L642-3 assume true; 77614#L642-1 assume !false; 77613#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 77516#L383 [2018-11-10 05:48:24,350 INFO L795 eck$LassoCheckResult]: Loop: 77516#L383 assume true; 77612#L331-1 assume !false; 80418#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 80416#L299 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 77607#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 77606#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 77575#L336 assume eval_~tmp~0 != 0; 77576#L336-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 80398#L344 assume !(eval_~tmp_ndt_1~0 != 0); 77561#L341 assume !(~t1_st~0 == 0); 77554#L355 assume !(~t2_st~0 == 0); 77525#L369 assume !(~t3_st~0 == 0); 77516#L383 [2018-11-10 05:48:24,350 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:24,350 INFO L82 PathProgramCache]: Analyzing trace with hash 1764031817, now seen corresponding path program 1 times [2018-11-10 05:48:24,350 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:24,350 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:24,351 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:24,351 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:48:24,351 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:24,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:48:24,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:48:24,360 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:24,361 INFO L82 PathProgramCache]: Analyzing trace with hash -2144534838, now seen corresponding path program 1 times [2018-11-10 05:48:24,361 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:24,361 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:24,361 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:24,361 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:48:24,362 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:24,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:48:24,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:48:24,365 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:24,365 INFO L82 PathProgramCache]: Analyzing trace with hash -443002862, now seen corresponding path program 1 times [2018-11-10 05:48:24,365 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:24,365 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:24,365 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:24,366 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:48:24,366 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:24,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:48:24,406 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:48:24,406 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:48:24,407 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 05:48:24,435 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 05:48:24,436 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 05:48:24,436 INFO L87 Difference]: Start difference. First operand 10609 states and 13528 transitions. cyclomatic complexity: 2967 Second operand 3 states. [2018-11-10 05:48:24,475 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:48:24,475 INFO L93 Difference]: Finished difference Result 18344 states and 23023 transitions. [2018-11-10 05:48:24,477 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 05:48:24,477 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18344 states and 23023 transitions. [2018-11-10 05:48:24,512 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 5860 [2018-11-10 05:48:24,541 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18344 states to 18344 states and 23023 transitions. [2018-11-10 05:48:24,541 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6416 [2018-11-10 05:48:24,545 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6416 [2018-11-10 05:48:24,545 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18344 states and 23023 transitions. [2018-11-10 05:48:24,545 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-10 05:48:24,546 INFO L705 BuchiCegarLoop]: Abstraction has 18344 states and 23023 transitions. [2018-11-10 05:48:24,555 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18344 states and 23023 transitions. [2018-11-10 05:48:24,643 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18344 to 17516. [2018-11-10 05:48:24,643 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17516 states. [2018-11-10 05:48:24,660 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17516 states to 17516 states and 22069 transitions. [2018-11-10 05:48:24,661 INFO L728 BuchiCegarLoop]: Abstraction has 17516 states and 22069 transitions. [2018-11-10 05:48:24,661 INFO L608 BuchiCegarLoop]: Abstraction has 17516 states and 22069 transitions. [2018-11-10 05:48:24,661 INFO L442 BuchiCegarLoop]: ======== Iteration 19============ [2018-11-10 05:48:24,661 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17516 states and 22069 transitions. [2018-11-10 05:48:24,684 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 5584 [2018-11-10 05:48:24,685 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:48:24,685 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:48:24,685 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:24,685 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:24,685 INFO L793 eck$LassoCheckResult]: Stem: 105733#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 105428#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 105429#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 105719#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 105720#L271 assume ~m_i~0 == 1;~m_st~0 := 0; 105907#L271-2 assume !(~t1_i~0 == 1);~t1_st~0 := 2; 105924#L276-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 105663#L281-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 105664#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 105718#L408 assume !(~M_E~0 == 0); 105968#L408-2 assume !(~T1_E~0 == 0); 105640#L413-1 assume !(~T2_E~0 == 0); 105641#L418-1 assume !(~T3_E~0 == 0); 105769#L423-1 assume !(~E_1~0 == 0); 105486#L428-1 assume !(~E_2~0 == 0); 105487#L433-1 assume !(~E_3~0 == 0); 105501#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 105701#L187 assume !(~m_pc~0 == 1); 105702#L187-2 is_master_triggered_~__retres1~0 := 0; 105703#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 105704#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 105825#L500 assume !(activate_threads_~tmp~1 != 0); 105826#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 105832#L206 assume !(~t1_pc~0 == 1); 106072#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 106073#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 105504#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 105505#L508 assume !(activate_threads_~tmp___0~0 != 0); 105896#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 105903#L225 assume !(~t2_pc~0 == 1); 109855#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 109854#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 109853#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 109852#L516 assume !(activate_threads_~tmp___1~0 != 0); 109851#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 109850#L244 assume !(~t3_pc~0 == 1); 109849#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 109848#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 109847#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 109846#L524 assume !(activate_threads_~tmp___2~0 != 0); 109845#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 109844#L451 assume !(~M_E~0 == 1); 109843#L451-2 assume !(~T1_E~0 == 1); 109842#L456-1 assume !(~T2_E~0 == 1); 109841#L461-1 assume !(~T3_E~0 == 1); 109840#L466-1 assume !(~E_1~0 == 1); 109839#L471-1 assume !(~E_2~0 == 1); 109838#L476-1 assume !(~E_3~0 == 1); 109836#L481-1 assume { :end_inline_reset_delta_events } true; 109833#L642-3 assume true; 109830#L642-1 assume !false; 109254#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 109252#L383 [2018-11-10 05:48:24,685 INFO L795 eck$LassoCheckResult]: Loop: 109252#L383 assume true; 109250#L331-1 assume !false; 109248#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 109246#L299 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 109244#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 109242#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 109240#L336 assume eval_~tmp~0 != 0; 109237#L336-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 109234#L344 assume !(eval_~tmp_ndt_1~0 != 0); 109231#L341 assume !(~t1_st~0 == 0); 109229#L355 assume !(~t2_st~0 == 0); 109227#L369 assume !(~t3_st~0 == 0); 109252#L383 [2018-11-10 05:48:24,686 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:24,686 INFO L82 PathProgramCache]: Analyzing trace with hash 1410943435, now seen corresponding path program 1 times [2018-11-10 05:48:24,686 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:24,686 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:24,686 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:24,686 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:48:24,687 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:24,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:48:24,706 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:48:24,706 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:48:24,706 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 05:48:24,707 INFO L798 eck$LassoCheckResult]: stem already infeasible [2018-11-10 05:48:24,707 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:24,707 INFO L82 PathProgramCache]: Analyzing trace with hash -2144534838, now seen corresponding path program 2 times [2018-11-10 05:48:24,707 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:24,707 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:24,707 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:24,707 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:48:24,708 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:24,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:48:24,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:48:24,747 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 05:48:24,747 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 05:48:24,747 INFO L87 Difference]: Start difference. First operand 17516 states and 22069 transitions. cyclomatic complexity: 4625 Second operand 3 states. [2018-11-10 05:48:24,764 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:48:24,764 INFO L93 Difference]: Finished difference Result 12033 states and 15255 transitions. [2018-11-10 05:48:24,764 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 05:48:24,764 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12033 states and 15255 transitions. [2018-11-10 05:48:24,786 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4126 [2018-11-10 05:48:24,804 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12033 states to 12033 states and 15255 transitions. [2018-11-10 05:48:24,804 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4233 [2018-11-10 05:48:24,806 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4233 [2018-11-10 05:48:24,806 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12033 states and 15255 transitions. [2018-11-10 05:48:24,807 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-10 05:48:24,807 INFO L705 BuchiCegarLoop]: Abstraction has 12033 states and 15255 transitions. [2018-11-10 05:48:24,812 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12033 states and 15255 transitions. [2018-11-10 05:48:24,860 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12033 to 12033. [2018-11-10 05:48:24,860 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12033 states. [2018-11-10 05:48:24,871 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12033 states to 12033 states and 15255 transitions. [2018-11-10 05:48:24,871 INFO L728 BuchiCegarLoop]: Abstraction has 12033 states and 15255 transitions. [2018-11-10 05:48:24,871 INFO L608 BuchiCegarLoop]: Abstraction has 12033 states and 15255 transitions. [2018-11-10 05:48:24,871 INFO L442 BuchiCegarLoop]: ======== Iteration 20============ [2018-11-10 05:48:24,871 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12033 states and 15255 transitions. [2018-11-10 05:48:24,886 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4126 [2018-11-10 05:48:24,887 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:48:24,887 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:48:24,887 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:24,887 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:24,887 INFO L793 eck$LassoCheckResult]: Stem: 135290#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 134983#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 134984#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 135277#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 135278#L271 assume ~m_i~0 == 1;~m_st~0 := 0; 135451#L271-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 135467#L276-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 135221#L281-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 135222#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 135276#L408 assume !(~M_E~0 == 0); 135502#L408-2 assume !(~T1_E~0 == 0); 135199#L413-1 assume !(~T2_E~0 == 0); 135200#L418-1 assume !(~T3_E~0 == 0); 135323#L423-1 assume !(~E_1~0 == 0); 135041#L428-1 assume !(~E_2~0 == 0); 135042#L433-1 assume !(~E_3~0 == 0); 135057#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 135260#L187 assume !(~m_pc~0 == 1); 135261#L187-2 is_master_triggered_~__retres1~0 := 0; 135262#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 135263#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 135376#L500 assume !(activate_threads_~tmp~1 != 0); 135377#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 135382#L206 assume !(~t1_pc~0 == 1); 135602#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 135603#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 135060#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 135061#L508 assume !(activate_threads_~tmp___0~0 != 0); 135443#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 135383#L225 assume !(~t2_pc~0 == 1); 135202#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 135378#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 135214#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 135031#L516 assume !(activate_threads_~tmp___1~0 != 0); 135032#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 135034#L244 assume !(~t3_pc~0 == 1); 135616#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 135425#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 135426#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 135484#L524 assume !(activate_threads_~tmp___2~0 != 0); 135485#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 135313#L451 assume !(~M_E~0 == 1); 135314#L451-2 assume !(~T1_E~0 == 1); 135324#L456-1 assume !(~T2_E~0 == 1); 135035#L461-1 assume !(~T3_E~0 == 1); 135036#L466-1 assume !(~E_1~0 == 1); 135056#L471-1 assume !(~E_2~0 == 1); 135536#L476-1 assume !(~E_3~0 == 1); 135584#L481-1 assume { :end_inline_reset_delta_events } true; 135619#L642-3 assume true; 137187#L642-1 assume !false; 137188#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 144015#L383 [2018-11-10 05:48:24,887 INFO L795 eck$LassoCheckResult]: Loop: 144015#L383 assume true; 144014#L331-1 assume !false; 144012#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 144010#L299 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 144008#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 144006#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 144004#L336 assume eval_~tmp~0 != 0; 144002#L336-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 143998#L344 assume !(eval_~tmp_ndt_1~0 != 0); 143999#L341 assume ~t1_st~0 == 0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 144025#L358 assume !(eval_~tmp_ndt_2~0 != 0); 144020#L355 assume !(~t2_st~0 == 0); 144018#L369 assume !(~t3_st~0 == 0); 144015#L383 [2018-11-10 05:48:24,888 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:24,888 INFO L82 PathProgramCache]: Analyzing trace with hash 1764031817, now seen corresponding path program 2 times [2018-11-10 05:48:24,888 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:24,888 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:24,888 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:24,888 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 05:48:24,889 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:24,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:48:24,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:48:24,898 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:24,898 INFO L82 PathProgramCache]: Analyzing trace with hash -2060137191, now seen corresponding path program 1 times [2018-11-10 05:48:24,898 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:24,898 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:24,898 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:24,898 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 05:48:24,899 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:24,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:48:24,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:48:24,902 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:24,902 INFO L82 PathProgramCache]: Analyzing trace with hash -852253487, now seen corresponding path program 1 times [2018-11-10 05:48:24,902 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:24,902 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:24,903 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:24,903 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:48:24,903 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:24,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:48:24,935 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:48:24,935 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:48:24,935 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-10 05:48:24,988 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 05:48:24,988 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 05:48:24,988 INFO L87 Difference]: Start difference. First operand 12033 states and 15255 transitions. cyclomatic complexity: 3270 Second operand 3 states. [2018-11-10 05:48:25,034 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:48:25,034 INFO L93 Difference]: Finished difference Result 19437 states and 24417 transitions. [2018-11-10 05:48:25,035 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 05:48:25,035 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19437 states and 24417 transitions. [2018-11-10 05:48:25,084 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6542 [2018-11-10 05:48:25,134 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19437 states to 19437 states and 24417 transitions. [2018-11-10 05:48:25,134 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6693 [2018-11-10 05:48:25,139 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6693 [2018-11-10 05:48:25,140 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19437 states and 24417 transitions. [2018-11-10 05:48:25,140 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-10 05:48:25,140 INFO L705 BuchiCegarLoop]: Abstraction has 19437 states and 24417 transitions. [2018-11-10 05:48:25,152 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19437 states and 24417 transitions. [2018-11-10 05:48:25,282 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19437 to 19437. [2018-11-10 05:48:25,282 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19437 states. [2018-11-10 05:48:25,297 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19437 states to 19437 states and 24417 transitions. [2018-11-10 05:48:25,297 INFO L728 BuchiCegarLoop]: Abstraction has 19437 states and 24417 transitions. [2018-11-10 05:48:25,297 INFO L608 BuchiCegarLoop]: Abstraction has 19437 states and 24417 transitions. [2018-11-10 05:48:25,297 INFO L442 BuchiCegarLoop]: ======== Iteration 21============ [2018-11-10 05:48:25,297 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19437 states and 24417 transitions. [2018-11-10 05:48:25,319 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6542 [2018-11-10 05:48:25,320 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:48:25,320 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:48:25,320 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:25,320 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:25,320 INFO L793 eck$LassoCheckResult]: Stem: 166767#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 166461#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 166462#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 166753#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 166754#L271 assume ~m_i~0 == 1;~m_st~0 := 0; 166930#L271-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 166948#L276-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 166696#L281-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 166697#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 166752#L408 assume !(~M_E~0 == 0); 166986#L408-2 assume !(~T1_E~0 == 0); 166672#L413-1 assume !(~T2_E~0 == 0); 166673#L418-1 assume !(~T3_E~0 == 0); 166800#L423-1 assume !(~E_1~0 == 0); 166516#L428-1 assume !(~E_2~0 == 0); 166517#L433-1 assume !(~E_3~0 == 0); 166531#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 166736#L187 assume !(~m_pc~0 == 1); 166737#L187-2 is_master_triggered_~__retres1~0 := 0; 166738#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 166739#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 166854#L500 assume !(activate_threads_~tmp~1 != 0); 166855#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 166862#L206 assume !(~t1_pc~0 == 1); 167098#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 167099#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 166534#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 166535#L508 assume !(activate_threads_~tmp___0~0 != 0); 166921#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 166863#L225 assume !(~t2_pc~0 == 1); 166675#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 166856#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 166685#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 166506#L516 assume !(activate_threads_~tmp___1~0 != 0); 166507#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 166509#L244 assume !(~t3_pc~0 == 1); 167114#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 166906#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 166907#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 166966#L524 assume !(activate_threads_~tmp___2~0 != 0); 166967#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 166790#L451 assume !(~M_E~0 == 1); 166791#L451-2 assume !(~T1_E~0 == 1); 166801#L456-1 assume !(~T2_E~0 == 1); 166510#L461-1 assume !(~T3_E~0 == 1); 166511#L466-1 assume !(~E_1~0 == 1); 166530#L471-1 assume !(~E_2~0 == 1); 167023#L476-1 assume !(~E_3~0 == 1); 167082#L481-1 assume { :end_inline_reset_delta_events } true; 167118#L642-3 assume true; 172397#L642-1 assume !false; 172398#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 179701#L383 [2018-11-10 05:48:25,321 INFO L795 eck$LassoCheckResult]: Loop: 179701#L383 assume true; 179699#L331-1 assume !false; 179652#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 179638#L299 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 179634#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 179629#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 179622#L336 assume eval_~tmp~0 != 0; 179616#L336-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 179610#L344 assume !(eval_~tmp_ndt_1~0 != 0); 179606#L341 assume ~t1_st~0 == 0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 179601#L358 assume !(eval_~tmp_ndt_2~0 != 0); 179599#L355 assume ~t2_st~0 == 0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 178936#L372 assume !(eval_~tmp_ndt_3~0 != 0); 179249#L369 assume !(~t3_st~0 == 0); 179701#L383 [2018-11-10 05:48:25,321 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:25,321 INFO L82 PathProgramCache]: Analyzing trace with hash 1764031817, now seen corresponding path program 3 times [2018-11-10 05:48:25,321 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:25,321 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:25,322 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:25,322 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:48:25,322 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:25,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:48:25,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:48:25,331 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:25,331 INFO L82 PathProgramCache]: Analyzing trace with hash 560128912, now seen corresponding path program 1 times [2018-11-10 05:48:25,331 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:25,331 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:25,332 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:25,332 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 05:48:25,332 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:25,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:48:25,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:48:25,335 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:25,336 INFO L82 PathProgramCache]: Analyzing trace with hash -650181928, now seen corresponding path program 1 times [2018-11-10 05:48:25,336 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:25,336 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:25,336 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:25,336 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:48:25,336 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:25,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 05:48:25,376 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 05:48:25,376 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-10 05:48:25,376 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-10 05:48:25,425 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-10 05:48:25,425 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-10 05:48:25,425 INFO L87 Difference]: Start difference. First operand 19437 states and 24417 transitions. cyclomatic complexity: 5028 Second operand 3 states. [2018-11-10 05:48:25,472 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-10 05:48:25,472 INFO L93 Difference]: Finished difference Result 24999 states and 31358 transitions. [2018-11-10 05:48:25,474 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-10 05:48:25,474 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24999 states and 31358 transitions. [2018-11-10 05:48:25,517 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8471 [2018-11-10 05:48:25,555 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24999 states to 24999 states and 31358 transitions. [2018-11-10 05:48:25,555 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8657 [2018-11-10 05:48:25,559 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8657 [2018-11-10 05:48:25,559 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24999 states and 31358 transitions. [2018-11-10 05:48:25,559 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-10 05:48:25,559 INFO L705 BuchiCegarLoop]: Abstraction has 24999 states and 31358 transitions. [2018-11-10 05:48:25,568 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24999 states and 31358 transitions. [2018-11-10 05:48:25,669 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24999 to 24999. [2018-11-10 05:48:25,669 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24999 states. [2018-11-10 05:48:25,689 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24999 states to 24999 states and 31358 transitions. [2018-11-10 05:48:25,689 INFO L728 BuchiCegarLoop]: Abstraction has 24999 states and 31358 transitions. [2018-11-10 05:48:25,689 INFO L608 BuchiCegarLoop]: Abstraction has 24999 states and 31358 transitions. [2018-11-10 05:48:25,689 INFO L442 BuchiCegarLoop]: ======== Iteration 22============ [2018-11-10 05:48:25,689 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24999 states and 31358 transitions. [2018-11-10 05:48:25,722 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8471 [2018-11-10 05:48:25,722 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-10 05:48:25,722 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-10 05:48:25,722 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:25,722 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-10 05:48:25,722 INFO L793 eck$LassoCheckResult]: Stem: 211205#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 210905#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 210906#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 211191#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 211192#L271 assume ~m_i~0 == 1;~m_st~0 := 0; 211368#L271-2 assume ~t1_i~0 == 1;~t1_st~0 := 0; 211388#L276-1 assume ~t2_i~0 == 1;~t2_st~0 := 0; 211133#L281-1 assume ~t3_i~0 == 1;~t3_st~0 := 0; 211134#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 211190#L408 assume !(~M_E~0 == 0); 211428#L408-2 assume !(~T1_E~0 == 0); 211111#L413-1 assume !(~T2_E~0 == 0); 211112#L418-1 assume !(~T3_E~0 == 0); 211236#L423-1 assume !(~E_1~0 == 0); 210959#L428-1 assume !(~E_2~0 == 0); 210960#L433-1 assume !(~E_3~0 == 0); 210973#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 211174#L187 assume !(~m_pc~0 == 1); 211175#L187-2 is_master_triggered_~__retres1~0 := 0; 211176#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 211177#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 211289#L500 assume !(activate_threads_~tmp~1 != 0); 211290#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 211294#L206 assume !(~t1_pc~0 == 1); 211547#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 211548#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 210976#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 210977#L508 assume !(activate_threads_~tmp___0~0 != 0); 211359#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 211295#L225 assume !(~t2_pc~0 == 1); 211118#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 211291#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 211132#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 210950#L516 assume !(activate_threads_~tmp___1~0 != 0); 210951#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 210952#L244 assume !(~t3_pc~0 == 1); 211572#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 211341#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 211342#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 211404#L524 assume !(activate_threads_~tmp___2~0 != 0); 211405#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 211226#L451 assume !(~M_E~0 == 1); 211227#L451-2 assume !(~T1_E~0 == 1); 211237#L456-1 assume !(~T2_E~0 == 1); 210953#L461-1 assume !(~T3_E~0 == 1); 210954#L466-1 assume !(~E_1~0 == 1); 210972#L471-1 assume !(~E_2~0 == 1); 211474#L476-1 assume !(~E_3~0 == 1); 211527#L481-1 assume { :end_inline_reset_delta_events } true; 211576#L642-3 assume true; 216132#L642-1 assume !false; 216133#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 217894#L383 [2018-11-10 05:48:25,723 INFO L795 eck$LassoCheckResult]: Loop: 217894#L383 assume true; 219599#L331-1 assume !false; 219598#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 219597#L299 assume ~m_st~0 == 0;exists_runnable_thread_~__retres1~4 := 1; 219596#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 219595#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 219594#L336 assume eval_~tmp~0 != 0; 219593#L336-1 assume ~m_st~0 == 0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 219591#L344 assume !(eval_~tmp_ndt_1~0 != 0); 219590#L341 assume ~t1_st~0 == 0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 219588#L358 assume !(eval_~tmp_ndt_2~0 != 0); 219568#L355 assume ~t2_st~0 == 0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 219566#L372 assume !(eval_~tmp_ndt_3~0 != 0); 219567#L369 assume ~t3_st~0 == 0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 219600#L386 assume !(eval_~tmp_ndt_4~0 != 0); 217894#L383 [2018-11-10 05:48:25,723 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:25,723 INFO L82 PathProgramCache]: Analyzing trace with hash 1764031817, now seen corresponding path program 4 times [2018-11-10 05:48:25,723 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:25,723 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:25,724 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:25,724 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:48:25,724 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:25,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:48:25,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:48:25,733 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:25,733 INFO L82 PathProgramCache]: Analyzing trace with hash 184126547, now seen corresponding path program 1 times [2018-11-10 05:48:25,733 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:25,733 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:25,734 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:25,734 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-10 05:48:25,734 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:25,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:48:25,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:48:25,737 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 05:48:25,738 INFO L82 PathProgramCache]: Analyzing trace with hash 1319196171, now seen corresponding path program 1 times [2018-11-10 05:48:25,738 INFO L225 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-10 05:48:25,738 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-10 05:48:25,738 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:25,738 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-10 05:48:25,738 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-10 05:48:25,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:48:25,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 05:48:25,992 WARN L179 SmtUtils]: Spent 167.00 ms on a formula simplification. DAG size of input: 126 DAG size of output: 86 [2018-11-10 05:48:26,048 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 10.11 05:48:26 BoogieIcfgContainer [2018-11-10 05:48:26,048 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2018-11-10 05:48:26,049 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-10 05:48:26,049 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-10 05:48:26,049 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-10 05:48:26,049 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.11 05:48:17" (3/4) ... [2018-11-10 05:48:26,052 INFO L141 WitnessPrinter]: Generating witness for non-termination counterexample [2018-11-10 05:48:26,098 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_336a3a10-29f9-4018-bc2b-dd0bc6bf9d7c/bin-2019/uautomizer/witness.graphml [2018-11-10 05:48:26,098 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-10 05:48:26,101 INFO L168 Benchmark]: Toolchain (without parser) took 9315.63 ms. Allocated memory was 1.0 GB in the beginning and 1.5 GB in the end (delta: 456.1 MB). Free memory was 959.1 MB in the beginning and 897.9 MB in the end (delta: 61.2 MB). Peak memory consumption was 517.3 MB. Max. memory is 11.5 GB. [2018-11-10 05:48:26,101 INFO L168 Benchmark]: CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-10 05:48:26,102 INFO L168 Benchmark]: CACSL2BoogieTranslator took 231.58 ms. Allocated memory is still 1.0 GB. Free memory was 959.1 MB in the beginning and 941.9 MB in the end (delta: 17.2 MB). Peak memory consumption was 17.2 MB. Max. memory is 11.5 GB. [2018-11-10 05:48:26,102 INFO L168 Benchmark]: Boogie Procedure Inliner took 37.34 ms. Allocated memory is still 1.0 GB. Free memory was 941.9 MB in the beginning and 939.3 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-11-10 05:48:26,102 INFO L168 Benchmark]: Boogie Preprocessor took 75.88 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 164.1 MB). Free memory was 939.3 MB in the beginning and 1.2 GB in the end (delta: -218.9 MB). Peak memory consumption was 18.8 MB. Max. memory is 11.5 GB. [2018-11-10 05:48:26,102 INFO L168 Benchmark]: RCFGBuilder took 630.80 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 70.9 MB). Peak memory consumption was 70.9 MB. Max. memory is 11.5 GB. [2018-11-10 05:48:26,103 INFO L168 Benchmark]: BuchiAutomizer took 8285.30 ms. Allocated memory was 1.2 GB in the beginning and 1.5 GB in the end (delta: 292.0 MB). Free memory was 1.1 GB in the beginning and 908.7 MB in the end (delta: 178.5 MB). Peak memory consumption was 470.6 MB. Max. memory is 11.5 GB. [2018-11-10 05:48:26,103 INFO L168 Benchmark]: Witness Printer took 49.76 ms. Allocated memory is still 1.5 GB. Free memory was 908.7 MB in the beginning and 897.9 MB in the end (delta: 10.8 MB). Peak memory consumption was 10.8 MB. Max. memory is 11.5 GB. [2018-11-10 05:48:26,105 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 231.58 ms. Allocated memory is still 1.0 GB. Free memory was 959.1 MB in the beginning and 941.9 MB in the end (delta: 17.2 MB). Peak memory consumption was 17.2 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 37.34 ms. Allocated memory is still 1.0 GB. Free memory was 941.9 MB in the beginning and 939.3 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 75.88 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 164.1 MB). Free memory was 939.3 MB in the beginning and 1.2 GB in the end (delta: -218.9 MB). Peak memory consumption was 18.8 MB. Max. memory is 11.5 GB. * RCFGBuilder took 630.80 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 70.9 MB). Peak memory consumption was 70.9 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 8285.30 ms. Allocated memory was 1.2 GB in the beginning and 1.5 GB in the end (delta: 292.0 MB). Free memory was 1.1 GB in the beginning and 908.7 MB in the end (delta: 178.5 MB). Peak memory consumption was 470.6 MB. Max. memory is 11.5 GB. * Witness Printer took 49.76 ms. Allocated memory is still 1.5 GB. Free memory was 908.7 MB in the beginning and 897.9 MB in the end (delta: 10.8 MB). Peak memory consumption was 10.8 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 23 terminating modules (21 trivial, 2 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function -1 * E_3 + 1 and consists of 3 locations. One deterministic module has affine ranking function -2 * T1_E + 3 and consists of 3 locations. 21 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 24999 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 8.2s and 22 iterations. TraceHistogramMax:2. Analysis of lassos took 4.6s. Construction of modules took 0.7s. Büchi inclusion checks took 0.9s. Highest rank in rank-based complementation 3. Minimization of det autom 15. Minimization of nondet autom 8. Automata minimization 0.9s AutomataMinimizationTime, 23 MinimizatonAttempts, 8259 StatesRemovedByMinimization, 14 NontrivialMinimizations. Non-live state removal took 0.5s Buchi closure took 0.0s. Biggest automaton had 24999 states and ocurred in iteration 21. Nontrivial modules had stage [2, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 7/7 HoareTripleCheckerStatistics: 10320 SDtfs, 11655 SDslu, 11716 SDs, 0 SdLazy, 581 SolverSat, 231 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.7s Time LassoAnalysisResults: nont1 unkn0 SFLI6 SFLT0 conc3 concLT2 SILN1 SILU0 SILI9 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital151 mio100 ax100 hnf100 lsp7 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq209 hnf86 smp100 dnf189 smp57 tf109 neg96 sie108 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 2ms VariablesStem: 0 VariablesLoop: 1 DisjunctsStem: 1 DisjunctsLoop: 2 SupportingInvariants: 0 MotzkinApplications: 4 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 13 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 2 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.1s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 331]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {__retres1=0, t3_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@76ccc1f1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@460cce05=0, tmp=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4b3bd57b=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@329061e8=0, __retres1=0, kernel_st=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@225b0249=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6d9678b6=0, t2_st=0, E_3=2, \result=0, E_1=2, tmp_ndt_2=0, \result=0, \result=0, tmp_ndt_4=0, m_st=0, tmp___2=0, tmp___0=0, t3_pc=0, tmp=0, __retres1=0, m_pc=0, \result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7179b7cf=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, E_2=2, T1_E=2, __retres1=1, tmp_ndt_1=0, M_E=2, tmp=0, tmp_ndt_3=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4f060c89=0, __retres1=0, t2_i=1, t3_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@54b04bd0=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@39f756e7=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@12a897d5=0, t1_st=0, t2_pc=0, tmp___1=0, T3_E=2, t1_i=1, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 331]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int m_st ; [L20] int t1_st ; [L21] int t2_st ; [L22] int t3_st ; [L23] int m_i ; [L24] int t1_i ; [L25] int t2_i ; [L26] int t3_i ; [L27] int M_E = 2; [L28] int T1_E = 2; [L29] int T2_E = 2; [L30] int T3_E = 2; [L31] int E_1 = 2; [L32] int E_2 = 2; [L33] int E_3 = 2; [L687] int __retres1 ; [L691] CALL init_model() [L600] m_i = 1 [L601] t1_i = 1 [L602] t2_i = 1 [L603] RET t3_i = 1 [L691] init_model() [L692] CALL start_simulation() [L628] int kernel_st ; [L629] int tmp ; [L630] int tmp___0 ; [L634] kernel_st = 0 [L635] FCALL update_channels() [L636] CALL init_threads() [L271] COND TRUE m_i == 1 [L272] m_st = 0 [L276] COND TRUE t1_i == 1 [L277] t1_st = 0 [L281] COND TRUE t2_i == 1 [L282] t2_st = 0 [L286] COND TRUE t3_i == 1 [L287] RET t3_st = 0 [L636] init_threads() [L637] CALL fire_delta_events() [L408] COND FALSE !(M_E == 0) [L413] COND FALSE !(T1_E == 0) [L418] COND FALSE !(T2_E == 0) [L423] COND FALSE !(T3_E == 0) [L428] COND FALSE !(E_1 == 0) [L433] COND FALSE !(E_2 == 0) [L438] COND FALSE, RET !(E_3 == 0) [L637] fire_delta_events() [L638] CALL activate_threads() [L491] int tmp ; [L492] int tmp___0 ; [L493] int tmp___1 ; [L494] int tmp___2 ; [L498] CALL, EXPR is_master_triggered() [L184] int __retres1 ; [L187] COND FALSE !(m_pc == 1) [L197] __retres1 = 0 [L199] RET return (__retres1); [L498] EXPR is_master_triggered() [L498] tmp = is_master_triggered() [L500] COND FALSE !(\read(tmp)) [L506] CALL, EXPR is_transmit1_triggered() [L203] int __retres1 ; [L206] COND FALSE !(t1_pc == 1) [L216] __retres1 = 0 [L218] RET return (__retres1); [L506] EXPR is_transmit1_triggered() [L506] tmp___0 = is_transmit1_triggered() [L508] COND FALSE !(\read(tmp___0)) [L514] CALL, EXPR is_transmit2_triggered() [L222] int __retres1 ; [L225] COND FALSE !(t2_pc == 1) [L235] __retres1 = 0 [L237] RET return (__retres1); [L514] EXPR is_transmit2_triggered() [L514] tmp___1 = is_transmit2_triggered() [L516] COND FALSE !(\read(tmp___1)) [L522] CALL, EXPR is_transmit3_triggered() [L241] int __retres1 ; [L244] COND FALSE !(t3_pc == 1) [L254] __retres1 = 0 [L256] RET return (__retres1); [L522] EXPR is_transmit3_triggered() [L522] tmp___2 = is_transmit3_triggered() [L524] COND FALSE, RET !(\read(tmp___2)) [L638] activate_threads() [L639] CALL reset_delta_events() [L451] COND FALSE !(M_E == 1) [L456] COND FALSE !(T1_E == 1) [L461] COND FALSE !(T2_E == 1) [L466] COND FALSE !(T3_E == 1) [L471] COND FALSE !(E_1 == 1) [L476] COND FALSE !(E_2 == 1) [L481] COND FALSE, RET !(E_3 == 1) [L639] reset_delta_events() [L642] COND TRUE 1 [L645] kernel_st = 1 [L646] CALL eval() [L327] int tmp ; Loop: [L331] COND TRUE 1 [L334] CALL, EXPR exists_runnable_thread() [L296] int __retres1 ; [L299] COND TRUE m_st == 0 [L300] __retres1 = 1 [L322] RET return (__retres1); [L334] EXPR exists_runnable_thread() [L334] tmp = exists_runnable_thread() [L336] COND TRUE \read(tmp) [L341] COND TRUE m_st == 0 [L342] int tmp_ndt_1; [L343] tmp_ndt_1 = __VERIFIER_nondet_int() [L344] COND FALSE !(\read(tmp_ndt_1)) [L355] COND TRUE t1_st == 0 [L356] int tmp_ndt_2; [L357] tmp_ndt_2 = __VERIFIER_nondet_int() [L358] COND FALSE !(\read(tmp_ndt_2)) [L369] COND TRUE t2_st == 0 [L370] int tmp_ndt_3; [L371] tmp_ndt_3 = __VERIFIER_nondet_int() [L372] COND FALSE !(\read(tmp_ndt_3)) [L383] COND TRUE t3_st == 0 [L384] int tmp_ndt_4; [L385] tmp_ndt_4 = __VERIFIER_nondet_int() [L386] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...