./Ultimate.py --spec ../../sv-benchmarks/c/MemSafety.prp --file ../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-read.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for memory safety (deref-memtrack) Using default analysis Version 5842f4b8 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/config/AutomizerMemDerefMemtrack.xml -i ../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-read.c -s /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/config/svcomp-DerefFreeMemtrack-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 9af739900018493f70ca6be86d814e194413d937 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Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(valid-deref) --- Real Ultimate output --- This is Ultimate 0.1.23-5842f4b [2018-11-18 15:27:59,276 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-18 15:27:59,277 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-18 15:27:59,285 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-18 15:27:59,285 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-18 15:27:59,286 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-18 15:27:59,287 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-18 15:27:59,288 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-18 15:27:59,289 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-18 15:27:59,290 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-18 15:27:59,290 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-18 15:27:59,290 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-18 15:27:59,291 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-18 15:27:59,292 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-18 15:27:59,293 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-18 15:27:59,294 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-18 15:27:59,294 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-18 15:27:59,295 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-18 15:27:59,297 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-18 15:27:59,298 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-18 15:27:59,299 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-18 15:27:59,300 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-18 15:27:59,302 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-18 15:27:59,302 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-18 15:27:59,302 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-18 15:27:59,303 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-18 15:27:59,303 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-18 15:27:59,304 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-18 15:27:59,304 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-18 15:27:59,306 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-18 15:27:59,306 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-18 15:27:59,306 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-18 15:27:59,306 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-18 15:27:59,306 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-18 15:27:59,307 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-18 15:27:59,308 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-18 15:27:59,308 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/config/svcomp-DerefFreeMemtrack-32bit-Automizer_Default.epf [2018-11-18 15:27:59,318 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-18 15:27:59,318 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-18 15:27:59,319 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-18 15:27:59,319 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-18 15:27:59,320 INFO L133 SettingsManager]: * Use SBE=true [2018-11-18 15:27:59,320 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-18 15:27:59,320 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-18 15:27:59,320 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-18 15:27:59,320 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-18 15:27:59,320 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-18 15:27:59,321 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-18 15:27:59,321 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-11-18 15:27:59,321 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-11-18 15:27:59,321 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-11-18 15:27:59,321 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-18 15:27:59,321 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-18 15:27:59,321 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-18 15:27:59,322 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-18 15:27:59,322 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-18 15:27:59,322 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-18 15:27:59,322 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-18 15:27:59,322 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-18 15:27:59,322 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-18 15:27:59,322 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-18 15:27:59,323 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-18 15:27:59,323 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-18 15:27:59,323 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 9af739900018493f70ca6be86d814e194413d937 [2018-11-18 15:27:59,345 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-18 15:27:59,352 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-18 15:27:59,354 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-18 15:27:59,355 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-18 15:27:59,355 INFO L276 PluginConnector]: CDTParser initialized [2018-11-18 15:27:59,356 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-read.c [2018-11-18 15:27:59,398 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/data/ed7d8dd6c/3363d42268134e5bbf129592d7b25e94/FLAG8f36365eb [2018-11-18 15:27:59,789 INFO L307 CDTParser]: Found 1 translation units. [2018-11-18 15:27:59,789 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-read.c [2018-11-18 15:27:59,794 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/data/ed7d8dd6c/3363d42268134e5bbf129592d7b25e94/FLAG8f36365eb [2018-11-18 15:27:59,802 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/data/ed7d8dd6c/3363d42268134e5bbf129592d7b25e94 [2018-11-18 15:27:59,804 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-18 15:27:59,805 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-11-18 15:27:59,805 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-18 15:27:59,805 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-18 15:27:59,807 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-18 15:27:59,808 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 03:27:59" (1/1) ... [2018-11-18 15:27:59,809 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3c3328d1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:27:59, skipping insertion in model container [2018-11-18 15:27:59,809 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 03:27:59" (1/1) ... [2018-11-18 15:27:59,815 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-18 15:27:59,828 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-18 15:27:59,928 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 15:27:59,933 INFO L191 MainTranslator]: Completed pre-run [2018-11-18 15:27:59,944 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 15:27:59,952 INFO L195 MainTranslator]: Completed translation [2018-11-18 15:27:59,952 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:27:59 WrapperNode [2018-11-18 15:27:59,952 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-18 15:27:59,953 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-18 15:27:59,953 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-18 15:27:59,953 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-18 15:27:59,963 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:27:59" (1/1) ... [2018-11-18 15:27:59,964 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:27:59" (1/1) ... [2018-11-18 15:27:59,970 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:27:59" (1/1) ... [2018-11-18 15:27:59,970 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:27:59" (1/1) ... [2018-11-18 15:27:59,976 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:27:59" (1/1) ... [2018-11-18 15:27:59,980 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:27:59" (1/1) ... [2018-11-18 15:27:59,981 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:27:59" (1/1) ... [2018-11-18 15:27:59,983 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-18 15:27:59,983 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-18 15:27:59,983 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-18 15:27:59,983 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-18 15:27:59,984 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:27:59" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-18 15:28:00,058 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-18 15:28:00,058 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-18 15:28:00,059 INFO L138 BoogieDeclarations]: Found implementation of procedure foo [2018-11-18 15:28:00,059 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-18 15:28:00,059 INFO L130 BoogieDeclarations]: Found specification of procedure foo [2018-11-18 15:28:00,059 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2018-11-18 15:28:00,059 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-18 15:28:00,059 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-18 15:28:00,059 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2018-11-18 15:28:00,059 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-18 15:28:00,059 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-18 15:28:00,059 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-18 15:28:00,060 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~int [2018-11-18 15:28:00,247 INFO L278 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-18 15:28:00,247 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 03:28:00 BoogieIcfgContainer [2018-11-18 15:28:00,248 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-18 15:28:00,248 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-18 15:28:00,248 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-18 15:28:00,250 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-18 15:28:00,250 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 18.11 03:27:59" (1/3) ... [2018-11-18 15:28:00,251 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3a9e93ea and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 18.11 03:28:00, skipping insertion in model container [2018-11-18 15:28:00,251 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:27:59" (2/3) ... [2018-11-18 15:28:00,251 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3a9e93ea and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 18.11 03:28:00, skipping insertion in model container [2018-11-18 15:28:00,251 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 03:28:00" (3/3) ... [2018-11-18 15:28:00,253 INFO L112 eAbstractionObserver]: Analyzing ICFG ArraysWithLenghtAtDeclaration_false-valid-deref-read.c [2018-11-18 15:28:00,258 INFO L136 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-18 15:28:00,263 INFO L148 ceAbstractionStarter]: Appying trace abstraction to program that has 8 error locations. [2018-11-18 15:28:00,274 INFO L257 AbstractCegarLoop]: Starting to check reachability of 8 error locations. [2018-11-18 15:28:00,295 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-18 15:28:00,296 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-18 15:28:00,296 INFO L383 AbstractCegarLoop]: Hoare is false [2018-11-18 15:28:00,296 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-18 15:28:00,296 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-18 15:28:00,296 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-18 15:28:00,296 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-18 15:28:00,296 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-18 15:28:00,297 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-18 15:28:00,309 INFO L276 IsEmpty]: Start isEmpty. Operand 43 states. [2018-11-18 15:28:00,315 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-11-18 15:28:00,315 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:00,316 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:00,317 INFO L423 AbstractCegarLoop]: === Iteration 1 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:00,321 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:00,321 INFO L82 PathProgramCache]: Analyzing trace with hash 1597032710, now seen corresponding path program 1 times [2018-11-18 15:28:00,322 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:00,322 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:00,359 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:00,359 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:00,359 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:00,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:00,406 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:28:00,407 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:28:00,407 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 15:28:00,409 INFO L459 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-11-18 15:28:00,417 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-11-18 15:28:00,418 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-11-18 15:28:00,419 INFO L87 Difference]: Start difference. First operand 43 states. Second operand 2 states. [2018-11-18 15:28:00,430 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:00,430 INFO L93 Difference]: Finished difference Result 43 states and 46 transitions. [2018-11-18 15:28:00,430 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-11-18 15:28:00,431 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 11 [2018-11-18 15:28:00,432 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:00,436 INFO L225 Difference]: With dead ends: 43 [2018-11-18 15:28:00,437 INFO L226 Difference]: Without dead ends: 40 [2018-11-18 15:28:00,438 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-11-18 15:28:00,448 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states. [2018-11-18 15:28:00,458 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 40. [2018-11-18 15:28:00,459 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40 states. [2018-11-18 15:28:00,460 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 43 transitions. [2018-11-18 15:28:00,460 INFO L78 Accepts]: Start accepts. Automaton has 40 states and 43 transitions. Word has length 11 [2018-11-18 15:28:00,461 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:00,461 INFO L480 AbstractCegarLoop]: Abstraction has 40 states and 43 transitions. [2018-11-18 15:28:00,461 INFO L481 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-11-18 15:28:00,461 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states and 43 transitions. [2018-11-18 15:28:00,461 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-11-18 15:28:00,461 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:00,461 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:00,462 INFO L423 AbstractCegarLoop]: === Iteration 2 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:00,462 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:00,462 INFO L82 PathProgramCache]: Analyzing trace with hash 1820883224, now seen corresponding path program 1 times [2018-11-18 15:28:00,462 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:00,462 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:00,463 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:00,463 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:00,463 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:00,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:00,501 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:28:00,501 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:28:00,501 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:28:00,502 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 15:28:00,502 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:28:00,502 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:28:00,503 INFO L87 Difference]: Start difference. First operand 40 states and 43 transitions. Second operand 3 states. [2018-11-18 15:28:00,554 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:00,554 INFO L93 Difference]: Finished difference Result 59 states and 63 transitions. [2018-11-18 15:28:00,555 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:28:00,555 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 12 [2018-11-18 15:28:00,555 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:00,556 INFO L225 Difference]: With dead ends: 59 [2018-11-18 15:28:00,557 INFO L226 Difference]: Without dead ends: 59 [2018-11-18 15:28:00,557 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:28:00,557 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2018-11-18 15:28:00,562 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 44. [2018-11-18 15:28:00,562 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 44 states. [2018-11-18 15:28:00,562 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 47 transitions. [2018-11-18 15:28:00,562 INFO L78 Accepts]: Start accepts. Automaton has 44 states and 47 transitions. Word has length 12 [2018-11-18 15:28:00,563 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:00,563 INFO L480 AbstractCegarLoop]: Abstraction has 44 states and 47 transitions. [2018-11-18 15:28:00,563 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 15:28:00,563 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 47 transitions. [2018-11-18 15:28:00,563 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2018-11-18 15:28:00,563 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:00,563 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:00,564 INFO L423 AbstractCegarLoop]: === Iteration 3 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:00,564 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:00,564 INFO L82 PathProgramCache]: Analyzing trace with hash 697121729, now seen corresponding path program 1 times [2018-11-18 15:28:00,564 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:00,564 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:00,565 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:00,565 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:00,565 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:00,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:00,628 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:28:00,628 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:28:00,628 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:28:00,629 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-18 15:28:00,629 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-18 15:28:00,629 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:28:00,629 INFO L87 Difference]: Start difference. First operand 44 states and 47 transitions. Second operand 6 states. [2018-11-18 15:28:00,780 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:00,781 INFO L93 Difference]: Finished difference Result 91 states and 96 transitions. [2018-11-18 15:28:00,781 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 15:28:00,781 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 13 [2018-11-18 15:28:00,781 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:00,783 INFO L225 Difference]: With dead ends: 91 [2018-11-18 15:28:00,783 INFO L226 Difference]: Without dead ends: 91 [2018-11-18 15:28:00,783 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-18 15:28:00,783 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91 states. [2018-11-18 15:28:00,787 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91 to 61. [2018-11-18 15:28:00,787 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 61 states. [2018-11-18 15:28:00,788 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 69 transitions. [2018-11-18 15:28:00,788 INFO L78 Accepts]: Start accepts. Automaton has 61 states and 69 transitions. Word has length 13 [2018-11-18 15:28:00,788 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:00,789 INFO L480 AbstractCegarLoop]: Abstraction has 61 states and 69 transitions. [2018-11-18 15:28:00,789 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-18 15:28:00,789 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 69 transitions. [2018-11-18 15:28:00,789 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-11-18 15:28:00,789 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:00,789 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:00,790 INFO L423 AbstractCegarLoop]: === Iteration 4 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:00,790 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:00,790 INFO L82 PathProgramCache]: Analyzing trace with hash 135937166, now seen corresponding path program 1 times [2018-11-18 15:28:00,790 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:00,790 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:00,791 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:00,791 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:00,791 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:00,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:00,906 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:28:00,906 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:28:00,906 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-18 15:28:00,907 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-18 15:28:00,907 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-18 15:28:00,907 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2018-11-18 15:28:00,907 INFO L87 Difference]: Start difference. First operand 61 states and 69 transitions. Second operand 7 states. [2018-11-18 15:28:01,066 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:01,066 INFO L93 Difference]: Finished difference Result 69 states and 74 transitions. [2018-11-18 15:28:01,066 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-18 15:28:01,067 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 14 [2018-11-18 15:28:01,067 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:01,067 INFO L225 Difference]: With dead ends: 69 [2018-11-18 15:28:01,067 INFO L226 Difference]: Without dead ends: 69 [2018-11-18 15:28:01,068 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2018-11-18 15:28:01,068 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states. [2018-11-18 15:28:01,071 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 61. [2018-11-18 15:28:01,071 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 61 states. [2018-11-18 15:28:01,072 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 68 transitions. [2018-11-18 15:28:01,072 INFO L78 Accepts]: Start accepts. Automaton has 61 states and 68 transitions. Word has length 14 [2018-11-18 15:28:01,073 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:01,073 INFO L480 AbstractCegarLoop]: Abstraction has 61 states and 68 transitions. [2018-11-18 15:28:01,073 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-18 15:28:01,073 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 68 transitions. [2018-11-18 15:28:01,073 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-11-18 15:28:01,073 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:01,073 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:01,073 INFO L423 AbstractCegarLoop]: === Iteration 5 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:01,074 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:01,074 INFO L82 PathProgramCache]: Analyzing trace with hash 135937165, now seen corresponding path program 1 times [2018-11-18 15:28:01,074 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:01,074 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:01,075 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:01,075 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:01,075 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:01,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:01,102 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:28:01,102 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:28:01,102 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-18 15:28:01,103 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 15:28:01,103 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:28:01,103 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:28:01,103 INFO L87 Difference]: Start difference. First operand 61 states and 68 transitions. Second operand 5 states. [2018-11-18 15:28:01,139 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:01,139 INFO L93 Difference]: Finished difference Result 60 states and 66 transitions. [2018-11-18 15:28:01,140 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 15:28:01,140 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 14 [2018-11-18 15:28:01,140 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:01,140 INFO L225 Difference]: With dead ends: 60 [2018-11-18 15:28:01,141 INFO L226 Difference]: Without dead ends: 60 [2018-11-18 15:28:01,141 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:28:01,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states. [2018-11-18 15:28:01,144 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 60. [2018-11-18 15:28:01,144 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2018-11-18 15:28:01,145 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 66 transitions. [2018-11-18 15:28:01,145 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 66 transitions. Word has length 14 [2018-11-18 15:28:01,145 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:01,145 INFO L480 AbstractCegarLoop]: Abstraction has 60 states and 66 transitions. [2018-11-18 15:28:01,145 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 15:28:01,145 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 66 transitions. [2018-11-18 15:28:01,146 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-11-18 15:28:01,146 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:01,146 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:01,146 INFO L423 AbstractCegarLoop]: === Iteration 6 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:01,146 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:01,146 INFO L82 PathProgramCache]: Analyzing trace with hash 1254753657, now seen corresponding path program 1 times [2018-11-18 15:28:01,146 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:01,147 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:01,147 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:01,147 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:01,147 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:01,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:01,234 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:28:01,234 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:28:01,234 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:28:01,240 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:01,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:01,258 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:28:01,280 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:28:01,294 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:28:01,295 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 3] total 9 [2018-11-18 15:28:01,295 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-18 15:28:01,295 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-18 15:28:01,295 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=69, Unknown=0, NotChecked=0, Total=90 [2018-11-18 15:28:01,296 INFO L87 Difference]: Start difference. First operand 60 states and 66 transitions. Second operand 10 states. [2018-11-18 15:28:01,436 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:01,436 INFO L93 Difference]: Finished difference Result 100 states and 109 transitions. [2018-11-18 15:28:01,437 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-18 15:28:01,437 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 19 [2018-11-18 15:28:01,437 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:01,437 INFO L225 Difference]: With dead ends: 100 [2018-11-18 15:28:01,438 INFO L226 Difference]: Without dead ends: 100 [2018-11-18 15:28:01,438 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 29 GetRequests, 17 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=52, Invalid=130, Unknown=0, NotChecked=0, Total=182 [2018-11-18 15:28:01,438 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states. [2018-11-18 15:28:01,441 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 71. [2018-11-18 15:28:01,442 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 71 states. [2018-11-18 15:28:01,442 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71 states to 71 states and 78 transitions. [2018-11-18 15:28:01,443 INFO L78 Accepts]: Start accepts. Automaton has 71 states and 78 transitions. Word has length 19 [2018-11-18 15:28:01,443 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:01,443 INFO L480 AbstractCegarLoop]: Abstraction has 71 states and 78 transitions. [2018-11-18 15:28:01,443 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-18 15:28:01,443 INFO L276 IsEmpty]: Start isEmpty. Operand 71 states and 78 transitions. [2018-11-18 15:28:01,444 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-11-18 15:28:01,444 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:01,444 INFO L375 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:01,444 INFO L423 AbstractCegarLoop]: === Iteration 7 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:01,444 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:01,445 INFO L82 PathProgramCache]: Analyzing trace with hash 539365409, now seen corresponding path program 1 times [2018-11-18 15:28:01,445 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:01,445 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:01,445 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:01,446 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:01,446 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:01,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:01,519 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:28:01,519 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:28:01,519 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:28:01,532 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:01,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:01,543 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:28:01,578 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:28:01,592 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:28:01,592 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 10 [2018-11-18 15:28:01,593 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-18 15:28:01,593 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-18 15:28:01,593 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=69, Unknown=0, NotChecked=0, Total=90 [2018-11-18 15:28:01,593 INFO L87 Difference]: Start difference. First operand 71 states and 78 transitions. Second operand 10 states. [2018-11-18 15:28:01,747 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:01,748 INFO L93 Difference]: Finished difference Result 104 states and 109 transitions. [2018-11-18 15:28:01,748 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-18 15:28:01,748 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 23 [2018-11-18 15:28:01,748 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:01,749 INFO L225 Difference]: With dead ends: 104 [2018-11-18 15:28:01,749 INFO L226 Difference]: Without dead ends: 95 [2018-11-18 15:28:01,749 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 32 GetRequests, 20 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=50, Invalid=132, Unknown=0, NotChecked=0, Total=182 [2018-11-18 15:28:01,749 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95 states. [2018-11-18 15:28:01,753 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95 to 77. [2018-11-18 15:28:01,753 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 77 states. [2018-11-18 15:28:01,754 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 82 transitions. [2018-11-18 15:28:01,754 INFO L78 Accepts]: Start accepts. Automaton has 77 states and 82 transitions. Word has length 23 [2018-11-18 15:28:01,754 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:01,754 INFO L480 AbstractCegarLoop]: Abstraction has 77 states and 82 transitions. [2018-11-18 15:28:01,754 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-18 15:28:01,754 INFO L276 IsEmpty]: Start isEmpty. Operand 77 states and 82 transitions. [2018-11-18 15:28:01,755 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-11-18 15:28:01,755 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:01,755 INFO L375 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:01,755 INFO L423 AbstractCegarLoop]: === Iteration 8 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:01,756 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:01,756 INFO L82 PathProgramCache]: Analyzing trace with hash 2065437657, now seen corresponding path program 2 times [2018-11-18 15:28:01,756 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:01,756 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:01,757 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:01,757 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:01,757 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:01,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:01,791 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-18 15:28:01,791 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:28:01,791 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 15:28:01,791 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 15:28:01,792 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:28:01,792 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:28:01,792 INFO L87 Difference]: Start difference. First operand 77 states and 82 transitions. Second operand 3 states. [2018-11-18 15:28:01,800 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:01,800 INFO L93 Difference]: Finished difference Result 75 states and 80 transitions. [2018-11-18 15:28:01,800 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:28:01,801 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 29 [2018-11-18 15:28:01,801 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:01,801 INFO L225 Difference]: With dead ends: 75 [2018-11-18 15:28:01,801 INFO L226 Difference]: Without dead ends: 75 [2018-11-18 15:28:01,802 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:28:01,802 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75 states. [2018-11-18 15:28:01,805 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75 to 75. [2018-11-18 15:28:01,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 75 states. [2018-11-18 15:28:01,806 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 80 transitions. [2018-11-18 15:28:01,806 INFO L78 Accepts]: Start accepts. Automaton has 75 states and 80 transitions. Word has length 29 [2018-11-18 15:28:01,806 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:01,806 INFO L480 AbstractCegarLoop]: Abstraction has 75 states and 80 transitions. [2018-11-18 15:28:01,806 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 15:28:01,806 INFO L276 IsEmpty]: Start isEmpty. Operand 75 states and 80 transitions. [2018-11-18 15:28:01,807 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-11-18 15:28:01,807 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:01,807 INFO L375 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:01,807 INFO L423 AbstractCegarLoop]: === Iteration 9 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:01,807 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:01,808 INFO L82 PathProgramCache]: Analyzing trace with hash 2065437658, now seen corresponding path program 1 times [2018-11-18 15:28:01,808 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:01,808 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:01,808 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:01,808 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:28:01,808 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:01,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:01,843 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-18 15:28:01,843 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:28:01,843 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 15:28:01,843 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 15:28:01,844 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:28:01,844 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:28:01,844 INFO L87 Difference]: Start difference. First operand 75 states and 80 transitions. Second operand 3 states. [2018-11-18 15:28:01,879 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:01,879 INFO L93 Difference]: Finished difference Result 79 states and 84 transitions. [2018-11-18 15:28:01,879 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:28:01,879 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 29 [2018-11-18 15:28:01,880 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:01,880 INFO L225 Difference]: With dead ends: 79 [2018-11-18 15:28:01,880 INFO L226 Difference]: Without dead ends: 79 [2018-11-18 15:28:01,880 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:28:01,880 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79 states. [2018-11-18 15:28:01,883 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79 to 77. [2018-11-18 15:28:01,883 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 77 states. [2018-11-18 15:28:01,883 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 82 transitions. [2018-11-18 15:28:01,884 INFO L78 Accepts]: Start accepts. Automaton has 77 states and 82 transitions. Word has length 29 [2018-11-18 15:28:01,884 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:01,884 INFO L480 AbstractCegarLoop]: Abstraction has 77 states and 82 transitions. [2018-11-18 15:28:01,884 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 15:28:01,884 INFO L276 IsEmpty]: Start isEmpty. Operand 77 states and 82 transitions. [2018-11-18 15:28:01,885 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-11-18 15:28:01,885 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:01,885 INFO L375 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:01,885 INFO L423 AbstractCegarLoop]: === Iteration 10 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:01,885 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:01,885 INFO L82 PathProgramCache]: Analyzing trace with hash -989786460, now seen corresponding path program 1 times [2018-11-18 15:28:01,886 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:01,886 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:01,886 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:01,886 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:01,887 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:01,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:01,917 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-18 15:28:01,917 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:28:01,917 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:28:01,926 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:01,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:01,941 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:28:01,957 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-18 15:28:01,981 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:28:01,981 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 5 [2018-11-18 15:28:01,982 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 15:28:01,982 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:28:01,982 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:28:01,982 INFO L87 Difference]: Start difference. First operand 77 states and 82 transitions. Second operand 5 states. [2018-11-18 15:28:02,017 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:02,017 INFO L93 Difference]: Finished difference Result 103 states and 109 transitions. [2018-11-18 15:28:02,017 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-18 15:28:02,018 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 37 [2018-11-18 15:28:02,018 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:02,018 INFO L225 Difference]: With dead ends: 103 [2018-11-18 15:28:02,018 INFO L226 Difference]: Without dead ends: 103 [2018-11-18 15:28:02,019 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 40 GetRequests, 37 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:28:02,019 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 103 states. [2018-11-18 15:28:02,021 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 103 to 86. [2018-11-18 15:28:02,022 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 86 states. [2018-11-18 15:28:02,022 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 93 transitions. [2018-11-18 15:28:02,022 INFO L78 Accepts]: Start accepts. Automaton has 86 states and 93 transitions. Word has length 37 [2018-11-18 15:28:02,023 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:02,023 INFO L480 AbstractCegarLoop]: Abstraction has 86 states and 93 transitions. [2018-11-18 15:28:02,023 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 15:28:02,023 INFO L276 IsEmpty]: Start isEmpty. Operand 86 states and 93 transitions. [2018-11-18 15:28:02,024 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-11-18 15:28:02,024 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:02,024 INFO L375 BasicCegarLoop]: trace histogram [6, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:02,024 INFO L423 AbstractCegarLoop]: === Iteration 11 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:02,024 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:02,025 INFO L82 PathProgramCache]: Analyzing trace with hash -982129233, now seen corresponding path program 1 times [2018-11-18 15:28:02,025 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:02,025 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:02,025 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:02,025 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:02,026 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:02,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:02,090 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 39 proven. 13 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-11-18 15:28:02,090 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:28:02,091 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:28:02,097 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:02,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:02,114 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:28:02,162 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 42 proven. 10 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-11-18 15:28:02,177 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:28:02,177 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 12 [2018-11-18 15:28:02,178 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-11-18 15:28:02,178 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-11-18 15:28:02,178 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=95, Unknown=0, NotChecked=0, Total=132 [2018-11-18 15:28:02,178 INFO L87 Difference]: Start difference. First operand 86 states and 93 transitions. Second operand 12 states. [2018-11-18 15:28:02,331 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:02,331 INFO L93 Difference]: Finished difference Result 108 states and 113 transitions. [2018-11-18 15:28:02,332 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-11-18 15:28:02,332 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 54 [2018-11-18 15:28:02,332 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:02,333 INFO L225 Difference]: With dead ends: 108 [2018-11-18 15:28:02,333 INFO L226 Difference]: Without dead ends: 105 [2018-11-18 15:28:02,333 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 67 GetRequests, 51 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=87, Invalid=219, Unknown=0, NotChecked=0, Total=306 [2018-11-18 15:28:02,333 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105 states. [2018-11-18 15:28:02,336 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105 to 86. [2018-11-18 15:28:02,336 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 86 states. [2018-11-18 15:28:02,337 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 92 transitions. [2018-11-18 15:28:02,337 INFO L78 Accepts]: Start accepts. Automaton has 86 states and 92 transitions. Word has length 54 [2018-11-18 15:28:02,338 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:02,338 INFO L480 AbstractCegarLoop]: Abstraction has 86 states and 92 transitions. [2018-11-18 15:28:02,338 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-11-18 15:28:02,338 INFO L276 IsEmpty]: Start isEmpty. Operand 86 states and 92 transitions. [2018-11-18 15:28:02,339 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-11-18 15:28:02,339 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:02,339 INFO L375 BasicCegarLoop]: trace histogram [7, 6, 6, 5, 5, 5, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:02,339 INFO L423 AbstractCegarLoop]: === Iteration 12 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:02,339 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:02,339 INFO L82 PathProgramCache]: Analyzing trace with hash 1295131761, now seen corresponding path program 1 times [2018-11-18 15:28:02,339 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:02,340 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:02,340 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:02,340 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:02,340 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:02,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:02,456 INFO L134 CoverageAnalysis]: Checked inductivity of 96 backedges. 53 proven. 30 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-11-18 15:28:02,456 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:28:02,456 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:28:02,465 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:02,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:02,480 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:28:02,548 INFO L134 CoverageAnalysis]: Checked inductivity of 96 backedges. 83 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-18 15:28:02,563 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:28:02,563 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 9] total 16 [2018-11-18 15:28:02,563 INFO L459 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-11-18 15:28:02,564 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-11-18 15:28:02,564 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=44, Invalid=196, Unknown=0, NotChecked=0, Total=240 [2018-11-18 15:28:02,564 INFO L87 Difference]: Start difference. First operand 86 states and 92 transitions. Second operand 16 states. [2018-11-18 15:28:02,906 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:02,906 INFO L93 Difference]: Finished difference Result 147 states and 152 transitions. [2018-11-18 15:28:02,906 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-11-18 15:28:02,906 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 57 [2018-11-18 15:28:02,907 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:02,907 INFO L225 Difference]: With dead ends: 147 [2018-11-18 15:28:02,907 INFO L226 Difference]: Without dead ends: 147 [2018-11-18 15:28:02,908 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 76 GetRequests, 50 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 132 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=155, Invalid=601, Unknown=0, NotChecked=0, Total=756 [2018-11-18 15:28:02,908 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 147 states. [2018-11-18 15:28:02,911 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 147 to 123. [2018-11-18 15:28:02,911 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 123 states. [2018-11-18 15:28:02,912 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 123 states to 123 states and 130 transitions. [2018-11-18 15:28:02,913 INFO L78 Accepts]: Start accepts. Automaton has 123 states and 130 transitions. Word has length 57 [2018-11-18 15:28:02,913 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:02,913 INFO L480 AbstractCegarLoop]: Abstraction has 123 states and 130 transitions. [2018-11-18 15:28:02,913 INFO L481 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-11-18 15:28:02,913 INFO L276 IsEmpty]: Start isEmpty. Operand 123 states and 130 transitions. [2018-11-18 15:28:02,914 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2018-11-18 15:28:02,914 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:02,914 INFO L375 BasicCegarLoop]: trace histogram [7, 5, 5, 5, 5, 5, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:02,914 INFO L423 AbstractCegarLoop]: === Iteration 13 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:02,915 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:02,915 INFO L82 PathProgramCache]: Analyzing trace with hash 1531366311, now seen corresponding path program 2 times [2018-11-18 15:28:02,915 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:02,915 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:02,915 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:02,915 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:02,916 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:02,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:02,978 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 86 trivial. 0 not checked. [2018-11-18 15:28:02,978 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:28:02,978 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:28:02,985 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-18 15:28:03,008 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 15:28:03,009 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:28:03,011 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:28:03,037 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 1 [2018-11-18 15:28:03,037 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-18 15:28:03,043 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 15:28:03,048 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 15:28:03,049 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 21 [2018-11-18 15:28:03,049 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-11-18 15:28:03,053 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 15:28:03,057 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-18 15:28:03,057 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 3 variables, input treesize:24, output treesize:17 [2018-11-18 15:28:03,175 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 86 trivial. 0 not checked. [2018-11-18 15:28:03,197 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:28:03,198 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 4] total 6 [2018-11-18 15:28:03,198 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-18 15:28:03,198 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-18 15:28:03,198 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-18 15:28:03,198 INFO L87 Difference]: Start difference. First operand 123 states and 130 transitions. Second operand 7 states. [2018-11-18 15:28:03,266 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:03,266 INFO L93 Difference]: Finished difference Result 127 states and 134 transitions. [2018-11-18 15:28:03,266 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 15:28:03,266 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 60 [2018-11-18 15:28:03,266 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:03,267 INFO L225 Difference]: With dead ends: 127 [2018-11-18 15:28:03,267 INFO L226 Difference]: Without dead ends: 127 [2018-11-18 15:28:03,267 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 63 GetRequests, 54 SyntacticMatches, 4 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-18 15:28:03,268 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127 states. [2018-11-18 15:28:03,270 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127 to 125. [2018-11-18 15:28:03,270 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 125 states. [2018-11-18 15:28:03,271 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125 states to 125 states and 132 transitions. [2018-11-18 15:28:03,271 INFO L78 Accepts]: Start accepts. Automaton has 125 states and 132 transitions. Word has length 60 [2018-11-18 15:28:03,271 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:03,271 INFO L480 AbstractCegarLoop]: Abstraction has 125 states and 132 transitions. [2018-11-18 15:28:03,271 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-18 15:28:03,271 INFO L276 IsEmpty]: Start isEmpty. Operand 125 states and 132 transitions. [2018-11-18 15:28:03,272 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-11-18 15:28:03,272 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:03,272 INFO L375 BasicCegarLoop]: trace histogram [7, 5, 5, 5, 5, 5, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:03,273 INFO L423 AbstractCegarLoop]: === Iteration 14 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:03,273 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:03,273 INFO L82 PathProgramCache]: Analyzing trace with hash -2125354639, now seen corresponding path program 2 times [2018-11-18 15:28:03,273 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:03,273 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:03,274 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:03,274 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:28:03,274 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:03,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:03,412 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 51 proven. 26 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-11-18 15:28:03,412 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:28:03,413 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:28:03,422 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-18 15:28:03,429 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-11-18 15:28:03,429 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:28:03,431 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:28:03,442 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 1 [2018-11-18 15:28:03,442 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-18 15:28:03,447 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 15:28:03,449 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 15:28:03,449 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 21 [2018-11-18 15:28:03,450 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-11-18 15:28:03,454 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 15:28:03,457 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-18 15:28:03,458 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 3 variables, input treesize:21, output treesize:14 [2018-11-18 15:28:03,587 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 97 trivial. 0 not checked. [2018-11-18 15:28:03,602 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-18 15:28:03,602 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [10] total 14 [2018-11-18 15:28:03,602 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-11-18 15:28:03,602 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-11-18 15:28:03,603 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=147, Unknown=0, NotChecked=0, Total=182 [2018-11-18 15:28:03,603 INFO L87 Difference]: Start difference. First operand 125 states and 132 transitions. Second operand 14 states. [2018-11-18 15:28:03,770 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:03,770 INFO L93 Difference]: Finished difference Result 106 states and 109 transitions. [2018-11-18 15:28:03,770 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-18 15:28:03,770 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 68 [2018-11-18 15:28:03,770 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:03,771 INFO L225 Difference]: With dead ends: 106 [2018-11-18 15:28:03,771 INFO L226 Difference]: Without dead ends: 106 [2018-11-18 15:28:03,771 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 85 GetRequests, 63 SyntacticMatches, 3 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 64 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=92, Invalid=328, Unknown=0, NotChecked=0, Total=420 [2018-11-18 15:28:03,771 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106 states. [2018-11-18 15:28:03,773 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106 to 104. [2018-11-18 15:28:03,773 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 104 states. [2018-11-18 15:28:03,774 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 104 states to 104 states and 107 transitions. [2018-11-18 15:28:03,774 INFO L78 Accepts]: Start accepts. Automaton has 104 states and 107 transitions. Word has length 68 [2018-11-18 15:28:03,774 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:03,774 INFO L480 AbstractCegarLoop]: Abstraction has 104 states and 107 transitions. [2018-11-18 15:28:03,774 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-11-18 15:28:03,774 INFO L276 IsEmpty]: Start isEmpty. Operand 104 states and 107 transitions. [2018-11-18 15:28:03,775 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-11-18 15:28:03,775 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:03,775 INFO L375 BasicCegarLoop]: trace histogram [12, 10, 10, 9, 9, 9, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:03,776 INFO L423 AbstractCegarLoop]: === Iteration 15 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:03,776 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:03,776 INFO L82 PathProgramCache]: Analyzing trace with hash 809132038, now seen corresponding path program 2 times [2018-11-18 15:28:03,776 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:03,776 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:03,777 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:03,777 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:28:03,777 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:03,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:03,861 INFO L134 CoverageAnalysis]: Checked inductivity of 313 backedges. 203 proven. 24 refuted. 0 times theorem prover too weak. 86 trivial. 0 not checked. [2018-11-18 15:28:03,861 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:28:03,862 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:28:03,877 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-18 15:28:03,912 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 15:28:03,912 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:28:03,915 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:28:03,982 INFO L134 CoverageAnalysis]: Checked inductivity of 313 backedges. 214 proven. 13 refuted. 0 times theorem prover too weak. 86 trivial. 0 not checked. [2018-11-18 15:28:04,007 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:28:04,007 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 11] total 18 [2018-11-18 15:28:04,007 INFO L459 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-11-18 15:28:04,008 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-11-18 15:28:04,008 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=79, Invalid=227, Unknown=0, NotChecked=0, Total=306 [2018-11-18 15:28:04,008 INFO L87 Difference]: Start difference. First operand 104 states and 107 transitions. Second operand 18 states. [2018-11-18 15:28:04,183 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:04,183 INFO L93 Difference]: Finished difference Result 151 states and 155 transitions. [2018-11-18 15:28:04,184 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-11-18 15:28:04,184 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 94 [2018-11-18 15:28:04,184 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:04,185 INFO L225 Difference]: With dead ends: 151 [2018-11-18 15:28:04,185 INFO L226 Difference]: Without dead ends: 151 [2018-11-18 15:28:04,185 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 112 GetRequests, 89 SyntacticMatches, 0 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 71 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=174, Invalid=426, Unknown=0, NotChecked=0, Total=600 [2018-11-18 15:28:04,185 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 151 states. [2018-11-18 15:28:04,188 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 151 to 141. [2018-11-18 15:28:04,188 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-11-18 15:28:04,189 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 145 transitions. [2018-11-18 15:28:04,189 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 145 transitions. Word has length 94 [2018-11-18 15:28:04,189 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:04,189 INFO L480 AbstractCegarLoop]: Abstraction has 141 states and 145 transitions. [2018-11-18 15:28:04,189 INFO L481 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-11-18 15:28:04,189 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 145 transitions. [2018-11-18 15:28:04,190 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 126 [2018-11-18 15:28:04,190 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:04,191 INFO L375 BasicCegarLoop]: trace histogram [16, 13, 13, 12, 12, 12, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:04,191 INFO L423 AbstractCegarLoop]: === Iteration 16 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:04,191 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:04,191 INFO L82 PathProgramCache]: Analyzing trace with hash -1481733671, now seen corresponding path program 3 times [2018-11-18 15:28:04,191 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:04,191 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:04,192 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:04,192 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:28:04,192 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:04,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:04,315 INFO L134 CoverageAnalysis]: Checked inductivity of 573 backedges. 257 proven. 52 refuted. 0 times theorem prover too weak. 264 trivial. 0 not checked. [2018-11-18 15:28:04,316 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:28:04,316 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:28:04,323 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 15:28:04,362 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2018-11-18 15:28:04,362 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:28:04,365 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:28:04,369 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 15:28:04,381 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 15:28:04,386 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 15:28:04,387 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 15:28:04,393 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 15:28:04,401 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 15:28:04,402 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:16, output treesize:30 [2018-11-18 15:28:04,606 INFO L134 CoverageAnalysis]: Checked inductivity of 573 backedges. 299 proven. 132 refuted. 0 times theorem prover too weak. 142 trivial. 0 not checked. [2018-11-18 15:28:04,621 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:28:04,621 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 15] total 21 [2018-11-18 15:28:04,622 INFO L459 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-11-18 15:28:04,622 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-11-18 15:28:04,622 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=86, Invalid=376, Unknown=0, NotChecked=0, Total=462 [2018-11-18 15:28:04,622 INFO L87 Difference]: Start difference. First operand 141 states and 145 transitions. Second operand 22 states. [2018-11-18 15:28:05,549 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:05,549 INFO L93 Difference]: Finished difference Result 216 states and 229 transitions. [2018-11-18 15:28:05,550 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2018-11-18 15:28:05,550 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 125 [2018-11-18 15:28:05,550 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:05,551 INFO L225 Difference]: With dead ends: 216 [2018-11-18 15:28:05,551 INFO L226 Difference]: Without dead ends: 216 [2018-11-18 15:28:05,552 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 168 GetRequests, 108 SyntacticMatches, 6 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 943 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=681, Invalid=2399, Unknown=0, NotChecked=0, Total=3080 [2018-11-18 15:28:05,552 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 216 states. [2018-11-18 15:28:05,556 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 216 to 206. [2018-11-18 15:28:05,556 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 206 states. [2018-11-18 15:28:05,557 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 206 states to 206 states and 219 transitions. [2018-11-18 15:28:05,557 INFO L78 Accepts]: Start accepts. Automaton has 206 states and 219 transitions. Word has length 125 [2018-11-18 15:28:05,557 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:05,557 INFO L480 AbstractCegarLoop]: Abstraction has 206 states and 219 transitions. [2018-11-18 15:28:05,558 INFO L481 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-11-18 15:28:05,558 INFO L276 IsEmpty]: Start isEmpty. Operand 206 states and 219 transitions. [2018-11-18 15:28:05,560 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 181 [2018-11-18 15:28:05,560 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:05,560 INFO L375 BasicCegarLoop]: trace histogram [24, 20, 20, 19, 19, 19, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:05,560 INFO L423 AbstractCegarLoop]: === Iteration 17 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:05,561 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:05,561 INFO L82 PathProgramCache]: Analyzing trace with hash -224959962, now seen corresponding path program 4 times [2018-11-18 15:28:05,561 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:05,561 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:05,561 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:05,561 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:28:05,562 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:05,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:05,725 INFO L134 CoverageAnalysis]: Checked inductivity of 1356 backedges. 528 proven. 80 refuted. 0 times theorem prover too weak. 748 trivial. 0 not checked. [2018-11-18 15:28:05,725 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:28:05,726 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:28:05,731 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 15:28:05,764 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 15:28:05,764 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:28:05,768 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:28:05,770 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 15:28:05,777 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 15:28:05,781 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 15:28:05,781 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 15:28:05,786 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 15:28:05,792 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 15:28:05,793 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 15:28:05,940 INFO L134 CoverageAnalysis]: Checked inductivity of 1356 backedges. 528 proven. 80 refuted. 0 times theorem prover too weak. 748 trivial. 0 not checked. [2018-11-18 15:28:05,956 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:28:05,956 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 16 [2018-11-18 15:28:05,956 INFO L459 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-11-18 15:28:05,956 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-11-18 15:28:05,956 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=82, Invalid=190, Unknown=0, NotChecked=0, Total=272 [2018-11-18 15:28:05,957 INFO L87 Difference]: Start difference. First operand 206 states and 219 transitions. Second operand 17 states. [2018-11-18 15:28:06,156 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:06,156 INFO L93 Difference]: Finished difference Result 233 states and 249 transitions. [2018-11-18 15:28:06,156 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-18 15:28:06,156 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 180 [2018-11-18 15:28:06,156 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:06,157 INFO L225 Difference]: With dead ends: 233 [2018-11-18 15:28:06,157 INFO L226 Difference]: Without dead ends: 233 [2018-11-18 15:28:06,157 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 195 GetRequests, 164 SyntacticMatches, 10 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 111 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=138, Invalid=368, Unknown=0, NotChecked=0, Total=506 [2018-11-18 15:28:06,158 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 233 states. [2018-11-18 15:28:06,160 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 233 to 212. [2018-11-18 15:28:06,160 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 212 states. [2018-11-18 15:28:06,161 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 212 states to 212 states and 226 transitions. [2018-11-18 15:28:06,161 INFO L78 Accepts]: Start accepts. Automaton has 212 states and 226 transitions. Word has length 180 [2018-11-18 15:28:06,161 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:06,161 INFO L480 AbstractCegarLoop]: Abstraction has 212 states and 226 transitions. [2018-11-18 15:28:06,161 INFO L481 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-11-18 15:28:06,161 INFO L276 IsEmpty]: Start isEmpty. Operand 212 states and 226 transitions. [2018-11-18 15:28:06,163 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 187 [2018-11-18 15:28:06,163 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:06,163 INFO L375 BasicCegarLoop]: trace histogram [25, 21, 21, 20, 20, 20, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:06,163 INFO L423 AbstractCegarLoop]: === Iteration 18 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:06,163 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:06,163 INFO L82 PathProgramCache]: Analyzing trace with hash 376913262, now seen corresponding path program 5 times [2018-11-18 15:28:06,164 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:06,164 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:06,164 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:06,164 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:28:06,164 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:06,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:06,327 INFO L134 CoverageAnalysis]: Checked inductivity of 1482 backedges. 717 proven. 71 refuted. 0 times theorem prover too weak. 694 trivial. 0 not checked. [2018-11-18 15:28:06,328 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:28:06,328 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:28:06,334 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-18 15:28:06,378 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2018-11-18 15:28:06,378 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:28:06,381 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:28:06,536 INFO L134 CoverageAnalysis]: Checked inductivity of 1482 backedges. 656 proven. 337 refuted. 0 times theorem prover too weak. 489 trivial. 0 not checked. [2018-11-18 15:28:06,551 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:28:06,551 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 20] total 28 [2018-11-18 15:28:06,552 INFO L459 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-11-18 15:28:06,552 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-11-18 15:28:06,552 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=149, Invalid=607, Unknown=0, NotChecked=0, Total=756 [2018-11-18 15:28:06,552 INFO L87 Difference]: Start difference. First operand 212 states and 226 transitions. Second operand 28 states. [2018-11-18 15:28:06,910 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:06,910 INFO L93 Difference]: Finished difference Result 349 states and 382 transitions. [2018-11-18 15:28:06,911 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-11-18 15:28:06,911 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 186 [2018-11-18 15:28:06,911 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:06,912 INFO L225 Difference]: With dead ends: 349 [2018-11-18 15:28:06,912 INFO L226 Difference]: Without dead ends: 349 [2018-11-18 15:28:06,913 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 214 GetRequests, 175 SyntacticMatches, 0 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 296 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=353, Invalid=1287, Unknown=0, NotChecked=0, Total=1640 [2018-11-18 15:28:06,913 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 349 states. [2018-11-18 15:28:06,919 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 349 to 331. [2018-11-18 15:28:06,920 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 331 states. [2018-11-18 15:28:06,921 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 331 states to 331 states and 361 transitions. [2018-11-18 15:28:06,921 INFO L78 Accepts]: Start accepts. Automaton has 331 states and 361 transitions. Word has length 186 [2018-11-18 15:28:06,921 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:06,921 INFO L480 AbstractCegarLoop]: Abstraction has 331 states and 361 transitions. [2018-11-18 15:28:06,922 INFO L481 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-11-18 15:28:06,922 INFO L276 IsEmpty]: Start isEmpty. Operand 331 states and 361 transitions. [2018-11-18 15:28:06,924 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 218 [2018-11-18 15:28:06,924 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:06,924 INFO L375 BasicCegarLoop]: trace histogram [29, 24, 24, 23, 23, 23, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:06,924 INFO L423 AbstractCegarLoop]: === Iteration 19 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:06,925 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:06,925 INFO L82 PathProgramCache]: Analyzing trace with hash -1241963327, now seen corresponding path program 6 times [2018-11-18 15:28:06,925 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:06,925 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:06,925 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:06,926 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:28:06,926 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:06,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:07,064 INFO L134 CoverageAnalysis]: Checked inductivity of 2000 backedges. 923 proven. 518 refuted. 0 times theorem prover too weak. 559 trivial. 0 not checked. [2018-11-18 15:28:07,065 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:28:07,065 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:28:07,075 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-18 15:28:07,127 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 9 check-sat command(s) [2018-11-18 15:28:07,127 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:28:07,130 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:28:07,138 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 15:28:07,140 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 15:28:07,146 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 15:28:07,146 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 15:28:07,152 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 15:28:07,161 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 15:28:07,161 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:16, output treesize:30 [2018-11-18 15:28:07,523 INFO L134 CoverageAnalysis]: Checked inductivity of 2000 backedges. 999 proven. 311 refuted. 0 times theorem prover too weak. 690 trivial. 0 not checked. [2018-11-18 15:28:07,539 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:28:07,539 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 15] total 28 [2018-11-18 15:28:07,539 INFO L459 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-11-18 15:28:07,539 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-11-18 15:28:07,540 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=98, Invalid=658, Unknown=0, NotChecked=0, Total=756 [2018-11-18 15:28:07,540 INFO L87 Difference]: Start difference. First operand 331 states and 361 transitions. Second operand 28 states. [2018-11-18 15:28:08,412 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:08,412 INFO L93 Difference]: Finished difference Result 418 states and 440 transitions. [2018-11-18 15:28:08,412 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-11-18 15:28:08,413 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 217 [2018-11-18 15:28:08,413 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:08,414 INFO L225 Difference]: With dead ends: 418 [2018-11-18 15:28:08,414 INFO L226 Difference]: Without dead ends: 406 [2018-11-18 15:28:08,415 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 263 GetRequests, 196 SyntacticMatches, 9 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 809 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=599, Invalid=2941, Unknown=0, NotChecked=0, Total=3540 [2018-11-18 15:28:08,415 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 406 states. [2018-11-18 15:28:08,421 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 406 to 347. [2018-11-18 15:28:08,421 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 347 states. [2018-11-18 15:28:08,423 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 347 states to 347 states and 362 transitions. [2018-11-18 15:28:08,423 INFO L78 Accepts]: Start accepts. Automaton has 347 states and 362 transitions. Word has length 217 [2018-11-18 15:28:08,423 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:08,423 INFO L480 AbstractCegarLoop]: Abstraction has 347 states and 362 transitions. [2018-11-18 15:28:08,423 INFO L481 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-11-18 15:28:08,423 INFO L276 IsEmpty]: Start isEmpty. Operand 347 states and 362 transitions. [2018-11-18 15:28:08,424 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 261 [2018-11-18 15:28:08,425 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:08,425 INFO L375 BasicCegarLoop]: trace histogram [35, 29, 29, 28, 28, 28, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:08,425 INFO L423 AbstractCegarLoop]: === Iteration 20 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:08,425 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:08,425 INFO L82 PathProgramCache]: Analyzing trace with hash -1552132018, now seen corresponding path program 7 times [2018-11-18 15:28:08,425 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:08,425 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:08,426 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:08,426 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:28:08,426 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:08,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:08,631 INFO L134 CoverageAnalysis]: Checked inductivity of 2947 backedges. 970 proven. 114 refuted. 0 times theorem prover too weak. 1863 trivial. 0 not checked. [2018-11-18 15:28:08,631 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:28:08,631 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:28:08,642 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:08,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:08,683 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:28:08,787 INFO L134 CoverageAnalysis]: Checked inductivity of 2947 backedges. 1829 proven. 44 refuted. 0 times theorem prover too weak. 1074 trivial. 0 not checked. [2018-11-18 15:28:08,802 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:28:08,802 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 12] total 22 [2018-11-18 15:28:08,803 INFO L459 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-11-18 15:28:08,803 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-11-18 15:28:08,803 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=80, Invalid=382, Unknown=0, NotChecked=0, Total=462 [2018-11-18 15:28:08,803 INFO L87 Difference]: Start difference. First operand 347 states and 362 transitions. Second operand 22 states. [2018-11-18 15:28:09,159 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:09,160 INFO L93 Difference]: Finished difference Result 339 states and 348 transitions. [2018-11-18 15:28:09,165 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-11-18 15:28:09,165 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 260 [2018-11-18 15:28:09,165 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:09,166 INFO L225 Difference]: With dead ends: 339 [2018-11-18 15:28:09,166 INFO L226 Difference]: Without dead ends: 330 [2018-11-18 15:28:09,167 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 284 GetRequests, 250 SyntacticMatches, 0 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 235 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=248, Invalid=1012, Unknown=0, NotChecked=0, Total=1260 [2018-11-18 15:28:09,167 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 330 states. [2018-11-18 15:28:09,171 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 330 to 294. [2018-11-18 15:28:09,171 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 294 states. [2018-11-18 15:28:09,172 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 294 states to 294 states and 300 transitions. [2018-11-18 15:28:09,172 INFO L78 Accepts]: Start accepts. Automaton has 294 states and 300 transitions. Word has length 260 [2018-11-18 15:28:09,172 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:09,172 INFO L480 AbstractCegarLoop]: Abstraction has 294 states and 300 transitions. [2018-11-18 15:28:09,173 INFO L481 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-11-18 15:28:09,173 INFO L276 IsEmpty]: Start isEmpty. Operand 294 states and 300 transitions. [2018-11-18 15:28:09,174 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 279 [2018-11-18 15:28:09,174 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:09,174 INFO L375 BasicCegarLoop]: trace histogram [38, 32, 32, 31, 31, 31, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:09,174 INFO L423 AbstractCegarLoop]: === Iteration 21 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:09,174 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:09,174 INFO L82 PathProgramCache]: Analyzing trace with hash 995818710, now seen corresponding path program 8 times [2018-11-18 15:28:09,175 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:09,175 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:09,175 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:09,175 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:09,175 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:09,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:09,473 INFO L134 CoverageAnalysis]: Checked inductivity of 3517 backedges. 1206 proven. 154 refuted. 0 times theorem prover too weak. 2157 trivial. 0 not checked. [2018-11-18 15:28:09,474 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:28:09,474 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:28:09,482 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-18 15:28:09,562 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 15:28:09,562 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:28:09,567 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:28:09,722 INFO L134 CoverageAnalysis]: Checked inductivity of 3517 backedges. 2271 proven. 70 refuted. 0 times theorem prover too weak. 1176 trivial. 0 not checked. [2018-11-18 15:28:09,737 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:28:09,737 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 14] total 25 [2018-11-18 15:28:09,738 INFO L459 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-11-18 15:28:09,738 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-11-18 15:28:09,738 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=102, Invalid=498, Unknown=0, NotChecked=0, Total=600 [2018-11-18 15:28:09,738 INFO L87 Difference]: Start difference. First operand 294 states and 300 transitions. Second operand 25 states. [2018-11-18 15:28:10,234 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:10,234 INFO L93 Difference]: Finished difference Result 348 states and 355 transitions. [2018-11-18 15:28:10,235 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-11-18 15:28:10,235 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 278 [2018-11-18 15:28:10,235 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:10,236 INFO L225 Difference]: With dead ends: 348 [2018-11-18 15:28:10,236 INFO L226 Difference]: Without dead ends: 339 [2018-11-18 15:28:10,236 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 306 GetRequests, 266 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 342 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=331, Invalid=1391, Unknown=0, NotChecked=0, Total=1722 [2018-11-18 15:28:10,237 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 339 states. [2018-11-18 15:28:10,240 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 339 to 306. [2018-11-18 15:28:10,240 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 306 states. [2018-11-18 15:28:10,241 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 306 states to 306 states and 311 transitions. [2018-11-18 15:28:10,241 INFO L78 Accepts]: Start accepts. Automaton has 306 states and 311 transitions. Word has length 278 [2018-11-18 15:28:10,242 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:10,242 INFO L480 AbstractCegarLoop]: Abstraction has 306 states and 311 transitions. [2018-11-18 15:28:10,242 INFO L481 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-11-18 15:28:10,242 INFO L276 IsEmpty]: Start isEmpty. Operand 306 states and 311 transitions. [2018-11-18 15:28:10,243 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 297 [2018-11-18 15:28:10,243 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:10,243 INFO L375 BasicCegarLoop]: trace histogram [41, 35, 35, 34, 34, 34, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:10,244 INFO L423 AbstractCegarLoop]: === Iteration 22 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:10,244 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:10,244 INFO L82 PathProgramCache]: Analyzing trace with hash 1300512094, now seen corresponding path program 9 times [2018-11-18 15:28:10,244 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:10,244 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:10,245 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:10,245 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:28:10,245 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:10,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:10,486 INFO L134 CoverageAnalysis]: Checked inductivity of 4141 backedges. 2791 proven. 393 refuted. 0 times theorem prover too weak. 957 trivial. 0 not checked. [2018-11-18 15:28:10,486 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:28:10,486 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:28:10,492 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 15:28:10,551 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 8 check-sat command(s) [2018-11-18 15:28:10,551 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:28:10,555 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:28:10,561 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 15:28:10,565 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 15:28:10,572 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 15:28:10,572 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 15:28:10,578 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 15:28:10,585 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 15:28:10,585 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 15:28:11,111 INFO L134 CoverageAnalysis]: Checked inductivity of 4141 backedges. 2019 proven. 448 refuted. 0 times theorem prover too weak. 1674 trivial. 0 not checked. [2018-11-18 15:28:11,126 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:28:11,127 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 18] total 37 [2018-11-18 15:28:11,127 INFO L459 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-11-18 15:28:11,127 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-11-18 15:28:11,127 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=178, Invalid=1154, Unknown=0, NotChecked=0, Total=1332 [2018-11-18 15:28:11,128 INFO L87 Difference]: Start difference. First operand 306 states and 311 transitions. Second operand 37 states. [2018-11-18 15:28:12,748 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:12,748 INFO L93 Difference]: Finished difference Result 369 states and 373 transitions. [2018-11-18 15:28:12,749 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2018-11-18 15:28:12,749 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 296 [2018-11-18 15:28:12,749 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:12,750 INFO L225 Difference]: With dead ends: 369 [2018-11-18 15:28:12,750 INFO L226 Difference]: Without dead ends: 314 [2018-11-18 15:28:12,752 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 361 GetRequests, 271 SyntacticMatches, 10 SemanticMatches, 80 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1996 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=1088, Invalid=5554, Unknown=0, NotChecked=0, Total=6642 [2018-11-18 15:28:12,752 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 314 states. [2018-11-18 15:28:12,755 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 314 to 306. [2018-11-18 15:28:12,755 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 306 states. [2018-11-18 15:28:12,759 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 306 states to 306 states and 309 transitions. [2018-11-18 15:28:12,759 INFO L78 Accepts]: Start accepts. Automaton has 306 states and 309 transitions. Word has length 296 [2018-11-18 15:28:12,759 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:12,759 INFO L480 AbstractCegarLoop]: Abstraction has 306 states and 309 transitions. [2018-11-18 15:28:12,759 INFO L481 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-11-18 15:28:12,760 INFO L276 IsEmpty]: Start isEmpty. Operand 306 states and 309 transitions. [2018-11-18 15:28:12,761 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 303 [2018-11-18 15:28:12,761 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:12,761 INFO L375 BasicCegarLoop]: trace histogram [42, 36, 36, 35, 35, 35, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:12,761 INFO L423 AbstractCegarLoop]: === Iteration 23 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:12,761 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:12,761 INFO L82 PathProgramCache]: Analyzing trace with hash -586720938, now seen corresponding path program 10 times [2018-11-18 15:28:12,762 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:12,762 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:12,762 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:12,762 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:28:12,762 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:12,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:12,983 INFO L134 CoverageAnalysis]: Checked inductivity of 4361 backedges. 1695 proven. 146 refuted. 0 times theorem prover too weak. 2520 trivial. 0 not checked. [2018-11-18 15:28:12,983 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:28:12,983 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:28:12,998 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 15:28:13,041 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 15:28:13,042 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:28:13,046 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:28:13,281 INFO L134 CoverageAnalysis]: Checked inductivity of 4361 backedges. 1618 proven. 628 refuted. 0 times theorem prover too weak. 2115 trivial. 0 not checked. [2018-11-18 15:28:13,296 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:28:13,297 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 23] total 34 [2018-11-18 15:28:13,297 INFO L459 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-11-18 15:28:13,297 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-11-18 15:28:13,298 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=223, Invalid=899, Unknown=0, NotChecked=0, Total=1122 [2018-11-18 15:28:13,298 INFO L87 Difference]: Start difference. First operand 306 states and 309 transitions. Second operand 34 states. [2018-11-18 15:28:13,799 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:13,799 INFO L93 Difference]: Finished difference Result 383 states and 387 transitions. [2018-11-18 15:28:13,799 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-11-18 15:28:13,799 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 302 [2018-11-18 15:28:13,799 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:13,800 INFO L225 Difference]: With dead ends: 383 [2018-11-18 15:28:13,800 INFO L226 Difference]: Without dead ends: 383 [2018-11-18 15:28:13,801 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 338 GetRequests, 289 SyntacticMatches, 0 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 473 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=549, Invalid=2001, Unknown=0, NotChecked=0, Total=2550 [2018-11-18 15:28:13,801 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 383 states. [2018-11-18 15:28:13,804 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 383 to 373. [2018-11-18 15:28:13,804 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 373 states. [2018-11-18 15:28:13,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 373 states to 373 states and 377 transitions. [2018-11-18 15:28:13,805 INFO L78 Accepts]: Start accepts. Automaton has 373 states and 377 transitions. Word has length 302 [2018-11-18 15:28:13,806 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:13,806 INFO L480 AbstractCegarLoop]: Abstraction has 373 states and 377 transitions. [2018-11-18 15:28:13,806 INFO L481 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-11-18 15:28:13,806 INFO L276 IsEmpty]: Start isEmpty. Operand 373 states and 377 transitions. [2018-11-18 15:28:13,808 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 358 [2018-11-18 15:28:13,808 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:13,808 INFO L375 BasicCegarLoop]: trace histogram [50, 43, 43, 42, 42, 42, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:13,808 INFO L423 AbstractCegarLoop]: === Iteration 24 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:13,808 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:13,808 INFO L82 PathProgramCache]: Analyzing trace with hash -2015619415, now seen corresponding path program 11 times [2018-11-18 15:28:13,808 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:13,809 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:13,809 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:13,809 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:28:13,809 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:13,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:14,153 INFO L134 CoverageAnalysis]: Checked inductivity of 6237 backedges. 3273 proven. 794 refuted. 0 times theorem prover too weak. 2170 trivial. 0 not checked. [2018-11-18 15:28:14,153 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:28:14,153 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:28:14,167 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-18 15:28:14,337 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 21 check-sat command(s) [2018-11-18 15:28:14,337 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:28:14,344 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:28:14,568 INFO L134 CoverageAnalysis]: Checked inductivity of 6237 backedges. 3278 proven. 789 refuted. 0 times theorem prover too weak. 2170 trivial. 0 not checked. [2018-11-18 15:28:14,584 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:28:14,584 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22] total 33 [2018-11-18 15:28:14,584 INFO L459 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-11-18 15:28:14,584 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-11-18 15:28:14,585 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=192, Invalid=864, Unknown=0, NotChecked=0, Total=1056 [2018-11-18 15:28:14,585 INFO L87 Difference]: Start difference. First operand 373 states and 377 transitions. Second operand 33 states. [2018-11-18 15:28:14,980 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:14,980 INFO L93 Difference]: Finished difference Result 384 states and 386 transitions. [2018-11-18 15:28:14,980 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-11-18 15:28:14,981 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 357 [2018-11-18 15:28:14,981 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:14,982 INFO L225 Difference]: With dead ends: 384 [2018-11-18 15:28:14,982 INFO L226 Difference]: Without dead ends: 378 [2018-11-18 15:28:14,983 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 397 GetRequests, 348 SyntacticMatches, 0 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 624 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=573, Invalid=1977, Unknown=0, NotChecked=0, Total=2550 [2018-11-18 15:28:14,983 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 378 states. [2018-11-18 15:28:14,986 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 378 to 373. [2018-11-18 15:28:14,986 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 373 states. [2018-11-18 15:28:14,987 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 373 states to 373 states and 375 transitions. [2018-11-18 15:28:14,987 INFO L78 Accepts]: Start accepts. Automaton has 373 states and 375 transitions. Word has length 357 [2018-11-18 15:28:14,987 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:14,987 INFO L480 AbstractCegarLoop]: Abstraction has 373 states and 375 transitions. [2018-11-18 15:28:14,987 INFO L481 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-11-18 15:28:14,987 INFO L276 IsEmpty]: Start isEmpty. Operand 373 states and 375 transitions. [2018-11-18 15:28:14,989 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 364 [2018-11-18 15:28:14,989 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:14,989 INFO L375 BasicCegarLoop]: trace histogram [51, 44, 44, 43, 43, 43, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:14,989 INFO L423 AbstractCegarLoop]: === Iteration 25 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:14,990 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:14,990 INFO L82 PathProgramCache]: Analyzing trace with hash 1640746593, now seen corresponding path program 12 times [2018-11-18 15:28:14,990 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:14,990 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:14,990 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:14,990 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:28:14,991 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:15,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:15,396 INFO L134 CoverageAnalysis]: Checked inductivity of 6507 backedges. 1953 proven. 200 refuted. 0 times theorem prover too weak. 4354 trivial. 0 not checked. [2018-11-18 15:28:15,396 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:28:15,397 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:28:15,403 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-18 15:28:15,592 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 17 check-sat command(s) [2018-11-18 15:28:15,592 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:28:15,598 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:28:15,600 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 15:28:15,602 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 15:28:15,607 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 15:28:15,607 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 15:28:15,614 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 15:28:15,620 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 15:28:15,620 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 15:28:15,860 INFO L134 CoverageAnalysis]: Checked inductivity of 6507 backedges. 1953 proven. 200 refuted. 0 times theorem prover too weak. 4354 trivial. 0 not checked. [2018-11-18 15:28:15,875 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:28:15,875 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 14] total 15 [2018-11-18 15:28:15,876 INFO L459 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-11-18 15:28:15,876 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-11-18 15:28:15,876 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=89, Invalid=151, Unknown=0, NotChecked=0, Total=240 [2018-11-18 15:28:15,876 INFO L87 Difference]: Start difference. First operand 373 states and 375 transitions. Second operand 16 states. [2018-11-18 15:28:16,060 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:16,060 INFO L93 Difference]: Finished difference Result 387 states and 390 transitions. [2018-11-18 15:28:16,060 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-18 15:28:16,060 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 363 [2018-11-18 15:28:16,061 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:16,062 INFO L225 Difference]: With dead ends: 387 [2018-11-18 15:28:16,062 INFO L226 Difference]: Without dead ends: 387 [2018-11-18 15:28:16,062 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 384 GetRequests, 345 SyntacticMatches, 16 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 99 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=216, Invalid=384, Unknown=0, NotChecked=0, Total=600 [2018-11-18 15:28:16,063 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 387 states. [2018-11-18 15:28:16,065 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 387 to 379. [2018-11-18 15:28:16,066 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 379 states. [2018-11-18 15:28:16,066 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 379 states to 379 states and 382 transitions. [2018-11-18 15:28:16,066 INFO L78 Accepts]: Start accepts. Automaton has 379 states and 382 transitions. Word has length 363 [2018-11-18 15:28:16,067 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:16,067 INFO L480 AbstractCegarLoop]: Abstraction has 379 states and 382 transitions. [2018-11-18 15:28:16,067 INFO L481 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-11-18 15:28:16,067 INFO L276 IsEmpty]: Start isEmpty. Operand 379 states and 382 transitions. [2018-11-18 15:28:16,069 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 370 [2018-11-18 15:28:16,069 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:16,069 INFO L375 BasicCegarLoop]: trace histogram [52, 45, 45, 44, 44, 44, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:16,069 INFO L423 AbstractCegarLoop]: === Iteration 26 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:16,069 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:16,069 INFO L82 PathProgramCache]: Analyzing trace with hash -1598402199, now seen corresponding path program 13 times [2018-11-18 15:28:16,070 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:16,070 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:16,070 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:16,070 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:28:16,070 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:16,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:16,331 INFO L134 CoverageAnalysis]: Checked inductivity of 6783 backedges. 2403 proven. 194 refuted. 0 times theorem prover too weak. 4186 trivial. 0 not checked. [2018-11-18 15:28:16,331 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:28:16,331 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:28:16,338 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:16,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:16,393 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:28:16,609 INFO L134 CoverageAnalysis]: Checked inductivity of 6783 backedges. 2429 proven. 168 refuted. 0 times theorem prover too weak. 4186 trivial. 0 not checked. [2018-11-18 15:28:16,624 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:28:16,624 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 21] total 33 [2018-11-18 15:28:16,624 INFO L459 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-11-18 15:28:16,625 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-11-18 15:28:16,625 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=254, Invalid=802, Unknown=0, NotChecked=0, Total=1056 [2018-11-18 15:28:16,625 INFO L87 Difference]: Start difference. First operand 379 states and 382 transitions. Second operand 33 states. [2018-11-18 15:28:16,984 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:16,984 INFO L93 Difference]: Finished difference Result 456 states and 460 transitions. [2018-11-18 15:28:16,984 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-11-18 15:28:16,984 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 369 [2018-11-18 15:28:16,985 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:16,985 INFO L225 Difference]: With dead ends: 456 [2018-11-18 15:28:16,985 INFO L226 Difference]: Without dead ends: 456 [2018-11-18 15:28:16,986 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 407 GetRequests, 359 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 371 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=659, Invalid=1791, Unknown=0, NotChecked=0, Total=2450 [2018-11-18 15:28:16,986 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 456 states. [2018-11-18 15:28:16,989 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 456 to 446. [2018-11-18 15:28:16,990 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 446 states. [2018-11-18 15:28:16,990 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 446 states to 446 states and 450 transitions. [2018-11-18 15:28:16,991 INFO L78 Accepts]: Start accepts. Automaton has 446 states and 450 transitions. Word has length 369 [2018-11-18 15:28:16,991 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:16,991 INFO L480 AbstractCegarLoop]: Abstraction has 446 states and 450 transitions. [2018-11-18 15:28:16,991 INFO L481 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-11-18 15:28:16,991 INFO L276 IsEmpty]: Start isEmpty. Operand 446 states and 450 transitions. [2018-11-18 15:28:16,993 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 431 [2018-11-18 15:28:16,993 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:16,993 INFO L375 BasicCegarLoop]: trace histogram [61, 53, 53, 52, 52, 52, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:16,994 INFO L423 AbstractCegarLoop]: === Iteration 27 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:16,994 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:16,994 INFO L82 PathProgramCache]: Analyzing trace with hash -762866562, now seen corresponding path program 14 times [2018-11-18 15:28:16,994 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:16,994 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:16,995 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:16,995 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:16,995 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:17,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:17,326 INFO L134 CoverageAnalysis]: Checked inductivity of 9408 backedges. 5831 proven. 669 refuted. 0 times theorem prover too weak. 2908 trivial. 0 not checked. [2018-11-18 15:28:17,326 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:28:17,326 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:28:17,332 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-18 15:28:17,405 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 15:28:17,405 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:28:17,409 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:28:17,640 INFO L134 CoverageAnalysis]: Checked inductivity of 9408 backedges. 4779 proven. 184 refuted. 0 times theorem prover too weak. 4445 trivial. 0 not checked. [2018-11-18 15:28:17,665 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:28:17,665 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 20] total 39 [2018-11-18 15:28:17,666 INFO L459 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-11-18 15:28:17,666 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-11-18 15:28:17,666 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=256, Invalid=1226, Unknown=0, NotChecked=0, Total=1482 [2018-11-18 15:28:17,666 INFO L87 Difference]: Start difference. First operand 446 states and 450 transitions. Second operand 39 states. [2018-11-18 15:28:18,361 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:18,361 INFO L93 Difference]: Finished difference Result 464 states and 466 transitions. [2018-11-18 15:28:18,361 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-11-18 15:28:18,361 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 430 [2018-11-18 15:28:18,361 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:18,362 INFO L225 Difference]: With dead ends: 464 [2018-11-18 15:28:18,362 INFO L226 Difference]: Without dead ends: 442 [2018-11-18 15:28:18,363 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 479 GetRequests, 417 SyntacticMatches, 0 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1109 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=731, Invalid=3301, Unknown=0, NotChecked=0, Total=4032 [2018-11-18 15:28:18,364 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 442 states. [2018-11-18 15:28:18,368 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 442 to 440. [2018-11-18 15:28:18,368 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 440 states. [2018-11-18 15:28:18,369 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 440 states to 440 states and 441 transitions. [2018-11-18 15:28:18,369 INFO L78 Accepts]: Start accepts. Automaton has 440 states and 441 transitions. Word has length 430 [2018-11-18 15:28:18,369 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:18,369 INFO L480 AbstractCegarLoop]: Abstraction has 440 states and 441 transitions. [2018-11-18 15:28:18,369 INFO L481 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-11-18 15:28:18,369 INFO L276 IsEmpty]: Start isEmpty. Operand 440 states and 441 transitions. [2018-11-18 15:28:18,371 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 437 [2018-11-18 15:28:18,371 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:18,372 INFO L375 BasicCegarLoop]: trace histogram [62, 54, 54, 53, 53, 53, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:18,372 INFO L423 AbstractCegarLoop]: === Iteration 28 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:18,372 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:18,372 INFO L82 PathProgramCache]: Analyzing trace with hash -1603398538, now seen corresponding path program 15 times [2018-11-18 15:28:18,372 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:18,372 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:18,373 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:18,373 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:28:18,373 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:18,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:18,727 INFO L134 CoverageAnalysis]: Checked inductivity of 9740 backedges. 2720 proven. 252 refuted. 0 times theorem prover too weak. 6768 trivial. 0 not checked. [2018-11-18 15:28:18,728 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:28:18,728 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:28:18,747 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 15:28:18,863 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2018-11-18 15:28:18,864 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:28:18,868 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:28:18,873 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 15:28:18,893 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 15:28:18,897 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 15:28:18,897 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 15:28:18,903 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 15:28:18,913 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 15:28:18,913 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 15:28:19,242 INFO L134 CoverageAnalysis]: Checked inductivity of 9740 backedges. 2720 proven. 252 refuted. 0 times theorem prover too weak. 6768 trivial. 0 not checked. [2018-11-18 15:28:19,258 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:28:19,259 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 15] total 16 [2018-11-18 15:28:19,259 INFO L459 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-11-18 15:28:19,259 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-11-18 15:28:19,259 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=102, Invalid=170, Unknown=0, NotChecked=0, Total=272 [2018-11-18 15:28:19,259 INFO L87 Difference]: Start difference. First operand 440 states and 441 transitions. Second operand 17 states. [2018-11-18 15:28:19,479 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:19,479 INFO L93 Difference]: Finished difference Result 451 states and 453 transitions. [2018-11-18 15:28:19,479 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-11-18 15:28:19,479 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 436 [2018-11-18 15:28:19,480 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:19,481 INFO L225 Difference]: With dead ends: 451 [2018-11-18 15:28:19,481 INFO L226 Difference]: Without dead ends: 451 [2018-11-18 15:28:19,481 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 459 GetRequests, 416 SyntacticMatches, 18 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 116 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=253, Invalid=449, Unknown=0, NotChecked=0, Total=702 [2018-11-18 15:28:19,481 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 451 states. [2018-11-18 15:28:19,485 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 451 to 446. [2018-11-18 15:28:19,485 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 446 states. [2018-11-18 15:28:19,486 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 446 states to 446 states and 448 transitions. [2018-11-18 15:28:19,486 INFO L78 Accepts]: Start accepts. Automaton has 446 states and 448 transitions. Word has length 436 [2018-11-18 15:28:19,487 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:19,487 INFO L480 AbstractCegarLoop]: Abstraction has 446 states and 448 transitions. [2018-11-18 15:28:19,487 INFO L481 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-11-18 15:28:19,487 INFO L276 IsEmpty]: Start isEmpty. Operand 446 states and 448 transitions. [2018-11-18 15:28:19,489 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 443 [2018-11-18 15:28:19,489 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:19,489 INFO L375 BasicCegarLoop]: trace histogram [63, 55, 55, 54, 54, 54, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:19,489 INFO L423 AbstractCegarLoop]: === Iteration 29 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:19,489 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:19,490 INFO L82 PathProgramCache]: Analyzing trace with hash 687010750, now seen corresponding path program 16 times [2018-11-18 15:28:19,490 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:19,490 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:19,490 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:19,490 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:28:19,490 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:19,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:19,761 INFO L134 CoverageAnalysis]: Checked inductivity of 10078 backedges. 3281 proven. 249 refuted. 0 times theorem prover too weak. 6548 trivial. 0 not checked. [2018-11-18 15:28:19,761 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:28:19,761 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:28:19,767 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 15:28:19,830 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 15:28:19,831 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:28:19,835 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:28:20,143 INFO L134 CoverageAnalysis]: Checked inductivity of 10078 backedges. 3188 proven. 1003 refuted. 0 times theorem prover too weak. 5887 trivial. 0 not checked. [2018-11-18 15:28:20,158 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:28:20,158 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 27] total 40 [2018-11-18 15:28:20,159 INFO L459 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-11-18 15:28:20,159 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-11-18 15:28:20,160 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=313, Invalid=1247, Unknown=0, NotChecked=0, Total=1560 [2018-11-18 15:28:20,160 INFO L87 Difference]: Start difference. First operand 446 states and 448 transitions. Second operand 40 states. [2018-11-18 15:28:20,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:20,724 INFO L93 Difference]: Finished difference Result 526 states and 529 transitions. [2018-11-18 15:28:20,724 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-11-18 15:28:20,725 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 442 [2018-11-18 15:28:20,725 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:20,725 INFO L225 Difference]: With dead ends: 526 [2018-11-18 15:28:20,726 INFO L226 Difference]: Without dead ends: 526 [2018-11-18 15:28:20,726 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 486 GetRequests, 427 SyntacticMatches, 0 SemanticMatches, 59 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 686 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=793, Invalid=2867, Unknown=0, NotChecked=0, Total=3660 [2018-11-18 15:28:20,726 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 526 states. [2018-11-18 15:28:20,730 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 526 to 519. [2018-11-18 15:28:20,730 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 519 states. [2018-11-18 15:28:20,731 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 519 states to 519 states and 522 transitions. [2018-11-18 15:28:20,731 INFO L78 Accepts]: Start accepts. Automaton has 519 states and 522 transitions. Word has length 442 [2018-11-18 15:28:20,732 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:20,732 INFO L480 AbstractCegarLoop]: Abstraction has 519 states and 522 transitions. [2018-11-18 15:28:20,732 INFO L481 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-11-18 15:28:20,732 INFO L276 IsEmpty]: Start isEmpty. Operand 519 states and 522 transitions. [2018-11-18 15:28:20,734 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 510 [2018-11-18 15:28:20,735 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:20,735 INFO L375 BasicCegarLoop]: trace histogram [73, 64, 64, 63, 63, 63, 10, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:20,735 INFO L423 AbstractCegarLoop]: === Iteration 30 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:20,735 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:20,735 INFO L82 PathProgramCache]: Analyzing trace with hash -1608566959, now seen corresponding path program 17 times [2018-11-18 15:28:20,735 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:20,735 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:20,736 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:20,736 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:28:20,736 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:20,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:21,063 INFO L134 CoverageAnalysis]: Checked inductivity of 13626 backedges. 3599 proven. 299 refuted. 0 times theorem prover too weak. 9728 trivial. 0 not checked. [2018-11-18 15:28:21,063 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:28:21,063 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:28:21,070 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-18 15:28:21,262 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 24 check-sat command(s) [2018-11-18 15:28:21,262 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:28:21,267 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:28:21,691 INFO L134 CoverageAnalysis]: Checked inductivity of 13626 backedges. 6393 proven. 1285 refuted. 0 times theorem prover too weak. 5948 trivial. 0 not checked. [2018-11-18 15:28:21,707 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:28:21,707 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 26] total 40 [2018-11-18 15:28:21,708 INFO L459 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-11-18 15:28:21,708 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-11-18 15:28:21,708 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=202, Invalid=1358, Unknown=0, NotChecked=0, Total=1560 [2018-11-18 15:28:21,708 INFO L87 Difference]: Start difference. First operand 519 states and 522 transitions. Second operand 40 states. [2018-11-18 15:28:23,237 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:23,237 INFO L93 Difference]: Finished difference Result 616 states and 619 transitions. [2018-11-18 15:28:23,237 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2018-11-18 15:28:23,237 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 509 [2018-11-18 15:28:23,238 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:23,239 INFO L225 Difference]: With dead ends: 616 [2018-11-18 15:28:23,239 INFO L226 Difference]: Without dead ends: 607 [2018-11-18 15:28:23,240 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 573 GetRequests, 486 SyntacticMatches, 0 SemanticMatches, 87 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1935 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=1189, Invalid=6643, Unknown=0, NotChecked=0, Total=7832 [2018-11-18 15:28:23,241 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 607 states. [2018-11-18 15:28:23,245 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 607 to 592. [2018-11-18 15:28:23,245 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 592 states. [2018-11-18 15:28:23,246 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 592 states to 592 states and 594 transitions. [2018-11-18 15:28:23,247 INFO L78 Accepts]: Start accepts. Automaton has 592 states and 594 transitions. Word has length 509 [2018-11-18 15:28:23,247 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:23,247 INFO L480 AbstractCegarLoop]: Abstraction has 592 states and 594 transitions. [2018-11-18 15:28:23,247 INFO L481 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-11-18 15:28:23,247 INFO L276 IsEmpty]: Start isEmpty. Operand 592 states and 594 transitions. [2018-11-18 15:28:23,250 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 589 [2018-11-18 15:28:23,250 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:23,251 INFO L375 BasicCegarLoop]: trace histogram [85, 75, 75, 74, 74, 74, 11, 11, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:23,251 INFO L423 AbstractCegarLoop]: === Iteration 31 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:23,251 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:23,251 INFO L82 PathProgramCache]: Analyzing trace with hash 1489211422, now seen corresponding path program 18 times [2018-11-18 15:28:23,251 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:23,251 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:23,252 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:23,252 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:28:23,252 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:23,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:23,787 INFO L134 CoverageAnalysis]: Checked inductivity of 18627 backedges. 10515 proven. 1017 refuted. 0 times theorem prover too weak. 7095 trivial. 0 not checked. [2018-11-18 15:28:23,788 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:28:23,788 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:28:23,794 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-18 15:28:24,118 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 21 check-sat command(s) [2018-11-18 15:28:24,119 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:28:24,125 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:28:24,129 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 15:28:24,131 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 15:28:24,135 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 15:28:24,136 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 15:28:24,142 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 15:28:24,149 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 15:28:24,149 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 15:28:25,139 INFO L134 CoverageAnalysis]: Checked inductivity of 18627 backedges. 4326 proven. 310 refuted. 0 times theorem prover too weak. 13991 trivial. 0 not checked. [2018-11-18 15:28:25,155 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:28:25,155 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 16] total 43 [2018-11-18 15:28:25,156 INFO L459 AbstractCegarLoop]: Interpolant automaton has 43 states [2018-11-18 15:28:25,156 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2018-11-18 15:28:25,156 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=254, Invalid=1552, Unknown=0, NotChecked=0, Total=1806 [2018-11-18 15:28:25,157 INFO L87 Difference]: Start difference. First operand 592 states and 594 transitions. Second operand 43 states. [2018-11-18 15:28:26,484 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:26,484 INFO L93 Difference]: Finished difference Result 616 states and 618 transitions. [2018-11-18 15:28:26,485 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-11-18 15:28:26,485 INFO L78 Accepts]: Start accepts. Automaton has 43 states. Word has length 588 [2018-11-18 15:28:26,485 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:26,486 INFO L225 Difference]: With dead ends: 616 [2018-11-18 15:28:26,486 INFO L226 Difference]: Without dead ends: 610 [2018-11-18 15:28:26,486 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 650 GetRequests, 556 SyntacticMatches, 19 SemanticMatches, 75 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1559 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=1058, Invalid=4794, Unknown=0, NotChecked=0, Total=5852 [2018-11-18 15:28:26,486 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 610 states. [2018-11-18 15:28:26,490 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 610 to 604. [2018-11-18 15:28:26,490 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 604 states. [2018-11-18 15:28:26,492 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 604 states to 604 states and 606 transitions. [2018-11-18 15:28:26,492 INFO L78 Accepts]: Start accepts. Automaton has 604 states and 606 transitions. Word has length 588 [2018-11-18 15:28:26,492 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:26,492 INFO L480 AbstractCegarLoop]: Abstraction has 604 states and 606 transitions. [2018-11-18 15:28:26,492 INFO L481 AbstractCegarLoop]: Interpolant automaton has 43 states. [2018-11-18 15:28:26,494 INFO L276 IsEmpty]: Start isEmpty. Operand 604 states and 606 transitions. [2018-11-18 15:28:26,497 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 601 [2018-11-18 15:28:26,497 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:26,498 INFO L375 BasicCegarLoop]: trace histogram [87, 77, 77, 76, 76, 76, 11, 11, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:26,498 INFO L423 AbstractCegarLoop]: === Iteration 32 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:26,498 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:26,498 INFO L82 PathProgramCache]: Analyzing trace with hash 296860510, now seen corresponding path program 19 times [2018-11-18 15:28:26,498 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:26,498 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:26,499 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:26,499 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:28:26,499 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:26,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:26,939 INFO L134 CoverageAnalysis]: Checked inductivity of 19569 backedges. 4800 proven. 374 refuted. 0 times theorem prover too weak. 14395 trivial. 0 not checked. [2018-11-18 15:28:26,940 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:28:26,940 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:28:26,946 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:27,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:27,032 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:28:27,035 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 15:28:27,037 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 15:28:27,055 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 15:28:27,055 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 15:28:27,061 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 15:28:27,068 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 15:28:27,068 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 15:28:27,813 INFO L134 CoverageAnalysis]: Checked inductivity of 19569 backedges. 4800 proven. 374 refuted. 0 times theorem prover too weak. 14395 trivial. 0 not checked. [2018-11-18 15:28:27,837 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:28:27,837 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16] total 28 [2018-11-18 15:28:27,838 INFO L459 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-11-18 15:28:27,838 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-11-18 15:28:27,838 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=226, Invalid=586, Unknown=0, NotChecked=0, Total=812 [2018-11-18 15:28:27,838 INFO L87 Difference]: Start difference. First operand 604 states and 606 transitions. Second operand 29 states. [2018-11-18 15:28:28,478 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:28,478 INFO L93 Difference]: Finished difference Result 628 states and 632 transitions. [2018-11-18 15:28:28,479 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-11-18 15:28:28,479 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 600 [2018-11-18 15:28:28,479 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:28,480 INFO L225 Difference]: With dead ends: 628 [2018-11-18 15:28:28,480 INFO L226 Difference]: Without dead ends: 628 [2018-11-18 15:28:28,481 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 627 GetRequests, 566 SyntacticMatches, 22 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 441 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=375, Invalid=1265, Unknown=0, NotChecked=0, Total=1640 [2018-11-18 15:28:28,481 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 628 states. [2018-11-18 15:28:28,485 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 628 to 610. [2018-11-18 15:28:28,485 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 610 states. [2018-11-18 15:28:28,486 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 610 states to 610 states and 613 transitions. [2018-11-18 15:28:28,486 INFO L78 Accepts]: Start accepts. Automaton has 610 states and 613 transitions. Word has length 600 [2018-11-18 15:28:28,487 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:28,487 INFO L480 AbstractCegarLoop]: Abstraction has 610 states and 613 transitions. [2018-11-18 15:28:28,487 INFO L481 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-11-18 15:28:28,487 INFO L276 IsEmpty]: Start isEmpty. Operand 610 states and 613 transitions. [2018-11-18 15:28:28,490 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 607 [2018-11-18 15:28:28,490 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:28,491 INFO L375 BasicCegarLoop]: trace histogram [88, 78, 78, 77, 77, 77, 11, 11, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:28,491 INFO L423 AbstractCegarLoop]: === Iteration 33 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:28,491 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:28,491 INFO L82 PathProgramCache]: Analyzing trace with hash -1761096538, now seen corresponding path program 20 times [2018-11-18 15:28:28,491 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:28,491 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:28,492 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:28,492 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:28,492 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:28,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:28,844 INFO L134 CoverageAnalysis]: Checked inductivity of 20049 backedges. 5619 proven. 380 refuted. 0 times theorem prover too weak. 14050 trivial. 0 not checked. [2018-11-18 15:28:28,844 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:28:28,845 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:28:28,851 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-18 15:28:28,931 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 15:28:28,932 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:28:28,936 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:28:29,326 INFO L134 CoverageAnalysis]: Checked inductivity of 20049 backedges. 5654 proven. 345 refuted. 0 times theorem prover too weak. 14050 trivial. 0 not checked. [2018-11-18 15:28:29,341 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:28:29,341 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 27] total 42 [2018-11-18 15:28:29,342 INFO L459 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-11-18 15:28:29,342 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-11-18 15:28:29,342 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=407, Invalid=1315, Unknown=0, NotChecked=0, Total=1722 [2018-11-18 15:28:29,342 INFO L87 Difference]: Start difference. First operand 610 states and 613 transitions. Second operand 42 states. [2018-11-18 15:28:29,753 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:29,753 INFO L93 Difference]: Finished difference Result 711 states and 715 transitions. [2018-11-18 15:28:29,753 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-11-18 15:28:29,754 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 606 [2018-11-18 15:28:29,754 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:29,755 INFO L225 Difference]: With dead ends: 711 [2018-11-18 15:28:29,755 INFO L226 Difference]: Without dead ends: 711 [2018-11-18 15:28:29,755 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 656 GetRequests, 593 SyntacticMatches, 0 SemanticMatches, 63 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 659 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1094, Invalid=3066, Unknown=0, NotChecked=0, Total=4160 [2018-11-18 15:28:29,755 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2018-11-18 15:28:29,759 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 701. [2018-11-18 15:28:29,759 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 701 states. [2018-11-18 15:28:29,761 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 701 states to 701 states and 705 transitions. [2018-11-18 15:28:29,761 INFO L78 Accepts]: Start accepts. Automaton has 701 states and 705 transitions. Word has length 606 [2018-11-18 15:28:29,761 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:29,761 INFO L480 AbstractCegarLoop]: Abstraction has 701 states and 705 transitions. [2018-11-18 15:28:29,761 INFO L481 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-11-18 15:28:29,761 INFO L276 IsEmpty]: Start isEmpty. Operand 701 states and 705 transitions. [2018-11-18 15:28:29,765 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 686 [2018-11-18 15:28:29,765 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:29,766 INFO L375 BasicCegarLoop]: trace histogram [100, 89, 89, 88, 88, 88, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:29,766 INFO L423 AbstractCegarLoop]: === Iteration 34 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:29,766 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:29,766 INFO L82 PathProgramCache]: Analyzing trace with hash 1710123385, now seen corresponding path program 21 times [2018-11-18 15:28:29,766 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:29,766 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:29,767 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:29,767 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:28:29,767 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:29,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:30,199 INFO L134 CoverageAnalysis]: Checked inductivity of 26037 backedges. 11003 proven. 1890 refuted. 0 times theorem prover too weak. 13144 trivial. 0 not checked. [2018-11-18 15:28:30,199 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:28:30,199 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:28:30,205 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 15:28:30,336 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 13 check-sat command(s) [2018-11-18 15:28:30,336 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:28:30,341 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:28:30,872 INFO L134 CoverageAnalysis]: Checked inductivity of 26037 backedges. 10440 proven. 1192 refuted. 0 times theorem prover too weak. 14405 trivial. 0 not checked. [2018-11-18 15:28:30,887 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:28:30,888 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 31] total 58 [2018-11-18 15:28:30,888 INFO L459 AbstractCegarLoop]: Interpolant automaton has 58 states [2018-11-18 15:28:30,888 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 58 interpolants. [2018-11-18 15:28:30,888 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=462, Invalid=2844, Unknown=0, NotChecked=0, Total=3306 [2018-11-18 15:28:30,888 INFO L87 Difference]: Start difference. First operand 701 states and 705 transitions. Second operand 58 states. [2018-11-18 15:28:32,195 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:32,195 INFO L93 Difference]: Finished difference Result 804 states and 806 transitions. [2018-11-18 15:28:32,195 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2018-11-18 15:28:32,195 INFO L78 Accepts]: Start accepts. Automaton has 58 states. Word has length 685 [2018-11-18 15:28:32,195 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:32,196 INFO L225 Difference]: With dead ends: 804 [2018-11-18 15:28:32,196 INFO L226 Difference]: Without dead ends: 795 [2018-11-18 15:28:32,197 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 776 GetRequests, 659 SyntacticMatches, 0 SemanticMatches, 117 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4573 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=1995, Invalid=12047, Unknown=0, NotChecked=0, Total=14042 [2018-11-18 15:28:32,197 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 795 states. [2018-11-18 15:28:32,200 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 795 to 701. [2018-11-18 15:28:32,200 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 701 states. [2018-11-18 15:28:32,202 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 701 states to 701 states and 703 transitions. [2018-11-18 15:28:32,202 INFO L78 Accepts]: Start accepts. Automaton has 701 states and 703 transitions. Word has length 685 [2018-11-18 15:28:32,202 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:32,202 INFO L480 AbstractCegarLoop]: Abstraction has 701 states and 703 transitions. [2018-11-18 15:28:32,202 INFO L481 AbstractCegarLoop]: Interpolant automaton has 58 states. [2018-11-18 15:28:32,202 INFO L276 IsEmpty]: Start isEmpty. Operand 701 states and 703 transitions. [2018-11-18 15:28:32,206 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 692 [2018-11-18 15:28:32,206 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:32,207 INFO L375 BasicCegarLoop]: trace histogram [101, 90, 90, 89, 89, 89, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:32,207 INFO L423 AbstractCegarLoop]: === Iteration 35 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:32,207 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:32,207 INFO L82 PathProgramCache]: Analyzing trace with hash -1390430927, now seen corresponding path program 22 times [2018-11-18 15:28:32,207 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:32,207 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:32,208 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:32,208 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:28:32,208 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:32,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:32,762 INFO L134 CoverageAnalysis]: Checked inductivity of 26591 backedges. 6149 proven. 444 refuted. 0 times theorem prover too weak. 19998 trivial. 0 not checked. [2018-11-18 15:28:32,762 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:28:32,763 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:28:32,769 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 15:28:32,901 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 15:28:32,901 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:28:32,908 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:28:32,910 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 15:28:32,912 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 15:28:32,915 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 15:28:32,916 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 15:28:32,920 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 15:28:32,926 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 15:28:32,927 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 15:28:33,697 INFO L134 CoverageAnalysis]: Checked inductivity of 26591 backedges. 6149 proven. 444 refuted. 0 times theorem prover too weak. 19998 trivial. 0 not checked. [2018-11-18 15:28:33,713 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:28:33,713 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17] total 30 [2018-11-18 15:28:33,713 INFO L459 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-11-18 15:28:33,713 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-11-18 15:28:33,713 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=257, Invalid=673, Unknown=0, NotChecked=0, Total=930 [2018-11-18 15:28:33,714 INFO L87 Difference]: Start difference. First operand 701 states and 703 transitions. Second operand 31 states. [2018-11-18 15:28:34,274 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:34,274 INFO L93 Difference]: Finished difference Result 715 states and 718 transitions. [2018-11-18 15:28:34,274 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-11-18 15:28:34,274 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 691 [2018-11-18 15:28:34,275 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:34,275 INFO L225 Difference]: With dead ends: 715 [2018-11-18 15:28:34,275 INFO L226 Difference]: Without dead ends: 715 [2018-11-18 15:28:34,276 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 720 GetRequests, 654 SyntacticMatches, 24 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 517 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=425, Invalid=1467, Unknown=0, NotChecked=0, Total=1892 [2018-11-18 15:28:34,276 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 715 states. [2018-11-18 15:28:34,278 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 715 to 707. [2018-11-18 15:28:34,279 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 707 states. [2018-11-18 15:28:34,280 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 707 states to 707 states and 710 transitions. [2018-11-18 15:28:34,280 INFO L78 Accepts]: Start accepts. Automaton has 707 states and 710 transitions. Word has length 691 [2018-11-18 15:28:34,280 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:34,280 INFO L480 AbstractCegarLoop]: Abstraction has 707 states and 710 transitions. [2018-11-18 15:28:34,280 INFO L481 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-11-18 15:28:34,281 INFO L276 IsEmpty]: Start isEmpty. Operand 707 states and 710 transitions. [2018-11-18 15:28:34,283 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 698 [2018-11-18 15:28:34,283 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:34,284 INFO L375 BasicCegarLoop]: trace histogram [102, 91, 91, 90, 90, 90, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:34,284 INFO L423 AbstractCegarLoop]: === Iteration 36 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:34,284 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:34,284 INFO L82 PathProgramCache]: Analyzing trace with hash -1239819207, now seen corresponding path program 23 times [2018-11-18 15:28:34,284 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:34,284 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:34,285 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:34,285 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:28:34,285 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:34,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:34,692 INFO L134 CoverageAnalysis]: Checked inductivity of 27151 backedges. 7115 proven. 456 refuted. 0 times theorem prover too weak. 19580 trivial. 0 not checked. [2018-11-18 15:28:34,692 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:28:34,692 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:28:34,698 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-18 15:28:35,227 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 27 check-sat command(s) [2018-11-18 15:28:35,227 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:28:35,234 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:28:35,668 INFO L134 CoverageAnalysis]: Checked inductivity of 27151 backedges. 6998 proven. 1723 refuted. 0 times theorem prover too weak. 18430 trivial. 0 not checked. [2018-11-18 15:28:35,684 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:28:35,685 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 34] total 49 [2018-11-18 15:28:35,685 INFO L459 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-11-18 15:28:35,686 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-11-18 15:28:35,686 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=478, Invalid=1874, Unknown=0, NotChecked=0, Total=2352 [2018-11-18 15:28:35,686 INFO L87 Difference]: Start difference. First operand 707 states and 710 transitions. Second operand 49 states. [2018-11-18 15:28:36,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:36,482 INFO L93 Difference]: Finished difference Result 808 states and 812 transitions. [2018-11-18 15:28:36,482 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-11-18 15:28:36,482 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 697 [2018-11-18 15:28:36,482 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:36,483 INFO L225 Difference]: With dead ends: 808 [2018-11-18 15:28:36,483 INFO L226 Difference]: Without dead ends: 808 [2018-11-18 15:28:36,484 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 753 GetRequests, 679 SyntacticMatches, 0 SemanticMatches, 74 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1073 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1249, Invalid=4451, Unknown=0, NotChecked=0, Total=5700 [2018-11-18 15:28:36,484 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 808 states. [2018-11-18 15:28:36,488 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 808 to 798. [2018-11-18 15:28:36,488 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 798 states. [2018-11-18 15:28:36,490 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 798 states to 798 states and 802 transitions. [2018-11-18 15:28:36,490 INFO L78 Accepts]: Start accepts. Automaton has 798 states and 802 transitions. Word has length 697 [2018-11-18 15:28:36,490 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:36,490 INFO L480 AbstractCegarLoop]: Abstraction has 798 states and 802 transitions. [2018-11-18 15:28:36,490 INFO L481 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-11-18 15:28:36,491 INFO L276 IsEmpty]: Start isEmpty. Operand 798 states and 802 transitions. [2018-11-18 15:28:36,496 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 783 [2018-11-18 15:28:36,496 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:36,496 INFO L375 BasicCegarLoop]: trace histogram [115, 103, 103, 102, 102, 102, 13, 13, 13, 13, 12, 12, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:36,496 INFO L423 AbstractCegarLoop]: === Iteration 37 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:36,496 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:36,496 INFO L82 PathProgramCache]: Analyzing trace with hash 1031851214, now seen corresponding path program 24 times [2018-11-18 15:28:36,496 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:36,496 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:36,497 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:36,497 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:28:36,497 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:36,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:36,993 INFO L134 CoverageAnalysis]: Checked inductivity of 34692 backedges. 18319 proven. 1437 refuted. 0 times theorem prover too weak. 14936 trivial. 0 not checked. [2018-11-18 15:28:36,993 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:28:36,993 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:28:37,000 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-18 15:28:37,560 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 22 check-sat command(s) [2018-11-18 15:28:37,560 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:28:37,567 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:28:37,569 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 15:28:37,580 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 15:28:37,587 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 15:28:37,587 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 15:28:37,592 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 15:28:37,598 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 15:28:37,599 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:16, output treesize:30 [2018-11-18 15:28:38,997 INFO L134 CoverageAnalysis]: Checked inductivity of 34692 backedges. 7646 proven. 524 refuted. 0 times theorem prover too weak. 26522 trivial. 0 not checked. [2018-11-18 15:28:39,013 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:28:39,013 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 19] total 50 [2018-11-18 15:28:39,014 INFO L459 AbstractCegarLoop]: Interpolant automaton has 50 states [2018-11-18 15:28:39,014 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2018-11-18 15:28:39,014 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=338, Invalid=2112, Unknown=0, NotChecked=0, Total=2450 [2018-11-18 15:28:39,014 INFO L87 Difference]: Start difference. First operand 798 states and 802 transitions. Second operand 50 states. [2018-11-18 15:28:41,249 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:41,249 INFO L93 Difference]: Finished difference Result 917 states and 920 transitions. [2018-11-18 15:28:41,249 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2018-11-18 15:28:41,250 INFO L78 Accepts]: Start accepts. Automaton has 50 states. Word has length 782 [2018-11-18 15:28:41,250 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:41,251 INFO L225 Difference]: With dead ends: 917 [2018-11-18 15:28:41,251 INFO L226 Difference]: Without dead ends: 899 [2018-11-18 15:28:41,252 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 866 GetRequests, 743 SyntacticMatches, 23 SemanticMatches, 100 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2925 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=1461, Invalid=8841, Unknown=0, NotChecked=0, Total=10302 [2018-11-18 15:28:41,252 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 899 states. [2018-11-18 15:28:41,258 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 899 to 883. [2018-11-18 15:28:41,258 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 883 states. [2018-11-18 15:28:41,258 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 883 states to 883 states and 885 transitions. [2018-11-18 15:28:41,259 INFO L78 Accepts]: Start accepts. Automaton has 883 states and 885 transitions. Word has length 782 [2018-11-18 15:28:41,259 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:41,259 INFO L480 AbstractCegarLoop]: Abstraction has 883 states and 885 transitions. [2018-11-18 15:28:41,259 INFO L481 AbstractCegarLoop]: Interpolant automaton has 50 states. [2018-11-18 15:28:41,259 INFO L276 IsEmpty]: Start isEmpty. Operand 883 states and 885 transitions. [2018-11-18 15:28:41,265 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 880 [2018-11-18 15:28:41,265 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:41,265 INFO L375 BasicCegarLoop]: trace histogram [130, 117, 117, 116, 116, 116, 14, 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:41,265 INFO L423 AbstractCegarLoop]: === Iteration 38 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:41,265 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:41,266 INFO L82 PathProgramCache]: Analyzing trace with hash 319312921, now seen corresponding path program 25 times [2018-11-18 15:28:41,266 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:41,266 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:41,266 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:41,266 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:28:41,266 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:41,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:41,853 INFO L134 CoverageAnalysis]: Checked inductivity of 44592 backedges. 16762 proven. 2594 refuted. 0 times theorem prover too weak. 25236 trivial. 0 not checked. [2018-11-18 15:28:41,853 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:28:41,853 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:28:41,859 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:41,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:41,977 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:28:42,407 INFO L134 CoverageAnalysis]: Checked inductivity of 44592 backedges. 16980 proven. 494 refuted. 0 times theorem prover too weak. 27118 trivial. 0 not checked. [2018-11-18 15:28:42,423 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:28:42,423 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 30] total 49 [2018-11-18 15:28:42,423 INFO L459 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-11-18 15:28:42,423 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-11-18 15:28:42,423 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=476, Invalid=1876, Unknown=0, NotChecked=0, Total=2352 [2018-11-18 15:28:42,424 INFO L87 Difference]: Start difference. First operand 883 states and 885 transitions. Second operand 49 states. [2018-11-18 15:28:43,227 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:43,227 INFO L93 Difference]: Finished difference Result 908 states and 910 transitions. [2018-11-18 15:28:43,227 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2018-11-18 15:28:43,227 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 879 [2018-11-18 15:28:43,227 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:43,228 INFO L225 Difference]: With dead ends: 908 [2018-11-18 15:28:43,229 INFO L226 Difference]: Without dead ends: 902 [2018-11-18 15:28:43,229 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 944 GetRequests, 867 SyntacticMatches, 0 SemanticMatches, 77 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1829 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1346, Invalid=4816, Unknown=0, NotChecked=0, Total=6162 [2018-11-18 15:28:43,229 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 902 states. [2018-11-18 15:28:43,233 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 902 to 893. [2018-11-18 15:28:43,233 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 893 states. [2018-11-18 15:28:43,234 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 893 states to 893 states and 895 transitions. [2018-11-18 15:28:43,234 INFO L78 Accepts]: Start accepts. Automaton has 893 states and 895 transitions. Word has length 879 [2018-11-18 15:28:43,234 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:43,234 INFO L480 AbstractCegarLoop]: Abstraction has 893 states and 895 transitions. [2018-11-18 15:28:43,234 INFO L481 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-11-18 15:28:43,234 INFO L276 IsEmpty]: Start isEmpty. Operand 893 states and 895 transitions. [2018-11-18 15:28:43,237 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 886 [2018-11-18 15:28:43,237 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:43,237 INFO L375 BasicCegarLoop]: trace histogram [131, 118, 118, 117, 117, 117, 14, 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:43,238 INFO L423 AbstractCegarLoop]: === Iteration 39 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:43,238 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:43,238 INFO L82 PathProgramCache]: Analyzing trace with hash 1313629137, now seen corresponding path program 26 times [2018-11-18 15:28:43,238 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:43,238 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:43,238 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:43,238 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:43,238 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:43,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:43,841 INFO L134 CoverageAnalysis]: Checked inductivity of 45318 backedges. 8905 proven. 520 refuted. 0 times theorem prover too weak. 35893 trivial. 0 not checked. [2018-11-18 15:28:43,841 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:28:43,841 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:28:43,848 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-18 15:28:43,965 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 15:28:43,965 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:28:43,973 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:28:43,975 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 15:28:43,984 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 15:28:43,991 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 15:28:43,991 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 15:28:43,996 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 15:28:44,003 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 15:28:44,003 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 15:28:45,061 INFO L134 CoverageAnalysis]: Checked inductivity of 45318 backedges. 8905 proven. 520 refuted. 0 times theorem prover too weak. 35893 trivial. 0 not checked. [2018-11-18 15:28:45,076 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:28:45,077 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18] total 32 [2018-11-18 15:28:45,077 INFO L459 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-11-18 15:28:45,077 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-11-18 15:28:45,077 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=290, Invalid=766, Unknown=0, NotChecked=0, Total=1056 [2018-11-18 15:28:45,077 INFO L87 Difference]: Start difference. First operand 893 states and 895 transitions. Second operand 33 states. [2018-11-18 15:28:45,712 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:45,712 INFO L93 Difference]: Finished difference Result 901 states and 903 transitions. [2018-11-18 15:28:45,712 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-11-18 15:28:45,712 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 885 [2018-11-18 15:28:45,713 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:45,714 INFO L225 Difference]: With dead ends: 901 [2018-11-18 15:28:45,714 INFO L226 Difference]: Without dead ends: 901 [2018-11-18 15:28:45,715 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 916 GetRequests, 843 SyntacticMatches, 28 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 602 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=478, Invalid=1684, Unknown=0, NotChecked=0, Total=2162 [2018-11-18 15:28:45,715 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 901 states. [2018-11-18 15:28:45,719 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 901 to 895. [2018-11-18 15:28:45,719 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 895 states. [2018-11-18 15:28:45,720 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 895 states to 895 states and 897 transitions. [2018-11-18 15:28:45,720 INFO L78 Accepts]: Start accepts. Automaton has 895 states and 897 transitions. Word has length 885 [2018-11-18 15:28:45,721 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:45,721 INFO L480 AbstractCegarLoop]: Abstraction has 895 states and 897 transitions. [2018-11-18 15:28:45,721 INFO L481 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-11-18 15:28:45,721 INFO L276 IsEmpty]: Start isEmpty. Operand 895 states and 897 transitions. [2018-11-18 15:28:45,725 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 892 [2018-11-18 15:28:45,725 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:45,725 INFO L375 BasicCegarLoop]: trace histogram [132, 119, 119, 118, 118, 118, 14, 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:45,725 INFO L423 AbstractCegarLoop]: === Iteration 40 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:45,725 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:45,726 INFO L82 PathProgramCache]: Analyzing trace with hash 1383142105, now seen corresponding path program 27 times [2018-11-18 15:28:45,726 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:45,726 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:45,726 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:45,726 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:28:45,726 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:45,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:46,340 INFO L134 CoverageAnalysis]: Checked inductivity of 46050 backedges. 9555 proven. 602 refuted. 0 times theorem prover too weak. 35893 trivial. 0 not checked. [2018-11-18 15:28:46,340 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:28:46,340 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:28:46,346 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 15:28:46,537 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2018-11-18 15:28:46,537 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:28:46,543 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:28:46,545 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 15:28:46,556 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 15:28:46,563 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 15:28:46,563 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 15:28:46,568 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 15:28:46,574 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 15:28:46,574 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 15:28:47,509 INFO L134 CoverageAnalysis]: Checked inductivity of 46050 backedges. 9555 proven. 602 refuted. 0 times theorem prover too weak. 35893 trivial. 0 not checked. [2018-11-18 15:28:47,524 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:28:47,525 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 20] total 21 [2018-11-18 15:28:47,525 INFO L459 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-11-18 15:28:47,525 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-11-18 15:28:47,525 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=182, Invalid=280, Unknown=0, NotChecked=0, Total=462 [2018-11-18 15:28:47,525 INFO L87 Difference]: Start difference. First operand 895 states and 897 transitions. Second operand 22 states. [2018-11-18 15:28:47,858 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:47,858 INFO L93 Difference]: Finished difference Result 919 states and 923 transitions. [2018-11-18 15:28:47,859 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-11-18 15:28:47,859 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 891 [2018-11-18 15:28:47,859 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:47,860 INFO L225 Difference]: With dead ends: 919 [2018-11-18 15:28:47,860 INFO L226 Difference]: Without dead ends: 919 [2018-11-18 15:28:47,860 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 924 GetRequests, 861 SyntacticMatches, 28 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 216 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=483, Invalid=849, Unknown=0, NotChecked=0, Total=1332 [2018-11-18 15:28:47,861 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 919 states. [2018-11-18 15:28:47,864 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 919 to 901. [2018-11-18 15:28:47,864 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 901 states. [2018-11-18 15:28:47,865 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 901 states to 901 states and 904 transitions. [2018-11-18 15:28:47,865 INFO L78 Accepts]: Start accepts. Automaton has 901 states and 904 transitions. Word has length 891 [2018-11-18 15:28:47,865 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:47,865 INFO L480 AbstractCegarLoop]: Abstraction has 901 states and 904 transitions. [2018-11-18 15:28:47,865 INFO L481 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-11-18 15:28:47,865 INFO L276 IsEmpty]: Start isEmpty. Operand 901 states and 904 transitions. [2018-11-18 15:28:47,869 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 898 [2018-11-18 15:28:47,869 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:47,869 INFO L375 BasicCegarLoop]: trace histogram [133, 120, 120, 119, 119, 119, 14, 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:47,869 INFO L423 AbstractCegarLoop]: === Iteration 41 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:47,869 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:47,869 INFO L82 PathProgramCache]: Analyzing trace with hash -1253549087, now seen corresponding path program 28 times [2018-11-18 15:28:47,869 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:47,869 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:47,870 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:47,870 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:28:47,870 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:47,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:48,418 INFO L134 CoverageAnalysis]: Checked inductivity of 46788 backedges. 10851 proven. 629 refuted. 0 times theorem prover too weak. 35308 trivial. 0 not checked. [2018-11-18 15:28:48,418 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:28:48,418 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:28:48,425 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 15:28:48,527 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 15:28:48,527 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:28:48,534 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:28:49,125 INFO L134 CoverageAnalysis]: Checked inductivity of 46788 backedges. 10718 proven. 2308 refuted. 0 times theorem prover too weak. 33762 trivial. 0 not checked. [2018-11-18 15:28:49,140 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:28:49,140 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 37] total 55 [2018-11-18 15:28:49,141 INFO L459 AbstractCegarLoop]: Interpolant automaton has 55 states [2018-11-18 15:28:49,141 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2018-11-18 15:28:49,141 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=608, Invalid=2362, Unknown=0, NotChecked=0, Total=2970 [2018-11-18 15:28:49,141 INFO L87 Difference]: Start difference. First operand 901 states and 904 transitions. Second operand 55 states. [2018-11-18 15:28:49,953 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:49,953 INFO L93 Difference]: Finished difference Result 1020 states and 1024 transitions. [2018-11-18 15:28:49,953 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2018-11-18 15:28:49,953 INFO L78 Accepts]: Start accepts. Automaton has 55 states. Word has length 897 [2018-11-18 15:28:49,954 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:49,955 INFO L225 Difference]: With dead ends: 1020 [2018-11-18 15:28:49,955 INFO L226 Difference]: Without dead ends: 1020 [2018-11-18 15:28:49,955 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 961 GetRequests, 877 SyntacticMatches, 0 SemanticMatches, 84 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1376 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=1613, Invalid=5697, Unknown=0, NotChecked=0, Total=7310 [2018-11-18 15:28:49,956 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1020 states. [2018-11-18 15:28:49,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1020 to 1010. [2018-11-18 15:28:49,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1010 states. [2018-11-18 15:28:49,961 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1010 states to 1010 states and 1014 transitions. [2018-11-18 15:28:49,961 INFO L78 Accepts]: Start accepts. Automaton has 1010 states and 1014 transitions. Word has length 897 [2018-11-18 15:28:49,961 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:49,961 INFO L480 AbstractCegarLoop]: Abstraction has 1010 states and 1014 transitions. [2018-11-18 15:28:49,961 INFO L481 AbstractCegarLoop]: Interpolant automaton has 55 states. [2018-11-18 15:28:49,961 INFO L276 IsEmpty]: Start isEmpty. Operand 1010 states and 1014 transitions. [2018-11-18 15:28:49,966 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 995 [2018-11-18 15:28:49,967 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:49,967 INFO L375 BasicCegarLoop]: trace histogram [148, 134, 134, 133, 133, 133, 15, 15, 15, 15, 14, 14, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:49,967 INFO L423 AbstractCegarLoop]: === Iteration 42 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:49,967 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:49,967 INFO L82 PathProgramCache]: Analyzing trace with hash 620594870, now seen corresponding path program 29 times [2018-11-18 15:28:49,967 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:49,967 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:49,968 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:49,968 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:28:49,968 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:50,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:50,695 INFO L134 CoverageAnalysis]: Checked inductivity of 58191 backedges. 11554 proven. 690 refuted. 0 times theorem prover too weak. 45947 trivial. 0 not checked. [2018-11-18 15:28:50,695 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:28:50,695 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:28:50,702 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-18 15:28:51,484 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 30 check-sat command(s) [2018-11-18 15:28:51,484 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:28:51,495 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:28:52,251 INFO L134 CoverageAnalysis]: Checked inductivity of 58191 backedges. 21373 proven. 2980 refuted. 0 times theorem prover too weak. 33838 trivial. 0 not checked. [2018-11-18 15:28:52,269 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:28:52,269 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 36] total 55 [2018-11-18 15:28:52,269 INFO L459 AbstractCegarLoop]: Interpolant automaton has 55 states [2018-11-18 15:28:52,269 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2018-11-18 15:28:52,270 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=418, Invalid=2552, Unknown=0, NotChecked=0, Total=2970 [2018-11-18 15:28:52,270 INFO L87 Difference]: Start difference. First operand 1010 states and 1014 transitions. Second operand 55 states. [2018-11-18 15:28:53,937 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:53,937 INFO L93 Difference]: Finished difference Result 1030 states and 1033 transitions. [2018-11-18 15:28:53,937 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-11-18 15:28:53,937 INFO L78 Accepts]: Start accepts. Automaton has 55 states. Word has length 994 [2018-11-18 15:28:53,938 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:53,939 INFO L225 Difference]: With dead ends: 1030 [2018-11-18 15:28:53,939 INFO L226 Difference]: Without dead ends: 1024 [2018-11-18 15:28:53,940 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1061 GetRequests, 961 SyntacticMatches, 0 SemanticMatches, 100 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2473 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=1773, Invalid=8529, Unknown=0, NotChecked=0, Total=10302 [2018-11-18 15:28:53,941 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1024 states. [2018-11-18 15:28:53,947 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1024 to 1016. [2018-11-18 15:28:53,947 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1016 states. [2018-11-18 15:28:53,948 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1016 states to 1016 states and 1019 transitions. [2018-11-18 15:28:53,948 INFO L78 Accepts]: Start accepts. Automaton has 1016 states and 1019 transitions. Word has length 994 [2018-11-18 15:28:53,949 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:53,949 INFO L480 AbstractCegarLoop]: Abstraction has 1016 states and 1019 transitions. [2018-11-18 15:28:53,949 INFO L481 AbstractCegarLoop]: Interpolant automaton has 55 states. [2018-11-18 15:28:53,949 INFO L276 IsEmpty]: Start isEmpty. Operand 1016 states and 1019 transitions. [2018-11-18 15:28:53,956 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1007 [2018-11-18 15:28:53,956 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:53,956 INFO L375 BasicCegarLoop]: trace histogram [150, 136, 136, 135, 135, 135, 15, 15, 15, 15, 14, 14, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:53,957 INFO L423 AbstractCegarLoop]: === Iteration 43 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:53,957 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:53,957 INFO L82 PathProgramCache]: Analyzing trace with hash -1447052810, now seen corresponding path program 30 times [2018-11-18 15:28:53,957 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:53,957 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:53,958 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:53,958 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:28:53,958 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:53,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:54,740 INFO L134 CoverageAnalysis]: Checked inductivity of 59857 backedges. 12390 proven. 784 refuted. 0 times theorem prover too weak. 46683 trivial. 0 not checked. [2018-11-18 15:28:54,741 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:28:54,741 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:28:54,751 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-18 15:28:55,785 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 26 check-sat command(s) [2018-11-18 15:28:55,785 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:28:55,795 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:28:55,797 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 15:28:55,799 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 15:28:55,803 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 15:28:55,804 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 15:28:55,813 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 15:28:55,819 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 15:28:55,820 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:16, output treesize:30 [2018-11-18 15:28:57,490 INFO L134 CoverageAnalysis]: Checked inductivity of 59857 backedges. 12390 proven. 711 refuted. 0 times theorem prover too weak. 46756 trivial. 0 not checked. [2018-11-18 15:28:57,507 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:28:57,507 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21] total 40 [2018-11-18 15:28:57,507 INFO L459 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-11-18 15:28:57,508 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-11-18 15:28:57,508 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=380, Invalid=1260, Unknown=0, NotChecked=0, Total=1640 [2018-11-18 15:28:57,508 INFO L87 Difference]: Start difference. First operand 1016 states and 1019 transitions. Second operand 41 states. [2018-11-18 15:28:58,486 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:58,486 INFO L93 Difference]: Finished difference Result 1151 states and 1157 transitions. [2018-11-18 15:28:58,486 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2018-11-18 15:28:58,486 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 1006 [2018-11-18 15:28:58,486 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:28:58,488 INFO L225 Difference]: With dead ends: 1151 [2018-11-18 15:28:58,488 INFO L226 Difference]: Without dead ends: 1151 [2018-11-18 15:28:58,488 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1062 GetRequests, 959 SyntacticMatches, 28 SemanticMatches, 75 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2168 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=1400, Invalid=4452, Unknown=0, NotChecked=0, Total=5852 [2018-11-18 15:28:58,489 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1151 states. [2018-11-18 15:28:58,493 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1151 to 1125. [2018-11-18 15:28:58,493 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1125 states. [2018-11-18 15:28:58,494 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1125 states to 1125 states and 1130 transitions. [2018-11-18 15:28:58,494 INFO L78 Accepts]: Start accepts. Automaton has 1125 states and 1130 transitions. Word has length 1006 [2018-11-18 15:28:58,495 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:28:58,495 INFO L480 AbstractCegarLoop]: Abstraction has 1125 states and 1130 transitions. [2018-11-18 15:28:58,495 INFO L481 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-11-18 15:28:58,495 INFO L276 IsEmpty]: Start isEmpty. Operand 1125 states and 1130 transitions. [2018-11-18 15:28:58,500 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1116 [2018-11-18 15:28:58,500 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:28:58,500 INFO L375 BasicCegarLoop]: trace histogram [167, 152, 152, 151, 151, 151, 16, 16, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:58,500 INFO L423 AbstractCegarLoop]: === Iteration 44 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:28:58,500 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:58,500 INFO L82 PathProgramCache]: Analyzing trace with hash -511871151, now seen corresponding path program 31 times [2018-11-18 15:28:58,500 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:58,500 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:58,501 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:58,501 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:28:58,501 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:58,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:59,273 INFO L134 CoverageAnalysis]: Checked inductivity of 74539 backedges. 26719 proven. 3402 refuted. 0 times theorem prover too weak. 44418 trivial. 0 not checked. [2018-11-18 15:28:59,273 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:28:59,273 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:28:59,280 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:59,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:59,437 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:29:00,056 INFO L134 CoverageAnalysis]: Checked inductivity of 74539 backedges. 26977 proven. 660 refuted. 0 times theorem prover too weak. 46902 trivial. 0 not checked. [2018-11-18 15:29:00,073 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:29:00,073 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 34] total 55 [2018-11-18 15:29:00,074 INFO L459 AbstractCegarLoop]: Interpolant automaton has 55 states [2018-11-18 15:29:00,074 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2018-11-18 15:29:00,074 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=606, Invalid=2364, Unknown=0, NotChecked=0, Total=2970 [2018-11-18 15:29:00,075 INFO L87 Difference]: Start difference. First operand 1125 states and 1130 transitions. Second operand 55 states. [2018-11-18 15:29:01,036 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:29:01,036 INFO L93 Difference]: Finished difference Result 1144 states and 1148 transitions. [2018-11-18 15:29:01,037 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2018-11-18 15:29:01,037 INFO L78 Accepts]: Start accepts. Automaton has 55 states. Word has length 1115 [2018-11-18 15:29:01,038 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:29:01,039 INFO L225 Difference]: With dead ends: 1144 [2018-11-18 15:29:01,039 INFO L226 Difference]: Without dead ends: 1138 [2018-11-18 15:29:01,040 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1187 GetRequests, 1100 SyntacticMatches, 0 SemanticMatches, 87 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2396 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=1711, Invalid=6121, Unknown=0, NotChecked=0, Total=7832 [2018-11-18 15:29:01,041 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1138 states. [2018-11-18 15:29:01,045 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1138 to 1131. [2018-11-18 15:29:01,045 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1131 states. [2018-11-18 15:29:01,046 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1131 states to 1131 states and 1135 transitions. [2018-11-18 15:29:01,046 INFO L78 Accepts]: Start accepts. Automaton has 1131 states and 1135 transitions. Word has length 1115 [2018-11-18 15:29:01,047 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:29:01,047 INFO L480 AbstractCegarLoop]: Abstraction has 1131 states and 1135 transitions. [2018-11-18 15:29:01,047 INFO L481 AbstractCegarLoop]: Interpolant automaton has 55 states. [2018-11-18 15:29:01,047 INFO L276 IsEmpty]: Start isEmpty. Operand 1131 states and 1135 transitions. [2018-11-18 15:29:01,053 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1122 [2018-11-18 15:29:01,053 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:29:01,053 INFO L375 BasicCegarLoop]: trace histogram [168, 153, 153, 152, 152, 152, 16, 16, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:01,053 INFO L423 AbstractCegarLoop]: === Iteration 45 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:29:01,054 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:01,054 INFO L82 PathProgramCache]: Analyzing trace with hash 1600859401, now seen corresponding path program 32 times [2018-11-18 15:29:01,054 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:01,054 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:01,054 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:01,055 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:01,055 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:01,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:01,776 INFO L134 CoverageAnalysis]: Checked inductivity of 75479 backedges. 15699 proven. 830 refuted. 0 times theorem prover too weak. 58950 trivial. 0 not checked. [2018-11-18 15:29:01,776 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:29:01,776 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:29:01,782 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-18 15:29:01,937 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 15:29:01,937 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:29:01,945 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:29:02,689 INFO L134 CoverageAnalysis]: Checked inductivity of 75479 backedges. 15749 proven. 780 refuted. 0 times theorem prover too weak. 58950 trivial. 0 not checked. [2018-11-18 15:29:02,706 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:29:02,707 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 37] total 57 [2018-11-18 15:29:02,707 INFO L459 AbstractCegarLoop]: Interpolant automaton has 57 states [2018-11-18 15:29:02,708 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2018-11-18 15:29:02,708 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=742, Invalid=2450, Unknown=0, NotChecked=0, Total=3192 [2018-11-18 15:29:02,708 INFO L87 Difference]: Start difference. First operand 1131 states and 1135 transitions. Second operand 57 states. [2018-11-18 15:29:03,587 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:29:03,587 INFO L93 Difference]: Finished difference Result 1265 states and 1270 transitions. [2018-11-18 15:29:03,587 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2018-11-18 15:29:03,587 INFO L78 Accepts]: Start accepts. Automaton has 57 states. Word has length 1121 [2018-11-18 15:29:03,588 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:29:03,589 INFO L225 Difference]: With dead ends: 1265 [2018-11-18 15:29:03,589 INFO L226 Difference]: Without dead ends: 1265 [2018-11-18 15:29:03,590 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1191 GetRequests, 1103 SyntacticMatches, 0 SemanticMatches, 88 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1319 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=2059, Invalid=5951, Unknown=0, NotChecked=0, Total=8010 [2018-11-18 15:29:03,590 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1265 states. [2018-11-18 15:29:03,596 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1265 to 1252. [2018-11-18 15:29:03,596 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1252 states. [2018-11-18 15:29:03,597 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1252 states to 1252 states and 1257 transitions. [2018-11-18 15:29:03,597 INFO L78 Accepts]: Start accepts. Automaton has 1252 states and 1257 transitions. Word has length 1121 [2018-11-18 15:29:03,597 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:29:03,597 INFO L480 AbstractCegarLoop]: Abstraction has 1252 states and 1257 transitions. [2018-11-18 15:29:03,597 INFO L481 AbstractCegarLoop]: Interpolant automaton has 57 states. [2018-11-18 15:29:03,597 INFO L276 IsEmpty]: Start isEmpty. Operand 1252 states and 1257 transitions. [2018-11-18 15:29:03,603 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1231 [2018-11-18 15:29:03,603 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:29:03,603 INFO L375 BasicCegarLoop]: trace histogram [185, 169, 169, 168, 168, 168, 17, 17, 17, 17, 16, 16, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:03,604 INFO L423 AbstractCegarLoop]: === Iteration 46 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:29:03,604 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:03,604 INFO L82 PathProgramCache]: Analyzing trace with hash -779387106, now seen corresponding path program 33 times [2018-11-18 15:29:03,604 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:03,604 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:03,604 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:03,605 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:29:03,605 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:03,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:04,529 INFO L134 CoverageAnalysis]: Checked inductivity of 91872 backedges. 41783 proven. 2493 refuted. 0 times theorem prover too weak. 47596 trivial. 0 not checked. [2018-11-18 15:29:04,529 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:29:04,529 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:29:04,537 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 15:29:04,893 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2018-11-18 15:29:04,893 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:29:04,901 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:29:06,059 INFO L134 CoverageAnalysis]: Checked inductivity of 91872 backedges. 29675 proven. 2452 refuted. 0 times theorem prover too weak. 59745 trivial. 0 not checked. [2018-11-18 15:29:06,075 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:29:06,075 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 41] total 78 [2018-11-18 15:29:06,076 INFO L459 AbstractCegarLoop]: Interpolant automaton has 78 states [2018-11-18 15:29:06,076 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 78 interpolants. [2018-11-18 15:29:06,076 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=870, Invalid=5136, Unknown=0, NotChecked=0, Total=6006 [2018-11-18 15:29:06,076 INFO L87 Difference]: Start difference. First operand 1252 states and 1257 transitions. Second operand 78 states. [2018-11-18 15:29:08,225 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:29:08,225 INFO L93 Difference]: Finished difference Result 1385 states and 1389 transitions. [2018-11-18 15:29:08,226 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 81 states. [2018-11-18 15:29:08,226 INFO L78 Accepts]: Start accepts. Automaton has 78 states. Word has length 1230 [2018-11-18 15:29:08,226 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:29:08,228 INFO L225 Difference]: With dead ends: 1385 [2018-11-18 15:29:08,228 INFO L226 Difference]: Without dead ends: 1379 [2018-11-18 15:29:08,229 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1343 GetRequests, 1194 SyntacticMatches, 0 SemanticMatches, 149 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7113 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=3586, Invalid=19064, Unknown=0, NotChecked=0, Total=22650 [2018-11-18 15:29:08,229 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1379 states. [2018-11-18 15:29:08,234 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1379 to 1252. [2018-11-18 15:29:08,234 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1252 states. [2018-11-18 15:29:08,235 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1252 states to 1252 states and 1255 transitions. [2018-11-18 15:29:08,235 INFO L78 Accepts]: Start accepts. Automaton has 1252 states and 1255 transitions. Word has length 1230 [2018-11-18 15:29:08,235 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:29:08,235 INFO L480 AbstractCegarLoop]: Abstraction has 1252 states and 1255 transitions. [2018-11-18 15:29:08,235 INFO L481 AbstractCegarLoop]: Interpolant automaton has 78 states. [2018-11-18 15:29:08,235 INFO L276 IsEmpty]: Start isEmpty. Operand 1252 states and 1255 transitions. [2018-11-18 15:29:08,241 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1237 [2018-11-18 15:29:08,241 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:29:08,241 INFO L375 BasicCegarLoop]: trace histogram [186, 170, 170, 169, 169, 169, 17, 17, 17, 17, 16, 16, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:08,242 INFO L423 AbstractCegarLoop]: === Iteration 47 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:29:08,242 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:08,242 INFO L82 PathProgramCache]: Analyzing trace with hash 888497942, now seen corresponding path program 34 times [2018-11-18 15:29:08,242 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:08,242 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:08,242 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:08,242 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:29:08,242 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:08,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:09,246 INFO L134 CoverageAnalysis]: Checked inductivity of 92916 backedges. 16704 proven. 884 refuted. 0 times theorem prover too weak. 75328 trivial. 0 not checked. [2018-11-18 15:29:09,247 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:29:09,247 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:29:09,253 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 15:29:09,553 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 15:29:09,554 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:29:09,566 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:29:09,568 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 15:29:09,570 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 15:29:09,581 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 15:29:09,581 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 15:29:09,591 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 15:29:09,598 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 15:29:09,598 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 15:29:11,558 INFO L134 CoverageAnalysis]: Checked inductivity of 92916 backedges. 16704 proven. 884 refuted. 0 times theorem prover too weak. 75328 trivial. 0 not checked. [2018-11-18 15:29:11,576 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:29:11,577 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22] total 40 [2018-11-18 15:29:11,577 INFO L459 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-11-18 15:29:11,578 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-11-18 15:29:11,578 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=442, Invalid=1198, Unknown=0, NotChecked=0, Total=1640 [2018-11-18 15:29:11,578 INFO L87 Difference]: Start difference. First operand 1252 states and 1255 transitions. Second operand 41 states. [2018-11-18 15:29:12,479 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:29:12,479 INFO L93 Difference]: Finished difference Result 1269 states and 1273 transitions. [2018-11-18 15:29:12,480 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-11-18 15:29:12,480 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 1236 [2018-11-18 15:29:12,481 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:29:12,483 INFO L225 Difference]: With dead ends: 1269 [2018-11-18 15:29:12,483 INFO L226 Difference]: Without dead ends: 1269 [2018-11-18 15:29:12,483 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1275 GetRequests, 1184 SyntacticMatches, 34 SemanticMatches, 57 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 987 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=720, Invalid=2702, Unknown=0, NotChecked=0, Total=3422 [2018-11-18 15:29:12,484 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1269 states. [2018-11-18 15:29:12,489 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1269 to 1258. [2018-11-18 15:29:12,489 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1258 states. [2018-11-18 15:29:12,490 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1258 states to 1258 states and 1262 transitions. [2018-11-18 15:29:12,490 INFO L78 Accepts]: Start accepts. Automaton has 1258 states and 1262 transitions. Word has length 1236 [2018-11-18 15:29:12,491 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:29:12,491 INFO L480 AbstractCegarLoop]: Abstraction has 1258 states and 1262 transitions. [2018-11-18 15:29:12,491 INFO L481 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-11-18 15:29:12,491 INFO L276 IsEmpty]: Start isEmpty. Operand 1258 states and 1262 transitions. [2018-11-18 15:29:12,498 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1243 [2018-11-18 15:29:12,498 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:29:12,498 INFO L375 BasicCegarLoop]: trace histogram [187, 171, 171, 170, 170, 170, 17, 17, 17, 17, 16, 16, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:12,498 INFO L423 AbstractCegarLoop]: === Iteration 48 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:29:12,499 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:12,499 INFO L82 PathProgramCache]: Analyzing trace with hash -887501218, now seen corresponding path program 35 times [2018-11-18 15:29:12,499 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:12,499 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:12,499 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:12,500 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:29:12,500 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:12,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:13,351 INFO L134 CoverageAnalysis]: Checked inductivity of 93966 backedges. 18585 proven. 941 refuted. 0 times theorem prover too weak. 74440 trivial. 0 not checked. [2018-11-18 15:29:13,351 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:29:13,351 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:29:13,357 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-18 15:29:14,653 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 33 check-sat command(s) [2018-11-18 15:29:14,653 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:29:14,668 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:29:15,610 INFO L134 CoverageAnalysis]: Checked inductivity of 93966 backedges. 18428 proven. 3343 refuted. 0 times theorem prover too weak. 72195 trivial. 0 not checked. [2018-11-18 15:29:15,628 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:29:15,628 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 44] total 64 [2018-11-18 15:29:15,629 INFO L459 AbstractCegarLoop]: Interpolant automaton has 64 states [2018-11-18 15:29:15,629 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 64 interpolants. [2018-11-18 15:29:15,629 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=833, Invalid=3199, Unknown=0, NotChecked=0, Total=4032 [2018-11-18 15:29:15,629 INFO L87 Difference]: Start difference. First operand 1258 states and 1262 transitions. Second operand 64 states. [2018-11-18 15:29:16,873 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:29:16,874 INFO L93 Difference]: Finished difference Result 1392 states and 1397 transitions. [2018-11-18 15:29:16,874 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 62 states. [2018-11-18 15:29:16,874 INFO L78 Accepts]: Start accepts. Automaton has 64 states. Word has length 1242 [2018-11-18 15:29:16,874 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:29:16,876 INFO L225 Difference]: With dead ends: 1392 [2018-11-18 15:29:16,876 INFO L226 Difference]: Without dead ends: 1392 [2018-11-18 15:29:16,877 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1318 GetRequests, 1219 SyntacticMatches, 0 SemanticMatches, 99 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1898 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=2249, Invalid=7851, Unknown=0, NotChecked=0, Total=10100 [2018-11-18 15:29:16,878 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1392 states. [2018-11-18 15:29:16,883 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1392 to 1379. [2018-11-18 15:29:16,883 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1379 states. [2018-11-18 15:29:16,884 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1379 states to 1379 states and 1384 transitions. [2018-11-18 15:29:16,884 INFO L78 Accepts]: Start accepts. Automaton has 1379 states and 1384 transitions. Word has length 1242 [2018-11-18 15:29:16,884 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:29:16,884 INFO L480 AbstractCegarLoop]: Abstraction has 1379 states and 1384 transitions. [2018-11-18 15:29:16,884 INFO L481 AbstractCegarLoop]: Interpolant automaton has 64 states. [2018-11-18 15:29:16,884 INFO L276 IsEmpty]: Start isEmpty. Operand 1379 states and 1384 transitions. [2018-11-18 15:29:16,891 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1358 [2018-11-18 15:29:16,891 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:29:16,891 INFO L375 BasicCegarLoop]: trace histogram [205, 188, 188, 187, 187, 187, 18, 18, 18, 18, 17, 17, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:16,891 INFO L423 AbstractCegarLoop]: === Iteration 49 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:29:16,892 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:16,892 INFO L82 PathProgramCache]: Analyzing trace with hash -1904678671, now seen corresponding path program 36 times [2018-11-18 15:29:16,892 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:16,892 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:16,892 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:16,892 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:29:16,892 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:16,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:17,917 INFO L134 CoverageAnalysis]: Checked inductivity of 113322 backedges. 36728 proven. 4314 refuted. 0 times theorem prover too weak. 72280 trivial. 0 not checked. [2018-11-18 15:29:17,917 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:29:17,917 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:29:17,924 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-18 15:29:20,722 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 37 check-sat command(s) [2018-11-18 15:29:20,722 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:29:20,737 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:29:22,028 INFO L134 CoverageAnalysis]: Checked inductivity of 113322 backedges. 49816 proven. 2755 refuted. 0 times theorem prover too weak. 60751 trivial. 0 not checked. [2018-11-18 15:29:22,047 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:29:22,048 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 41] total 78 [2018-11-18 15:29:22,048 INFO L459 AbstractCegarLoop]: Interpolant automaton has 78 states [2018-11-18 15:29:22,049 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 78 interpolants. [2018-11-18 15:29:22,049 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=972, Invalid=5034, Unknown=0, NotChecked=0, Total=6006 [2018-11-18 15:29:22,049 INFO L87 Difference]: Start difference. First operand 1379 states and 1384 transitions. Second operand 78 states. [2018-11-18 15:29:23,794 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:29:23,794 INFO L93 Difference]: Finished difference Result 1400 states and 1403 transitions. [2018-11-18 15:29:23,794 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 75 states. [2018-11-18 15:29:23,794 INFO L78 Accepts]: Start accepts. Automaton has 78 states. Word has length 1357 [2018-11-18 15:29:23,795 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:29:23,797 INFO L225 Difference]: With dead ends: 1400 [2018-11-18 15:29:23,797 INFO L226 Difference]: Without dead ends: 1378 [2018-11-18 15:29:23,798 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1454 GetRequests, 1323 SyntacticMatches, 0 SemanticMatches, 131 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5309 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=2992, Invalid=14564, Unknown=0, NotChecked=0, Total=17556 [2018-11-18 15:29:23,799 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1378 states. [2018-11-18 15:29:23,804 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1378 to 1373. [2018-11-18 15:29:23,804 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1373 states. [2018-11-18 15:29:23,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1373 states to 1373 states and 1375 transitions. [2018-11-18 15:29:23,805 INFO L78 Accepts]: Start accepts. Automaton has 1373 states and 1375 transitions. Word has length 1357 [2018-11-18 15:29:23,806 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:29:23,806 INFO L480 AbstractCegarLoop]: Abstraction has 1373 states and 1375 transitions. [2018-11-18 15:29:23,806 INFO L481 AbstractCegarLoop]: Interpolant automaton has 78 states. [2018-11-18 15:29:23,806 INFO L276 IsEmpty]: Start isEmpty. Operand 1373 states and 1375 transitions. [2018-11-18 15:29:23,813 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1364 [2018-11-18 15:29:23,813 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:29:23,813 INFO L375 BasicCegarLoop]: trace histogram [206, 189, 189, 188, 188, 188, 18, 18, 18, 18, 17, 17, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:23,813 INFO L423 AbstractCegarLoop]: === Iteration 50 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:29:23,813 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:23,814 INFO L82 PathProgramCache]: Analyzing trace with hash -450420055, now seen corresponding path program 37 times [2018-11-18 15:29:23,814 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:23,814 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:23,814 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:23,814 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:29:23,814 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:23,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:24,946 INFO L134 CoverageAnalysis]: Checked inductivity of 114482 backedges. 19703 proven. 990 refuted. 0 times theorem prover too weak. 93789 trivial. 0 not checked. [2018-11-18 15:29:24,946 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:29:24,946 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:29:24,952 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:25,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:25,157 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:29:25,159 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 15:29:25,161 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 15:29:25,164 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 15:29:25,164 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 15:29:25,172 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 15:29:25,178 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 15:29:25,178 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 15:29:27,464 INFO L134 CoverageAnalysis]: Checked inductivity of 114482 backedges. 19703 proven. 990 refuted. 0 times theorem prover too weak. 93789 trivial. 0 not checked. [2018-11-18 15:29:27,480 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:29:27,481 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23] total 42 [2018-11-18 15:29:27,481 INFO L459 AbstractCegarLoop]: Interpolant automaton has 43 states [2018-11-18 15:29:27,481 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2018-11-18 15:29:27,481 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=485, Invalid=1321, Unknown=0, NotChecked=0, Total=1806 [2018-11-18 15:29:27,481 INFO L87 Difference]: Start difference. First operand 1373 states and 1375 transitions. Second operand 43 states. [2018-11-18 15:29:28,464 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:29:28,464 INFO L93 Difference]: Finished difference Result 1387 states and 1390 transitions. [2018-11-18 15:29:28,464 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-11-18 15:29:28,464 INFO L78 Accepts]: Start accepts. Automaton has 43 states. Word has length 1363 [2018-11-18 15:29:28,465 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:29:28,467 INFO L225 Difference]: With dead ends: 1387 [2018-11-18 15:29:28,467 INFO L226 Difference]: Without dead ends: 1387 [2018-11-18 15:29:28,468 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1404 GetRequests, 1308 SyntacticMatches, 36 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1099 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=788, Invalid=2994, Unknown=0, NotChecked=0, Total=3782 [2018-11-18 15:29:28,469 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1387 states. [2018-11-18 15:29:28,474 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1387 to 1379. [2018-11-18 15:29:28,474 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1379 states. [2018-11-18 15:29:28,475 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1379 states to 1379 states and 1382 transitions. [2018-11-18 15:29:28,475 INFO L78 Accepts]: Start accepts. Automaton has 1379 states and 1382 transitions. Word has length 1363 [2018-11-18 15:29:28,476 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:29:28,476 INFO L480 AbstractCegarLoop]: Abstraction has 1379 states and 1382 transitions. [2018-11-18 15:29:28,476 INFO L481 AbstractCegarLoop]: Interpolant automaton has 43 states. [2018-11-18 15:29:28,476 INFO L276 IsEmpty]: Start isEmpty. Operand 1379 states and 1382 transitions. [2018-11-18 15:29:28,484 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1370 [2018-11-18 15:29:28,484 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:29:28,485 INFO L375 BasicCegarLoop]: trace histogram [207, 190, 190, 189, 189, 189, 18, 18, 18, 18, 17, 17, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:28,485 INFO L423 AbstractCegarLoop]: === Iteration 51 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:29:28,485 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:28,485 INFO L82 PathProgramCache]: Analyzing trace with hash 1611091889, now seen corresponding path program 38 times [2018-11-18 15:29:28,486 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:28,486 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:28,486 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:28,486 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:28,486 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:28,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:29,432 INFO L134 CoverageAnalysis]: Checked inductivity of 115648 backedges. 21803 proven. 1059 refuted. 0 times theorem prover too weak. 92786 trivial. 0 not checked. [2018-11-18 15:29:29,432 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:29:29,432 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:29:29,439 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-18 15:29:29,628 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 15:29:29,628 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:29:29,637 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:29:30,614 INFO L134 CoverageAnalysis]: Checked inductivity of 115648 backedges. 21859 proven. 1003 refuted. 0 times theorem prover too weak. 92786 trivial. 0 not checked. [2018-11-18 15:29:30,630 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:29:30,630 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 41] total 63 [2018-11-18 15:29:30,631 INFO L459 AbstractCegarLoop]: Interpolant automaton has 63 states [2018-11-18 15:29:30,631 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 63 interpolants. [2018-11-18 15:29:30,631 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=904, Invalid=3002, Unknown=0, NotChecked=0, Total=3906 [2018-11-18 15:29:30,631 INFO L87 Difference]: Start difference. First operand 1379 states and 1382 transitions. Second operand 63 states. [2018-11-18 15:29:31,686 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:29:31,686 INFO L93 Difference]: Finished difference Result 1516 states and 1520 transitions. [2018-11-18 15:29:31,687 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2018-11-18 15:29:31,687 INFO L78 Accepts]: Start accepts. Automaton has 63 states. Word has length 1369 [2018-11-18 15:29:31,688 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:29:31,690 INFO L225 Difference]: With dead ends: 1516 [2018-11-18 15:29:31,690 INFO L226 Difference]: Without dead ends: 1516 [2018-11-18 15:29:31,691 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1447 GetRequests, 1349 SyntacticMatches, 0 SemanticMatches, 98 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1646 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=2529, Invalid=7371, Unknown=0, NotChecked=0, Total=9900 [2018-11-18 15:29:31,691 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1516 states. [2018-11-18 15:29:31,697 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1516 to 1506. [2018-11-18 15:29:31,697 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1506 states. [2018-11-18 15:29:31,698 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1506 states to 1506 states and 1510 transitions. [2018-11-18 15:29:31,698 INFO L78 Accepts]: Start accepts. Automaton has 1506 states and 1510 transitions. Word has length 1369 [2018-11-18 15:29:31,699 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:29:31,699 INFO L480 AbstractCegarLoop]: Abstraction has 1506 states and 1510 transitions. [2018-11-18 15:29:31,699 INFO L481 AbstractCegarLoop]: Interpolant automaton has 63 states. [2018-11-18 15:29:31,699 INFO L276 IsEmpty]: Start isEmpty. Operand 1506 states and 1510 transitions. [2018-11-18 15:29:31,708 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1491 [2018-11-18 15:29:31,708 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:29:31,709 INFO L375 BasicCegarLoop]: trace histogram [226, 208, 208, 207, 207, 207, 19, 19, 19, 19, 18, 18, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:31,709 INFO L423 AbstractCegarLoop]: === Iteration 52 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:29:31,709 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:31,709 INFO L82 PathProgramCache]: Analyzing trace with hash 456029702, now seen corresponding path program 39 times [2018-11-18 15:29:31,709 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:31,709 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:31,710 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:31,710 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:29:31,710 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:31,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:32,909 INFO L134 CoverageAnalysis]: Checked inductivity of 138303 backedges. 58711 proven. 3129 refuted. 0 times theorem prover too weak. 76463 trivial. 0 not checked. [2018-11-18 15:29:32,910 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:29:32,910 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:29:32,916 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 15:29:33,310 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 20 check-sat command(s) [2018-11-18 15:29:33,311 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:29:33,320 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:29:34,791 INFO L134 CoverageAnalysis]: Checked inductivity of 138303 backedges. 41415 proven. 3082 refuted. 0 times theorem prover too weak. 93806 trivial. 0 not checked. [2018-11-18 15:29:34,807 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:29:34,807 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 45] total 86 [2018-11-18 15:29:34,808 INFO L459 AbstractCegarLoop]: Interpolant automaton has 86 states [2018-11-18 15:29:34,808 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 86 interpolants. [2018-11-18 15:29:34,809 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1065, Invalid=6245, Unknown=0, NotChecked=0, Total=7310 [2018-11-18 15:29:34,809 INFO L87 Difference]: Start difference. First operand 1506 states and 1510 transitions. Second operand 86 states. [2018-11-18 15:29:37,242 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:29:37,242 INFO L93 Difference]: Finished difference Result 1521 states and 1523 transitions. [2018-11-18 15:29:37,242 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 88 states. [2018-11-18 15:29:37,242 INFO L78 Accepts]: Start accepts. Automaton has 86 states. Word has length 1490 [2018-11-18 15:29:37,243 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:29:37,245 INFO L225 Difference]: With dead ends: 1521 [2018-11-18 15:29:37,245 INFO L226 Difference]: Without dead ends: 1515 [2018-11-18 15:29:37,247 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1614 GetRequests, 1450 SyntacticMatches, 0 SemanticMatches, 164 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8668 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=4376, Invalid=23014, Unknown=0, NotChecked=0, Total=27390 [2018-11-18 15:29:37,248 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1515 states. [2018-11-18 15:29:37,256 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1515 to 1506. [2018-11-18 15:29:37,256 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1506 states. [2018-11-18 15:29:37,257 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1506 states to 1506 states and 1508 transitions. [2018-11-18 15:29:37,257 INFO L78 Accepts]: Start accepts. Automaton has 1506 states and 1508 transitions. Word has length 1490 [2018-11-18 15:29:37,257 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:29:37,257 INFO L480 AbstractCegarLoop]: Abstraction has 1506 states and 1508 transitions. [2018-11-18 15:29:37,257 INFO L481 AbstractCegarLoop]: Interpolant automaton has 86 states. [2018-11-18 15:29:37,258 INFO L276 IsEmpty]: Start isEmpty. Operand 1506 states and 1508 transitions. [2018-11-18 15:29:37,266 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1497 [2018-11-18 15:29:37,266 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:29:37,266 INFO L375 BasicCegarLoop]: trace histogram [227, 209, 209, 208, 208, 208, 19, 19, 19, 19, 18, 18, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:37,267 INFO L423 AbstractCegarLoop]: === Iteration 53 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:29:37,267 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:37,267 INFO L82 PathProgramCache]: Analyzing trace with hash -75954178, now seen corresponding path program 40 times [2018-11-18 15:29:37,267 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:37,267 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:37,267 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:37,268 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:29:37,268 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:37,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:38,628 INFO L134 CoverageAnalysis]: Checked inductivity of 139585 backedges. 23040 proven. 1102 refuted. 0 times theorem prover too weak. 115443 trivial. 0 not checked. [2018-11-18 15:29:38,629 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:29:38,629 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:29:38,635 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 15:29:38,995 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 15:29:38,995 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:29:39,011 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:29:39,012 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 15:29:39,014 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 15:29:39,018 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 15:29:39,018 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 15:29:39,023 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 15:29:39,037 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 15:29:39,037 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 15:29:41,679 INFO L134 CoverageAnalysis]: Checked inductivity of 139585 backedges. 23040 proven. 1102 refuted. 0 times theorem prover too weak. 115443 trivial. 0 not checked. [2018-11-18 15:29:41,698 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:29:41,698 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24] total 44 [2018-11-18 15:29:41,699 INFO L459 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-11-18 15:29:41,699 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-11-18 15:29:41,699 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=530, Invalid=1450, Unknown=0, NotChecked=0, Total=1980 [2018-11-18 15:29:41,699 INFO L87 Difference]: Start difference. First operand 1506 states and 1508 transitions. Second operand 45 states. [2018-11-18 15:29:42,614 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:29:42,614 INFO L93 Difference]: Finished difference Result 1520 states and 1523 transitions. [2018-11-18 15:29:42,615 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-11-18 15:29:42,615 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 1496 [2018-11-18 15:29:42,615 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:29:42,617 INFO L225 Difference]: With dead ends: 1520 [2018-11-18 15:29:42,617 INFO L226 Difference]: Without dead ends: 1520 [2018-11-18 15:29:42,617 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1539 GetRequests, 1438 SyntacticMatches, 38 SemanticMatches, 63 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1217 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=859, Invalid=3301, Unknown=0, NotChecked=0, Total=4160 [2018-11-18 15:29:42,618 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1520 states. [2018-11-18 15:29:42,626 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1520 to 1512. [2018-11-18 15:29:42,627 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1512 states. [2018-11-18 15:29:42,628 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1512 states to 1512 states and 1515 transitions. [2018-11-18 15:29:42,628 INFO L78 Accepts]: Start accepts. Automaton has 1512 states and 1515 transitions. Word has length 1496 [2018-11-18 15:29:42,629 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:29:42,629 INFO L480 AbstractCegarLoop]: Abstraction has 1512 states and 1515 transitions. [2018-11-18 15:29:42,629 INFO L481 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-11-18 15:29:42,629 INFO L276 IsEmpty]: Start isEmpty. Operand 1512 states and 1515 transitions. [2018-11-18 15:29:42,639 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1503 [2018-11-18 15:29:42,639 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:29:42,639 INFO L375 BasicCegarLoop]: trace histogram [228, 210, 210, 209, 209, 209, 19, 19, 19, 19, 18, 18, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:42,639 INFO L423 AbstractCegarLoop]: === Iteration 54 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:29:42,639 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:42,639 INFO L82 PathProgramCache]: Analyzing trace with hash 957030726, now seen corresponding path program 41 times [2018-11-18 15:29:42,639 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:42,639 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:42,640 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:42,640 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:29:42,640 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:42,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:43,751 INFO L134 CoverageAnalysis]: Checked inductivity of 140873 backedges. 25371 proven. 1184 refuted. 0 times theorem prover too weak. 114318 trivial. 0 not checked. [2018-11-18 15:29:43,751 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:29:43,751 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:29:43,759 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-18 15:29:45,606 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 44 check-sat command(s) [2018-11-18 15:29:45,606 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:29:45,625 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:29:46,861 INFO L134 CoverageAnalysis]: Checked inductivity of 140873 backedges. 25198 proven. 4138 refuted. 0 times theorem prover too weak. 111537 trivial. 0 not checked. [2018-11-18 15:29:46,881 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:29:46,881 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 48] total 70 [2018-11-18 15:29:46,882 INFO L459 AbstractCegarLoop]: Interpolant automaton has 70 states [2018-11-18 15:29:46,882 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 70 interpolants. [2018-11-18 15:29:46,882 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1003, Invalid=3827, Unknown=0, NotChecked=0, Total=4830 [2018-11-18 15:29:46,882 INFO L87 Difference]: Start difference. First operand 1512 states and 1515 transitions. Second operand 70 states. [2018-11-18 15:29:48,222 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:29:48,222 INFO L93 Difference]: Finished difference Result 1655 states and 1659 transitions. [2018-11-18 15:29:48,222 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2018-11-18 15:29:48,222 INFO L78 Accepts]: Start accepts. Automaton has 70 states. Word has length 1502 [2018-11-18 15:29:48,223 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:29:48,225 INFO L225 Difference]: With dead ends: 1655 [2018-11-18 15:29:48,225 INFO L226 Difference]: Without dead ends: 1655 [2018-11-18 15:29:48,225 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1586 GetRequests, 1477 SyntacticMatches, 0 SemanticMatches, 109 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2291 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=2733, Invalid=9477, Unknown=0, NotChecked=0, Total=12210 [2018-11-18 15:29:48,226 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1655 states. [2018-11-18 15:29:48,233 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1655 to 1645. [2018-11-18 15:29:48,233 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1645 states. [2018-11-18 15:29:48,234 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1645 states to 1645 states and 1649 transitions. [2018-11-18 15:29:48,234 INFO L78 Accepts]: Start accepts. Automaton has 1645 states and 1649 transitions. Word has length 1502 [2018-11-18 15:29:48,235 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:29:48,235 INFO L480 AbstractCegarLoop]: Abstraction has 1645 states and 1649 transitions. [2018-11-18 15:29:48,235 INFO L481 AbstractCegarLoop]: Interpolant automaton has 70 states. [2018-11-18 15:29:48,235 INFO L276 IsEmpty]: Start isEmpty. Operand 1645 states and 1649 transitions. [2018-11-18 15:29:48,244 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1630 [2018-11-18 15:29:48,244 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:29:48,245 INFO L375 BasicCegarLoop]: trace histogram [248, 229, 229, 228, 228, 228, 20, 20, 20, 20, 19, 19, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:48,245 INFO L423 AbstractCegarLoop]: === Iteration 55 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:29:48,245 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:48,245 INFO L82 PathProgramCache]: Analyzing trace with hash -1144954599, now seen corresponding path program 42 times [2018-11-18 15:29:48,245 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:48,245 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:48,246 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:48,246 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:29:48,246 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:48,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:49,573 INFO L134 CoverageAnalysis]: Checked inductivity of 167181 backedges. 50223 proven. 5330 refuted. 0 times theorem prover too weak. 111628 trivial. 0 not checked. [2018-11-18 15:29:49,573 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:29:49,573 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:29:49,580 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-18 15:29:51,393 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 41 check-sat command(s) [2018-11-18 15:29:51,393 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:29:51,407 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:29:53,075 INFO L134 CoverageAnalysis]: Checked inductivity of 167181 backedges. 48296 proven. 3424 refuted. 0 times theorem prover too weak. 115461 trivial. 0 not checked. [2018-11-18 15:29:53,093 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:29:53,093 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 47] total 90 [2018-11-18 15:29:53,094 INFO L459 AbstractCegarLoop]: Interpolant automaton has 90 states [2018-11-18 15:29:53,094 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 90 interpolants. [2018-11-18 15:29:53,094 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1154, Invalid=6856, Unknown=0, NotChecked=0, Total=8010 [2018-11-18 15:29:53,094 INFO L87 Difference]: Start difference. First operand 1645 states and 1649 transitions. Second operand 90 states. [2018-11-18 15:29:56,015 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:29:56,015 INFO L93 Difference]: Finished difference Result 1660 states and 1662 transitions. [2018-11-18 15:29:56,015 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 109 states. [2018-11-18 15:29:56,015 INFO L78 Accepts]: Start accepts. Automaton has 90 states. Word has length 1629 [2018-11-18 15:29:56,016 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:29:56,017 INFO L225 Difference]: With dead ends: 1660 [2018-11-18 15:29:56,017 INFO L226 Difference]: Without dead ends: 1654 [2018-11-18 15:29:56,018 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1776 GetRequests, 1587 SyntacticMatches, 0 SemanticMatches, 189 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12613 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=4959, Invalid=31331, Unknown=0, NotChecked=0, Total=36290 [2018-11-18 15:29:56,019 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1654 states. [2018-11-18 15:29:56,024 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1654 to 1645. [2018-11-18 15:29:56,025 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1645 states. [2018-11-18 15:29:56,026 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1645 states to 1645 states and 1647 transitions. [2018-11-18 15:29:56,026 INFO L78 Accepts]: Start accepts. Automaton has 1645 states and 1647 transitions. Word has length 1629 [2018-11-18 15:29:56,026 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:29:56,026 INFO L480 AbstractCegarLoop]: Abstraction has 1645 states and 1647 transitions. [2018-11-18 15:29:56,026 INFO L481 AbstractCegarLoop]: Interpolant automaton has 90 states. [2018-11-18 15:29:56,026 INFO L276 IsEmpty]: Start isEmpty. Operand 1645 states and 1647 transitions. [2018-11-18 15:29:56,036 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1636 [2018-11-18 15:29:56,036 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:29:56,036 INFO L375 BasicCegarLoop]: trace histogram [249, 230, 230, 229, 229, 229, 20, 20, 20, 20, 19, 19, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:56,036 INFO L423 AbstractCegarLoop]: === Iteration 56 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:29:56,036 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:56,036 INFO L82 PathProgramCache]: Analyzing trace with hash -1535093551, now seen corresponding path program 43 times [2018-11-18 15:29:56,036 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:56,037 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:56,037 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:56,037 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:29:56,037 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:56,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:57,587 INFO L134 CoverageAnalysis]: Checked inductivity of 168591 backedges. 26733 proven. 1220 refuted. 0 times theorem prover too weak. 140638 trivial. 0 not checked. [2018-11-18 15:29:57,588 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:29:57,588 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:29:57,595 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:57,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:57,831 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:29:57,833 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 15:29:57,835 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 15:29:57,842 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 15:29:57,843 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 15:29:57,848 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 15:29:57,854 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 15:29:57,854 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 15:30:01,069 INFO L134 CoverageAnalysis]: Checked inductivity of 168591 backedges. 26733 proven. 1220 refuted. 0 times theorem prover too weak. 140638 trivial. 0 not checked. [2018-11-18 15:30:01,086 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:30:01,086 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25] total 46 [2018-11-18 15:30:01,087 INFO L459 AbstractCegarLoop]: Interpolant automaton has 47 states [2018-11-18 15:30:01,087 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2018-11-18 15:30:01,087 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=577, Invalid=1585, Unknown=0, NotChecked=0, Total=2162 [2018-11-18 15:30:01,087 INFO L87 Difference]: Start difference. First operand 1645 states and 1647 transitions. Second operand 47 states. [2018-11-18 15:30:02,525 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:30:02,525 INFO L93 Difference]: Finished difference Result 1659 states and 1662 transitions. [2018-11-18 15:30:02,525 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-11-18 15:30:02,525 INFO L78 Accepts]: Start accepts. Automaton has 47 states. Word has length 1635 [2018-11-18 15:30:02,526 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:30:02,528 INFO L225 Difference]: With dead ends: 1659 [2018-11-18 15:30:02,528 INFO L226 Difference]: Without dead ends: 1659 [2018-11-18 15:30:02,529 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1680 GetRequests, 1574 SyntacticMatches, 40 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1341 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=933, Invalid=3623, Unknown=0, NotChecked=0, Total=4556 [2018-11-18 15:30:02,530 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1659 states. [2018-11-18 15:30:02,535 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1659 to 1651. [2018-11-18 15:30:02,536 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1651 states. [2018-11-18 15:30:02,537 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1651 states to 1651 states and 1654 transitions. [2018-11-18 15:30:02,537 INFO L78 Accepts]: Start accepts. Automaton has 1651 states and 1654 transitions. Word has length 1635 [2018-11-18 15:30:02,538 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:30:02,538 INFO L480 AbstractCegarLoop]: Abstraction has 1651 states and 1654 transitions. [2018-11-18 15:30:02,538 INFO L481 AbstractCegarLoop]: Interpolant automaton has 47 states. [2018-11-18 15:30:02,538 INFO L276 IsEmpty]: Start isEmpty. Operand 1651 states and 1654 transitions. [2018-11-18 15:30:02,548 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1642 [2018-11-18 15:30:02,549 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:30:02,549 INFO L375 BasicCegarLoop]: trace histogram [250, 231, 231, 230, 230, 230, 20, 20, 20, 20, 19, 19, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:30:02,549 INFO L423 AbstractCegarLoop]: === Iteration 57 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:30:02,549 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:30:02,550 INFO L82 PathProgramCache]: Analyzing trace with hash -1272167463, now seen corresponding path program 44 times [2018-11-18 15:30:02,550 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:30:02,550 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:30:02,550 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:30:02,550 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:30:02,550 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:30:02,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:30:03,846 INFO L134 CoverageAnalysis]: Checked inductivity of 170007 backedges. 29307 proven. 1316 refuted. 0 times theorem prover too weak. 139384 trivial. 0 not checked. [2018-11-18 15:30:03,846 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:30:03,846 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:30:03,852 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-18 15:30:04,079 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 15:30:04,079 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:30:04,091 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:30:05,380 INFO L134 CoverageAnalysis]: Checked inductivity of 170007 backedges. 29369 proven. 1254 refuted. 0 times theorem prover too weak. 139384 trivial. 0 not checked. [2018-11-18 15:30:05,397 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:30:05,397 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 45] total 69 [2018-11-18 15:30:05,398 INFO L459 AbstractCegarLoop]: Interpolant automaton has 69 states [2018-11-18 15:30:05,398 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2018-11-18 15:30:05,398 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1082, Invalid=3610, Unknown=0, NotChecked=0, Total=4692 [2018-11-18 15:30:05,399 INFO L87 Difference]: Start difference. First operand 1651 states and 1654 transitions. Second operand 69 states. [2018-11-18 15:30:06,703 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:30:06,703 INFO L93 Difference]: Finished difference Result 1800 states and 1804 transitions. [2018-11-18 15:30:06,703 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2018-11-18 15:30:06,703 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 1641 [2018-11-18 15:30:06,704 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:30:06,706 INFO L225 Difference]: With dead ends: 1800 [2018-11-18 15:30:06,707 INFO L226 Difference]: Without dead ends: 1800 [2018-11-18 15:30:06,707 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1727 GetRequests, 1619 SyntacticMatches, 0 SemanticMatches, 108 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2009 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=3047, Invalid=8943, Unknown=0, NotChecked=0, Total=11990 [2018-11-18 15:30:06,708 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1800 states. [2018-11-18 15:30:06,718 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1800 to 1790. [2018-11-18 15:30:06,719 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1790 states. [2018-11-18 15:30:06,720 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 1794 transitions. [2018-11-18 15:30:06,721 INFO L78 Accepts]: Start accepts. Automaton has 1790 states and 1794 transitions. Word has length 1641 [2018-11-18 15:30:06,721 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:30:06,722 INFO L480 AbstractCegarLoop]: Abstraction has 1790 states and 1794 transitions. [2018-11-18 15:30:06,722 INFO L481 AbstractCegarLoop]: Interpolant automaton has 69 states. [2018-11-18 15:30:06,722 INFO L276 IsEmpty]: Start isEmpty. Operand 1790 states and 1794 transitions. [2018-11-18 15:30:06,740 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1775 [2018-11-18 15:30:06,740 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:30:06,740 INFO L375 BasicCegarLoop]: trace histogram [271, 251, 251, 250, 250, 250, 21, 21, 21, 21, 20, 20, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:30:06,741 INFO L423 AbstractCegarLoop]: === Iteration 58 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:30:06,741 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:30:06,741 INFO L82 PathProgramCache]: Analyzing trace with hash -1968198802, now seen corresponding path program 45 times [2018-11-18 15:30:06,741 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:30:06,741 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:30:06,742 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:30:06,742 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:30:06,742 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:30:06,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:30:08,359 INFO L134 CoverageAnalysis]: Checked inductivity of 200340 backedges. 79679 proven. 3837 refuted. 0 times theorem prover too weak. 116824 trivial. 0 not checked. [2018-11-18 15:30:08,360 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:30:08,360 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:30:08,367 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 15:30:08,807 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 22 check-sat command(s) [2018-11-18 15:30:08,807 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:30:08,818 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:30:10,711 INFO L134 CoverageAnalysis]: Checked inductivity of 200340 backedges. 55899 proven. 3784 refuted. 0 times theorem prover too weak. 140657 trivial. 0 not checked. [2018-11-18 15:30:10,727 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:30:10,728 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 49] total 94 [2018-11-18 15:30:10,729 INFO L459 AbstractCegarLoop]: Interpolant automaton has 94 states [2018-11-18 15:30:10,729 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 94 interpolants. [2018-11-18 15:30:10,730 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1280, Invalid=7462, Unknown=0, NotChecked=0, Total=8742 [2018-11-18 15:30:10,730 INFO L87 Difference]: Start difference. First operand 1790 states and 1794 transitions. Second operand 94 states. [2018-11-18 15:30:13,531 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:30:13,531 INFO L93 Difference]: Finished difference Result 1805 states and 1807 transitions. [2018-11-18 15:30:13,532 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2018-11-18 15:30:13,532 INFO L78 Accepts]: Start accepts. Automaton has 94 states. Word has length 1774 [2018-11-18 15:30:13,532 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:30:13,534 INFO L225 Difference]: With dead ends: 1805 [2018-11-18 15:30:13,534 INFO L226 Difference]: Without dead ends: 1799 [2018-11-18 15:30:13,536 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1910 GetRequests, 1730 SyntacticMatches, 0 SemanticMatches, 180 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10525 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=5252, Invalid=27690, Unknown=0, NotChecked=0, Total=32942 [2018-11-18 15:30:13,537 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1799 states. [2018-11-18 15:30:13,546 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1799 to 1790. [2018-11-18 15:30:13,546 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1790 states. [2018-11-18 15:30:13,548 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 1792 transitions. [2018-11-18 15:30:13,548 INFO L78 Accepts]: Start accepts. Automaton has 1790 states and 1792 transitions. Word has length 1774 [2018-11-18 15:30:13,549 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:30:13,549 INFO L480 AbstractCegarLoop]: Abstraction has 1790 states and 1792 transitions. [2018-11-18 15:30:13,549 INFO L481 AbstractCegarLoop]: Interpolant automaton has 94 states. [2018-11-18 15:30:13,549 INFO L276 IsEmpty]: Start isEmpty. Operand 1790 states and 1792 transitions. [2018-11-18 15:30:13,565 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1781 [2018-11-18 15:30:13,565 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:30:13,565 INFO L375 BasicCegarLoop]: trace histogram [272, 252, 252, 251, 251, 251, 21, 21, 21, 21, 20, 20, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:30:13,565 INFO L423 AbstractCegarLoop]: === Iteration 59 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:30:13,565 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:30:13,566 INFO L82 PathProgramCache]: Analyzing trace with hash 1365116774, now seen corresponding path program 46 times [2018-11-18 15:30:13,566 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:30:13,566 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:30:13,566 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:30:13,566 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:30:13,566 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:30:13,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:30:15,345 INFO L134 CoverageAnalysis]: Checked inductivity of 201884 backedges. 30800 proven. 1344 refuted. 0 times theorem prover too weak. 169740 trivial. 0 not checked. [2018-11-18 15:30:15,345 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:30:15,345 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:30:15,353 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 15:30:15,848 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 15:30:15,849 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:30:15,867 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:30:15,869 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 15:30:15,872 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 15:30:15,876 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 15:30:15,876 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 15:30:15,881 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 15:30:15,889 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 15:30:15,889 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 15:30:19,607 INFO L134 CoverageAnalysis]: Checked inductivity of 201884 backedges. 30800 proven. 1344 refuted. 0 times theorem prover too weak. 169740 trivial. 0 not checked. [2018-11-18 15:30:19,627 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:30:19,627 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26] total 48 [2018-11-18 15:30:19,628 INFO L459 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-11-18 15:30:19,628 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-11-18 15:30:19,628 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=626, Invalid=1726, Unknown=0, NotChecked=0, Total=2352 [2018-11-18 15:30:19,629 INFO L87 Difference]: Start difference. First operand 1790 states and 1792 transitions. Second operand 49 states. [2018-11-18 15:30:20,874 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:30:20,874 INFO L93 Difference]: Finished difference Result 1804 states and 1807 transitions. [2018-11-18 15:30:20,874 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-11-18 15:30:20,874 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 1780 [2018-11-18 15:30:20,875 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:30:20,878 INFO L225 Difference]: With dead ends: 1804 [2018-11-18 15:30:20,878 INFO L226 Difference]: Without dead ends: 1804 [2018-11-18 15:30:20,878 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1827 GetRequests, 1716 SyntacticMatches, 42 SemanticMatches, 69 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1471 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=1010, Invalid=3960, Unknown=0, NotChecked=0, Total=4970 [2018-11-18 15:30:20,879 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1804 states. [2018-11-18 15:30:20,886 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1804 to 1796. [2018-11-18 15:30:20,886 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1796 states. [2018-11-18 15:30:20,888 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1796 states to 1796 states and 1799 transitions. [2018-11-18 15:30:20,888 INFO L78 Accepts]: Start accepts. Automaton has 1796 states and 1799 transitions. Word has length 1780 [2018-11-18 15:30:20,889 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:30:20,889 INFO L480 AbstractCegarLoop]: Abstraction has 1796 states and 1799 transitions. [2018-11-18 15:30:20,889 INFO L481 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-11-18 15:30:20,889 INFO L276 IsEmpty]: Start isEmpty. Operand 1796 states and 1799 transitions. [2018-11-18 15:30:20,902 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1787 [2018-11-18 15:30:20,902 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:30:20,902 INFO L375 BasicCegarLoop]: trace histogram [273, 253, 253, 252, 252, 252, 21, 21, 21, 21, 20, 20, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:30:20,903 INFO L423 AbstractCegarLoop]: === Iteration 60 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:30:20,903 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:30:20,903 INFO L82 PathProgramCache]: Analyzing trace with hash 1719464622, now seen corresponding path program 47 times [2018-11-18 15:30:20,903 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:30:20,903 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:30:20,904 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:30:20,904 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:30:20,904 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:30:20,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:30:22,359 INFO L134 CoverageAnalysis]: Checked inductivity of 203434 backedges. 33629 proven. 1455 refuted. 0 times theorem prover too weak. 168350 trivial. 0 not checked. [2018-11-18 15:30:22,360 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:30:22,360 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:30:22,367 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-18 15:30:26,846 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 55 check-sat command(s) [2018-11-18 15:30:26,847 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:30:26,874 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:30:28,415 INFO L134 CoverageAnalysis]: Checked inductivity of 203434 backedges. 33440 proven. 5017 refuted. 0 times theorem prover too weak. 164977 trivial. 0 not checked. [2018-11-18 15:30:28,437 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:30:28,437 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 52] total 76 [2018-11-18 15:30:28,438 INFO L459 AbstractCegarLoop]: Interpolant automaton has 76 states [2018-11-18 15:30:28,438 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 76 interpolants. [2018-11-18 15:30:28,439 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1189, Invalid=4511, Unknown=0, NotChecked=0, Total=5700 [2018-11-18 15:30:28,439 INFO L87 Difference]: Start difference. First operand 1796 states and 1799 transitions. Second operand 76 states. [2018-11-18 15:30:29,885 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:30:29,886 INFO L93 Difference]: Finished difference Result 1951 states and 1955 transitions. [2018-11-18 15:30:29,886 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 74 states. [2018-11-18 15:30:29,886 INFO L78 Accepts]: Start accepts. Automaton has 76 states. Word has length 1786 [2018-11-18 15:30:29,887 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:30:29,889 INFO L225 Difference]: With dead ends: 1951 [2018-11-18 15:30:29,889 INFO L226 Difference]: Without dead ends: 1951 [2018-11-18 15:30:29,890 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1878 GetRequests, 1759 SyntacticMatches, 0 SemanticMatches, 119 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2720 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=3265, Invalid=11255, Unknown=0, NotChecked=0, Total=14520 [2018-11-18 15:30:29,890 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1951 states. [2018-11-18 15:30:29,898 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1951 to 1941. [2018-11-18 15:30:29,899 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1941 states. [2018-11-18 15:30:29,901 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1941 states to 1941 states and 1945 transitions. [2018-11-18 15:30:29,901 INFO L78 Accepts]: Start accepts. Automaton has 1941 states and 1945 transitions. Word has length 1786 [2018-11-18 15:30:29,902 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:30:29,902 INFO L480 AbstractCegarLoop]: Abstraction has 1941 states and 1945 transitions. [2018-11-18 15:30:29,902 INFO L481 AbstractCegarLoop]: Interpolant automaton has 76 states. [2018-11-18 15:30:29,902 INFO L276 IsEmpty]: Start isEmpty. Operand 1941 states and 1945 transitions. [2018-11-18 15:30:29,918 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1926 [2018-11-18 15:30:29,919 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:30:29,919 INFO L375 BasicCegarLoop]: trace histogram [295, 274, 274, 273, 273, 273, 22, 22, 22, 22, 21, 21, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:30:29,919 INFO L423 AbstractCegarLoop]: === Iteration 61 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:30:29,920 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:30:29,920 INFO L82 PathProgramCache]: Analyzing trace with hash 1907288769, now seen corresponding path program 48 times [2018-11-18 15:30:29,920 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:30:29,920 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:30:29,921 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:30:29,921 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:30:29,921 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:30:30,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:30:31,695 INFO L134 CoverageAnalysis]: Checked inductivity of 238182 backedges. 66658 proven. 6450 refuted. 0 times theorem prover too weak. 165074 trivial. 0 not checked. [2018-11-18 15:30:31,695 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:30:31,695 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:30:31,703 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-18 15:30:33,275 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 45 check-sat command(s) [2018-11-18 15:30:33,275 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:30:33,293 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:30:35,365 INFO L134 CoverageAnalysis]: Checked inductivity of 238182 backedges. 64260 proven. 4162 refuted. 0 times theorem prover too weak. 169760 trivial. 0 not checked. [2018-11-18 15:30:35,384 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:30:35,384 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 51] total 98 [2018-11-18 15:30:35,385 INFO L459 AbstractCegarLoop]: Interpolant automaton has 98 states [2018-11-18 15:30:35,386 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 98 interpolants. [2018-11-18 15:30:35,386 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1377, Invalid=8129, Unknown=0, NotChecked=0, Total=9506 [2018-11-18 15:30:35,386 INFO L87 Difference]: Start difference. First operand 1941 states and 1945 transitions. Second operand 98 states. [2018-11-18 15:30:38,405 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:30:38,405 INFO L93 Difference]: Finished difference Result 1956 states and 1958 transitions. [2018-11-18 15:30:38,405 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 119 states. [2018-11-18 15:30:38,405 INFO L78 Accepts]: Start accepts. Automaton has 98 states. Word has length 1925 [2018-11-18 15:30:38,406 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:30:38,407 INFO L225 Difference]: With dead ends: 1956 [2018-11-18 15:30:38,407 INFO L226 Difference]: Without dead ends: 1950 [2018-11-18 15:30:38,409 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2086 GetRequests, 1879 SyntacticMatches, 0 SemanticMatches, 207 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15243 ImplicationChecksByTransitivity, 3.1s TimeCoverageRelationStatistics Valid=5910, Invalid=37562, Unknown=0, NotChecked=0, Total=43472 [2018-11-18 15:30:38,410 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1950 states. [2018-11-18 15:30:38,417 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1950 to 1941. [2018-11-18 15:30:38,417 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1941 states. [2018-11-18 15:30:38,419 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1941 states to 1941 states and 1943 transitions. [2018-11-18 15:30:38,419 INFO L78 Accepts]: Start accepts. Automaton has 1941 states and 1943 transitions. Word has length 1925 [2018-11-18 15:30:38,420 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:30:38,420 INFO L480 AbstractCegarLoop]: Abstraction has 1941 states and 1943 transitions. [2018-11-18 15:30:38,420 INFO L481 AbstractCegarLoop]: Interpolant automaton has 98 states. [2018-11-18 15:30:38,420 INFO L276 IsEmpty]: Start isEmpty. Operand 1941 states and 1943 transitions. [2018-11-18 15:30:38,434 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1932 [2018-11-18 15:30:38,434 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:30:38,435 INFO L375 BasicCegarLoop]: trace histogram [296, 275, 275, 274, 274, 274, 22, 22, 22, 22, 21, 21, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:30:38,435 INFO L423 AbstractCegarLoop]: === Iteration 62 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:30:38,435 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:30:38,435 INFO L82 PathProgramCache]: Analyzing trace with hash 1398241401, now seen corresponding path program 49 times [2018-11-18 15:30:38,436 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:30:38,436 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:30:38,436 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:30:38,436 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:30:38,436 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:30:38,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:30:40,402 INFO L134 CoverageAnalysis]: Checked inductivity of 239866 backedges. 35259 proven. 1474 refuted. 0 times theorem prover too weak. 203133 trivial. 0 not checked. [2018-11-18 15:30:40,402 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:30:40,402 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:30:40,410 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:30:40,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:30:40,679 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:30:40,681 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 15:30:40,688 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 15:30:40,695 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 15:30:40,695 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 15:30:40,700 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 15:30:40,706 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 15:30:40,706 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 15:30:44,821 INFO L134 CoverageAnalysis]: Checked inductivity of 239866 backedges. 35259 proven. 1474 refuted. 0 times theorem prover too weak. 203133 trivial. 0 not checked. [2018-11-18 15:30:44,838 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:30:44,839 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27] total 50 [2018-11-18 15:30:44,839 INFO L459 AbstractCegarLoop]: Interpolant automaton has 51 states [2018-11-18 15:30:44,840 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2018-11-18 15:30:44,840 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=677, Invalid=1873, Unknown=0, NotChecked=0, Total=2550 [2018-11-18 15:30:44,840 INFO L87 Difference]: Start difference. First operand 1941 states and 1943 transitions. Second operand 51 states. [2018-11-18 15:30:46,143 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:30:46,143 INFO L93 Difference]: Finished difference Result 1955 states and 1958 transitions. [2018-11-18 15:30:46,143 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-11-18 15:30:46,143 INFO L78 Accepts]: Start accepts. Automaton has 51 states. Word has length 1931 [2018-11-18 15:30:46,144 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:30:46,147 INFO L225 Difference]: With dead ends: 1955 [2018-11-18 15:30:46,147 INFO L226 Difference]: Without dead ends: 1955 [2018-11-18 15:30:46,148 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1980 GetRequests, 1864 SyntacticMatches, 44 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1607 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=1090, Invalid=4312, Unknown=0, NotChecked=0, Total=5402 [2018-11-18 15:30:46,149 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1955 states. [2018-11-18 15:30:46,159 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1955 to 1947. [2018-11-18 15:30:46,160 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1947 states. [2018-11-18 15:30:46,161 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1947 states to 1947 states and 1950 transitions. [2018-11-18 15:30:46,162 INFO L78 Accepts]: Start accepts. Automaton has 1947 states and 1950 transitions. Word has length 1931 [2018-11-18 15:30:46,163 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:30:46,163 INFO L480 AbstractCegarLoop]: Abstraction has 1947 states and 1950 transitions. [2018-11-18 15:30:46,163 INFO L481 AbstractCegarLoop]: Interpolant automaton has 51 states. [2018-11-18 15:30:46,163 INFO L276 IsEmpty]: Start isEmpty. Operand 1947 states and 1950 transitions. [2018-11-18 15:30:46,180 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1938 [2018-11-18 15:30:46,180 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:30:46,181 INFO L375 BasicCegarLoop]: trace histogram [297, 276, 276, 275, 275, 275, 22, 22, 22, 22, 21, 21, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:30:46,181 INFO L423 AbstractCegarLoop]: === Iteration 63 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:30:46,181 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:30:46,182 INFO L82 PathProgramCache]: Analyzing trace with hash -688649855, now seen corresponding path program 50 times [2018-11-18 15:30:46,182 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:30:46,182 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:30:46,182 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:30:46,182 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:30:46,183 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:30:46,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:30:47,850 INFO L134 CoverageAnalysis]: Checked inductivity of 241556 backedges. 38355 proven. 1601 refuted. 0 times theorem prover too weak. 201600 trivial. 0 not checked. [2018-11-18 15:30:47,851 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:30:47,851 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:30:47,858 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-18 15:30:48,129 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 15:30:48,129 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:30:48,144 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:30:49,793 INFO L134 CoverageAnalysis]: Checked inductivity of 241556 backedges. 38423 proven. 1533 refuted. 0 times theorem prover too weak. 201600 trivial. 0 not checked. [2018-11-18 15:30:49,810 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:30:49,810 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 49] total 75 [2018-11-18 15:30:49,811 INFO L459 AbstractCegarLoop]: Interpolant automaton has 75 states [2018-11-18 15:30:49,811 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 75 interpolants. [2018-11-18 15:30:49,811 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1276, Invalid=4274, Unknown=0, NotChecked=0, Total=5550 [2018-11-18 15:30:49,811 INFO L87 Difference]: Start difference. First operand 1947 states and 1950 transitions. Second operand 75 states. [2018-11-18 15:30:51,169 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:30:51,169 INFO L93 Difference]: Finished difference Result 2108 states and 2112 transitions. [2018-11-18 15:30:51,170 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 71 states. [2018-11-18 15:30:51,170 INFO L78 Accepts]: Start accepts. Automaton has 75 states. Word has length 1937 [2018-11-18 15:30:51,171 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:30:51,173 INFO L225 Difference]: With dead ends: 2108 [2018-11-18 15:30:51,173 INFO L226 Difference]: Without dead ends: 2108 [2018-11-18 15:30:51,173 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2031 GetRequests, 1913 SyntacticMatches, 0 SemanticMatches, 118 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2408 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=3613, Invalid=10667, Unknown=0, NotChecked=0, Total=14280 [2018-11-18 15:30:51,174 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2108 states. [2018-11-18 15:30:51,182 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2108 to 2098. [2018-11-18 15:30:51,182 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2098 states. [2018-11-18 15:30:51,184 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2098 states to 2098 states and 2102 transitions. [2018-11-18 15:30:51,184 INFO L78 Accepts]: Start accepts. Automaton has 2098 states and 2102 transitions. Word has length 1937 [2018-11-18 15:30:51,185 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:30:51,185 INFO L480 AbstractCegarLoop]: Abstraction has 2098 states and 2102 transitions. [2018-11-18 15:30:51,185 INFO L481 AbstractCegarLoop]: Interpolant automaton has 75 states. [2018-11-18 15:30:51,185 INFO L276 IsEmpty]: Start isEmpty. Operand 2098 states and 2102 transitions. [2018-11-18 15:30:51,203 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2083 [2018-11-18 15:30:51,203 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:30:51,203 INFO L375 BasicCegarLoop]: trace histogram [320, 298, 298, 297, 297, 297, 23, 23, 23, 23, 22, 22, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:30:51,203 INFO L423 AbstractCegarLoop]: === Iteration 64 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:30:51,203 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:30:51,204 INFO L82 PathProgramCache]: Analyzing trace with hash 266198870, now seen corresponding path program 51 times [2018-11-18 15:30:51,204 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:30:51,204 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:30:51,204 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:30:51,205 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:30:51,205 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:30:51,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:30:53,456 INFO L134 CoverageAnalysis]: Checked inductivity of 281127 backedges. 39986 proven. 1610 refuted. 0 times theorem prover too weak. 239531 trivial. 0 not checked. [2018-11-18 15:30:53,456 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:30:53,456 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:30:53,463 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 15:30:54,109 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) [2018-11-18 15:30:54,109 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:30:54,123 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:30:56,459 INFO L134 CoverageAnalysis]: Checked inductivity of 281127 backedges. 73415 proven. 4558 refuted. 0 times theorem prover too weak. 203154 trivial. 0 not checked. [2018-11-18 15:30:56,477 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:30:56,478 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 53] total 80 [2018-11-18 15:30:56,478 INFO L459 AbstractCegarLoop]: Interpolant automaton has 80 states [2018-11-18 15:30:56,478 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 80 interpolants. [2018-11-18 15:30:56,479 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=966, Invalid=5354, Unknown=0, NotChecked=0, Total=6320 [2018-11-18 15:30:56,479 INFO L87 Difference]: Start difference. First operand 2098 states and 2102 transitions. Second operand 80 states. [2018-11-18 15:30:59,721 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:30:59,721 INFO L93 Difference]: Finished difference Result 2276 states and 2282 transitions. [2018-11-18 15:30:59,721 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 81 states. [2018-11-18 15:30:59,721 INFO L78 Accepts]: Start accepts. Automaton has 80 states. Word has length 2082 [2018-11-18 15:30:59,722 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:30:59,725 INFO L225 Difference]: With dead ends: 2276 [2018-11-18 15:30:59,725 INFO L226 Difference]: Without dead ends: 2276 [2018-11-18 15:30:59,726 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2186 GetRequests, 2031 SyntacticMatches, 0 SemanticMatches, 155 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6270 ImplicationChecksByTransitivity, 3.5s TimeCoverageRelationStatistics Valid=4703, Invalid=19789, Unknown=0, NotChecked=0, Total=24492 [2018-11-18 15:30:59,727 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2276 states. [2018-11-18 15:30:59,734 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2276 to 2110. [2018-11-18 15:30:59,734 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2110 states. [2018-11-18 15:30:59,736 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2110 states to 2110 states and 2115 transitions. [2018-11-18 15:30:59,736 INFO L78 Accepts]: Start accepts. Automaton has 2110 states and 2115 transitions. Word has length 2082 [2018-11-18 15:30:59,736 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:30:59,736 INFO L480 AbstractCegarLoop]: Abstraction has 2110 states and 2115 transitions. [2018-11-18 15:30:59,737 INFO L481 AbstractCegarLoop]: Interpolant automaton has 80 states. [2018-11-18 15:30:59,737 INFO L276 IsEmpty]: Start isEmpty. Operand 2110 states and 2115 transitions. [2018-11-18 15:30:59,751 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2095 [2018-11-18 15:30:59,752 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:30:59,752 INFO L375 BasicCegarLoop]: trace histogram [322, 300, 300, 299, 299, 299, 23, 23, 23, 23, 22, 22, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:30:59,752 INFO L423 AbstractCegarLoop]: === Iteration 65 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:30:59,752 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:30:59,752 INFO L82 PathProgramCache]: Analyzing trace with hash 1360921238, now seen corresponding path program 52 times [2018-11-18 15:30:59,752 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:30:59,752 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:30:59,753 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:30:59,753 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:30:59,753 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:30:59,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:31:02,034 INFO L134 CoverageAnalysis]: Checked inductivity of 284793 backedges. 41822 proven. 1752 refuted. 0 times theorem prover too weak. 241219 trivial. 0 not checked. [2018-11-18 15:31:02,035 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:31:02,035 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:31:02,042 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 15:31:02,319 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 15:31:02,319 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:31:02,339 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:31:04,640 INFO L134 CoverageAnalysis]: Checked inductivity of 284793 backedges. 43298 proven. 5980 refuted. 0 times theorem prover too weak. 235515 trivial. 0 not checked. [2018-11-18 15:31:04,657 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:31:04,657 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 55] total 83 [2018-11-18 15:31:04,658 INFO L459 AbstractCegarLoop]: Interpolant automaton has 83 states [2018-11-18 15:31:04,659 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 83 interpolants. [2018-11-18 15:31:04,659 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1022, Invalid=5784, Unknown=0, NotChecked=0, Total=6806 [2018-11-18 15:31:04,659 INFO L87 Difference]: Start difference. First operand 2110 states and 2115 transitions. Second operand 83 states. [2018-11-18 15:31:08,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:31:08,121 INFO L93 Difference]: Finished difference Result 2459 states and 2470 transitions. [2018-11-18 15:31:08,122 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 85 states. [2018-11-18 15:31:08,122 INFO L78 Accepts]: Start accepts. Automaton has 83 states. Word has length 2094 [2018-11-18 15:31:08,122 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:31:08,124 INFO L225 Difference]: With dead ends: 2459 [2018-11-18 15:31:08,124 INFO L226 Difference]: Without dead ends: 2459 [2018-11-18 15:31:08,125 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2226 GetRequests, 2064 SyntacticMatches, 0 SemanticMatches, 162 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6949 ImplicationChecksByTransitivity, 3.7s TimeCoverageRelationStatistics Valid=3786, Invalid=22946, Unknown=0, NotChecked=0, Total=26732 [2018-11-18 15:31:08,126 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2459 states. [2018-11-18 15:31:08,136 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2459 to 2437. [2018-11-18 15:31:08,136 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2437 states. [2018-11-18 15:31:08,138 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2437 states to 2437 states and 2448 transitions. [2018-11-18 15:31:08,138 INFO L78 Accepts]: Start accepts. Automaton has 2437 states and 2448 transitions. Word has length 2094 [2018-11-18 15:31:08,139 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:31:08,139 INFO L480 AbstractCegarLoop]: Abstraction has 2437 states and 2448 transitions. [2018-11-18 15:31:08,139 INFO L481 AbstractCegarLoop]: Interpolant automaton has 83 states. [2018-11-18 15:31:08,139 INFO L276 IsEmpty]: Start isEmpty. Operand 2437 states and 2448 transitions. [2018-11-18 15:31:08,157 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2246 [2018-11-18 15:31:08,157 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:31:08,158 INFO L375 BasicCegarLoop]: trace histogram [346, 323, 323, 322, 322, 322, 24, 24, 24, 24, 23, 23, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:31:08,158 INFO L423 AbstractCegarLoop]: === Iteration 66 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:31:08,158 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:31:08,158 INFO L82 PathProgramCache]: Analyzing trace with hash 1129057257, now seen corresponding path program 53 times [2018-11-18 15:31:08,158 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:31:08,158 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:31:08,159 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:31:08,159 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:31:08,159 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:31:08,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:31:10,331 INFO L134 CoverageAnalysis]: Checked inductivity of 329613 backedges. 83189 proven. 10651 refuted. 0 times theorem prover too weak. 235773 trivial. 0 not checked. [2018-11-18 15:31:10,332 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:31:10,332 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:31:10,339 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-18 15:31:14,761 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 57 check-sat command(s) [2018-11-18 15:31:14,761 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:31:14,790 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:31:16,742 INFO L134 CoverageAnalysis]: Checked inductivity of 329613 backedges. 119078 proven. 8587 refuted. 0 times theorem prover too weak. 201948 trivial. 0 not checked. [2018-11-18 15:31:16,768 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:31:16,769 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 52] total 80 [2018-11-18 15:31:16,770 INFO L459 AbstractCegarLoop]: Interpolant automaton has 80 states [2018-11-18 15:31:16,770 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 80 interpolants. [2018-11-18 15:31:16,770 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1194, Invalid=5126, Unknown=0, NotChecked=0, Total=6320 [2018-11-18 15:31:16,770 INFO L87 Difference]: Start difference. First operand 2437 states and 2448 transitions. Second operand 80 states. [2018-11-18 15:31:18,230 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:31:18,230 INFO L93 Difference]: Finished difference Result 2279 states and 2284 transitions. [2018-11-18 15:31:18,231 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 74 states. [2018-11-18 15:31:18,231 INFO L78 Accepts]: Start accepts. Automaton has 80 states. Word has length 2245 [2018-11-18 15:31:18,232 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:31:18,235 INFO L225 Difference]: With dead ends: 2279 [2018-11-18 15:31:18,235 INFO L226 Difference]: Without dead ends: 2270 [2018-11-18 15:31:18,237 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2347 GetRequests, 2219 SyntacticMatches, 0 SemanticMatches, 128 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5357 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=3610, Invalid=13160, Unknown=0, NotChecked=0, Total=16770 [2018-11-18 15:31:18,238 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2270 states. [2018-11-18 15:31:18,248 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2270 to 2267. [2018-11-18 15:31:18,249 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2267 states. [2018-11-18 15:31:18,251 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2267 states to 2267 states and 2272 transitions. [2018-11-18 15:31:18,251 INFO L78 Accepts]: Start accepts. Automaton has 2267 states and 2272 transitions. Word has length 2245 [2018-11-18 15:31:18,252 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:31:18,253 INFO L480 AbstractCegarLoop]: Abstraction has 2267 states and 2272 transitions. [2018-11-18 15:31:18,253 INFO L481 AbstractCegarLoop]: Interpolant automaton has 80 states. [2018-11-18 15:31:18,253 INFO L276 IsEmpty]: Start isEmpty. Operand 2267 states and 2272 transitions. [2018-11-18 15:31:18,275 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2252 [2018-11-18 15:31:18,275 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:31:18,276 INFO L375 BasicCegarLoop]: trace histogram [347, 324, 324, 323, 323, 323, 24, 24, 24, 24, 23, 23, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:31:18,276 INFO L423 AbstractCegarLoop]: === Iteration 67 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:31:18,276 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:31:18,277 INFO L82 PathProgramCache]: Analyzing trace with hash 698270449, now seen corresponding path program 54 times [2018-11-18 15:31:18,277 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:31:18,277 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:31:18,277 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:31:18,277 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:31:18,278 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:31:18,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:31:20,566 INFO L134 CoverageAnalysis]: Checked inductivity of 331595 backedges. 88155 proven. 7674 refuted. 0 times theorem prover too weak. 235766 trivial. 0 not checked. [2018-11-18 15:31:20,566 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:31:20,566 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:31:20,573 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-18 15:31:24,459 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 49 check-sat command(s) [2018-11-18 15:31:24,459 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:31:24,482 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:31:24,489 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 15:31:24,491 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 15:31:24,497 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 15:31:24,497 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 15:31:24,504 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 15:31:24,512 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 15:31:24,512 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 15:31:31,591 INFO L134 CoverageAnalysis]: Checked inductivity of 331595 backedges. 83296 proven. 5208 refuted. 0 times theorem prover too weak. 243091 trivial. 0 not checked. [2018-11-18 15:31:31,610 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:31:31,610 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 34] total 87 [2018-11-18 15:31:31,611 INFO L459 AbstractCegarLoop]: Interpolant automaton has 87 states [2018-11-18 15:31:31,611 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 87 interpolants. [2018-11-18 15:31:31,612 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1293, Invalid=6189, Unknown=0, NotChecked=0, Total=7482 [2018-11-18 15:31:31,612 INFO L87 Difference]: Start difference. First operand 2267 states and 2272 transitions. Second operand 87 states. [2018-11-18 15:31:36,418 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:31:36,418 INFO L93 Difference]: Finished difference Result 2280 states and 2283 transitions. [2018-11-18 15:31:36,419 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 129 states. [2018-11-18 15:31:36,419 INFO L78 Accepts]: Start accepts. Automaton has 87 states. Word has length 2251 [2018-11-18 15:31:36,420 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:31:36,422 INFO L225 Difference]: With dead ends: 2280 [2018-11-18 15:31:36,422 INFO L226 Difference]: Without dead ends: 2274 [2018-11-18 15:31:36,425 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2429 GetRequests, 2176 SyntacticMatches, 44 SemanticMatches, 209 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17077 ImplicationChecksByTransitivity, 5.4s TimeCoverageRelationStatistics Valid=7151, Invalid=37159, Unknown=0, NotChecked=0, Total=44310 [2018-11-18 15:31:36,426 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2274 states. [2018-11-18 15:31:36,433 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2274 to 2267. [2018-11-18 15:31:36,433 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2267 states. [2018-11-18 15:31:36,435 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2267 states to 2267 states and 2270 transitions. [2018-11-18 15:31:36,435 INFO L78 Accepts]: Start accepts. Automaton has 2267 states and 2270 transitions. Word has length 2251 [2018-11-18 15:31:36,436 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:31:36,437 INFO L480 AbstractCegarLoop]: Abstraction has 2267 states and 2270 transitions. [2018-11-18 15:31:36,437 INFO L481 AbstractCegarLoop]: Interpolant automaton has 87 states. [2018-11-18 15:31:36,437 INFO L276 IsEmpty]: Start isEmpty. Operand 2267 states and 2270 transitions. [2018-11-18 15:31:36,454 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2258 [2018-11-18 15:31:36,455 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:31:36,455 INFO L375 BasicCegarLoop]: trace histogram [348, 325, 325, 324, 324, 324, 24, 24, 24, 24, 23, 23, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:31:36,455 INFO L423 AbstractCegarLoop]: === Iteration 68 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:31:36,455 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:31:36,456 INFO L82 PathProgramCache]: Analyzing trace with hash -1199365975, now seen corresponding path program 55 times [2018-11-18 15:31:36,456 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:31:36,456 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:31:36,457 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:31:36,457 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:31:36,457 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:31:36,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:31:38,593 INFO L134 CoverageAnalysis]: Checked inductivity of 333583 backedges. 49091 proven. 1914 refuted. 0 times theorem prover too weak. 282578 trivial. 0 not checked. [2018-11-18 15:31:38,593 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:31:38,593 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:31:38,600 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:31:38,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:31:38,901 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:31:41,053 INFO L134 CoverageAnalysis]: Checked inductivity of 333583 backedges. 49165 proven. 1840 refuted. 0 times theorem prover too weak. 282578 trivial. 0 not checked. [2018-11-18 15:31:41,073 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:31:41,074 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 53] total 81 [2018-11-18 15:31:41,075 INFO L459 AbstractCegarLoop]: Interpolant automaton has 81 states [2018-11-18 15:31:41,076 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 81 interpolants. [2018-11-18 15:31:41,076 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1486, Invalid=4994, Unknown=0, NotChecked=0, Total=6480 [2018-11-18 15:31:41,076 INFO L87 Difference]: Start difference. First operand 2267 states and 2270 transitions. Second operand 81 states. [2018-11-18 15:31:42,253 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:31:42,253 INFO L93 Difference]: Finished difference Result 2440 states and 2444 transitions. [2018-11-18 15:31:42,254 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 77 states. [2018-11-18 15:31:42,254 INFO L78 Accepts]: Start accepts. Automaton has 81 states. Word has length 2257 [2018-11-18 15:31:42,255 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:31:42,256 INFO L225 Difference]: With dead ends: 2440 [2018-11-18 15:31:42,257 INFO L226 Difference]: Without dead ends: 2440 [2018-11-18 15:31:42,257 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2359 GetRequests, 2231 SyntacticMatches, 0 SemanticMatches, 128 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2843 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=4227, Invalid=12543, Unknown=0, NotChecked=0, Total=16770 [2018-11-18 15:31:42,258 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2440 states. [2018-11-18 15:31:42,268 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2440 to 2430. [2018-11-18 15:31:42,268 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2430 states. [2018-11-18 15:31:42,270 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2430 states to 2430 states and 2434 transitions. [2018-11-18 15:31:42,270 INFO L78 Accepts]: Start accepts. Automaton has 2430 states and 2434 transitions. Word has length 2257 [2018-11-18 15:31:42,270 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:31:42,270 INFO L480 AbstractCegarLoop]: Abstraction has 2430 states and 2434 transitions. [2018-11-18 15:31:42,271 INFO L481 AbstractCegarLoop]: Interpolant automaton has 81 states. [2018-11-18 15:31:42,271 INFO L276 IsEmpty]: Start isEmpty. Operand 2430 states and 2434 transitions. [2018-11-18 15:31:42,291 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2415 [2018-11-18 15:31:42,291 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:31:42,291 INFO L375 BasicCegarLoop]: trace histogram [373, 349, 349, 348, 348, 348, 25, 25, 25, 25, 24, 24, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:31:42,291 INFO L423 AbstractCegarLoop]: === Iteration 69 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:31:42,291 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:31:42,292 INFO L82 PathProgramCache]: Analyzing trace with hash 491606462, now seen corresponding path program 56 times [2018-11-18 15:31:42,292 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:31:42,292 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:31:42,292 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:31:42,293 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:31:42,293 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:31:42,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:31:44,988 INFO L134 CoverageAnalysis]: Checked inductivity of 384096 backedges. 135463 proven. 5469 refuted. 0 times theorem prover too weak. 243164 trivial. 0 not checked. [2018-11-18 15:31:44,989 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:31:44,989 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:31:44,996 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-18 15:31:45,319 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 15:31:45,319 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:31:45,337 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:31:47,976 INFO L134 CoverageAnalysis]: Checked inductivity of 384096 backedges. 97891 proven. 1704 refuted. 0 times theorem prover too weak. 284501 trivial. 0 not checked. [2018-11-18 15:31:47,997 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:31:47,998 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 52] total 103 [2018-11-18 15:31:47,999 INFO L459 AbstractCegarLoop]: Interpolant automaton has 103 states [2018-11-18 15:31:47,999 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 103 interpolants. [2018-11-18 15:31:48,000 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1704, Invalid=8802, Unknown=0, NotChecked=0, Total=10506 [2018-11-18 15:31:48,000 INFO L87 Difference]: Start difference. First operand 2430 states and 2434 transitions. Second operand 103 states. [2018-11-18 15:31:51,046 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:31:51,046 INFO L93 Difference]: Finished difference Result 2441 states and 2443 transitions. [2018-11-18 15:31:51,047 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 100 states. [2018-11-18 15:31:51,047 INFO L78 Accepts]: Start accepts. Automaton has 103 states. Word has length 2414 [2018-11-18 15:31:51,048 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:31:51,050 INFO L225 Difference]: With dead ends: 2441 [2018-11-18 15:31:51,050 INFO L226 Difference]: Without dead ends: 2435 [2018-11-18 15:31:51,052 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2543 GetRequests, 2369 SyntacticMatches, 0 SemanticMatches, 174 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10445 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=4843, Invalid=25957, Unknown=0, NotChecked=0, Total=30800 [2018-11-18 15:31:51,053 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2435 states. [2018-11-18 15:31:51,061 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2435 to 2430. [2018-11-18 15:31:51,062 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2430 states. [2018-11-18 15:31:51,063 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2430 states to 2430 states and 2432 transitions. [2018-11-18 15:31:51,064 INFO L78 Accepts]: Start accepts. Automaton has 2430 states and 2432 transitions. Word has length 2414 [2018-11-18 15:31:51,065 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:31:51,065 INFO L480 AbstractCegarLoop]: Abstraction has 2430 states and 2432 transitions. [2018-11-18 15:31:51,065 INFO L481 AbstractCegarLoop]: Interpolant automaton has 103 states. [2018-11-18 15:31:51,065 INFO L276 IsEmpty]: Start isEmpty. Operand 2430 states and 2432 transitions. [2018-11-18 15:31:51,085 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2421 [2018-11-18 15:31:51,085 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:31:51,086 INFO L375 BasicCegarLoop]: trace histogram [374, 350, 350, 349, 349, 349, 25, 25, 25, 25, 24, 24, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:31:51,086 INFO L423 AbstractCegarLoop]: === Iteration 70 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:31:51,086 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:31:51,087 INFO L82 PathProgramCache]: Analyzing trace with hash -1024679498, now seen corresponding path program 57 times [2018-11-18 15:31:51,087 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:31:51,087 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:31:51,087 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:31:51,087 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:31:51,088 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:31:51,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:31:54,037 INFO L134 CoverageAnalysis]: Checked inductivity of 386236 backedges. 51168 proven. 1900 refuted. 0 times theorem prover too weak. 333168 trivial. 0 not checked. [2018-11-18 15:31:54,037 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:31:54,037 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:31:54,044 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 15:31:55,170 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 26 check-sat command(s) [2018-11-18 15:31:55,170 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:31:55,192 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:31:55,194 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 15:31:55,201 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 15:31:55,205 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 15:31:55,206 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 15:31:55,212 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 15:31:55,220 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 15:31:55,220 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 15:32:01,589 INFO L134 CoverageAnalysis]: Checked inductivity of 386236 backedges. 51168 proven. 1900 refuted. 0 times theorem prover too weak. 333168 trivial. 0 not checked. [2018-11-18 15:32:01,607 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:32:01,607 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 31] total 32 [2018-11-18 15:32:01,607 INFO L459 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-11-18 15:32:01,608 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-11-18 15:32:01,608 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=446, Invalid=610, Unknown=0, NotChecked=0, Total=1056 [2018-11-18 15:32:01,608 INFO L87 Difference]: Start difference. First operand 2430 states and 2432 transitions. Second operand 33 states. [2018-11-18 15:32:02,290 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:32:02,290 INFO L93 Difference]: Finished difference Result 2444 states and 2447 transitions. [2018-11-18 15:32:02,290 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-11-18 15:32:02,290 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 2420 [2018-11-18 15:32:02,291 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:32:02,293 INFO L225 Difference]: With dead ends: 2444 [2018-11-18 15:32:02,293 INFO L226 Difference]: Without dead ends: 2444 [2018-11-18 15:32:02,293 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2475 GetRequests, 2368 SyntacticMatches, 50 SemanticMatches, 57 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 524 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=1253, Invalid=2169, Unknown=0, NotChecked=0, Total=3422 [2018-11-18 15:32:02,294 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2444 states. [2018-11-18 15:32:02,307 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2444 to 2436. [2018-11-18 15:32:02,307 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2436 states. [2018-11-18 15:32:02,309 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2436 states to 2436 states and 2439 transitions. [2018-11-18 15:32:02,309 INFO L78 Accepts]: Start accepts. Automaton has 2436 states and 2439 transitions. Word has length 2420 [2018-11-18 15:32:02,310 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:32:02,310 INFO L480 AbstractCegarLoop]: Abstraction has 2436 states and 2439 transitions. [2018-11-18 15:32:02,310 INFO L481 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-11-18 15:32:02,310 INFO L276 IsEmpty]: Start isEmpty. Operand 2436 states and 2439 transitions. [2018-11-18 15:32:02,334 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2427 [2018-11-18 15:32:02,334 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:32:02,335 INFO L375 BasicCegarLoop]: trace histogram [375, 351, 351, 350, 350, 350, 25, 25, 25, 25, 24, 24, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:32:02,335 INFO L423 AbstractCegarLoop]: === Iteration 71 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:32:02,335 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:32:02,335 INFO L82 PathProgramCache]: Analyzing trace with hash -48066306, now seen corresponding path program 58 times [2018-11-18 15:32:02,335 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:32:02,336 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:32:02,336 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:32:02,336 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:32:02,336 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:32:02,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:32:04,863 INFO L134 CoverageAnalysis]: Checked inductivity of 388382 backedges. 55137 proven. 2081 refuted. 0 times theorem prover too weak. 331164 trivial. 0 not checked. [2018-11-18 15:32:04,863 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:32:04,863 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:32:04,870 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 15:32:05,148 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 15:32:05,148 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:32:05,166 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:32:07,700 INFO L134 CoverageAnalysis]: Checked inductivity of 388382 backedges. 54916 proven. 7027 refuted. 0 times theorem prover too weak. 326439 trivial. 0 not checked. [2018-11-18 15:32:07,717 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:32:07,718 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 59] total 88 [2018-11-18 15:32:07,718 INFO L459 AbstractCegarLoop]: Interpolant automaton has 88 states [2018-11-18 15:32:07,719 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 88 interpolants. [2018-11-18 15:32:07,719 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1609, Invalid=6047, Unknown=0, NotChecked=0, Total=7656 [2018-11-18 15:32:07,719 INFO L87 Difference]: Start difference. First operand 2436 states and 2439 transitions. Second operand 88 states. [2018-11-18 15:32:09,870 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:32:09,871 INFO L93 Difference]: Finished difference Result 2615 states and 2619 transitions. [2018-11-18 15:32:09,871 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 86 states. [2018-11-18 15:32:09,871 INFO L78 Accepts]: Start accepts. Automaton has 88 states. Word has length 2426 [2018-11-18 15:32:09,872 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:32:09,874 INFO L225 Difference]: With dead ends: 2615 [2018-11-18 15:32:09,874 INFO L226 Difference]: Without dead ends: 2615 [2018-11-18 15:32:09,875 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2534 GetRequests, 2395 SyntacticMatches, 0 SemanticMatches, 139 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3686 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=4473, Invalid=15267, Unknown=0, NotChecked=0, Total=19740 [2018-11-18 15:32:09,875 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2615 states. [2018-11-18 15:32:09,883 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2615 to 2605. [2018-11-18 15:32:09,884 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2605 states. [2018-11-18 15:32:09,885 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2605 states to 2605 states and 2609 transitions. [2018-11-18 15:32:09,885 INFO L78 Accepts]: Start accepts. Automaton has 2605 states and 2609 transitions. Word has length 2426 [2018-11-18 15:32:09,886 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:32:09,886 INFO L480 AbstractCegarLoop]: Abstraction has 2605 states and 2609 transitions. [2018-11-18 15:32:09,886 INFO L481 AbstractCegarLoop]: Interpolant automaton has 88 states. [2018-11-18 15:32:09,886 INFO L276 IsEmpty]: Start isEmpty. Operand 2605 states and 2609 transitions. [2018-11-18 15:32:09,908 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2590 [2018-11-18 15:32:09,908 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:32:09,908 INFO L375 BasicCegarLoop]: trace histogram [401, 376, 376, 375, 375, 375, 26, 26, 26, 26, 25, 25, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:32:09,909 INFO L423 AbstractCegarLoop]: === Iteration 72 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:32:09,909 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:32:09,909 INFO L82 PathProgramCache]: Analyzing trace with hash -1655328111, now seen corresponding path program 59 times [2018-11-18 15:32:09,909 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:32:09,909 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:32:09,909 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:32:09,909 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:32:09,910 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:32:10,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:32:12,777 INFO L134 CoverageAnalysis]: Checked inductivity of 445050 backedges. 109500 proven. 9002 refuted. 0 times theorem prover too weak. 326548 trivial. 0 not checked. [2018-11-18 15:32:12,777 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:32:12,777 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:32:12,785 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-18 15:32:20,142 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 60 check-sat command(s) [2018-11-18 15:32:20,142 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:32:20,179 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:32:22,781 INFO L134 CoverageAnalysis]: Checked inductivity of 445050 backedges. 109462 proven. 10996 refuted. 0 times theorem prover too weak. 324592 trivial. 0 not checked. [2018-11-18 15:32:22,808 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:32:22,809 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 58] total 89 [2018-11-18 15:32:22,809 INFO L459 AbstractCegarLoop]: Interpolant automaton has 89 states [2018-11-18 15:32:22,810 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 89 interpolants. [2018-11-18 15:32:22,810 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1500, Invalid=6332, Unknown=0, NotChecked=0, Total=7832 [2018-11-18 15:32:22,810 INFO L87 Difference]: Start difference. First operand 2605 states and 2609 transitions. Second operand 89 states. [2018-11-18 15:32:24,572 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:32:24,572 INFO L93 Difference]: Finished difference Result 2616 states and 2618 transitions. [2018-11-18 15:32:24,572 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 83 states. [2018-11-18 15:32:24,572 INFO L78 Accepts]: Start accepts. Automaton has 89 states. Word has length 2589 [2018-11-18 15:32:24,573 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:32:24,575 INFO L225 Difference]: With dead ends: 2616 [2018-11-18 15:32:24,576 INFO L226 Difference]: Without dead ends: 2610 [2018-11-18 15:32:24,577 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2703 GetRequests, 2560 SyntacticMatches, 0 SemanticMatches, 143 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6797 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=4501, Invalid=16379, Unknown=0, NotChecked=0, Total=20880 [2018-11-18 15:32:24,578 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2610 states. [2018-11-18 15:32:24,587 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2610 to 2605. [2018-11-18 15:32:24,587 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2605 states. [2018-11-18 15:32:24,590 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2605 states to 2605 states and 2607 transitions. [2018-11-18 15:32:24,590 INFO L78 Accepts]: Start accepts. Automaton has 2605 states and 2607 transitions. Word has length 2589 [2018-11-18 15:32:24,591 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:32:24,591 INFO L480 AbstractCegarLoop]: Abstraction has 2605 states and 2607 transitions. [2018-11-18 15:32:24,591 INFO L481 AbstractCegarLoop]: Interpolant automaton has 89 states. [2018-11-18 15:32:24,591 INFO L276 IsEmpty]: Start isEmpty. Operand 2605 states and 2607 transitions. [2018-11-18 15:32:24,619 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2596 [2018-11-18 15:32:24,619 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:32:24,620 INFO L375 BasicCegarLoop]: trace histogram [402, 377, 377, 376, 376, 376, 26, 26, 26, 26, 25, 25, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:32:24,620 INFO L423 AbstractCegarLoop]: === Iteration 73 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:32:24,620 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:32:24,620 INFO L82 PathProgramCache]: Analyzing trace with hash 637277257, now seen corresponding path program 60 times [2018-11-18 15:32:24,621 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:32:24,621 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:32:24,621 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:32:24,621 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:32:24,621 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:32:24,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:32:27,880 INFO L134 CoverageAnalysis]: Checked inductivity of 447354 backedges. 57375 proven. 2054 refuted. 0 times theorem prover too weak. 387925 trivial. 0 not checked. [2018-11-18 15:32:27,881 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:32:27,881 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:32:27,888 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-18 15:32:36,643 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 53 check-sat command(s) [2018-11-18 15:32:36,643 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:32:36,681 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:32:36,682 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 15:32:36,685 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 15:32:36,696 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 15:32:36,697 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 15:32:36,702 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 15:32:36,710 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 15:32:36,710 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 15:32:44,122 INFO L134 CoverageAnalysis]: Checked inductivity of 447354 backedges. 57375 proven. 2054 refuted. 0 times theorem prover too weak. 387925 trivial. 0 not checked. [2018-11-18 15:32:44,147 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:32:44,148 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 32] total 33 [2018-11-18 15:32:44,148 INFO L459 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-11-18 15:32:44,148 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-11-18 15:32:44,148 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=476, Invalid=646, Unknown=0, NotChecked=0, Total=1122 [2018-11-18 15:32:44,149 INFO L87 Difference]: Start difference. First operand 2605 states and 2607 transitions. Second operand 34 states. [2018-11-18 15:32:44,882 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:32:44,882 INFO L93 Difference]: Finished difference Result 2619 states and 2622 transitions. [2018-11-18 15:32:44,882 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-11-18 15:32:44,882 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 2595 [2018-11-18 15:32:44,883 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:32:44,885 INFO L225 Difference]: With dead ends: 2619 [2018-11-18 15:32:44,885 INFO L226 Difference]: Without dead ends: 2619 [2018-11-18 15:32:44,885 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2652 GetRequests, 2541 SyntacticMatches, 52 SemanticMatches, 59 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 558 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=1341, Invalid=2319, Unknown=0, NotChecked=0, Total=3660 [2018-11-18 15:32:44,886 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2619 states. [2018-11-18 15:32:44,894 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2619 to 2611. [2018-11-18 15:32:44,894 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2611 states. [2018-11-18 15:32:44,896 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2611 states to 2611 states and 2614 transitions. [2018-11-18 15:32:44,896 INFO L78 Accepts]: Start accepts. Automaton has 2611 states and 2614 transitions. Word has length 2595 [2018-11-18 15:32:44,896 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:32:44,896 INFO L480 AbstractCegarLoop]: Abstraction has 2611 states and 2614 transitions. [2018-11-18 15:32:44,897 INFO L481 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-11-18 15:32:44,897 INFO L276 IsEmpty]: Start isEmpty. Operand 2611 states and 2614 transitions. [2018-11-18 15:32:44,919 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2602 [2018-11-18 15:32:44,919 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:32:44,919 INFO L375 BasicCegarLoop]: trace histogram [403, 378, 378, 377, 377, 377, 26, 26, 26, 26, 25, 25, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:32:44,919 INFO L423 AbstractCegarLoop]: === Iteration 74 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:32:44,919 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:32:44,919 INFO L82 PathProgramCache]: Analyzing trace with hash 2139654481, now seen corresponding path program 61 times [2018-11-18 15:32:44,919 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:32:44,919 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:32:44,920 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:32:44,920 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:32:44,920 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:32:45,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:32:47,688 INFO L134 CoverageAnalysis]: Checked inductivity of 449664 backedges. 61659 proven. 2255 refuted. 0 times theorem prover too weak. 385750 trivial. 0 not checked. [2018-11-18 15:32:47,688 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:32:47,688 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:32:47,694 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:32:48,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:32:48,062 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:32:50,792 INFO L134 CoverageAnalysis]: Checked inductivity of 449664 backedges. 61739 proven. 2175 refuted. 0 times theorem prover too weak. 385750 trivial. 0 not checked. [2018-11-18 15:32:50,813 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:32:50,813 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 57] total 87 [2018-11-18 15:32:50,814 INFO L459 AbstractCegarLoop]: Interpolant automaton has 87 states [2018-11-18 15:32:50,814 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 87 interpolants. [2018-11-18 15:32:50,815 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1712, Invalid=5770, Unknown=0, NotChecked=0, Total=7482 [2018-11-18 15:32:50,815 INFO L87 Difference]: Start difference. First operand 2611 states and 2614 transitions. Second operand 87 states. [2018-11-18 15:32:52,578 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:32:52,578 INFO L93 Difference]: Finished difference Result 2796 states and 2800 transitions. [2018-11-18 15:32:52,578 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 83 states. [2018-11-18 15:32:52,578 INFO L78 Accepts]: Start accepts. Automaton has 87 states. Word has length 2601 [2018-11-18 15:32:52,580 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:32:52,584 INFO L225 Difference]: With dead ends: 2796 [2018-11-18 15:32:52,584 INFO L226 Difference]: Without dead ends: 2796 [2018-11-18 15:32:52,585 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2711 GetRequests, 2573 SyntacticMatches, 0 SemanticMatches, 138 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3314 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=4889, Invalid=14571, Unknown=0, NotChecked=0, Total=19460 [2018-11-18 15:32:52,587 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2796 states. [2018-11-18 15:32:52,597 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2796 to 2786. [2018-11-18 15:32:52,598 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2786 states. [2018-11-18 15:32:52,601 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2786 states to 2786 states and 2790 transitions. [2018-11-18 15:32:52,601 INFO L78 Accepts]: Start accepts. Automaton has 2786 states and 2790 transitions. Word has length 2601 [2018-11-18 15:32:52,602 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:32:52,602 INFO L480 AbstractCegarLoop]: Abstraction has 2786 states and 2790 transitions. [2018-11-18 15:32:52,602 INFO L481 AbstractCegarLoop]: Interpolant automaton has 87 states. [2018-11-18 15:32:52,603 INFO L276 IsEmpty]: Start isEmpty. Operand 2786 states and 2790 transitions. [2018-11-18 15:32:52,634 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2771 [2018-11-18 15:32:52,634 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:32:52,635 INFO L375 BasicCegarLoop]: trace histogram [430, 404, 404, 403, 403, 403, 27, 27, 27, 27, 26, 26, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:32:52,635 INFO L423 AbstractCegarLoop]: === Iteration 75 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:32:52,635 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:32:52,635 INFO L82 PathProgramCache]: Analyzing trace with hash 1771553446, now seen corresponding path program 62 times [2018-11-18 15:32:52,636 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:32:52,636 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:32:52,636 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:32:52,636 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:32:52,636 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:32:52,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:32:56,151 INFO L134 CoverageAnalysis]: Checked inductivity of 512967 backedges. 171143 proven. 6393 refuted. 0 times theorem prover too weak. 335431 trivial. 0 not checked. [2018-11-18 15:32:56,151 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:32:56,151 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:32:56,157 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-18 15:32:56,534 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 15:32:56,534 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:32:56,553 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:32:59,852 INFO L134 CoverageAnalysis]: Checked inductivity of 512967 backedges. 122976 proven. 2002 refuted. 0 times theorem prover too weak. 387989 trivial. 0 not checked. [2018-11-18 15:32:59,872 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:32:59,873 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 56] total 111 [2018-11-18 15:32:59,874 INFO L459 AbstractCegarLoop]: Interpolant automaton has 111 states [2018-11-18 15:32:59,875 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 111 interpolants. [2018-11-18 15:32:59,875 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1975, Invalid=10235, Unknown=0, NotChecked=0, Total=12210 [2018-11-18 15:32:59,875 INFO L87 Difference]: Start difference. First operand 2786 states and 2790 transitions. Second operand 111 states. [2018-11-18 15:33:03,455 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:33:03,456 INFO L93 Difference]: Finished difference Result 2797 states and 2799 transitions. [2018-11-18 15:33:03,456 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 108 states. [2018-11-18 15:33:03,456 INFO L78 Accepts]: Start accepts. Automaton has 111 states. Word has length 2770 [2018-11-18 15:33:03,457 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:33:03,460 INFO L225 Difference]: With dead ends: 2797 [2018-11-18 15:33:03,460 INFO L226 Difference]: Without dead ends: 2791 [2018-11-18 15:33:03,462 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2909 GetRequests, 2721 SyntacticMatches, 0 SemanticMatches, 188 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12278 ImplicationChecksByTransitivity, 2.9s TimeCoverageRelationStatistics Valid=5609, Invalid=30301, Unknown=0, NotChecked=0, Total=35910 [2018-11-18 15:33:03,464 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2791 states. [2018-11-18 15:33:03,472 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2791 to 2786. [2018-11-18 15:33:03,473 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2786 states. [2018-11-18 15:33:03,475 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2786 states to 2786 states and 2788 transitions. [2018-11-18 15:33:03,475 INFO L78 Accepts]: Start accepts. Automaton has 2786 states and 2788 transitions. Word has length 2770 [2018-11-18 15:33:03,476 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:33:03,476 INFO L480 AbstractCegarLoop]: Abstraction has 2786 states and 2788 transitions. [2018-11-18 15:33:03,476 INFO L481 AbstractCegarLoop]: Interpolant automaton has 111 states. [2018-11-18 15:33:03,477 INFO L276 IsEmpty]: Start isEmpty. Operand 2786 states and 2788 transitions. [2018-11-18 15:33:03,503 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2777 [2018-11-18 15:33:03,503 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:33:03,503 INFO L375 BasicCegarLoop]: trace histogram [431, 405, 405, 404, 404, 404, 27, 27, 27, 27, 26, 26, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:33:03,503 INFO L423 AbstractCegarLoop]: === Iteration 76 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:33:03,504 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:33:03,504 INFO L82 PathProgramCache]: Analyzing trace with hash 155466910, now seen corresponding path program 63 times [2018-11-18 15:33:03,504 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:33:03,504 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:33:03,505 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:33:03,505 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:33:03,505 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:33:03,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:33:07,114 INFO L134 CoverageAnalysis]: Checked inductivity of 515441 backedges. 64064 proven. 2214 refuted. 0 times theorem prover too weak. 449163 trivial. 0 not checked. [2018-11-18 15:33:07,115 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:33:07,115 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:33:07,123 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 15:33:08,979 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 28 check-sat command(s) [2018-11-18 15:33:08,979 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:33:08,998 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:33:09,004 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 15:33:09,006 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 15:33:09,010 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 15:33:09,010 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 15:33:09,016 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 15:33:09,022 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 15:33:09,022 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 15:33:17,610 INFO L134 CoverageAnalysis]: Checked inductivity of 515441 backedges. 64064 proven. 2214 refuted. 0 times theorem prover too weak. 449163 trivial. 0 not checked. [2018-11-18 15:33:17,632 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:33:17,632 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 33] total 34 [2018-11-18 15:33:17,633 INFO L459 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-11-18 15:33:17,633 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-11-18 15:33:17,633 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=507, Invalid=683, Unknown=0, NotChecked=0, Total=1190 [2018-11-18 15:33:17,633 INFO L87 Difference]: Start difference. First operand 2786 states and 2788 transitions. Second operand 35 states. [2018-11-18 15:33:18,379 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:33:18,379 INFO L93 Difference]: Finished difference Result 2800 states and 2803 transitions. [2018-11-18 15:33:18,380 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-11-18 15:33:18,380 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 2776 [2018-11-18 15:33:18,381 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:33:18,384 INFO L225 Difference]: With dead ends: 2800 [2018-11-18 15:33:18,384 INFO L226 Difference]: Without dead ends: 2800 [2018-11-18 15:33:18,384 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2835 GetRequests, 2720 SyntacticMatches, 54 SemanticMatches, 61 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 593 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=1432, Invalid=2474, Unknown=0, NotChecked=0, Total=3906 [2018-11-18 15:33:18,385 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2800 states. [2018-11-18 15:33:18,394 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2800 to 2792. [2018-11-18 15:33:18,394 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2792 states. [2018-11-18 15:33:18,397 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2792 states to 2792 states and 2795 transitions. [2018-11-18 15:33:18,397 INFO L78 Accepts]: Start accepts. Automaton has 2792 states and 2795 transitions. Word has length 2776 [2018-11-18 15:33:18,398 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:33:18,398 INFO L480 AbstractCegarLoop]: Abstraction has 2792 states and 2795 transitions. [2018-11-18 15:33:18,398 INFO L481 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-11-18 15:33:18,398 INFO L276 IsEmpty]: Start isEmpty. Operand 2792 states and 2795 transitions. [2018-11-18 15:33:18,424 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2783 [2018-11-18 15:33:18,424 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:33:18,425 INFO L375 BasicCegarLoop]: trace histogram [432, 406, 406, 405, 405, 405, 27, 27, 27, 27, 26, 26, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:33:18,425 INFO L423 AbstractCegarLoop]: === Iteration 77 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:33:18,425 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:33:18,425 INFO L82 PathProgramCache]: Analyzing trace with hash 1451515366, now seen corresponding path program 64 times [2018-11-18 15:33:18,425 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:33:18,425 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:33:18,426 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:33:18,426 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:33:18,426 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:33:18,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:33:21,557 INFO L134 CoverageAnalysis]: Checked inductivity of 517921 backedges. 68675 proven. 2436 refuted. 0 times theorem prover too weak. 446810 trivial. 0 not checked. [2018-11-18 15:33:21,557 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:33:21,557 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:33:21,564 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 15:33:21,913 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 15:33:21,913 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:33:21,936 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:33:25,242 INFO L134 CoverageAnalysis]: Checked inductivity of 517921 backedges. 68438 proven. 8158 refuted. 0 times theorem prover too weak. 441325 trivial. 0 not checked. [2018-11-18 15:33:25,262 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:33:25,262 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 63] total 94 [2018-11-18 15:33:25,263 INFO L459 AbstractCegarLoop]: Interpolant automaton has 94 states [2018-11-18 15:33:25,263 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 94 interpolants. [2018-11-18 15:33:25,263 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1843, Invalid=6899, Unknown=0, NotChecked=0, Total=8742 [2018-11-18 15:33:25,264 INFO L87 Difference]: Start difference. First operand 2792 states and 2795 transitions. Second operand 94 states. [2018-11-18 15:33:26,998 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:33:26,999 INFO L93 Difference]: Finished difference Result 2983 states and 2987 transitions. [2018-11-18 15:33:26,999 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 92 states. [2018-11-18 15:33:26,999 INFO L78 Accepts]: Start accepts. Automaton has 94 states. Word has length 2782 [2018-11-18 15:33:27,000 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:33:27,003 INFO L225 Difference]: With dead ends: 2983 [2018-11-18 15:33:27,003 INFO L226 Difference]: Without dead ends: 2983 [2018-11-18 15:33:27,004 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2898 GetRequests, 2749 SyntacticMatches, 0 SemanticMatches, 149 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4223 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=5149, Invalid=17501, Unknown=0, NotChecked=0, Total=22650 [2018-11-18 15:33:27,005 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2983 states. [2018-11-18 15:33:27,016 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2983 to 2973. [2018-11-18 15:33:27,016 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2973 states. [2018-11-18 15:33:27,018 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2973 states to 2973 states and 2977 transitions. [2018-11-18 15:33:27,019 INFO L78 Accepts]: Start accepts. Automaton has 2973 states and 2977 transitions. Word has length 2782 [2018-11-18 15:33:27,019 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:33:27,020 INFO L480 AbstractCegarLoop]: Abstraction has 2973 states and 2977 transitions. [2018-11-18 15:33:27,020 INFO L481 AbstractCegarLoop]: Interpolant automaton has 94 states. [2018-11-18 15:33:27,020 INFO L276 IsEmpty]: Start isEmpty. Operand 2973 states and 2977 transitions. [2018-11-18 15:33:27,054 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2958 [2018-11-18 15:33:27,054 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:33:27,054 INFO L375 BasicCegarLoop]: trace histogram [460, 433, 433, 432, 432, 432, 28, 28, 28, 28, 27, 27, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:33:27,054 INFO L423 AbstractCegarLoop]: === Iteration 78 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:33:27,055 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:33:27,055 INFO L82 PathProgramCache]: Analyzing trace with hash -1078497095, now seen corresponding path program 65 times [2018-11-18 15:33:27,055 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:33:27,055 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:33:27,055 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:33:27,055 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:33:27,055 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:33:27,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:33:30,802 INFO L134 CoverageAnalysis]: Checked inductivity of 588357 backedges. 136483 proven. 10434 refuted. 0 times theorem prover too weak. 441440 trivial. 0 not checked. [2018-11-18 15:33:30,803 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:33:30,803 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:33:30,809 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-18 15:33:47,903 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 62 check-sat command(s) [2018-11-18 15:33:47,903 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:33:47,948 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:33:51,201 INFO L134 CoverageAnalysis]: Checked inductivity of 588357 backedges. 136433 proven. 12762 refuted. 0 times theorem prover too weak. 439162 trivial. 0 not checked. [2018-11-18 15:33:51,230 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:33:51,230 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 62] total 95 [2018-11-18 15:33:51,231 INFO L459 AbstractCegarLoop]: Interpolant automaton has 95 states [2018-11-18 15:33:51,231 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 95 interpolants. [2018-11-18 15:33:51,231 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1724, Invalid=7206, Unknown=0, NotChecked=0, Total=8930 [2018-11-18 15:33:51,231 INFO L87 Difference]: Start difference. First operand 2973 states and 2977 transitions. Second operand 95 states. [2018-11-18 15:33:53,368 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:33:53,368 INFO L93 Difference]: Finished difference Result 2984 states and 2986 transitions. [2018-11-18 15:33:53,368 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 89 states. [2018-11-18 15:33:53,368 INFO L78 Accepts]: Start accepts. Automaton has 95 states. Word has length 2957 [2018-11-18 15:33:53,369 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:33:53,372 INFO L225 Difference]: With dead ends: 2984 [2018-11-18 15:33:53,372 INFO L226 Difference]: Without dead ends: 2978 [2018-11-18 15:33:53,373 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3079 GetRequests, 2926 SyntacticMatches, 0 SemanticMatches, 153 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7852 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=5150, Invalid=18720, Unknown=0, NotChecked=0, Total=23870 [2018-11-18 15:33:53,374 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2978 states. [2018-11-18 15:33:53,385 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2978 to 2973. [2018-11-18 15:33:53,385 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2973 states. [2018-11-18 15:33:53,387 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2973 states to 2973 states and 2975 transitions. [2018-11-18 15:33:53,387 INFO L78 Accepts]: Start accepts. Automaton has 2973 states and 2975 transitions. Word has length 2957 [2018-11-18 15:33:53,388 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:33:53,388 INFO L480 AbstractCegarLoop]: Abstraction has 2973 states and 2975 transitions. [2018-11-18 15:33:53,388 INFO L481 AbstractCegarLoop]: Interpolant automaton has 95 states. [2018-11-18 15:33:53,388 INFO L276 IsEmpty]: Start isEmpty. Operand 2973 states and 2975 transitions. [2018-11-18 15:33:53,419 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2964 [2018-11-18 15:33:53,420 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:33:53,420 INFO L375 BasicCegarLoop]: trace histogram [461, 434, 434, 433, 433, 433, 28, 28, 28, 28, 27, 27, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:33:53,420 INFO L423 AbstractCegarLoop]: === Iteration 79 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:33:53,420 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:33:53,420 INFO L82 PathProgramCache]: Analyzing trace with hash 303172721, now seen corresponding path program 66 times [2018-11-18 15:33:53,420 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:33:53,420 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:33:53,421 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:33:53,421 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:33:53,421 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:33:53,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:33:57,391 INFO L134 CoverageAnalysis]: Checked inductivity of 591007 backedges. 71253 proven. 2380 refuted. 0 times theorem prover too weak. 517374 trivial. 0 not checked. [2018-11-18 15:33:57,391 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:33:57,391 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 73 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 73 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:33:57,398 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-18 15:34:20,239 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 57 check-sat command(s) [2018-11-18 15:34:20,239 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:34:20,275 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:34:20,277 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 15:34:20,279 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 15:34:20,283 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 15:34:20,283 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 15:34:20,288 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 15:34:20,294 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 15:34:20,294 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 15:34:29,558 INFO L134 CoverageAnalysis]: Checked inductivity of 591007 backedges. 71253 proven. 2380 refuted. 0 times theorem prover too weak. 517374 trivial. 0 not checked. [2018-11-18 15:34:29,582 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:34:29,583 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 34] total 35 [2018-11-18 15:34:29,583 INFO L459 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-11-18 15:34:29,584 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-11-18 15:34:29,584 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=539, Invalid=721, Unknown=0, NotChecked=0, Total=1260 [2018-11-18 15:34:29,584 INFO L87 Difference]: Start difference. First operand 2973 states and 2975 transitions. Second operand 36 states. [2018-11-18 15:34:30,370 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:34:30,370 INFO L93 Difference]: Finished difference Result 2987 states and 2990 transitions. [2018-11-18 15:34:30,371 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-11-18 15:34:30,371 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 2963 [2018-11-18 15:34:30,372 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:34:30,374 INFO L225 Difference]: With dead ends: 2987 [2018-11-18 15:34:30,374 INFO L226 Difference]: Without dead ends: 2987 [2018-11-18 15:34:30,375 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3024 GetRequests, 2905 SyntacticMatches, 56 SemanticMatches, 63 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 629 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=1526, Invalid=2634, Unknown=0, NotChecked=0, Total=4160 [2018-11-18 15:34:30,376 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2987 states. [2018-11-18 15:34:30,391 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2987 to 2979. [2018-11-18 15:34:30,391 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2979 states. [2018-11-18 15:34:30,393 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2979 states to 2979 states and 2982 transitions. [2018-11-18 15:34:30,393 INFO L78 Accepts]: Start accepts. Automaton has 2979 states and 2982 transitions. Word has length 2963 [2018-11-18 15:34:30,394 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:34:30,394 INFO L480 AbstractCegarLoop]: Abstraction has 2979 states and 2982 transitions. [2018-11-18 15:34:30,394 INFO L481 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-11-18 15:34:30,394 INFO L276 IsEmpty]: Start isEmpty. Operand 2979 states and 2982 transitions. [2018-11-18 15:34:30,428 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2970 [2018-11-18 15:34:30,428 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:34:30,428 INFO L375 BasicCegarLoop]: trace histogram [462, 435, 435, 434, 434, 434, 28, 28, 28, 28, 27, 27, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:34:30,428 INFO L423 AbstractCegarLoop]: === Iteration 80 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:34:30,428 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:34:30,428 INFO L82 PathProgramCache]: Analyzing trace with hash -1791114375, now seen corresponding path program 67 times [2018-11-18 15:34:30,429 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:34:30,429 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:34:30,429 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:34:30,429 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:34:30,429 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:34:30,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:34:34,060 INFO L134 CoverageAnalysis]: Checked inductivity of 593663 backedges. 76203 proven. 2624 refuted. 0 times theorem prover too weak. 514836 trivial. 0 not checked. [2018-11-18 15:34:34,060 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:34:34,060 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:34:34,070 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:34:34,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:34:34,498 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:34:37,979 INFO L134 CoverageAnalysis]: Checked inductivity of 593663 backedges. 76289 proven. 2538 refuted. 0 times theorem prover too weak. 514836 trivial. 0 not checked. [2018-11-18 15:34:37,997 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:34:37,997 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 61] total 93 [2018-11-18 15:34:37,998 INFO L459 AbstractCegarLoop]: Interpolant automaton has 93 states [2018-11-18 15:34:37,998 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 93 interpolants. [2018-11-18 15:34:37,998 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1954, Invalid=6602, Unknown=0, NotChecked=0, Total=8556 [2018-11-18 15:34:37,998 INFO L87 Difference]: Start difference. First operand 2979 states and 2982 transitions. Second operand 93 states. [2018-11-18 15:34:40,122 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:34:40,123 INFO L93 Difference]: Finished difference Result 3176 states and 3180 transitions. [2018-11-18 15:34:40,123 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 89 states. [2018-11-18 15:34:40,123 INFO L78 Accepts]: Start accepts. Automaton has 93 states. Word has length 2969 [2018-11-18 15:34:40,124 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:34:40,127 INFO L225 Difference]: With dead ends: 3176 [2018-11-18 15:34:40,127 INFO L226 Difference]: Without dead ends: 3176 [2018-11-18 15:34:40,128 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3087 GetRequests, 2939 SyntacticMatches, 0 SemanticMatches, 148 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3821 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=5599, Invalid=16751, Unknown=0, NotChecked=0, Total=22350 [2018-11-18 15:34:40,129 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3176 states. [2018-11-18 15:34:40,141 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3176 to 3166. [2018-11-18 15:34:40,141 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3166 states. [2018-11-18 15:34:40,143 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3166 states to 3166 states and 3170 transitions. [2018-11-18 15:34:40,143 INFO L78 Accepts]: Start accepts. Automaton has 3166 states and 3170 transitions. Word has length 2969 [2018-11-18 15:34:40,144 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:34:40,144 INFO L480 AbstractCegarLoop]: Abstraction has 3166 states and 3170 transitions. [2018-11-18 15:34:40,144 INFO L481 AbstractCegarLoop]: Interpolant automaton has 93 states. [2018-11-18 15:34:40,144 INFO L276 IsEmpty]: Start isEmpty. Operand 3166 states and 3170 transitions. [2018-11-18 15:34:40,182 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3151 [2018-11-18 15:34:40,182 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:34:40,183 INFO L375 BasicCegarLoop]: trace histogram [491, 463, 463, 462, 462, 462, 29, 29, 29, 29, 28, 28, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:34:40,183 INFO L423 AbstractCegarLoop]: === Iteration 81 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:34:40,183 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:34:40,183 INFO L82 PathProgramCache]: Analyzing trace with hash 370962958, now seen corresponding path program 68 times [2018-11-18 15:34:40,183 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:34:40,183 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:34:40,184 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:34:40,184 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:34:40,184 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:34:40,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:34:44,479 INFO L134 CoverageAnalysis]: Checked inductivity of 671748 backedges. 212591 proven. 7389 refuted. 0 times theorem prover too weak. 451768 trivial. 0 not checked. [2018-11-18 15:34:44,479 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:34:44,479 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 75 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 75 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:34:44,485 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-18 15:34:44,938 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 15:34:44,939 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:34:44,961 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:34:49,100 INFO L134 CoverageAnalysis]: Checked inductivity of 671748 backedges. 152009 proven. 2324 refuted. 0 times theorem prover too weak. 517415 trivial. 0 not checked. [2018-11-18 15:34:49,121 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:34:49,122 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 60] total 119 [2018-11-18 15:34:49,123 INFO L459 AbstractCegarLoop]: Interpolant automaton has 119 states [2018-11-18 15:34:49,123 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 119 interpolants. [2018-11-18 15:34:49,123 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2266, Invalid=11776, Unknown=0, NotChecked=0, Total=14042 [2018-11-18 15:34:49,124 INFO L87 Difference]: Start difference. First operand 3166 states and 3170 transitions. Second operand 119 states. [2018-11-18 15:34:53,344 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:34:53,344 INFO L93 Difference]: Finished difference Result 3177 states and 3179 transitions. [2018-11-18 15:34:53,344 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 116 states. [2018-11-18 15:34:53,344 INFO L78 Accepts]: Start accepts. Automaton has 119 states. Word has length 3150 [2018-11-18 15:34:53,346 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:34:53,348 INFO L225 Difference]: With dead ends: 3177 [2018-11-18 15:34:53,349 INFO L226 Difference]: Without dead ends: 3171 [2018-11-18 15:34:53,350 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3299 GetRequests, 3097 SyntacticMatches, 0 SemanticMatches, 202 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14259 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=6431, Invalid=34981, Unknown=0, NotChecked=0, Total=41412 [2018-11-18 15:34:53,351 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3171 states. [2018-11-18 15:34:53,360 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3171 to 3166. [2018-11-18 15:34:53,361 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3166 states. [2018-11-18 15:34:53,363 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3166 states to 3166 states and 3168 transitions. [2018-11-18 15:34:53,363 INFO L78 Accepts]: Start accepts. Automaton has 3166 states and 3168 transitions. Word has length 3150 [2018-11-18 15:34:53,365 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:34:53,365 INFO L480 AbstractCegarLoop]: Abstraction has 3166 states and 3168 transitions. [2018-11-18 15:34:53,365 INFO L481 AbstractCegarLoop]: Interpolant automaton has 119 states. [2018-11-18 15:34:53,365 INFO L276 IsEmpty]: Start isEmpty. Operand 3166 states and 3168 transitions. [2018-11-18 15:34:53,398 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3157 [2018-11-18 15:34:53,398 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:34:53,399 INFO L375 BasicCegarLoop]: trace histogram [492, 464, 464, 463, 463, 463, 29, 29, 29, 29, 28, 28, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:34:53,399 INFO L423 AbstractCegarLoop]: === Iteration 82 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:34:53,399 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:34:53,399 INFO L82 PathProgramCache]: Analyzing trace with hash 475608582, now seen corresponding path program 69 times [2018-11-18 15:34:53,400 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:34:53,400 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:34:53,400 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:34:53,400 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:34:53,400 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:34:53,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:34:57,967 INFO L134 CoverageAnalysis]: Checked inductivity of 674580 backedges. 78960 proven. 2552 refuted. 0 times theorem prover too weak. 593068 trivial. 0 not checked. [2018-11-18 15:34:57,968 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:34:57,968 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:34:57,975 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 15:35:03,058 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 30 check-sat command(s) [2018-11-18 15:35:03,058 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:35:03,079 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:35:03,080 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 15:35:03,085 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 15:35:03,096 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 15:35:03,097 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 15:35:03,102 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 15:35:03,108 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 15:35:03,109 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 15:35:14,002 INFO L134 CoverageAnalysis]: Checked inductivity of 674580 backedges. 78960 proven. 2552 refuted. 0 times theorem prover too weak. 593068 trivial. 0 not checked. [2018-11-18 15:35:14,025 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:35:14,026 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 35] total 36 [2018-11-18 15:35:14,027 INFO L459 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-11-18 15:35:14,027 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-11-18 15:35:14,027 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=572, Invalid=760, Unknown=0, NotChecked=0, Total=1332 [2018-11-18 15:35:14,028 INFO L87 Difference]: Start difference. First operand 3166 states and 3168 transitions. Second operand 37 states. [2018-11-18 15:35:14,970 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:35:14,970 INFO L93 Difference]: Finished difference Result 3180 states and 3183 transitions. [2018-11-18 15:35:14,971 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-11-18 15:35:14,971 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 3156 [2018-11-18 15:35:14,972 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:35:14,975 INFO L225 Difference]: With dead ends: 3180 [2018-11-18 15:35:14,975 INFO L226 Difference]: Without dead ends: 3180 [2018-11-18 15:35:14,975 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3219 GetRequests, 3096 SyntacticMatches, 58 SemanticMatches, 65 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 666 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=1623, Invalid=2799, Unknown=0, NotChecked=0, Total=4422 [2018-11-18 15:35:14,976 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3180 states. [2018-11-18 15:35:14,995 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3180 to 3172. [2018-11-18 15:35:14,995 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3172 states. [2018-11-18 15:35:14,999 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3172 states to 3172 states and 3175 transitions. [2018-11-18 15:35:14,999 INFO L78 Accepts]: Start accepts. Automaton has 3172 states and 3175 transitions. Word has length 3156 [2018-11-18 15:35:15,000 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:35:15,000 INFO L480 AbstractCegarLoop]: Abstraction has 3172 states and 3175 transitions. [2018-11-18 15:35:15,000 INFO L481 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-11-18 15:35:15,000 INFO L276 IsEmpty]: Start isEmpty. Operand 3172 states and 3175 transitions. [2018-11-18 15:35:15,039 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3163 [2018-11-18 15:35:15,039 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:35:15,039 INFO L375 BasicCegarLoop]: trace histogram [493, 465, 465, 464, 464, 464, 29, 29, 29, 29, 28, 28, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:35:15,040 INFO L423 AbstractCegarLoop]: === Iteration 83 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:35:15,040 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:35:15,040 INFO L82 PathProgramCache]: Analyzing trace with hash 935504206, now seen corresponding path program 70 times [2018-11-18 15:35:15,040 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:35:15,040 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:35:15,041 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:35:15,041 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:35:15,041 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:35:15,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:35:18,870 INFO L134 CoverageAnalysis]: Checked inductivity of 677418 backedges. 84261 proven. 2819 refuted. 0 times theorem prover too weak. 590338 trivial. 0 not checked. [2018-11-18 15:35:18,871 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:35:18,871 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 77 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 77 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:35:18,877 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 15:35:19,256 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 15:35:19,256 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:35:19,279 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:35:23,331 INFO L134 CoverageAnalysis]: Checked inductivity of 677418 backedges. 84008 proven. 9373 refuted. 0 times theorem prover too weak. 584037 trivial. 0 not checked. [2018-11-18 15:35:23,349 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:35:23,349 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 67] total 100 [2018-11-18 15:35:23,350 INFO L459 AbstractCegarLoop]: Interpolant automaton has 100 states [2018-11-18 15:35:23,350 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 100 interpolants. [2018-11-18 15:35:23,351 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2093, Invalid=7807, Unknown=0, NotChecked=0, Total=9900 [2018-11-18 15:35:23,351 INFO L87 Difference]: Start difference. First operand 3172 states and 3175 transitions. Second operand 100 states. [2018-11-18 15:35:25,684 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:35:25,685 INFO L93 Difference]: Finished difference Result 3375 states and 3379 transitions. [2018-11-18 15:35:25,685 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 98 states. [2018-11-18 15:35:25,685 INFO L78 Accepts]: Start accepts. Automaton has 100 states. Word has length 3162 [2018-11-18 15:35:25,686 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:35:25,688 INFO L225 Difference]: With dead ends: 3375 [2018-11-18 15:35:25,688 INFO L226 Difference]: Without dead ends: 3375 [2018-11-18 15:35:25,689 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3286 GetRequests, 3127 SyntacticMatches, 0 SemanticMatches, 159 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4796 ImplicationChecksByTransitivity, 2.9s TimeCoverageRelationStatistics Valid=5873, Invalid=19887, Unknown=0, NotChecked=0, Total=25760 [2018-11-18 15:35:25,691 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3375 states. [2018-11-18 15:35:25,701 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3375 to 3365. [2018-11-18 15:35:25,701 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3365 states. [2018-11-18 15:35:25,704 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3365 states to 3365 states and 3369 transitions. [2018-11-18 15:35:25,704 INFO L78 Accepts]: Start accepts. Automaton has 3365 states and 3369 transitions. Word has length 3162 [2018-11-18 15:35:25,706 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:35:25,706 INFO L480 AbstractCegarLoop]: Abstraction has 3365 states and 3369 transitions. [2018-11-18 15:35:25,706 INFO L481 AbstractCegarLoop]: Interpolant automaton has 100 states. [2018-11-18 15:35:25,706 INFO L276 IsEmpty]: Start isEmpty. Operand 3365 states and 3369 transitions. [2018-11-18 15:35:25,743 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3350 [2018-11-18 15:35:25,743 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:35:25,743 INFO L375 BasicCegarLoop]: trace histogram [523, 494, 494, 493, 493, 493, 30, 30, 30, 30, 29, 29, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:35:25,744 INFO L423 AbstractCegarLoop]: === Iteration 84 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:35:25,744 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:35:25,744 INFO L82 PathProgramCache]: Analyzing trace with hash -426819487, now seen corresponding path program 71 times [2018-11-18 15:35:25,744 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:35:25,744 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:35:25,745 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:35:25,745 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:35:25,745 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:35:25,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:35:30,254 INFO L134 CoverageAnalysis]: Checked inductivity of 763686 backedges. 167558 proven. 11970 refuted. 0 times theorem prover too weak. 584158 trivial. 0 not checked. [2018-11-18 15:35:30,254 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:35:30,254 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:35:30,260 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-18 15:36:09,063 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 70 check-sat command(s) [2018-11-18 15:36:09,063 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:36:09,132 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:36:13,333 INFO L134 CoverageAnalysis]: Checked inductivity of 763686 backedges. 167496 proven. 14656 refuted. 0 times theorem prover too weak. 581534 trivial. 0 not checked. [2018-11-18 15:36:13,373 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:36:13,373 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [66, 66] total 101 [2018-11-18 15:36:13,374 INFO L459 AbstractCegarLoop]: Interpolant automaton has 101 states [2018-11-18 15:36:13,374 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 101 interpolants. [2018-11-18 15:36:13,375 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1964, Invalid=8136, Unknown=0, NotChecked=0, Total=10100 [2018-11-18 15:36:13,375 INFO L87 Difference]: Start difference. First operand 3365 states and 3369 transitions. Second operand 101 states. [2018-11-18 15:36:15,322 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:36:15,322 INFO L93 Difference]: Finished difference Result 3376 states and 3378 transitions. [2018-11-18 15:36:15,322 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 95 states. [2018-11-18 15:36:15,322 INFO L78 Accepts]: Start accepts. Automaton has 101 states. Word has length 3349 [2018-11-18 15:36:15,324 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:36:15,326 INFO L225 Difference]: With dead ends: 3376 [2018-11-18 15:36:15,326 INFO L226 Difference]: Without dead ends: 3370 [2018-11-18 15:36:15,327 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3479 GetRequests, 3316 SyntacticMatches, 0 SemanticMatches, 163 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8983 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=5843, Invalid=21217, Unknown=0, NotChecked=0, Total=27060 [2018-11-18 15:36:15,329 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3370 states. [2018-11-18 15:36:15,339 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3370 to 3365. [2018-11-18 15:36:15,339 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3365 states. [2018-11-18 15:36:15,341 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3365 states to 3365 states and 3367 transitions. [2018-11-18 15:36:15,342 INFO L78 Accepts]: Start accepts. Automaton has 3365 states and 3367 transitions. Word has length 3349 [2018-11-18 15:36:15,343 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:36:15,343 INFO L480 AbstractCegarLoop]: Abstraction has 3365 states and 3367 transitions. [2018-11-18 15:36:15,343 INFO L481 AbstractCegarLoop]: Interpolant automaton has 101 states. [2018-11-18 15:36:15,343 INFO L276 IsEmpty]: Start isEmpty. Operand 3365 states and 3367 transitions. [2018-11-18 15:36:15,384 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3356 [2018-11-18 15:36:15,384 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:36:15,385 INFO L375 BasicCegarLoop]: trace histogram [524, 495, 495, 494, 494, 494, 30, 30, 30, 30, 29, 29, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:36:15,385 INFO L423 AbstractCegarLoop]: === Iteration 85 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:36:15,385 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:36:15,385 INFO L82 PathProgramCache]: Analyzing trace with hash -1061751271, now seen corresponding path program 72 times [2018-11-18 15:36:15,385 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:36:15,385 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:36:15,386 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:36:15,386 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:36:15,386 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:36:15,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:36:20,411 INFO L134 CoverageAnalysis]: Checked inductivity of 766706 backedges. 87203 proven. 2730 refuted. 0 times theorem prover too weak. 676773 trivial. 0 not checked. [2018-11-18 15:36:20,411 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:36:20,411 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 79 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 79 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:36:20,421 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-18 15:36:48,479 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 59 check-sat command(s) [2018-11-18 15:36:48,479 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:36:48,534 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:36:48,549 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 15:36:48,560 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 15:36:48,566 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 15:36:48,566 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 15:36:48,573 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 15:36:48,580 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 15:36:48,580 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:13, output treesize:24 [2018-11-18 15:37:03,325 INFO L134 CoverageAnalysis]: Checked inductivity of 766706 backedges. 161453 proven. 21227 refuted. 0 times theorem prover too weak. 584026 trivial. 0 not checked. [2018-11-18 15:37:03,352 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:37:03,353 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 45] total 76 [2018-11-18 15:37:03,354 INFO L459 AbstractCegarLoop]: Interpolant automaton has 77 states [2018-11-18 15:37:03,355 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 77 interpolants. [2018-11-18 15:37:03,355 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1111, Invalid=4741, Unknown=0, NotChecked=0, Total=5852 [2018-11-18 15:37:03,355 INFO L87 Difference]: Start difference. First operand 3365 states and 3367 transitions. Second operand 77 states. [2018-11-18 15:37:07,337 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:37:07,337 INFO L93 Difference]: Finished difference Result 3591 states and 3598 transitions. [2018-11-18 15:37:07,338 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 107 states. [2018-11-18 15:37:07,338 INFO L78 Accepts]: Start accepts. Automaton has 77 states. Word has length 3355 [2018-11-18 15:37:07,339 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:37:07,342 INFO L225 Difference]: With dead ends: 3591 [2018-11-18 15:37:07,342 INFO L226 Difference]: Without dead ends: 3591 [2018-11-18 15:37:07,343 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3465 GetRequests, 3258 SyntacticMatches, 58 SemanticMatches, 149 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8762 ImplicationChecksByTransitivity, 5.8s TimeCoverageRelationStatistics Valid=5022, Invalid=17628, Unknown=0, NotChecked=0, Total=22650 [2018-11-18 15:37:07,345 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3591 states. [2018-11-18 15:37:07,359 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3591 to 3573. [2018-11-18 15:37:07,360 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3573 states. [2018-11-18 15:37:07,364 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3573 states to 3573 states and 3579 transitions. [2018-11-18 15:37:07,364 INFO L78 Accepts]: Start accepts. Automaton has 3573 states and 3579 transitions. Word has length 3355 [2018-11-18 15:37:07,366 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:37:07,366 INFO L480 AbstractCegarLoop]: Abstraction has 3573 states and 3579 transitions. [2018-11-18 15:37:07,366 INFO L481 AbstractCegarLoop]: Interpolant automaton has 77 states. [2018-11-18 15:37:07,366 INFO L276 IsEmpty]: Start isEmpty. Operand 3573 states and 3579 transitions. [2018-11-18 15:37:07,443 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3555 [2018-11-18 15:37:07,443 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:37:07,443 INFO L375 BasicCegarLoop]: trace histogram [556, 526, 526, 525, 525, 525, 31, 31, 31, 31, 30, 30, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:37:07,444 INFO L423 AbstractCegarLoop]: === Iteration 86 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:37:07,444 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:37:07,444 INFO L82 PathProgramCache]: Analyzing trace with hash 2067800054, now seen corresponding path program 73 times [2018-11-18 15:37:07,444 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:37:07,445 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:37:07,445 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:37:07,445 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:37:07,445 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:37:07,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:37:13,026 INFO L134 CoverageAnalysis]: Checked inductivity of 864735 backedges. 260239 proven. 8457 refuted. 0 times theorem prover too weak. 596039 trivial. 0 not checked. [2018-11-18 15:37:13,026 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:37:13,026 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:37:13,035 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:37:13,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:37:13,639 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:37:18,748 INFO L134 CoverageAnalysis]: Checked inductivity of 864735 backedges. 185278 proven. 2670 refuted. 0 times theorem prover too weak. 676787 trivial. 0 not checked. [2018-11-18 15:37:18,767 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:37:18,767 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 64] total 127 [2018-11-18 15:37:18,768 INFO L459 AbstractCegarLoop]: Interpolant automaton has 127 states [2018-11-18 15:37:18,768 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 127 interpolants. [2018-11-18 15:37:18,769 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2577, Invalid=13425, Unknown=0, NotChecked=0, Total=16002 [2018-11-18 15:37:18,769 INFO L87 Difference]: Start difference. First operand 3573 states and 3579 transitions. Second operand 127 states. [2018-11-18 15:37:23,597 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:37:23,597 INFO L93 Difference]: Finished difference Result 3582 states and 3586 transitions. [2018-11-18 15:37:23,597 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 124 states. [2018-11-18 15:37:23,597 INFO L78 Accepts]: Start accepts. Automaton has 127 states. Word has length 3554 [2018-11-18 15:37:23,598 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:37:23,601 INFO L225 Difference]: With dead ends: 3582 [2018-11-18 15:37:23,601 INFO L226 Difference]: Without dead ends: 3579 [2018-11-18 15:37:23,603 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3713 GetRequests, 3497 SyntacticMatches, 0 SemanticMatches, 216 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16388 ImplicationChecksByTransitivity, 3.6s TimeCoverageRelationStatistics Valid=7309, Invalid=39997, Unknown=0, NotChecked=0, Total=47306 [2018-11-18 15:37:23,604 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3579 states. [2018-11-18 15:37:23,619 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3579 to 3570. [2018-11-18 15:37:23,619 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3570 states. [2018-11-18 15:37:23,621 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3570 states to 3570 states and 3573 transitions. [2018-11-18 15:37:23,621 INFO L78 Accepts]: Start accepts. Automaton has 3570 states and 3573 transitions. Word has length 3554 [2018-11-18 15:37:23,622 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:37:23,623 INFO L480 AbstractCegarLoop]: Abstraction has 3570 states and 3573 transitions. [2018-11-18 15:37:23,623 INFO L481 AbstractCegarLoop]: Interpolant automaton has 127 states. [2018-11-18 15:37:23,623 INFO L276 IsEmpty]: Start isEmpty. Operand 3570 states and 3573 transitions. [2018-11-18 15:37:23,662 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3561 [2018-11-18 15:37:23,662 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:37:23,662 INFO L375 BasicCegarLoop]: trace histogram [557, 527, 527, 526, 526, 526, 31, 31, 31, 31, 30, 30, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:37:23,662 INFO L423 AbstractCegarLoop]: === Iteration 87 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:37:23,662 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:37:23,663 INFO L82 PathProgramCache]: Analyzing trace with hash -1275048466, now seen corresponding path program 74 times [2018-11-18 15:37:23,663 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:37:23,663 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:37:23,663 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:37:23,663 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:37:23,663 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:37:23,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:37:29,449 INFO L134 CoverageAnalysis]: Checked inductivity of 867949 backedges. 96000 proven. 2914 refuted. 0 times theorem prover too weak. 769035 trivial. 0 not checked. [2018-11-18 15:37:29,449 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:37:29,449 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 81 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 81 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:37:29,459 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-18 15:37:30,018 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 15:37:30,019 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:37:30,051 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:37:30,053 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 15:37:30,088 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 15:37:30,102 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 15 [2018-11-18 15:37:30,102 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-11-18 15:37:30,113 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-11-18 15:37:30,121 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-11-18 15:37:30,121 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:16, output treesize:30 [2018-11-18 15:37:45,937 INFO L134 CoverageAnalysis]: Checked inductivity of 867949 backedges. 96000 proven. 3197 refuted. 0 times theorem prover too weak. 768752 trivial. 0 not checked. [2018-11-18 15:37:45,959 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:37:45,960 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 37] total 70 [2018-11-18 15:37:45,962 INFO L459 AbstractCegarLoop]: Interpolant automaton has 71 states [2018-11-18 15:37:45,962 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 71 interpolants. [2018-11-18 15:37:45,962 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1202, Invalid=3768, Unknown=0, NotChecked=0, Total=4970 [2018-11-18 15:37:45,962 INFO L87 Difference]: Start difference. First operand 3570 states and 3573 transitions. Second operand 71 states. [2018-11-18 15:37:48,448 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:37:48,448 INFO L93 Difference]: Finished difference Result 3807 states and 3814 transitions. [2018-11-18 15:37:48,448 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 103 states. [2018-11-18 15:37:48,448 INFO L78 Accepts]: Start accepts. Automaton has 71 states. Word has length 3560 [2018-11-18 15:37:48,450 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:37:48,453 INFO L225 Difference]: With dead ends: 3807 [2018-11-18 15:37:48,453 INFO L226 Difference]: Without dead ends: 3807 [2018-11-18 15:37:48,454 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3662 GetRequests, 3466 SyntacticMatches, 60 SemanticMatches, 136 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7667 ImplicationChecksByTransitivity, 4.6s TimeCoverageRelationStatistics Valid=4280, Invalid=14626, Unknown=0, NotChecked=0, Total=18906 [2018-11-18 15:37:48,455 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3807 states. [2018-11-18 15:37:48,468 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3807 to 3775. [2018-11-18 15:37:48,469 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3775 states. [2018-11-18 15:37:48,471 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3775 states to 3775 states and 3780 transitions. [2018-11-18 15:37:48,471 INFO L78 Accepts]: Start accepts. Automaton has 3775 states and 3780 transitions. Word has length 3560 [2018-11-18 15:37:48,473 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:37:48,473 INFO L480 AbstractCegarLoop]: Abstraction has 3775 states and 3780 transitions. [2018-11-18 15:37:48,473 INFO L481 AbstractCegarLoop]: Interpolant automaton has 71 states. [2018-11-18 15:37:48,473 INFO L276 IsEmpty]: Start isEmpty. Operand 3775 states and 3780 transitions. [2018-11-18 15:37:48,526 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3766 [2018-11-18 15:37:48,526 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:37:48,526 INFO L375 BasicCegarLoop]: trace histogram [590, 559, 559, 558, 558, 558, 32, 32, 32, 32, 31, 31, 31, 31, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:37:48,526 INFO L423 AbstractCegarLoop]: === Iteration 88 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:37:48,527 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:37:48,527 INFO L82 PathProgramCache]: Analyzing trace with hash 1642832265, now seen corresponding path program 75 times [2018-11-18 15:37:48,527 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:37:48,527 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:37:48,527 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:37:48,528 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:37:48,528 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:37:48,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:37:54,419 INFO L134 CoverageAnalysis]: Checked inductivity of 975477 backedges. 203013 proven. 13610 refuted. 0 times theorem prover too weak. 758854 trivial. 0 not checked. [2018-11-18 15:37:54,419 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:37:54,419 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/z3 Starting monitored process 82 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 82 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:37:54,449 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 15:38:01,682 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 33 check-sat command(s) [2018-11-18 15:38:01,682 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:38:01,706 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:38:08,061 INFO L134 CoverageAnalysis]: Checked inductivity of 975477 backedges. 197480 proven. 8932 refuted. 0 times theorem prover too weak. 769065 trivial. 0 not checked. [2018-11-18 15:38:08,086 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:38:08,087 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [70, 71] total 138 [2018-11-18 15:38:08,088 INFO L459 AbstractCegarLoop]: Interpolant automaton has 138 states [2018-11-18 15:38:08,089 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 138 interpolants. [2018-11-18 15:38:08,090 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2792, Invalid=16114, Unknown=0, NotChecked=0, Total=18906 [2018-11-18 15:38:08,090 INFO L87 Difference]: Start difference. First operand 3775 states and 3780 transitions. Second operand 138 states. [2018-11-18 15:38:14,913 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:38:14,914 INFO L93 Difference]: Finished difference Result 4017 states and 4021 transitions. [2018-11-18 15:38:14,914 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 169 states. [2018-11-18 15:38:14,914 INFO L78 Accepts]: Start accepts. Automaton has 138 states. Word has length 3765 [2018-11-18 15:38:14,916 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:38:14,919 INFO L225 Difference]: With dead ends: 4017 [2018-11-18 15:38:14,919 INFO L226 Difference]: Without dead ends: 4008 [2018-11-18 15:38:14,924 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3996 GetRequests, 3699 SyntacticMatches, 0 SemanticMatches, 297 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32113 ImplicationChecksByTransitivity, 6.3s TimeCoverageRelationStatistics Valid=11925, Invalid=77177, Unknown=0, NotChecked=0, Total=89102 [2018-11-18 15:38:14,925 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4008 states. [2018-11-18 15:38:14,938 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4008 to 3995. [2018-11-18 15:38:14,938 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3995 states. [2018-11-18 15:38:14,941 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3995 states to 3995 states and 3999 transitions. [2018-11-18 15:38:14,941 INFO L78 Accepts]: Start accepts. Automaton has 3995 states and 3999 transitions. Word has length 3765 [2018-11-18 15:38:14,943 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:38:14,943 INFO L480 AbstractCegarLoop]: Abstraction has 3995 states and 3999 transitions. [2018-11-18 15:38:14,943 INFO L481 AbstractCegarLoop]: Interpolant automaton has 138 states. [2018-11-18 15:38:14,943 INFO L276 IsEmpty]: Start isEmpty. Operand 3995 states and 3999 transitions. [2018-11-18 15:38:14,988 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3772 [2018-11-18 15:38:14,988 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:38:14,988 INFO L375 BasicCegarLoop]: trace histogram [591, 560, 560, 559, 559, 559, 32, 32, 32, 32, 31, 31, 31, 31, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:38:14,988 INFO L423 AbstractCegarLoop]: === Iteration 89 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr1REQUIRES_VIOLATION, mainErr0REQUIRES_VIOLATION]=== [2018-11-18 15:38:14,988 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:38:14,989 INFO L82 PathProgramCache]: Analyzing trace with hash -350662335, now seen corresponding path program 76 times [2018-11-18 15:38:14,989 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:38:14,989 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:38:14,989 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:38:14,990 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:38:14,990 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:38:15,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:38:16,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:38:17,635 INFO L442 BasicCegarLoop]: Counterexample might be feasible [2018-11-18 15:38:18,086 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 18.11 03:38:18 BoogieIcfgContainer [2018-11-18 15:38:18,086 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-18 15:38:18,087 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-18 15:38:18,087 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-18 15:38:18,087 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-18 15:38:18,087 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 03:28:00" (3/4) ... [2018-11-18 15:38:18,090 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-11-18 15:38:18,534 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_0a0d66cf-1c1f-46a6-8dce-70497b80c277/bin-2019/uautomizer/witness.graphml [2018-11-18 15:38:18,534 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-18 15:38:18,535 INFO L168 Benchmark]: Toolchain (without parser) took 618730.91 ms. Allocated memory was 1.0 GB in the beginning and 5.1 GB in the end (delta: 4.1 GB). Free memory was 958.2 MB in the beginning and 3.5 GB in the end (delta: -2.6 GB). Peak memory consumption was 1.5 GB. Max. memory is 11.5 GB. [2018-11-18 15:38:18,536 INFO L168 Benchmark]: CDTParser took 0.10 ms. Allocated memory is still 1.0 GB. Free memory is still 985.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 15:38:18,537 INFO L168 Benchmark]: CACSL2BoogieTranslator took 147.59 ms. Allocated memory is still 1.0 GB. Free memory was 958.2 MB in the beginning and 947.2 MB in the end (delta: 10.9 MB). Peak memory consumption was 10.9 MB. Max. memory is 11.5 GB. [2018-11-18 15:38:18,537 INFO L168 Benchmark]: Boogie Preprocessor took 29.83 ms. Allocated memory is still 1.0 GB. Free memory was 947.2 MB in the beginning and 944.6 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-11-18 15:38:18,537 INFO L168 Benchmark]: RCFGBuilder took 264.76 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 127.4 MB). Free memory was 944.6 MB in the beginning and 1.1 GB in the end (delta: -163.2 MB). Peak memory consumption was 14.5 MB. Max. memory is 11.5 GB. [2018-11-18 15:38:18,538 INFO L168 Benchmark]: TraceAbstraction took 617838.14 ms. Allocated memory was 1.2 GB in the beginning and 5.1 GB in the end (delta: 3.9 GB). Free memory was 1.1 GB in the beginning and 3.6 GB in the end (delta: -2.5 GB). Peak memory consumption was 1.4 GB. Max. memory is 11.5 GB. [2018-11-18 15:38:18,538 INFO L168 Benchmark]: Witness Printer took 447.79 ms. Allocated memory is still 5.1 GB. Free memory was 3.6 GB in the beginning and 3.5 GB in the end (delta: 82.7 MB). Peak memory consumption was 82.7 MB. Max. memory is 11.5 GB. [2018-11-18 15:38:18,540 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.10 ms. Allocated memory is still 1.0 GB. Free memory is still 985.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 147.59 ms. Allocated memory is still 1.0 GB. Free memory was 958.2 MB in the beginning and 947.2 MB in the end (delta: 10.9 MB). Peak memory consumption was 10.9 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 29.83 ms. Allocated memory is still 1.0 GB. Free memory was 947.2 MB in the beginning and 944.6 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 264.76 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 127.4 MB). Free memory was 944.6 MB in the beginning and 1.1 GB in the end (delta: -163.2 MB). Peak memory consumption was 14.5 MB. Max. memory is 11.5 GB. * TraceAbstraction took 617838.14 ms. Allocated memory was 1.2 GB in the beginning and 5.1 GB in the end (delta: 3.9 GB). Free memory was 1.1 GB in the beginning and 3.6 GB in the end (delta: -2.5 GB). Peak memory consumption was 1.4 GB. Max. memory is 11.5 GB. * Witness Printer took 447.79 ms. Allocated memory is still 5.1 GB. Free memory was 3.6 GB in the beginning and 3.5 GB in the end (delta: 82.7 MB). Peak memory consumption was 82.7 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 18]: pointer dereference may fail pointer dereference may fail We found a FailurePath: [L24] int i, b[32]; [L25] FCALL char mask[32]; [L26] i = 0 VAL [b={159:0}, i=0, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=0, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=0, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=0, b={143:0}, b={143:0}, i=0, size=0] [L17] COND TRUE i <= size + 1 VAL [\old(size)=0, b={143:0}, b={143:0}, i=0, size=0] [L18] EXPR a[i] VAL [\old(size)=0, b={143:0}, b={143:0}, i=0, size=0] [L18] EXPR, FCALL b[i] VAL [\old(size)=0, b={143:0}, b={143:0}, b[i]=160, i=0, size=0] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=0, b={143:0}, b={143:0}, i=1, size=0] [L17] COND TRUE i <= size + 1 VAL [\old(size)=0, b={143:0}, b={143:0}, i=1, size=0] [L18] EXPR a[i] VAL [\old(size)=0, b={143:0}, b={143:0}, i=1, size=0] [L18] EXPR, FCALL b[i] VAL [\old(size)=0, b={143:0}, b={143:0}, b[i]=131, i=1, size=0] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=0, b={143:0}, b={143:0}, i=2, size=0] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=0, b={143:0}, b={143:0}, i=2, size=0] [L20] RET return i; VAL [\old(size)=0, \result=2, b={143:0}, b={143:0}, i=2, size=0] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=2, i=0, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=2, i=0, mask={143:0}] [L26] i++ VAL [b={159:0}, i=1, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=1, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=1, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=1, b={143:0}, b={143:0}, i=0, size=1] [L17] COND TRUE i <= size + 1 VAL [\old(size)=1, b={143:0}, b={143:0}, i=0, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={143:0}, b={143:0}, i=0, size=1] [L18] EXPR, FCALL b[i] VAL [\old(size)=1, b={143:0}, b={143:0}, b[i]=160, i=0, size=1] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=1, b={143:0}, b={143:0}, i=1, size=1] [L17] COND TRUE i <= size + 1 VAL [\old(size)=1, b={143:0}, b={143:0}, i=1, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={143:0}, b={143:0}, i=1, size=1] [L18] EXPR, FCALL b[i] VAL [\old(size)=1, b={143:0}, b={143:0}, b[i]=131, i=1, size=1] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=1, b={143:0}, b={143:0}, i=2, size=1] [L17] COND TRUE i <= size + 1 VAL [\old(size)=1, b={143:0}, b={143:0}, i=2, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={143:0}, b={143:0}, i=2, size=1] [L18] EXPR, FCALL b[i] VAL [\old(size)=1, b={143:0}, b={143:0}, b[i]=133, i=2, size=1] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=1, b={143:0}, b={143:0}, i=3, size=1] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=1, b={143:0}, b={143:0}, i=3, size=1] [L20] RET return i; VAL [\old(size)=1, \result=3, b={143:0}, b={143:0}, i=3, size=1] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=3, i=1, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=3, i=1, mask={143:0}] [L26] i++ VAL [b={159:0}, i=2, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=2, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=2, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=2, b={143:0}, b={143:0}, i=0, size=2] [L17] COND TRUE i <= size + 1 VAL [\old(size)=2, b={143:0}, b={143:0}, i=0, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={143:0}, b={143:0}, i=0, size=2] [L18] EXPR, FCALL b[i] VAL [\old(size)=2, b={143:0}, b={143:0}, b[i]=160, i=0, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={143:0}, b={143:0}, i=1, size=2] [L17] COND TRUE i <= size + 1 VAL [\old(size)=2, b={143:0}, b={143:0}, i=1, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={143:0}, b={143:0}, i=1, size=2] [L18] EXPR, FCALL b[i] VAL [\old(size)=2, b={143:0}, b={143:0}, b[i]=131, i=1, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={143:0}, b={143:0}, i=2, size=2] [L17] COND TRUE i <= size + 1 VAL [\old(size)=2, b={143:0}, b={143:0}, i=2, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={143:0}, b={143:0}, i=2, size=2] [L18] EXPR, FCALL b[i] VAL [\old(size)=2, b={143:0}, b={143:0}, b[i]=133, i=2, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={143:0}, b={143:0}, i=3, size=2] [L17] COND TRUE i <= size + 1 VAL [\old(size)=2, b={143:0}, b={143:0}, i=3, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={143:0}, b={143:0}, i=3, size=2] [L18] EXPR, FCALL b[i] VAL [\old(size)=2, b={143:0}, b={143:0}, b[i]=135, i=3, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={143:0}, b={143:0}, i=4, size=2] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=2, b={143:0}, b={143:0}, i=4, size=2] [L20] RET return i; VAL [\old(size)=2, \result=4, b={143:0}, b={143:0}, i=4, size=2] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=4, i=2, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=4, i=2, mask={143:0}] [L26] i++ VAL [b={159:0}, i=3, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=3, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=3, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=3, b={143:0}, b={143:0}, i=0, size=3] [L17] COND TRUE i <= size + 1 VAL [\old(size)=3, b={143:0}, b={143:0}, i=0, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={143:0}, b={143:0}, i=0, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={143:0}, b={143:0}, b[i]=160, i=0, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={143:0}, b={143:0}, i=1, size=3] [L17] COND TRUE i <= size + 1 VAL [\old(size)=3, b={143:0}, b={143:0}, i=1, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={143:0}, b={143:0}, i=1, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={143:0}, b={143:0}, b[i]=131, i=1, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={143:0}, b={143:0}, i=2, size=3] [L17] COND TRUE i <= size + 1 VAL [\old(size)=3, b={143:0}, b={143:0}, i=2, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={143:0}, b={143:0}, i=2, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={143:0}, b={143:0}, b[i]=133, i=2, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={143:0}, b={143:0}, i=3, size=3] [L17] COND TRUE i <= size + 1 VAL [\old(size)=3, b={143:0}, b={143:0}, i=3, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={143:0}, b={143:0}, i=3, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={143:0}, b={143:0}, b[i]=135, i=3, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={143:0}, b={143:0}, i=4, size=3] [L17] COND TRUE i <= size + 1 VAL [\old(size)=3, b={143:0}, b={143:0}, i=4, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={143:0}, b={143:0}, i=4, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={143:0}, b={143:0}, b[i]=151, i=4, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={143:0}, b={143:0}, i=5, size=3] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=3, b={143:0}, b={143:0}, i=5, size=3] [L20] RET return i; VAL [\old(size)=3, \result=5, b={143:0}, b={143:0}, i=5, size=3] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=5, i=3, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=5, i=3, mask={143:0}] [L26] i++ VAL [b={159:0}, i=4, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=4, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=4, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=4, b={143:0}, b={143:0}, i=0, size=4] [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={143:0}, b={143:0}, i=0, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={143:0}, b={143:0}, i=0, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={143:0}, b={143:0}, b[i]=160, i=0, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={143:0}, b={143:0}, i=1, size=4] [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={143:0}, b={143:0}, i=1, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={143:0}, b={143:0}, i=1, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={143:0}, b={143:0}, b[i]=131, i=1, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={143:0}, b={143:0}, i=2, size=4] [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={143:0}, b={143:0}, i=2, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={143:0}, b={143:0}, i=2, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={143:0}, b={143:0}, b[i]=133, i=2, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={143:0}, b={143:0}, i=3, size=4] [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={143:0}, b={143:0}, i=3, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={143:0}, b={143:0}, i=3, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={143:0}, b={143:0}, b[i]=135, i=3, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={143:0}, b={143:0}, i=4, size=4] [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={143:0}, b={143:0}, i=4, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={143:0}, b={143:0}, i=4, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={143:0}, b={143:0}, b[i]=151, i=4, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={143:0}, b={143:0}, i=5, size=4] [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={143:0}, b={143:0}, i=5, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={143:0}, b={143:0}, i=5, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={143:0}, b={143:0}, b[i]=137, i=5, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={143:0}, b={143:0}, i=6, size=4] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=4, b={143:0}, b={143:0}, i=6, size=4] [L20] RET return i; VAL [\old(size)=4, \result=6, b={143:0}, b={143:0}, i=6, size=4] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=6, i=4, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=6, i=4, mask={143:0}] [L26] i++ VAL [b={159:0}, i=5, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=5, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=5, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=5, b={143:0}, b={143:0}, i=0, size=5] [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={143:0}, b={143:0}, i=0, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={143:0}, b={143:0}, i=0, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={143:0}, b={143:0}, b[i]=160, i=0, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={143:0}, b={143:0}, i=1, size=5] [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={143:0}, b={143:0}, i=1, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={143:0}, b={143:0}, i=1, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={143:0}, b={143:0}, b[i]=131, i=1, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={143:0}, b={143:0}, i=2, size=5] [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={143:0}, b={143:0}, i=2, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={143:0}, b={143:0}, i=2, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={143:0}, b={143:0}, b[i]=133, i=2, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={143:0}, b={143:0}, i=3, size=5] [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={143:0}, b={143:0}, i=3, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={143:0}, b={143:0}, i=3, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={143:0}, b={143:0}, b[i]=135, i=3, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={143:0}, b={143:0}, i=4, size=5] [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={143:0}, b={143:0}, i=4, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={143:0}, b={143:0}, i=4, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={143:0}, b={143:0}, b[i]=151, i=4, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={143:0}, b={143:0}, i=5, size=5] [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={143:0}, b={143:0}, i=5, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={143:0}, b={143:0}, i=5, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={143:0}, b={143:0}, b[i]=137, i=5, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={143:0}, b={143:0}, i=6, size=5] [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={143:0}, b={143:0}, i=6, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={143:0}, b={143:0}, i=6, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={143:0}, b={143:0}, b[i]=136, i=6, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={143:0}, b={143:0}, i=7, size=5] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=5, b={143:0}, b={143:0}, i=7, size=5] [L20] RET return i; VAL [\old(size)=5, \result=7, b={143:0}, b={143:0}, i=7, size=5] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=7, i=5, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=7, i=5, mask={143:0}] [L26] i++ VAL [b={159:0}, i=6, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=6, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=6, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=6, b={143:0}, b={143:0}, i=0, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={143:0}, b={143:0}, i=0, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={143:0}, b={143:0}, i=0, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={143:0}, b={143:0}, b[i]=160, i=0, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={143:0}, b={143:0}, i=1, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={143:0}, b={143:0}, i=1, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={143:0}, b={143:0}, i=1, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={143:0}, b={143:0}, b[i]=131, i=1, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={143:0}, b={143:0}, i=2, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={143:0}, b={143:0}, i=2, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={143:0}, b={143:0}, i=2, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={143:0}, b={143:0}, b[i]=133, i=2, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={143:0}, b={143:0}, i=3, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={143:0}, b={143:0}, i=3, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={143:0}, b={143:0}, i=3, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={143:0}, b={143:0}, b[i]=135, i=3, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={143:0}, b={143:0}, i=4, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={143:0}, b={143:0}, i=4, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={143:0}, b={143:0}, i=4, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={143:0}, b={143:0}, b[i]=151, i=4, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={143:0}, b={143:0}, i=5, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={143:0}, b={143:0}, i=5, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={143:0}, b={143:0}, i=5, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={143:0}, b={143:0}, b[i]=137, i=5, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={143:0}, b={143:0}, i=6, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={143:0}, b={143:0}, i=6, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={143:0}, b={143:0}, i=6, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={143:0}, b={143:0}, b[i]=136, i=6, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={143:0}, b={143:0}, i=7, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={143:0}, b={143:0}, i=7, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={143:0}, b={143:0}, i=7, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={143:0}, b={143:0}, b[i]=154, i=7, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={143:0}, b={143:0}, i=8, size=6] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=6, b={143:0}, b={143:0}, i=8, size=6] [L20] RET return i; VAL [\old(size)=6, \result=8, b={143:0}, b={143:0}, i=8, size=6] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=8, i=6, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=8, i=6, mask={143:0}] [L26] i++ VAL [b={159:0}, i=7, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=7, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=7, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=7, b={143:0}, b={143:0}, i=0, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={143:0}, b={143:0}, i=0, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={143:0}, b={143:0}, i=0, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={143:0}, b={143:0}, b[i]=160, i=0, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={143:0}, b={143:0}, i=1, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={143:0}, b={143:0}, i=1, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={143:0}, b={143:0}, i=1, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={143:0}, b={143:0}, b[i]=131, i=1, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={143:0}, b={143:0}, i=2, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={143:0}, b={143:0}, i=2, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={143:0}, b={143:0}, i=2, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={143:0}, b={143:0}, b[i]=133, i=2, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={143:0}, b={143:0}, i=3, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={143:0}, b={143:0}, i=3, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={143:0}, b={143:0}, i=3, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={143:0}, b={143:0}, b[i]=135, i=3, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={143:0}, b={143:0}, i=4, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={143:0}, b={143:0}, i=4, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={143:0}, b={143:0}, i=4, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={143:0}, b={143:0}, b[i]=151, i=4, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={143:0}, b={143:0}, i=5, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={143:0}, b={143:0}, i=5, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={143:0}, b={143:0}, i=5, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={143:0}, b={143:0}, b[i]=137, i=5, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={143:0}, b={143:0}, i=6, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={143:0}, b={143:0}, i=6, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={143:0}, b={143:0}, i=6, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={143:0}, b={143:0}, b[i]=136, i=6, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={143:0}, b={143:0}, i=7, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={143:0}, b={143:0}, i=7, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={143:0}, b={143:0}, i=7, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={143:0}, b={143:0}, b[i]=154, i=7, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={143:0}, b={143:0}, i=8, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={143:0}, b={143:0}, i=8, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={143:0}, b={143:0}, i=8, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={143:0}, b={143:0}, b[i]=132, i=8, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={143:0}, b={143:0}, i=9, size=7] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=7, b={143:0}, b={143:0}, i=9, size=7] [L20] RET return i; VAL [\old(size)=7, \result=9, b={143:0}, b={143:0}, i=9, size=7] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=9, i=7, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=9, i=7, mask={143:0}] [L26] i++ VAL [b={159:0}, i=8, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=8, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=8, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=8, b={143:0}, b={143:0}, i=0, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={143:0}, b={143:0}, i=0, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={143:0}, b={143:0}, i=0, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={143:0}, b={143:0}, b[i]=160, i=0, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={143:0}, b={143:0}, i=1, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={143:0}, b={143:0}, i=1, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={143:0}, b={143:0}, i=1, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={143:0}, b={143:0}, b[i]=131, i=1, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={143:0}, b={143:0}, i=2, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={143:0}, b={143:0}, i=2, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={143:0}, b={143:0}, i=2, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={143:0}, b={143:0}, b[i]=133, i=2, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={143:0}, b={143:0}, i=3, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={143:0}, b={143:0}, i=3, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={143:0}, b={143:0}, i=3, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={143:0}, b={143:0}, b[i]=135, i=3, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={143:0}, b={143:0}, i=4, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={143:0}, b={143:0}, i=4, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={143:0}, b={143:0}, i=4, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={143:0}, b={143:0}, b[i]=151, i=4, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={143:0}, b={143:0}, i=5, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={143:0}, b={143:0}, i=5, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={143:0}, b={143:0}, i=5, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={143:0}, b={143:0}, b[i]=137, i=5, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={143:0}, b={143:0}, i=6, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={143:0}, b={143:0}, i=6, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={143:0}, b={143:0}, i=6, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={143:0}, b={143:0}, b[i]=136, i=6, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={143:0}, b={143:0}, i=7, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={143:0}, b={143:0}, i=7, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={143:0}, b={143:0}, i=7, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={143:0}, b={143:0}, b[i]=154, i=7, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={143:0}, b={143:0}, i=8, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={143:0}, b={143:0}, i=8, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={143:0}, b={143:0}, i=8, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={143:0}, b={143:0}, b[i]=132, i=8, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={143:0}, b={143:0}, i=9, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={143:0}, b={143:0}, i=9, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={143:0}, b={143:0}, i=9, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={143:0}, b={143:0}, b[i]=138, i=9, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={143:0}, b={143:0}, i=10, size=8] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=8, b={143:0}, b={143:0}, i=10, size=8] [L20] RET return i; VAL [\old(size)=8, \result=10, b={143:0}, b={143:0}, i=10, size=8] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=10, i=8, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=10, i=8, mask={143:0}] [L26] i++ VAL [b={159:0}, i=9, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=9, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=9, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=9, b={143:0}, b={143:0}, i=0, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={143:0}, b={143:0}, i=0, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=0, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=160, i=0, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=1, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={143:0}, b={143:0}, i=1, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=1, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=131, i=1, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=2, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={143:0}, b={143:0}, i=2, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=2, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=133, i=2, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=3, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={143:0}, b={143:0}, i=3, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=3, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=135, i=3, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=4, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={143:0}, b={143:0}, i=4, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=4, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=151, i=4, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=5, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={143:0}, b={143:0}, i=5, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=5, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=137, i=5, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=6, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={143:0}, b={143:0}, i=6, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=6, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=136, i=6, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=7, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={143:0}, b={143:0}, i=7, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=7, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=154, i=7, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=8, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={143:0}, b={143:0}, i=8, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=8, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=132, i=8, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=9, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={143:0}, b={143:0}, i=9, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=9, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=138, i=9, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=10, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={143:0}, b={143:0}, i=10, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=10, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=150, i=10, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=11, size=9] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=9, b={143:0}, b={143:0}, i=11, size=9] [L20] RET return i; VAL [\old(size)=9, \result=11, b={143:0}, b={143:0}, i=11, size=9] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=11, i=9, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=11, i=9, mask={143:0}] [L26] i++ VAL [b={159:0}, i=10, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=10, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=10, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=10, b={143:0}, b={143:0}, i=0, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={143:0}, b={143:0}, i=0, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=0, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=160, i=0, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=1, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={143:0}, b={143:0}, i=1, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=1, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=131, i=1, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=2, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={143:0}, b={143:0}, i=2, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=2, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=133, i=2, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=3, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={143:0}, b={143:0}, i=3, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=3, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=135, i=3, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=4, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={143:0}, b={143:0}, i=4, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=4, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=151, i=4, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=5, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={143:0}, b={143:0}, i=5, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=5, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=137, i=5, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=6, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={143:0}, b={143:0}, i=6, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=6, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=136, i=6, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=7, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={143:0}, b={143:0}, i=7, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=7, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=154, i=7, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=8, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={143:0}, b={143:0}, i=8, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=8, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=132, i=8, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=9, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={143:0}, b={143:0}, i=9, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=9, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=138, i=9, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=10, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={143:0}, b={143:0}, i=10, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=10, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=150, i=10, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=11, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={143:0}, b={143:0}, i=11, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=11, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=129, i=11, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=12, size=10] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=10, b={143:0}, b={143:0}, i=12, size=10] [L20] RET return i; VAL [\old(size)=10, \result=12, b={143:0}, b={143:0}, i=12, size=10] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=12, i=10, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=12, i=10, mask={143:0}] [L26] i++ VAL [b={159:0}, i=11, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=11, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=11, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=11, b={143:0}, b={143:0}, i=0, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={143:0}, b={143:0}, i=0, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=0, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=160, i=0, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=1, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={143:0}, b={143:0}, i=1, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=1, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=131, i=1, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=2, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={143:0}, b={143:0}, i=2, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=2, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=133, i=2, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=3, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={143:0}, b={143:0}, i=3, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=3, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=135, i=3, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=4, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={143:0}, b={143:0}, i=4, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=4, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=151, i=4, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=5, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={143:0}, b={143:0}, i=5, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=5, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=137, i=5, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=6, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={143:0}, b={143:0}, i=6, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=6, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=136, i=6, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=7, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={143:0}, b={143:0}, i=7, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=7, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=154, i=7, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=8, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={143:0}, b={143:0}, i=8, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=8, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=132, i=8, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=9, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={143:0}, b={143:0}, i=9, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=9, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=138, i=9, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=10, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={143:0}, b={143:0}, i=10, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=10, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=150, i=10, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=11, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={143:0}, b={143:0}, i=11, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=11, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=129, i=11, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=12, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={143:0}, b={143:0}, i=12, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=12, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=144, i=12, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=13, size=11] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=11, b={143:0}, b={143:0}, i=13, size=11] [L20] RET return i; VAL [\old(size)=11, \result=13, b={143:0}, b={143:0}, i=13, size=11] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=13, i=11, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=13, i=11, mask={143:0}] [L26] i++ VAL [b={159:0}, i=12, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=12, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=12, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=12, b={143:0}, b={143:0}, i=0, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={143:0}, b={143:0}, i=0, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=0, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=160, i=0, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=1, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={143:0}, b={143:0}, i=1, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=1, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=131, i=1, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=2, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={143:0}, b={143:0}, i=2, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=2, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=133, i=2, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=3, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={143:0}, b={143:0}, i=3, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=3, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=135, i=3, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=4, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={143:0}, b={143:0}, i=4, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=4, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=151, i=4, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=5, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={143:0}, b={143:0}, i=5, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=5, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=137, i=5, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=6, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={143:0}, b={143:0}, i=6, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=6, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=136, i=6, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=7, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={143:0}, b={143:0}, i=7, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=7, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=154, i=7, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=8, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={143:0}, b={143:0}, i=8, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=8, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=132, i=8, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=9, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={143:0}, b={143:0}, i=9, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=9, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=138, i=9, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=10, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={143:0}, b={143:0}, i=10, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=10, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=150, i=10, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=11, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={143:0}, b={143:0}, i=11, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=11, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=129, i=11, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=12, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={143:0}, b={143:0}, i=12, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=12, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=144, i=12, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=13, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={143:0}, b={143:0}, i=13, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=13, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=134, i=13, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=14, size=12] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=12, b={143:0}, b={143:0}, i=14, size=12] [L20] RET return i; VAL [\old(size)=12, \result=14, b={143:0}, b={143:0}, i=14, size=12] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=14, i=12, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=14, i=12, mask={143:0}] [L26] i++ VAL [b={159:0}, i=13, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=13, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=13, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=13, b={143:0}, b={143:0}, i=0, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={143:0}, b={143:0}, i=0, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=0, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=160, i=0, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=1, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={143:0}, b={143:0}, i=1, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=1, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=131, i=1, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=2, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={143:0}, b={143:0}, i=2, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=2, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=133, i=2, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=3, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={143:0}, b={143:0}, i=3, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=3, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=135, i=3, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=4, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={143:0}, b={143:0}, i=4, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=4, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=151, i=4, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=5, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={143:0}, b={143:0}, i=5, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=5, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=137, i=5, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=6, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={143:0}, b={143:0}, i=6, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=6, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=136, i=6, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=7, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={143:0}, b={143:0}, i=7, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=7, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=154, i=7, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=8, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={143:0}, b={143:0}, i=8, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=8, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=132, i=8, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=9, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={143:0}, b={143:0}, i=9, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=9, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=138, i=9, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=10, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={143:0}, b={143:0}, i=10, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=10, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=150, i=10, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=11, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={143:0}, b={143:0}, i=11, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=11, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=129, i=11, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=12, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={143:0}, b={143:0}, i=12, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=12, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=144, i=12, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=13, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={143:0}, b={143:0}, i=13, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=13, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=134, i=13, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=14, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={143:0}, b={143:0}, i=14, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=14, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=155, i=14, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=15, size=13] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=13, b={143:0}, b={143:0}, i=15, size=13] [L20] RET return i; VAL [\old(size)=13, \result=15, b={143:0}, b={143:0}, i=15, size=13] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=15, i=13, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=15, i=13, mask={143:0}] [L26] i++ VAL [b={159:0}, i=14, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=14, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=14, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=14, b={143:0}, b={143:0}, i=0, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={143:0}, b={143:0}, i=0, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=0, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=160, i=0, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=1, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={143:0}, b={143:0}, i=1, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=1, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=131, i=1, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=2, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={143:0}, b={143:0}, i=2, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=2, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=133, i=2, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=3, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={143:0}, b={143:0}, i=3, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=3, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=135, i=3, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=4, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={143:0}, b={143:0}, i=4, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=4, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=151, i=4, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=5, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={143:0}, b={143:0}, i=5, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=5, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=137, i=5, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=6, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={143:0}, b={143:0}, i=6, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=6, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=136, i=6, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=7, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={143:0}, b={143:0}, i=7, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=7, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=154, i=7, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=8, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={143:0}, b={143:0}, i=8, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=8, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=132, i=8, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=9, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={143:0}, b={143:0}, i=9, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=9, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=138, i=9, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=10, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={143:0}, b={143:0}, i=10, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=10, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=150, i=10, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=11, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={143:0}, b={143:0}, i=11, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=11, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=129, i=11, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=12, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={143:0}, b={143:0}, i=12, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=12, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=144, i=12, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=13, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={143:0}, b={143:0}, i=13, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=13, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=134, i=13, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=14, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={143:0}, b={143:0}, i=14, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=14, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=155, i=14, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=15, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={143:0}, b={143:0}, i=15, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=15, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=142, i=15, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=16, size=14] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=14, b={143:0}, b={143:0}, i=16, size=14] [L20] RET return i; VAL [\old(size)=14, \result=16, b={143:0}, b={143:0}, i=16, size=14] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=16, i=14, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=16, i=14, mask={143:0}] [L26] i++ VAL [b={159:0}, i=15, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=15, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=15, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=15, b={143:0}, b={143:0}, i=0, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={143:0}, b={143:0}, i=0, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=0, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=160, i=0, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=1, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={143:0}, b={143:0}, i=1, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=1, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=131, i=1, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=2, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={143:0}, b={143:0}, i=2, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=2, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=133, i=2, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=3, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={143:0}, b={143:0}, i=3, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=3, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=135, i=3, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=4, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={143:0}, b={143:0}, i=4, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=4, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=151, i=4, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=5, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={143:0}, b={143:0}, i=5, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=5, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=137, i=5, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=6, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={143:0}, b={143:0}, i=6, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=6, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=136, i=6, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=7, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={143:0}, b={143:0}, i=7, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=7, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=154, i=7, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=8, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={143:0}, b={143:0}, i=8, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=8, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=132, i=8, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=9, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={143:0}, b={143:0}, i=9, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=9, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=138, i=9, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=10, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={143:0}, b={143:0}, i=10, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=10, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=150, i=10, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=11, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={143:0}, b={143:0}, i=11, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=11, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=129, i=11, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=12, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={143:0}, b={143:0}, i=12, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=12, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=144, i=12, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=13, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={143:0}, b={143:0}, i=13, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=13, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=134, i=13, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=14, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={143:0}, b={143:0}, i=14, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=14, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=155, i=14, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=15, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={143:0}, b={143:0}, i=15, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=15, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=142, i=15, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=16, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={143:0}, b={143:0}, i=16, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=16, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=148, i=16, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=17, size=15] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=15, b={143:0}, b={143:0}, i=17, size=15] [L20] RET return i; VAL [\old(size)=15, \result=17, b={143:0}, b={143:0}, i=17, size=15] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=17, i=15, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=17, i=15, mask={143:0}] [L26] i++ VAL [b={159:0}, i=16, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=16, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=16, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=16, b={143:0}, b={143:0}, i=0, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={143:0}, b={143:0}, i=0, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=0, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=160, i=0, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=1, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={143:0}, b={143:0}, i=1, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=1, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=131, i=1, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=2, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={143:0}, b={143:0}, i=2, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=2, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=133, i=2, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=3, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={143:0}, b={143:0}, i=3, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=3, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=135, i=3, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=4, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={143:0}, b={143:0}, i=4, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=4, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=151, i=4, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=5, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={143:0}, b={143:0}, i=5, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=5, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=137, i=5, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=6, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={143:0}, b={143:0}, i=6, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=6, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=136, i=6, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=7, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={143:0}, b={143:0}, i=7, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=7, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=154, i=7, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=8, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={143:0}, b={143:0}, i=8, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=8, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=132, i=8, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=9, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={143:0}, b={143:0}, i=9, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=9, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=138, i=9, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=10, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={143:0}, b={143:0}, i=10, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=10, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=150, i=10, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=11, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={143:0}, b={143:0}, i=11, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=11, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=129, i=11, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=12, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={143:0}, b={143:0}, i=12, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=12, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=144, i=12, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=13, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={143:0}, b={143:0}, i=13, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=13, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=134, i=13, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=14, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={143:0}, b={143:0}, i=14, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=14, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=155, i=14, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=15, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={143:0}, b={143:0}, i=15, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=15, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=142, i=15, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=16, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={143:0}, b={143:0}, i=16, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=16, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=148, i=16, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=17, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={143:0}, b={143:0}, i=17, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=17, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=163, i=17, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=18, size=16] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=16, b={143:0}, b={143:0}, i=18, size=16] [L20] RET return i; VAL [\old(size)=16, \result=18, b={143:0}, b={143:0}, i=18, size=16] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=18, i=16, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=18, i=16, mask={143:0}] [L26] i++ VAL [b={159:0}, i=17, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=17, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=17, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=17, b={143:0}, b={143:0}, i=0, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={143:0}, b={143:0}, i=0, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=0, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=160, i=0, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=1, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={143:0}, b={143:0}, i=1, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=1, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=131, i=1, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=2, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={143:0}, b={143:0}, i=2, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=2, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=133, i=2, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=3, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={143:0}, b={143:0}, i=3, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=3, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=135, i=3, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=4, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={143:0}, b={143:0}, i=4, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=4, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=151, i=4, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=5, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={143:0}, b={143:0}, i=5, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=5, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=137, i=5, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=6, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={143:0}, b={143:0}, i=6, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=6, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=136, i=6, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=7, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={143:0}, b={143:0}, i=7, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=7, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=154, i=7, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=8, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={143:0}, b={143:0}, i=8, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=8, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=132, i=8, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=9, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={143:0}, b={143:0}, i=9, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=9, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=138, i=9, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=10, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={143:0}, b={143:0}, i=10, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=10, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=150, i=10, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=11, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={143:0}, b={143:0}, i=11, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=11, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=129, i=11, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=12, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={143:0}, b={143:0}, i=12, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=12, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=144, i=12, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=13, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={143:0}, b={143:0}, i=13, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=13, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=134, i=13, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=14, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={143:0}, b={143:0}, i=14, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=14, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=155, i=14, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=15, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={143:0}, b={143:0}, i=15, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=15, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=142, i=15, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=16, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={143:0}, b={143:0}, i=16, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=16, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=148, i=16, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=17, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={143:0}, b={143:0}, i=17, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=17, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=163, i=17, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=18, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={143:0}, b={143:0}, i=18, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=18, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=146, i=18, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=19, size=17] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=17, b={143:0}, b={143:0}, i=19, size=17] [L20] RET return i; VAL [\old(size)=17, \result=19, b={143:0}, b={143:0}, i=19, size=17] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=19, i=17, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=19, i=17, mask={143:0}] [L26] i++ VAL [b={159:0}, i=18, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=18, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=18, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=18, b={143:0}, b={143:0}, i=0, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={143:0}, b={143:0}, i=0, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=0, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=160, i=0, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=1, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={143:0}, b={143:0}, i=1, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=1, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=131, i=1, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=2, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={143:0}, b={143:0}, i=2, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=2, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=133, i=2, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=3, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={143:0}, b={143:0}, i=3, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=3, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=135, i=3, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=4, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={143:0}, b={143:0}, i=4, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=4, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=151, i=4, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=5, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={143:0}, b={143:0}, i=5, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=5, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=137, i=5, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=6, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={143:0}, b={143:0}, i=6, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=6, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=136, i=6, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=7, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={143:0}, b={143:0}, i=7, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=7, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=154, i=7, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=8, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={143:0}, b={143:0}, i=8, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=8, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=132, i=8, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=9, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={143:0}, b={143:0}, i=9, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=9, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=138, i=9, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=10, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={143:0}, b={143:0}, i=10, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=10, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=150, i=10, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=11, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={143:0}, b={143:0}, i=11, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=11, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=129, i=11, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=12, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={143:0}, b={143:0}, i=12, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=12, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=144, i=12, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=13, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={143:0}, b={143:0}, i=13, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=13, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=134, i=13, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=14, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={143:0}, b={143:0}, i=14, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=14, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=155, i=14, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=15, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={143:0}, b={143:0}, i=15, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=15, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=142, i=15, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=16, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={143:0}, b={143:0}, i=16, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=16, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=148, i=16, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=17, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={143:0}, b={143:0}, i=17, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=17, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=163, i=17, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=18, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={143:0}, b={143:0}, i=18, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=18, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=146, i=18, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=19, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={143:0}, b={143:0}, i=19, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=19, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=140, i=19, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=20, size=18] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=18, b={143:0}, b={143:0}, i=20, size=18] [L20] RET return i; VAL [\old(size)=18, \result=20, b={143:0}, b={143:0}, i=20, size=18] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=20, i=18, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=20, i=18, mask={143:0}] [L26] i++ VAL [b={159:0}, i=19, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=19, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=19, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=19, b={143:0}, b={143:0}, i=0, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=0, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=0, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=160, i=0, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=1, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=1, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=1, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=131, i=1, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=2, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=2, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=2, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=133, i=2, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=3, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=3, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=3, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=135, i=3, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=4, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=4, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=4, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=151, i=4, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=5, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=5, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=5, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=137, i=5, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=6, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=6, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=6, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=136, i=6, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=7, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=7, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=7, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=154, i=7, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=8, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=8, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=8, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=132, i=8, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=9, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=9, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=9, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=138, i=9, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=10, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=10, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=10, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=150, i=10, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=11, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=11, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=11, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=129, i=11, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=12, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=12, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=12, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=144, i=12, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=13, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=13, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=13, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=134, i=13, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=14, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=14, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=14, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=155, i=14, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=15, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=15, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=15, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=142, i=15, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=16, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=16, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=16, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=148, i=16, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=17, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=17, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=17, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=163, i=17, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=18, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=18, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=18, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=146, i=18, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=19, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=19, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=19, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=140, i=19, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=20, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={143:0}, b={143:0}, i=20, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=20, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=156, i=20, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=21, size=19] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=19, b={143:0}, b={143:0}, i=21, size=19] [L20] RET return i; VAL [\old(size)=19, \result=21, b={143:0}, b={143:0}, i=21, size=19] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=21, i=19, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=21, i=19, mask={143:0}] [L26] i++ VAL [b={159:0}, i=20, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=20, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=20, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=20, b={143:0}, b={143:0}, i=0, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=0, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=0, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=160, i=0, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=1, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=1, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=1, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=131, i=1, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=2, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=2, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=2, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=133, i=2, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=3, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=3, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=3, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=135, i=3, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=4, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=4, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=4, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=151, i=4, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=5, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=5, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=5, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=137, i=5, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=6, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=6, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=6, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=136, i=6, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=7, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=7, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=7, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=154, i=7, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=8, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=8, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=8, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=132, i=8, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=9, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=9, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=9, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=138, i=9, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=10, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=10, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=10, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=150, i=10, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=11, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=11, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=11, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=129, i=11, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=12, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=12, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=12, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=144, i=12, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=13, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=13, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=13, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=134, i=13, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=14, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=14, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=14, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=155, i=14, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=15, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=15, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=15, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=142, i=15, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=16, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=16, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=16, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=148, i=16, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=17, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=17, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=17, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=163, i=17, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=18, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=18, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=18, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=146, i=18, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=19, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=19, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=19, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=140, i=19, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=20, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=20, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=20, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=156, i=20, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=21, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={143:0}, b={143:0}, i=21, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=21, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=139, i=21, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=22, size=20] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=20, b={143:0}, b={143:0}, i=22, size=20] [L20] RET return i; VAL [\old(size)=20, \result=22, b={143:0}, b={143:0}, i=22, size=20] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=22, i=20, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=22, i=20, mask={143:0}] [L26] i++ VAL [b={159:0}, i=21, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=21, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=21, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=21, b={143:0}, b={143:0}, i=0, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=0, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=0, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=160, i=0, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=1, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=1, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=1, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=131, i=1, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=2, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=2, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=2, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=133, i=2, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=3, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=3, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=3, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=135, i=3, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=4, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=4, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=4, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=151, i=4, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=5, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=5, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=5, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=137, i=5, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=6, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=6, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=6, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=136, i=6, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=7, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=7, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=7, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=154, i=7, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=8, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=8, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=8, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=132, i=8, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=9, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=9, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=9, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=138, i=9, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=10, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=10, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=10, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=150, i=10, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=11, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=11, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=11, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=129, i=11, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=12, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=12, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=12, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=144, i=12, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=13, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=13, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=13, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=134, i=13, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=14, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=14, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=14, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=155, i=14, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=15, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=15, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=15, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=142, i=15, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=16, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=16, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=16, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=148, i=16, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=17, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=17, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=17, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=163, i=17, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=18, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=18, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=18, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=146, i=18, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=19, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=19, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=19, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=140, i=19, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=20, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=20, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=20, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=156, i=20, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=21, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=21, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=21, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=139, i=21, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=22, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={143:0}, b={143:0}, i=22, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=22, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=157, i=22, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=23, size=21] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=21, b={143:0}, b={143:0}, i=23, size=21] [L20] RET return i; VAL [\old(size)=21, \result=23, b={143:0}, b={143:0}, i=23, size=21] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=23, i=21, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=23, i=21, mask={143:0}] [L26] i++ VAL [b={159:0}, i=22, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=22, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=22, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=22, b={143:0}, b={143:0}, i=0, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=0, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=0, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=160, i=0, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=1, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=1, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=1, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=131, i=1, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=2, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=2, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=2, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=133, i=2, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=3, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=3, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=3, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=135, i=3, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=4, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=4, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=4, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=151, i=4, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=5, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=5, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=5, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=137, i=5, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=6, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=6, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=6, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=136, i=6, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=7, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=7, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=7, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=154, i=7, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=8, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=8, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=8, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=132, i=8, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=9, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=9, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=9, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=138, i=9, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=10, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=10, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=10, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=150, i=10, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=11, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=11, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=11, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=129, i=11, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=12, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=12, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=12, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=144, i=12, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=13, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=13, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=13, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=134, i=13, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=14, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=14, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=14, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=155, i=14, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=15, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=15, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=15, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=142, i=15, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=16, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=16, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=16, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=148, i=16, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=17, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=17, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=17, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=163, i=17, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=18, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=18, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=18, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=146, i=18, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=19, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=19, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=19, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=140, i=19, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=20, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=20, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=20, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=156, i=20, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=21, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=21, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=21, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=139, i=21, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=22, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=22, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=22, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=157, i=22, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=23, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={143:0}, b={143:0}, i=23, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=23, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=152, i=23, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=24, size=22] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=22, b={143:0}, b={143:0}, i=24, size=22] [L20] RET return i; VAL [\old(size)=22, \result=24, b={143:0}, b={143:0}, i=24, size=22] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=24, i=22, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=24, i=22, mask={143:0}] [L26] i++ VAL [b={159:0}, i=23, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=23, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=23, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=23, b={143:0}, b={143:0}, i=0, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=0, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=0, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=160, i=0, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=1, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=1, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=1, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=131, i=1, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=2, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=2, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=2, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=133, i=2, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=3, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=3, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=3, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=135, i=3, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=4, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=4, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=4, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=151, i=4, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=5, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=5, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=5, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=137, i=5, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=6, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=6, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=6, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=136, i=6, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=7, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=7, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=7, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=154, i=7, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=8, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=8, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=8, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=132, i=8, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=9, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=9, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=9, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=138, i=9, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=10, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=10, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=10, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=150, i=10, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=11, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=11, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=11, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=129, i=11, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=12, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=12, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=12, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=144, i=12, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=13, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=13, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=13, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=134, i=13, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=14, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=14, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=14, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=155, i=14, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=15, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=15, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=15, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=142, i=15, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=16, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=16, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=16, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=148, i=16, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=17, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=17, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=17, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=163, i=17, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=18, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=18, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=18, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=146, i=18, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=19, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=19, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=19, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=140, i=19, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=20, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=20, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=20, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=156, i=20, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=21, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=21, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=21, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=139, i=21, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=22, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=22, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=22, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=157, i=22, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=23, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=23, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=23, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=152, i=23, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=24, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={143:0}, b={143:0}, i=24, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=24, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=162, i=24, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=25, size=23] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=23, b={143:0}, b={143:0}, i=25, size=23] [L20] RET return i; VAL [\old(size)=23, \result=25, b={143:0}, b={143:0}, i=25, size=23] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=25, i=23, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=25, i=23, mask={143:0}] [L26] i++ VAL [b={159:0}, i=24, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=24, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=24, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=24, b={143:0}, b={143:0}, i=0, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=0, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=0, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=160, i=0, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=1, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=1, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=1, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=131, i=1, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=2, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=2, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=2, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=133, i=2, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=3, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=3, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=3, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=135, i=3, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=4, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=4, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=4, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=151, i=4, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=5, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=5, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=5, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=137, i=5, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=6, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=6, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=6, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=136, i=6, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=7, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=7, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=7, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=154, i=7, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=8, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=8, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=8, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=132, i=8, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=9, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=9, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=9, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=138, i=9, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=10, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=10, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=10, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=150, i=10, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=11, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=11, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=11, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=129, i=11, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=12, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=12, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=12, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=144, i=12, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=13, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=13, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=13, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=134, i=13, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=14, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=14, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=14, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=155, i=14, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=15, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=15, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=15, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=142, i=15, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=16, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=16, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=16, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=148, i=16, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=17, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=17, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=17, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=163, i=17, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=18, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=18, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=18, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=146, i=18, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=19, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=19, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=19, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=140, i=19, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=20, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=20, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=20, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=156, i=20, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=21, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=21, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=21, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=139, i=21, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=22, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=22, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=22, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=157, i=22, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=23, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=23, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=23, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=152, i=23, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=24, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=24, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=24, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=162, i=24, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=25, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={143:0}, b={143:0}, i=25, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=25, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=164, i=25, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=26, size=24] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=24, b={143:0}, b={143:0}, i=26, size=24] [L20] RET return i; VAL [\old(size)=24, \result=26, b={143:0}, b={143:0}, i=26, size=24] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=26, i=24, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=26, i=24, mask={143:0}] [L26] i++ VAL [b={159:0}, i=25, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=25, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=25, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=25, b={143:0}, b={143:0}, i=0, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=0, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=0, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=160, i=0, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=1, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=1, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=1, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=131, i=1, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=2, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=2, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=2, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=133, i=2, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=3, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=3, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=3, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=135, i=3, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=4, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=4, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=4, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=151, i=4, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=5, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=5, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=5, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=137, i=5, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=6, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=6, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=6, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=136, i=6, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=7, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=7, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=7, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=154, i=7, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=8, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=8, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=8, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=132, i=8, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=9, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=9, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=9, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=138, i=9, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=10, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=10, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=10, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=150, i=10, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=11, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=11, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=11, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=129, i=11, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=12, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=12, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=12, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=144, i=12, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=13, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=13, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=13, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=134, i=13, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=14, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=14, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=14, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=155, i=14, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=15, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=15, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=15, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=142, i=15, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=16, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=16, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=16, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=148, i=16, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=17, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=17, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=17, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=163, i=17, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=18, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=18, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=18, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=146, i=18, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=19, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=19, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=19, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=140, i=19, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=20, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=20, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=20, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=156, i=20, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=21, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=21, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=21, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=139, i=21, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=22, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=22, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=22, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=157, i=22, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=23, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=23, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=23, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=152, i=23, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=24, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=24, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=24, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=162, i=24, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=25, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=25, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=25, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=164, i=25, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=26, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={143:0}, b={143:0}, i=26, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=26, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=161, i=26, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=27, size=25] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=25, b={143:0}, b={143:0}, i=27, size=25] [L20] RET return i; VAL [\old(size)=25, \result=27, b={143:0}, b={143:0}, i=27, size=25] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=27, i=25, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=27, i=25, mask={143:0}] [L26] i++ VAL [b={159:0}, i=26, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=26, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=26, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=26, b={143:0}, b={143:0}, i=0, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=0, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=0, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=160, i=0, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=1, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=1, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=1, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=131, i=1, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=2, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=2, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=2, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=133, i=2, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=3, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=3, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=3, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=135, i=3, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=4, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=4, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=4, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=151, i=4, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=5, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=5, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=5, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=137, i=5, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=6, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=6, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=6, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=136, i=6, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=7, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=7, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=7, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=154, i=7, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=8, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=8, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=8, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=132, i=8, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=9, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=9, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=9, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=138, i=9, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=10, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=10, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=10, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=150, i=10, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=11, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=11, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=11, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=129, i=11, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=12, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=12, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=12, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=144, i=12, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=13, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=13, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=13, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=134, i=13, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=14, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=14, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=14, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=155, i=14, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=15, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=15, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=15, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=142, i=15, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=16, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=16, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=16, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=148, i=16, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=17, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=17, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=17, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=163, i=17, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=18, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=18, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=18, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=146, i=18, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=19, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=19, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=19, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=140, i=19, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=20, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=20, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=20, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=156, i=20, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=21, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=21, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=21, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=139, i=21, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=22, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=22, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=22, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=157, i=22, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=23, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=23, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=23, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=152, i=23, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=24, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=24, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=24, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=162, i=24, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=25, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=25, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=25, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=164, i=25, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=26, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=26, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=26, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=161, i=26, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=27, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={143:0}, b={143:0}, i=27, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=27, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=141, i=27, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=28, size=26] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=26, b={143:0}, b={143:0}, i=28, size=26] [L20] RET return i; VAL [\old(size)=26, \result=28, b={143:0}, b={143:0}, i=28, size=26] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=28, i=26, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=28, i=26, mask={143:0}] [L26] i++ VAL [b={159:0}, i=27, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=27, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=27, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=27, b={143:0}, b={143:0}, i=0, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=0, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=0, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=160, i=0, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=1, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=1, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=1, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=131, i=1, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=2, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=2, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=2, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=133, i=2, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=3, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=3, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=3, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=135, i=3, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=4, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=4, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=4, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=151, i=4, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=5, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=5, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=5, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=137, i=5, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=6, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=6, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=6, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=136, i=6, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=7, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=7, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=7, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=154, i=7, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=8, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=8, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=8, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=132, i=8, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=9, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=9, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=9, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=138, i=9, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=10, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=10, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=10, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=150, i=10, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=11, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=11, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=11, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=129, i=11, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=12, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=12, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=12, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=144, i=12, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=13, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=13, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=13, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=134, i=13, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=14, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=14, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=14, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=155, i=14, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=15, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=15, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=15, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=142, i=15, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=16, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=16, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=16, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=148, i=16, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=17, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=17, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=17, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=163, i=17, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=18, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=18, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=18, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=146, i=18, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=19, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=19, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=19, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=140, i=19, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=20, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=20, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=20, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=156, i=20, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=21, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=21, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=21, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=139, i=21, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=22, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=22, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=22, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=157, i=22, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=23, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=23, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=23, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=152, i=23, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=24, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=24, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=24, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=162, i=24, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=25, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=25, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=25, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=164, i=25, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=26, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=26, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=26, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=161, i=26, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=27, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=27, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=27, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=141, i=27, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=28, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={143:0}, b={143:0}, i=28, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=28, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=130, i=28, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=29, size=27] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=27, b={143:0}, b={143:0}, i=29, size=27] [L20] RET return i; VAL [\old(size)=27, \result=29, b={143:0}, b={143:0}, i=29, size=27] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=29, i=27, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=29, i=27, mask={143:0}] [L26] i++ VAL [b={159:0}, i=28, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=28, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=28, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=28, b={143:0}, b={143:0}, i=0, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=0, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=0, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=160, i=0, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=1, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=1, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=1, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=131, i=1, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=2, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=2, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=2, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=133, i=2, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=3, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=3, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=3, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=135, i=3, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=4, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=4, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=4, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=151, i=4, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=5, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=5, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=5, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=137, i=5, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=6, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=6, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=6, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=136, i=6, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=7, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=7, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=7, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=154, i=7, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=8, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=8, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=8, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=132, i=8, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=9, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=9, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=9, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=138, i=9, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=10, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=10, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=10, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=150, i=10, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=11, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=11, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=11, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=129, i=11, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=12, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=12, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=12, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=144, i=12, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=13, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=13, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=13, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=134, i=13, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=14, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=14, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=14, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=155, i=14, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=15, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=15, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=15, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=142, i=15, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=16, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=16, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=16, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=148, i=16, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=17, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=17, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=17, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=163, i=17, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=18, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=18, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=18, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=146, i=18, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=19, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=19, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=19, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=140, i=19, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=20, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=20, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=20, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=156, i=20, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=21, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=21, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=21, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=139, i=21, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=22, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=22, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=22, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=157, i=22, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=23, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=23, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=23, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=152, i=23, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=24, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=24, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=24, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=162, i=24, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=25, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=25, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=25, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=164, i=25, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=26, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=26, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=26, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=161, i=26, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=27, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=27, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=27, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=141, i=27, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=28, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=28, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=28, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=130, i=28, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=29, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={143:0}, b={143:0}, i=29, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=29, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=147, i=29, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=30, size=28] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=28, b={143:0}, b={143:0}, i=30, size=28] [L20] RET return i; VAL [\old(size)=28, \result=30, b={143:0}, b={143:0}, i=30, size=28] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=30, i=28, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=30, i=28, mask={143:0}] [L26] i++ VAL [b={159:0}, i=29, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=29, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=29, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=29, b={143:0}, b={143:0}, i=0, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=0, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=0, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=160, i=0, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=1, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=1, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=1, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=131, i=1, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=2, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=2, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=2, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=133, i=2, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=3, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=3, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=3, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=135, i=3, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=4, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=4, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=4, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=151, i=4, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=5, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=5, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=5, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=137, i=5, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=6, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=6, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=6, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=136, i=6, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=7, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=7, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=7, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=154, i=7, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=8, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=8, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=8, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=132, i=8, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=9, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=9, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=9, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=138, i=9, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=10, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=10, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=10, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=150, i=10, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=11, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=11, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=11, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=129, i=11, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=12, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=12, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=12, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=144, i=12, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=13, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=13, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=13, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=134, i=13, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=14, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=14, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=14, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=155, i=14, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=15, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=15, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=15, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=142, i=15, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=16, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=16, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=16, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=148, i=16, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=17, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=17, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=17, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=163, i=17, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=18, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=18, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=18, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=146, i=18, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=19, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=19, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=19, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=140, i=19, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=20, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=20, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=20, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=156, i=20, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=21, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=21, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=21, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=139, i=21, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=22, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=22, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=22, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=157, i=22, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=23, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=23, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=23, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=152, i=23, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=24, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=24, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=24, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=162, i=24, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=25, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=25, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=25, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=164, i=25, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=26, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=26, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=26, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=161, i=26, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=27, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=27, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=27, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=141, i=27, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=28, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=28, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=28, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=130, i=28, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=29, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=29, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=29, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=147, i=29, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=30, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={143:0}, b={143:0}, i=30, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=30, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=153, i=30, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=31, size=29] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=29, b={143:0}, b={143:0}, i=31, size=29] [L20] RET return i; VAL [\old(size)=29, \result=31, b={143:0}, b={143:0}, i=31, size=29] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=31, i=29, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=31, i=29, mask={143:0}] [L26] i++ VAL [b={159:0}, i=30, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=30, mask={143:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=30, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=30, b={143:0}, b={143:0}, i=0, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=0, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=0, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=160, i=0, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=1, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=1, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=1, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=131, i=1, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=2, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=2, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=2, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=133, i=2, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=3, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=3, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=3, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=135, i=3, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=4, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=4, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=4, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=151, i=4, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=5, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=5, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=5, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=137, i=5, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=6, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=6, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=6, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=136, i=6, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=7, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=7, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=7, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=154, i=7, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=8, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=8, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=8, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=132, i=8, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=9, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=9, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=9, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=138, i=9, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=10, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=10, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=10, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=150, i=10, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=11, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=11, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=11, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=129, i=11, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=12, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=12, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=12, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=144, i=12, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=13, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=13, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=13, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=134, i=13, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=14, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=14, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=14, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=155, i=14, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=15, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=15, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=15, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=142, i=15, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=16, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=16, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=16, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=148, i=16, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=17, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=17, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=17, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=163, i=17, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=18, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=18, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=18, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=146, i=18, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=19, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=19, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=19, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=140, i=19, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=20, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=20, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=20, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=156, i=20, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=21, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=21, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=21, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=139, i=21, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=22, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=22, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=22, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=157, i=22, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=23, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=23, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=23, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=152, i=23, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=24, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=24, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=24, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=162, i=24, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=25, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=25, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=25, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=164, i=25, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=26, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=26, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=26, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=161, i=26, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=27, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=27, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=27, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=141, i=27, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=28, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=28, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=28, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=130, i=28, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=29, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=29, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=29, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=147, i=29, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=30, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=30, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=30, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=153, i=30, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=31, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={143:0}, b={143:0}, i=31, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=31, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=145, i=31, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=32, size=30] [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=30, b={143:0}, b={143:0}, i=32, size=30] [L20] RET return i; VAL [\old(size)=30, \result=32, b={143:0}, b={143:0}, i=32, size=30] [L27] EXPR foo(mask, i) VAL [b={159:0}, foo(mask, i)=32, i=30, mask={143:0}] [L27] FCALL b[i] = foo(mask, i) VAL [b={159:0}, foo(mask, i)=32, i=30, mask={143:0}] [L26] i++ VAL [b={159:0}, i=31, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=31, mask={143:0}] [L27] CALL foo(mask, i) VAL [\old(size)=31, b={143:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=31, b={143:0}, b={143:0}, i=0, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=0, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=0, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=160, i=0, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=1, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=1, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=1, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=131, i=1, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=2, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=2, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=2, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=133, i=2, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=3, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=3, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=3, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=135, i=3, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=4, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=4, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=4, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=151, i=4, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=5, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=5, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=5, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=137, i=5, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=6, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=6, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=6, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=136, i=6, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=7, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=7, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=7, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=154, i=7, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=8, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=8, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=8, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=132, i=8, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=9, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=9, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=9, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=138, i=9, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=10, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=10, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=10, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=150, i=10, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=11, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=11, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=11, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=129, i=11, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=12, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=12, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=12, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=144, i=12, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=13, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=13, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=13, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=134, i=13, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=14, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=14, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=14, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=155, i=14, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=15, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=15, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=15, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=142, i=15, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=16, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=16, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=16, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=148, i=16, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=17, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=17, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=17, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=163, i=17, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=18, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=18, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=18, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=146, i=18, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=19, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=19, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=19, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=140, i=19, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=20, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=20, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=20, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=156, i=20, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=21, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=21, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=21, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=139, i=21, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=22, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=22, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=22, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=157, i=22, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=23, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=23, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=23, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=152, i=23, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=24, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=24, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=24, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=162, i=24, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=25, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=25, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=25, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=164, i=25, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=26, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=26, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=26, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=161, i=26, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=27, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=27, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=27, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=141, i=27, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=28, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=28, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=28, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=130, i=28, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=29, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=29, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=29, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=147, i=29, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=30, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=30, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=30, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=153, i=30, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=31, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=31, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=31, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=145, i=31, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=32, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={143:0}, b={143:0}, i=32, size=31] [L18] a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=32, size=31] [L18] FCALL b[i] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 43 locations, 8 error locations. UNSAFE Result, 617.7s OverallTime, 89 OverallIterations, 591 TraceHistogramMax, 118.1s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 4971 SDtfs, 52066 SDslu, 71239 SDs, 0 SdLazy, 185433 SolverSat, 6532 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 48.6s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 122133 GetRequests, 113555 SyntacticMatches, 914 SemanticMatches, 7664 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 301624 ImplicationChecksByTransitivity, 128.6s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=3995occurred in iteration=88, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.7s AutomataMinimizationTime, 88 MinimizatonAttempts, 1364 StatesRemovedByMinimization, 85 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 4.0s SsaConstructionTime, 179.0s SatisfiabilityAnalysisTime, 229.2s InterpolantComputationTime, 236221 NumberOfCodeBlocks, 218018 NumberOfCodeBlocksAsserted, 1329 NumberOfCheckSat, 232281 ConstructedInterpolants, 33440 QuantifiedInterpolants, 1334089546 SizeOfPredicates, 332 NumberOfNonLiveVariables, 222777 ConjunctsInSsa, 3230 ConjunctsInUnsatCore, 169 InterpolantComputations, 8 PerfectInterpolantSequences, 34048601/34444258 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...