./Ultimate.py --spec ../../sv-benchmarks/c/MemSafety.prp --file ../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-write.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for memory safety (deref-memtrack) Using default analysis Version 5842f4b8 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/config/AutomizerMemDerefMemtrack.xml -i ../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-write.c -s /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/config/svcomp-DerefFreeMemtrack-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 68d161eb03bccd8280d2086bc4cdb7b46f7ee157 ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(valid-deref) --- Real Ultimate output --- This is Ultimate 0.1.23-5842f4b [2018-11-18 10:06:10,130 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-18 10:06:10,132 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-18 10:06:10,141 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-18 10:06:10,141 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-18 10:06:10,142 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-18 10:06:10,143 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-18 10:06:10,144 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-18 10:06:10,145 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-18 10:06:10,146 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-18 10:06:10,146 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-18 10:06:10,146 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-18 10:06:10,147 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-18 10:06:10,148 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-18 10:06:10,149 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-18 10:06:10,150 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-18 10:06:10,150 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-18 10:06:10,152 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-18 10:06:10,153 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-18 10:06:10,154 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-18 10:06:10,155 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-18 10:06:10,156 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-18 10:06:10,158 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-18 10:06:10,158 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-18 10:06:10,158 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-18 10:06:10,158 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-18 10:06:10,159 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-18 10:06:10,160 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-18 10:06:10,160 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-18 10:06:10,162 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-18 10:06:10,162 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-18 10:06:10,162 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-18 10:06:10,162 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-18 10:06:10,162 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-18 10:06:10,163 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-18 10:06:10,163 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-18 10:06:10,164 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/config/svcomp-DerefFreeMemtrack-32bit-Automizer_Default.epf [2018-11-18 10:06:10,174 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-18 10:06:10,174 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-18 10:06:10,175 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-18 10:06:10,175 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-18 10:06:10,175 INFO L133 SettingsManager]: * Use SBE=true [2018-11-18 10:06:10,175 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-18 10:06:10,175 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-18 10:06:10,176 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-18 10:06:10,176 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-18 10:06:10,176 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-18 10:06:10,176 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-18 10:06:10,176 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-11-18 10:06:10,176 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-11-18 10:06:10,176 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-11-18 10:06:10,176 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-18 10:06:10,177 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-18 10:06:10,177 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-18 10:06:10,177 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-18 10:06:10,177 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-18 10:06:10,177 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-18 10:06:10,177 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-18 10:06:10,177 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-18 10:06:10,177 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-18 10:06:10,178 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-18 10:06:10,178 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-18 10:06:10,178 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-18 10:06:10,178 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 68d161eb03bccd8280d2086bc4cdb7b46f7ee157 [2018-11-18 10:06:10,204 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-18 10:06:10,211 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-18 10:06:10,213 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-18 10:06:10,214 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-18 10:06:10,215 INFO L276 PluginConnector]: CDTParser initialized [2018-11-18 10:06:10,215 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-write.c [2018-11-18 10:06:10,251 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/data/a3052f142/0a57d9b46aac4c5ca58b5372ea194d71/FLAGdae9bc293 [2018-11-18 10:06:10,661 INFO L307 CDTParser]: Found 1 translation units. [2018-11-18 10:06:10,662 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-write.c [2018-11-18 10:06:10,666 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/data/a3052f142/0a57d9b46aac4c5ca58b5372ea194d71/FLAGdae9bc293 [2018-11-18 10:06:10,676 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/data/a3052f142/0a57d9b46aac4c5ca58b5372ea194d71 [2018-11-18 10:06:10,678 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-18 10:06:10,679 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-11-18 10:06:10,679 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-18 10:06:10,680 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-18 10:06:10,682 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-18 10:06:10,683 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 10:06:10" (1/1) ... [2018-11-18 10:06:10,684 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@44c038ee and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:06:10, skipping insertion in model container [2018-11-18 10:06:10,685 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 10:06:10" (1/1) ... [2018-11-18 10:06:10,691 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-18 10:06:10,703 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-18 10:06:10,801 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 10:06:10,807 INFO L191 MainTranslator]: Completed pre-run [2018-11-18 10:06:10,819 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 10:06:10,831 INFO L195 MainTranslator]: Completed translation [2018-11-18 10:06:10,832 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:06:10 WrapperNode [2018-11-18 10:06:10,832 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-18 10:06:10,832 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-18 10:06:10,832 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-18 10:06:10,833 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-18 10:06:10,841 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:06:10" (1/1) ... [2018-11-18 10:06:10,841 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:06:10" (1/1) ... [2018-11-18 10:06:10,846 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:06:10" (1/1) ... [2018-11-18 10:06:10,846 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:06:10" (1/1) ... [2018-11-18 10:06:10,850 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:06:10" (1/1) ... [2018-11-18 10:06:10,854 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:06:10" (1/1) ... [2018-11-18 10:06:10,854 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:06:10" (1/1) ... [2018-11-18 10:06:10,856 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-18 10:06:10,856 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-18 10:06:10,856 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-18 10:06:10,856 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-18 10:06:10,857 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:06:10" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-18 10:06:10,937 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-18 10:06:10,937 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-18 10:06:10,937 INFO L138 BoogieDeclarations]: Found implementation of procedure foo [2018-11-18 10:06:10,937 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-18 10:06:10,937 INFO L130 BoogieDeclarations]: Found specification of procedure foo [2018-11-18 10:06:10,938 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2018-11-18 10:06:10,938 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-18 10:06:10,938 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-18 10:06:10,938 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2018-11-18 10:06:10,938 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-18 10:06:10,938 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-18 10:06:10,938 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-18 10:06:10,938 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~int [2018-11-18 10:06:11,096 INFO L278 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-18 10:06:11,097 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 10:06:11 BoogieIcfgContainer [2018-11-18 10:06:11,097 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-18 10:06:11,097 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-18 10:06:11,097 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-18 10:06:11,099 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-18 10:06:11,099 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 18.11 10:06:10" (1/3) ... [2018-11-18 10:06:11,100 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7d04ac52 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 18.11 10:06:11, skipping insertion in model container [2018-11-18 10:06:11,100 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:06:10" (2/3) ... [2018-11-18 10:06:11,100 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7d04ac52 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 18.11 10:06:11, skipping insertion in model container [2018-11-18 10:06:11,101 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 10:06:11" (3/3) ... [2018-11-18 10:06:11,102 INFO L112 eAbstractionObserver]: Analyzing ICFG ArraysWithLenghtAtDeclaration_false-valid-deref-write.c [2018-11-18 10:06:11,110 INFO L136 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-18 10:06:11,114 INFO L148 ceAbstractionStarter]: Appying trace abstraction to program that has 8 error locations. [2018-11-18 10:06:11,123 INFO L257 AbstractCegarLoop]: Starting to check reachability of 8 error locations. [2018-11-18 10:06:11,138 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-18 10:06:11,139 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-18 10:06:11,139 INFO L383 AbstractCegarLoop]: Hoare is false [2018-11-18 10:06:11,139 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-18 10:06:11,139 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-18 10:06:11,139 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-18 10:06:11,139 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-18 10:06:11,139 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-18 10:06:11,139 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-18 10:06:11,148 INFO L276 IsEmpty]: Start isEmpty. Operand 43 states. [2018-11-18 10:06:11,156 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-11-18 10:06:11,156 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:11,157 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:11,159 INFO L423 AbstractCegarLoop]: === Iteration 1 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:11,163 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:11,163 INFO L82 PathProgramCache]: Analyzing trace with hash 1597032710, now seen corresponding path program 1 times [2018-11-18 10:06:11,165 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:11,165 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:11,202 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:11,202 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:06:11,202 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:11,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:11,249 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:06:11,251 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:06:11,251 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 10:06:11,253 INFO L459 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-11-18 10:06:11,263 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-11-18 10:06:11,264 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-11-18 10:06:11,266 INFO L87 Difference]: Start difference. First operand 43 states. Second operand 2 states. [2018-11-18 10:06:11,280 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:11,280 INFO L93 Difference]: Finished difference Result 43 states and 46 transitions. [2018-11-18 10:06:11,280 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-11-18 10:06:11,281 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 11 [2018-11-18 10:06:11,281 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:11,286 INFO L225 Difference]: With dead ends: 43 [2018-11-18 10:06:11,286 INFO L226 Difference]: Without dead ends: 40 [2018-11-18 10:06:11,287 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-11-18 10:06:11,298 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states. [2018-11-18 10:06:11,313 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 40. [2018-11-18 10:06:11,314 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40 states. [2018-11-18 10:06:11,315 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 43 transitions. [2018-11-18 10:06:11,316 INFO L78 Accepts]: Start accepts. Automaton has 40 states and 43 transitions. Word has length 11 [2018-11-18 10:06:11,316 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:11,316 INFO L480 AbstractCegarLoop]: Abstraction has 40 states and 43 transitions. [2018-11-18 10:06:11,316 INFO L481 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-11-18 10:06:11,316 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states and 43 transitions. [2018-11-18 10:06:11,317 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-11-18 10:06:11,317 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:11,317 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:11,317 INFO L423 AbstractCegarLoop]: === Iteration 2 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:11,318 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:11,318 INFO L82 PathProgramCache]: Analyzing trace with hash 1820883224, now seen corresponding path program 1 times [2018-11-18 10:06:11,318 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:11,318 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:11,319 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:11,319 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:06:11,319 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:11,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:11,374 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:06:11,374 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:06:11,374 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:06:11,375 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 10:06:11,375 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:06:11,375 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:06:11,376 INFO L87 Difference]: Start difference. First operand 40 states and 43 transitions. Second operand 3 states. [2018-11-18 10:06:11,455 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:11,455 INFO L93 Difference]: Finished difference Result 59 states and 63 transitions. [2018-11-18 10:06:11,455 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:06:11,455 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 12 [2018-11-18 10:06:11,455 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:11,457 INFO L225 Difference]: With dead ends: 59 [2018-11-18 10:06:11,457 INFO L226 Difference]: Without dead ends: 59 [2018-11-18 10:06:11,458 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:06:11,458 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2018-11-18 10:06:11,463 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 44. [2018-11-18 10:06:11,463 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 44 states. [2018-11-18 10:06:11,464 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 47 transitions. [2018-11-18 10:06:11,464 INFO L78 Accepts]: Start accepts. Automaton has 44 states and 47 transitions. Word has length 12 [2018-11-18 10:06:11,465 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:11,465 INFO L480 AbstractCegarLoop]: Abstraction has 44 states and 47 transitions. [2018-11-18 10:06:11,465 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 10:06:11,465 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 47 transitions. [2018-11-18 10:06:11,465 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2018-11-18 10:06:11,465 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:11,465 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:11,466 INFO L423 AbstractCegarLoop]: === Iteration 3 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:11,466 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:11,466 INFO L82 PathProgramCache]: Analyzing trace with hash 697121729, now seen corresponding path program 1 times [2018-11-18 10:06:11,466 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:11,466 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:11,467 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:11,467 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:06:11,467 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:11,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:11,501 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:06:11,501 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:06:11,501 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 10:06:11,502 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 10:06:11,502 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:06:11,502 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:06:11,502 INFO L87 Difference]: Start difference. First operand 44 states and 47 transitions. Second operand 3 states. [2018-11-18 10:06:11,548 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:11,548 INFO L93 Difference]: Finished difference Result 55 states and 59 transitions. [2018-11-18 10:06:11,551 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:06:11,551 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 13 [2018-11-18 10:06:11,551 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:11,553 INFO L225 Difference]: With dead ends: 55 [2018-11-18 10:06:11,553 INFO L226 Difference]: Without dead ends: 55 [2018-11-18 10:06:11,554 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:06:11,554 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55 states. [2018-11-18 10:06:11,557 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55 to 47. [2018-11-18 10:06:11,557 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 47 states. [2018-11-18 10:06:11,558 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 51 transitions. [2018-11-18 10:06:11,558 INFO L78 Accepts]: Start accepts. Automaton has 47 states and 51 transitions. Word has length 13 [2018-11-18 10:06:11,558 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:11,558 INFO L480 AbstractCegarLoop]: Abstraction has 47 states and 51 transitions. [2018-11-18 10:06:11,558 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 10:06:11,558 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 51 transitions. [2018-11-18 10:06:11,559 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-11-18 10:06:11,559 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:11,559 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:11,559 INFO L423 AbstractCegarLoop]: === Iteration 4 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:11,559 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:11,560 INFO L82 PathProgramCache]: Analyzing trace with hash 135937166, now seen corresponding path program 1 times [2018-11-18 10:06:11,560 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:11,560 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:11,561 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:11,561 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:06:11,561 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:11,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:11,687 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:06:11,687 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:06:11,688 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 10:06:11,688 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-18 10:06:11,688 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-18 10:06:11,688 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-11-18 10:06:11,689 INFO L87 Difference]: Start difference. First operand 47 states and 51 transitions. Second operand 6 states. [2018-11-18 10:06:11,789 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:11,789 INFO L93 Difference]: Finished difference Result 49 states and 53 transitions. [2018-11-18 10:06:11,789 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 10:06:11,790 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 14 [2018-11-18 10:06:11,790 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:11,790 INFO L225 Difference]: With dead ends: 49 [2018-11-18 10:06:11,791 INFO L226 Difference]: Without dead ends: 49 [2018-11-18 10:06:11,791 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2018-11-18 10:06:11,791 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states. [2018-11-18 10:06:11,794 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 46. [2018-11-18 10:06:11,794 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46 states. [2018-11-18 10:06:11,795 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 50 transitions. [2018-11-18 10:06:11,795 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 50 transitions. Word has length 14 [2018-11-18 10:06:11,795 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:11,795 INFO L480 AbstractCegarLoop]: Abstraction has 46 states and 50 transitions. [2018-11-18 10:06:11,795 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-18 10:06:11,795 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 50 transitions. [2018-11-18 10:06:11,796 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-11-18 10:06:11,796 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:11,796 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:11,796 INFO L423 AbstractCegarLoop]: === Iteration 5 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:11,796 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:11,797 INFO L82 PathProgramCache]: Analyzing trace with hash 135937165, now seen corresponding path program 1 times [2018-11-18 10:06:11,797 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:11,797 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:11,797 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:11,798 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:06:11,798 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:11,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:11,833 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:06:11,834 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:06:11,834 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-18 10:06:11,834 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 10:06:11,834 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 10:06:11,834 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 10:06:11,835 INFO L87 Difference]: Start difference. First operand 46 states and 50 transitions. Second operand 5 states. [2018-11-18 10:06:11,887 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:11,887 INFO L93 Difference]: Finished difference Result 45 states and 49 transitions. [2018-11-18 10:06:11,888 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 10:06:11,888 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 14 [2018-11-18 10:06:11,888 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:11,888 INFO L225 Difference]: With dead ends: 45 [2018-11-18 10:06:11,888 INFO L226 Difference]: Without dead ends: 45 [2018-11-18 10:06:11,889 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-18 10:06:11,889 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45 states. [2018-11-18 10:06:11,891 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45 to 45. [2018-11-18 10:06:11,892 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45 states. [2018-11-18 10:06:11,892 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 49 transitions. [2018-11-18 10:06:11,893 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 49 transitions. Word has length 14 [2018-11-18 10:06:11,893 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:11,893 INFO L480 AbstractCegarLoop]: Abstraction has 45 states and 49 transitions. [2018-11-18 10:06:11,893 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 10:06:11,893 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 49 transitions. [2018-11-18 10:06:11,894 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-11-18 10:06:11,894 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:11,894 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:11,894 INFO L423 AbstractCegarLoop]: === Iteration 6 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:11,894 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:11,894 INFO L82 PathProgramCache]: Analyzing trace with hash -497753495, now seen corresponding path program 1 times [2018-11-18 10:06:11,894 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:11,894 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:11,895 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:11,895 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:06:11,895 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:11,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:11,956 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:06:11,957 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:06:11,957 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 10:06:11,957 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 10:06:11,957 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:06:11,957 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:06:11,957 INFO L87 Difference]: Start difference. First operand 45 states and 49 transitions. Second operand 3 states. [2018-11-18 10:06:11,977 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:11,977 INFO L93 Difference]: Finished difference Result 43 states and 47 transitions. [2018-11-18 10:06:11,977 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:06:11,978 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 17 [2018-11-18 10:06:11,978 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:11,978 INFO L225 Difference]: With dead ends: 43 [2018-11-18 10:06:11,978 INFO L226 Difference]: Without dead ends: 43 [2018-11-18 10:06:11,979 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:06:11,979 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states. [2018-11-18 10:06:11,981 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 43. [2018-11-18 10:06:11,981 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 43 states. [2018-11-18 10:06:11,982 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 47 transitions. [2018-11-18 10:06:11,982 INFO L78 Accepts]: Start accepts. Automaton has 43 states and 47 transitions. Word has length 17 [2018-11-18 10:06:11,983 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:11,983 INFO L480 AbstractCegarLoop]: Abstraction has 43 states and 47 transitions. [2018-11-18 10:06:11,983 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 10:06:11,983 INFO L276 IsEmpty]: Start isEmpty. Operand 43 states and 47 transitions. [2018-11-18 10:06:11,983 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-11-18 10:06:11,983 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:11,984 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:11,984 INFO L423 AbstractCegarLoop]: === Iteration 7 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:11,984 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:11,984 INFO L82 PathProgramCache]: Analyzing trace with hash -497753494, now seen corresponding path program 1 times [2018-11-18 10:06:11,984 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:11,984 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:11,985 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:11,985 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:06:11,985 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:11,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:12,027 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:06:12,027 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:06:12,027 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-18 10:06:12,027 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-18 10:06:12,028 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-18 10:06:12,028 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-11-18 10:06:12,028 INFO L87 Difference]: Start difference. First operand 43 states and 47 transitions. Second operand 6 states. [2018-11-18 10:06:12,143 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:12,143 INFO L93 Difference]: Finished difference Result 62 states and 67 transitions. [2018-11-18 10:06:12,144 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 10:06:12,144 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 17 [2018-11-18 10:06:12,144 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:12,145 INFO L225 Difference]: With dead ends: 62 [2018-11-18 10:06:12,145 INFO L226 Difference]: Without dead ends: 62 [2018-11-18 10:06:12,145 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-18 10:06:12,145 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62 states. [2018-11-18 10:06:12,148 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62 to 47. [2018-11-18 10:06:12,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 47 states. [2018-11-18 10:06:12,149 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 52 transitions. [2018-11-18 10:06:12,149 INFO L78 Accepts]: Start accepts. Automaton has 47 states and 52 transitions. Word has length 17 [2018-11-18 10:06:12,149 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:12,150 INFO L480 AbstractCegarLoop]: Abstraction has 47 states and 52 transitions. [2018-11-18 10:06:12,150 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-18 10:06:12,150 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 52 transitions. [2018-11-18 10:06:12,150 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-11-18 10:06:12,150 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:12,150 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:12,151 INFO L423 AbstractCegarLoop]: === Iteration 8 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:12,151 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:12,151 INFO L82 PathProgramCache]: Analyzing trace with hash 1254753657, now seen corresponding path program 1 times [2018-11-18 10:06:12,151 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:12,151 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:12,152 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:12,152 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:06:12,152 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:12,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:12,190 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:06:12,190 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:06:12,190 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:06:12,198 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:06:12,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:12,217 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:06:12,230 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:06:12,245 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:06:12,245 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3] total 3 [2018-11-18 10:06:12,245 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-18 10:06:12,245 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-18 10:06:12,245 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-18 10:06:12,246 INFO L87 Difference]: Start difference. First operand 47 states and 52 transitions. Second operand 4 states. [2018-11-18 10:06:12,280 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:12,280 INFO L93 Difference]: Finished difference Result 59 states and 66 transitions. [2018-11-18 10:06:12,280 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-18 10:06:12,280 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 19 [2018-11-18 10:06:12,281 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:12,281 INFO L225 Difference]: With dead ends: 59 [2018-11-18 10:06:12,281 INFO L226 Difference]: Without dead ends: 59 [2018-11-18 10:06:12,281 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 17 SyntacticMatches, 3 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-18 10:06:12,282 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2018-11-18 10:06:12,284 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 53. [2018-11-18 10:06:12,284 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 53 states. [2018-11-18 10:06:12,285 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 59 transitions. [2018-11-18 10:06:12,285 INFO L78 Accepts]: Start accepts. Automaton has 53 states and 59 transitions. Word has length 19 [2018-11-18 10:06:12,285 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:12,285 INFO L480 AbstractCegarLoop]: Abstraction has 53 states and 59 transitions. [2018-11-18 10:06:12,285 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-18 10:06:12,285 INFO L276 IsEmpty]: Start isEmpty. Operand 53 states and 59 transitions. [2018-11-18 10:06:12,286 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-11-18 10:06:12,286 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:12,286 INFO L375 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:12,286 INFO L423 AbstractCegarLoop]: === Iteration 9 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:12,286 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:12,286 INFO L82 PathProgramCache]: Analyzing trace with hash 539365410, now seen corresponding path program 1 times [2018-11-18 10:06:12,286 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:12,286 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:12,287 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:12,287 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:06:12,287 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:12,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:12,326 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:06:12,326 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:06:12,326 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:06:12,341 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:06:12,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:12,352 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:06:12,386 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:06:12,402 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:06:12,402 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 9 [2018-11-18 10:06:12,402 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-18 10:06:12,402 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-18 10:06:12,402 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=50, Unknown=0, NotChecked=0, Total=72 [2018-11-18 10:06:12,403 INFO L87 Difference]: Start difference. First operand 53 states and 59 transitions. Second operand 9 states. [2018-11-18 10:06:12,505 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:12,505 INFO L93 Difference]: Finished difference Result 71 states and 75 transitions. [2018-11-18 10:06:12,505 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-18 10:06:12,505 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 23 [2018-11-18 10:06:12,506 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:12,506 INFO L225 Difference]: With dead ends: 71 [2018-11-18 10:06:12,506 INFO L226 Difference]: Without dead ends: 65 [2018-11-18 10:06:12,507 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 20 SyntacticMatches, 1 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=35, Invalid=75, Unknown=0, NotChecked=0, Total=110 [2018-11-18 10:06:12,507 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65 states. [2018-11-18 10:06:12,508 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65 to 49. [2018-11-18 10:06:12,508 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 49 states. [2018-11-18 10:06:12,509 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 52 transitions. [2018-11-18 10:06:12,509 INFO L78 Accepts]: Start accepts. Automaton has 49 states and 52 transitions. Word has length 23 [2018-11-18 10:06:12,509 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:12,510 INFO L480 AbstractCegarLoop]: Abstraction has 49 states and 52 transitions. [2018-11-18 10:06:12,510 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-18 10:06:12,510 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 52 transitions. [2018-11-18 10:06:12,510 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-11-18 10:06:12,510 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:12,511 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:12,512 INFO L423 AbstractCegarLoop]: === Iteration 10 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:12,512 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:12,512 INFO L82 PathProgramCache]: Analyzing trace with hash 1493607729, now seen corresponding path program 2 times [2018-11-18 10:06:12,512 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:12,512 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:12,513 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:12,513 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:06:12,513 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:12,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:12,584 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 7 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:06:12,584 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:06:12,585 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:06:12,597 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-18 10:06:12,610 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 10:06:12,610 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:06:12,612 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:06:12,651 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 7 proven. 2 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-11-18 10:06:12,666 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:06:12,666 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7] total 12 [2018-11-18 10:06:12,667 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-11-18 10:06:12,667 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-11-18 10:06:12,667 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=101, Unknown=0, NotChecked=0, Total=132 [2018-11-18 10:06:12,667 INFO L87 Difference]: Start difference. First operand 49 states and 52 transitions. Second operand 12 states. [2018-11-18 10:06:12,792 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:12,792 INFO L93 Difference]: Finished difference Result 80 states and 83 transitions. [2018-11-18 10:06:12,793 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-18 10:06:12,793 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 25 [2018-11-18 10:06:12,793 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:12,793 INFO L225 Difference]: With dead ends: 80 [2018-11-18 10:06:12,793 INFO L226 Difference]: Without dead ends: 80 [2018-11-18 10:06:12,794 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 22 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=68, Invalid=172, Unknown=0, NotChecked=0, Total=240 [2018-11-18 10:06:12,794 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states. [2018-11-18 10:06:12,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 68. [2018-11-18 10:06:12,797 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 68 states. [2018-11-18 10:06:12,797 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68 states to 68 states and 71 transitions. [2018-11-18 10:06:12,798 INFO L78 Accepts]: Start accepts. Automaton has 68 states and 71 transitions. Word has length 25 [2018-11-18 10:06:12,798 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:12,798 INFO L480 AbstractCegarLoop]: Abstraction has 68 states and 71 transitions. [2018-11-18 10:06:12,798 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-11-18 10:06:12,798 INFO L276 IsEmpty]: Start isEmpty. Operand 68 states and 71 transitions. [2018-11-18 10:06:12,799 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-11-18 10:06:12,799 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:12,799 INFO L375 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:12,799 INFO L423 AbstractCegarLoop]: === Iteration 11 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:12,799 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:12,799 INFO L82 PathProgramCache]: Analyzing trace with hash 2065437658, now seen corresponding path program 2 times [2018-11-18 10:06:12,799 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:12,799 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:12,800 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:12,800 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:06:12,800 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:12,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:12,838 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-18 10:06:12,838 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:06:12,838 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 10:06:12,838 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 10:06:12,839 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:06:12,839 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:06:12,839 INFO L87 Difference]: Start difference. First operand 68 states and 71 transitions. Second operand 3 states. [2018-11-18 10:06:12,861 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:12,861 INFO L93 Difference]: Finished difference Result 72 states and 75 transitions. [2018-11-18 10:06:12,861 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:06:12,862 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 29 [2018-11-18 10:06:12,862 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:12,862 INFO L225 Difference]: With dead ends: 72 [2018-11-18 10:06:12,862 INFO L226 Difference]: Without dead ends: 72 [2018-11-18 10:06:12,863 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:06:12,863 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72 states. [2018-11-18 10:06:12,865 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72 to 70. [2018-11-18 10:06:12,866 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 70 states. [2018-11-18 10:06:12,866 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70 states to 70 states and 73 transitions. [2018-11-18 10:06:12,867 INFO L78 Accepts]: Start accepts. Automaton has 70 states and 73 transitions. Word has length 29 [2018-11-18 10:06:12,867 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:12,867 INFO L480 AbstractCegarLoop]: Abstraction has 70 states and 73 transitions. [2018-11-18 10:06:12,867 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 10:06:12,867 INFO L276 IsEmpty]: Start isEmpty. Operand 70 states and 73 transitions. [2018-11-18 10:06:12,868 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-11-18 10:06:12,868 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:12,868 INFO L375 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:12,868 INFO L423 AbstractCegarLoop]: === Iteration 12 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:12,869 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:12,869 INFO L82 PathProgramCache]: Analyzing trace with hash -989786460, now seen corresponding path program 1 times [2018-11-18 10:06:12,869 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:12,869 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:12,870 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:12,870 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:06:12,870 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:12,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:12,930 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 2 proven. 7 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-11-18 10:06:12,930 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:06:12,930 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:06:12,946 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:06:12,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:12,961 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:06:12,993 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-18 10:06:13,008 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:06:13,009 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 4] total 10 [2018-11-18 10:06:13,009 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-18 10:06:13,009 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-18 10:06:13,009 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2018-11-18 10:06:13,009 INFO L87 Difference]: Start difference. First operand 70 states and 73 transitions. Second operand 10 states. [2018-11-18 10:06:13,095 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:13,096 INFO L93 Difference]: Finished difference Result 87 states and 91 transitions. [2018-11-18 10:06:13,096 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-18 10:06:13,096 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 37 [2018-11-18 10:06:13,096 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:13,097 INFO L225 Difference]: With dead ends: 87 [2018-11-18 10:06:13,097 INFO L226 Difference]: Without dead ends: 87 [2018-11-18 10:06:13,097 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 38 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=49, Invalid=133, Unknown=0, NotChecked=0, Total=182 [2018-11-18 10:06:13,097 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87 states. [2018-11-18 10:06:13,100 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87 to 57. [2018-11-18 10:06:13,100 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 57 states. [2018-11-18 10:06:13,101 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 58 transitions. [2018-11-18 10:06:13,101 INFO L78 Accepts]: Start accepts. Automaton has 57 states and 58 transitions. Word has length 37 [2018-11-18 10:06:13,101 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:13,101 INFO L480 AbstractCegarLoop]: Abstraction has 57 states and 58 transitions. [2018-11-18 10:06:13,101 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-18 10:06:13,101 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 58 transitions. [2018-11-18 10:06:13,102 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-11-18 10:06:13,102 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:13,102 INFO L375 BasicCegarLoop]: trace histogram [6, 5, 4, 4, 4, 4, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:13,103 INFO L423 AbstractCegarLoop]: === Iteration 13 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:13,103 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:13,103 INFO L82 PathProgramCache]: Analyzing trace with hash 1028958598, now seen corresponding path program 1 times [2018-11-18 10:06:13,103 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:13,103 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:13,104 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:13,104 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:06:13,104 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:13,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:13,171 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 36 proven. 12 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-11-18 10:06:13,171 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:06:13,171 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:06:13,190 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:06:13,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:13,207 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:06:13,221 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 36 proven. 12 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-11-18 10:06:13,245 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:06:13,245 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 4 [2018-11-18 10:06:13,245 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 10:06:13,245 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 10:06:13,246 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 10:06:13,246 INFO L87 Difference]: Start difference. First operand 57 states and 58 transitions. Second operand 5 states. [2018-11-18 10:06:13,284 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:13,285 INFO L93 Difference]: Finished difference Result 69 states and 71 transitions. [2018-11-18 10:06:13,285 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 10:06:13,285 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 50 [2018-11-18 10:06:13,285 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:13,286 INFO L225 Difference]: With dead ends: 69 [2018-11-18 10:06:13,286 INFO L226 Difference]: Without dead ends: 69 [2018-11-18 10:06:13,286 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 54 GetRequests, 48 SyntacticMatches, 3 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 10:06:13,286 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states. [2018-11-18 10:06:13,288 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 63. [2018-11-18 10:06:13,288 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2018-11-18 10:06:13,289 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 65 transitions. [2018-11-18 10:06:13,289 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 65 transitions. Word has length 50 [2018-11-18 10:06:13,289 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:13,289 INFO L480 AbstractCegarLoop]: Abstraction has 63 states and 65 transitions. [2018-11-18 10:06:13,289 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 10:06:13,289 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 65 transitions. [2018-11-18 10:06:13,290 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-11-18 10:06:13,290 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:13,290 INFO L375 BasicCegarLoop]: trace histogram [6, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:13,291 INFO L423 AbstractCegarLoop]: === Iteration 14 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:13,291 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:13,291 INFO L82 PathProgramCache]: Analyzing trace with hash -982129233, now seen corresponding path program 1 times [2018-11-18 10:06:13,291 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:13,291 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:13,292 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:13,292 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:06:13,292 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:13,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:13,377 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 5 proven. 57 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-11-18 10:06:13,377 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:06:13,377 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:06:13,393 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:06:13,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:13,411 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:06:13,460 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 42 proven. 10 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-11-18 10:06:13,476 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:06:13,476 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 8] total 15 [2018-11-18 10:06:13,477 INFO L459 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-11-18 10:06:13,477 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-11-18 10:06:13,477 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=43, Invalid=167, Unknown=0, NotChecked=0, Total=210 [2018-11-18 10:06:13,477 INFO L87 Difference]: Start difference. First operand 63 states and 65 transitions. Second operand 15 states. [2018-11-18 10:06:13,600 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:13,600 INFO L93 Difference]: Finished difference Result 71 states and 72 transitions. [2018-11-18 10:06:13,600 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-18 10:06:13,600 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 54 [2018-11-18 10:06:13,601 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:13,601 INFO L225 Difference]: With dead ends: 71 [2018-11-18 10:06:13,601 INFO L226 Difference]: Without dead ends: 68 [2018-11-18 10:06:13,601 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 71 GetRequests, 53 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 48 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=92, Invalid=288, Unknown=0, NotChecked=0, Total=380 [2018-11-18 10:06:13,602 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68 states. [2018-11-18 10:06:13,603 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68 to 63. [2018-11-18 10:06:13,603 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2018-11-18 10:06:13,604 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 64 transitions. [2018-11-18 10:06:13,604 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 64 transitions. Word has length 54 [2018-11-18 10:06:13,604 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:13,604 INFO L480 AbstractCegarLoop]: Abstraction has 63 states and 64 transitions. [2018-11-18 10:06:13,604 INFO L481 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-11-18 10:06:13,604 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 64 transitions. [2018-11-18 10:06:13,605 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-11-18 10:06:13,605 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:13,605 INFO L375 BasicCegarLoop]: trace histogram [7, 6, 5, 5, 5, 5, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:13,606 INFO L423 AbstractCegarLoop]: === Iteration 15 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:13,606 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:13,606 INFO L82 PathProgramCache]: Analyzing trace with hash -373863554, now seen corresponding path program 2 times [2018-11-18 10:06:13,606 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:13,606 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:13,607 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:13,607 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:06:13,607 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:13,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:13,676 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 70 proven. 11 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-18 10:06:13,676 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:06:13,676 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:06:13,688 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-18 10:06:13,708 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 10:06:13,709 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:06:13,711 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:06:13,776 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 78 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-18 10:06:13,792 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:06:13,792 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9] total 15 [2018-11-18 10:06:13,793 INFO L459 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-11-18 10:06:13,793 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-11-18 10:06:13,793 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=56, Invalid=154, Unknown=0, NotChecked=0, Total=210 [2018-11-18 10:06:13,793 INFO L87 Difference]: Start difference. First operand 63 states and 64 transitions. Second operand 15 states. [2018-11-18 10:06:13,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:13,932 INFO L93 Difference]: Finished difference Result 97 states and 98 transitions. [2018-11-18 10:06:13,933 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-18 10:06:13,933 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 56 [2018-11-18 10:06:13,933 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:13,934 INFO L225 Difference]: With dead ends: 97 [2018-11-18 10:06:13,934 INFO L226 Difference]: Without dead ends: 97 [2018-11-18 10:06:13,934 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 70 GetRequests, 52 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 38 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=113, Invalid=267, Unknown=0, NotChecked=0, Total=380 [2018-11-18 10:06:13,934 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states. [2018-11-18 10:06:13,936 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 92. [2018-11-18 10:06:13,937 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 92 states. [2018-11-18 10:06:13,937 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92 states to 92 states and 93 transitions. [2018-11-18 10:06:13,937 INFO L78 Accepts]: Start accepts. Automaton has 92 states and 93 transitions. Word has length 56 [2018-11-18 10:06:13,938 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:13,938 INFO L480 AbstractCegarLoop]: Abstraction has 92 states and 93 transitions. [2018-11-18 10:06:13,938 INFO L481 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-11-18 10:06:13,938 INFO L276 IsEmpty]: Start isEmpty. Operand 92 states and 93 transitions. [2018-11-18 10:06:13,940 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2018-11-18 10:06:13,940 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:13,940 INFO L375 BasicCegarLoop]: trace histogram [7, 5, 5, 5, 5, 5, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:13,940 INFO L423 AbstractCegarLoop]: === Iteration 16 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:13,940 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:13,940 INFO L82 PathProgramCache]: Analyzing trace with hash 1531366311, now seen corresponding path program 2 times [2018-11-18 10:06:13,941 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:13,941 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:13,941 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:13,941 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:06:13,941 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:13,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:14,000 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 86 trivial. 0 not checked. [2018-11-18 10:06:14,001 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:06:14,001 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:06:14,010 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-18 10:06:14,028 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 10:06:14,028 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:06:14,032 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:06:14,065 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 1 [2018-11-18 10:06:14,066 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-18 10:06:14,074 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 10:06:14,077 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 10:06:14,077 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 21 [2018-11-18 10:06:14,078 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-11-18 10:06:14,092 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 10:06:14,097 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-18 10:06:14,098 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 3 variables, input treesize:24, output treesize:17 [2018-11-18 10:06:14,234 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 86 trivial. 0 not checked. [2018-11-18 10:06:14,257 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:06:14,258 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 4] total 6 [2018-11-18 10:06:14,258 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-18 10:06:14,258 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-18 10:06:14,258 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-18 10:06:14,258 INFO L87 Difference]: Start difference. First operand 92 states and 93 transitions. Second operand 7 states. [2018-11-18 10:06:14,292 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:14,293 INFO L93 Difference]: Finished difference Result 96 states and 97 transitions. [2018-11-18 10:06:14,293 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 10:06:14,293 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 60 [2018-11-18 10:06:14,294 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:14,294 INFO L225 Difference]: With dead ends: 96 [2018-11-18 10:06:14,294 INFO L226 Difference]: Without dead ends: 96 [2018-11-18 10:06:14,294 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 63 GetRequests, 54 SyntacticMatches, 4 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-18 10:06:14,295 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96 states. [2018-11-18 10:06:14,296 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96 to 94. [2018-11-18 10:06:14,296 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 94 states. [2018-11-18 10:06:14,297 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 94 states to 94 states and 95 transitions. [2018-11-18 10:06:14,297 INFO L78 Accepts]: Start accepts. Automaton has 94 states and 95 transitions. Word has length 60 [2018-11-18 10:06:14,297 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:14,297 INFO L480 AbstractCegarLoop]: Abstraction has 94 states and 95 transitions. [2018-11-18 10:06:14,297 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-18 10:06:14,298 INFO L276 IsEmpty]: Start isEmpty. Operand 94 states and 95 transitions. [2018-11-18 10:06:14,298 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-11-18 10:06:14,298 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:14,299 INFO L375 BasicCegarLoop]: trace histogram [11, 9, 8, 8, 8, 8, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:14,299 INFO L423 AbstractCegarLoop]: === Iteration 17 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:14,299 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:14,299 INFO L82 PathProgramCache]: Analyzing trace with hash -2097865839, now seen corresponding path program 3 times [2018-11-18 10:06:14,299 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:14,299 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:14,300 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:14,300 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:06:14,300 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:14,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:14,383 INFO L134 CoverageAnalysis]: Checked inductivity of 249 backedges. 135 proven. 16 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-11-18 10:06:14,383 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:06:14,384 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:06:14,391 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 10:06:14,408 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2018-11-18 10:06:14,408 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:06:14,411 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:06:14,431 INFO L134 CoverageAnalysis]: Checked inductivity of 249 backedges. 135 proven. 16 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-11-18 10:06:14,447 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:06:14,447 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 10 [2018-11-18 10:06:14,447 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-18 10:06:14,447 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-18 10:06:14,447 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=82, Unknown=0, NotChecked=0, Total=110 [2018-11-18 10:06:14,448 INFO L87 Difference]: Start difference. First operand 94 states and 95 transitions. Second operand 11 states. [2018-11-18 10:06:14,517 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:14,517 INFO L93 Difference]: Finished difference Result 129 states and 131 transitions. [2018-11-18 10:06:14,518 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-18 10:06:14,518 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 87 [2018-11-18 10:06:14,518 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:14,519 INFO L225 Difference]: With dead ends: 129 [2018-11-18 10:06:14,519 INFO L226 Difference]: Without dead ends: 129 [2018-11-18 10:06:14,519 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 98 GetRequests, 86 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=49, Invalid=133, Unknown=0, NotChecked=0, Total=182 [2018-11-18 10:06:14,519 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 129 states. [2018-11-18 10:06:14,521 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 129 to 123. [2018-11-18 10:06:14,521 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 123 states. [2018-11-18 10:06:14,522 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 123 states to 123 states and 125 transitions. [2018-11-18 10:06:14,522 INFO L78 Accepts]: Start accepts. Automaton has 123 states and 125 transitions. Word has length 87 [2018-11-18 10:06:14,522 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:14,522 INFO L480 AbstractCegarLoop]: Abstraction has 123 states and 125 transitions. [2018-11-18 10:06:14,522 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-18 10:06:14,523 INFO L276 IsEmpty]: Start isEmpty. Operand 123 states and 125 transitions. [2018-11-18 10:06:14,523 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2018-11-18 10:06:14,523 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:14,523 INFO L375 BasicCegarLoop]: trace histogram [11, 8, 8, 8, 8, 8, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:14,524 INFO L423 AbstractCegarLoop]: === Iteration 18 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:14,524 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:14,524 INFO L82 PathProgramCache]: Analyzing trace with hash -2111284678, now seen corresponding path program 3 times [2018-11-18 10:06:14,524 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:14,524 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:14,528 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:14,528 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:06:14,528 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:14,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:14,630 INFO L134 CoverageAnalysis]: Checked inductivity of 251 backedges. 88 proven. 136 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-11-18 10:06:14,630 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:06:14,630 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:06:14,641 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 10:06:14,660 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2018-11-18 10:06:14,661 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:06:14,663 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:06:14,677 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 1 [2018-11-18 10:06:14,677 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-18 10:06:14,697 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 12 [2018-11-18 10:06:14,699 INFO L700 Elim1Store]: detected not equals via solver [2018-11-18 10:06:14,700 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 21 [2018-11-18 10:06:14,700 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-11-18 10:06:14,705 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-18 10:06:14,710 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-18 10:06:14,710 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 3 variables, input treesize:21, output treesize:14 [2018-11-18 10:06:14,966 INFO L134 CoverageAnalysis]: Checked inductivity of 251 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 239 trivial. 0 not checked. [2018-11-18 10:06:14,981 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-18 10:06:14,981 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [14] total 19 [2018-11-18 10:06:14,982 INFO L459 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-11-18 10:06:14,982 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-11-18 10:06:14,982 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=282, Unknown=0, NotChecked=0, Total=342 [2018-11-18 10:06:14,982 INFO L87 Difference]: Start difference. First operand 123 states and 125 transitions. Second operand 19 states. [2018-11-18 10:06:15,228 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:15,229 INFO L93 Difference]: Finished difference Result 148 states and 150 transitions. [2018-11-18 10:06:15,229 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-11-18 10:06:15,229 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 91 [2018-11-18 10:06:15,229 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:15,230 INFO L225 Difference]: With dead ends: 148 [2018-11-18 10:06:15,230 INFO L226 Difference]: Without dead ends: 142 [2018-11-18 10:06:15,230 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 118 GetRequests, 86 SyntacticMatches, 5 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 172 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=166, Invalid=646, Unknown=0, NotChecked=0, Total=812 [2018-11-18 10:06:15,231 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 142 states. [2018-11-18 10:06:15,233 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 142 to 133. [2018-11-18 10:06:15,233 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 133 states. [2018-11-18 10:06:15,234 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 133 states to 133 states and 135 transitions. [2018-11-18 10:06:15,234 INFO L78 Accepts]: Start accepts. Automaton has 133 states and 135 transitions. Word has length 91 [2018-11-18 10:06:15,234 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:15,234 INFO L480 AbstractCegarLoop]: Abstraction has 133 states and 135 transitions. [2018-11-18 10:06:15,234 INFO L481 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-11-18 10:06:15,234 INFO L276 IsEmpty]: Start isEmpty. Operand 133 states and 135 transitions. [2018-11-18 10:06:15,235 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 125 [2018-11-18 10:06:15,236 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:15,236 INFO L375 BasicCegarLoop]: trace histogram [16, 13, 12, 12, 12, 12, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:15,236 INFO L423 AbstractCegarLoop]: === Iteration 19 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:15,236 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:15,236 INFO L82 PathProgramCache]: Analyzing trace with hash 966829158, now seen corresponding path program 4 times [2018-11-18 10:06:15,236 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:15,236 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:15,237 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:15,237 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:06:15,237 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:15,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:15,294 INFO L134 CoverageAnalysis]: Checked inductivity of 561 backedges. 213 proven. 27 refuted. 0 times theorem prover too weak. 321 trivial. 0 not checked. [2018-11-18 10:06:15,294 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:06:15,294 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:06:15,303 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 10:06:15,340 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 10:06:15,340 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:06:15,342 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:06:15,371 INFO L134 CoverageAnalysis]: Checked inductivity of 561 backedges. 213 proven. 27 refuted. 0 times theorem prover too weak. 321 trivial. 0 not checked. [2018-11-18 10:06:15,387 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:06:15,387 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 5] total 9 [2018-11-18 10:06:15,388 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-18 10:06:15,388 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-18 10:06:15,388 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2018-11-18 10:06:15,388 INFO L87 Difference]: Start difference. First operand 133 states and 135 transitions. Second operand 10 states. [2018-11-18 10:06:15,428 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:15,428 INFO L93 Difference]: Finished difference Result 141 states and 143 transitions. [2018-11-18 10:06:15,428 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 10:06:15,428 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 124 [2018-11-18 10:06:15,429 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:15,429 INFO L225 Difference]: With dead ends: 141 [2018-11-18 10:06:15,429 INFO L226 Difference]: Without dead ends: 141 [2018-11-18 10:06:15,429 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 129 GetRequests, 120 SyntacticMatches, 1 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2018-11-18 10:06:15,430 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 141 states. [2018-11-18 10:06:15,432 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 141 to 134. [2018-11-18 10:06:15,432 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 134 states. [2018-11-18 10:06:15,433 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 136 transitions. [2018-11-18 10:06:15,433 INFO L78 Accepts]: Start accepts. Automaton has 134 states and 136 transitions. Word has length 124 [2018-11-18 10:06:15,433 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:15,433 INFO L480 AbstractCegarLoop]: Abstraction has 134 states and 136 transitions. [2018-11-18 10:06:15,433 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-18 10:06:15,433 INFO L276 IsEmpty]: Start isEmpty. Operand 134 states and 136 transitions. [2018-11-18 10:06:15,434 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 131 [2018-11-18 10:06:15,434 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:15,434 INFO L375 BasicCegarLoop]: trace histogram [17, 14, 13, 13, 13, 13, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:15,435 INFO L423 AbstractCegarLoop]: === Iteration 20 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:15,435 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:15,435 INFO L82 PathProgramCache]: Analyzing trace with hash 1628675678, now seen corresponding path program 5 times [2018-11-18 10:06:15,435 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:15,435 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:15,436 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:15,436 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:06:15,436 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:15,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:15,629 INFO L134 CoverageAnalysis]: Checked inductivity of 642 backedges. 320 proven. 34 refuted. 0 times theorem prover too weak. 288 trivial. 0 not checked. [2018-11-18 10:06:15,629 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:06:15,629 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:06:15,636 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-18 10:06:15,680 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2018-11-18 10:06:15,680 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:06:15,682 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:06:15,729 INFO L134 CoverageAnalysis]: Checked inductivity of 642 backedges. 273 proven. 48 refuted. 0 times theorem prover too weak. 321 trivial. 0 not checked. [2018-11-18 10:06:15,745 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:06:15,745 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 7] total 18 [2018-11-18 10:06:15,745 INFO L459 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-11-18 10:06:15,745 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-11-18 10:06:15,745 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=285, Unknown=0, NotChecked=0, Total=342 [2018-11-18 10:06:15,746 INFO L87 Difference]: Start difference. First operand 134 states and 136 transitions. Second operand 19 states. [2018-11-18 10:06:15,946 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:15,946 INFO L93 Difference]: Finished difference Result 205 states and 211 transitions. [2018-11-18 10:06:15,946 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-11-18 10:06:15,946 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 130 [2018-11-18 10:06:15,947 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:15,947 INFO L225 Difference]: With dead ends: 205 [2018-11-18 10:06:15,947 INFO L226 Difference]: Without dead ends: 205 [2018-11-18 10:06:15,948 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 149 GetRequests, 125 SyntacticMatches, 0 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 105 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=118, Invalid=532, Unknown=0, NotChecked=0, Total=650 [2018-11-18 10:06:15,948 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 205 states. [2018-11-18 10:06:15,950 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 205 to 177. [2018-11-18 10:06:15,951 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 177 states. [2018-11-18 10:06:15,951 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 177 states to 177 states and 181 transitions. [2018-11-18 10:06:15,951 INFO L78 Accepts]: Start accepts. Automaton has 177 states and 181 transitions. Word has length 130 [2018-11-18 10:06:15,952 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:15,952 INFO L480 AbstractCegarLoop]: Abstraction has 177 states and 181 transitions. [2018-11-18 10:06:15,952 INFO L481 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-11-18 10:06:15,952 INFO L276 IsEmpty]: Start isEmpty. Operand 177 states and 181 transitions. [2018-11-18 10:06:15,953 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 174 [2018-11-18 10:06:15,953 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:15,954 INFO L375 BasicCegarLoop]: trace histogram [23, 19, 18, 18, 18, 18, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:15,954 INFO L423 AbstractCegarLoop]: === Iteration 21 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:15,954 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:15,954 INFO L82 PathProgramCache]: Analyzing trace with hash 214822433, now seen corresponding path program 6 times [2018-11-18 10:06:15,954 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:15,954 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:15,955 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:15,955 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:06:15,955 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:15,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:16,099 INFO L134 CoverageAnalysis]: Checked inductivity of 1218 backedges. 699 proven. 198 refuted. 0 times theorem prover too weak. 321 trivial. 0 not checked. [2018-11-18 10:06:16,099 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:06:16,099 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:06:16,106 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-18 10:06:16,151 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2018-11-18 10:06:16,151 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:06:16,154 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:06:16,302 INFO L134 CoverageAnalysis]: Checked inductivity of 1218 backedges. 549 proven. 317 refuted. 0 times theorem prover too weak. 352 trivial. 0 not checked. [2018-11-18 10:06:16,318 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:06:16,318 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 15] total 29 [2018-11-18 10:06:16,318 INFO L459 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-11-18 10:06:16,318 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-11-18 10:06:16,318 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=692, Unknown=0, NotChecked=0, Total=812 [2018-11-18 10:06:16,319 INFO L87 Difference]: Start difference. First operand 177 states and 181 transitions. Second operand 29 states. [2018-11-18 10:06:16,836 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:16,836 INFO L93 Difference]: Finished difference Result 361 states and 374 transitions. [2018-11-18 10:06:16,836 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-11-18 10:06:16,836 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 173 [2018-11-18 10:06:16,836 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:16,838 INFO L225 Difference]: With dead ends: 361 [2018-11-18 10:06:16,838 INFO L226 Difference]: Without dead ends: 361 [2018-11-18 10:06:16,839 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 215 GetRequests, 163 SyntacticMatches, 0 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 698 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=598, Invalid=2264, Unknown=0, NotChecked=0, Total=2862 [2018-11-18 10:06:16,839 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 361 states. [2018-11-18 10:06:16,845 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 361 to 345. [2018-11-18 10:06:16,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 345 states. [2018-11-18 10:06:16,846 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 345 states to 345 states and 358 transitions. [2018-11-18 10:06:16,846 INFO L78 Accepts]: Start accepts. Automaton has 345 states and 358 transitions. Word has length 173 [2018-11-18 10:06:16,846 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:16,847 INFO L480 AbstractCegarLoop]: Abstraction has 345 states and 358 transitions. [2018-11-18 10:06:16,847 INFO L481 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-11-18 10:06:16,847 INFO L276 IsEmpty]: Start isEmpty. Operand 345 states and 358 transitions. [2018-11-18 10:06:16,848 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 192 [2018-11-18 10:06:16,848 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:16,848 INFO L375 BasicCegarLoop]: trace histogram [26, 22, 21, 21, 21, 21, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:16,849 INFO L423 AbstractCegarLoop]: === Iteration 22 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:16,849 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:16,849 INFO L82 PathProgramCache]: Analyzing trace with hash 151723673, now seen corresponding path program 7 times [2018-11-18 10:06:16,849 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:16,849 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:16,850 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:16,850 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:06:16,850 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:16,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:16,975 INFO L134 CoverageAnalysis]: Checked inductivity of 1593 backedges. 736 proven. 71 refuted. 0 times theorem prover too weak. 786 trivial. 0 not checked. [2018-11-18 10:06:16,975 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:06:16,975 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:06:16,984 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:06:17,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:17,019 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:06:17,114 INFO L134 CoverageAnalysis]: Checked inductivity of 1593 backedges. 1071 proven. 39 refuted. 0 times theorem prover too weak. 483 trivial. 0 not checked. [2018-11-18 10:06:17,130 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:06:17,130 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 11] total 23 [2018-11-18 10:06:17,130 INFO L459 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-11-18 10:06:17,130 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-11-18 10:06:17,131 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=89, Invalid=417, Unknown=0, NotChecked=0, Total=506 [2018-11-18 10:06:17,131 INFO L87 Difference]: Start difference. First operand 345 states and 358 transitions. Second operand 23 states. [2018-11-18 10:06:17,503 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:17,504 INFO L93 Difference]: Finished difference Result 403 states and 416 transitions. [2018-11-18 10:06:17,504 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-11-18 10:06:17,504 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 191 [2018-11-18 10:06:17,504 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:17,505 INFO L225 Difference]: With dead ends: 403 [2018-11-18 10:06:17,505 INFO L226 Difference]: Without dead ends: 394 [2018-11-18 10:06:17,506 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 221 GetRequests, 186 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 213 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=323, Invalid=1009, Unknown=0, NotChecked=0, Total=1332 [2018-11-18 10:06:17,506 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 394 states. [2018-11-18 10:06:17,519 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 394 to 382. [2018-11-18 10:06:17,519 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 382 states. [2018-11-18 10:06:17,521 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 382 states to 382 states and 395 transitions. [2018-11-18 10:06:17,521 INFO L78 Accepts]: Start accepts. Automaton has 382 states and 395 transitions. Word has length 191 [2018-11-18 10:06:17,521 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:17,521 INFO L480 AbstractCegarLoop]: Abstraction has 382 states and 395 transitions. [2018-11-18 10:06:17,521 INFO L481 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-11-18 10:06:17,521 INFO L276 IsEmpty]: Start isEmpty. Operand 382 states and 395 transitions. [2018-11-18 10:06:17,523 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 229 [2018-11-18 10:06:17,523 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:17,523 INFO L375 BasicCegarLoop]: trace histogram [31, 26, 25, 25, 25, 25, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:17,524 INFO L423 AbstractCegarLoop]: === Iteration 23 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:17,524 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:17,524 INFO L82 PathProgramCache]: Analyzing trace with hash -1624684946, now seen corresponding path program 8 times [2018-11-18 10:06:17,524 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:17,524 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:17,524 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:17,525 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:06:17,525 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:17,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:17,714 INFO L134 CoverageAnalysis]: Checked inductivity of 2285 backedges. 1242 proven. 291 refuted. 0 times theorem prover too weak. 752 trivial. 0 not checked. [2018-11-18 10:06:17,714 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:06:17,714 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:06:17,721 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-18 10:06:17,760 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 10:06:17,761 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:06:17,763 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:06:17,907 INFO L134 CoverageAnalysis]: Checked inductivity of 2285 backedges. 1409 proven. 70 refuted. 0 times theorem prover too weak. 806 trivial. 0 not checked. [2018-11-18 10:06:17,922 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:06:17,922 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 14] total 31 [2018-11-18 10:06:17,923 INFO L459 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-11-18 10:06:17,923 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-11-18 10:06:17,923 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=148, Invalid=782, Unknown=0, NotChecked=0, Total=930 [2018-11-18 10:06:17,923 INFO L87 Difference]: Start difference. First operand 382 states and 395 transitions. Second operand 31 states. [2018-11-18 10:06:18,330 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:18,330 INFO L93 Difference]: Finished difference Result 260 states and 261 transitions. [2018-11-18 10:06:18,331 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-11-18 10:06:18,331 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 228 [2018-11-18 10:06:18,331 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:18,332 INFO L225 Difference]: With dead ends: 260 [2018-11-18 10:06:18,332 INFO L226 Difference]: Without dead ends: 245 [2018-11-18 10:06:18,332 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 269 GetRequests, 218 SyntacticMatches, 0 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 698 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=465, Invalid=2291, Unknown=0, NotChecked=0, Total=2756 [2018-11-18 10:06:18,333 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 245 states. [2018-11-18 10:06:18,335 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 245 to 238. [2018-11-18 10:06:18,335 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 238 states. [2018-11-18 10:06:18,335 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 238 states to 238 states and 239 transitions. [2018-11-18 10:06:18,336 INFO L78 Accepts]: Start accepts. Automaton has 238 states and 239 transitions. Word has length 228 [2018-11-18 10:06:18,336 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:18,336 INFO L480 AbstractCegarLoop]: Abstraction has 238 states and 239 transitions. [2018-11-18 10:06:18,336 INFO L481 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-11-18 10:06:18,336 INFO L276 IsEmpty]: Start isEmpty. Operand 238 states and 239 transitions. [2018-11-18 10:06:18,338 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 235 [2018-11-18 10:06:18,338 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:18,339 INFO L375 BasicCegarLoop]: trace histogram [32, 27, 26, 26, 26, 26, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:18,339 INFO L423 AbstractCegarLoop]: === Iteration 24 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:18,339 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:18,339 INFO L82 PathProgramCache]: Analyzing trace with hash 2121953718, now seen corresponding path program 9 times [2018-11-18 10:06:18,339 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:18,339 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:18,340 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:18,340 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:06:18,340 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:18,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:18,484 INFO L134 CoverageAnalysis]: Checked inductivity of 2448 backedges. 909 proven. 91 refuted. 0 times theorem prover too weak. 1448 trivial. 0 not checked. [2018-11-18 10:06:18,484 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:06:18,484 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:06:18,491 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 10:06:18,536 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 7 check-sat command(s) [2018-11-18 10:06:18,536 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:06:18,539 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:06:18,628 INFO L134 CoverageAnalysis]: Checked inductivity of 2448 backedges. 850 proven. 108 refuted. 0 times theorem prover too weak. 1490 trivial. 0 not checked. [2018-11-18 10:06:18,644 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:06:18,644 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 9] total 21 [2018-11-18 10:06:18,644 INFO L459 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-11-18 10:06:18,644 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-11-18 10:06:18,644 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=79, Invalid=383, Unknown=0, NotChecked=0, Total=462 [2018-11-18 10:06:18,645 INFO L87 Difference]: Start difference. First operand 238 states and 239 transitions. Second operand 22 states. [2018-11-18 10:06:18,956 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:18,956 INFO L93 Difference]: Finished difference Result 312 states and 316 transitions. [2018-11-18 10:06:18,956 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-11-18 10:06:18,957 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 234 [2018-11-18 10:06:18,957 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:18,958 INFO L225 Difference]: With dead ends: 312 [2018-11-18 10:06:18,958 INFO L226 Difference]: Without dead ends: 312 [2018-11-18 10:06:18,958 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 261 GetRequests, 226 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 235 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=264, Invalid=1068, Unknown=0, NotChecked=0, Total=1332 [2018-11-18 10:06:18,959 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 312 states. [2018-11-18 10:06:18,961 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 312 to 293. [2018-11-18 10:06:18,961 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 293 states. [2018-11-18 10:06:18,962 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 293 states to 293 states and 296 transitions. [2018-11-18 10:06:18,962 INFO L78 Accepts]: Start accepts. Automaton has 293 states and 296 transitions. Word has length 234 [2018-11-18 10:06:18,963 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:18,963 INFO L480 AbstractCegarLoop]: Abstraction has 293 states and 296 transitions. [2018-11-18 10:06:18,963 INFO L481 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-11-18 10:06:18,963 INFO L276 IsEmpty]: Start isEmpty. Operand 293 states and 296 transitions. [2018-11-18 10:06:18,964 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 290 [2018-11-18 10:06:18,964 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:18,964 INFO L375 BasicCegarLoop]: trace histogram [40, 34, 33, 33, 33, 33, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:18,964 INFO L423 AbstractCegarLoop]: === Iteration 25 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:18,965 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:18,965 INFO L82 PathProgramCache]: Analyzing trace with hash 1623396665, now seen corresponding path program 10 times [2018-11-18 10:06:18,965 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:18,965 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:18,965 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:18,966 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:06:18,966 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:18,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:19,166 INFO L134 CoverageAnalysis]: Checked inductivity of 3894 backedges. 2002 proven. 402 refuted. 0 times theorem prover too weak. 1490 trivial. 0 not checked. [2018-11-18 10:06:19,167 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:06:19,167 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:06:19,176 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 10:06:19,221 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 10:06:19,221 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:06:19,225 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:06:19,475 INFO L134 CoverageAnalysis]: Checked inductivity of 3894 backedges. 2149 proven. 491 refuted. 0 times theorem prover too weak. 1254 trivial. 0 not checked. [2018-11-18 10:06:19,490 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:06:19,491 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 19] total 38 [2018-11-18 10:06:19,491 INFO L459 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-11-18 10:06:19,491 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-11-18 10:06:19,492 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=195, Invalid=1211, Unknown=0, NotChecked=0, Total=1406 [2018-11-18 10:06:19,492 INFO L87 Difference]: Start difference. First operand 293 states and 296 transitions. Second operand 38 states. [2018-11-18 10:06:20,198 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:20,198 INFO L93 Difference]: Finished difference Result 312 states and 313 transitions. [2018-11-18 10:06:20,198 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-11-18 10:06:20,198 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 289 [2018-11-18 10:06:20,199 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:20,200 INFO L225 Difference]: With dead ends: 312 [2018-11-18 10:06:20,200 INFO L226 Difference]: Without dead ends: 306 [2018-11-18 10:06:20,201 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 348 GetRequests, 275 SyntacticMatches, 0 SemanticMatches, 73 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1562 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=889, Invalid=4661, Unknown=0, NotChecked=0, Total=5550 [2018-11-18 10:06:20,201 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 306 states. [2018-11-18 10:06:20,203 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 306 to 299. [2018-11-18 10:06:20,203 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 299 states. [2018-11-18 10:06:20,204 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 299 states to 299 states and 300 transitions. [2018-11-18 10:06:20,205 INFO L78 Accepts]: Start accepts. Automaton has 299 states and 300 transitions. Word has length 289 [2018-11-18 10:06:20,205 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:20,205 INFO L480 AbstractCegarLoop]: Abstraction has 299 states and 300 transitions. [2018-11-18 10:06:20,205 INFO L481 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-11-18 10:06:20,205 INFO L276 IsEmpty]: Start isEmpty. Operand 299 states and 300 transitions. [2018-11-18 10:06:20,206 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 296 [2018-11-18 10:06:20,206 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:20,206 INFO L375 BasicCegarLoop]: trace histogram [41, 35, 34, 34, 34, 34, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:20,207 INFO L423 AbstractCegarLoop]: === Iteration 26 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:20,207 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:20,207 INFO L82 PathProgramCache]: Analyzing trace with hash 345701441, now seen corresponding path program 11 times [2018-11-18 10:06:20,207 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:20,207 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:20,207 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:20,208 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:06:20,208 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:20,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:20,331 INFO L134 CoverageAnalysis]: Checked inductivity of 4107 backedges. 1349 proven. 130 refuted. 0 times theorem prover too weak. 2628 trivial. 0 not checked. [2018-11-18 10:06:20,332 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:06:20,332 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:06:20,339 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-18 10:06:20,461 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 15 check-sat command(s) [2018-11-18 10:06:20,461 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:06:20,465 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:06:20,596 INFO L134 CoverageAnalysis]: Checked inductivity of 4107 backedges. 1311 proven. 147 refuted. 0 times theorem prover too weak. 2649 trivial. 0 not checked. [2018-11-18 10:06:20,612 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:06:20,612 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 10] total 22 [2018-11-18 10:06:20,612 INFO L459 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-11-18 10:06:20,612 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-11-18 10:06:20,613 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=75, Invalid=431, Unknown=0, NotChecked=0, Total=506 [2018-11-18 10:06:20,613 INFO L87 Difference]: Start difference. First operand 299 states and 300 transitions. Second operand 23 states. [2018-11-18 10:06:21,225 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:21,225 INFO L93 Difference]: Finished difference Result 383 states and 387 transitions. [2018-11-18 10:06:21,226 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-11-18 10:06:21,226 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 295 [2018-11-18 10:06:21,226 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:21,227 INFO L225 Difference]: With dead ends: 383 [2018-11-18 10:06:21,227 INFO L226 Difference]: Without dead ends: 383 [2018-11-18 10:06:21,228 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 318 GetRequests, 286 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 189 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=174, Invalid=948, Unknown=0, NotChecked=0, Total=1122 [2018-11-18 10:06:21,228 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 383 states. [2018-11-18 10:06:21,232 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 383 to 360. [2018-11-18 10:06:21,232 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 360 states. [2018-11-18 10:06:21,237 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 360 states to 360 states and 363 transitions. [2018-11-18 10:06:21,237 INFO L78 Accepts]: Start accepts. Automaton has 360 states and 363 transitions. Word has length 295 [2018-11-18 10:06:21,238 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:21,238 INFO L480 AbstractCegarLoop]: Abstraction has 360 states and 363 transitions. [2018-11-18 10:06:21,238 INFO L481 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-11-18 10:06:21,238 INFO L276 IsEmpty]: Start isEmpty. Operand 360 states and 363 transitions. [2018-11-18 10:06:21,239 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 357 [2018-11-18 10:06:21,239 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:21,239 INFO L375 BasicCegarLoop]: trace histogram [50, 43, 42, 42, 42, 42, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:21,240 INFO L423 AbstractCegarLoop]: === Iteration 27 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:21,240 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:21,240 INFO L82 PathProgramCache]: Analyzing trace with hash 627716678, now seen corresponding path program 12 times [2018-11-18 10:06:21,240 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:21,240 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:21,241 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:21,241 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:06:21,241 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:21,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:21,522 INFO L134 CoverageAnalysis]: Checked inductivity of 6195 backedges. 3015 proven. 531 refuted. 0 times theorem prover too weak. 2649 trivial. 0 not checked. [2018-11-18 10:06:21,522 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:06:21,523 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:06:21,529 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-18 10:06:21,664 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 17 check-sat command(s) [2018-11-18 10:06:21,664 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:06:21,668 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:06:21,983 INFO L134 CoverageAnalysis]: Checked inductivity of 6195 backedges. 2876 proven. 523 refuted. 0 times theorem prover too weak. 2796 trivial. 0 not checked. [2018-11-18 10:06:21,999 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:06:21,999 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 17] total 35 [2018-11-18 10:06:21,999 INFO L459 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-11-18 10:06:22,000 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-11-18 10:06:22,000 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=210, Invalid=980, Unknown=0, NotChecked=0, Total=1190 [2018-11-18 10:06:22,000 INFO L87 Difference]: Start difference. First operand 360 states and 363 transitions. Second operand 35 states. [2018-11-18 10:06:22,596 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:22,596 INFO L93 Difference]: Finished difference Result 440 states and 445 transitions. [2018-11-18 10:06:22,597 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-11-18 10:06:22,597 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 356 [2018-11-18 10:06:22,598 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:22,599 INFO L225 Difference]: With dead ends: 440 [2018-11-18 10:06:22,599 INFO L226 Difference]: Without dead ends: 440 [2018-11-18 10:06:22,600 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 404 GetRequests, 346 SyntacticMatches, 0 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 921 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=812, Invalid=2728, Unknown=0, NotChecked=0, Total=3540 [2018-11-18 10:06:22,600 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 440 states. [2018-11-18 10:06:22,607 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 440 to 433. [2018-11-18 10:06:22,607 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 433 states. [2018-11-18 10:06:22,608 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 433 states to 433 states and 438 transitions. [2018-11-18 10:06:22,609 INFO L78 Accepts]: Start accepts. Automaton has 433 states and 438 transitions. Word has length 356 [2018-11-18 10:06:22,610 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:22,610 INFO L480 AbstractCegarLoop]: Abstraction has 433 states and 438 transitions. [2018-11-18 10:06:22,610 INFO L481 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-11-18 10:06:22,610 INFO L276 IsEmpty]: Start isEmpty. Operand 433 states and 438 transitions. [2018-11-18 10:06:22,612 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 363 [2018-11-18 10:06:22,612 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:22,612 INFO L375 BasicCegarLoop]: trace histogram [51, 44, 43, 43, 43, 43, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:22,612 INFO L423 AbstractCegarLoop]: === Iteration 28 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:22,613 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:22,613 INFO L82 PathProgramCache]: Analyzing trace with hash -2025282674, now seen corresponding path program 13 times [2018-11-18 10:06:22,613 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:22,613 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:22,613 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:22,613 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:06:22,614 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:22,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:22,926 INFO L134 CoverageAnalysis]: Checked inductivity of 6464 backedges. 2102 proven. 176 refuted. 0 times theorem prover too weak. 4186 trivial. 0 not checked. [2018-11-18 10:06:22,926 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:06:22,926 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:06:22,939 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:06:23,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:23,023 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:06:23,164 INFO L134 CoverageAnalysis]: Checked inductivity of 6464 backedges. 1911 proven. 192 refuted. 0 times theorem prover too weak. 4361 trivial. 0 not checked. [2018-11-18 10:06:23,179 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:06:23,180 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 10] total 29 [2018-11-18 10:06:23,180 INFO L459 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-11-18 10:06:23,180 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-11-18 10:06:23,180 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=130, Invalid=740, Unknown=0, NotChecked=0, Total=870 [2018-11-18 10:06:23,181 INFO L87 Difference]: Start difference. First operand 433 states and 438 transitions. Second operand 30 states. [2018-11-18 10:06:23,721 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:23,721 INFO L93 Difference]: Finished difference Result 587 states and 598 transitions. [2018-11-18 10:06:23,722 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-11-18 10:06:23,722 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 362 [2018-11-18 10:06:23,722 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:23,723 INFO L225 Difference]: With dead ends: 587 [2018-11-18 10:06:23,723 INFO L226 Difference]: Without dead ends: 587 [2018-11-18 10:06:23,723 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 394 GetRequests, 353 SyntacticMatches, 1 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 331 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=261, Invalid=1461, Unknown=0, NotChecked=0, Total=1722 [2018-11-18 10:06:23,724 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 587 states. [2018-11-18 10:06:23,728 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 587 to 564. [2018-11-18 10:06:23,728 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 564 states. [2018-11-18 10:06:23,730 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 564 states to 564 states and 574 transitions. [2018-11-18 10:06:23,730 INFO L78 Accepts]: Start accepts. Automaton has 564 states and 574 transitions. Word has length 362 [2018-11-18 10:06:23,730 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:23,730 INFO L480 AbstractCegarLoop]: Abstraction has 564 states and 574 transitions. [2018-11-18 10:06:23,730 INFO L481 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-11-18 10:06:23,730 INFO L276 IsEmpty]: Start isEmpty. Operand 564 states and 574 transitions. [2018-11-18 10:06:23,732 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 424 [2018-11-18 10:06:23,732 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:23,732 INFO L375 BasicCegarLoop]: trace histogram [60, 52, 51, 51, 51, 51, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:23,732 INFO L423 AbstractCegarLoop]: === Iteration 29 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:23,732 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:23,732 INFO L82 PathProgramCache]: Analyzing trace with hash -328844263, now seen corresponding path program 14 times [2018-11-18 10:06:23,732 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:23,732 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:23,733 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:23,733 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:06:23,733 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:23,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:24,019 INFO L134 CoverageAnalysis]: Checked inductivity of 9031 backedges. 3759 proven. 956 refuted. 0 times theorem prover too weak. 4316 trivial. 0 not checked. [2018-11-18 10:06:24,019 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:06:24,019 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:06:24,028 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-18 10:06:24,090 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 10:06:24,091 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:06:24,095 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:06:24,364 INFO L134 CoverageAnalysis]: Checked inductivity of 9031 backedges. 5454 proven. 140 refuted. 0 times theorem prover too weak. 3437 trivial. 0 not checked. [2018-11-18 10:06:24,379 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:06:24,379 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 18] total 41 [2018-11-18 10:06:24,380 INFO L459 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-11-18 10:06:24,380 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-11-18 10:06:24,380 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=248, Invalid=1392, Unknown=0, NotChecked=0, Total=1640 [2018-11-18 10:06:24,380 INFO L87 Difference]: Start difference. First operand 564 states and 574 transitions. Second operand 41 states. [2018-11-18 10:06:25,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:25,068 INFO L93 Difference]: Finished difference Result 452 states and 455 transitions. [2018-11-18 10:06:25,068 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2018-11-18 10:06:25,068 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 423 [2018-11-18 10:06:25,069 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:25,070 INFO L225 Difference]: With dead ends: 452 [2018-11-18 10:06:25,070 INFO L226 Difference]: Without dead ends: 443 [2018-11-18 10:06:25,071 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 480 GetRequests, 409 SyntacticMatches, 0 SemanticMatches, 71 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1456 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=833, Invalid=4423, Unknown=0, NotChecked=0, Total=5256 [2018-11-18 10:06:25,071 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 443 states. [2018-11-18 10:06:25,075 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 443 to 439. [2018-11-18 10:06:25,075 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 439 states. [2018-11-18 10:06:25,076 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 439 states to 439 states and 442 transitions. [2018-11-18 10:06:25,076 INFO L78 Accepts]: Start accepts. Automaton has 439 states and 442 transitions. Word has length 423 [2018-11-18 10:06:25,077 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:25,077 INFO L480 AbstractCegarLoop]: Abstraction has 439 states and 442 transitions. [2018-11-18 10:06:25,077 INFO L481 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-11-18 10:06:25,077 INFO L276 IsEmpty]: Start isEmpty. Operand 439 states and 442 transitions. [2018-11-18 10:06:25,079 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 430 [2018-11-18 10:06:25,079 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:25,079 INFO L375 BasicCegarLoop]: trace histogram [61, 53, 52, 52, 52, 52, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:25,079 INFO L423 AbstractCegarLoop]: === Iteration 30 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:25,080 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:25,080 INFO L82 PathProgramCache]: Analyzing trace with hash 1360864721, now seen corresponding path program 15 times [2018-11-18 10:06:25,080 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:25,080 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:25,080 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:25,086 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:06:25,086 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:25,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:25,407 INFO L134 CoverageAnalysis]: Checked inductivity of 9356 backedges. 4317 proven. 678 refuted. 0 times theorem prover too weak. 4361 trivial. 0 not checked. [2018-11-18 10:06:25,407 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:06:25,407 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:06:25,416 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 10:06:25,507 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2018-11-18 10:06:25,507 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:06:25,512 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:06:25,835 INFO L134 CoverageAnalysis]: Checked inductivity of 9356 backedges. 4134 proven. 669 refuted. 0 times theorem prover too weak. 4553 trivial. 0 not checked. [2018-11-18 10:06:25,860 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:06:25,861 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 18] total 38 [2018-11-18 10:06:25,861 INFO L459 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-11-18 10:06:25,862 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-11-18 10:06:25,862 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=251, Invalid=1155, Unknown=0, NotChecked=0, Total=1406 [2018-11-18 10:06:25,862 INFO L87 Difference]: Start difference. First operand 439 states and 442 transitions. Second operand 38 states. [2018-11-18 10:06:26,472 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:26,472 INFO L93 Difference]: Finished difference Result 519 states and 524 transitions. [2018-11-18 10:06:26,473 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-11-18 10:06:26,473 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 429 [2018-11-18 10:06:26,473 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:26,475 INFO L225 Difference]: With dead ends: 519 [2018-11-18 10:06:26,475 INFO L226 Difference]: Without dead ends: 519 [2018-11-18 10:06:26,476 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 482 GetRequests, 418 SyntacticMatches, 0 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1145 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=989, Invalid=3301, Unknown=0, NotChecked=0, Total=4290 [2018-11-18 10:06:26,476 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 519 states. [2018-11-18 10:06:26,482 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 519 to 512. [2018-11-18 10:06:26,482 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 512 states. [2018-11-18 10:06:26,483 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 512 states to 512 states and 517 transitions. [2018-11-18 10:06:26,483 INFO L78 Accepts]: Start accepts. Automaton has 512 states and 517 transitions. Word has length 429 [2018-11-18 10:06:26,483 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:26,484 INFO L480 AbstractCegarLoop]: Abstraction has 512 states and 517 transitions. [2018-11-18 10:06:26,484 INFO L481 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-11-18 10:06:26,484 INFO L276 IsEmpty]: Start isEmpty. Operand 512 states and 517 transitions. [2018-11-18 10:06:26,486 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 436 [2018-11-18 10:06:26,486 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:26,486 INFO L375 BasicCegarLoop]: trace histogram [62, 54, 53, 53, 53, 53, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:26,486 INFO L423 AbstractCegarLoop]: === Iteration 31 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:26,487 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:26,487 INFO L82 PathProgramCache]: Analyzing trace with hash -51722535, now seen corresponding path program 16 times [2018-11-18 10:06:26,487 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:26,487 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:26,488 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:26,488 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:06:26,488 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:26,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:26,802 INFO L134 CoverageAnalysis]: Checked inductivity of 9687 backedges. 2718 proven. 229 refuted. 0 times theorem prover too weak. 6740 trivial. 0 not checked. [2018-11-18 10:06:26,802 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:06:26,802 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:06:26,815 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 10:06:26,973 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 10:06:26,973 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:06:26,979 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:06:27,173 INFO L134 CoverageAnalysis]: Checked inductivity of 9687 backedges. 2668 proven. 243 refuted. 0 times theorem prover too weak. 6776 trivial. 0 not checked. [2018-11-18 10:06:27,190 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:06:27,190 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 11] total 25 [2018-11-18 10:06:27,190 INFO L459 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-11-18 10:06:27,191 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-11-18 10:06:27,191 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=97, Invalid=553, Unknown=0, NotChecked=0, Total=650 [2018-11-18 10:06:27,191 INFO L87 Difference]: Start difference. First operand 512 states and 517 transitions. Second operand 26 states. [2018-11-18 10:06:27,777 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:27,778 INFO L93 Difference]: Finished difference Result 682 states and 693 transitions. [2018-11-18 10:06:27,778 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-11-18 10:06:27,778 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 435 [2018-11-18 10:06:27,779 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:27,780 INFO L225 Difference]: With dead ends: 682 [2018-11-18 10:06:27,780 INFO L226 Difference]: Without dead ends: 682 [2018-11-18 10:06:27,781 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 463 GetRequests, 425 SyntacticMatches, 0 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 250 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=223, Invalid=1337, Unknown=0, NotChecked=0, Total=1560 [2018-11-18 10:06:27,781 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 682 states. [2018-11-18 10:06:27,788 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 682 to 655. [2018-11-18 10:06:27,788 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 655 states. [2018-11-18 10:06:27,789 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 655 states to 655 states and 665 transitions. [2018-11-18 10:06:27,789 INFO L78 Accepts]: Start accepts. Automaton has 655 states and 665 transitions. Word has length 435 [2018-11-18 10:06:27,790 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:27,790 INFO L480 AbstractCegarLoop]: Abstraction has 655 states and 665 transitions. [2018-11-18 10:06:27,790 INFO L481 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-11-18 10:06:27,790 INFO L276 IsEmpty]: Start isEmpty. Operand 655 states and 665 transitions. [2018-11-18 10:06:27,793 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 503 [2018-11-18 10:06:27,793 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:27,793 INFO L375 BasicCegarLoop]: trace histogram [72, 63, 62, 62, 62, 62, 10, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:27,793 INFO L423 AbstractCegarLoop]: === Iteration 32 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:27,794 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:27,794 INFO L82 PathProgramCache]: Analyzing trace with hash -94038874, now seen corresponding path program 17 times [2018-11-18 10:06:27,794 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:27,794 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:27,794 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:27,795 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:06:27,795 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:27,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:28,242 INFO L134 CoverageAnalysis]: Checked inductivity of 13170 backedges. 5237 proven. 1209 refuted. 0 times theorem prover too weak. 6724 trivial. 0 not checked. [2018-11-18 10:06:28,243 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:06:28,243 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:06:28,253 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-18 10:06:28,460 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 23 check-sat command(s) [2018-11-18 10:06:28,460 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:06:28,467 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:06:28,869 INFO L134 CoverageAnalysis]: Checked inductivity of 13170 backedges. 7543 proven. 829 refuted. 0 times theorem prover too weak. 4798 trivial. 0 not checked. [2018-11-18 10:06:28,885 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:06:28,885 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 24] total 49 [2018-11-18 10:06:28,885 INFO L459 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-11-18 10:06:28,886 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-11-18 10:06:28,886 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=310, Invalid=2042, Unknown=0, NotChecked=0, Total=2352 [2018-11-18 10:06:28,886 INFO L87 Difference]: Start difference. First operand 655 states and 665 transitions. Second operand 49 states. [2018-11-18 10:06:29,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:29,932 INFO L93 Difference]: Finished difference Result 531 states and 534 transitions. [2018-11-18 10:06:29,932 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2018-11-18 10:06:29,932 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 502 [2018-11-18 10:06:29,933 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:29,934 INFO L225 Difference]: With dead ends: 531 [2018-11-18 10:06:29,934 INFO L226 Difference]: Without dead ends: 522 [2018-11-18 10:06:29,936 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 579 GetRequests, 483 SyntacticMatches, 0 SemanticMatches, 96 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2838 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=1460, Invalid=8046, Unknown=0, NotChecked=0, Total=9506 [2018-11-18 10:06:29,937 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 522 states. [2018-11-18 10:06:29,942 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 522 to 518. [2018-11-18 10:06:29,942 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 518 states. [2018-11-18 10:06:29,943 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 518 states to 518 states and 521 transitions. [2018-11-18 10:06:29,943 INFO L78 Accepts]: Start accepts. Automaton has 518 states and 521 transitions. Word has length 502 [2018-11-18 10:06:29,944 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:29,944 INFO L480 AbstractCegarLoop]: Abstraction has 518 states and 521 transitions. [2018-11-18 10:06:29,944 INFO L481 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-11-18 10:06:29,944 INFO L276 IsEmpty]: Start isEmpty. Operand 518 states and 521 transitions. [2018-11-18 10:06:29,946 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 509 [2018-11-18 10:06:29,946 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:29,946 INFO L375 BasicCegarLoop]: trace histogram [73, 64, 63, 63, 63, 63, 10, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:29,947 INFO L423 AbstractCegarLoop]: === Iteration 33 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:29,947 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:29,947 INFO L82 PathProgramCache]: Analyzing trace with hash 225205406, now seen corresponding path program 18 times [2018-11-18 10:06:29,947 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:29,947 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:29,948 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:29,948 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:06:29,948 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:29,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:30,288 INFO L134 CoverageAnalysis]: Checked inductivity of 13563 backedges. 5944 proven. 843 refuted. 0 times theorem prover too weak. 6776 trivial. 0 not checked. [2018-11-18 10:06:30,288 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:06:30,288 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:06:30,294 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-18 10:06:30,544 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 21 check-sat command(s) [2018-11-18 10:06:30,544 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:06:30,549 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:06:30,799 INFO L134 CoverageAnalysis]: Checked inductivity of 13563 backedges. 5711 proven. 833 refuted. 0 times theorem prover too weak. 7019 trivial. 0 not checked. [2018-11-18 10:06:30,814 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:06:30,814 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 19] total 41 [2018-11-18 10:06:30,815 INFO L459 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-11-18 10:06:30,815 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-11-18 10:06:30,815 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=296, Invalid=1344, Unknown=0, NotChecked=0, Total=1640 [2018-11-18 10:06:30,815 INFO L87 Difference]: Start difference. First operand 518 states and 521 transitions. Second operand 41 states. [2018-11-18 10:06:31,462 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:31,462 INFO L93 Difference]: Finished difference Result 604 states and 609 transitions. [2018-11-18 10:06:31,462 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-11-18 10:06:31,462 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 508 [2018-11-18 10:06:31,462 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:31,463 INFO L225 Difference]: With dead ends: 604 [2018-11-18 10:06:31,463 INFO L226 Difference]: Without dead ends: 604 [2018-11-18 10:06:31,464 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 566 GetRequests, 496 SyntacticMatches, 0 SemanticMatches, 70 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1393 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1184, Invalid=3928, Unknown=0, NotChecked=0, Total=5112 [2018-11-18 10:06:31,464 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 604 states. [2018-11-18 10:06:31,469 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 604 to 597. [2018-11-18 10:06:31,469 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 597 states. [2018-11-18 10:06:31,470 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 597 states to 597 states and 602 transitions. [2018-11-18 10:06:31,470 INFO L78 Accepts]: Start accepts. Automaton has 597 states and 602 transitions. Word has length 508 [2018-11-18 10:06:31,471 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:31,471 INFO L480 AbstractCegarLoop]: Abstraction has 597 states and 602 transitions. [2018-11-18 10:06:31,471 INFO L481 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-11-18 10:06:31,471 INFO L276 IsEmpty]: Start isEmpty. Operand 597 states and 602 transitions. [2018-11-18 10:06:31,474 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 515 [2018-11-18 10:06:31,474 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:31,474 INFO L375 BasicCegarLoop]: trace histogram [74, 65, 64, 64, 64, 64, 10, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:31,474 INFO L423 AbstractCegarLoop]: === Iteration 34 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:31,474 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:31,475 INFO L82 PathProgramCache]: Analyzing trace with hash 193147878, now seen corresponding path program 19 times [2018-11-18 10:06:31,475 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:31,475 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:31,475 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:31,475 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:06:31,475 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:31,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:31,752 INFO L134 CoverageAnalysis]: Checked inductivity of 13962 backedges. 3707 proven. 289 refuted. 0 times theorem prover too weak. 9966 trivial. 0 not checked. [2018-11-18 10:06:31,752 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:06:31,752 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:06:31,759 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:06:31,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:31,844 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:06:32,064 INFO L134 CoverageAnalysis]: Checked inductivity of 13962 backedges. 3600 proven. 300 refuted. 0 times theorem prover too weak. 10062 trivial. 0 not checked. [2018-11-18 10:06:32,079 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:06:32,080 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 12] total 28 [2018-11-18 10:06:32,080 INFO L459 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-11-18 10:06:32,080 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-11-18 10:06:32,080 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=115, Invalid=697, Unknown=0, NotChecked=0, Total=812 [2018-11-18 10:06:32,080 INFO L87 Difference]: Start difference. First operand 597 states and 602 transitions. Second operand 29 states. [2018-11-18 10:06:32,733 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:32,733 INFO L93 Difference]: Finished difference Result 779 states and 790 transitions. [2018-11-18 10:06:32,733 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-11-18 10:06:32,734 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 514 [2018-11-18 10:06:32,734 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:32,735 INFO L225 Difference]: With dead ends: 779 [2018-11-18 10:06:32,735 INFO L226 Difference]: Without dead ends: 779 [2018-11-18 10:06:32,735 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 545 GetRequests, 503 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 321 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=261, Invalid=1631, Unknown=0, NotChecked=0, Total=1892 [2018-11-18 10:06:32,735 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 779 states. [2018-11-18 10:06:32,741 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 779 to 752. [2018-11-18 10:06:32,741 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 752 states. [2018-11-18 10:06:32,742 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 752 states to 752 states and 762 transitions. [2018-11-18 10:06:32,742 INFO L78 Accepts]: Start accepts. Automaton has 752 states and 762 transitions. Word has length 514 [2018-11-18 10:06:32,742 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:32,743 INFO L480 AbstractCegarLoop]: Abstraction has 752 states and 762 transitions. [2018-11-18 10:06:32,743 INFO L481 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-11-18 10:06:32,743 INFO L276 IsEmpty]: Start isEmpty. Operand 752 states and 762 transitions. [2018-11-18 10:06:32,746 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 588 [2018-11-18 10:06:32,746 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:32,746 INFO L375 BasicCegarLoop]: trace histogram [85, 75, 74, 74, 74, 74, 11, 11, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:32,747 INFO L423 AbstractCegarLoop]: === Iteration 35 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:32,747 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:32,747 INFO L82 PathProgramCache]: Analyzing trace with hash -1182172111, now seen corresponding path program 20 times [2018-11-18 10:06:32,747 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:32,747 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:32,747 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:32,748 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:06:32,748 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:32,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:33,130 INFO L134 CoverageAnalysis]: Checked inductivity of 18553 backedges. 7058 proven. 1492 refuted. 0 times theorem prover too weak. 10003 trivial. 0 not checked. [2018-11-18 10:06:33,130 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:06:33,130 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:06:33,136 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-18 10:06:33,222 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 10:06:33,222 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:06:33,227 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:06:33,681 INFO L134 CoverageAnalysis]: Checked inductivity of 18553 backedges. 10388 proven. 234 refuted. 0 times theorem prover too weak. 7931 trivial. 0 not checked. [2018-11-18 10:06:33,696 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:06:33,697 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 22] total 49 [2018-11-18 10:06:33,697 INFO L459 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-11-18 10:06:33,697 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-11-18 10:06:33,698 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=355, Invalid=1997, Unknown=0, NotChecked=0, Total=2352 [2018-11-18 10:06:33,698 INFO L87 Difference]: Start difference. First operand 752 states and 762 transitions. Second operand 49 states. [2018-11-18 10:06:34,492 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:34,492 INFO L93 Difference]: Finished difference Result 616 states and 619 transitions. [2018-11-18 10:06:34,493 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2018-11-18 10:06:34,493 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 587 [2018-11-18 10:06:34,493 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:34,494 INFO L225 Difference]: With dead ends: 616 [2018-11-18 10:06:34,494 INFO L226 Difference]: Without dead ends: 607 [2018-11-18 10:06:34,495 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 656 GetRequests, 569 SyntacticMatches, 0 SemanticMatches, 87 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2264 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=1220, Invalid=6612, Unknown=0, NotChecked=0, Total=7832 [2018-11-18 10:06:34,496 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 607 states. [2018-11-18 10:06:34,500 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 607 to 603. [2018-11-18 10:06:34,500 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 603 states. [2018-11-18 10:06:34,501 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 603 states to 603 states and 606 transitions. [2018-11-18 10:06:34,502 INFO L78 Accepts]: Start accepts. Automaton has 603 states and 606 transitions. Word has length 587 [2018-11-18 10:06:34,502 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:34,502 INFO L480 AbstractCegarLoop]: Abstraction has 603 states and 606 transitions. [2018-11-18 10:06:34,502 INFO L481 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-11-18 10:06:34,502 INFO L276 IsEmpty]: Start isEmpty. Operand 603 states and 606 transitions. [2018-11-18 10:06:34,505 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 594 [2018-11-18 10:06:34,506 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:34,506 INFO L375 BasicCegarLoop]: trace histogram [86, 76, 75, 75, 75, 75, 11, 11, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:34,506 INFO L423 AbstractCegarLoop]: === Iteration 36 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:34,506 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:34,506 INFO L82 PathProgramCache]: Analyzing trace with hash -1816761367, now seen corresponding path program 21 times [2018-11-18 10:06:34,506 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:34,507 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:34,507 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:34,507 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:06:34,507 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:34,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:34,938 INFO L134 CoverageAnalysis]: Checked inductivity of 19020 backedges. 7932 proven. 1026 refuted. 0 times theorem prover too weak. 10062 trivial. 0 not checked. [2018-11-18 10:06:34,938 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:06:34,938 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:06:34,944 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 10:06:35,071 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2018-11-18 10:06:35,071 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:06:35,076 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:06:35,378 INFO L134 CoverageAnalysis]: Checked inductivity of 19020 backedges. 7643 proven. 1015 refuted. 0 times theorem prover too weak. 10362 trivial. 0 not checked. [2018-11-18 10:06:35,394 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:06:35,394 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 20] total 44 [2018-11-18 10:06:35,394 INFO L459 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-11-18 10:06:35,395 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-11-18 10:06:35,395 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=345, Invalid=1547, Unknown=0, NotChecked=0, Total=1892 [2018-11-18 10:06:35,395 INFO L87 Difference]: Start difference. First operand 603 states and 606 transitions. Second operand 44 states. [2018-11-18 10:06:36,119 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:36,120 INFO L93 Difference]: Finished difference Result 695 states and 700 transitions. [2018-11-18 10:06:36,120 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2018-11-18 10:06:36,120 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 593 [2018-11-18 10:06:36,120 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:36,121 INFO L225 Difference]: With dead ends: 695 [2018-11-18 10:06:36,121 INFO L226 Difference]: Without dead ends: 695 [2018-11-18 10:06:36,122 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 656 GetRequests, 580 SyntacticMatches, 0 SemanticMatches, 76 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1665 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1397, Invalid=4609, Unknown=0, NotChecked=0, Total=6006 [2018-11-18 10:06:36,122 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 695 states. [2018-11-18 10:06:36,127 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 695 to 688. [2018-11-18 10:06:36,127 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 688 states. [2018-11-18 10:06:36,128 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 688 states to 688 states and 693 transitions. [2018-11-18 10:06:36,128 INFO L78 Accepts]: Start accepts. Automaton has 688 states and 693 transitions. Word has length 593 [2018-11-18 10:06:36,129 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:36,129 INFO L480 AbstractCegarLoop]: Abstraction has 688 states and 693 transitions. [2018-11-18 10:06:36,129 INFO L481 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-11-18 10:06:36,129 INFO L276 IsEmpty]: Start isEmpty. Operand 688 states and 693 transitions. [2018-11-18 10:06:36,132 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 600 [2018-11-18 10:06:36,133 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:36,133 INFO L375 BasicCegarLoop]: trace histogram [87, 77, 76, 76, 76, 76, 11, 11, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:36,133 INFO L423 AbstractCegarLoop]: === Iteration 37 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:36,133 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:36,133 INFO L82 PathProgramCache]: Analyzing trace with hash 1117954801, now seen corresponding path program 22 times [2018-11-18 10:06:36,133 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:36,134 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:36,134 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:36,134 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:06:36,134 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:36,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:36,440 INFO L134 CoverageAnalysis]: Checked inductivity of 19493 backedges. 4787 proven. 356 refuted. 0 times theorem prover too weak. 14350 trivial. 0 not checked. [2018-11-18 10:06:36,440 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:06:36,440 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:06:36,449 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 10:06:36,608 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 10:06:36,608 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:06:36,613 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:06:36,818 INFO L134 CoverageAnalysis]: Checked inductivity of 19493 backedges. 4725 proven. 363 refuted. 0 times theorem prover too weak. 14405 trivial. 0 not checked. [2018-11-18 10:06:36,834 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:06:36,834 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 13] total 29 [2018-11-18 10:06:36,835 INFO L459 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-11-18 10:06:36,835 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-11-18 10:06:36,835 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=126, Invalid=744, Unknown=0, NotChecked=0, Total=870 [2018-11-18 10:06:36,835 INFO L87 Difference]: Start difference. First operand 688 states and 693 transitions. Second operand 30 states. [2018-11-18 10:06:37,694 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:37,694 INFO L93 Difference]: Finished difference Result 882 states and 893 transitions. [2018-11-18 10:06:37,695 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2018-11-18 10:06:37,695 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 599 [2018-11-18 10:06:37,695 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:37,697 INFO L225 Difference]: With dead ends: 882 [2018-11-18 10:06:37,697 INFO L226 Difference]: Without dead ends: 882 [2018-11-18 10:06:37,697 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 631 GetRequests, 587 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 337 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=272, Invalid=1798, Unknown=0, NotChecked=0, Total=2070 [2018-11-18 10:06:37,698 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 882 states. [2018-11-18 10:06:37,703 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 882 to 855. [2018-11-18 10:06:37,703 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 855 states. [2018-11-18 10:06:37,705 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 855 states to 855 states and 865 transitions. [2018-11-18 10:06:37,705 INFO L78 Accepts]: Start accepts. Automaton has 855 states and 865 transitions. Word has length 599 [2018-11-18 10:06:37,705 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:37,705 INFO L480 AbstractCegarLoop]: Abstraction has 855 states and 865 transitions. [2018-11-18 10:06:37,705 INFO L481 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-11-18 10:06:37,705 INFO L276 IsEmpty]: Start isEmpty. Operand 855 states and 865 transitions. [2018-11-18 10:06:37,709 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 679 [2018-11-18 10:06:37,709 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:37,709 INFO L375 BasicCegarLoop]: trace histogram [99, 88, 87, 87, 87, 87, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:37,709 INFO L423 AbstractCegarLoop]: === Iteration 38 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:37,709 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:37,710 INFO L82 PathProgramCache]: Analyzing trace with hash -160692354, now seen corresponding path program 23 times [2018-11-18 10:06:37,710 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:37,710 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:37,710 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:37,710 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:06:37,711 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:37,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:38,196 INFO L134 CoverageAnalysis]: Checked inductivity of 25402 backedges. 9258 proven. 1805 refuted. 0 times theorem prover too weak. 14339 trivial. 0 not checked. [2018-11-18 10:06:38,196 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:06:38,196 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:06:38,214 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-18 10:06:38,514 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 25 check-sat command(s) [2018-11-18 10:06:38,514 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:06:38,521 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:06:39,096 INFO L134 CoverageAnalysis]: Checked inductivity of 25402 backedges. 13533 proven. 1572 refuted. 0 times theorem prover too weak. 10297 trivial. 0 not checked. [2018-11-18 10:06:39,112 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:06:39,112 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 28] total 57 [2018-11-18 10:06:39,112 INFO L459 AbstractCegarLoop]: Interpolant automaton has 57 states [2018-11-18 10:06:39,113 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2018-11-18 10:06:39,113 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=421, Invalid=2771, Unknown=0, NotChecked=0, Total=3192 [2018-11-18 10:06:39,113 INFO L87 Difference]: Start difference. First operand 855 states and 865 transitions. Second operand 57 states. [2018-11-18 10:06:40,498 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:40,499 INFO L93 Difference]: Finished difference Result 707 states and 710 transitions. [2018-11-18 10:06:40,499 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 67 states. [2018-11-18 10:06:40,499 INFO L78 Accepts]: Start accepts. Automaton has 57 states. Word has length 678 [2018-11-18 10:06:40,499 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:40,500 INFO L225 Difference]: With dead ends: 707 [2018-11-18 10:06:40,500 INFO L226 Difference]: Without dead ends: 698 [2018-11-18 10:06:40,501 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 769 GetRequests, 655 SyntacticMatches, 0 SemanticMatches, 114 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4080 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=1990, Invalid=11350, Unknown=0, NotChecked=0, Total=13340 [2018-11-18 10:06:40,501 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 698 states. [2018-11-18 10:06:40,504 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 698 to 694. [2018-11-18 10:06:40,504 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 694 states. [2018-11-18 10:06:40,505 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 694 states to 694 states and 697 transitions. [2018-11-18 10:06:40,505 INFO L78 Accepts]: Start accepts. Automaton has 694 states and 697 transitions. Word has length 678 [2018-11-18 10:06:40,506 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:40,506 INFO L480 AbstractCegarLoop]: Abstraction has 694 states and 697 transitions. [2018-11-18 10:06:40,506 INFO L481 AbstractCegarLoop]: Interpolant automaton has 57 states. [2018-11-18 10:06:40,506 INFO L276 IsEmpty]: Start isEmpty. Operand 694 states and 697 transitions. [2018-11-18 10:06:40,510 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 685 [2018-11-18 10:06:40,510 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:40,510 INFO L375 BasicCegarLoop]: trace histogram [100, 89, 88, 88, 88, 88, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:40,510 INFO L423 AbstractCegarLoop]: === Iteration 39 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:40,511 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:40,511 INFO L82 PathProgramCache]: Analyzing trace with hash 1163543926, now seen corresponding path program 24 times [2018-11-18 10:06:40,511 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:40,511 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:40,511 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:40,512 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:06:40,512 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:40,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:40,982 INFO L134 CoverageAnalysis]: Checked inductivity of 25949 backedges. 10317 proven. 1227 refuted. 0 times theorem prover too weak. 14405 trivial. 0 not checked. [2018-11-18 10:06:40,982 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:06:40,982 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:06:40,988 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-18 10:06:41,404 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 22 check-sat command(s) [2018-11-18 10:06:41,404 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:06:41,410 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:06:41,739 INFO L134 CoverageAnalysis]: Checked inductivity of 25949 backedges. 6054 proven. 430 refuted. 0 times theorem prover too weak. 19465 trivial. 0 not checked. [2018-11-18 10:06:41,755 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:06:41,755 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 18] total 47 [2018-11-18 10:06:41,756 INFO L459 AbstractCegarLoop]: Interpolant automaton has 47 states [2018-11-18 10:06:41,756 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2018-11-18 10:06:41,756 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=309, Invalid=1853, Unknown=0, NotChecked=0, Total=2162 [2018-11-18 10:06:41,756 INFO L87 Difference]: Start difference. First operand 694 states and 697 transitions. Second operand 47 states. [2018-11-18 10:06:43,304 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:43,304 INFO L93 Difference]: Finished difference Result 889 states and 895 transitions. [2018-11-18 10:06:43,305 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 110 states. [2018-11-18 10:06:43,305 INFO L78 Accepts]: Start accepts. Automaton has 47 states. Word has length 684 [2018-11-18 10:06:43,305 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:43,307 INFO L225 Difference]: With dead ends: 889 [2018-11-18 10:06:43,307 INFO L226 Difference]: Without dead ends: 889 [2018-11-18 10:06:43,308 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 796 GetRequests, 670 SyntacticMatches, 0 SemanticMatches, 126 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5115 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=2562, Invalid=13694, Unknown=0, NotChecked=0, Total=16256 [2018-11-18 10:06:43,309 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 889 states. [2018-11-18 10:06:43,315 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 889 to 794. [2018-11-18 10:06:43,315 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 794 states. [2018-11-18 10:06:43,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 794 states to 794 states and 799 transitions. [2018-11-18 10:06:43,318 INFO L78 Accepts]: Start accepts. Automaton has 794 states and 799 transitions. Word has length 684 [2018-11-18 10:06:43,318 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:43,318 INFO L480 AbstractCegarLoop]: Abstraction has 794 states and 799 transitions. [2018-11-18 10:06:43,318 INFO L481 AbstractCegarLoop]: Interpolant automaton has 47 states. [2018-11-18 10:06:43,318 INFO L276 IsEmpty]: Start isEmpty. Operand 794 states and 799 transitions. [2018-11-18 10:06:43,323 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 776 [2018-11-18 10:06:43,323 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:43,323 INFO L375 BasicCegarLoop]: trace histogram [114, 102, 101, 101, 101, 101, 13, 13, 13, 13, 12, 12, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:43,324 INFO L423 AbstractCegarLoop]: === Iteration 40 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:43,324 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:43,324 INFO L82 PathProgramCache]: Analyzing trace with hash -1901592631, now seen corresponding path program 25 times [2018-11-18 10:06:43,324 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:43,324 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:43,325 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:43,325 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:06:43,325 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:43,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:43,902 INFO L134 CoverageAnalysis]: Checked inductivity of 33957 backedges. 13337 proven. 1747 refuted. 0 times theorem prover too weak. 18873 trivial. 0 not checked. [2018-11-18 10:06:43,902 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:06:43,902 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:06:43,909 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:06:44,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:44,014 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:06:44,383 INFO L134 CoverageAnalysis]: Checked inductivity of 33957 backedges. 13514 proven. 420 refuted. 0 times theorem prover too weak. 20023 trivial. 0 not checked. [2018-11-18 10:06:44,399 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:06:44,399 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 28] total 45 [2018-11-18 10:06:44,400 INFO L459 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-11-18 10:06:44,400 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-11-18 10:06:44,400 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=413, Invalid=1567, Unknown=0, NotChecked=0, Total=1980 [2018-11-18 10:06:44,400 INFO L87 Difference]: Start difference. First operand 794 states and 799 transitions. Second operand 45 states. [2018-11-18 10:06:44,908 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:44,908 INFO L93 Difference]: Finished difference Result 816 states and 818 transitions. [2018-11-18 10:06:44,908 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2018-11-18 10:06:44,908 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 775 [2018-11-18 10:06:44,909 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:44,910 INFO L225 Difference]: With dead ends: 816 [2018-11-18 10:06:44,910 INFO L226 Difference]: Without dead ends: 794 [2018-11-18 10:06:44,911 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 832 GetRequests, 764 SyntacticMatches, 0 SemanticMatches, 68 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1443 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1097, Invalid=3733, Unknown=0, NotChecked=0, Total=4830 [2018-11-18 10:06:44,911 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 794 states. [2018-11-18 10:06:44,915 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 794 to 791. [2018-11-18 10:06:44,915 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 791 states. [2018-11-18 10:06:44,916 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 791 states to 791 states and 792 transitions. [2018-11-18 10:06:44,916 INFO L78 Accepts]: Start accepts. Automaton has 791 states and 792 transitions. Word has length 775 [2018-11-18 10:06:44,917 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:44,917 INFO L480 AbstractCegarLoop]: Abstraction has 791 states and 792 transitions. [2018-11-18 10:06:44,917 INFO L481 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-11-18 10:06:44,917 INFO L276 IsEmpty]: Start isEmpty. Operand 791 states and 792 transitions. [2018-11-18 10:06:44,921 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 788 [2018-11-18 10:06:44,921 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:44,921 INFO L375 BasicCegarLoop]: trace histogram [116, 104, 103, 103, 103, 103, 13, 13, 13, 13, 12, 12, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:44,921 INFO L423 AbstractCegarLoop]: === Iteration 41 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:44,921 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:44,921 INFO L82 PathProgramCache]: Analyzing trace with hash 563564681, now seen corresponding path program 26 times [2018-11-18 10:06:44,921 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:44,922 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:44,922 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:44,922 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:06:44,922 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:44,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:45,270 INFO L134 CoverageAnalysis]: Checked inductivity of 35229 backedges. 7700 proven. 511 refuted. 0 times theorem prover too weak. 27018 trivial. 0 not checked. [2018-11-18 10:06:45,270 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:06:45,271 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:06:45,281 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-18 10:06:45,412 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 10:06:45,412 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:06:45,419 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:06:45,715 INFO L134 CoverageAnalysis]: Checked inductivity of 35229 backedges. 7626 proven. 507 refuted. 0 times theorem prover too weak. 27096 trivial. 0 not checked. [2018-11-18 10:06:45,730 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:06:45,731 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 15] total 33 [2018-11-18 10:06:45,731 INFO L459 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-11-18 10:06:45,731 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-11-18 10:06:45,731 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=159, Invalid=963, Unknown=0, NotChecked=0, Total=1122 [2018-11-18 10:06:45,731 INFO L87 Difference]: Start difference. First operand 791 states and 792 transitions. Second operand 34 states. [2018-11-18 10:06:46,736 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:46,736 INFO L93 Difference]: Finished difference Result 911 states and 915 transitions. [2018-11-18 10:06:46,736 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-11-18 10:06:46,736 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 787 [2018-11-18 10:06:46,737 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:46,738 INFO L225 Difference]: With dead ends: 911 [2018-11-18 10:06:46,738 INFO L226 Difference]: Without dead ends: 911 [2018-11-18 10:06:46,738 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 822 GetRequests, 773 SyntacticMatches, 0 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 419 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=317, Invalid=2233, Unknown=0, NotChecked=0, Total=2550 [2018-11-18 10:06:46,738 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 911 states. [2018-11-18 10:06:46,742 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 911 to 888. [2018-11-18 10:06:46,742 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 888 states. [2018-11-18 10:06:46,743 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 888 states to 888 states and 891 transitions. [2018-11-18 10:06:46,743 INFO L78 Accepts]: Start accepts. Automaton has 888 states and 891 transitions. Word has length 787 [2018-11-18 10:06:46,743 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:46,743 INFO L480 AbstractCegarLoop]: Abstraction has 888 states and 891 transitions. [2018-11-18 10:06:46,743 INFO L481 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-11-18 10:06:46,743 INFO L276 IsEmpty]: Start isEmpty. Operand 888 states and 891 transitions. [2018-11-18 10:06:46,746 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 885 [2018-11-18 10:06:46,746 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:46,747 INFO L375 BasicCegarLoop]: trace histogram [131, 118, 117, 117, 117, 117, 14, 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:46,747 INFO L423 AbstractCegarLoop]: === Iteration 42 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:46,747 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:46,747 INFO L82 PathProgramCache]: Analyzing trace with hash 289664206, now seen corresponding path program 27 times [2018-11-18 10:06:46,747 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:46,747 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:46,747 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:46,748 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:06:46,748 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:46,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:47,379 INFO L134 CoverageAnalysis]: Checked inductivity of 45201 backedges. 16422 proven. 1683 refuted. 0 times theorem prover too weak. 27096 trivial. 0 not checked. [2018-11-18 10:06:47,379 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:06:47,379 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:06:47,386 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 10:06:47,564 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2018-11-18 10:06:47,564 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:06:47,569 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:06:48,036 INFO L134 CoverageAnalysis]: Checked inductivity of 45201 backedges. 15929 proven. 1669 refuted. 0 times theorem prover too weak. 27603 trivial. 0 not checked. [2018-11-18 10:06:48,051 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:06:48,052 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 23] total 53 [2018-11-18 10:06:48,052 INFO L459 AbstractCegarLoop]: Interpolant automaton has 53 states [2018-11-18 10:06:48,052 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2018-11-18 10:06:48,052 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=516, Invalid=2240, Unknown=0, NotChecked=0, Total=2756 [2018-11-18 10:06:48,053 INFO L87 Difference]: Start difference. First operand 888 states and 891 transitions. Second operand 53 states. [2018-11-18 10:06:49,056 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:49,056 INFO L93 Difference]: Finished difference Result 1004 states and 1009 transitions. [2018-11-18 10:06:49,056 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-11-18 10:06:49,056 INFO L78 Accepts]: Start accepts. Automaton has 53 states. Word has length 884 [2018-11-18 10:06:49,057 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:49,058 INFO L225 Difference]: With dead ends: 1004 [2018-11-18 10:06:49,058 INFO L226 Difference]: Without dead ends: 1004 [2018-11-18 10:06:49,059 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 962 GetRequests, 868 SyntacticMatches, 0 SemanticMatches, 94 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2625 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=2144, Invalid=6976, Unknown=0, NotChecked=0, Total=9120 [2018-11-18 10:06:49,059 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1004 states. [2018-11-18 10:06:49,063 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1004 to 997. [2018-11-18 10:06:49,063 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 997 states. [2018-11-18 10:06:49,065 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 997 states to 997 states and 1002 transitions. [2018-11-18 10:06:49,065 INFO L78 Accepts]: Start accepts. Automaton has 997 states and 1002 transitions. Word has length 884 [2018-11-18 10:06:49,065 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:49,066 INFO L480 AbstractCegarLoop]: Abstraction has 997 states and 1002 transitions. [2018-11-18 10:06:49,066 INFO L481 AbstractCegarLoop]: Interpolant automaton has 53 states. [2018-11-18 10:06:49,066 INFO L276 IsEmpty]: Start isEmpty. Operand 997 states and 1002 transitions. [2018-11-18 10:06:49,070 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 891 [2018-11-18 10:06:49,070 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:49,070 INFO L375 BasicCegarLoop]: trace histogram [132, 119, 118, 118, 118, 118, 14, 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:49,070 INFO L423 AbstractCegarLoop]: === Iteration 43 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:49,070 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:49,070 INFO L82 PathProgramCache]: Analyzing trace with hash 321712150, now seen corresponding path program 28 times [2018-11-18 10:06:49,071 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:49,071 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:49,071 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:49,071 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:06:49,071 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:49,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:49,554 INFO L134 CoverageAnalysis]: Checked inductivity of 45932 backedges. 9593 proven. 599 refuted. 0 times theorem prover too weak. 35740 trivial. 0 not checked. [2018-11-18 10:06:49,554 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:06:49,554 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:06:49,561 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 10:06:49,737 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 10:06:49,737 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:06:49,745 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:06:50,095 INFO L134 CoverageAnalysis]: Checked inductivity of 45932 backedges. 9438 proven. 588 refuted. 0 times theorem prover too weak. 35906 trivial. 0 not checked. [2018-11-18 10:06:50,112 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:06:50,112 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 16] total 36 [2018-11-18 10:06:50,112 INFO L459 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-11-18 10:06:50,113 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-11-18 10:06:50,113 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=181, Invalid=1151, Unknown=0, NotChecked=0, Total=1332 [2018-11-18 10:06:50,113 INFO L87 Difference]: Start difference. First operand 997 states and 1002 transitions. Second operand 37 states. [2018-11-18 10:06:51,220 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:51,220 INFO L93 Difference]: Finished difference Result 1227 states and 1238 transitions. [2018-11-18 10:06:51,220 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-11-18 10:06:51,220 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 890 [2018-11-18 10:06:51,221 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:51,222 INFO L225 Difference]: With dead ends: 1227 [2018-11-18 10:06:51,222 INFO L226 Difference]: Without dead ends: 1227 [2018-11-18 10:06:51,223 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 929 GetRequests, 875 SyntacticMatches, 0 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 531 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=371, Invalid=2709, Unknown=0, NotChecked=0, Total=3080 [2018-11-18 10:06:51,223 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1227 states. [2018-11-18 10:06:51,229 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1227 to 1200. [2018-11-18 10:06:51,229 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1200 states. [2018-11-18 10:06:51,231 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1200 states to 1200 states and 1210 transitions. [2018-11-18 10:06:51,231 INFO L78 Accepts]: Start accepts. Automaton has 1200 states and 1210 transitions. Word has length 890 [2018-11-18 10:06:51,232 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:51,232 INFO L480 AbstractCegarLoop]: Abstraction has 1200 states and 1210 transitions. [2018-11-18 10:06:51,232 INFO L481 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-11-18 10:06:51,232 INFO L276 IsEmpty]: Start isEmpty. Operand 1200 states and 1210 transitions. [2018-11-18 10:06:51,238 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 988 [2018-11-18 10:06:51,239 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:51,239 INFO L375 BasicCegarLoop]: trace histogram [147, 133, 132, 132, 132, 132, 15, 15, 15, 15, 14, 14, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:51,239 INFO L423 AbstractCegarLoop]: === Iteration 44 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:51,239 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:51,239 INFO L82 PathProgramCache]: Analyzing trace with hash -1912049439, now seen corresponding path program 29 times [2018-11-18 10:06:51,239 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:51,239 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:51,240 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:51,240 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:06:51,240 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:51,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:51,978 INFO L134 CoverageAnalysis]: Checked inductivity of 57235 backedges. 18492 proven. 2924 refuted. 0 times theorem prover too weak. 35819 trivial. 0 not checked. [2018-11-18 10:06:51,978 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:06:51,978 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:06:51,984 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-18 10:06:52,739 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 29 check-sat command(s) [2018-11-18 10:06:52,739 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:06:52,749 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:06:53,570 INFO L134 CoverageAnalysis]: Checked inductivity of 57235 backedges. 27339 proven. 2589 refuted. 0 times theorem prover too weak. 27307 trivial. 0 not checked. [2018-11-18 10:06:53,587 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:06:53,588 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 34] total 69 [2018-11-18 10:06:53,588 INFO L459 AbstractCegarLoop]: Interpolant automaton has 69 states [2018-11-18 10:06:53,588 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2018-11-18 10:06:53,588 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=631, Invalid=4061, Unknown=0, NotChecked=0, Total=4692 [2018-11-18 10:06:53,589 INFO L87 Difference]: Start difference. First operand 1200 states and 1210 transitions. Second operand 69 states. [2018-11-18 10:06:55,406 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:55,406 INFO L93 Difference]: Finished difference Result 1016 states and 1019 transitions. [2018-11-18 10:06:55,407 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 82 states. [2018-11-18 10:06:55,407 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 987 [2018-11-18 10:06:55,407 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:55,408 INFO L225 Difference]: With dead ends: 1016 [2018-11-18 10:06:55,408 INFO L226 Difference]: Without dead ends: 1007 [2018-11-18 10:06:55,409 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1099 GetRequests, 958 SyntacticMatches, 0 SemanticMatches, 141 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6441 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=3007, Invalid=17299, Unknown=0, NotChecked=0, Total=20306 [2018-11-18 10:06:55,410 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1007 states. [2018-11-18 10:06:55,413 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1007 to 1003. [2018-11-18 10:06:55,413 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1003 states. [2018-11-18 10:06:55,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1003 states to 1003 states and 1006 transitions. [2018-11-18 10:06:55,414 INFO L78 Accepts]: Start accepts. Automaton has 1003 states and 1006 transitions. Word has length 987 [2018-11-18 10:06:55,414 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:55,414 INFO L480 AbstractCegarLoop]: Abstraction has 1003 states and 1006 transitions. [2018-11-18 10:06:55,414 INFO L481 AbstractCegarLoop]: Interpolant automaton has 69 states. [2018-11-18 10:06:55,415 INFO L276 IsEmpty]: Start isEmpty. Operand 1003 states and 1006 transitions. [2018-11-18 10:06:55,418 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 994 [2018-11-18 10:06:55,419 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:55,419 INFO L375 BasicCegarLoop]: trace histogram [148, 134, 133, 133, 133, 133, 15, 15, 15, 15, 14, 14, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:55,419 INFO L423 AbstractCegarLoop]: === Iteration 45 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:55,419 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:55,419 INFO L82 PathProgramCache]: Analyzing trace with hash 1266945177, now seen corresponding path program 30 times [2018-11-18 10:06:55,419 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:55,419 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:55,420 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:55,420 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:06:55,420 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:55,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:06:56,116 INFO L134 CoverageAnalysis]: Checked inductivity of 58058 backedges. 20214 proven. 1938 refuted. 0 times theorem prover too weak. 35906 trivial. 0 not checked. [2018-11-18 10:06:56,117 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:06:56,117 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:06:56,123 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-18 10:06:56,953 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 26 check-sat command(s) [2018-11-18 10:06:56,953 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:06:56,963 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:06:57,490 INFO L134 CoverageAnalysis]: Checked inductivity of 58058 backedges. 11508 proven. 694 refuted. 0 times theorem prover too weak. 45856 trivial. 0 not checked. [2018-11-18 10:06:57,507 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:06:57,507 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 21] total 56 [2018-11-18 10:06:57,508 INFO L459 AbstractCegarLoop]: Interpolant automaton has 56 states [2018-11-18 10:06:57,508 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 56 interpolants. [2018-11-18 10:06:57,508 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=447, Invalid=2633, Unknown=0, NotChecked=0, Total=3080 [2018-11-18 10:06:57,508 INFO L87 Difference]: Start difference. First operand 1003 states and 1006 transitions. Second operand 56 states. [2018-11-18 10:06:59,535 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:06:59,535 INFO L93 Difference]: Finished difference Result 1234 states and 1240 transitions. [2018-11-18 10:06:59,535 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 137 states. [2018-11-18 10:06:59,535 INFO L78 Accepts]: Start accepts. Automaton has 56 states. Word has length 993 [2018-11-18 10:06:59,536 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:06:59,537 INFO L225 Difference]: With dead ends: 1234 [2018-11-18 10:06:59,537 INFO L226 Difference]: Without dead ends: 1234 [2018-11-18 10:06:59,538 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1132 GetRequests, 976 SyntacticMatches, 0 SemanticMatches, 156 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8088 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=3714, Invalid=21092, Unknown=0, NotChecked=0, Total=24806 [2018-11-18 10:06:59,539 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1234 states. [2018-11-18 10:06:59,543 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1234 to 1121. [2018-11-18 10:06:59,543 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1121 states. [2018-11-18 10:06:59,545 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1121 states to 1121 states and 1126 transitions. [2018-11-18 10:06:59,545 INFO L78 Accepts]: Start accepts. Automaton has 1121 states and 1126 transitions. Word has length 993 [2018-11-18 10:06:59,545 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:06:59,546 INFO L480 AbstractCegarLoop]: Abstraction has 1121 states and 1126 transitions. [2018-11-18 10:06:59,546 INFO L481 AbstractCegarLoop]: Interpolant automaton has 56 states. [2018-11-18 10:06:59,546 INFO L276 IsEmpty]: Start isEmpty. Operand 1121 states and 1126 transitions. [2018-11-18 10:06:59,557 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1103 [2018-11-18 10:06:59,557 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:06:59,558 INFO L375 BasicCegarLoop]: trace histogram [165, 150, 149, 149, 149, 149, 16, 16, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:06:59,558 INFO L423 AbstractCegarLoop]: === Iteration 46 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:06:59,558 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:06:59,558 INFO L82 PathProgramCache]: Analyzing trace with hash -1692750162, now seen corresponding path program 31 times [2018-11-18 10:06:59,558 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:06:59,559 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:06:59,559 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:59,559 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:06:59,559 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:06:59,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:07:00,339 INFO L134 CoverageAnalysis]: Checked inductivity of 72528 backedges. 24956 proven. 2644 refuted. 0 times theorem prover too weak. 44928 trivial. 0 not checked. [2018-11-18 10:07:00,339 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:07:00,339 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:07:00,345 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:07:00,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:07:00,498 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:07:01,117 INFO L134 CoverageAnalysis]: Checked inductivity of 72528 backedges. 25175 proven. 660 refuted. 0 times theorem prover too weak. 46693 trivial. 0 not checked. [2018-11-18 10:07:01,133 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:07:01,133 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 34] total 54 [2018-11-18 10:07:01,134 INFO L459 AbstractCegarLoop]: Interpolant automaton has 54 states [2018-11-18 10:07:01,134 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2018-11-18 10:07:01,134 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=602, Invalid=2260, Unknown=0, NotChecked=0, Total=2862 [2018-11-18 10:07:01,134 INFO L87 Difference]: Start difference. First operand 1121 states and 1126 transitions. Second operand 54 states. [2018-11-18 10:07:01,841 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:07:01,841 INFO L93 Difference]: Finished difference Result 1143 states and 1145 transitions. [2018-11-18 10:07:01,842 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2018-11-18 10:07:01,842 INFO L78 Accepts]: Start accepts. Automaton has 54 states. Word has length 1102 [2018-11-18 10:07:01,842 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:07:01,843 INFO L225 Difference]: With dead ends: 1143 [2018-11-18 10:07:01,844 INFO L226 Difference]: Without dead ends: 1121 [2018-11-18 10:07:01,844 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1171 GetRequests, 1088 SyntacticMatches, 0 SemanticMatches, 83 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2232 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1613, Invalid=5527, Unknown=0, NotChecked=0, Total=7140 [2018-11-18 10:07:01,844 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1121 states. [2018-11-18 10:07:01,851 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1121 to 1118. [2018-11-18 10:07:01,852 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1118 states. [2018-11-18 10:07:01,853 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1118 states to 1118 states and 1119 transitions. [2018-11-18 10:07:01,853 INFO L78 Accepts]: Start accepts. Automaton has 1118 states and 1119 transitions. Word has length 1102 [2018-11-18 10:07:01,854 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:07:01,854 INFO L480 AbstractCegarLoop]: Abstraction has 1118 states and 1119 transitions. [2018-11-18 10:07:01,854 INFO L481 AbstractCegarLoop]: Interpolant automaton has 54 states. [2018-11-18 10:07:01,854 INFO L276 IsEmpty]: Start isEmpty. Operand 1118 states and 1119 transitions. [2018-11-18 10:07:01,859 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1115 [2018-11-18 10:07:01,860 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:07:01,860 INFO L375 BasicCegarLoop]: trace histogram [167, 152, 151, 151, 151, 151, 16, 16, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:07:01,860 INFO L423 AbstractCegarLoop]: === Iteration 47 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:07:01,860 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:07:01,860 INFO L82 PathProgramCache]: Analyzing trace with hash 1904319470, now seen corresponding path program 32 times [2018-11-18 10:07:01,860 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:07:01,860 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:07:01,861 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:07:01,861 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:07:01,861 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:07:01,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:07:02,614 INFO L134 CoverageAnalysis]: Checked inductivity of 74388 backedges. 14642 proven. 796 refuted. 0 times theorem prover too weak. 58950 trivial. 0 not checked. [2018-11-18 10:07:02,614 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:07:02,614 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:07:02,622 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-18 10:07:02,793 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 10:07:02,793 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:07:02,802 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:07:03,409 INFO L134 CoverageAnalysis]: Checked inductivity of 74388 backedges. 13875 proven. 768 refuted. 0 times theorem prover too weak. 59745 trivial. 0 not checked. [2018-11-18 10:07:03,425 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:07:03,426 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 18] total 53 [2018-11-18 10:07:03,426 INFO L459 AbstractCegarLoop]: Interpolant automaton has 54 states [2018-11-18 10:07:03,427 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2018-11-18 10:07:03,427 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=378, Invalid=2484, Unknown=0, NotChecked=0, Total=2862 [2018-11-18 10:07:03,427 INFO L87 Difference]: Start difference. First operand 1118 states and 1119 transitions. Second operand 54 states. [2018-11-18 10:07:04,781 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:07:04,781 INFO L93 Difference]: Finished difference Result 1252 states and 1256 transitions. [2018-11-18 10:07:04,782 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 55 states. [2018-11-18 10:07:04,782 INFO L78 Accepts]: Start accepts. Automaton has 54 states. Word has length 1114 [2018-11-18 10:07:04,783 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:07:04,784 INFO L225 Difference]: With dead ends: 1252 [2018-11-18 10:07:04,784 INFO L226 Difference]: Without dead ends: 1252 [2018-11-18 10:07:04,785 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1169 GetRequests, 1097 SyntacticMatches, 1 SemanticMatches, 71 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1152 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=660, Invalid=4596, Unknown=0, NotChecked=0, Total=5256 [2018-11-18 10:07:04,785 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1252 states. [2018-11-18 10:07:04,790 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1252 to 1233. [2018-11-18 10:07:04,790 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1233 states. [2018-11-18 10:07:04,792 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1233 states to 1233 states and 1236 transitions. [2018-11-18 10:07:04,792 INFO L78 Accepts]: Start accepts. Automaton has 1233 states and 1236 transitions. Word has length 1114 [2018-11-18 10:07:04,792 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:07:04,792 INFO L480 AbstractCegarLoop]: Abstraction has 1233 states and 1236 transitions. [2018-11-18 10:07:04,793 INFO L481 AbstractCegarLoop]: Interpolant automaton has 54 states. [2018-11-18 10:07:04,793 INFO L276 IsEmpty]: Start isEmpty. Operand 1233 states and 1236 transitions. [2018-11-18 10:07:04,799 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1230 [2018-11-18 10:07:04,799 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:07:04,800 INFO L375 BasicCegarLoop]: trace histogram [185, 169, 168, 168, 168, 168, 17, 17, 17, 17, 16, 16, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:07:04,800 INFO L423 AbstractCegarLoop]: === Iteration 48 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:07:04,800 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:07:04,800 INFO L82 PathProgramCache]: Analyzing trace with hash -2103351503, now seen corresponding path program 33 times [2018-11-18 10:07:04,800 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:07:04,800 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:07:04,801 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:07:04,801 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:07:04,801 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:07:04,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:07:05,747 INFO L134 CoverageAnalysis]: Checked inductivity of 91704 backedges. 29457 proven. 2502 refuted. 0 times theorem prover too weak. 59745 trivial. 0 not checked. [2018-11-18 10:07:05,748 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:07:05,748 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:07:05,754 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 10:07:06,007 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2018-11-18 10:07:06,008 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:07:06,015 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:07:06,782 INFO L134 CoverageAnalysis]: Checked inductivity of 91704 backedges. 28706 proven. 2485 refuted. 0 times theorem prover too weak. 60513 trivial. 0 not checked. [2018-11-18 10:07:06,798 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:07:06,799 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 26] total 62 [2018-11-18 10:07:06,799 INFO L459 AbstractCegarLoop]: Interpolant automaton has 62 states [2018-11-18 10:07:06,799 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2018-11-18 10:07:06,799 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=723, Invalid=3059, Unknown=0, NotChecked=0, Total=3782 [2018-11-18 10:07:06,800 INFO L87 Difference]: Start difference. First operand 1233 states and 1236 transitions. Second operand 62 states. [2018-11-18 10:07:07,995 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:07:07,995 INFO L93 Difference]: Finished difference Result 1367 states and 1372 transitions. [2018-11-18 10:07:07,996 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2018-11-18 10:07:07,996 INFO L78 Accepts]: Start accepts. Automaton has 62 states. Word has length 1229 [2018-11-18 10:07:07,996 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:07:07,998 INFO L225 Difference]: With dead ends: 1367 [2018-11-18 10:07:07,998 INFO L226 Difference]: Without dead ends: 1367 [2018-11-18 10:07:07,999 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1322 GetRequests, 1210 SyntacticMatches, 0 SemanticMatches, 112 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3801 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=3053, Invalid=9829, Unknown=0, NotChecked=0, Total=12882 [2018-11-18 10:07:08,000 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1367 states. [2018-11-18 10:07:08,007 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1367 to 1360. [2018-11-18 10:07:08,008 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1360 states. [2018-11-18 10:07:08,009 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1360 states to 1360 states and 1365 transitions. [2018-11-18 10:07:08,009 INFO L78 Accepts]: Start accepts. Automaton has 1360 states and 1365 transitions. Word has length 1229 [2018-11-18 10:07:08,010 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:07:08,010 INFO L480 AbstractCegarLoop]: Abstraction has 1360 states and 1365 transitions. [2018-11-18 10:07:08,010 INFO L481 AbstractCegarLoop]: Interpolant automaton has 62 states. [2018-11-18 10:07:08,010 INFO L276 IsEmpty]: Start isEmpty. Operand 1360 states and 1365 transitions. [2018-11-18 10:07:08,021 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1236 [2018-11-18 10:07:08,021 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:07:08,021 INFO L375 BasicCegarLoop]: trace histogram [186, 170, 169, 169, 169, 169, 17, 17, 17, 17, 16, 16, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:07:08,022 INFO L423 AbstractCegarLoop]: === Iteration 49 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:07:08,022 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:07:08,022 INFO L82 PathProgramCache]: Analyzing trace with hash -1495359431, now seen corresponding path program 34 times [2018-11-18 10:07:08,022 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:07:08,022 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:07:08,023 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:07:08,023 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:07:08,023 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:07:08,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:07:08,724 INFO L134 CoverageAnalysis]: Checked inductivity of 92747 backedges. 16634 proven. 905 refuted. 0 times theorem prover too weak. 75208 trivial. 0 not checked. [2018-11-18 10:07:08,724 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:07:08,724 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:07:08,731 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 10:07:09,597 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 10:07:09,597 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:07:09,608 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:07:10,173 INFO L134 CoverageAnalysis]: Checked inductivity of 92747 backedges. 16536 proven. 867 refuted. 0 times theorem prover too weak. 75344 trivial. 0 not checked. [2018-11-18 10:07:10,191 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:07:10,191 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 19] total 41 [2018-11-18 10:07:10,192 INFO L459 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-11-18 10:07:10,192 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-11-18 10:07:10,192 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=237, Invalid=1485, Unknown=0, NotChecked=0, Total=1722 [2018-11-18 10:07:10,192 INFO L87 Difference]: Start difference. First operand 1360 states and 1365 transitions. Second operand 42 states. [2018-11-18 10:07:11,572 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:07:11,572 INFO L93 Difference]: Finished difference Result 1626 states and 1637 transitions. [2018-11-18 10:07:11,573 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2018-11-18 10:07:11,573 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 1235 [2018-11-18 10:07:11,573 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:07:11,575 INFO L225 Difference]: With dead ends: 1626 [2018-11-18 10:07:11,575 INFO L226 Difference]: Without dead ends: 1626 [2018-11-18 10:07:11,575 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1279 GetRequests, 1217 SyntacticMatches, 0 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 670 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=443, Invalid=3589, Unknown=0, NotChecked=0, Total=4032 [2018-11-18 10:07:11,576 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1626 states. [2018-11-18 10:07:11,587 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1626 to 1599. [2018-11-18 10:07:11,587 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1599 states. [2018-11-18 10:07:11,589 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1599 states to 1599 states and 1609 transitions. [2018-11-18 10:07:11,589 INFO L78 Accepts]: Start accepts. Automaton has 1599 states and 1609 transitions. Word has length 1235 [2018-11-18 10:07:11,589 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:07:11,589 INFO L480 AbstractCegarLoop]: Abstraction has 1599 states and 1609 transitions. [2018-11-18 10:07:11,590 INFO L481 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-11-18 10:07:11,590 INFO L276 IsEmpty]: Start isEmpty. Operand 1599 states and 1609 transitions. [2018-11-18 10:07:11,597 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1351 [2018-11-18 10:07:11,598 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:07:11,598 INFO L375 BasicCegarLoop]: trace histogram [204, 187, 186, 186, 186, 186, 18, 18, 18, 18, 17, 17, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:07:11,598 INFO L423 AbstractCegarLoop]: === Iteration 50 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:07:11,598 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:07:11,598 INFO L82 PathProgramCache]: Analyzing trace with hash 1968183046, now seen corresponding path program 35 times [2018-11-18 10:07:11,598 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:07:11,598 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:07:11,599 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:07:11,599 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:07:11,599 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:07:11,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:07:12,674 INFO L134 CoverageAnalysis]: Checked inductivity of 111982 backedges. 32433 proven. 4313 refuted. 0 times theorem prover too weak. 75236 trivial. 0 not checked. [2018-11-18 10:07:12,674 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:07:12,674 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:07:12,692 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-18 10:07:19,042 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 35 check-sat command(s) [2018-11-18 10:07:19,042 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:07:19,061 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:07:20,423 INFO L134 CoverageAnalysis]: Checked inductivity of 111982 backedges. 48237 proven. 3840 refuted. 0 times theorem prover too weak. 59905 trivial. 0 not checked. [2018-11-18 10:07:20,443 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:07:20,443 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 40] total 81 [2018-11-18 10:07:20,444 INFO L459 AbstractCegarLoop]: Interpolant automaton has 81 states [2018-11-18 10:07:20,444 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 81 interpolants. [2018-11-18 10:07:20,444 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=886, Invalid=5594, Unknown=0, NotChecked=0, Total=6480 [2018-11-18 10:07:20,444 INFO L87 Difference]: Start difference. First operand 1599 states and 1609 transitions. Second operand 81 states. [2018-11-18 10:07:22,864 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:07:22,864 INFO L93 Difference]: Finished difference Result 1379 states and 1382 transitions. [2018-11-18 10:07:22,864 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 97 states. [2018-11-18 10:07:22,865 INFO L78 Accepts]: Start accepts. Automaton has 81 states. Word has length 1350 [2018-11-18 10:07:22,865 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:07:22,867 INFO L225 Difference]: With dead ends: 1379 [2018-11-18 10:07:22,867 INFO L226 Difference]: Without dead ends: 1370 [2018-11-18 10:07:22,868 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1483 GetRequests, 1315 SyntacticMatches, 0 SemanticMatches, 168 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9333 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=4240, Invalid=24490, Unknown=0, NotChecked=0, Total=28730 [2018-11-18 10:07:22,868 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1370 states. [2018-11-18 10:07:22,873 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1370 to 1366. [2018-11-18 10:07:22,873 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1366 states. [2018-11-18 10:07:22,874 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1366 states to 1366 states and 1369 transitions. [2018-11-18 10:07:22,874 INFO L78 Accepts]: Start accepts. Automaton has 1366 states and 1369 transitions. Word has length 1350 [2018-11-18 10:07:22,874 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:07:22,874 INFO L480 AbstractCegarLoop]: Abstraction has 1366 states and 1369 transitions. [2018-11-18 10:07:22,874 INFO L481 AbstractCegarLoop]: Interpolant automaton has 81 states. [2018-11-18 10:07:22,874 INFO L276 IsEmpty]: Start isEmpty. Operand 1366 states and 1369 transitions. [2018-11-18 10:07:22,881 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1357 [2018-11-18 10:07:22,881 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:07:22,882 INFO L375 BasicCegarLoop]: trace histogram [205, 188, 187, 187, 187, 187, 18, 18, 18, 18, 17, 17, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:07:22,882 INFO L423 AbstractCegarLoop]: === Iteration 51 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:07:22,882 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:07:22,882 INFO L82 PathProgramCache]: Analyzing trace with hash -1169819906, now seen corresponding path program 36 times [2018-11-18 10:07:22,882 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:07:22,882 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:07:22,883 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:07:22,883 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:07:22,883 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:07:22,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:07:23,961 INFO L134 CoverageAnalysis]: Checked inductivity of 113135 backedges. 34980 proven. 2811 refuted. 0 times theorem prover too weak. 75344 trivial. 0 not checked. [2018-11-18 10:07:23,962 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:07:23,962 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:07:23,968 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-18 10:07:26,558 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 37 check-sat command(s) [2018-11-18 10:07:26,558 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:07:26,572 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:07:27,530 INFO L134 CoverageAnalysis]: Checked inductivity of 113135 backedges. 32425 proven. 4607 refuted. 0 times theorem prover too weak. 76103 trivial. 0 not checked. [2018-11-18 10:07:27,558 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:07:27,559 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 28] total 68 [2018-11-18 10:07:27,560 INFO L459 AbstractCegarLoop]: Interpolant automaton has 68 states [2018-11-18 10:07:27,560 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 68 interpolants. [2018-11-18 10:07:27,560 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=809, Invalid=3747, Unknown=0, NotChecked=0, Total=4556 [2018-11-18 10:07:27,560 INFO L87 Difference]: Start difference. First operand 1366 states and 1369 transitions. Second operand 68 states. [2018-11-18 10:07:29,428 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:07:29,428 INFO L93 Difference]: Finished difference Result 1639 states and 1648 transitions. [2018-11-18 10:07:29,429 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 88 states. [2018-11-18 10:07:29,429 INFO L78 Accepts]: Start accepts. Automaton has 68 states. Word has length 1356 [2018-11-18 10:07:29,430 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:07:29,431 INFO L225 Difference]: With dead ends: 1639 [2018-11-18 10:07:29,431 INFO L226 Difference]: Without dead ends: 1639 [2018-11-18 10:07:29,432 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1476 GetRequests, 1333 SyntacticMatches, 0 SemanticMatches, 143 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6340 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=4602, Invalid=16278, Unknown=0, NotChecked=0, Total=20880 [2018-11-18 10:07:29,433 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1639 states. [2018-11-18 10:07:29,438 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1639 to 1626. [2018-11-18 10:07:29,438 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1626 states. [2018-11-18 10:07:29,439 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1626 states to 1626 states and 1635 transitions. [2018-11-18 10:07:29,439 INFO L78 Accepts]: Start accepts. Automaton has 1626 states and 1635 transitions. Word has length 1356 [2018-11-18 10:07:29,440 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:07:29,440 INFO L480 AbstractCegarLoop]: Abstraction has 1626 states and 1635 transitions. [2018-11-18 10:07:29,440 INFO L481 AbstractCegarLoop]: Interpolant automaton has 68 states. [2018-11-18 10:07:29,440 INFO L276 IsEmpty]: Start isEmpty. Operand 1626 states and 1635 transitions. [2018-11-18 10:07:29,448 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1490 [2018-11-18 10:07:29,449 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:07:29,449 INFO L375 BasicCegarLoop]: trace histogram [226, 208, 207, 207, 207, 207, 19, 19, 19, 19, 18, 18, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:07:29,449 INFO L423 AbstractCegarLoop]: === Iteration 52 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:07:29,449 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:07:29,450 INFO L82 PathProgramCache]: Analyzing trace with hash -1093668023, now seen corresponding path program 37 times [2018-11-18 10:07:29,450 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:07:29,450 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:07:29,450 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:07:29,450 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:07:29,450 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:07:29,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:07:30,682 INFO L134 CoverageAnalysis]: Checked inductivity of 138096 backedges. 41152 proven. 3138 refuted. 0 times theorem prover too weak. 93806 trivial. 0 not checked. [2018-11-18 10:07:30,683 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:07:30,683 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:07:30,689 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:07:30,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:07:30,886 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:07:32,220 INFO L134 CoverageAnalysis]: Checked inductivity of 138096 backedges. 43256 proven. 954 refuted. 0 times theorem prover too weak. 93886 trivial. 0 not checked. [2018-11-18 10:07:32,236 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:07:32,236 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 40] total 83 [2018-11-18 10:07:32,237 INFO L459 AbstractCegarLoop]: Interpolant automaton has 83 states [2018-11-18 10:07:32,237 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 83 interpolants. [2018-11-18 10:07:32,237 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1058, Invalid=5748, Unknown=0, NotChecked=0, Total=6806 [2018-11-18 10:07:32,237 INFO L87 Difference]: Start difference. First operand 1626 states and 1635 transitions. Second operand 83 states. [2018-11-18 10:07:34,181 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:07:34,181 INFO L93 Difference]: Finished difference Result 1518 states and 1520 transitions. [2018-11-18 10:07:34,181 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 99 states. [2018-11-18 10:07:34,181 INFO L78 Accepts]: Start accepts. Automaton has 83 states. Word has length 1489 [2018-11-18 10:07:34,181 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:07:34,183 INFO L225 Difference]: With dead ends: 1518 [2018-11-18 10:07:34,183 INFO L226 Difference]: Without dead ends: 1506 [2018-11-18 10:07:34,184 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1608 GetRequests, 1453 SyntacticMatches, 0 SemanticMatches, 155 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7666 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=3754, Invalid=20738, Unknown=0, NotChecked=0, Total=24492 [2018-11-18 10:07:34,184 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1506 states. [2018-11-18 10:07:34,191 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1506 to 1499. [2018-11-18 10:07:34,192 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1499 states. [2018-11-18 10:07:34,193 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1499 states to 1499 states and 1500 transitions. [2018-11-18 10:07:34,193 INFO L78 Accepts]: Start accepts. Automaton has 1499 states and 1500 transitions. Word has length 1489 [2018-11-18 10:07:34,194 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:07:34,194 INFO L480 AbstractCegarLoop]: Abstraction has 1499 states and 1500 transitions. [2018-11-18 10:07:34,194 INFO L481 AbstractCegarLoop]: Interpolant automaton has 83 states. [2018-11-18 10:07:34,194 INFO L276 IsEmpty]: Start isEmpty. Operand 1499 states and 1500 transitions. [2018-11-18 10:07:34,205 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1496 [2018-11-18 10:07:34,205 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:07:34,205 INFO L375 BasicCegarLoop]: trace histogram [227, 209, 208, 208, 208, 208, 19, 19, 19, 19, 18, 18, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:07:34,205 INFO L423 AbstractCegarLoop]: === Iteration 53 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:07:34,206 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:07:34,206 INFO L82 PathProgramCache]: Analyzing trace with hash 1383023185, now seen corresponding path program 38 times [2018-11-18 10:07:34,206 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:07:34,206 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:07:34,206 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:07:34,206 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:07:34,206 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:07:34,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:07:35,074 INFO L134 CoverageAnalysis]: Checked inductivity of 139377 backedges. 22943 proven. 1144 refuted. 0 times theorem prover too weak. 115290 trivial. 0 not checked. [2018-11-18 10:07:35,075 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:07:35,075 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:07:35,081 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-18 10:07:35,275 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 10:07:35,275 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:07:35,285 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:07:36,066 INFO L134 CoverageAnalysis]: Checked inductivity of 139377 backedges. 22833 proven. 1083 refuted. 0 times theorem prover too weak. 115461 trivial. 0 not checked. [2018-11-18 10:07:36,082 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:07:36,082 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 21] total 45 [2018-11-18 10:07:36,083 INFO L459 AbstractCegarLoop]: Interpolant automaton has 46 states [2018-11-18 10:07:36,083 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2018-11-18 10:07:36,083 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=282, Invalid=1788, Unknown=0, NotChecked=0, Total=2070 [2018-11-18 10:07:36,083 INFO L87 Difference]: Start difference. First operand 1499 states and 1500 transitions. Second operand 46 states. [2018-11-18 10:07:37,448 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:07:37,448 INFO L93 Difference]: Finished difference Result 1655 states and 1659 transitions. [2018-11-18 10:07:37,448 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2018-11-18 10:07:37,448 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 1495 [2018-11-18 10:07:37,449 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:07:37,451 INFO L225 Difference]: With dead ends: 1655 [2018-11-18 10:07:37,451 INFO L226 Difference]: Without dead ends: 1655 [2018-11-18 10:07:37,451 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1542 GetRequests, 1475 SyntacticMatches, 0 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 782 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=500, Invalid=4192, Unknown=0, NotChecked=0, Total=4692 [2018-11-18 10:07:37,452 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1655 states. [2018-11-18 10:07:37,457 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1655 to 1632. [2018-11-18 10:07:37,458 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1632 states. [2018-11-18 10:07:37,459 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1632 states to 1632 states and 1635 transitions. [2018-11-18 10:07:37,459 INFO L78 Accepts]: Start accepts. Automaton has 1632 states and 1635 transitions. Word has length 1495 [2018-11-18 10:07:37,460 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:07:37,460 INFO L480 AbstractCegarLoop]: Abstraction has 1632 states and 1635 transitions. [2018-11-18 10:07:37,460 INFO L481 AbstractCegarLoop]: Interpolant automaton has 46 states. [2018-11-18 10:07:37,460 INFO L276 IsEmpty]: Start isEmpty. Operand 1632 states and 1635 transitions. [2018-11-18 10:07:37,474 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1629 [2018-11-18 10:07:37,474 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:07:37,474 INFO L375 BasicCegarLoop]: trace histogram [248, 229, 228, 228, 228, 228, 20, 20, 20, 20, 19, 19, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:07:37,474 INFO L423 AbstractCegarLoop]: === Iteration 54 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:07:37,474 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:07:37,475 INFO L82 PathProgramCache]: Analyzing trace with hash -1283860010, now seen corresponding path program 39 times [2018-11-18 10:07:37,475 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:07:37,475 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:07:37,475 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:07:37,475 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:07:37,476 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:07:37,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:07:38,886 INFO L134 CoverageAnalysis]: Checked inductivity of 166953 backedges. 48009 proven. 3483 refuted. 0 times theorem prover too weak. 115461 trivial. 0 not checked. [2018-11-18 10:07:38,886 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:07:38,886 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:07:38,892 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 10:07:39,293 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) [2018-11-18 10:07:39,293 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:07:39,302 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:07:40,307 INFO L134 CoverageAnalysis]: Checked inductivity of 166953 backedges. 26382 proven. 1200 refuted. 0 times theorem prover too weak. 139371 trivial. 0 not checked. [2018-11-18 10:07:40,323 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:07:40,323 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 23] total 70 [2018-11-18 10:07:40,324 INFO L459 AbstractCegarLoop]: Interpolant automaton has 70 states [2018-11-18 10:07:40,324 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 70 interpolants. [2018-11-18 10:07:40,325 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=751, Invalid=4079, Unknown=0, NotChecked=0, Total=4830 [2018-11-18 10:07:40,325 INFO L87 Difference]: Start difference. First operand 1632 states and 1635 transitions. Second operand 70 states. [2018-11-18 10:07:42,116 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:07:42,116 INFO L93 Difference]: Finished difference Result 1793 states and 1799 transitions. [2018-11-18 10:07:42,116 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 71 states. [2018-11-18 10:07:42,116 INFO L78 Accepts]: Start accepts. Automaton has 70 states. Word has length 1628 [2018-11-18 10:07:42,117 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:07:42,119 INFO L225 Difference]: With dead ends: 1793 [2018-11-18 10:07:42,119 INFO L226 Difference]: Without dead ends: 1793 [2018-11-18 10:07:42,120 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1737 GetRequests, 1607 SyntacticMatches, 0 SemanticMatches, 130 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4130 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=3932, Invalid=13360, Unknown=0, NotChecked=0, Total=17292 [2018-11-18 10:07:42,120 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1793 states. [2018-11-18 10:07:42,126 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1793 to 1783. [2018-11-18 10:07:42,126 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1783 states. [2018-11-18 10:07:42,127 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1783 states to 1783 states and 1789 transitions. [2018-11-18 10:07:42,127 INFO L78 Accepts]: Start accepts. Automaton has 1783 states and 1789 transitions. Word has length 1628 [2018-11-18 10:07:42,128 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:07:42,128 INFO L480 AbstractCegarLoop]: Abstraction has 1783 states and 1789 transitions. [2018-11-18 10:07:42,128 INFO L481 AbstractCegarLoop]: Interpolant automaton has 70 states. [2018-11-18 10:07:42,128 INFO L276 IsEmpty]: Start isEmpty. Operand 1783 states and 1789 transitions. [2018-11-18 10:07:42,139 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1641 [2018-11-18 10:07:42,139 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:07:42,139 INFO L375 BasicCegarLoop]: trace histogram [250, 231, 230, 230, 230, 230, 20, 20, 20, 20, 19, 19, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:07:42,140 INFO L423 AbstractCegarLoop]: === Iteration 55 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:07:42,140 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:07:42,140 INFO L82 PathProgramCache]: Analyzing trace with hash -456679658, now seen corresponding path program 40 times [2018-11-18 10:07:42,140 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:07:42,140 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:07:42,140 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:07:42,140 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:07:42,140 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:07:42,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:07:43,435 INFO L134 CoverageAnalysis]: Checked inductivity of 169777 backedges. 29077 proven. 1316 refuted. 0 times theorem prover too weak. 139384 trivial. 0 not checked. [2018-11-18 10:07:43,436 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:07:43,436 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:07:43,442 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 10:07:43,625 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 10:07:43,625 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:07:43,637 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:07:45,065 INFO L134 CoverageAnalysis]: Checked inductivity of 169777 backedges. 28896 proven. 4567 refuted. 0 times theorem prover too weak. 136314 trivial. 0 not checked. [2018-11-18 10:07:45,081 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:07:45,081 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 49] total 73 [2018-11-18 10:07:45,082 INFO L459 AbstractCegarLoop]: Interpolant automaton has 73 states [2018-11-18 10:07:45,082 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 73 interpolants. [2018-11-18 10:07:45,082 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1094, Invalid=4162, Unknown=0, NotChecked=0, Total=5256 [2018-11-18 10:07:45,082 INFO L87 Difference]: Start difference. First operand 1783 states and 1789 transitions. Second operand 73 states. [2018-11-18 10:07:46,310 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:07:46,310 INFO L93 Difference]: Finished difference Result 2069 states and 2079 transitions. [2018-11-18 10:07:46,311 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 71 states. [2018-11-18 10:07:46,311 INFO L78 Accepts]: Start accepts. Automaton has 73 states. Word has length 1640 [2018-11-18 10:07:46,311 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:07:46,314 INFO L225 Difference]: With dead ends: 2069 [2018-11-18 10:07:46,314 INFO L226 Difference]: Without dead ends: 2069 [2018-11-18 10:07:46,315 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1728 GetRequests, 1614 SyntacticMatches, 0 SemanticMatches, 114 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2501 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=2993, Invalid=10347, Unknown=0, NotChecked=0, Total=13340 [2018-11-18 10:07:46,316 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2069 states. [2018-11-18 10:07:46,327 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2069 to 2058. [2018-11-18 10:07:46,327 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2058 states. [2018-11-18 10:07:46,328 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2058 states to 2058 states and 2068 transitions. [2018-11-18 10:07:46,328 INFO L78 Accepts]: Start accepts. Automaton has 2058 states and 2068 transitions. Word has length 1640 [2018-11-18 10:07:46,329 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:07:46,329 INFO L480 AbstractCegarLoop]: Abstraction has 2058 states and 2068 transitions. [2018-11-18 10:07:46,329 INFO L481 AbstractCegarLoop]: Interpolant automaton has 73 states. [2018-11-18 10:07:46,329 INFO L276 IsEmpty]: Start isEmpty. Operand 2058 states and 2068 transitions. [2018-11-18 10:07:46,342 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1768 [2018-11-18 10:07:46,342 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:07:46,342 INFO L375 BasicCegarLoop]: trace histogram [270, 250, 249, 249, 249, 249, 21, 21, 21, 21, 20, 20, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:07:46,342 INFO L423 AbstractCegarLoop]: === Iteration 56 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:07:46,342 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:07:46,342 INFO L82 PathProgramCache]: Analyzing trace with hash -496614615, now seen corresponding path program 41 times [2018-11-18 10:07:46,343 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:07:46,343 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:07:46,343 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:07:46,343 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:07:46,343 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:07:46,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:07:47,937 INFO L134 CoverageAnalysis]: Checked inductivity of 198553 backedges. 52053 proven. 5972 refuted. 0 times theorem prover too weak. 140528 trivial. 0 not checked. [2018-11-18 10:07:47,937 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:07:47,937 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:07:47,943 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-18 10:07:50,073 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 53 check-sat command(s) [2018-11-18 10:07:50,073 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:07:50,093 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:07:51,931 INFO L134 CoverageAnalysis]: Checked inductivity of 198553 backedges. 77678 proven. 6466 refuted. 0 times theorem prover too weak. 114409 trivial. 0 not checked. [2018-11-18 10:07:51,951 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:07:51,951 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 46] total 93 [2018-11-18 10:07:51,952 INFO L459 AbstractCegarLoop]: Interpolant automaton has 93 states [2018-11-18 10:07:51,952 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 93 interpolants. [2018-11-18 10:07:51,952 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1173, Invalid=7383, Unknown=0, NotChecked=0, Total=8556 [2018-11-18 10:07:51,953 INFO L87 Difference]: Start difference. First operand 2058 states and 2068 transitions. Second operand 93 states. [2018-11-18 10:07:54,791 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:07:54,791 INFO L93 Difference]: Finished difference Result 1796 states and 1799 transitions. [2018-11-18 10:07:54,792 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 111 states. [2018-11-18 10:07:54,792 INFO L78 Accepts]: Start accepts. Automaton has 93 states. Word has length 1767 [2018-11-18 10:07:54,792 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:07:54,794 INFO L225 Difference]: With dead ends: 1796 [2018-11-18 10:07:54,794 INFO L226 Difference]: Without dead ends: 1787 [2018-11-18 10:07:54,796 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1920 GetRequests, 1726 SyntacticMatches, 0 SemanticMatches, 194 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12588 ImplicationChecksByTransitivity, 2.8s TimeCoverageRelationStatistics Valid=5595, Invalid=32625, Unknown=0, NotChecked=0, Total=38220 [2018-11-18 10:07:54,797 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1787 states. [2018-11-18 10:07:54,803 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1787 to 1783. [2018-11-18 10:07:54,804 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1783 states. [2018-11-18 10:07:54,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1783 states to 1783 states and 1786 transitions. [2018-11-18 10:07:54,805 INFO L78 Accepts]: Start accepts. Automaton has 1783 states and 1786 transitions. Word has length 1767 [2018-11-18 10:07:54,806 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:07:54,806 INFO L480 AbstractCegarLoop]: Abstraction has 1783 states and 1786 transitions. [2018-11-18 10:07:54,806 INFO L481 AbstractCegarLoop]: Interpolant automaton has 93 states. [2018-11-18 10:07:54,806 INFO L276 IsEmpty]: Start isEmpty. Operand 1783 states and 1786 transitions. [2018-11-18 10:07:54,818 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1774 [2018-11-18 10:07:54,818 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:07:54,818 INFO L375 BasicCegarLoop]: trace histogram [271, 251, 250, 250, 250, 250, 21, 21, 21, 21, 20, 20, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:07:54,818 INFO L423 AbstractCegarLoop]: === Iteration 57 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:07:54,818 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:07:54,818 INFO L82 PathProgramCache]: Analyzing trace with hash -1726058271, now seen corresponding path program 42 times [2018-11-18 10:07:54,819 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:07:54,819 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:07:54,819 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:07:54,819 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:07:54,819 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:07:54,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:07:56,410 INFO L134 CoverageAnalysis]: Checked inductivity of 200090 backedges. 55587 proven. 3846 refuted. 0 times theorem prover too weak. 140657 trivial. 0 not checked. [2018-11-18 10:07:56,410 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:07:56,410 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:07:56,417 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-18 10:07:57,714 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 43 check-sat command(s) [2018-11-18 10:07:57,714 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:07:57,726 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:07:58,938 INFO L134 CoverageAnalysis]: Checked inductivity of 200090 backedges. 30421 proven. 1323 refuted. 0 times theorem prover too weak. 168346 trivial. 0 not checked. [2018-11-18 10:07:58,955 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:07:58,955 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 24] total 73 [2018-11-18 10:07:58,956 INFO L459 AbstractCegarLoop]: Interpolant automaton has 73 states [2018-11-18 10:07:58,956 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 73 interpolants. [2018-11-18 10:07:58,956 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=819, Invalid=4437, Unknown=0, NotChecked=0, Total=5256 [2018-11-18 10:07:58,956 INFO L87 Difference]: Start difference. First operand 1783 states and 1786 transitions. Second operand 73 states. [2018-11-18 10:08:00,954 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:08:00,954 INFO L93 Difference]: Finished difference Result 1944 states and 1950 transitions. [2018-11-18 10:08:00,954 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 74 states. [2018-11-18 10:08:00,954 INFO L78 Accepts]: Start accepts. Automaton has 73 states. Word has length 1773 [2018-11-18 10:08:00,955 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:08:00,958 INFO L225 Difference]: With dead ends: 1944 [2018-11-18 10:08:00,958 INFO L226 Difference]: Without dead ends: 1944 [2018-11-18 10:08:00,959 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1887 GetRequests, 1751 SyntacticMatches, 0 SemanticMatches, 136 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4536 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=4305, Invalid=14601, Unknown=0, NotChecked=0, Total=18906 [2018-11-18 10:08:00,960 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1944 states. [2018-11-18 10:08:00,967 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1944 to 1934. [2018-11-18 10:08:00,967 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1934 states. [2018-11-18 10:08:00,968 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1934 states to 1934 states and 1940 transitions. [2018-11-18 10:08:00,968 INFO L78 Accepts]: Start accepts. Automaton has 1934 states and 1940 transitions. Word has length 1773 [2018-11-18 10:08:00,969 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:08:00,969 INFO L480 AbstractCegarLoop]: Abstraction has 1934 states and 1940 transitions. [2018-11-18 10:08:00,969 INFO L481 AbstractCegarLoop]: Interpolant automaton has 73 states. [2018-11-18 10:08:00,969 INFO L276 IsEmpty]: Start isEmpty. Operand 1934 states and 1940 transitions. [2018-11-18 10:08:00,982 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1786 [2018-11-18 10:08:00,982 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:08:00,982 INFO L375 BasicCegarLoop]: trace histogram [273, 253, 252, 252, 252, 252, 21, 21, 21, 21, 20, 20, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:08:00,982 INFO L423 AbstractCegarLoop]: === Iteration 58 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:08:00,983 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:08:00,983 INFO L82 PathProgramCache]: Analyzing trace with hash 1995129249, now seen corresponding path program 43 times [2018-11-18 10:08:00,983 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:08:00,983 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:08:00,983 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:08:00,984 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:08:00,984 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:08:01,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:08:02,445 INFO L134 CoverageAnalysis]: Checked inductivity of 203182 backedges. 33377 proven. 1455 refuted. 0 times theorem prover too weak. 168350 trivial. 0 not checked. [2018-11-18 10:08:02,445 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:08:02,445 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:08:02,452 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:08:02,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:08:02,694 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:08:04,178 INFO L134 CoverageAnalysis]: Checked inductivity of 203182 backedges. 33442 proven. 1390 refuted. 0 times theorem prover too weak. 168350 trivial. 0 not checked. [2018-11-18 10:08:04,194 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:08:04,195 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 47] total 72 [2018-11-18 10:08:04,195 INFO L459 AbstractCegarLoop]: Interpolant automaton has 72 states [2018-11-18 10:08:04,195 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 72 interpolants. [2018-11-18 10:08:04,196 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1177, Invalid=3935, Unknown=0, NotChecked=0, Total=5112 [2018-11-18 10:08:04,196 INFO L87 Difference]: Start difference. First operand 1934 states and 1940 transitions. Second operand 72 states. [2018-11-18 10:08:05,343 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:08:05,344 INFO L93 Difference]: Finished difference Result 2232 states and 2242 transitions. [2018-11-18 10:08:05,344 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2018-11-18 10:08:05,344 INFO L78 Accepts]: Start accepts. Automaton has 72 states. Word has length 1785 [2018-11-18 10:08:05,345 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:08:05,347 INFO L225 Difference]: With dead ends: 2232 [2018-11-18 10:08:05,347 INFO L226 Difference]: Without dead ends: 2232 [2018-11-18 10:08:05,348 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1875 GetRequests, 1762 SyntacticMatches, 0 SemanticMatches, 113 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2204 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=3324, Invalid=9786, Unknown=0, NotChecked=0, Total=13110 [2018-11-18 10:08:05,349 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2232 states. [2018-11-18 10:08:05,361 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2232 to 2221. [2018-11-18 10:08:05,362 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2221 states. [2018-11-18 10:08:05,364 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2221 states to 2221 states and 2231 transitions. [2018-11-18 10:08:05,364 INFO L78 Accepts]: Start accepts. Automaton has 2221 states and 2231 transitions. Word has length 1785 [2018-11-18 10:08:05,365 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:08:05,365 INFO L480 AbstractCegarLoop]: Abstraction has 2221 states and 2231 transitions. [2018-11-18 10:08:05,365 INFO L481 AbstractCegarLoop]: Interpolant automaton has 72 states. [2018-11-18 10:08:05,365 INFO L276 IsEmpty]: Start isEmpty. Operand 2221 states and 2231 transitions. [2018-11-18 10:08:05,383 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1919 [2018-11-18 10:08:05,383 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:08:05,384 INFO L375 BasicCegarLoop]: trace histogram [294, 273, 272, 272, 272, 272, 22, 22, 22, 22, 21, 21, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:08:05,384 INFO L423 AbstractCegarLoop]: === Iteration 59 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:08:05,384 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:08:05,384 INFO L82 PathProgramCache]: Analyzing trace with hash -1443852490, now seen corresponding path program 44 times [2018-11-18 10:08:05,385 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:08:05,385 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:08:05,385 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:08:05,385 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:08:05,385 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:08:05,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:08:07,183 INFO L134 CoverageAnalysis]: Checked inductivity of 236232 backedges. 60023 proven. 6585 refuted. 0 times theorem prover too weak. 169624 trivial. 0 not checked. [2018-11-18 10:08:07,183 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:08:07,183 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:08:07,189 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-18 10:08:07,441 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 10:08:07,441 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:08:07,455 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:08:09,327 INFO L134 CoverageAnalysis]: Checked inductivity of 236232 backedges. 90006 proven. 1180 refuted. 0 times theorem prover too weak. 145046 trivial. 0 not checked. [2018-11-18 10:08:09,344 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:08:09,344 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 44] total 93 [2018-11-18 10:08:09,345 INFO L459 AbstractCegarLoop]: Interpolant automaton has 93 states [2018-11-18 10:08:09,345 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 93 interpolants. [2018-11-18 10:08:09,346 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1301, Invalid=7255, Unknown=0, NotChecked=0, Total=8556 [2018-11-18 10:08:09,346 INFO L87 Difference]: Start difference. First operand 2221 states and 2231 transitions. Second operand 93 states. [2018-11-18 10:08:11,912 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:08:11,912 INFO L93 Difference]: Finished difference Result 1947 states and 1950 transitions. [2018-11-18 10:08:11,912 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 111 states. [2018-11-18 10:08:11,912 INFO L78 Accepts]: Start accepts. Automaton has 93 states. Word has length 1918 [2018-11-18 10:08:11,913 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:08:11,915 INFO L225 Difference]: With dead ends: 1947 [2018-11-18 10:08:11,915 INFO L226 Difference]: Without dead ends: 1938 [2018-11-18 10:08:11,916 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2053 GetRequests, 1878 SyntacticMatches, 0 SemanticMatches, 175 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9854 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=4707, Invalid=26445, Unknown=0, NotChecked=0, Total=31152 [2018-11-18 10:08:11,917 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1938 states. [2018-11-18 10:08:11,923 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1938 to 1934. [2018-11-18 10:08:11,923 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1934 states. [2018-11-18 10:08:11,925 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1934 states to 1934 states and 1937 transitions. [2018-11-18 10:08:11,925 INFO L78 Accepts]: Start accepts. Automaton has 1934 states and 1937 transitions. Word has length 1918 [2018-11-18 10:08:11,926 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:08:11,926 INFO L480 AbstractCegarLoop]: Abstraction has 1934 states and 1937 transitions. [2018-11-18 10:08:11,926 INFO L481 AbstractCegarLoop]: Interpolant automaton has 93 states. [2018-11-18 10:08:11,926 INFO L276 IsEmpty]: Start isEmpty. Operand 1934 states and 1937 transitions. [2018-11-18 10:08:11,940 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1925 [2018-11-18 10:08:11,941 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:08:11,941 INFO L375 BasicCegarLoop]: trace histogram [295, 274, 273, 273, 273, 273, 22, 22, 22, 22, 21, 21, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:08:11,941 INFO L423 AbstractCegarLoop]: === Iteration 60 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:08:11,941 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:08:11,942 INFO L82 PathProgramCache]: Analyzing trace with hash -631211218, now seen corresponding path program 45 times [2018-11-18 10:08:11,942 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:08:11,942 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:08:11,942 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:08:11,942 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:08:11,942 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:08:12,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:08:13,828 INFO L134 CoverageAnalysis]: Checked inductivity of 237909 backedges. 63922 proven. 4227 refuted. 0 times theorem prover too weak. 169760 trivial. 0 not checked. [2018-11-18 10:08:13,828 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:08:13,828 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:08:13,836 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 10:08:14,405 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 23 check-sat command(s) [2018-11-18 10:08:14,405 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:08:14,416 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:08:15,961 INFO L134 CoverageAnalysis]: Checked inductivity of 237909 backedges. 62621 proven. 4205 refuted. 0 times theorem prover too weak. 171083 trivial. 0 not checked. [2018-11-18 10:08:15,977 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:08:15,978 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 31] total 77 [2018-11-18 10:08:15,978 INFO L459 AbstractCegarLoop]: Interpolant automaton has 77 states [2018-11-18 10:08:15,979 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 77 interpolants. [2018-11-18 10:08:15,979 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1148, Invalid=4704, Unknown=0, NotChecked=0, Total=5852 [2018-11-18 10:08:15,979 INFO L87 Difference]: Start difference. First operand 1934 states and 1937 transitions. Second operand 77 states. [2018-11-18 10:08:17,607 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:08:17,607 INFO L93 Difference]: Finished difference Result 2092 states and 2097 transitions. [2018-11-18 10:08:17,607 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 75 states. [2018-11-18 10:08:17,607 INFO L78 Accepts]: Start accepts. Automaton has 77 states. Word has length 1924 [2018-11-18 10:08:17,608 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:08:17,611 INFO L225 Difference]: With dead ends: 2092 [2018-11-18 10:08:17,611 INFO L226 Difference]: Without dead ends: 2092 [2018-11-18 10:08:17,612 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2042 GetRequests, 1900 SyntacticMatches, 0 SemanticMatches, 142 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6241 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=4928, Invalid=15664, Unknown=0, NotChecked=0, Total=20592 [2018-11-18 10:08:17,613 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2092 states. [2018-11-18 10:08:17,620 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2092 to 2085. [2018-11-18 10:08:17,621 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2085 states. [2018-11-18 10:08:17,622 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2085 states to 2085 states and 2090 transitions. [2018-11-18 10:08:17,623 INFO L78 Accepts]: Start accepts. Automaton has 2085 states and 2090 transitions. Word has length 1924 [2018-11-18 10:08:17,624 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:08:17,624 INFO L480 AbstractCegarLoop]: Abstraction has 2085 states and 2090 transitions. [2018-11-18 10:08:17,624 INFO L481 AbstractCegarLoop]: Interpolant automaton has 77 states. [2018-11-18 10:08:17,624 INFO L276 IsEmpty]: Start isEmpty. Operand 2085 states and 2090 transitions. [2018-11-18 10:08:17,639 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1931 [2018-11-18 10:08:17,639 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:08:17,640 INFO L375 BasicCegarLoop]: trace histogram [296, 275, 274, 274, 274, 274, 22, 22, 22, 22, 21, 21, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:08:17,640 INFO L423 AbstractCegarLoop]: === Iteration 61 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:08:17,640 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:08:17,641 INFO L82 PathProgramCache]: Analyzing trace with hash -1894558090, now seen corresponding path program 46 times [2018-11-18 10:08:17,641 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:08:17,641 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:08:17,641 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:08:17,641 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:08:17,641 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:08:17,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:08:18,976 INFO L134 CoverageAnalysis]: Checked inductivity of 239592 backedges. 35237 proven. 1555 refuted. 0 times theorem prover too weak. 202800 trivial. 0 not checked. [2018-11-18 10:08:18,976 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:08:18,976 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:08:18,985 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 10:08:20,155 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 10:08:20,155 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:08:20,173 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:08:21,397 INFO L134 CoverageAnalysis]: Checked inductivity of 239592 backedges. 34986 proven. 1452 refuted. 0 times theorem prover too weak. 203154 trivial. 0 not checked. [2018-11-18 10:08:21,417 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:08:21,417 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 24] total 52 [2018-11-18 10:08:21,418 INFO L459 AbstractCegarLoop]: Interpolant automaton has 53 states [2018-11-18 10:08:21,418 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2018-11-18 10:08:21,418 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=361, Invalid=2395, Unknown=0, NotChecked=0, Total=2756 [2018-11-18 10:08:21,418 INFO L87 Difference]: Start difference. First operand 2085 states and 2090 transitions. Second operand 53 states. [2018-11-18 10:08:23,269 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:08:23,269 INFO L93 Difference]: Finished difference Result 2411 states and 2422 transitions. [2018-11-18 10:08:23,269 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 75 states. [2018-11-18 10:08:23,269 INFO L78 Accepts]: Start accepts. Automaton has 53 states. Word has length 1930 [2018-11-18 10:08:23,270 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:08:23,273 INFO L225 Difference]: With dead ends: 2411 [2018-11-18 10:08:23,273 INFO L226 Difference]: Without dead ends: 2411 [2018-11-18 10:08:23,274 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 1985 GetRequests, 1907 SyntacticMatches, 0 SemanticMatches, 78 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1095 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=639, Invalid=5681, Unknown=0, NotChecked=0, Total=6320 [2018-11-18 10:08:23,275 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2411 states. [2018-11-18 10:08:23,284 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2411 to 2384. [2018-11-18 10:08:23,284 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2384 states. [2018-11-18 10:08:23,286 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2384 states to 2384 states and 2394 transitions. [2018-11-18 10:08:23,286 INFO L78 Accepts]: Start accepts. Automaton has 2384 states and 2394 transitions. Word has length 1930 [2018-11-18 10:08:23,287 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:08:23,287 INFO L480 AbstractCegarLoop]: Abstraction has 2384 states and 2394 transitions. [2018-11-18 10:08:23,287 INFO L481 AbstractCegarLoop]: Interpolant automaton has 53 states. [2018-11-18 10:08:23,287 INFO L276 IsEmpty]: Start isEmpty. Operand 2384 states and 2394 transitions. [2018-11-18 10:08:23,304 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2076 [2018-11-18 10:08:23,304 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:08:23,304 INFO L375 BasicCegarLoop]: trace histogram [319, 297, 296, 296, 296, 296, 23, 23, 23, 23, 22, 22, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:08:23,304 INFO L423 AbstractCegarLoop]: === Iteration 62 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:08:23,305 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:08:23,305 INFO L82 PathProgramCache]: Analyzing trace with hash -1524454335, now seen corresponding path program 47 times [2018-11-18 10:08:23,305 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:08:23,305 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:08:23,306 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:08:23,306 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:08:23,306 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:08:23,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:08:25,336 INFO L134 CoverageAnalysis]: Checked inductivity of 279007 backedges. 68768 proven. 7228 refuted. 0 times theorem prover too weak. 203011 trivial. 0 not checked. [2018-11-18 10:08:25,336 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:08:25,336 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:08:25,343 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-18 10:08:30,186 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 56 check-sat command(s) [2018-11-18 10:08:30,186 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:08:30,211 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:08:32,495 INFO L134 CoverageAnalysis]: Checked inductivity of 279007 backedges. 102768 proven. 7848 refuted. 0 times theorem prover too weak. 168391 trivial. 0 not checked. [2018-11-18 10:08:32,516 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:08:32,517 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 50] total 101 [2018-11-18 10:08:32,517 INFO L459 AbstractCegarLoop]: Interpolant automaton has 101 states [2018-11-18 10:08:32,517 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 101 interpolants. [2018-11-18 10:08:32,518 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1396, Invalid=8704, Unknown=0, NotChecked=0, Total=10100 [2018-11-18 10:08:32,518 INFO L87 Difference]: Start difference. First operand 2384 states and 2394 transitions. Second operand 101 states. [2018-11-18 10:08:35,779 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:08:35,779 INFO L93 Difference]: Finished difference Result 2104 states and 2107 transitions. [2018-11-18 10:08:35,779 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 121 states. [2018-11-18 10:08:35,779 INFO L78 Accepts]: Start accepts. Automaton has 101 states. Word has length 2075 [2018-11-18 10:08:35,780 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:08:35,783 INFO L225 Difference]: With dead ends: 2104 [2018-11-18 10:08:35,783 INFO L226 Difference]: Without dead ends: 2095 [2018-11-18 10:08:35,785 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2242 GetRequests, 2030 SyntacticMatches, 0 SemanticMatches, 212 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15151 ImplicationChecksByTransitivity, 3.2s TimeCoverageRelationStatistics Valid=6669, Invalid=38913, Unknown=0, NotChecked=0, Total=45582 [2018-11-18 10:08:35,786 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2095 states. [2018-11-18 10:08:35,793 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2095 to 2091. [2018-11-18 10:08:35,793 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2091 states. [2018-11-18 10:08:35,795 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2091 states to 2091 states and 2094 transitions. [2018-11-18 10:08:35,795 INFO L78 Accepts]: Start accepts. Automaton has 2091 states and 2094 transitions. Word has length 2075 [2018-11-18 10:08:35,796 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:08:35,796 INFO L480 AbstractCegarLoop]: Abstraction has 2091 states and 2094 transitions. [2018-11-18 10:08:35,796 INFO L481 AbstractCegarLoop]: Interpolant automaton has 101 states. [2018-11-18 10:08:35,796 INFO L276 IsEmpty]: Start isEmpty. Operand 2091 states and 2094 transitions. [2018-11-18 10:08:35,812 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2082 [2018-11-18 10:08:35,812 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:08:35,813 INFO L375 BasicCegarLoop]: trace histogram [320, 298, 297, 297, 297, 297, 23, 23, 23, 23, 22, 22, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:08:35,813 INFO L423 AbstractCegarLoop]: === Iteration 63 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:08:35,813 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:08:35,813 INFO L82 PathProgramCache]: Analyzing trace with hash -1931075591, now seen corresponding path program 48 times [2018-11-18 10:08:35,813 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:08:35,813 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:08:35,814 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:08:35,814 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:08:35,814 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:08:35,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:08:37,872 INFO L134 CoverageAnalysis]: Checked inductivity of 280830 backedges. 73050 proven. 4626 refuted. 0 times theorem prover too weak. 203154 trivial. 0 not checked. [2018-11-18 10:08:37,872 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:08:37,872 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:08:37,879 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-18 10:08:39,883 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 47 check-sat command(s) [2018-11-18 10:08:39,883 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:08:39,898 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:08:41,560 INFO L134 CoverageAnalysis]: Checked inductivity of 280830 backedges. 71621 proven. 4603 refuted. 0 times theorem prover too weak. 204606 trivial. 0 not checked. [2018-11-18 10:08:41,579 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:08:41,579 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 32] total 80 [2018-11-18 10:08:41,580 INFO L459 AbstractCegarLoop]: Interpolant automaton has 80 states [2018-11-18 10:08:41,580 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 80 interpolants. [2018-11-18 10:08:41,580 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1245, Invalid=5075, Unknown=0, NotChecked=0, Total=6320 [2018-11-18 10:08:41,580 INFO L87 Difference]: Start difference. First operand 2091 states and 2094 transitions. Second operand 80 states. [2018-11-18 10:08:43,169 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:08:43,169 INFO L93 Difference]: Finished difference Result 2255 states and 2260 transitions. [2018-11-18 10:08:43,169 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 78 states. [2018-11-18 10:08:43,169 INFO L78 Accepts]: Start accepts. Automaton has 80 states. Word has length 2081 [2018-11-18 10:08:43,170 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:08:43,173 INFO L225 Difference]: With dead ends: 2255 [2018-11-18 10:08:43,173 INFO L226 Difference]: Without dead ends: 2255 [2018-11-18 10:08:43,174 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2204 GetRequests, 2056 SyntacticMatches, 0 SemanticMatches, 148 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6801 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=5357, Invalid=16993, Unknown=0, NotChecked=0, Total=22350 [2018-11-18 10:08:43,176 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2255 states. [2018-11-18 10:08:43,184 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2255 to 2248. [2018-11-18 10:08:43,184 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2248 states. [2018-11-18 10:08:43,186 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2248 states to 2248 states and 2253 transitions. [2018-11-18 10:08:43,186 INFO L78 Accepts]: Start accepts. Automaton has 2248 states and 2253 transitions. Word has length 2081 [2018-11-18 10:08:43,186 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:08:43,186 INFO L480 AbstractCegarLoop]: Abstraction has 2248 states and 2253 transitions. [2018-11-18 10:08:43,186 INFO L481 AbstractCegarLoop]: Interpolant automaton has 80 states. [2018-11-18 10:08:43,187 INFO L276 IsEmpty]: Start isEmpty. Operand 2248 states and 2253 transitions. [2018-11-18 10:08:43,202 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2088 [2018-11-18 10:08:43,202 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:08:43,202 INFO L375 BasicCegarLoop]: trace histogram [321, 299, 298, 298, 298, 298, 23, 23, 23, 23, 22, 22, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:08:43,203 INFO L423 AbstractCegarLoop]: === Iteration 64 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:08:43,203 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:08:43,203 INFO L82 PathProgramCache]: Analyzing trace with hash -165397759, now seen corresponding path program 49 times [2018-11-18 10:08:43,203 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:08:43,203 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:08:43,203 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:08:43,203 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:08:43,204 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:08:43,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:08:44,712 INFO L134 CoverageAnalysis]: Checked inductivity of 282659 backedges. 39965 proven. 1706 refuted. 0 times theorem prover too weak. 240988 trivial. 0 not checked. [2018-11-18 10:08:44,712 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:08:44,712 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:08:44,719 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:08:44,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:08:45,012 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:08:46,353 INFO L134 CoverageAnalysis]: Checked inductivity of 282659 backedges. 39831 proven. 1587 refuted. 0 times theorem prover too weak. 241241 trivial. 0 not checked. [2018-11-18 10:08:46,369 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:08:46,370 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 25] total 53 [2018-11-18 10:08:46,371 INFO L459 AbstractCegarLoop]: Interpolant automaton has 54 states [2018-11-18 10:08:46,371 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2018-11-18 10:08:46,371 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=384, Invalid=2478, Unknown=0, NotChecked=0, Total=2862 [2018-11-18 10:08:46,371 INFO L87 Difference]: Start difference. First operand 2248 states and 2253 transitions. Second operand 54 states. [2018-11-18 10:08:48,329 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:08:48,329 INFO L93 Difference]: Finished difference Result 2586 states and 2597 transitions. [2018-11-18 10:08:48,329 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 78 states. [2018-11-18 10:08:48,329 INFO L78 Accepts]: Start accepts. Automaton has 54 states. Word has length 2087 [2018-11-18 10:08:48,331 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:08:48,333 INFO L225 Difference]: With dead ends: 2586 [2018-11-18 10:08:48,333 INFO L226 Difference]: Without dead ends: 2586 [2018-11-18 10:08:48,334 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2143 GetRequests, 2063 SyntacticMatches, 0 SemanticMatches, 80 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1111 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=650, Invalid=5992, Unknown=0, NotChecked=0, Total=6642 [2018-11-18 10:08:48,335 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2586 states. [2018-11-18 10:08:48,343 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2586 to 2559. [2018-11-18 10:08:48,343 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2559 states. [2018-11-18 10:08:48,345 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2559 states to 2559 states and 2569 transitions. [2018-11-18 10:08:48,345 INFO L78 Accepts]: Start accepts. Automaton has 2559 states and 2569 transitions. Word has length 2087 [2018-11-18 10:08:48,346 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:08:48,346 INFO L480 AbstractCegarLoop]: Abstraction has 2559 states and 2569 transitions. [2018-11-18 10:08:48,346 INFO L481 AbstractCegarLoop]: Interpolant automaton has 54 states. [2018-11-18 10:08:48,347 INFO L276 IsEmpty]: Start isEmpty. Operand 2559 states and 2569 transitions. [2018-11-18 10:08:48,365 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2239 [2018-11-18 10:08:48,365 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:08:48,366 INFO L375 BasicCegarLoop]: trace histogram [345, 322, 321, 321, 321, 321, 24, 24, 24, 24, 23, 23, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:08:48,366 INFO L423 AbstractCegarLoop]: === Iteration 65 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:08:48,366 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:08:48,366 INFO L82 PathProgramCache]: Analyzing trace with hash 2057025806, now seen corresponding path program 50 times [2018-11-18 10:08:48,366 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:08:48,366 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:08:48,367 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:08:48,367 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:08:48,367 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:08:48,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:08:50,663 INFO L134 CoverageAnalysis]: Checked inductivity of 327316 backedges. 78324 proven. 7901 refuted. 0 times theorem prover too weak. 241091 trivial. 0 not checked. [2018-11-18 10:08:50,663 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:08:50,663 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:08:50,670 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-18 10:08:50,994 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 10:08:50,995 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:08:51,010 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:08:53,403 INFO L134 CoverageAnalysis]: Checked inductivity of 327316 backedges. 117534 proven. 1430 refuted. 0 times theorem prover too weak. 208352 trivial. 0 not checked. [2018-11-18 10:08:53,420 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:08:53,420 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 48] total 101 [2018-11-18 10:08:53,421 INFO L459 AbstractCegarLoop]: Interpolant automaton has 101 states [2018-11-18 10:08:53,422 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 101 interpolants. [2018-11-18 10:08:53,422 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1538, Invalid=8562, Unknown=0, NotChecked=0, Total=10100 [2018-11-18 10:08:53,422 INFO L87 Difference]: Start difference. First operand 2559 states and 2569 transitions. Second operand 101 states. [2018-11-18 10:08:55,931 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:08:55,931 INFO L93 Difference]: Finished difference Result 2267 states and 2270 transitions. [2018-11-18 10:08:55,931 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 121 states. [2018-11-18 10:08:55,931 INFO L78 Accepts]: Start accepts. Automaton has 101 states. Word has length 2238 [2018-11-18 10:08:55,933 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:08:55,935 INFO L225 Difference]: With dead ends: 2267 [2018-11-18 10:08:55,935 INFO L226 Difference]: Without dead ends: 2258 [2018-11-18 10:08:55,936 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2385 GetRequests, 2194 SyntacticMatches, 0 SemanticMatches, 191 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11806 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=5588, Invalid=31468, Unknown=0, NotChecked=0, Total=37056 [2018-11-18 10:08:55,937 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2258 states. [2018-11-18 10:08:55,944 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2258 to 2254. [2018-11-18 10:08:55,944 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2254 states. [2018-11-18 10:08:55,946 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2254 states to 2254 states and 2257 transitions. [2018-11-18 10:08:55,946 INFO L78 Accepts]: Start accepts. Automaton has 2254 states and 2257 transitions. Word has length 2238 [2018-11-18 10:08:55,947 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:08:55,947 INFO L480 AbstractCegarLoop]: Abstraction has 2254 states and 2257 transitions. [2018-11-18 10:08:55,947 INFO L481 AbstractCegarLoop]: Interpolant automaton has 101 states. [2018-11-18 10:08:55,947 INFO L276 IsEmpty]: Start isEmpty. Operand 2254 states and 2257 transitions. [2018-11-18 10:08:55,966 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2245 [2018-11-18 10:08:55,966 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:08:55,966 INFO L375 BasicCegarLoop]: trace histogram [346, 323, 322, 322, 322, 322, 24, 24, 24, 24, 23, 23, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:08:55,967 INFO L423 AbstractCegarLoop]: === Iteration 66 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:08:55,967 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:08:55,967 INFO L82 PathProgramCache]: Analyzing trace with hash -1417323770, now seen corresponding path program 51 times [2018-11-18 10:08:55,967 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:08:55,967 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:08:55,968 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:08:55,968 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:08:55,968 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:08:56,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:08:58,269 INFO L134 CoverageAnalysis]: Checked inductivity of 329291 backedges. 83007 proven. 5043 refuted. 0 times theorem prover too weak. 241241 trivial. 0 not checked. [2018-11-18 10:08:58,269 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:08:58,269 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:08:58,276 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 10:08:59,218 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 25 check-sat command(s) [2018-11-18 10:08:59,219 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:08:59,232 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:09:01,146 INFO L134 CoverageAnalysis]: Checked inductivity of 329291 backedges. 81444 proven. 5019 refuted. 0 times theorem prover too weak. 242828 trivial. 0 not checked. [2018-11-18 10:09:01,162 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:09:01,163 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 33] total 83 [2018-11-18 10:09:01,164 INFO L459 AbstractCegarLoop]: Interpolant automaton has 83 states [2018-11-18 10:09:01,164 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 83 interpolants. [2018-11-18 10:09:01,164 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1346, Invalid=5460, Unknown=0, NotChecked=0, Total=6806 [2018-11-18 10:09:01,164 INFO L87 Difference]: Start difference. First operand 2254 states and 2257 transitions. Second operand 83 states. [2018-11-18 10:09:02,934 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:09:02,934 INFO L93 Difference]: Finished difference Result 2424 states and 2429 transitions. [2018-11-18 10:09:02,934 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 81 states. [2018-11-18 10:09:02,934 INFO L78 Accepts]: Start accepts. Automaton has 83 states. Word has length 2244 [2018-11-18 10:09:02,936 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:09:02,938 INFO L225 Difference]: With dead ends: 2424 [2018-11-18 10:09:02,938 INFO L226 Difference]: Without dead ends: 2424 [2018-11-18 10:09:02,939 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2372 GetRequests, 2218 SyntacticMatches, 0 SemanticMatches, 154 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7385 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=5804, Invalid=18376, Unknown=0, NotChecked=0, Total=24180 [2018-11-18 10:09:02,940 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2424 states. [2018-11-18 10:09:02,947 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2424 to 2417. [2018-11-18 10:09:02,947 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2417 states. [2018-11-18 10:09:02,949 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2417 states to 2417 states and 2422 transitions. [2018-11-18 10:09:02,949 INFO L78 Accepts]: Start accepts. Automaton has 2417 states and 2422 transitions. Word has length 2244 [2018-11-18 10:09:02,950 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:09:02,951 INFO L480 AbstractCegarLoop]: Abstraction has 2417 states and 2422 transitions. [2018-11-18 10:09:02,951 INFO L481 AbstractCegarLoop]: Interpolant automaton has 83 states. [2018-11-18 10:09:02,951 INFO L276 IsEmpty]: Start isEmpty. Operand 2417 states and 2422 transitions. [2018-11-18 10:09:02,969 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2251 [2018-11-18 10:09:02,969 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:09:02,970 INFO L375 BasicCegarLoop]: trace histogram [347, 324, 323, 323, 323, 323, 24, 24, 24, 24, 23, 23, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:09:02,970 INFO L423 AbstractCegarLoop]: === Iteration 67 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:09:02,970 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:09:02,970 INFO L82 PathProgramCache]: Analyzing trace with hash -1667335090, now seen corresponding path program 52 times [2018-11-18 10:09:02,970 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:09:02,970 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:09:02,971 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:09:02,971 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:09:02,971 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:09:03,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:09:04,819 INFO L134 CoverageAnalysis]: Checked inductivity of 331272 backedges. 46062 proven. 1864 refuted. 0 times theorem prover too weak. 283346 trivial. 0 not checked. [2018-11-18 10:09:04,820 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:09:04,820 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:09:04,827 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 10:09:07,554 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 10:09:07,554 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:09:07,577 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:09:09,189 INFO L134 CoverageAnalysis]: Checked inductivity of 331272 backedges. 45103 proven. 1728 refuted. 0 times theorem prover too weak. 284441 trivial. 0 not checked. [2018-11-18 10:09:09,210 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:09:09,211 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 26] total 62 [2018-11-18 10:09:09,211 INFO L459 AbstractCegarLoop]: Interpolant automaton has 63 states [2018-11-18 10:09:09,212 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 63 interpolants. [2018-11-18 10:09:09,212 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=461, Invalid=3445, Unknown=0, NotChecked=0, Total=3906 [2018-11-18 10:09:09,212 INFO L87 Difference]: Start difference. First operand 2417 states and 2422 transitions. Second operand 63 states. [2018-11-18 10:09:11,592 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:09:11,592 INFO L93 Difference]: Finished difference Result 2767 states and 2778 transitions. [2018-11-18 10:09:11,592 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 81 states. [2018-11-18 10:09:11,592 INFO L78 Accepts]: Start accepts. Automaton has 63 states. Word has length 2250 [2018-11-18 10:09:11,593 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:09:11,595 INFO L225 Difference]: With dead ends: 2767 [2018-11-18 10:09:11,595 INFO L226 Difference]: Without dead ends: 2767 [2018-11-18 10:09:11,595 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2315 GetRequests, 2225 SyntacticMatches, 0 SemanticMatches, 90 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1671 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=884, Invalid=7488, Unknown=0, NotChecked=0, Total=8372 [2018-11-18 10:09:11,596 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2767 states. [2018-11-18 10:09:11,606 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2767 to 2740. [2018-11-18 10:09:11,606 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2740 states. [2018-11-18 10:09:11,608 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2740 states to 2740 states and 2750 transitions. [2018-11-18 10:09:11,608 INFO L78 Accepts]: Start accepts. Automaton has 2740 states and 2750 transitions. Word has length 2250 [2018-11-18 10:09:11,609 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:09:11,609 INFO L480 AbstractCegarLoop]: Abstraction has 2740 states and 2750 transitions. [2018-11-18 10:09:11,609 INFO L481 AbstractCegarLoop]: Interpolant automaton has 63 states. [2018-11-18 10:09:11,609 INFO L276 IsEmpty]: Start isEmpty. Operand 2740 states and 2750 transitions. [2018-11-18 10:09:11,629 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2408 [2018-11-18 10:09:11,629 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:09:11,630 INFO L375 BasicCegarLoop]: trace histogram [372, 348, 347, 347, 347, 347, 25, 25, 25, 25, 24, 24, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:09:11,630 INFO L423 AbstractCegarLoop]: === Iteration 68 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:09:11,630 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:09:11,630 INFO L82 PathProgramCache]: Analyzing trace with hash 1963665113, now seen corresponding path program 53 times [2018-11-18 10:09:11,630 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:09:11,630 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:09:11,631 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:09:11,631 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:09:11,631 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:09:11,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:09:14,193 INFO L134 CoverageAnalysis]: Checked inductivity of 381615 backedges. 88727 proven. 8604 refuted. 0 times theorem prover too weak. 284284 trivial. 0 not checked. [2018-11-18 10:09:14,194 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:09:14,194 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:09:14,200 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-18 10:09:20,234 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 58 check-sat command(s) [2018-11-18 10:09:20,234 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:09:20,264 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:09:23,107 INFO L134 CoverageAnalysis]: Checked inductivity of 381615 backedges. 132738 proven. 9358 refuted. 0 times theorem prover too weak. 239519 trivial. 0 not checked. [2018-11-18 10:09:23,130 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:09:23,131 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 54] total 109 [2018-11-18 10:09:23,131 INFO L459 AbstractCegarLoop]: Interpolant automaton has 109 states [2018-11-18 10:09:23,131 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 109 interpolants. [2018-11-18 10:09:23,132 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1639, Invalid=10133, Unknown=0, NotChecked=0, Total=11772 [2018-11-18 10:09:23,132 INFO L87 Difference]: Start difference. First operand 2740 states and 2750 transitions. Second operand 109 states. [2018-11-18 10:09:27,014 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:09:27,014 INFO L93 Difference]: Finished difference Result 2436 states and 2439 transitions. [2018-11-18 10:09:27,014 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 131 states. [2018-11-18 10:09:27,015 INFO L78 Accepts]: Start accepts. Automaton has 109 states. Word has length 2407 [2018-11-18 10:09:27,015 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:09:27,017 INFO L225 Difference]: With dead ends: 2436 [2018-11-18 10:09:27,017 INFO L226 Difference]: Without dead ends: 2427 [2018-11-18 10:09:27,019 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2588 GetRequests, 2358 SyntacticMatches, 0 SemanticMatches, 230 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17950 ImplicationChecksByTransitivity, 3.7s TimeCoverageRelationStatistics Valid=7839, Invalid=45753, Unknown=0, NotChecked=0, Total=53592 [2018-11-18 10:09:27,020 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2427 states. [2018-11-18 10:09:27,028 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2427 to 2423. [2018-11-18 10:09:27,028 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2423 states. [2018-11-18 10:09:27,030 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2423 states to 2423 states and 2426 transitions. [2018-11-18 10:09:27,030 INFO L78 Accepts]: Start accepts. Automaton has 2423 states and 2426 transitions. Word has length 2407 [2018-11-18 10:09:27,031 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:09:27,031 INFO L480 AbstractCegarLoop]: Abstraction has 2423 states and 2426 transitions. [2018-11-18 10:09:27,031 INFO L481 AbstractCegarLoop]: Interpolant automaton has 109 states. [2018-11-18 10:09:27,031 INFO L276 IsEmpty]: Start isEmpty. Operand 2423 states and 2426 transitions. [2018-11-18 10:09:27,051 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2414 [2018-11-18 10:09:27,051 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:09:27,051 INFO L375 BasicCegarLoop]: trace histogram [373, 349, 348, 348, 348, 348, 25, 25, 25, 25, 24, 24, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:09:27,051 INFO L423 AbstractCegarLoop]: === Iteration 69 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:09:27,051 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:09:27,052 INFO L82 PathProgramCache]: Analyzing trace with hash 1678426257, now seen corresponding path program 54 times [2018-11-18 10:09:27,052 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:09:27,052 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:09:27,052 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:09:27,052 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:09:27,052 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:09:27,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:09:29,654 INFO L134 CoverageAnalysis]: Checked inductivity of 383748 backedges. 93829 proven. 5478 refuted. 0 times theorem prover too weak. 284441 trivial. 0 not checked. [2018-11-18 10:09:29,654 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:09:29,654 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:09:29,661 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-18 10:09:36,191 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 51 check-sat command(s) [2018-11-18 10:09:36,192 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:09:36,212 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:09:38,371 INFO L134 CoverageAnalysis]: Checked inductivity of 383748 backedges. 92126 proven. 5453 refuted. 0 times theorem prover too weak. 286169 trivial. 0 not checked. [2018-11-18 10:09:38,391 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:09:38,391 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 34] total 86 [2018-11-18 10:09:38,392 INFO L459 AbstractCegarLoop]: Interpolant automaton has 86 states [2018-11-18 10:09:38,393 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 86 interpolants. [2018-11-18 10:09:38,393 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1451, Invalid=5859, Unknown=0, NotChecked=0, Total=7310 [2018-11-18 10:09:38,393 INFO L87 Difference]: Start difference. First operand 2423 states and 2426 transitions. Second operand 86 states. [2018-11-18 10:09:40,389 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:09:40,390 INFO L93 Difference]: Finished difference Result 2599 states and 2604 transitions. [2018-11-18 10:09:40,390 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 84 states. [2018-11-18 10:09:40,390 INFO L78 Accepts]: Start accepts. Automaton has 86 states. Word has length 2413 [2018-11-18 10:09:40,391 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:09:40,393 INFO L225 Difference]: With dead ends: 2599 [2018-11-18 10:09:40,393 INFO L226 Difference]: Without dead ends: 2599 [2018-11-18 10:09:40,394 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2546 GetRequests, 2386 SyntacticMatches, 0 SemanticMatches, 160 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7993 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=6269, Invalid=19813, Unknown=0, NotChecked=0, Total=26082 [2018-11-18 10:09:40,395 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2599 states. [2018-11-18 10:09:40,403 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2599 to 2592. [2018-11-18 10:09:40,403 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2592 states. [2018-11-18 10:09:40,404 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2592 states to 2592 states and 2597 transitions. [2018-11-18 10:09:40,404 INFO L78 Accepts]: Start accepts. Automaton has 2592 states and 2597 transitions. Word has length 2413 [2018-11-18 10:09:40,405 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:09:40,405 INFO L480 AbstractCegarLoop]: Abstraction has 2592 states and 2597 transitions. [2018-11-18 10:09:40,405 INFO L481 AbstractCegarLoop]: Interpolant automaton has 86 states. [2018-11-18 10:09:40,405 INFO L276 IsEmpty]: Start isEmpty. Operand 2592 states and 2597 transitions. [2018-11-18 10:09:40,426 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2420 [2018-11-18 10:09:40,426 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:09:40,426 INFO L375 BasicCegarLoop]: trace histogram [374, 350, 349, 349, 349, 349, 25, 25, 25, 25, 24, 24, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:09:40,427 INFO L423 AbstractCegarLoop]: === Iteration 70 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:09:40,427 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:09:40,427 INFO L82 PathProgramCache]: Analyzing trace with hash -171601511, now seen corresponding path program 55 times [2018-11-18 10:09:40,427 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:09:40,427 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:09:40,427 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:09:40,428 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:09:40,428 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:09:40,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:09:42,357 INFO L134 CoverageAnalysis]: Checked inductivity of 385887 backedges. 50966 proven. 2029 refuted. 0 times theorem prover too weak. 332892 trivial. 0 not checked. [2018-11-18 10:09:42,357 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:09:42,357 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:09:42,366 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:09:42,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:09:42,717 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:09:44,450 INFO L134 CoverageAnalysis]: Checked inductivity of 385887 backedges. 50820 proven. 1875 refuted. 0 times theorem prover too weak. 333192 trivial. 0 not checked. [2018-11-18 10:09:44,480 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:09:44,481 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 27] total 57 [2018-11-18 10:09:44,481 INFO L459 AbstractCegarLoop]: Interpolant automaton has 58 states [2018-11-18 10:09:44,481 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 58 interpolants. [2018-11-18 10:09:44,481 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=441, Invalid=2865, Unknown=0, NotChecked=0, Total=3306 [2018-11-18 10:09:44,482 INFO L87 Difference]: Start difference. First operand 2592 states and 2597 transitions. Second operand 58 states. [2018-11-18 10:09:47,018 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:09:47,018 INFO L93 Difference]: Finished difference Result 2954 states and 2965 transitions. [2018-11-18 10:09:47,018 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 84 states. [2018-11-18 10:09:47,018 INFO L78 Accepts]: Start accepts. Automaton has 58 states. Word has length 2419 [2018-11-18 10:09:47,019 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:09:47,021 INFO L225 Difference]: With dead ends: 2954 [2018-11-18 10:09:47,021 INFO L226 Difference]: Without dead ends: 2954 [2018-11-18 10:09:47,022 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2479 GetRequests, 2393 SyntacticMatches, 0 SemanticMatches, 86 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1282 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=727, Invalid=6929, Unknown=0, NotChecked=0, Total=7656 [2018-11-18 10:09:47,022 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2954 states. [2018-11-18 10:09:47,034 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2954 to 2927. [2018-11-18 10:09:47,034 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2927 states. [2018-11-18 10:09:47,037 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2927 states to 2927 states and 2937 transitions. [2018-11-18 10:09:47,037 INFO L78 Accepts]: Start accepts. Automaton has 2927 states and 2937 transitions. Word has length 2419 [2018-11-18 10:09:47,038 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:09:47,038 INFO L480 AbstractCegarLoop]: Abstraction has 2927 states and 2937 transitions. [2018-11-18 10:09:47,038 INFO L481 AbstractCegarLoop]: Interpolant automaton has 58 states. [2018-11-18 10:09:47,038 INFO L276 IsEmpty]: Start isEmpty. Operand 2927 states and 2937 transitions. [2018-11-18 10:09:47,061 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2583 [2018-11-18 10:09:47,061 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:09:47,062 INFO L375 BasicCegarLoop]: trace histogram [400, 375, 374, 374, 374, 374, 26, 26, 26, 26, 25, 25, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:09:47,062 INFO L423 AbstractCegarLoop]: === Iteration 71 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:09:47,062 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:09:47,062 INFO L82 PathProgramCache]: Analyzing trace with hash 272826726, now seen corresponding path program 56 times [2018-11-18 10:09:47,062 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:09:47,062 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:09:47,063 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:09:47,063 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:09:47,063 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:09:47,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:09:49,964 INFO L134 CoverageAnalysis]: Checked inductivity of 442378 backedges. 100013 proven. 9337 refuted. 0 times theorem prover too weak. 333028 trivial. 0 not checked. [2018-11-18 10:09:49,964 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:09:49,964 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:09:49,972 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-18 10:09:50,325 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 10:09:50,325 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:09:50,347 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:09:53,331 INFO L134 CoverageAnalysis]: Checked inductivity of 442378 backedges. 150158 proven. 1704 refuted. 0 times theorem prover too weak. 290516 trivial. 0 not checked. [2018-11-18 10:09:53,348 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:09:53,349 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 52] total 109 [2018-11-18 10:09:53,349 INFO L459 AbstractCegarLoop]: Interpolant automaton has 109 states [2018-11-18 10:09:53,349 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 109 interpolants. [2018-11-18 10:09:53,350 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1795, Invalid=9977, Unknown=0, NotChecked=0, Total=11772 [2018-11-18 10:09:53,350 INFO L87 Difference]: Start difference. First operand 2927 states and 2937 transitions. Second operand 109 states. [2018-11-18 10:09:56,476 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:09:56,477 INFO L93 Difference]: Finished difference Result 2611 states and 2614 transitions. [2018-11-18 10:09:56,477 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 131 states. [2018-11-18 10:09:56,477 INFO L78 Accepts]: Start accepts. Automaton has 109 states. Word has length 2582 [2018-11-18 10:09:56,478 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:09:56,480 INFO L225 Difference]: With dead ends: 2611 [2018-11-18 10:09:56,480 INFO L226 Difference]: Without dead ends: 2602 [2018-11-18 10:09:56,481 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2741 GetRequests, 2534 SyntacticMatches, 0 SemanticMatches, 207 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13934 ImplicationChecksByTransitivity, 3.1s TimeCoverageRelationStatistics Valid=6545, Invalid=36927, Unknown=0, NotChecked=0, Total=43472 [2018-11-18 10:09:56,482 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2602 states. [2018-11-18 10:09:56,490 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2602 to 2598. [2018-11-18 10:09:56,490 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2598 states. [2018-11-18 10:09:56,491 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2598 states to 2598 states and 2601 transitions. [2018-11-18 10:09:56,491 INFO L78 Accepts]: Start accepts. Automaton has 2598 states and 2601 transitions. Word has length 2582 [2018-11-18 10:09:56,492 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:09:56,492 INFO L480 AbstractCegarLoop]: Abstraction has 2598 states and 2601 transitions. [2018-11-18 10:09:56,492 INFO L481 AbstractCegarLoop]: Interpolant automaton has 109 states. [2018-11-18 10:09:56,492 INFO L276 IsEmpty]: Start isEmpty. Operand 2598 states and 2601 transitions. [2018-11-18 10:09:56,515 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2589 [2018-11-18 10:09:56,515 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:09:56,515 INFO L375 BasicCegarLoop]: trace histogram [401, 376, 375, 375, 375, 375, 26, 26, 26, 26, 25, 25, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:09:56,515 INFO L423 AbstractCegarLoop]: === Iteration 72 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:09:56,516 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:09:56,516 INFO L82 PathProgramCache]: Analyzing trace with hash 500791646, now seen corresponding path program 57 times [2018-11-18 10:09:56,516 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:09:56,516 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:09:56,517 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:09:56,517 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:09:56,517 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:09:56,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:09:59,393 INFO L134 CoverageAnalysis]: Checked inductivity of 444675 backedges. 105552 proven. 5931 refuted. 0 times theorem prover too weak. 333192 trivial. 0 not checked. [2018-11-18 10:09:59,393 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:09:59,393 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:09:59,401 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 10:10:00,957 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 27 check-sat command(s) [2018-11-18 10:10:00,957 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:10:00,972 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:10:03,154 INFO L134 CoverageAnalysis]: Checked inductivity of 444675 backedges. 56841 proven. 2028 refuted. 0 times theorem prover too weak. 385806 trivial. 0 not checked. [2018-11-18 10:10:03,171 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:10:03,172 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 29] total 88 [2018-11-18 10:10:03,172 INFO L459 AbstractCegarLoop]: Interpolant automaton has 88 states [2018-11-18 10:10:03,172 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 88 interpolants. [2018-11-18 10:10:03,173 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1204, Invalid=6452, Unknown=0, NotChecked=0, Total=7656 [2018-11-18 10:10:03,173 INFO L87 Difference]: Start difference. First operand 2598 states and 2601 transitions. Second operand 88 states. [2018-11-18 10:10:05,710 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:10:05,710 INFO L93 Difference]: Finished difference Result 2789 states and 2795 transitions. [2018-11-18 10:10:05,710 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 89 states. [2018-11-18 10:10:05,710 INFO L78 Accepts]: Start accepts. Automaton has 88 states. Word has length 2588 [2018-11-18 10:10:05,711 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:10:05,712 INFO L225 Difference]: With dead ends: 2789 [2018-11-18 10:10:05,713 INFO L226 Difference]: Without dead ends: 2789 [2018-11-18 10:10:05,713 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2727 GetRequests, 2561 SyntacticMatches, 0 SemanticMatches, 166 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6851 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=6425, Invalid=21631, Unknown=0, NotChecked=0, Total=28056 [2018-11-18 10:10:05,714 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2789 states. [2018-11-18 10:10:05,721 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2789 to 2779. [2018-11-18 10:10:05,721 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2779 states. [2018-11-18 10:10:05,723 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2779 states to 2779 states and 2785 transitions. [2018-11-18 10:10:05,723 INFO L78 Accepts]: Start accepts. Automaton has 2779 states and 2785 transitions. Word has length 2588 [2018-11-18 10:10:05,724 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:10:05,724 INFO L480 AbstractCegarLoop]: Abstraction has 2779 states and 2785 transitions. [2018-11-18 10:10:05,724 INFO L481 AbstractCegarLoop]: Interpolant automaton has 88 states. [2018-11-18 10:10:05,724 INFO L276 IsEmpty]: Start isEmpty. Operand 2779 states and 2785 transitions. [2018-11-18 10:10:05,747 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2601 [2018-11-18 10:10:05,747 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:10:05,747 INFO L375 BasicCegarLoop]: trace histogram [403, 378, 377, 377, 377, 377, 26, 26, 26, 26, 25, 25, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:10:05,748 INFO L423 AbstractCegarLoop]: === Iteration 73 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:10:05,748 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:10:05,748 INFO L82 PathProgramCache]: Analyzing trace with hash -762262882, now seen corresponding path program 58 times [2018-11-18 10:10:05,748 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:10:05,748 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:10:05,749 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:10:05,749 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:10:05,749 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:10:05,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:10:08,460 INFO L134 CoverageAnalysis]: Checked inductivity of 449287 backedges. 61282 proven. 2255 refuted. 0 times theorem prover too weak. 385750 trivial. 0 not checked. [2018-11-18 10:10:08,460 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:10:08,460 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:10:08,469 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 10:10:08,767 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 10:10:08,767 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:10:08,785 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:10:11,604 INFO L134 CoverageAnalysis]: Checked inductivity of 449287 backedges. 61053 proven. 7582 refuted. 0 times theorem prover too weak. 380652 trivial. 0 not checked. [2018-11-18 10:10:11,621 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:10:11,621 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 61] total 91 [2018-11-18 10:10:11,622 INFO L459 AbstractCegarLoop]: Interpolant automaton has 91 states [2018-11-18 10:10:11,622 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 91 interpolants. [2018-11-18 10:10:11,623 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1724, Invalid=6466, Unknown=0, NotChecked=0, Total=8190 [2018-11-18 10:10:11,623 INFO L87 Difference]: Start difference. First operand 2779 states and 2785 transitions. Second operand 91 states. [2018-11-18 10:10:13,616 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:10:13,616 INFO L93 Difference]: Finished difference Result 3137 states and 3147 transitions. [2018-11-18 10:10:13,616 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 89 states. [2018-11-18 10:10:13,616 INFO L78 Accepts]: Start accepts. Automaton has 91 states. Word has length 2600 [2018-11-18 10:10:13,618 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:10:13,621 INFO L225 Difference]: With dead ends: 3137 [2018-11-18 10:10:13,621 INFO L226 Difference]: Without dead ends: 3137 [2018-11-18 10:10:13,622 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2712 GetRequests, 2568 SyntacticMatches, 0 SemanticMatches, 144 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3950 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=4805, Invalid=16365, Unknown=0, NotChecked=0, Total=21170 [2018-11-18 10:10:13,623 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3137 states. [2018-11-18 10:10:13,637 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3137 to 3126. [2018-11-18 10:10:13,637 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3126 states. [2018-11-18 10:10:13,640 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3126 states to 3126 states and 3136 transitions. [2018-11-18 10:10:13,640 INFO L78 Accepts]: Start accepts. Automaton has 3126 states and 3136 transitions. Word has length 2600 [2018-11-18 10:10:13,641 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:10:13,642 INFO L480 AbstractCegarLoop]: Abstraction has 3126 states and 3136 transitions. [2018-11-18 10:10:13,642 INFO L481 AbstractCegarLoop]: Interpolant automaton has 91 states. [2018-11-18 10:10:13,642 INFO L276 IsEmpty]: Start isEmpty. Operand 3126 states and 3136 transitions. [2018-11-18 10:10:13,672 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2764 [2018-11-18 10:10:13,672 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:10:13,673 INFO L375 BasicCegarLoop]: trace histogram [429, 403, 402, 402, 402, 402, 27, 27, 27, 27, 26, 26, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:10:13,673 INFO L423 AbstractCegarLoop]: === Iteration 74 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:10:13,673 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:10:13,673 INFO L82 PathProgramCache]: Analyzing trace with hash 1862136561, now seen corresponding path program 59 times [2018-11-18 10:10:13,673 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:10:13,673 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:10:13,674 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:10:13,674 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:10:13,674 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:10:13,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:10:16,876 INFO L134 CoverageAnalysis]: Checked inductivity of 510097 backedges. 112218 proven. 10100 refuted. 0 times theorem prover too weak. 387779 trivial. 0 not checked. [2018-11-18 10:10:16,876 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:10:16,876 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:10:16,883 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-18 10:10:25,399 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 60 check-sat command(s) [2018-11-18 10:10:25,399 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:10:25,435 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:10:28,960 INFO L134 CoverageAnalysis]: Checked inductivity of 510097 backedges. 168020 proven. 10996 refuted. 0 times theorem prover too weak. 331081 trivial. 0 not checked. [2018-11-18 10:10:28,985 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:10:28,986 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 58] total 117 [2018-11-18 10:10:28,987 INFO L459 AbstractCegarLoop]: Interpolant automaton has 117 states [2018-11-18 10:10:28,987 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 117 interpolants. [2018-11-18 10:10:28,988 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1902, Invalid=11670, Unknown=0, NotChecked=0, Total=13572 [2018-11-18 10:10:28,988 INFO L87 Difference]: Start difference. First operand 3126 states and 3136 transitions. Second operand 117 states. [2018-11-18 10:10:32,787 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:10:32,787 INFO L93 Difference]: Finished difference Result 2792 states and 2795 transitions. [2018-11-18 10:10:32,788 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 141 states. [2018-11-18 10:10:32,788 INFO L78 Accepts]: Start accepts. Automaton has 117 states. Word has length 2763 [2018-11-18 10:10:32,789 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:10:32,791 INFO L225 Difference]: With dead ends: 2792 [2018-11-18 10:10:32,792 INFO L226 Difference]: Without dead ends: 2783 [2018-11-18 10:10:32,796 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2958 GetRequests, 2710 SyntacticMatches, 0 SemanticMatches, 248 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20985 ImplicationChecksByTransitivity, 4.2s TimeCoverageRelationStatistics Valid=9105, Invalid=53145, Unknown=0, NotChecked=0, Total=62250 [2018-11-18 10:10:32,797 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2783 states. [2018-11-18 10:10:32,810 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2783 to 2779. [2018-11-18 10:10:32,810 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2779 states. [2018-11-18 10:10:32,812 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2779 states to 2779 states and 2782 transitions. [2018-11-18 10:10:32,812 INFO L78 Accepts]: Start accepts. Automaton has 2779 states and 2782 transitions. Word has length 2763 [2018-11-18 10:10:32,814 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:10:32,814 INFO L480 AbstractCegarLoop]: Abstraction has 2779 states and 2782 transitions. [2018-11-18 10:10:32,814 INFO L481 AbstractCegarLoop]: Interpolant automaton has 117 states. [2018-11-18 10:10:32,814 INFO L276 IsEmpty]: Start isEmpty. Operand 2779 states and 2782 transitions. [2018-11-18 10:10:32,842 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2770 [2018-11-18 10:10:32,842 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:10:32,843 INFO L375 BasicCegarLoop]: trace histogram [430, 404, 403, 403, 403, 403, 27, 27, 27, 27, 26, 26, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:10:32,843 INFO L423 AbstractCegarLoop]: === Iteration 75 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:10:32,843 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:10:32,843 INFO L82 PathProgramCache]: Analyzing trace with hash 1304072873, now seen corresponding path program 60 times [2018-11-18 10:10:32,844 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:10:32,844 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:10:32,844 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:10:32,844 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:10:32,844 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:10:33,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:10:36,092 INFO L134 CoverageAnalysis]: Checked inductivity of 512564 backedges. 118212 proven. 6402 refuted. 0 times theorem prover too weak. 387950 trivial. 0 not checked. [2018-11-18 10:10:36,092 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:10:36,092 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:10:36,119 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-18 10:10:50,376 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 55 check-sat command(s) [2018-11-18 10:10:50,376 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:10:50,401 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:10:53,152 INFO L134 CoverageAnalysis]: Checked inductivity of 512564 backedges. 116211 proven. 6375 refuted. 0 times theorem prover too weak. 389978 trivial. 0 not checked. [2018-11-18 10:10:53,173 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:10:53,174 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 36] total 92 [2018-11-18 10:10:53,174 INFO L459 AbstractCegarLoop]: Interpolant automaton has 92 states [2018-11-18 10:10:53,174 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 92 interpolants. [2018-11-18 10:10:53,175 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1673, Invalid=6699, Unknown=0, NotChecked=0, Total=8372 [2018-11-18 10:10:53,175 INFO L87 Difference]: Start difference. First operand 2779 states and 2782 transitions. Second operand 92 states. [2018-11-18 10:10:55,218 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:10:55,218 INFO L93 Difference]: Finished difference Result 2967 states and 2972 transitions. [2018-11-18 10:10:55,218 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 90 states. [2018-11-18 10:10:55,218 INFO L78 Accepts]: Start accepts. Automaton has 92 states. Word has length 2769 [2018-11-18 10:10:55,219 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:10:55,221 INFO L225 Difference]: With dead ends: 2967 [2018-11-18 10:10:55,221 INFO L226 Difference]: Without dead ends: 2967 [2018-11-18 10:10:55,223 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2912 GetRequests, 2740 SyntacticMatches, 0 SemanticMatches, 172 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9281 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=7253, Invalid=22849, Unknown=0, NotChecked=0, Total=30102 [2018-11-18 10:10:55,224 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2967 states. [2018-11-18 10:10:55,232 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2967 to 2960. [2018-11-18 10:10:55,232 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2960 states. [2018-11-18 10:10:55,234 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2960 states to 2960 states and 2965 transitions. [2018-11-18 10:10:55,234 INFO L78 Accepts]: Start accepts. Automaton has 2960 states and 2965 transitions. Word has length 2769 [2018-11-18 10:10:55,235 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:10:55,235 INFO L480 AbstractCegarLoop]: Abstraction has 2960 states and 2965 transitions. [2018-11-18 10:10:55,235 INFO L481 AbstractCegarLoop]: Interpolant automaton has 92 states. [2018-11-18 10:10:55,235 INFO L276 IsEmpty]: Start isEmpty. Operand 2960 states and 2965 transitions. [2018-11-18 10:10:55,261 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2776 [2018-11-18 10:10:55,261 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:10:55,261 INFO L375 BasicCegarLoop]: trace histogram [431, 405, 404, 404, 404, 404, 27, 27, 27, 27, 26, 26, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:10:55,262 INFO L423 AbstractCegarLoop]: === Iteration 76 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:10:55,262 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:10:55,262 INFO L82 PathProgramCache]: Analyzing trace with hash 974846385, now seen corresponding path program 61 times [2018-11-18 10:10:55,262 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:10:55,262 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:10:55,262 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:10:55,262 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:10:55,262 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:10:55,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:10:57,723 INFO L134 CoverageAnalysis]: Checked inductivity of 515037 backedges. 63819 proven. 2380 refuted. 0 times theorem prover too weak. 448838 trivial. 0 not checked. [2018-11-18 10:10:57,723 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:10:57,723 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:10:57,731 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:10:58,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:10:58,109 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:11:00,408 INFO L134 CoverageAnalysis]: Checked inductivity of 515037 backedges. 63661 proven. 2187 refuted. 0 times theorem prover too weak. 449189 trivial. 0 not checked. [2018-11-18 10:11:00,426 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:11:00,426 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 29] total 61 [2018-11-18 10:11:00,427 INFO L459 AbstractCegarLoop]: Interpolant automaton has 62 states [2018-11-18 10:11:00,427 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2018-11-18 10:11:00,427 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=502, Invalid=3280, Unknown=0, NotChecked=0, Total=3782 [2018-11-18 10:11:00,427 INFO L87 Difference]: Start difference. First operand 2960 states and 2965 transitions. Second operand 62 states. [2018-11-18 10:11:02,989 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:11:02,989 INFO L93 Difference]: Finished difference Result 3346 states and 3357 transitions. [2018-11-18 10:11:02,990 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 90 states. [2018-11-18 10:11:02,990 INFO L78 Accepts]: Start accepts. Automaton has 62 states. Word has length 2775 [2018-11-18 10:11:02,991 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:11:02,993 INFO L225 Difference]: With dead ends: 3346 [2018-11-18 10:11:02,993 INFO L226 Difference]: Without dead ends: 3346 [2018-11-18 10:11:02,994 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 2839 GetRequests, 2747 SyntacticMatches, 0 SemanticMatches, 92 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1465 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=808, Invalid=7934, Unknown=0, NotChecked=0, Total=8742 [2018-11-18 10:11:02,994 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3346 states. [2018-11-18 10:11:03,009 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3346 to 3319. [2018-11-18 10:11:03,009 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3319 states. [2018-11-18 10:11:03,011 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3319 states to 3319 states and 3329 transitions. [2018-11-18 10:11:03,011 INFO L78 Accepts]: Start accepts. Automaton has 3319 states and 3329 transitions. Word has length 2775 [2018-11-18 10:11:03,012 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:11:03,012 INFO L480 AbstractCegarLoop]: Abstraction has 3319 states and 3329 transitions. [2018-11-18 10:11:03,012 INFO L481 AbstractCegarLoop]: Interpolant automaton has 62 states. [2018-11-18 10:11:03,012 INFO L276 IsEmpty]: Start isEmpty. Operand 3319 states and 3329 transitions. [2018-11-18 10:11:03,041 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2951 [2018-11-18 10:11:03,041 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:11:03,042 INFO L375 BasicCegarLoop]: trace histogram [459, 432, 431, 431, 431, 431, 28, 28, 28, 28, 27, 27, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:11:03,042 INFO L423 AbstractCegarLoop]: === Iteration 77 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:11:03,042 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:11:03,042 INFO L82 PathProgramCache]: Analyzing trace with hash -1860376514, now seen corresponding path program 62 times [2018-11-18 10:11:03,042 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:11:03,042 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:11:03,042 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:11:03,043 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:11:03,043 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:11:03,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:11:06,628 INFO L134 CoverageAnalysis]: Checked inductivity of 585282 backedges. 125378 proven. 10893 refuted. 0 times theorem prover too weak. 449011 trivial. 0 not checked. [2018-11-18 10:11:06,628 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:11:06,628 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:11:06,634 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-18 10:11:07,051 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 10:11:07,051 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:11:07,070 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:11:10,766 INFO L134 CoverageAnalysis]: Checked inductivity of 585282 backedges. 188310 proven. 2002 refuted. 0 times theorem prover too weak. 394970 trivial. 0 not checked. [2018-11-18 10:11:10,783 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:11:10,784 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 56] total 117 [2018-11-18 10:11:10,784 INFO L459 AbstractCegarLoop]: Interpolant automaton has 117 states [2018-11-18 10:11:10,784 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 117 interpolants. [2018-11-18 10:11:10,785 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2072, Invalid=11500, Unknown=0, NotChecked=0, Total=13572 [2018-11-18 10:11:10,785 INFO L87 Difference]: Start difference. First operand 3319 states and 3329 transitions. Second operand 117 states. [2018-11-18 10:11:14,092 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:11:14,093 INFO L93 Difference]: Finished difference Result 2979 states and 2982 transitions. [2018-11-18 10:11:14,093 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 141 states. [2018-11-18 10:11:14,093 INFO L78 Accepts]: Start accepts. Automaton has 117 states. Word has length 2950 [2018-11-18 10:11:14,094 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:11:14,096 INFO L225 Difference]: With dead ends: 2979 [2018-11-18 10:11:14,096 INFO L226 Difference]: Without dead ends: 2970 [2018-11-18 10:11:14,097 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3121 GetRequests, 2898 SyntacticMatches, 0 SemanticMatches, 223 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16238 ImplicationChecksByTransitivity, 3.6s TimeCoverageRelationStatistics Valid=7578, Invalid=42822, Unknown=0, NotChecked=0, Total=50400 [2018-11-18 10:11:14,098 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2970 states. [2018-11-18 10:11:14,111 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2970 to 2966. [2018-11-18 10:11:14,111 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2966 states. [2018-11-18 10:11:14,113 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2966 states to 2966 states and 2969 transitions. [2018-11-18 10:11:14,113 INFO L78 Accepts]: Start accepts. Automaton has 2966 states and 2969 transitions. Word has length 2950 [2018-11-18 10:11:14,114 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:11:14,114 INFO L480 AbstractCegarLoop]: Abstraction has 2966 states and 2969 transitions. [2018-11-18 10:11:14,114 INFO L481 AbstractCegarLoop]: Interpolant automaton has 117 states. [2018-11-18 10:11:14,114 INFO L276 IsEmpty]: Start isEmpty. Operand 2966 states and 2969 transitions. [2018-11-18 10:11:14,144 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2957 [2018-11-18 10:11:14,144 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:11:14,144 INFO L375 BasicCegarLoop]: trace histogram [460, 433, 432, 432, 432, 432, 28, 28, 28, 28, 27, 27, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:11:14,144 INFO L423 AbstractCegarLoop]: === Iteration 78 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:11:14,144 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:11:14,144 INFO L82 PathProgramCache]: Analyzing trace with hash 380851766, now seen corresponding path program 63 times [2018-11-18 10:11:14,144 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:11:14,145 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:11:14,145 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:11:14,145 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:11:14,145 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:11:14,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:11:17,774 INFO L134 CoverageAnalysis]: Checked inductivity of 587925 backedges. 131845 proven. 6891 refuted. 0 times theorem prover too weak. 449189 trivial. 0 not checked. [2018-11-18 10:11:17,774 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:11:17,774 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:11:17,782 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 10:11:19,861 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 29 check-sat command(s) [2018-11-18 10:11:19,861 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:11:19,877 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:11:22,907 INFO L134 CoverageAnalysis]: Checked inductivity of 587925 backedges. 129686 proven. 6863 refuted. 0 times theorem prover too weak. 451376 trivial. 0 not checked. [2018-11-18 10:11:22,925 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:11:22,926 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 37] total 95 [2018-11-18 10:11:22,927 INFO L459 AbstractCegarLoop]: Interpolant automaton has 95 states [2018-11-18 10:11:22,927 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 95 interpolants. [2018-11-18 10:11:22,928 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1790, Invalid=7140, Unknown=0, NotChecked=0, Total=8930 [2018-11-18 10:11:22,928 INFO L87 Difference]: Start difference. First operand 2966 states and 2969 transitions. Second operand 95 states. [2018-11-18 10:11:25,181 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:11:25,181 INFO L93 Difference]: Finished difference Result 3160 states and 3165 transitions. [2018-11-18 10:11:25,181 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 93 states. [2018-11-18 10:11:25,181 INFO L78 Accepts]: Start accepts. Automaton has 95 states. Word has length 2956 [2018-11-18 10:11:25,182 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:11:25,185 INFO L225 Difference]: With dead ends: 3160 [2018-11-18 10:11:25,185 INFO L226 Difference]: Without dead ends: 3160 [2018-11-18 10:11:25,186 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3104 GetRequests, 2926 SyntacticMatches, 0 SemanticMatches, 178 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9961 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=7772, Invalid=24448, Unknown=0, NotChecked=0, Total=32220 [2018-11-18 10:11:25,187 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3160 states. [2018-11-18 10:11:25,196 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3160 to 3153. [2018-11-18 10:11:25,196 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3153 states. [2018-11-18 10:11:25,198 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3153 states to 3153 states and 3158 transitions. [2018-11-18 10:11:25,198 INFO L78 Accepts]: Start accepts. Automaton has 3153 states and 3158 transitions. Word has length 2956 [2018-11-18 10:11:25,199 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:11:25,199 INFO L480 AbstractCegarLoop]: Abstraction has 3153 states and 3158 transitions. [2018-11-18 10:11:25,199 INFO L481 AbstractCegarLoop]: Interpolant automaton has 95 states. [2018-11-18 10:11:25,199 INFO L276 IsEmpty]: Start isEmpty. Operand 3153 states and 3158 transitions. [2018-11-18 10:11:25,228 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2963 [2018-11-18 10:11:25,228 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:11:25,229 INFO L375 BasicCegarLoop]: trace histogram [461, 434, 433, 433, 433, 433, 28, 28, 28, 28, 27, 27, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:11:25,229 INFO L423 AbstractCegarLoop]: === Iteration 79 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:11:25,229 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:11:25,229 INFO L82 PathProgramCache]: Analyzing trace with hash -1791335554, now seen corresponding path program 64 times [2018-11-18 10:11:25,229 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:11:25,229 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:11:25,230 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:11:25,230 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:11:25,230 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:11:25,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:11:28,081 INFO L134 CoverageAnalysis]: Checked inductivity of 590574 backedges. 71444 proven. 2566 refuted. 0 times theorem prover too weak. 516564 trivial. 0 not checked. [2018-11-18 10:11:28,081 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:11:28,081 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:11:28,089 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 10:11:35,907 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 10:11:35,907 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:11:35,937 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:11:38,467 INFO L134 CoverageAnalysis]: Checked inductivity of 590574 backedges. 70821 proven. 2352 refuted. 0 times theorem prover too weak. 517401 trivial. 0 not checked. [2018-11-18 10:11:38,493 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:11:38,494 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 30] total 66 [2018-11-18 10:11:38,494 INFO L459 AbstractCegarLoop]: Interpolant automaton has 67 states [2018-11-18 10:11:38,494 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 67 interpolants. [2018-11-18 10:11:38,495 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=549, Invalid=3873, Unknown=0, NotChecked=0, Total=4422 [2018-11-18 10:11:38,495 INFO L87 Difference]: Start difference. First operand 3153 states and 3158 transitions. Second operand 67 states. [2018-11-18 10:11:41,155 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:11:41,155 INFO L93 Difference]: Finished difference Result 3551 states and 3562 transitions. [2018-11-18 10:11:41,155 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 93 states. [2018-11-18 10:11:41,155 INFO L78 Accepts]: Start accepts. Automaton has 67 states. Word has length 2962 [2018-11-18 10:11:41,157 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:11:41,159 INFO L225 Difference]: With dead ends: 3551 [2018-11-18 10:11:41,159 INFO L226 Difference]: Without dead ends: 3551 [2018-11-18 10:11:41,159 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3031 GetRequests, 2933 SyntacticMatches, 0 SemanticMatches, 98 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1807 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=946, Invalid=8954, Unknown=0, NotChecked=0, Total=9900 [2018-11-18 10:11:41,160 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3551 states. [2018-11-18 10:11:41,170 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3551 to 3524. [2018-11-18 10:11:41,170 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3524 states. [2018-11-18 10:11:41,173 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3524 states to 3524 states and 3534 transitions. [2018-11-18 10:11:41,173 INFO L78 Accepts]: Start accepts. Automaton has 3524 states and 3534 transitions. Word has length 2962 [2018-11-18 10:11:41,174 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:11:41,175 INFO L480 AbstractCegarLoop]: Abstraction has 3524 states and 3534 transitions. [2018-11-18 10:11:41,175 INFO L481 AbstractCegarLoop]: Interpolant automaton has 67 states. [2018-11-18 10:11:41,175 INFO L276 IsEmpty]: Start isEmpty. Operand 3524 states and 3534 transitions. [2018-11-18 10:11:41,209 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3144 [2018-11-18 10:11:41,209 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:11:41,209 INFO L375 BasicCegarLoop]: trace histogram [490, 462, 461, 461, 461, 461, 29, 29, 29, 29, 28, 28, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:11:41,209 INFO L423 AbstractCegarLoop]: === Iteration 80 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:11:41,209 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:11:41,209 INFO L82 PathProgramCache]: Analyzing trace with hash 1883492489, now seen corresponding path program 65 times [2018-11-18 10:11:41,210 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:11:41,210 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:11:41,210 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:11:41,210 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:11:41,210 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:11:41,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:11:45,190 INFO L134 CoverageAnalysis]: Checked inductivity of 668461 backedges. 139529 proven. 11716 refuted. 0 times theorem prover too weak. 517216 trivial. 0 not checked. [2018-11-18 10:11:45,190 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:11:45,190 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 73 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 73 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:11:45,198 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-18 10:12:06,450 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 62 check-sat command(s) [2018-11-18 10:12:06,450 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:12:06,498 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:12:10,800 INFO L134 CoverageAnalysis]: Checked inductivity of 668461 backedges. 209046 proven. 12762 refuted. 0 times theorem prover too weak. 446653 trivial. 0 not checked. [2018-11-18 10:12:10,829 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:12:10,830 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [66, 62] total 125 [2018-11-18 10:12:10,830 INFO L459 AbstractCegarLoop]: Interpolant automaton has 125 states [2018-11-18 10:12:10,830 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 125 interpolants. [2018-11-18 10:12:10,831 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2185, Invalid=13315, Unknown=0, NotChecked=0, Total=15500 [2018-11-18 10:12:10,831 INFO L87 Difference]: Start difference. First operand 3524 states and 3534 transitions. Second operand 125 states. [2018-11-18 10:12:15,417 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:12:15,417 INFO L93 Difference]: Finished difference Result 3172 states and 3175 transitions. [2018-11-18 10:12:15,417 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 151 states. [2018-11-18 10:12:15,417 INFO L78 Accepts]: Start accepts. Automaton has 125 states. Word has length 3143 [2018-11-18 10:12:15,419 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:12:15,421 INFO L225 Difference]: With dead ends: 3172 [2018-11-18 10:12:15,421 INFO L226 Difference]: Without dead ends: 3163 [2018-11-18 10:12:15,425 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3352 GetRequests, 3086 SyntacticMatches, 0 SemanticMatches, 266 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24256 ImplicationChecksByTransitivity, 4.8s TimeCoverageRelationStatistics Valid=10467, Invalid=61089, Unknown=0, NotChecked=0, Total=71556 [2018-11-18 10:12:15,426 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3163 states. [2018-11-18 10:12:15,435 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3163 to 3159. [2018-11-18 10:12:15,435 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3159 states. [2018-11-18 10:12:15,437 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3159 states to 3159 states and 3162 transitions. [2018-11-18 10:12:15,437 INFO L78 Accepts]: Start accepts. Automaton has 3159 states and 3162 transitions. Word has length 3143 [2018-11-18 10:12:15,439 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:12:15,439 INFO L480 AbstractCegarLoop]: Abstraction has 3159 states and 3162 transitions. [2018-11-18 10:12:15,439 INFO L481 AbstractCegarLoop]: Interpolant automaton has 125 states. [2018-11-18 10:12:15,439 INFO L276 IsEmpty]: Start isEmpty. Operand 3159 states and 3162 transitions. [2018-11-18 10:12:15,473 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3150 [2018-11-18 10:12:15,473 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:12:15,473 INFO L375 BasicCegarLoop]: trace histogram [491, 463, 462, 462, 462, 462, 29, 29, 29, 29, 28, 28, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:12:15,473 INFO L423 AbstractCegarLoop]: === Iteration 81 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:12:15,473 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:12:15,474 INFO L82 PathProgramCache]: Analyzing trace with hash -542222783, now seen corresponding path program 66 times [2018-11-18 10:12:15,474 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:12:15,474 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:12:15,474 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:12:15,474 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:12:15,475 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:12:15,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:12:19,489 INFO L134 CoverageAnalysis]: Checked inductivity of 671286 backedges. 146487 proven. 7398 refuted. 0 times theorem prover too weak. 517401 trivial. 0 not checked. [2018-11-18 10:12:19,489 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:12:19,489 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:12:19,497 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-18 10:12:36,927 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 59 check-sat command(s) [2018-11-18 10:12:36,928 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:12:36,961 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:12:40,700 INFO L134 CoverageAnalysis]: Checked inductivity of 671286 backedges. 142885 proven. 20435 refuted. 0 times theorem prover too weak. 507966 trivial. 0 not checked. [2018-11-18 10:12:40,724 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:12:40,725 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [66, 46] total 106 [2018-11-18 10:12:40,725 INFO L459 AbstractCegarLoop]: Interpolant automaton has 106 states [2018-11-18 10:12:40,726 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 106 interpolants. [2018-11-18 10:12:40,726 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1952, Invalid=9178, Unknown=0, NotChecked=0, Total=11130 [2018-11-18 10:12:40,726 INFO L87 Difference]: Start difference. First operand 3159 states and 3162 transitions. Second operand 106 states. [2018-11-18 10:12:43,728 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:12:43,729 INFO L93 Difference]: Finished difference Result 3359 states and 3364 transitions. [2018-11-18 10:12:43,729 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 110 states. [2018-11-18 10:12:43,729 INFO L78 Accepts]: Start accepts. Automaton has 106 states. Word has length 3149 [2018-11-18 10:12:43,730 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:12:43,732 INFO L225 Difference]: With dead ends: 3359 [2018-11-18 10:12:43,732 INFO L226 Difference]: Without dead ends: 3359 [2018-11-18 10:12:43,733 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3313 GetRequests, 3110 SyntacticMatches, 0 SemanticMatches, 203 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13575 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=8964, Invalid=32856, Unknown=0, NotChecked=0, Total=41820 [2018-11-18 10:12:43,734 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3359 states. [2018-11-18 10:12:43,744 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3359 to 3352. [2018-11-18 10:12:43,744 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3352 states. [2018-11-18 10:12:43,747 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3352 states to 3352 states and 3357 transitions. [2018-11-18 10:12:43,747 INFO L78 Accepts]: Start accepts. Automaton has 3352 states and 3357 transitions. Word has length 3149 [2018-11-18 10:12:43,748 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:12:43,748 INFO L480 AbstractCegarLoop]: Abstraction has 3352 states and 3357 transitions. [2018-11-18 10:12:43,748 INFO L481 AbstractCegarLoop]: Interpolant automaton has 106 states. [2018-11-18 10:12:43,748 INFO L276 IsEmpty]: Start isEmpty. Operand 3352 states and 3357 transitions. [2018-11-18 10:12:43,781 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3156 [2018-11-18 10:12:43,781 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:12:43,781 INFO L375 BasicCegarLoop]: trace histogram [492, 464, 463, 463, 463, 463, 29, 29, 29, 29, 28, 28, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:12:43,781 INFO L423 AbstractCegarLoop]: === Iteration 82 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:12:43,781 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:12:43,782 INFO L82 PathProgramCache]: Analyzing trace with hash -1924320439, now seen corresponding path program 67 times [2018-11-18 10:12:43,782 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:12:43,782 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:12:43,782 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:12:43,782 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:12:43,782 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:12:43,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:12:46,910 INFO L134 CoverageAnalysis]: Checked inductivity of 674117 backedges. 78668 proven. 2759 refuted. 0 times theorem prover too weak. 592690 trivial. 0 not checked. [2018-11-18 10:12:46,910 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:12:46,910 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 75 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 75 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:12:46,917 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:12:47,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:12:47,355 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:12:50,142 INFO L134 CoverageAnalysis]: Checked inductivity of 674117 backedges. 78498 proven. 2523 refuted. 0 times theorem prover too weak. 593096 trivial. 0 not checked. [2018-11-18 10:12:50,160 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:12:50,160 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 31] total 65 [2018-11-18 10:12:50,161 INFO L459 AbstractCegarLoop]: Interpolant automaton has 66 states [2018-11-18 10:12:50,161 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 66 interpolants. [2018-11-18 10:12:50,161 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=567, Invalid=3723, Unknown=0, NotChecked=0, Total=4290 [2018-11-18 10:12:50,161 INFO L87 Difference]: Start difference. First operand 3352 states and 3357 transitions. Second operand 66 states. [2018-11-18 10:12:52,682 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:12:52,682 INFO L93 Difference]: Finished difference Result 3762 states and 3773 transitions. [2018-11-18 10:12:52,682 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2018-11-18 10:12:52,682 INFO L78 Accepts]: Start accepts. Automaton has 66 states. Word has length 3155 [2018-11-18 10:12:52,683 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:12:52,686 INFO L225 Difference]: With dead ends: 3762 [2018-11-18 10:12:52,686 INFO L226 Difference]: Without dead ends: 3762 [2018-11-18 10:12:52,686 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3223 GetRequests, 3125 SyntacticMatches, 0 SemanticMatches, 98 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1660 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=893, Invalid=9007, Unknown=0, NotChecked=0, Total=9900 [2018-11-18 10:12:52,687 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3762 states. [2018-11-18 10:12:52,701 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3762 to 3735. [2018-11-18 10:12:52,701 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3735 states. [2018-11-18 10:12:52,704 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3735 states to 3735 states and 3745 transitions. [2018-11-18 10:12:52,704 INFO L78 Accepts]: Start accepts. Automaton has 3735 states and 3745 transitions. Word has length 3155 [2018-11-18 10:12:52,706 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:12:52,706 INFO L480 AbstractCegarLoop]: Abstraction has 3735 states and 3745 transitions. [2018-11-18 10:12:52,706 INFO L481 AbstractCegarLoop]: Interpolant automaton has 66 states. [2018-11-18 10:12:52,706 INFO L276 IsEmpty]: Start isEmpty. Operand 3735 states and 3745 transitions. [2018-11-18 10:12:52,744 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3343 [2018-11-18 10:12:52,744 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:12:52,745 INFO L375 BasicCegarLoop]: trace histogram [522, 493, 492, 492, 492, 492, 30, 30, 30, 30, 29, 29, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:12:52,745 INFO L423 AbstractCegarLoop]: === Iteration 83 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:12:52,745 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:12:52,745 INFO L82 PathProgramCache]: Analyzing trace with hash 1701146006, now seen corresponding path program 68 times [2018-11-18 10:12:52,745 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:12:52,745 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:12:52,746 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:12:52,746 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:12:52,746 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:12:52,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:12:57,156 INFO L134 CoverageAnalysis]: Checked inductivity of 760180 backedges. 154707 proven. 12569 refuted. 0 times theorem prover too weak. 592904 trivial. 0 not checked. [2018-11-18 10:12:57,156 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:12:57,156 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:12:57,164 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-18 10:12:57,599 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 10:12:57,599 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:12:57,621 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:13:02,162 INFO L134 CoverageAnalysis]: Checked inductivity of 760180 backedges. 232422 proven. 2324 refuted. 0 times theorem prover too weak. 525434 trivial. 0 not checked. [2018-11-18 10:13:02,180 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:13:02,180 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 60] total 125 [2018-11-18 10:13:02,181 INFO L459 AbstractCegarLoop]: Interpolant automaton has 125 states [2018-11-18 10:13:02,182 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 125 interpolants. [2018-11-18 10:13:02,182 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2369, Invalid=13131, Unknown=0, NotChecked=0, Total=15500 [2018-11-18 10:13:02,183 INFO L87 Difference]: Start difference. First operand 3735 states and 3745 transitions. Second operand 125 states. [2018-11-18 10:13:06,173 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:13:06,173 INFO L93 Difference]: Finished difference Result 3371 states and 3374 transitions. [2018-11-18 10:13:06,173 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 151 states. [2018-11-18 10:13:06,174 INFO L78 Accepts]: Start accepts. Automaton has 125 states. Word has length 3342 [2018-11-18 10:13:06,175 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:13:06,178 INFO L225 Difference]: With dead ends: 3371 [2018-11-18 10:13:06,178 INFO L226 Difference]: Without dead ends: 3362 [2018-11-18 10:13:06,181 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3525 GetRequests, 3286 SyntacticMatches, 0 SemanticMatches, 239 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18718 ImplicationChecksByTransitivity, 4.0s TimeCoverageRelationStatistics Valid=8687, Invalid=49153, Unknown=0, NotChecked=0, Total=57840 [2018-11-18 10:13:06,182 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3362 states. [2018-11-18 10:13:06,192 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3362 to 3358. [2018-11-18 10:13:06,193 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3358 states. [2018-11-18 10:13:06,195 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3358 states to 3358 states and 3361 transitions. [2018-11-18 10:13:06,195 INFO L78 Accepts]: Start accepts. Automaton has 3358 states and 3361 transitions. Word has length 3342 [2018-11-18 10:13:06,196 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:13:06,197 INFO L480 AbstractCegarLoop]: Abstraction has 3358 states and 3361 transitions. [2018-11-18 10:13:06,197 INFO L481 AbstractCegarLoop]: Interpolant automaton has 125 states. [2018-11-18 10:13:06,197 INFO L276 IsEmpty]: Start isEmpty. Operand 3358 states and 3361 transitions. [2018-11-18 10:13:06,234 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3349 [2018-11-18 10:13:06,235 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:13:06,235 INFO L375 BasicCegarLoop]: trace histogram [523, 494, 493, 493, 493, 493, 30, 30, 30, 30, 29, 29, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:13:06,235 INFO L423 AbstractCegarLoop]: === Iteration 84 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:13:06,235 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:13:06,236 INFO L82 PathProgramCache]: Analyzing trace with hash -2091978354, now seen corresponding path program 69 times [2018-11-18 10:13:06,236 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:13:06,236 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:13:06,236 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:13:06,237 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:13:06,237 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:13:06,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:13:10,697 INFO L134 CoverageAnalysis]: Checked inductivity of 763193 backedges. 162174 proven. 7923 refuted. 0 times theorem prover too weak. 593096 trivial. 0 not checked. [2018-11-18 10:13:10,698 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:13:10,698 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 77 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 77 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:13:10,705 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 10:13:14,364 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 31 check-sat command(s) [2018-11-18 10:13:14,364 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:13:14,382 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:13:18,128 INFO L134 CoverageAnalysis]: Checked inductivity of 763193 backedges. 159681 proven. 7893 refuted. 0 times theorem prover too weak. 595619 trivial. 0 not checked. [2018-11-18 10:13:18,147 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:13:18,148 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 39] total 101 [2018-11-18 10:13:18,148 INFO L459 AbstractCegarLoop]: Interpolant automaton has 101 states [2018-11-18 10:13:18,148 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 101 interpolants. [2018-11-18 10:13:18,149 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2036, Invalid=8064, Unknown=0, NotChecked=0, Total=10100 [2018-11-18 10:13:18,149 INFO L87 Difference]: Start difference. First operand 3358 states and 3361 transitions. Second operand 101 states. [2018-11-18 10:13:20,706 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:13:20,706 INFO L93 Difference]: Finished difference Result 3564 states and 3569 transitions. [2018-11-18 10:13:20,707 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 99 states. [2018-11-18 10:13:20,707 INFO L78 Accepts]: Start accepts. Automaton has 101 states. Word has length 3348 [2018-11-18 10:13:20,708 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:13:20,710 INFO L225 Difference]: With dead ends: 3564 [2018-11-18 10:13:20,711 INFO L226 Difference]: Without dead ends: 3564 [2018-11-18 10:13:20,712 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3506 GetRequests, 3316 SyntacticMatches, 0 SemanticMatches, 190 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11393 ImplicationChecksByTransitivity, 3.1s TimeCoverageRelationStatistics Valid=8864, Invalid=27808, Unknown=0, NotChecked=0, Total=36672 [2018-11-18 10:13:20,713 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3564 states. [2018-11-18 10:13:20,724 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3564 to 3557. [2018-11-18 10:13:20,724 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3557 states. [2018-11-18 10:13:20,727 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3557 states to 3557 states and 3562 transitions. [2018-11-18 10:13:20,727 INFO L78 Accepts]: Start accepts. Automaton has 3557 states and 3562 transitions. Word has length 3348 [2018-11-18 10:13:20,729 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:13:20,729 INFO L480 AbstractCegarLoop]: Abstraction has 3557 states and 3562 transitions. [2018-11-18 10:13:20,729 INFO L481 AbstractCegarLoop]: Interpolant automaton has 101 states. [2018-11-18 10:13:20,729 INFO L276 IsEmpty]: Start isEmpty. Operand 3557 states and 3562 transitions. [2018-11-18 10:13:20,767 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3355 [2018-11-18 10:13:20,768 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:13:20,768 INFO L375 BasicCegarLoop]: trace histogram [524, 495, 494, 494, 494, 494, 30, 30, 30, 30, 29, 29, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:13:20,768 INFO L423 AbstractCegarLoop]: === Iteration 85 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:13:20,768 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:13:20,769 INFO L82 PathProgramCache]: Analyzing trace with hash 519939286, now seen corresponding path program 70 times [2018-11-18 10:13:20,769 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:13:20,769 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:13:20,769 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:13:20,769 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:13:20,770 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:13:21,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:13:24,283 INFO L134 CoverageAnalysis]: Checked inductivity of 766212 backedges. 87057 proven. 2959 refuted. 0 times theorem prover too weak. 676196 trivial. 0 not checked. [2018-11-18 10:13:24,283 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:13:24,283 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:13:24,291 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 10:13:32,230 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 10:13:32,230 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:13:32,264 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:13:35,439 INFO L134 CoverageAnalysis]: Checked inductivity of 766212 backedges. 86710 proven. 2700 refuted. 0 times theorem prover too weak. 676802 trivial. 0 not checked. [2018-11-18 10:13:35,466 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:13:35,466 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 32] total 68 [2018-11-18 10:13:35,467 INFO L459 AbstractCegarLoop]: Interpolant automaton has 69 states [2018-11-18 10:13:35,467 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2018-11-18 10:13:35,467 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=605, Invalid=4087, Unknown=0, NotChecked=0, Total=4692 [2018-11-18 10:13:35,467 INFO L87 Difference]: Start difference. First operand 3557 states and 3562 transitions. Second operand 69 states. [2018-11-18 10:13:39,262 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:13:39,263 INFO L93 Difference]: Finished difference Result 3979 states and 3990 transitions. [2018-11-18 10:13:39,263 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 99 states. [2018-11-18 10:13:39,263 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 3354 [2018-11-18 10:13:39,264 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:13:39,267 INFO L225 Difference]: With dead ends: 3979 [2018-11-18 10:13:39,267 INFO L226 Difference]: Without dead ends: 3979 [2018-11-18 10:13:39,268 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3425 GetRequests, 3323 SyntacticMatches, 0 SemanticMatches, 102 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1851 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=971, Invalid=9741, Unknown=0, NotChecked=0, Total=10712 [2018-11-18 10:13:39,268 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3979 states. [2018-11-18 10:13:39,280 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3979 to 3952. [2018-11-18 10:13:39,281 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3952 states. [2018-11-18 10:13:39,283 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3952 states to 3952 states and 3962 transitions. [2018-11-18 10:13:39,283 INFO L78 Accepts]: Start accepts. Automaton has 3952 states and 3962 transitions. Word has length 3354 [2018-11-18 10:13:39,285 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:13:39,285 INFO L480 AbstractCegarLoop]: Abstraction has 3952 states and 3962 transitions. [2018-11-18 10:13:39,285 INFO L481 AbstractCegarLoop]: Interpolant automaton has 69 states. [2018-11-18 10:13:39,285 INFO L276 IsEmpty]: Start isEmpty. Operand 3952 states and 3962 transitions. [2018-11-18 10:13:39,327 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3548 [2018-11-18 10:13:39,327 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:13:39,327 INFO L375 BasicCegarLoop]: trace histogram [555, 525, 524, 524, 524, 524, 31, 31, 31, 31, 30, 30, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:13:39,328 INFO L423 AbstractCegarLoop]: === Iteration 86 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:13:39,328 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:13:39,328 INFO L82 PathProgramCache]: Analyzing trace with hash -1840250975, now seen corresponding path program 71 times [2018-11-18 10:13:39,328 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:13:39,328 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:13:39,329 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:13:39,329 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:13:39,329 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:13:39,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:13:44,243 INFO L134 CoverageAnalysis]: Checked inductivity of 861003 backedges. 170948 proven. 13452 refuted. 0 times theorem prover too weak. 676603 trivial. 0 not checked. [2018-11-18 10:13:44,244 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:13:44,244 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 79 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 79 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:13:44,251 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-18 10:14:14,076 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 74 check-sat command(s) [2018-11-18 10:14:14,076 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:14:14,145 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:14:19,359 INFO L134 CoverageAnalysis]: Checked inductivity of 861003 backedges. 256248 proven. 14656 refuted. 0 times theorem prover too weak. 590099 trivial. 0 not checked. [2018-11-18 10:14:19,393 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:14:19,394 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [70, 66] total 133 [2018-11-18 10:14:19,394 INFO L459 AbstractCegarLoop]: Interpolant automaton has 133 states [2018-11-18 10:14:19,395 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 133 interpolants. [2018-11-18 10:14:19,396 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2488, Invalid=15068, Unknown=0, NotChecked=0, Total=17556 [2018-11-18 10:14:19,396 INFO L87 Difference]: Start difference. First operand 3952 states and 3962 transitions. Second operand 133 states. [2018-11-18 10:14:25,783 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:14:25,783 INFO L93 Difference]: Finished difference Result 3576 states and 3579 transitions. [2018-11-18 10:14:25,783 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 161 states. [2018-11-18 10:14:25,783 INFO L78 Accepts]: Start accepts. Automaton has 133 states. Word has length 3547 [2018-11-18 10:14:25,784 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:14:25,787 INFO L225 Difference]: With dead ends: 3576 [2018-11-18 10:14:25,787 INFO L226 Difference]: Without dead ends: 3567 [2018-11-18 10:14:25,790 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3770 GetRequests, 3486 SyntacticMatches, 0 SemanticMatches, 284 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 27763 ImplicationChecksByTransitivity, 5.4s TimeCoverageRelationStatistics Valid=11925, Invalid=69585, Unknown=0, NotChecked=0, Total=81510 [2018-11-18 10:14:25,791 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3567 states. [2018-11-18 10:14:25,805 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3567 to 3563. [2018-11-18 10:14:25,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3563 states. [2018-11-18 10:14:25,808 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3563 states to 3563 states and 3566 transitions. [2018-11-18 10:14:25,808 INFO L78 Accepts]: Start accepts. Automaton has 3563 states and 3566 transitions. Word has length 3547 [2018-11-18 10:14:25,810 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:14:25,810 INFO L480 AbstractCegarLoop]: Abstraction has 3563 states and 3566 transitions. [2018-11-18 10:14:25,810 INFO L481 AbstractCegarLoop]: Interpolant automaton has 133 states. [2018-11-18 10:14:25,810 INFO L276 IsEmpty]: Start isEmpty. Operand 3563 states and 3566 transitions. [2018-11-18 10:14:25,851 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3554 [2018-11-18 10:14:25,851 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:14:25,851 INFO L375 BasicCegarLoop]: trace histogram [556, 526, 525, 525, 525, 525, 31, 31, 31, 31, 30, 30, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:14:25,851 INFO L423 AbstractCegarLoop]: === Iteration 87 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:14:25,851 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:14:25,852 INFO L82 PathProgramCache]: Analyzing trace with hash -1041675431, now seen corresponding path program 72 times [2018-11-18 10:14:25,852 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:14:25,852 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:14:25,852 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:14:25,852 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:14:25,852 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:14:26,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:14:30,804 INFO L134 CoverageAnalysis]: Checked inductivity of 864210 backedges. 178942 proven. 8466 refuted. 0 times theorem prover too weak. 676802 trivial. 0 not checked. [2018-11-18 10:14:30,804 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:14:30,804 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:14:30,812 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-18 10:15:02,887 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 59 check-sat command(s) [2018-11-18 10:15:02,887 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 10:15:02,939 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:15:08,091 INFO L134 CoverageAnalysis]: Checked inductivity of 864210 backedges. 175233 proven. 22236 refuted. 0 times theorem prover too weak. 666741 trivial. 0 not checked. [2018-11-18 10:15:08,115 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:15:08,116 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [70, 48] total 117 [2018-11-18 10:15:08,117 INFO L459 AbstractCegarLoop]: Interpolant automaton has 117 states [2018-11-18 10:15:08,117 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 117 interpolants. [2018-11-18 10:15:08,117 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1929, Invalid=11643, Unknown=0, NotChecked=0, Total=13572 [2018-11-18 10:15:08,118 INFO L87 Difference]: Start difference. First operand 3563 states and 3566 transitions. Second operand 117 states. [2018-11-18 10:15:16,831 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:15:16,831 INFO L93 Difference]: Finished difference Result 3982 states and 3988 transitions. [2018-11-18 10:15:16,832 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 299 states. [2018-11-18 10:15:16,832 INFO L78 Accepts]: Start accepts. Automaton has 117 states. Word has length 3553 [2018-11-18 10:15:16,834 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:15:16,837 INFO L225 Difference]: With dead ends: 3982 [2018-11-18 10:15:16,837 INFO L226 Difference]: Without dead ends: 3982 [2018-11-18 10:15:16,843 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3881 GetRequests, 3506 SyntacticMatches, 1 SemanticMatches, 374 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 55469 ImplicationChecksByTransitivity, 9.0s TimeCoverageRelationStatistics Valid=21283, Invalid=119717, Unknown=0, NotChecked=0, Total=141000 [2018-11-18 10:15:16,844 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3982 states. [2018-11-18 10:15:16,855 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3982 to 3777. [2018-11-18 10:15:16,855 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3777 states. [2018-11-18 10:15:16,858 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3777 states to 3777 states and 3782 transitions. [2018-11-18 10:15:16,858 INFO L78 Accepts]: Start accepts. Automaton has 3777 states and 3782 transitions. Word has length 3553 [2018-11-18 10:15:16,860 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:15:16,860 INFO L480 AbstractCegarLoop]: Abstraction has 3777 states and 3782 transitions. [2018-11-18 10:15:16,860 INFO L481 AbstractCegarLoop]: Interpolant automaton has 117 states. [2018-11-18 10:15:16,860 INFO L276 IsEmpty]: Start isEmpty. Operand 3777 states and 3782 transitions. [2018-11-18 10:15:16,907 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3759 [2018-11-18 10:15:16,907 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:15:16,907 INFO L375 BasicCegarLoop]: trace histogram [589, 558, 557, 557, 557, 557, 32, 32, 32, 32, 31, 31, 31, 31, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:15:16,908 INFO L423 AbstractCegarLoop]: === Iteration 88 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:15:16,908 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:15:16,908 INFO L82 PathProgramCache]: Analyzing trace with hash -559728786, now seen corresponding path program 73 times [2018-11-18 10:15:16,908 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:15:16,908 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:15:16,909 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:15:16,909 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:15:16,909 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:15:17,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:15:22,197 INFO L134 CoverageAnalysis]: Checked inductivity of 971512 backedges. 199404 proven. 10468 refuted. 0 times theorem prover too weak. 761640 trivial. 0 not checked. [2018-11-18 10:15:22,197 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 10:15:22,197 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/z3 Starting monitored process 81 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 81 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 10:15:22,206 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:15:22,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:15:22,736 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 10:15:27,313 INFO L134 CoverageAnalysis]: Checked inductivity of 971512 backedges. 199847 proven. 2852 refuted. 0 times theorem prover too weak. 768813 trivial. 0 not checked. [2018-11-18 10:15:27,331 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 10:15:27,332 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [70, 66] total 102 [2018-11-18 10:15:27,333 INFO L459 AbstractCegarLoop]: Interpolant automaton has 102 states [2018-11-18 10:15:27,334 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 102 interpolants. [2018-11-18 10:15:27,334 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2218, Invalid=8084, Unknown=0, NotChecked=0, Total=10302 [2018-11-18 10:15:27,334 INFO L87 Difference]: Start difference. First operand 3777 states and 3782 transitions. Second operand 102 states. [2018-11-18 10:15:29,483 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:15:29,483 INFO L93 Difference]: Finished difference Result 3799 states and 3801 transitions. [2018-11-18 10:15:29,483 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 97 states. [2018-11-18 10:15:29,483 INFO L78 Accepts]: Start accepts. Automaton has 102 states. Word has length 3758 [2018-11-18 10:15:29,485 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 10:15:29,488 INFO L225 Difference]: With dead ends: 3799 [2018-11-18 10:15:29,488 INFO L226 Difference]: Without dead ends: 3777 [2018-11-18 10:15:29,489 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3891 GetRequests, 3728 SyntacticMatches, 0 SemanticMatches, 163 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9328 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=6037, Invalid=21023, Unknown=0, NotChecked=0, Total=27060 [2018-11-18 10:15:29,490 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3777 states. [2018-11-18 10:15:29,501 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3777 to 3774. [2018-11-18 10:15:29,501 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3774 states. [2018-11-18 10:15:29,503 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3774 states to 3774 states and 3775 transitions. [2018-11-18 10:15:29,503 INFO L78 Accepts]: Start accepts. Automaton has 3774 states and 3775 transitions. Word has length 3758 [2018-11-18 10:15:29,504 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 10:15:29,504 INFO L480 AbstractCegarLoop]: Abstraction has 3774 states and 3775 transitions. [2018-11-18 10:15:29,504 INFO L481 AbstractCegarLoop]: Interpolant automaton has 102 states. [2018-11-18 10:15:29,504 INFO L276 IsEmpty]: Start isEmpty. Operand 3774 states and 3775 transitions. [2018-11-18 10:15:29,557 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3771 [2018-11-18 10:15:29,557 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 10:15:29,557 INFO L375 BasicCegarLoop]: trace histogram [591, 560, 559, 559, 559, 559, 32, 32, 32, 32, 31, 31, 31, 31, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:15:29,557 INFO L423 AbstractCegarLoop]: === Iteration 89 === [fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, fooErr1REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION]=== [2018-11-18 10:15:29,557 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:15:29,558 INFO L82 PathProgramCache]: Analyzing trace with hash -288406354, now seen corresponding path program 74 times [2018-11-18 10:15:29,558 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:15:29,558 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:15:29,558 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:15:29,558 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:15:29,558 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:15:30,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:15:31,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:15:31,652 INFO L442 BasicCegarLoop]: Counterexample might be feasible [2018-11-18 10:15:32,029 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 18.11 10:15:32 BoogieIcfgContainer [2018-11-18 10:15:32,029 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-18 10:15:32,030 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-18 10:15:32,030 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-18 10:15:32,030 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-18 10:15:32,030 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 10:06:11" (3/4) ... [2018-11-18 10:15:32,032 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-11-18 10:15:32,430 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_9dd01780-a7d9-4ccd-b715-b5e31821f5fc/bin-2019/uautomizer/witness.graphml [2018-11-18 10:15:32,430 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-18 10:15:32,431 INFO L168 Benchmark]: Toolchain (without parser) took 561752.55 ms. Allocated memory was 1.0 GB in the beginning and 5.0 GB in the end (delta: 4.0 GB). Free memory was 958.0 MB in the beginning and 2.1 GB in the end (delta: -1.1 GB). Peak memory consumption was 2.9 GB. Max. memory is 11.5 GB. [2018-11-18 10:15:32,432 INFO L168 Benchmark]: CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 10:15:32,436 INFO L168 Benchmark]: CACSL2BoogieTranslator took 152.59 ms. Allocated memory is still 1.0 GB. Free memory was 958.0 MB in the beginning and 947.1 MB in the end (delta: 10.9 MB). Peak memory consumption was 10.9 MB. Max. memory is 11.5 GB. [2018-11-18 10:15:32,437 INFO L168 Benchmark]: Boogie Preprocessor took 23.33 ms. Allocated memory is still 1.0 GB. Free memory was 947.1 MB in the beginning and 944.4 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-11-18 10:15:32,437 INFO L168 Benchmark]: RCFGBuilder took 240.93 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 142.1 MB). Free memory was 944.4 MB in the beginning and 1.1 GB in the end (delta: -174.1 MB). Peak memory consumption was 14.5 MB. Max. memory is 11.5 GB. [2018-11-18 10:15:32,437 INFO L168 Benchmark]: TraceAbstraction took 560932.05 ms. Allocated memory was 1.2 GB in the beginning and 5.0 GB in the end (delta: 3.8 GB). Free memory was 1.1 GB in the beginning and 2.2 GB in the end (delta: -1.0 GB). Peak memory consumption was 2.8 GB. Max. memory is 11.5 GB. [2018-11-18 10:15:32,438 INFO L168 Benchmark]: Witness Printer took 400.80 ms. Allocated memory is still 5.0 GB. Free memory was 2.2 GB in the beginning and 2.1 GB in the end (delta: 82.7 MB). Peak memory consumption was 82.7 MB. Max. memory is 11.5 GB. [2018-11-18 10:15:32,439 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 152.59 ms. Allocated memory is still 1.0 GB. Free memory was 958.0 MB in the beginning and 947.1 MB in the end (delta: 10.9 MB). Peak memory consumption was 10.9 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 23.33 ms. Allocated memory is still 1.0 GB. Free memory was 947.1 MB in the beginning and 944.4 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 240.93 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 142.1 MB). Free memory was 944.4 MB in the beginning and 1.1 GB in the end (delta: -174.1 MB). Peak memory consumption was 14.5 MB. Max. memory is 11.5 GB. * TraceAbstraction took 560932.05 ms. Allocated memory was 1.2 GB in the beginning and 5.0 GB in the end (delta: 3.8 GB). Free memory was 1.1 GB in the beginning and 2.2 GB in the end (delta: -1.0 GB). Peak memory consumption was 2.8 GB. Max. memory is 11.5 GB. * Witness Printer took 400.80 ms. Allocated memory is still 5.0 GB. Free memory was 2.2 GB in the beginning and 2.1 GB in the end (delta: 82.7 MB). Peak memory consumption was 82.7 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 18]: array index can be out of bounds array index can be out of bounds We found a FailurePath: [L24] int i, b[32]; [L25] FCALL char mask[32]; [L26] i = 0 VAL [b={159:0}, i=0, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=0, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=1, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=1, b={143:0}, b={143:0}, i=0, size=1] [L17] COND TRUE i <= size VAL [\old(size)=1, b={143:0}, b={143:0}, i=0, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={143:0}, b={143:0}, i=0, size=1] [L18] EXPR, FCALL b[i] VAL [\old(size)=1, b={143:0}, b={143:0}, b[i]=160, i=0, size=1] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=1, b={143:0}, b={143:0}, i=1, size=1] [L17] COND TRUE i <= size VAL [\old(size)=1, b={143:0}, b={143:0}, i=1, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={143:0}, b={143:0}, i=1, size=1] [L18] EXPR, FCALL b[i] VAL [\old(size)=1, b={143:0}, b={143:0}, b[i]=131, i=1, size=1] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=1, b={143:0}, b={143:0}, i=2, size=1] [L17] COND FALSE !(i <= size) VAL [\old(size)=1, b={143:0}, b={143:0}, i=2, size=1] [L20] RET return i; VAL [\old(size)=1, \result=2, b={143:0}, b={143:0}, i=2, size=1] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=2, i=0, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=2, i=0, mask={143:0}] [L26] i++ VAL [b={159:0}, i=1, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=1, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=2, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=2, b={143:0}, b={143:0}, i=0, size=2] [L17] COND TRUE i <= size VAL [\old(size)=2, b={143:0}, b={143:0}, i=0, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={143:0}, b={143:0}, i=0, size=2] [L18] EXPR, FCALL b[i] VAL [\old(size)=2, b={143:0}, b={143:0}, b[i]=160, i=0, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={143:0}, b={143:0}, i=1, size=2] [L17] COND TRUE i <= size VAL [\old(size)=2, b={143:0}, b={143:0}, i=1, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={143:0}, b={143:0}, i=1, size=2] [L18] EXPR, FCALL b[i] VAL [\old(size)=2, b={143:0}, b={143:0}, b[i]=131, i=1, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={143:0}, b={143:0}, i=2, size=2] [L17] COND TRUE i <= size VAL [\old(size)=2, b={143:0}, b={143:0}, i=2, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={143:0}, b={143:0}, i=2, size=2] [L18] EXPR, FCALL b[i] VAL [\old(size)=2, b={143:0}, b={143:0}, b[i]=133, i=2, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={143:0}, b={143:0}, i=3, size=2] [L17] COND FALSE !(i <= size) VAL [\old(size)=2, b={143:0}, b={143:0}, i=3, size=2] [L20] RET return i; VAL [\old(size)=2, \result=3, b={143:0}, b={143:0}, i=3, size=2] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=3, i=1, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=3, i=1, mask={143:0}] [L26] i++ VAL [b={159:0}, i=2, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=2, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=3, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=3, b={143:0}, b={143:0}, i=0, size=3] [L17] COND TRUE i <= size VAL [\old(size)=3, b={143:0}, b={143:0}, i=0, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={143:0}, b={143:0}, i=0, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={143:0}, b={143:0}, b[i]=160, i=0, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={143:0}, b={143:0}, i=1, size=3] [L17] COND TRUE i <= size VAL [\old(size)=3, b={143:0}, b={143:0}, i=1, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={143:0}, b={143:0}, i=1, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={143:0}, b={143:0}, b[i]=131, i=1, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={143:0}, b={143:0}, i=2, size=3] [L17] COND TRUE i <= size VAL [\old(size)=3, b={143:0}, b={143:0}, i=2, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={143:0}, b={143:0}, i=2, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={143:0}, b={143:0}, b[i]=133, i=2, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={143:0}, b={143:0}, i=3, size=3] [L17] COND TRUE i <= size VAL [\old(size)=3, b={143:0}, b={143:0}, i=3, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={143:0}, b={143:0}, i=3, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={143:0}, b={143:0}, b[i]=135, i=3, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={143:0}, b={143:0}, i=4, size=3] [L17] COND FALSE !(i <= size) VAL [\old(size)=3, b={143:0}, b={143:0}, i=4, size=3] [L20] RET return i; VAL [\old(size)=3, \result=4, b={143:0}, b={143:0}, i=4, size=3] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=4, i=2, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=4, i=2, mask={143:0}] [L26] i++ VAL [b={159:0}, i=3, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=3, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=4, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=4, b={143:0}, b={143:0}, i=0, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={143:0}, b={143:0}, i=0, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={143:0}, b={143:0}, i=0, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={143:0}, b={143:0}, b[i]=160, i=0, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={143:0}, b={143:0}, i=1, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={143:0}, b={143:0}, i=1, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={143:0}, b={143:0}, i=1, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={143:0}, b={143:0}, b[i]=131, i=1, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={143:0}, b={143:0}, i=2, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={143:0}, b={143:0}, i=2, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={143:0}, b={143:0}, i=2, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={143:0}, b={143:0}, b[i]=133, i=2, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={143:0}, b={143:0}, i=3, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={143:0}, b={143:0}, i=3, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={143:0}, b={143:0}, i=3, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={143:0}, b={143:0}, b[i]=135, i=3, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={143:0}, b={143:0}, i=4, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={143:0}, b={143:0}, i=4, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={143:0}, b={143:0}, i=4, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={143:0}, b={143:0}, b[i]=151, i=4, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={143:0}, b={143:0}, i=5, size=4] [L17] COND FALSE !(i <= size) VAL [\old(size)=4, b={143:0}, b={143:0}, i=5, size=4] [L20] RET return i; VAL [\old(size)=4, \result=5, b={143:0}, b={143:0}, i=5, size=4] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=5, i=3, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=5, i=3, mask={143:0}] [L26] i++ VAL [b={159:0}, i=4, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=4, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=5, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=5, b={143:0}, b={143:0}, i=0, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={143:0}, b={143:0}, i=0, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={143:0}, b={143:0}, i=0, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={143:0}, b={143:0}, b[i]=160, i=0, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={143:0}, b={143:0}, i=1, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={143:0}, b={143:0}, i=1, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={143:0}, b={143:0}, i=1, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={143:0}, b={143:0}, b[i]=131, i=1, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={143:0}, b={143:0}, i=2, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={143:0}, b={143:0}, i=2, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={143:0}, b={143:0}, i=2, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={143:0}, b={143:0}, b[i]=133, i=2, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={143:0}, b={143:0}, i=3, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={143:0}, b={143:0}, i=3, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={143:0}, b={143:0}, i=3, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={143:0}, b={143:0}, b[i]=135, i=3, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={143:0}, b={143:0}, i=4, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={143:0}, b={143:0}, i=4, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={143:0}, b={143:0}, i=4, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={143:0}, b={143:0}, b[i]=151, i=4, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={143:0}, b={143:0}, i=5, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={143:0}, b={143:0}, i=5, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={143:0}, b={143:0}, i=5, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={143:0}, b={143:0}, b[i]=137, i=5, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={143:0}, b={143:0}, i=6, size=5] [L17] COND FALSE !(i <= size) VAL [\old(size)=5, b={143:0}, b={143:0}, i=6, size=5] [L20] RET return i; VAL [\old(size)=5, \result=6, b={143:0}, b={143:0}, i=6, size=5] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=6, i=4, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=6, i=4, mask={143:0}] [L26] i++ VAL [b={159:0}, i=5, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=5, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=6, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=6, b={143:0}, b={143:0}, i=0, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={143:0}, b={143:0}, i=0, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={143:0}, b={143:0}, i=0, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={143:0}, b={143:0}, b[i]=160, i=0, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={143:0}, b={143:0}, i=1, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={143:0}, b={143:0}, i=1, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={143:0}, b={143:0}, i=1, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={143:0}, b={143:0}, b[i]=131, i=1, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={143:0}, b={143:0}, i=2, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={143:0}, b={143:0}, i=2, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={143:0}, b={143:0}, i=2, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={143:0}, b={143:0}, b[i]=133, i=2, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={143:0}, b={143:0}, i=3, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={143:0}, b={143:0}, i=3, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={143:0}, b={143:0}, i=3, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={143:0}, b={143:0}, b[i]=135, i=3, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={143:0}, b={143:0}, i=4, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={143:0}, b={143:0}, i=4, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={143:0}, b={143:0}, i=4, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={143:0}, b={143:0}, b[i]=151, i=4, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={143:0}, b={143:0}, i=5, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={143:0}, b={143:0}, i=5, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={143:0}, b={143:0}, i=5, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={143:0}, b={143:0}, b[i]=137, i=5, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={143:0}, b={143:0}, i=6, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={143:0}, b={143:0}, i=6, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={143:0}, b={143:0}, i=6, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={143:0}, b={143:0}, b[i]=136, i=6, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={143:0}, b={143:0}, i=7, size=6] [L17] COND FALSE !(i <= size) VAL [\old(size)=6, b={143:0}, b={143:0}, i=7, size=6] [L20] RET return i; VAL [\old(size)=6, \result=7, b={143:0}, b={143:0}, i=7, size=6] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=7, i=5, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=7, i=5, mask={143:0}] [L26] i++ VAL [b={159:0}, i=6, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=6, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=7, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=7, b={143:0}, b={143:0}, i=0, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={143:0}, b={143:0}, i=0, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={143:0}, b={143:0}, i=0, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={143:0}, b={143:0}, b[i]=160, i=0, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={143:0}, b={143:0}, i=1, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={143:0}, b={143:0}, i=1, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={143:0}, b={143:0}, i=1, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={143:0}, b={143:0}, b[i]=131, i=1, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={143:0}, b={143:0}, i=2, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={143:0}, b={143:0}, i=2, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={143:0}, b={143:0}, i=2, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={143:0}, b={143:0}, b[i]=133, i=2, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={143:0}, b={143:0}, i=3, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={143:0}, b={143:0}, i=3, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={143:0}, b={143:0}, i=3, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={143:0}, b={143:0}, b[i]=135, i=3, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={143:0}, b={143:0}, i=4, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={143:0}, b={143:0}, i=4, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={143:0}, b={143:0}, i=4, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={143:0}, b={143:0}, b[i]=151, i=4, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={143:0}, b={143:0}, i=5, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={143:0}, b={143:0}, i=5, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={143:0}, b={143:0}, i=5, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={143:0}, b={143:0}, b[i]=137, i=5, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={143:0}, b={143:0}, i=6, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={143:0}, b={143:0}, i=6, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={143:0}, b={143:0}, i=6, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={143:0}, b={143:0}, b[i]=136, i=6, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={143:0}, b={143:0}, i=7, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={143:0}, b={143:0}, i=7, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={143:0}, b={143:0}, i=7, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={143:0}, b={143:0}, b[i]=154, i=7, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={143:0}, b={143:0}, i=8, size=7] [L17] COND FALSE !(i <= size) VAL [\old(size)=7, b={143:0}, b={143:0}, i=8, size=7] [L20] RET return i; VAL [\old(size)=7, \result=8, b={143:0}, b={143:0}, i=8, size=7] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=8, i=6, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=8, i=6, mask={143:0}] [L26] i++ VAL [b={159:0}, i=7, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=7, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=8, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=8, b={143:0}, b={143:0}, i=0, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={143:0}, b={143:0}, i=0, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={143:0}, b={143:0}, i=0, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={143:0}, b={143:0}, b[i]=160, i=0, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={143:0}, b={143:0}, i=1, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={143:0}, b={143:0}, i=1, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={143:0}, b={143:0}, i=1, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={143:0}, b={143:0}, b[i]=131, i=1, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={143:0}, b={143:0}, i=2, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={143:0}, b={143:0}, i=2, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={143:0}, b={143:0}, i=2, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={143:0}, b={143:0}, b[i]=133, i=2, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={143:0}, b={143:0}, i=3, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={143:0}, b={143:0}, i=3, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={143:0}, b={143:0}, i=3, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={143:0}, b={143:0}, b[i]=135, i=3, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={143:0}, b={143:0}, i=4, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={143:0}, b={143:0}, i=4, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={143:0}, b={143:0}, i=4, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={143:0}, b={143:0}, b[i]=151, i=4, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={143:0}, b={143:0}, i=5, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={143:0}, b={143:0}, i=5, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={143:0}, b={143:0}, i=5, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={143:0}, b={143:0}, b[i]=137, i=5, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={143:0}, b={143:0}, i=6, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={143:0}, b={143:0}, i=6, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={143:0}, b={143:0}, i=6, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={143:0}, b={143:0}, b[i]=136, i=6, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={143:0}, b={143:0}, i=7, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={143:0}, b={143:0}, i=7, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={143:0}, b={143:0}, i=7, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={143:0}, b={143:0}, b[i]=154, i=7, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={143:0}, b={143:0}, i=8, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={143:0}, b={143:0}, i=8, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={143:0}, b={143:0}, i=8, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={143:0}, b={143:0}, b[i]=132, i=8, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={143:0}, b={143:0}, i=9, size=8] [L17] COND FALSE !(i <= size) VAL [\old(size)=8, b={143:0}, b={143:0}, i=9, size=8] [L20] RET return i; VAL [\old(size)=8, \result=9, b={143:0}, b={143:0}, i=9, size=8] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=9, i=7, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=9, i=7, mask={143:0}] [L26] i++ VAL [b={159:0}, i=8, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=8, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=9, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=9, b={143:0}, b={143:0}, i=0, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={143:0}, b={143:0}, i=0, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=0, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=160, i=0, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=1, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={143:0}, b={143:0}, i=1, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=1, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=131, i=1, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=2, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={143:0}, b={143:0}, i=2, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=2, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=133, i=2, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=3, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={143:0}, b={143:0}, i=3, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=3, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=135, i=3, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=4, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={143:0}, b={143:0}, i=4, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=4, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=151, i=4, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=5, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={143:0}, b={143:0}, i=5, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=5, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=137, i=5, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=6, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={143:0}, b={143:0}, i=6, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=6, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=136, i=6, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=7, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={143:0}, b={143:0}, i=7, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=7, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=154, i=7, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=8, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={143:0}, b={143:0}, i=8, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=8, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=132, i=8, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=9, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={143:0}, b={143:0}, i=9, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={143:0}, b={143:0}, i=9, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={143:0}, b={143:0}, b[i]=138, i=9, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={143:0}, b={143:0}, i=10, size=9] [L17] COND FALSE !(i <= size) VAL [\old(size)=9, b={143:0}, b={143:0}, i=10, size=9] [L20] RET return i; VAL [\old(size)=9, \result=10, b={143:0}, b={143:0}, i=10, size=9] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=10, i=8, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=10, i=8, mask={143:0}] [L26] i++ VAL [b={159:0}, i=9, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=9, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=10, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=10, b={143:0}, b={143:0}, i=0, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={143:0}, b={143:0}, i=0, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=0, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=160, i=0, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=1, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={143:0}, b={143:0}, i=1, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=1, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=131, i=1, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=2, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={143:0}, b={143:0}, i=2, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=2, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=133, i=2, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=3, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={143:0}, b={143:0}, i=3, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=3, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=135, i=3, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=4, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={143:0}, b={143:0}, i=4, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=4, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=151, i=4, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=5, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={143:0}, b={143:0}, i=5, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=5, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=137, i=5, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=6, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={143:0}, b={143:0}, i=6, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=6, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=136, i=6, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=7, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={143:0}, b={143:0}, i=7, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=7, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=154, i=7, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=8, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={143:0}, b={143:0}, i=8, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=8, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=132, i=8, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=9, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={143:0}, b={143:0}, i=9, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=9, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=138, i=9, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=10, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={143:0}, b={143:0}, i=10, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={143:0}, b={143:0}, i=10, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={143:0}, b={143:0}, b[i]=150, i=10, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={143:0}, b={143:0}, i=11, size=10] [L17] COND FALSE !(i <= size) VAL [\old(size)=10, b={143:0}, b={143:0}, i=11, size=10] [L20] RET return i; VAL [\old(size)=10, \result=11, b={143:0}, b={143:0}, i=11, size=10] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=11, i=9, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=11, i=9, mask={143:0}] [L26] i++ VAL [b={159:0}, i=10, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=10, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=11, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=11, b={143:0}, b={143:0}, i=0, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={143:0}, b={143:0}, i=0, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=0, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=160, i=0, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=1, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={143:0}, b={143:0}, i=1, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=1, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=131, i=1, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=2, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={143:0}, b={143:0}, i=2, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=2, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=133, i=2, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=3, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={143:0}, b={143:0}, i=3, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=3, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=135, i=3, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=4, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={143:0}, b={143:0}, i=4, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=4, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=151, i=4, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=5, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={143:0}, b={143:0}, i=5, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=5, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=137, i=5, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=6, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={143:0}, b={143:0}, i=6, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=6, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=136, i=6, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=7, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={143:0}, b={143:0}, i=7, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=7, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=154, i=7, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=8, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={143:0}, b={143:0}, i=8, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=8, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=132, i=8, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=9, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={143:0}, b={143:0}, i=9, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=9, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=138, i=9, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=10, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={143:0}, b={143:0}, i=10, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=10, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=150, i=10, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=11, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={143:0}, b={143:0}, i=11, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={143:0}, b={143:0}, i=11, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={143:0}, b={143:0}, b[i]=129, i=11, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={143:0}, b={143:0}, i=12, size=11] [L17] COND FALSE !(i <= size) VAL [\old(size)=11, b={143:0}, b={143:0}, i=12, size=11] [L20] RET return i; VAL [\old(size)=11, \result=12, b={143:0}, b={143:0}, i=12, size=11] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=12, i=10, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=12, i=10, mask={143:0}] [L26] i++ VAL [b={159:0}, i=11, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=11, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=12, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=12, b={143:0}, b={143:0}, i=0, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={143:0}, b={143:0}, i=0, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=0, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=160, i=0, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=1, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={143:0}, b={143:0}, i=1, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=1, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=131, i=1, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=2, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={143:0}, b={143:0}, i=2, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=2, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=133, i=2, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=3, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={143:0}, b={143:0}, i=3, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=3, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=135, i=3, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=4, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={143:0}, b={143:0}, i=4, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=4, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=151, i=4, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=5, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={143:0}, b={143:0}, i=5, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=5, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=137, i=5, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=6, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={143:0}, b={143:0}, i=6, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=6, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=136, i=6, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=7, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={143:0}, b={143:0}, i=7, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=7, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=154, i=7, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=8, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={143:0}, b={143:0}, i=8, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=8, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=132, i=8, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=9, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={143:0}, b={143:0}, i=9, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=9, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=138, i=9, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=10, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={143:0}, b={143:0}, i=10, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=10, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=150, i=10, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=11, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={143:0}, b={143:0}, i=11, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=11, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=129, i=11, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=12, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={143:0}, b={143:0}, i=12, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={143:0}, b={143:0}, i=12, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={143:0}, b={143:0}, b[i]=144, i=12, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={143:0}, b={143:0}, i=13, size=12] [L17] COND FALSE !(i <= size) VAL [\old(size)=12, b={143:0}, b={143:0}, i=13, size=12] [L20] RET return i; VAL [\old(size)=12, \result=13, b={143:0}, b={143:0}, i=13, size=12] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=13, i=11, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=13, i=11, mask={143:0}] [L26] i++ VAL [b={159:0}, i=12, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=12, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=13, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=13, b={143:0}, b={143:0}, i=0, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={143:0}, b={143:0}, i=0, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=0, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=160, i=0, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=1, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={143:0}, b={143:0}, i=1, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=1, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=131, i=1, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=2, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={143:0}, b={143:0}, i=2, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=2, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=133, i=2, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=3, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={143:0}, b={143:0}, i=3, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=3, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=135, i=3, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=4, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={143:0}, b={143:0}, i=4, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=4, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=151, i=4, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=5, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={143:0}, b={143:0}, i=5, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=5, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=137, i=5, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=6, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={143:0}, b={143:0}, i=6, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=6, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=136, i=6, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=7, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={143:0}, b={143:0}, i=7, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=7, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=154, i=7, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=8, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={143:0}, b={143:0}, i=8, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=8, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=132, i=8, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=9, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={143:0}, b={143:0}, i=9, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=9, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=138, i=9, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=10, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={143:0}, b={143:0}, i=10, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=10, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=150, i=10, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=11, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={143:0}, b={143:0}, i=11, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=11, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=129, i=11, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=12, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={143:0}, b={143:0}, i=12, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=12, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=144, i=12, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=13, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={143:0}, b={143:0}, i=13, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={143:0}, b={143:0}, i=13, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={143:0}, b={143:0}, b[i]=134, i=13, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={143:0}, b={143:0}, i=14, size=13] [L17] COND FALSE !(i <= size) VAL [\old(size)=13, b={143:0}, b={143:0}, i=14, size=13] [L20] RET return i; VAL [\old(size)=13, \result=14, b={143:0}, b={143:0}, i=14, size=13] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=14, i=12, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=14, i=12, mask={143:0}] [L26] i++ VAL [b={159:0}, i=13, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=13, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=14, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=14, b={143:0}, b={143:0}, i=0, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={143:0}, b={143:0}, i=0, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=0, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=160, i=0, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=1, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={143:0}, b={143:0}, i=1, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=1, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=131, i=1, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=2, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={143:0}, b={143:0}, i=2, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=2, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=133, i=2, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=3, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={143:0}, b={143:0}, i=3, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=3, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=135, i=3, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=4, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={143:0}, b={143:0}, i=4, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=4, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=151, i=4, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=5, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={143:0}, b={143:0}, i=5, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=5, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=137, i=5, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=6, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={143:0}, b={143:0}, i=6, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=6, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=136, i=6, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=7, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={143:0}, b={143:0}, i=7, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=7, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=154, i=7, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=8, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={143:0}, b={143:0}, i=8, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=8, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=132, i=8, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=9, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={143:0}, b={143:0}, i=9, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=9, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=138, i=9, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=10, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={143:0}, b={143:0}, i=10, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=10, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=150, i=10, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=11, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={143:0}, b={143:0}, i=11, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=11, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=129, i=11, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=12, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={143:0}, b={143:0}, i=12, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=12, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=144, i=12, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=13, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={143:0}, b={143:0}, i=13, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=13, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=134, i=13, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=14, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={143:0}, b={143:0}, i=14, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={143:0}, b={143:0}, i=14, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={143:0}, b={143:0}, b[i]=155, i=14, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={143:0}, b={143:0}, i=15, size=14] [L17] COND FALSE !(i <= size) VAL [\old(size)=14, b={143:0}, b={143:0}, i=15, size=14] [L20] RET return i; VAL [\old(size)=14, \result=15, b={143:0}, b={143:0}, i=15, size=14] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=15, i=13, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=15, i=13, mask={143:0}] [L26] i++ VAL [b={159:0}, i=14, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=14, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=15, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=15, b={143:0}, b={143:0}, i=0, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={143:0}, b={143:0}, i=0, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=0, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=160, i=0, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=1, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={143:0}, b={143:0}, i=1, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=1, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=131, i=1, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=2, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={143:0}, b={143:0}, i=2, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=2, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=133, i=2, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=3, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={143:0}, b={143:0}, i=3, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=3, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=135, i=3, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=4, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={143:0}, b={143:0}, i=4, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=4, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=151, i=4, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=5, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={143:0}, b={143:0}, i=5, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=5, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=137, i=5, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=6, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={143:0}, b={143:0}, i=6, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=6, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=136, i=6, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=7, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={143:0}, b={143:0}, i=7, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=7, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=154, i=7, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=8, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={143:0}, b={143:0}, i=8, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=8, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=132, i=8, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=9, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={143:0}, b={143:0}, i=9, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=9, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=138, i=9, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=10, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={143:0}, b={143:0}, i=10, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=10, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=150, i=10, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=11, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={143:0}, b={143:0}, i=11, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=11, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=129, i=11, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=12, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={143:0}, b={143:0}, i=12, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=12, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=144, i=12, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=13, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={143:0}, b={143:0}, i=13, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=13, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=134, i=13, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=14, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={143:0}, b={143:0}, i=14, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=14, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=155, i=14, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=15, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={143:0}, b={143:0}, i=15, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={143:0}, b={143:0}, i=15, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={143:0}, b={143:0}, b[i]=142, i=15, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={143:0}, b={143:0}, i=16, size=15] [L17] COND FALSE !(i <= size) VAL [\old(size)=15, b={143:0}, b={143:0}, i=16, size=15] [L20] RET return i; VAL [\old(size)=15, \result=16, b={143:0}, b={143:0}, i=16, size=15] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=16, i=14, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=16, i=14, mask={143:0}] [L26] i++ VAL [b={159:0}, i=15, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=15, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=16, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=16, b={143:0}, b={143:0}, i=0, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={143:0}, b={143:0}, i=0, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=0, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=160, i=0, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=1, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={143:0}, b={143:0}, i=1, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=1, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=131, i=1, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=2, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={143:0}, b={143:0}, i=2, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=2, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=133, i=2, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=3, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={143:0}, b={143:0}, i=3, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=3, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=135, i=3, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=4, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={143:0}, b={143:0}, i=4, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=4, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=151, i=4, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=5, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={143:0}, b={143:0}, i=5, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=5, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=137, i=5, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=6, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={143:0}, b={143:0}, i=6, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=6, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=136, i=6, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=7, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={143:0}, b={143:0}, i=7, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=7, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=154, i=7, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=8, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={143:0}, b={143:0}, i=8, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=8, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=132, i=8, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=9, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={143:0}, b={143:0}, i=9, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=9, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=138, i=9, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=10, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={143:0}, b={143:0}, i=10, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=10, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=150, i=10, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=11, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={143:0}, b={143:0}, i=11, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=11, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=129, i=11, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=12, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={143:0}, b={143:0}, i=12, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=12, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=144, i=12, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=13, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={143:0}, b={143:0}, i=13, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=13, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=134, i=13, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=14, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={143:0}, b={143:0}, i=14, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=14, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=155, i=14, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=15, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={143:0}, b={143:0}, i=15, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=15, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=142, i=15, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=16, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={143:0}, b={143:0}, i=16, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={143:0}, b={143:0}, i=16, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={143:0}, b={143:0}, b[i]=148, i=16, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={143:0}, b={143:0}, i=17, size=16] [L17] COND FALSE !(i <= size) VAL [\old(size)=16, b={143:0}, b={143:0}, i=17, size=16] [L20] RET return i; VAL [\old(size)=16, \result=17, b={143:0}, b={143:0}, i=17, size=16] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=17, i=15, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=17, i=15, mask={143:0}] [L26] i++ VAL [b={159:0}, i=16, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=16, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=17, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=17, b={143:0}, b={143:0}, i=0, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={143:0}, b={143:0}, i=0, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=0, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=160, i=0, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=1, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={143:0}, b={143:0}, i=1, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=1, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=131, i=1, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=2, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={143:0}, b={143:0}, i=2, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=2, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=133, i=2, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=3, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={143:0}, b={143:0}, i=3, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=3, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=135, i=3, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=4, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={143:0}, b={143:0}, i=4, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=4, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=151, i=4, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=5, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={143:0}, b={143:0}, i=5, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=5, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=137, i=5, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=6, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={143:0}, b={143:0}, i=6, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=6, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=136, i=6, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=7, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={143:0}, b={143:0}, i=7, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=7, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=154, i=7, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=8, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={143:0}, b={143:0}, i=8, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=8, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=132, i=8, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=9, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={143:0}, b={143:0}, i=9, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=9, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=138, i=9, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=10, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={143:0}, b={143:0}, i=10, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=10, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=150, i=10, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=11, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={143:0}, b={143:0}, i=11, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=11, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=129, i=11, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=12, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={143:0}, b={143:0}, i=12, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=12, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=144, i=12, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=13, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={143:0}, b={143:0}, i=13, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=13, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=134, i=13, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=14, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={143:0}, b={143:0}, i=14, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=14, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=155, i=14, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=15, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={143:0}, b={143:0}, i=15, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=15, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=142, i=15, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=16, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={143:0}, b={143:0}, i=16, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=16, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=148, i=16, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=17, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={143:0}, b={143:0}, i=17, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={143:0}, b={143:0}, i=17, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={143:0}, b={143:0}, b[i]=163, i=17, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={143:0}, b={143:0}, i=18, size=17] [L17] COND FALSE !(i <= size) VAL [\old(size)=17, b={143:0}, b={143:0}, i=18, size=17] [L20] RET return i; VAL [\old(size)=17, \result=18, b={143:0}, b={143:0}, i=18, size=17] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=18, i=16, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=18, i=16, mask={143:0}] [L26] i++ VAL [b={159:0}, i=17, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=17, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=18, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=18, b={143:0}, b={143:0}, i=0, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={143:0}, b={143:0}, i=0, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=0, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=160, i=0, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=1, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={143:0}, b={143:0}, i=1, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=1, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=131, i=1, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=2, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={143:0}, b={143:0}, i=2, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=2, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=133, i=2, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=3, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={143:0}, b={143:0}, i=3, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=3, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=135, i=3, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=4, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={143:0}, b={143:0}, i=4, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=4, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=151, i=4, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=5, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={143:0}, b={143:0}, i=5, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=5, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=137, i=5, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=6, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={143:0}, b={143:0}, i=6, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=6, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=136, i=6, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=7, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={143:0}, b={143:0}, i=7, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=7, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=154, i=7, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=8, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={143:0}, b={143:0}, i=8, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=8, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=132, i=8, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=9, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={143:0}, b={143:0}, i=9, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=9, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=138, i=9, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=10, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={143:0}, b={143:0}, i=10, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=10, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=150, i=10, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=11, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={143:0}, b={143:0}, i=11, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=11, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=129, i=11, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=12, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={143:0}, b={143:0}, i=12, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=12, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=144, i=12, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=13, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={143:0}, b={143:0}, i=13, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=13, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=134, i=13, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=14, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={143:0}, b={143:0}, i=14, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=14, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=155, i=14, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=15, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={143:0}, b={143:0}, i=15, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=15, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=142, i=15, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=16, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={143:0}, b={143:0}, i=16, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=16, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=148, i=16, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=17, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={143:0}, b={143:0}, i=17, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=17, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=163, i=17, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=18, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={143:0}, b={143:0}, i=18, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={143:0}, b={143:0}, i=18, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={143:0}, b={143:0}, b[i]=146, i=18, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={143:0}, b={143:0}, i=19, size=18] [L17] COND FALSE !(i <= size) VAL [\old(size)=18, b={143:0}, b={143:0}, i=19, size=18] [L20] RET return i; VAL [\old(size)=18, \result=19, b={143:0}, b={143:0}, i=19, size=18] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=19, i=17, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=19, i=17, mask={143:0}] [L26] i++ VAL [b={159:0}, i=18, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=18, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=19, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=19, b={143:0}, b={143:0}, i=0, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={143:0}, b={143:0}, i=0, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=0, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=160, i=0, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=1, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={143:0}, b={143:0}, i=1, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=1, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=131, i=1, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=2, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={143:0}, b={143:0}, i=2, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=2, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=133, i=2, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=3, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={143:0}, b={143:0}, i=3, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=3, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=135, i=3, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=4, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={143:0}, b={143:0}, i=4, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=4, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=151, i=4, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=5, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={143:0}, b={143:0}, i=5, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=5, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=137, i=5, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=6, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={143:0}, b={143:0}, i=6, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=6, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=136, i=6, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=7, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={143:0}, b={143:0}, i=7, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=7, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=154, i=7, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=8, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={143:0}, b={143:0}, i=8, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=8, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=132, i=8, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=9, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={143:0}, b={143:0}, i=9, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=9, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=138, i=9, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=10, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={143:0}, b={143:0}, i=10, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=10, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=150, i=10, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=11, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={143:0}, b={143:0}, i=11, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=11, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=129, i=11, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=12, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={143:0}, b={143:0}, i=12, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=12, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=144, i=12, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=13, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={143:0}, b={143:0}, i=13, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=13, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=134, i=13, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=14, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={143:0}, b={143:0}, i=14, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=14, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=155, i=14, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=15, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={143:0}, b={143:0}, i=15, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=15, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=142, i=15, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=16, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={143:0}, b={143:0}, i=16, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=16, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=148, i=16, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=17, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={143:0}, b={143:0}, i=17, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=17, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=163, i=17, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=18, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={143:0}, b={143:0}, i=18, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=18, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=146, i=18, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=19, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={143:0}, b={143:0}, i=19, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={143:0}, b={143:0}, i=19, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={143:0}, b={143:0}, b[i]=140, i=19, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={143:0}, b={143:0}, i=20, size=19] [L17] COND FALSE !(i <= size) VAL [\old(size)=19, b={143:0}, b={143:0}, i=20, size=19] [L20] RET return i; VAL [\old(size)=19, \result=20, b={143:0}, b={143:0}, i=20, size=19] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=20, i=18, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=20, i=18, mask={143:0}] [L26] i++ VAL [b={159:0}, i=19, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=19, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=20, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=20, b={143:0}, b={143:0}, i=0, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=0, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=0, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=160, i=0, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=1, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=1, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=1, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=131, i=1, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=2, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=2, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=2, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=133, i=2, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=3, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=3, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=3, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=135, i=3, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=4, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=4, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=4, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=151, i=4, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=5, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=5, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=5, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=137, i=5, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=6, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=6, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=6, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=136, i=6, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=7, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=7, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=7, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=154, i=7, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=8, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=8, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=8, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=132, i=8, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=9, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=9, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=9, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=138, i=9, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=10, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=10, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=10, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=150, i=10, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=11, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=11, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=11, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=129, i=11, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=12, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=12, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=12, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=144, i=12, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=13, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=13, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=13, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=134, i=13, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=14, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=14, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=14, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=155, i=14, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=15, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=15, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=15, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=142, i=15, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=16, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=16, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=16, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=148, i=16, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=17, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=17, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=17, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=163, i=17, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=18, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=18, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=18, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=146, i=18, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=19, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=19, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=19, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=140, i=19, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=20, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={143:0}, b={143:0}, i=20, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={143:0}, b={143:0}, i=20, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={143:0}, b={143:0}, b[i]=156, i=20, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={143:0}, b={143:0}, i=21, size=20] [L17] COND FALSE !(i <= size) VAL [\old(size)=20, b={143:0}, b={143:0}, i=21, size=20] [L20] RET return i; VAL [\old(size)=20, \result=21, b={143:0}, b={143:0}, i=21, size=20] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=21, i=19, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=21, i=19, mask={143:0}] [L26] i++ VAL [b={159:0}, i=20, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=20, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=21, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=21, b={143:0}, b={143:0}, i=0, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=0, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=0, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=160, i=0, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=1, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=1, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=1, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=131, i=1, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=2, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=2, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=2, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=133, i=2, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=3, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=3, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=3, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=135, i=3, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=4, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=4, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=4, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=151, i=4, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=5, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=5, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=5, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=137, i=5, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=6, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=6, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=6, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=136, i=6, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=7, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=7, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=7, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=154, i=7, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=8, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=8, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=8, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=132, i=8, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=9, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=9, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=9, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=138, i=9, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=10, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=10, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=10, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=150, i=10, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=11, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=11, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=11, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=129, i=11, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=12, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=12, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=12, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=144, i=12, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=13, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=13, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=13, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=134, i=13, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=14, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=14, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=14, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=155, i=14, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=15, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=15, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=15, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=142, i=15, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=16, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=16, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=16, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=148, i=16, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=17, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=17, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=17, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=163, i=17, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=18, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=18, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=18, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=146, i=18, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=19, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=19, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=19, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=140, i=19, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=20, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=20, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=20, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=156, i=20, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=21, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={143:0}, b={143:0}, i=21, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={143:0}, b={143:0}, i=21, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={143:0}, b={143:0}, b[i]=139, i=21, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={143:0}, b={143:0}, i=22, size=21] [L17] COND FALSE !(i <= size) VAL [\old(size)=21, b={143:0}, b={143:0}, i=22, size=21] [L20] RET return i; VAL [\old(size)=21, \result=22, b={143:0}, b={143:0}, i=22, size=21] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=22, i=20, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=22, i=20, mask={143:0}] [L26] i++ VAL [b={159:0}, i=21, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=21, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=22, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=22, b={143:0}, b={143:0}, i=0, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=0, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=0, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=160, i=0, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=1, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=1, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=1, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=131, i=1, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=2, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=2, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=2, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=133, i=2, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=3, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=3, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=3, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=135, i=3, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=4, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=4, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=4, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=151, i=4, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=5, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=5, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=5, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=137, i=5, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=6, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=6, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=6, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=136, i=6, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=7, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=7, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=7, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=154, i=7, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=8, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=8, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=8, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=132, i=8, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=9, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=9, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=9, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=138, i=9, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=10, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=10, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=10, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=150, i=10, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=11, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=11, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=11, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=129, i=11, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=12, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=12, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=12, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=144, i=12, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=13, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=13, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=13, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=134, i=13, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=14, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=14, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=14, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=155, i=14, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=15, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=15, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=15, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=142, i=15, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=16, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=16, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=16, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=148, i=16, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=17, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=17, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=17, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=163, i=17, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=18, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=18, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=18, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=146, i=18, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=19, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=19, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=19, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=140, i=19, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=20, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=20, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=20, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=156, i=20, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=21, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=21, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=21, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=139, i=21, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=22, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={143:0}, b={143:0}, i=22, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={143:0}, b={143:0}, i=22, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={143:0}, b={143:0}, b[i]=157, i=22, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={143:0}, b={143:0}, i=23, size=22] [L17] COND FALSE !(i <= size) VAL [\old(size)=22, b={143:0}, b={143:0}, i=23, size=22] [L20] RET return i; VAL [\old(size)=22, \result=23, b={143:0}, b={143:0}, i=23, size=22] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=23, i=21, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=23, i=21, mask={143:0}] [L26] i++ VAL [b={159:0}, i=22, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=22, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=23, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=23, b={143:0}, b={143:0}, i=0, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=0, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=0, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=160, i=0, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=1, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=1, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=1, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=131, i=1, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=2, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=2, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=2, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=133, i=2, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=3, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=3, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=3, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=135, i=3, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=4, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=4, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=4, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=151, i=4, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=5, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=5, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=5, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=137, i=5, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=6, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=6, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=6, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=136, i=6, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=7, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=7, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=7, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=154, i=7, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=8, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=8, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=8, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=132, i=8, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=9, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=9, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=9, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=138, i=9, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=10, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=10, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=10, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=150, i=10, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=11, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=11, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=11, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=129, i=11, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=12, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=12, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=12, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=144, i=12, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=13, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=13, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=13, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=134, i=13, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=14, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=14, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=14, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=155, i=14, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=15, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=15, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=15, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=142, i=15, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=16, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=16, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=16, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=148, i=16, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=17, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=17, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=17, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=163, i=17, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=18, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=18, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=18, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=146, i=18, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=19, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=19, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=19, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=140, i=19, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=20, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=20, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=20, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=156, i=20, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=21, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=21, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=21, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=139, i=21, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=22, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=22, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=22, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=157, i=22, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=23, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={143:0}, b={143:0}, i=23, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={143:0}, b={143:0}, i=23, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={143:0}, b={143:0}, b[i]=152, i=23, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={143:0}, b={143:0}, i=24, size=23] [L17] COND FALSE !(i <= size) VAL [\old(size)=23, b={143:0}, b={143:0}, i=24, size=23] [L20] RET return i; VAL [\old(size)=23, \result=24, b={143:0}, b={143:0}, i=24, size=23] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=24, i=22, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=24, i=22, mask={143:0}] [L26] i++ VAL [b={159:0}, i=23, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=23, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=24, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=24, b={143:0}, b={143:0}, i=0, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=0, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=0, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=160, i=0, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=1, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=1, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=1, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=131, i=1, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=2, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=2, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=2, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=133, i=2, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=3, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=3, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=3, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=135, i=3, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=4, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=4, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=4, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=151, i=4, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=5, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=5, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=5, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=137, i=5, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=6, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=6, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=6, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=136, i=6, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=7, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=7, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=7, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=154, i=7, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=8, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=8, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=8, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=132, i=8, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=9, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=9, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=9, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=138, i=9, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=10, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=10, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=10, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=150, i=10, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=11, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=11, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=11, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=129, i=11, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=12, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=12, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=12, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=144, i=12, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=13, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=13, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=13, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=134, i=13, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=14, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=14, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=14, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=155, i=14, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=15, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=15, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=15, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=142, i=15, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=16, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=16, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=16, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=148, i=16, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=17, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=17, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=17, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=163, i=17, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=18, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=18, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=18, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=146, i=18, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=19, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=19, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=19, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=140, i=19, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=20, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=20, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=20, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=156, i=20, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=21, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=21, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=21, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=139, i=21, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=22, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=22, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=22, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=157, i=22, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=23, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=23, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=23, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=152, i=23, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=24, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={143:0}, b={143:0}, i=24, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={143:0}, b={143:0}, i=24, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={143:0}, b={143:0}, b[i]=162, i=24, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={143:0}, b={143:0}, i=25, size=24] [L17] COND FALSE !(i <= size) VAL [\old(size)=24, b={143:0}, b={143:0}, i=25, size=24] [L20] RET return i; VAL [\old(size)=24, \result=25, b={143:0}, b={143:0}, i=25, size=24] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=25, i=23, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=25, i=23, mask={143:0}] [L26] i++ VAL [b={159:0}, i=24, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=24, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=25, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=25, b={143:0}, b={143:0}, i=0, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=0, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=0, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=160, i=0, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=1, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=1, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=1, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=131, i=1, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=2, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=2, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=2, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=133, i=2, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=3, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=3, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=3, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=135, i=3, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=4, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=4, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=4, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=151, i=4, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=5, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=5, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=5, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=137, i=5, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=6, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=6, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=6, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=136, i=6, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=7, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=7, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=7, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=154, i=7, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=8, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=8, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=8, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=132, i=8, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=9, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=9, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=9, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=138, i=9, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=10, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=10, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=10, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=150, i=10, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=11, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=11, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=11, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=129, i=11, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=12, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=12, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=12, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=144, i=12, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=13, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=13, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=13, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=134, i=13, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=14, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=14, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=14, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=155, i=14, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=15, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=15, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=15, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=142, i=15, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=16, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=16, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=16, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=148, i=16, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=17, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=17, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=17, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=163, i=17, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=18, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=18, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=18, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=146, i=18, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=19, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=19, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=19, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=140, i=19, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=20, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=20, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=20, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=156, i=20, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=21, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=21, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=21, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=139, i=21, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=22, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=22, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=22, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=157, i=22, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=23, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=23, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=23, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=152, i=23, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=24, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=24, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=24, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=162, i=24, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=25, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={143:0}, b={143:0}, i=25, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={143:0}, b={143:0}, i=25, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={143:0}, b={143:0}, b[i]=164, i=25, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={143:0}, b={143:0}, i=26, size=25] [L17] COND FALSE !(i <= size) VAL [\old(size)=25, b={143:0}, b={143:0}, i=26, size=25] [L20] RET return i; VAL [\old(size)=25, \result=26, b={143:0}, b={143:0}, i=26, size=25] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=26, i=24, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=26, i=24, mask={143:0}] [L26] i++ VAL [b={159:0}, i=25, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=25, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=26, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=26, b={143:0}, b={143:0}, i=0, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=0, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=0, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=160, i=0, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=1, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=1, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=1, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=131, i=1, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=2, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=2, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=2, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=133, i=2, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=3, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=3, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=3, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=135, i=3, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=4, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=4, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=4, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=151, i=4, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=5, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=5, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=5, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=137, i=5, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=6, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=6, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=6, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=136, i=6, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=7, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=7, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=7, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=154, i=7, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=8, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=8, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=8, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=132, i=8, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=9, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=9, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=9, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=138, i=9, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=10, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=10, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=10, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=150, i=10, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=11, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=11, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=11, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=129, i=11, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=12, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=12, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=12, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=144, i=12, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=13, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=13, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=13, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=134, i=13, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=14, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=14, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=14, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=155, i=14, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=15, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=15, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=15, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=142, i=15, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=16, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=16, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=16, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=148, i=16, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=17, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=17, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=17, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=163, i=17, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=18, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=18, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=18, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=146, i=18, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=19, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=19, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=19, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=140, i=19, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=20, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=20, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=20, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=156, i=20, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=21, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=21, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=21, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=139, i=21, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=22, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=22, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=22, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=157, i=22, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=23, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=23, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=23, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=152, i=23, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=24, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=24, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=24, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=162, i=24, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=25, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=25, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=25, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=164, i=25, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=26, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={143:0}, b={143:0}, i=26, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={143:0}, b={143:0}, i=26, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={143:0}, b={143:0}, b[i]=161, i=26, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={143:0}, b={143:0}, i=27, size=26] [L17] COND FALSE !(i <= size) VAL [\old(size)=26, b={143:0}, b={143:0}, i=27, size=26] [L20] RET return i; VAL [\old(size)=26, \result=27, b={143:0}, b={143:0}, i=27, size=26] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=27, i=25, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=27, i=25, mask={143:0}] [L26] i++ VAL [b={159:0}, i=26, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=26, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=27, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=27, b={143:0}, b={143:0}, i=0, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=0, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=0, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=160, i=0, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=1, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=1, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=1, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=131, i=1, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=2, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=2, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=2, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=133, i=2, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=3, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=3, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=3, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=135, i=3, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=4, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=4, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=4, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=151, i=4, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=5, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=5, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=5, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=137, i=5, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=6, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=6, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=6, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=136, i=6, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=7, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=7, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=7, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=154, i=7, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=8, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=8, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=8, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=132, i=8, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=9, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=9, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=9, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=138, i=9, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=10, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=10, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=10, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=150, i=10, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=11, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=11, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=11, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=129, i=11, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=12, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=12, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=12, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=144, i=12, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=13, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=13, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=13, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=134, i=13, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=14, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=14, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=14, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=155, i=14, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=15, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=15, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=15, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=142, i=15, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=16, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=16, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=16, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=148, i=16, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=17, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=17, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=17, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=163, i=17, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=18, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=18, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=18, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=146, i=18, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=19, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=19, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=19, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=140, i=19, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=20, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=20, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=20, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=156, i=20, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=21, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=21, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=21, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=139, i=21, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=22, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=22, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=22, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=157, i=22, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=23, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=23, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=23, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=152, i=23, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=24, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=24, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=24, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=162, i=24, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=25, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=25, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=25, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=164, i=25, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=26, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=26, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=26, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=161, i=26, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=27, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={143:0}, b={143:0}, i=27, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={143:0}, b={143:0}, i=27, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={143:0}, b={143:0}, b[i]=141, i=27, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={143:0}, b={143:0}, i=28, size=27] [L17] COND FALSE !(i <= size) VAL [\old(size)=27, b={143:0}, b={143:0}, i=28, size=27] [L20] RET return i; VAL [\old(size)=27, \result=28, b={143:0}, b={143:0}, i=28, size=27] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=28, i=26, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=28, i=26, mask={143:0}] [L26] i++ VAL [b={159:0}, i=27, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=27, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=28, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=28, b={143:0}, b={143:0}, i=0, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=0, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=0, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=160, i=0, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=1, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=1, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=1, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=131, i=1, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=2, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=2, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=2, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=133, i=2, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=3, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=3, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=3, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=135, i=3, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=4, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=4, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=4, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=151, i=4, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=5, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=5, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=5, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=137, i=5, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=6, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=6, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=6, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=136, i=6, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=7, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=7, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=7, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=154, i=7, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=8, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=8, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=8, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=132, i=8, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=9, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=9, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=9, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=138, i=9, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=10, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=10, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=10, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=150, i=10, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=11, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=11, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=11, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=129, i=11, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=12, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=12, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=12, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=144, i=12, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=13, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=13, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=13, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=134, i=13, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=14, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=14, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=14, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=155, i=14, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=15, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=15, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=15, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=142, i=15, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=16, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=16, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=16, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=148, i=16, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=17, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=17, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=17, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=163, i=17, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=18, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=18, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=18, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=146, i=18, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=19, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=19, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=19, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=140, i=19, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=20, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=20, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=20, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=156, i=20, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=21, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=21, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=21, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=139, i=21, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=22, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=22, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=22, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=157, i=22, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=23, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=23, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=23, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=152, i=23, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=24, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=24, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=24, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=162, i=24, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=25, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=25, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=25, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=164, i=25, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=26, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=26, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=26, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=161, i=26, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=27, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=27, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=27, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=141, i=27, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=28, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={143:0}, b={143:0}, i=28, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={143:0}, b={143:0}, i=28, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={143:0}, b={143:0}, b[i]=130, i=28, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={143:0}, b={143:0}, i=29, size=28] [L17] COND FALSE !(i <= size) VAL [\old(size)=28, b={143:0}, b={143:0}, i=29, size=28] [L20] RET return i; VAL [\old(size)=28, \result=29, b={143:0}, b={143:0}, i=29, size=28] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=29, i=27, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=29, i=27, mask={143:0}] [L26] i++ VAL [b={159:0}, i=28, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=28, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=29, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=29, b={143:0}, b={143:0}, i=0, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=0, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=0, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=160, i=0, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=1, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=1, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=1, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=131, i=1, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=2, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=2, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=2, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=133, i=2, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=3, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=3, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=3, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=135, i=3, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=4, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=4, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=4, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=151, i=4, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=5, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=5, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=5, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=137, i=5, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=6, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=6, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=6, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=136, i=6, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=7, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=7, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=7, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=154, i=7, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=8, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=8, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=8, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=132, i=8, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=9, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=9, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=9, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=138, i=9, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=10, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=10, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=10, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=150, i=10, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=11, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=11, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=11, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=129, i=11, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=12, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=12, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=12, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=144, i=12, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=13, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=13, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=13, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=134, i=13, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=14, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=14, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=14, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=155, i=14, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=15, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=15, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=15, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=142, i=15, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=16, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=16, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=16, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=148, i=16, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=17, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=17, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=17, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=163, i=17, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=18, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=18, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=18, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=146, i=18, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=19, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=19, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=19, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=140, i=19, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=20, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=20, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=20, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=156, i=20, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=21, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=21, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=21, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=139, i=21, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=22, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=22, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=22, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=157, i=22, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=23, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=23, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=23, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=152, i=23, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=24, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=24, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=24, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=162, i=24, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=25, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=25, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=25, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=164, i=25, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=26, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=26, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=26, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=161, i=26, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=27, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=27, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=27, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=141, i=27, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=28, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=28, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=28, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=130, i=28, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=29, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={143:0}, b={143:0}, i=29, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={143:0}, b={143:0}, i=29, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={143:0}, b={143:0}, b[i]=147, i=29, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={143:0}, b={143:0}, i=30, size=29] [L17] COND FALSE !(i <= size) VAL [\old(size)=29, b={143:0}, b={143:0}, i=30, size=29] [L20] RET return i; VAL [\old(size)=29, \result=30, b={143:0}, b={143:0}, i=30, size=29] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=30, i=28, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=30, i=28, mask={143:0}] [L26] i++ VAL [b={159:0}, i=29, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=29, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=30, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=30, b={143:0}, b={143:0}, i=0, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=0, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=0, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=160, i=0, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=1, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=1, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=1, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=131, i=1, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=2, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=2, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=2, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=133, i=2, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=3, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=3, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=3, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=135, i=3, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=4, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=4, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=4, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=151, i=4, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=5, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=5, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=5, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=137, i=5, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=6, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=6, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=6, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=136, i=6, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=7, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=7, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=7, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=154, i=7, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=8, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=8, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=8, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=132, i=8, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=9, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=9, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=9, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=138, i=9, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=10, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=10, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=10, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=150, i=10, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=11, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=11, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=11, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=129, i=11, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=12, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=12, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=12, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=144, i=12, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=13, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=13, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=13, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=134, i=13, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=14, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=14, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=14, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=155, i=14, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=15, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=15, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=15, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=142, i=15, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=16, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=16, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=16, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=148, i=16, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=17, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=17, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=17, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=163, i=17, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=18, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=18, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=18, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=146, i=18, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=19, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=19, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=19, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=140, i=19, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=20, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=20, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=20, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=156, i=20, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=21, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=21, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=21, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=139, i=21, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=22, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=22, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=22, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=157, i=22, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=23, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=23, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=23, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=152, i=23, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=24, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=24, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=24, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=162, i=24, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=25, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=25, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=25, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=164, i=25, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=26, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=26, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=26, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=161, i=26, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=27, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=27, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=27, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=141, i=27, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=28, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=28, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=28, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=130, i=28, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=29, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=29, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=29, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=147, i=29, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=30, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={143:0}, b={143:0}, i=30, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={143:0}, b={143:0}, i=30, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={143:0}, b={143:0}, b[i]=153, i=30, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={143:0}, b={143:0}, i=31, size=30] [L17] COND FALSE !(i <= size) VAL [\old(size)=30, b={143:0}, b={143:0}, i=31, size=30] [L20] RET return i; VAL [\old(size)=30, \result=31, b={143:0}, b={143:0}, i=31, size=30] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=31, i=29, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=31, i=29, mask={143:0}] [L26] i++ VAL [b={159:0}, i=30, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=30, mask={143:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=31, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=31, b={143:0}, b={143:0}, i=0, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=0, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=0, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=160, i=0, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=1, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=1, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=1, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=131, i=1, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=2, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=2, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=2, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=133, i=2, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=3, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=3, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=3, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=135, i=3, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=4, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=4, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=4, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=151, i=4, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=5, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=5, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=5, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=137, i=5, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=6, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=6, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=6, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=136, i=6, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=7, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=7, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=7, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=154, i=7, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=8, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=8, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=8, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=132, i=8, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=9, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=9, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=9, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=138, i=9, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=10, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=10, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=10, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=150, i=10, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=11, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=11, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=11, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=129, i=11, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=12, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=12, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=12, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=144, i=12, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=13, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=13, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=13, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=134, i=13, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=14, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=14, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=14, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=155, i=14, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=15, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=15, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=15, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=142, i=15, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=16, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=16, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=16, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=148, i=16, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=17, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=17, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=17, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=163, i=17, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=18, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=18, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=18, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=146, i=18, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=19, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=19, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=19, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=140, i=19, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=20, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=20, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=20, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=156, i=20, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=21, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=21, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=21, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=139, i=21, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=22, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=22, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=22, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=157, i=22, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=23, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=23, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=23, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=152, i=23, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=24, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=24, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=24, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=162, i=24, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=25, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=25, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=25, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=164, i=25, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=26, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=26, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=26, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=161, i=26, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=27, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=27, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=27, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=141, i=27, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=28, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=28, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=28, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=130, i=28, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=29, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=29, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=29, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=147, i=29, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=30, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=30, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=30, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=153, i=30, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=31, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={143:0}, b={143:0}, i=31, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={143:0}, b={143:0}, i=31, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={143:0}, b={143:0}, b[i]=145, i=31, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={143:0}, b={143:0}, i=32, size=31] [L17] COND FALSE !(i <= size) VAL [\old(size)=31, b={143:0}, b={143:0}, i=32, size=31] [L20] RET return i; VAL [\old(size)=31, \result=32, b={143:0}, b={143:0}, i=32, size=31] [L27] EXPR foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=32, i=30, mask={143:0}] [L27] FCALL b[i] = foo(mask, i + 1) VAL [b={159:0}, foo(mask, i + 1)=32, i=30, mask={143:0}] [L26] i++ VAL [b={159:0}, i=31, mask={143:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={159:0}, i=31, mask={143:0}] [L27] CALL foo(mask, i + 1) VAL [\old(size)=32, b={143:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=32, b={143:0}, b={143:0}, i=0, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=0, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=0, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=160, i=0, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=1, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=1, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=1, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=131, i=1, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=2, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=2, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=2, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=133, i=2, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=3, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=3, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=3, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=135, i=3, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=4, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=4, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=4, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=151, i=4, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=5, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=5, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=5, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=137, i=5, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=6, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=6, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=6, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=136, i=6, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=7, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=7, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=7, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=154, i=7, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=8, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=8, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=8, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=132, i=8, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=9, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=9, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=9, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=138, i=9, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=10, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=10, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=10, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=150, i=10, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=11, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=11, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=11, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=129, i=11, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=12, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=12, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=12, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=144, i=12, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=13, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=13, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=13, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=134, i=13, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=14, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=14, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=14, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=155, i=14, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=15, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=15, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=15, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=142, i=15, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=16, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=16, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=16, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=148, i=16, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=17, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=17, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=17, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=163, i=17, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=18, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=18, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=18, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=146, i=18, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=19, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=19, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=19, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=140, i=19, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=20, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=20, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=20, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=156, i=20, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=21, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=21, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=21, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=139, i=21, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=22, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=22, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=22, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=157, i=22, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=23, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=23, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=23, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=152, i=23, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=24, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=24, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=24, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=162, i=24, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=25, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=25, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=25, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=164, i=25, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=26, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=26, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=26, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=161, i=26, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=27, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=27, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=27, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=141, i=27, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=28, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=28, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=28, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=130, i=28, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=29, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=29, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=29, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=147, i=29, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=30, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=30, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=30, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=153, i=30, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=31, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=31, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=31, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={143:0}, b={143:0}, b[i]=145, i=31, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={143:0}, b={143:0}, i=32, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={143:0}, b={143:0}, i=32, size=32] [L18] a[i] VAL [\old(size)=32, b={143:0}, b={143:0}, i=32, size=32] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 43 locations, 8 error locations. UNSAFE Result, 560.8s OverallTime, 89 OverallIterations, 591 TraceHistogramMax, 134.2s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 4604 SDtfs, 84383 SDslu, 86024 SDs, 0 SdLazy, 234020 SolverSat, 13209 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 54.2s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 121332 GetRequests, 112633 SyntacticMatches, 21 SemanticMatches, 8678 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 440473 ImplicationChecksByTransitivity, 125.4s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=3952occurred in iteration=85, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.7s AutomataMinimizationTime, 88 MinimizatonAttempts, 1369 StatesRemovedByMinimization, 85 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 3.8s SsaConstructionTime, 198.6s SatisfiabilityAnalysisTime, 145.1s InterpolantComputationTime, 232687 NumberOfCodeBlocks, 216838 NumberOfCodeBlocksAsserted, 1318 NumberOfCheckSat, 228749 ConstructedInterpolants, 139 QuantifiedInterpolants, 774926612 SizeOfPredicates, 204 NumberOfNonLiveVariables, 223534 ConjunctsInSsa, 2653 ConjunctsInUnsatCore, 168 InterpolantComputations, 9 PerfectInterpolantSequences, 34708935/35177818 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...