./Ultimate.py --spec ../../sv-benchmarks/c/ReachSafety.prp --file ../../sv-benchmarks/c/psyco/psyco_abp_1_false-unreach-call_false-termination_true-no-overflow.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 5842f4b8 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/psyco/psyco_abp_1_false-unreach-call_false-termination_true-no-overflow.c -s /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/config/svcomp-Reach-32bit-PetriAutomizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 747981090a474d9d2269aea1ffd03eef2ddc8848 ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-5842f4b [2018-11-18 15:50:14,853 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-18 15:50:14,854 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-18 15:50:14,862 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-18 15:50:14,862 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-18 15:50:14,863 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-18 15:50:14,864 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-18 15:50:14,865 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-18 15:50:14,866 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-18 15:50:14,867 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-18 15:50:14,867 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-18 15:50:14,868 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-18 15:50:14,868 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-18 15:50:14,870 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-18 15:50:14,870 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-18 15:50:14,871 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-18 15:50:14,871 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-18 15:50:14,873 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-18 15:50:14,875 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-18 15:50:14,876 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-18 15:50:14,877 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-18 15:50:14,878 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-18 15:50:14,880 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-18 15:50:14,880 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-18 15:50:14,880 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-18 15:50:14,881 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-18 15:50:14,882 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-18 15:50:14,882 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-18 15:50:14,883 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-18 15:50:14,884 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-18 15:50:14,884 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-18 15:50:14,885 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-18 15:50:14,885 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-18 15:50:14,885 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-18 15:50:14,886 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-18 15:50:14,887 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-18 15:50:14,887 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/config/svcomp-Reach-32bit-PetriAutomizer_Default.epf [2018-11-18 15:50:14,902 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-18 15:50:14,902 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-18 15:50:14,903 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-18 15:50:14,903 INFO L133 SettingsManager]: * Process only entry and re-entry procedures=false [2018-11-18 15:50:14,903 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-18 15:50:14,903 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-18 15:50:14,903 INFO L133 SettingsManager]: * Use SBE=true [2018-11-18 15:50:14,904 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-18 15:50:14,904 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-18 15:50:14,904 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-18 15:50:14,904 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-18 15:50:14,904 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-18 15:50:14,904 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-18 15:50:14,904 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-18 15:50:14,904 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-18 15:50:14,905 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-18 15:50:14,905 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-18 15:50:14,905 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-18 15:50:14,905 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-18 15:50:14,905 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-18 15:50:14,905 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-18 15:50:14,905 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-18 15:50:14,905 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-18 15:50:14,906 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-18 15:50:14,906 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-18 15:50:14,906 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-18 15:50:14,906 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-18 15:50:14,906 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-18 15:50:14,906 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-18 15:50:14,906 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-18 15:50:14,906 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 747981090a474d9d2269aea1ffd03eef2ddc8848 [2018-11-18 15:50:14,930 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-18 15:50:14,939 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-18 15:50:14,941 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-18 15:50:14,943 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-18 15:50:14,943 INFO L276 PluginConnector]: CDTParser initialized [2018-11-18 15:50:14,944 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/../../sv-benchmarks/c/psyco/psyco_abp_1_false-unreach-call_false-termination_true-no-overflow.c [2018-11-18 15:50:14,985 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/data/f96eecee5/f6cc62c8e854470691fd142cfecda01a/FLAGaba43dbef [2018-11-18 15:50:15,360 INFO L307 CDTParser]: Found 1 translation units. [2018-11-18 15:50:15,360 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/sv-benchmarks/c/psyco/psyco_abp_1_false-unreach-call_false-termination_true-no-overflow.c [2018-11-18 15:50:15,370 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/data/f96eecee5/f6cc62c8e854470691fd142cfecda01a/FLAGaba43dbef [2018-11-18 15:50:15,760 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/data/f96eecee5/f6cc62c8e854470691fd142cfecda01a [2018-11-18 15:50:15,763 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-18 15:50:15,764 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-11-18 15:50:15,765 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-18 15:50:15,765 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-18 15:50:15,768 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-18 15:50:15,769 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 03:50:15" (1/1) ... [2018-11-18 15:50:15,771 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6b17c7b5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:50:15, skipping insertion in model container [2018-11-18 15:50:15,772 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 03:50:15" (1/1) ... [2018-11-18 15:50:15,778 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-18 15:50:15,817 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-18 15:50:16,008 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 15:50:16,011 INFO L191 MainTranslator]: Completed pre-run [2018-11-18 15:50:16,063 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 15:50:16,076 INFO L195 MainTranslator]: Completed translation [2018-11-18 15:50:16,076 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:50:16 WrapperNode [2018-11-18 15:50:16,076 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-18 15:50:16,077 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-18 15:50:16,077 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-18 15:50:16,077 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-18 15:50:16,142 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:50:16" (1/1) ... [2018-11-18 15:50:16,142 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:50:16" (1/1) ... [2018-11-18 15:50:16,151 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:50:16" (1/1) ... [2018-11-18 15:50:16,151 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:50:16" (1/1) ... [2018-11-18 15:50:16,166 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:50:16" (1/1) ... [2018-11-18 15:50:16,176 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:50:16" (1/1) ... [2018-11-18 15:50:16,181 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:50:16" (1/1) ... [2018-11-18 15:50:16,185 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-18 15:50:16,185 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-18 15:50:16,185 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-18 15:50:16,185 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-18 15:50:16,187 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:50:16" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-18 15:50:16,241 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-18 15:50:16,242 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-18 15:50:16,242 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-18 15:50:16,242 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-11-18 15:50:16,242 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-11-18 15:50:16,242 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-18 15:50:16,242 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-18 15:50:16,242 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-18 15:50:17,379 INFO L278 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-18 15:50:17,379 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 03:50:17 BoogieIcfgContainer [2018-11-18 15:50:17,379 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-18 15:50:17,380 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-18 15:50:17,380 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-18 15:50:17,383 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-18 15:50:17,383 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 18.11 03:50:15" (1/3) ... [2018-11-18 15:50:17,384 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1bf8bb2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 18.11 03:50:17, skipping insertion in model container [2018-11-18 15:50:17,384 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:50:16" (2/3) ... [2018-11-18 15:50:17,386 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1bf8bb2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 18.11 03:50:17, skipping insertion in model container [2018-11-18 15:50:17,386 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 03:50:17" (3/3) ... [2018-11-18 15:50:17,389 INFO L112 eAbstractionObserver]: Analyzing ICFG psyco_abp_1_false-unreach-call_false-termination_true-no-overflow.c [2018-11-18 15:50:17,400 INFO L136 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-18 15:50:17,408 INFO L148 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-18 15:50:17,425 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-18 15:50:17,457 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-18 15:50:17,458 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-18 15:50:17,458 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-18 15:50:17,458 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-18 15:50:17,458 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-18 15:50:17,458 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-18 15:50:17,459 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-18 15:50:17,459 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-18 15:50:17,459 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-18 15:50:17,484 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states. [2018-11-18 15:50:17,491 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-11-18 15:50:17,491 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:17,492 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:17,494 INFO L423 AbstractCegarLoop]: === Iteration 1 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:17,501 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:17,501 INFO L82 PathProgramCache]: Analyzing trace with hash -662778961, now seen corresponding path program 1 times [2018-11-18 15:50:17,503 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:17,503 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:17,533 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:17,533 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:17,533 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:17,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:17,640 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:50:17,642 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:50:17,642 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:50:17,645 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 15:50:17,653 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:50:17,653 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:50:17,655 INFO L87 Difference]: Start difference. First operand 115 states. Second operand 3 states. [2018-11-18 15:50:18,160 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:18,160 INFO L93 Difference]: Finished difference Result 331 states and 635 transitions. [2018-11-18 15:50:18,161 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:50:18,162 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 14 [2018-11-18 15:50:18,163 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:18,173 INFO L225 Difference]: With dead ends: 331 [2018-11-18 15:50:18,174 INFO L226 Difference]: Without dead ends: 206 [2018-11-18 15:50:18,177 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:50:18,198 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 206 states. [2018-11-18 15:50:18,221 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 206 to 182. [2018-11-18 15:50:18,223 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 182 states. [2018-11-18 15:50:18,225 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 182 states to 182 states and 314 transitions. [2018-11-18 15:50:18,227 INFO L78 Accepts]: Start accepts. Automaton has 182 states and 314 transitions. Word has length 14 [2018-11-18 15:50:18,227 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:18,227 INFO L480 AbstractCegarLoop]: Abstraction has 182 states and 314 transitions. [2018-11-18 15:50:18,227 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 15:50:18,227 INFO L276 IsEmpty]: Start isEmpty. Operand 182 states and 314 transitions. [2018-11-18 15:50:18,228 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-11-18 15:50:18,228 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:18,228 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:18,228 INFO L423 AbstractCegarLoop]: === Iteration 2 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:18,229 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:18,229 INFO L82 PathProgramCache]: Analyzing trace with hash -1058783719, now seen corresponding path program 1 times [2018-11-18 15:50:18,229 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:18,229 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:18,230 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:18,230 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:18,230 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:18,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:18,278 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:50:18,278 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:50:18,278 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:50:18,279 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 15:50:18,279 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:50:18,280 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:50:18,280 INFO L87 Difference]: Start difference. First operand 182 states and 314 transitions. Second operand 3 states. [2018-11-18 15:50:18,333 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:18,333 INFO L93 Difference]: Finished difference Result 365 states and 632 transitions. [2018-11-18 15:50:18,333 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:50:18,334 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 15 [2018-11-18 15:50:18,334 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:18,335 INFO L225 Difference]: With dead ends: 365 [2018-11-18 15:50:18,335 INFO L226 Difference]: Without dead ends: 189 [2018-11-18 15:50:18,336 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:50:18,337 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 189 states. [2018-11-18 15:50:18,348 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 189 to 189. [2018-11-18 15:50:18,348 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 189 states. [2018-11-18 15:50:18,349 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 189 states to 189 states and 322 transitions. [2018-11-18 15:50:18,349 INFO L78 Accepts]: Start accepts. Automaton has 189 states and 322 transitions. Word has length 15 [2018-11-18 15:50:18,350 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:18,350 INFO L480 AbstractCegarLoop]: Abstraction has 189 states and 322 transitions. [2018-11-18 15:50:18,350 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 15:50:18,350 INFO L276 IsEmpty]: Start isEmpty. Operand 189 states and 322 transitions. [2018-11-18 15:50:18,351 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-11-18 15:50:18,351 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:18,351 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:18,351 INFO L423 AbstractCegarLoop]: === Iteration 3 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:18,351 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:18,351 INFO L82 PathProgramCache]: Analyzing trace with hash -426524154, now seen corresponding path program 1 times [2018-11-18 15:50:18,352 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:18,352 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:18,352 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:18,352 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:18,353 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:18,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:18,748 WARN L180 SmtUtils]: Spent 178.00 ms on a formula simplification. DAG size of input: 80 DAG size of output: 22 [2018-11-18 15:50:18,750 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:50:18,751 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:50:18,751 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-18 15:50:18,751 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-18 15:50:18,751 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-18 15:50:18,752 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-18 15:50:18,752 INFO L87 Difference]: Start difference. First operand 189 states and 322 transitions. Second operand 4 states. [2018-11-18 15:50:19,092 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:19,092 INFO L93 Difference]: Finished difference Result 290 states and 484 transitions. [2018-11-18 15:50:19,093 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:50:19,093 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 21 [2018-11-18 15:50:19,093 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:19,095 INFO L225 Difference]: With dead ends: 290 [2018-11-18 15:50:19,095 INFO L226 Difference]: Without dead ends: 274 [2018-11-18 15:50:19,096 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-18 15:50:19,096 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 274 states. [2018-11-18 15:50:19,107 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 274 to 259. [2018-11-18 15:50:19,107 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 259 states. [2018-11-18 15:50:19,109 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 259 states to 259 states and 436 transitions. [2018-11-18 15:50:19,110 INFO L78 Accepts]: Start accepts. Automaton has 259 states and 436 transitions. Word has length 21 [2018-11-18 15:50:19,110 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:19,110 INFO L480 AbstractCegarLoop]: Abstraction has 259 states and 436 transitions. [2018-11-18 15:50:19,110 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-18 15:50:19,110 INFO L276 IsEmpty]: Start isEmpty. Operand 259 states and 436 transitions. [2018-11-18 15:50:19,111 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-11-18 15:50:19,111 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:19,111 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:19,111 INFO L423 AbstractCegarLoop]: === Iteration 4 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:19,112 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:19,112 INFO L82 PathProgramCache]: Analyzing trace with hash -1881066880, now seen corresponding path program 1 times [2018-11-18 15:50:19,112 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:19,112 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:19,114 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:19,114 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:19,115 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:19,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:19,174 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:50:19,174 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:50:19,174 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:50:19,174 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 15:50:19,174 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:50:19,175 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:50:19,175 INFO L87 Difference]: Start difference. First operand 259 states and 436 transitions. Second operand 3 states. [2018-11-18 15:50:19,265 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:19,265 INFO L93 Difference]: Finished difference Result 468 states and 791 transitions. [2018-11-18 15:50:19,265 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:50:19,265 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 22 [2018-11-18 15:50:19,266 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:19,267 INFO L225 Difference]: With dead ends: 468 [2018-11-18 15:50:19,267 INFO L226 Difference]: Without dead ends: 216 [2018-11-18 15:50:19,268 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:50:19,268 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 216 states. [2018-11-18 15:50:19,273 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 216 to 214. [2018-11-18 15:50:19,274 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 214 states. [2018-11-18 15:50:19,275 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 214 states to 214 states and 355 transitions. [2018-11-18 15:50:19,275 INFO L78 Accepts]: Start accepts. Automaton has 214 states and 355 transitions. Word has length 22 [2018-11-18 15:50:19,275 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:19,275 INFO L480 AbstractCegarLoop]: Abstraction has 214 states and 355 transitions. [2018-11-18 15:50:19,276 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 15:50:19,276 INFO L276 IsEmpty]: Start isEmpty. Operand 214 states and 355 transitions. [2018-11-18 15:50:19,278 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-11-18 15:50:19,278 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:19,278 INFO L375 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:19,278 INFO L423 AbstractCegarLoop]: === Iteration 5 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:19,278 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:19,278 INFO L82 PathProgramCache]: Analyzing trace with hash 30525515, now seen corresponding path program 1 times [2018-11-18 15:50:19,279 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:19,279 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:19,279 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:19,280 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:19,280 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:19,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:19,381 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 11 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:50:19,382 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:50:19,382 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:50:19,391 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:19,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:19,427 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:50:19,445 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-11-18 15:50:19,467 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-18 15:50:19,467 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [4] total 5 [2018-11-18 15:50:19,467 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 15:50:19,467 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:50:19,468 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:50:19,468 INFO L87 Difference]: Start difference. First operand 214 states and 355 transitions. Second operand 5 states. [2018-11-18 15:50:19,728 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:19,729 INFO L93 Difference]: Finished difference Result 498 states and 813 transitions. [2018-11-18 15:50:19,729 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-18 15:50:19,729 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 28 [2018-11-18 15:50:19,729 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:19,730 INFO L225 Difference]: With dead ends: 498 [2018-11-18 15:50:19,730 INFO L226 Difference]: Without dead ends: 288 [2018-11-18 15:50:19,731 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 35 GetRequests, 30 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2018-11-18 15:50:19,731 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 288 states. [2018-11-18 15:50:19,740 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 288 to 245. [2018-11-18 15:50:19,740 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 245 states. [2018-11-18 15:50:19,742 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 245 states to 245 states and 408 transitions. [2018-11-18 15:50:19,742 INFO L78 Accepts]: Start accepts. Automaton has 245 states and 408 transitions. Word has length 28 [2018-11-18 15:50:19,742 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:19,742 INFO L480 AbstractCegarLoop]: Abstraction has 245 states and 408 transitions. [2018-11-18 15:50:19,743 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 15:50:19,743 INFO L276 IsEmpty]: Start isEmpty. Operand 245 states and 408 transitions. [2018-11-18 15:50:19,743 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2018-11-18 15:50:19,744 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:19,744 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:19,744 INFO L423 AbstractCegarLoop]: === Iteration 6 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:19,744 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:19,744 INFO L82 PathProgramCache]: Analyzing trace with hash 2061294478, now seen corresponding path program 1 times [2018-11-18 15:50:19,744 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:19,745 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:19,745 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:19,746 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:19,746 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:19,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:19,816 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:50:19,816 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:50:19,816 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:50:19,851 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:19,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:19,881 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:50:19,911 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:50:19,935 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:50:19,935 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 5 [2018-11-18 15:50:19,936 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 15:50:19,936 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:50:19,936 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:50:19,937 INFO L87 Difference]: Start difference. First operand 245 states and 408 transitions. Second operand 5 states. [2018-11-18 15:50:20,146 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:20,146 INFO L93 Difference]: Finished difference Result 464 states and 780 transitions. [2018-11-18 15:50:20,146 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 15:50:20,147 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 30 [2018-11-18 15:50:20,147 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:20,148 INFO L225 Difference]: With dead ends: 464 [2018-11-18 15:50:20,148 INFO L226 Difference]: Without dead ends: 452 [2018-11-18 15:50:20,149 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 30 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:50:20,149 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 452 states. [2018-11-18 15:50:20,160 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 452 to 438. [2018-11-18 15:50:20,160 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 438 states. [2018-11-18 15:50:20,162 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 438 states to 438 states and 730 transitions. [2018-11-18 15:50:20,162 INFO L78 Accepts]: Start accepts. Automaton has 438 states and 730 transitions. Word has length 30 [2018-11-18 15:50:20,162 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:20,163 INFO L480 AbstractCegarLoop]: Abstraction has 438 states and 730 transitions. [2018-11-18 15:50:20,163 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 15:50:20,163 INFO L276 IsEmpty]: Start isEmpty. Operand 438 states and 730 transitions. [2018-11-18 15:50:20,163 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2018-11-18 15:50:20,164 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:20,164 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:20,164 INFO L423 AbstractCegarLoop]: === Iteration 7 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:20,164 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:20,164 INFO L82 PathProgramCache]: Analyzing trace with hash -512937066, now seen corresponding path program 1 times [2018-11-18 15:50:20,164 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:20,164 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:20,165 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:20,165 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:20,165 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:20,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:20,343 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:50:20,343 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:50:20,343 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:50:20,354 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:20,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:20,395 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:50:20,525 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:50:20,557 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:50:20,557 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 4] total 6 [2018-11-18 15:50:20,558 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-18 15:50:20,558 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-18 15:50:20,558 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:50:20,558 INFO L87 Difference]: Start difference. First operand 438 states and 730 transitions. Second operand 6 states. [2018-11-18 15:50:20,737 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:20,737 INFO L93 Difference]: Finished difference Result 495 states and 817 transitions. [2018-11-18 15:50:20,737 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-18 15:50:20,737 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 31 [2018-11-18 15:50:20,738 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:20,739 INFO L225 Difference]: With dead ends: 495 [2018-11-18 15:50:20,739 INFO L226 Difference]: Without dead ends: 490 [2018-11-18 15:50:20,740 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 35 GetRequests, 30 SyntacticMatches, 1 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:50:20,740 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 490 states. [2018-11-18 15:50:20,748 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 490 to 484. [2018-11-18 15:50:20,749 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 484 states. [2018-11-18 15:50:20,750 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 484 states to 484 states and 802 transitions. [2018-11-18 15:50:20,751 INFO L78 Accepts]: Start accepts. Automaton has 484 states and 802 transitions. Word has length 31 [2018-11-18 15:50:20,751 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:20,751 INFO L480 AbstractCegarLoop]: Abstraction has 484 states and 802 transitions. [2018-11-18 15:50:20,751 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-18 15:50:20,751 INFO L276 IsEmpty]: Start isEmpty. Operand 484 states and 802 transitions. [2018-11-18 15:50:20,752 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-11-18 15:50:20,752 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:20,752 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:20,752 INFO L423 AbstractCegarLoop]: === Iteration 8 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:20,752 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:20,753 INFO L82 PathProgramCache]: Analyzing trace with hash 325020427, now seen corresponding path program 1 times [2018-11-18 15:50:20,753 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:20,753 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:20,753 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:20,753 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:20,754 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:20,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:20,838 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-11-18 15:50:20,838 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:50:20,839 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:50:20,839 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 15:50:20,839 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:50:20,839 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:50:20,839 INFO L87 Difference]: Start difference. First operand 484 states and 802 transitions. Second operand 3 states. [2018-11-18 15:50:20,918 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:20,918 INFO L93 Difference]: Finished difference Result 949 states and 1566 transitions. [2018-11-18 15:50:20,918 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:50:20,918 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 32 [2018-11-18 15:50:20,919 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:20,920 INFO L225 Difference]: With dead ends: 949 [2018-11-18 15:50:20,921 INFO L226 Difference]: Without dead ends: 495 [2018-11-18 15:50:20,921 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:50:20,922 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 495 states. [2018-11-18 15:50:20,932 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 495 to 493. [2018-11-18 15:50:20,932 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 493 states. [2018-11-18 15:50:20,934 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 493 states to 493 states and 794 transitions. [2018-11-18 15:50:20,935 INFO L78 Accepts]: Start accepts. Automaton has 493 states and 794 transitions. Word has length 32 [2018-11-18 15:50:20,935 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:20,935 INFO L480 AbstractCegarLoop]: Abstraction has 493 states and 794 transitions. [2018-11-18 15:50:20,935 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 15:50:20,935 INFO L276 IsEmpty]: Start isEmpty. Operand 493 states and 794 transitions. [2018-11-18 15:50:20,936 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-11-18 15:50:20,936 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:20,936 INFO L375 BasicCegarLoop]: trace histogram [4, 4, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:20,936 INFO L423 AbstractCegarLoop]: === Iteration 9 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:20,942 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:20,943 INFO L82 PathProgramCache]: Analyzing trace with hash 2019699710, now seen corresponding path program 1 times [2018-11-18 15:50:20,943 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:20,943 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:20,944 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:20,944 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:20,944 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:20,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:21,046 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-18 15:50:21,046 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:50:21,046 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:50:21,047 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 15:50:21,047 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:50:21,047 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:50:21,047 INFO L87 Difference]: Start difference. First operand 493 states and 794 transitions. Second operand 3 states. [2018-11-18 15:50:21,236 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:21,238 INFO L93 Difference]: Finished difference Result 939 states and 1525 transitions. [2018-11-18 15:50:21,239 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:50:21,239 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 40 [2018-11-18 15:50:21,240 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:21,243 INFO L225 Difference]: With dead ends: 939 [2018-11-18 15:50:21,243 INFO L226 Difference]: Without dead ends: 495 [2018-11-18 15:50:21,244 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:50:21,244 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 495 states. [2018-11-18 15:50:21,255 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 495 to 493. [2018-11-18 15:50:21,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 493 states. [2018-11-18 15:50:21,257 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 493 states to 493 states and 788 transitions. [2018-11-18 15:50:21,257 INFO L78 Accepts]: Start accepts. Automaton has 493 states and 788 transitions. Word has length 40 [2018-11-18 15:50:21,257 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:21,257 INFO L480 AbstractCegarLoop]: Abstraction has 493 states and 788 transitions. [2018-11-18 15:50:21,257 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 15:50:21,258 INFO L276 IsEmpty]: Start isEmpty. Operand 493 states and 788 transitions. [2018-11-18 15:50:21,260 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-11-18 15:50:21,262 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:21,262 INFO L375 BasicCegarLoop]: trace histogram [4, 4, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:21,263 INFO L423 AbstractCegarLoop]: === Iteration 10 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:21,263 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:21,263 INFO L82 PathProgramCache]: Analyzing trace with hash 937434793, now seen corresponding path program 1 times [2018-11-18 15:50:21,263 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:21,263 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:21,264 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:21,264 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:21,264 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:21,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:21,748 WARN L180 SmtUtils]: Spent 195.00 ms on a formula simplification. DAG size of input: 12 DAG size of output: 11 [2018-11-18 15:50:22,117 WARN L180 SmtUtils]: Spent 192.00 ms on a formula simplification. DAG size of input: 31 DAG size of output: 20 [2018-11-18 15:50:22,119 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 9 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:50:22,119 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:50:22,119 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:50:22,128 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:22,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:22,166 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:50:22,299 WARN L180 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 18 DAG size of output: 10 [2018-11-18 15:50:22,305 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 9 proven. 8 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-11-18 15:50:22,333 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:50:22,333 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 5] total 8 [2018-11-18 15:50:22,333 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-18 15:50:22,334 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-18 15:50:22,334 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-18 15:50:22,334 INFO L87 Difference]: Start difference. First operand 493 states and 788 transitions. Second operand 8 states. [2018-11-18 15:50:22,840 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:22,841 INFO L93 Difference]: Finished difference Result 1031 states and 1639 transitions. [2018-11-18 15:50:22,849 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-18 15:50:22,849 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 41 [2018-11-18 15:50:22,849 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:22,851 INFO L225 Difference]: With dead ends: 1031 [2018-11-18 15:50:22,851 INFO L226 Difference]: Without dead ends: 580 [2018-11-18 15:50:22,852 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 41 SyntacticMatches, 1 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2018-11-18 15:50:22,855 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 580 states. [2018-11-18 15:50:22,867 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 580 to 544. [2018-11-18 15:50:22,868 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 544 states. [2018-11-18 15:50:22,870 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 544 states to 544 states and 867 transitions. [2018-11-18 15:50:22,870 INFO L78 Accepts]: Start accepts. Automaton has 544 states and 867 transitions. Word has length 41 [2018-11-18 15:50:22,870 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:22,870 INFO L480 AbstractCegarLoop]: Abstraction has 544 states and 867 transitions. [2018-11-18 15:50:22,870 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-18 15:50:22,870 INFO L276 IsEmpty]: Start isEmpty. Operand 544 states and 867 transitions. [2018-11-18 15:50:22,873 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-11-18 15:50:22,873 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:22,873 INFO L375 BasicCegarLoop]: trace histogram [4, 4, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:22,873 INFO L423 AbstractCegarLoop]: === Iteration 11 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:22,873 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:22,874 INFO L82 PathProgramCache]: Analyzing trace with hash -992845957, now seen corresponding path program 1 times [2018-11-18 15:50:22,874 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:22,874 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:22,874 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:22,874 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:22,875 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:22,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:23,062 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 9 proven. 10 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-11-18 15:50:23,062 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:50:23,062 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:50:23,087 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:23,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:23,112 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:50:23,128 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 9 proven. 10 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-11-18 15:50:23,144 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:50:23,144 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 4 [2018-11-18 15:50:23,144 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-18 15:50:23,145 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-18 15:50:23,145 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-18 15:50:23,145 INFO L87 Difference]: Start difference. First operand 544 states and 867 transitions. Second operand 4 states. [2018-11-18 15:50:23,300 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:23,300 INFO L93 Difference]: Finished difference Result 558 states and 879 transitions. [2018-11-18 15:50:23,301 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-18 15:50:23,301 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 42 [2018-11-18 15:50:23,301 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:23,303 INFO L225 Difference]: With dead ends: 558 [2018-11-18 15:50:23,303 INFO L226 Difference]: Without dead ends: 546 [2018-11-18 15:50:23,304 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 46 GetRequests, 41 SyntacticMatches, 3 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-18 15:50:23,304 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 546 states. [2018-11-18 15:50:23,316 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 546 to 544. [2018-11-18 15:50:23,316 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 544 states. [2018-11-18 15:50:23,318 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 544 states to 544 states and 841 transitions. [2018-11-18 15:50:23,318 INFO L78 Accepts]: Start accepts. Automaton has 544 states and 841 transitions. Word has length 42 [2018-11-18 15:50:23,319 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:23,319 INFO L480 AbstractCegarLoop]: Abstraction has 544 states and 841 transitions. [2018-11-18 15:50:23,319 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-18 15:50:23,319 INFO L276 IsEmpty]: Start isEmpty. Operand 544 states and 841 transitions. [2018-11-18 15:50:23,319 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-11-18 15:50:23,319 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:23,319 INFO L375 BasicCegarLoop]: trace histogram [4, 4, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:23,320 INFO L423 AbstractCegarLoop]: === Iteration 12 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:23,320 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:23,320 INFO L82 PathProgramCache]: Analyzing trace with hash -275920596, now seen corresponding path program 1 times [2018-11-18 15:50:23,320 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:23,320 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:23,323 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:23,323 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:23,323 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:23,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:23,538 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 9 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:50:23,539 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:50:23,539 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:50:23,550 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:23,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:23,582 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:50:23,598 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 9 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:50:23,614 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:50:23,614 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 5] total 6 [2018-11-18 15:50:23,615 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-18 15:50:23,615 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-18 15:50:23,615 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:50:23,615 INFO L87 Difference]: Start difference. First operand 544 states and 841 transitions. Second operand 6 states. [2018-11-18 15:50:23,918 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:23,918 INFO L93 Difference]: Finished difference Result 553 states and 848 transitions. [2018-11-18 15:50:23,919 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 15:50:23,919 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 44 [2018-11-18 15:50:23,919 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:23,925 INFO L225 Difference]: With dead ends: 553 [2018-11-18 15:50:23,925 INFO L226 Difference]: Without dead ends: 551 [2018-11-18 15:50:23,926 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 51 GetRequests, 43 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2018-11-18 15:50:23,926 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 551 states. [2018-11-18 15:50:23,940 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 551 to 545. [2018-11-18 15:50:23,940 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 545 states. [2018-11-18 15:50:23,942 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 545 states to 545 states and 842 transitions. [2018-11-18 15:50:23,942 INFO L78 Accepts]: Start accepts. Automaton has 545 states and 842 transitions. Word has length 44 [2018-11-18 15:50:23,943 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:23,944 INFO L480 AbstractCegarLoop]: Abstraction has 545 states and 842 transitions. [2018-11-18 15:50:23,944 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-18 15:50:23,944 INFO L276 IsEmpty]: Start isEmpty. Operand 545 states and 842 transitions. [2018-11-18 15:50:23,945 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-11-18 15:50:23,945 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:23,945 INFO L375 BasicCegarLoop]: trace histogram [4, 4, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:23,945 INFO L423 AbstractCegarLoop]: === Iteration 13 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:23,945 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:23,945 INFO L82 PathProgramCache]: Analyzing trace with hash 161633879, now seen corresponding path program 1 times [2018-11-18 15:50:23,946 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:23,946 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:23,946 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:23,946 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:23,946 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:23,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:24,030 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-18 15:50:24,030 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:50:24,031 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:50:24,031 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 15:50:24,031 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:50:24,031 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:50:24,031 INFO L87 Difference]: Start difference. First operand 545 states and 842 transitions. Second operand 3 states. [2018-11-18 15:50:24,246 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:24,246 INFO L93 Difference]: Finished difference Result 1053 states and 1621 transitions. [2018-11-18 15:50:24,249 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:50:24,249 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 45 [2018-11-18 15:50:24,250 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:24,251 INFO L225 Difference]: With dead ends: 1053 [2018-11-18 15:50:24,251 INFO L226 Difference]: Without dead ends: 557 [2018-11-18 15:50:24,252 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:50:24,253 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 557 states. [2018-11-18 15:50:24,266 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 557 to 555. [2018-11-18 15:50:24,266 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 555 states. [2018-11-18 15:50:24,267 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 555 states to 555 states and 835 transitions. [2018-11-18 15:50:24,268 INFO L78 Accepts]: Start accepts. Automaton has 555 states and 835 transitions. Word has length 45 [2018-11-18 15:50:24,268 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:24,268 INFO L480 AbstractCegarLoop]: Abstraction has 555 states and 835 transitions. [2018-11-18 15:50:24,268 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 15:50:24,268 INFO L276 IsEmpty]: Start isEmpty. Operand 555 states and 835 transitions. [2018-11-18 15:50:24,268 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2018-11-18 15:50:24,270 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:24,270 INFO L375 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:24,270 INFO L423 AbstractCegarLoop]: === Iteration 14 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:24,271 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:24,271 INFO L82 PathProgramCache]: Analyzing trace with hash 1614817955, now seen corresponding path program 1 times [2018-11-18 15:50:24,271 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:24,271 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:24,271 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:24,271 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:24,272 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:24,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:24,351 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 22 proven. 0 refuted. 0 times theorem prover too weak. 23 trivial. 0 not checked. [2018-11-18 15:50:24,351 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:50:24,351 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:50:24,351 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 15:50:24,351 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:50:24,352 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:50:24,352 INFO L87 Difference]: Start difference. First operand 555 states and 835 transitions. Second operand 3 states. [2018-11-18 15:50:24,503 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:24,504 INFO L93 Difference]: Finished difference Result 799 states and 1202 transitions. [2018-11-18 15:50:24,504 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:50:24,505 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 55 [2018-11-18 15:50:24,505 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:24,506 INFO L225 Difference]: With dead ends: 799 [2018-11-18 15:50:24,506 INFO L226 Difference]: Without dead ends: 313 [2018-11-18 15:50:24,507 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:50:24,507 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 313 states. [2018-11-18 15:50:24,516 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 313 to 311. [2018-11-18 15:50:24,517 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 311 states. [2018-11-18 15:50:24,518 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 311 states to 311 states and 454 transitions. [2018-11-18 15:50:24,518 INFO L78 Accepts]: Start accepts. Automaton has 311 states and 454 transitions. Word has length 55 [2018-11-18 15:50:24,518 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:24,518 INFO L480 AbstractCegarLoop]: Abstraction has 311 states and 454 transitions. [2018-11-18 15:50:24,519 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 15:50:24,519 INFO L276 IsEmpty]: Start isEmpty. Operand 311 states and 454 transitions. [2018-11-18 15:50:24,519 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-11-18 15:50:24,519 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:24,519 INFO L375 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:24,519 INFO L423 AbstractCegarLoop]: === Iteration 15 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:24,522 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:24,522 INFO L82 PathProgramCache]: Analyzing trace with hash 1860919614, now seen corresponding path program 1 times [2018-11-18 15:50:24,522 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:24,523 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:24,524 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:24,526 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:24,526 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:24,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:24,701 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 23 proven. 14 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-11-18 15:50:24,701 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:50:24,701 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:50:24,719 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:24,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:24,771 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:50:24,782 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 23 proven. 14 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-11-18 15:50:24,814 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:50:24,814 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 5 [2018-11-18 15:50:24,814 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 15:50:24,814 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:50:24,814 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:50:24,815 INFO L87 Difference]: Start difference. First operand 311 states and 454 transitions. Second operand 5 states. [2018-11-18 15:50:25,073 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:25,073 INFO L93 Difference]: Finished difference Result 660 states and 968 transitions. [2018-11-18 15:50:25,073 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 15:50:25,074 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 56 [2018-11-18 15:50:25,074 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:25,074 INFO L225 Difference]: With dead ends: 660 [2018-11-18 15:50:25,074 INFO L226 Difference]: Without dead ends: 418 [2018-11-18 15:50:25,075 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 61 GetRequests, 58 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:50:25,075 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 418 states. [2018-11-18 15:50:25,085 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 418 to 389. [2018-11-18 15:50:25,085 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 389 states. [2018-11-18 15:50:25,086 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 389 states to 389 states and 573 transitions. [2018-11-18 15:50:25,086 INFO L78 Accepts]: Start accepts. Automaton has 389 states and 573 transitions. Word has length 56 [2018-11-18 15:50:25,087 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:25,087 INFO L480 AbstractCegarLoop]: Abstraction has 389 states and 573 transitions. [2018-11-18 15:50:25,087 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 15:50:25,087 INFO L276 IsEmpty]: Start isEmpty. Operand 389 states and 573 transitions. [2018-11-18 15:50:25,087 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-11-18 15:50:25,087 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:25,087 INFO L375 BasicCegarLoop]: trace histogram [5, 5, 4, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:25,088 INFO L423 AbstractCegarLoop]: === Iteration 16 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:25,088 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:25,088 INFO L82 PathProgramCache]: Analyzing trace with hash 2119085052, now seen corresponding path program 1 times [2018-11-18 15:50:25,088 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:25,088 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:25,092 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:25,093 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:25,093 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:25,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:25,272 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 12 proven. 25 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-11-18 15:50:25,272 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:50:25,272 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2018-11-18 15:50:25,288 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:50:25,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:25,326 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:50:25,346 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 12 proven. 25 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-11-18 15:50:25,372 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:50:25,373 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 5 [2018-11-18 15:50:25,373 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 15:50:25,373 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:50:25,373 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:50:25,373 INFO L87 Difference]: Start difference. First operand 389 states and 573 transitions. Second operand 5 states. [2018-11-18 15:50:25,581 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:25,582 INFO L93 Difference]: Finished difference Result 436 states and 639 transitions. [2018-11-18 15:50:25,584 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 15:50:25,584 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 56 [2018-11-18 15:50:25,585 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:25,586 INFO L225 Difference]: With dead ends: 436 [2018-11-18 15:50:25,586 INFO L226 Difference]: Without dead ends: 430 [2018-11-18 15:50:25,586 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 61 GetRequests, 57 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:50:25,587 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430 states. [2018-11-18 15:50:25,596 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 427. [2018-11-18 15:50:25,597 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 427 states. [2018-11-18 15:50:25,598 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 427 states to 427 states and 627 transitions. [2018-11-18 15:50:25,598 INFO L78 Accepts]: Start accepts. Automaton has 427 states and 627 transitions. Word has length 56 [2018-11-18 15:50:25,598 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:25,598 INFO L480 AbstractCegarLoop]: Abstraction has 427 states and 627 transitions. [2018-11-18 15:50:25,598 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 15:50:25,598 INFO L276 IsEmpty]: Start isEmpty. Operand 427 states and 627 transitions. [2018-11-18 15:50:25,599 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2018-11-18 15:50:25,599 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:25,599 INFO L375 BasicCegarLoop]: trace histogram [5, 5, 4, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:25,599 INFO L423 AbstractCegarLoop]: === Iteration 17 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:25,600 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:25,600 INFO L82 PathProgramCache]: Analyzing trace with hash 807144158, now seen corresponding path program 1 times [2018-11-18 15:50:25,600 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:25,600 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:25,604 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:25,604 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:25,604 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:25,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:25,819 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 12 proven. 31 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:50:25,819 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:50:25,819 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:50:25,827 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:25,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:25,868 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:50:25,983 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 12 proven. 31 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:50:25,999 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:50:25,999 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 6] total 11 [2018-11-18 15:50:26,000 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-18 15:50:26,000 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-18 15:50:26,000 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=84, Unknown=0, NotChecked=0, Total=110 [2018-11-18 15:50:26,000 INFO L87 Difference]: Start difference. First operand 427 states and 627 transitions. Second operand 11 states. [2018-11-18 15:50:26,277 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:26,277 INFO L93 Difference]: Finished difference Result 430 states and 629 transitions. [2018-11-18 15:50:26,277 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-18 15:50:26,277 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 60 [2018-11-18 15:50:26,277 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:26,278 INFO L225 Difference]: With dead ends: 430 [2018-11-18 15:50:26,278 INFO L226 Difference]: Without dead ends: 428 [2018-11-18 15:50:26,279 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 68 GetRequests, 57 SyntacticMatches, 1 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=31, Invalid=101, Unknown=0, NotChecked=0, Total=132 [2018-11-18 15:50:26,279 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 428 states. [2018-11-18 15:50:26,287 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 428 to 427. [2018-11-18 15:50:26,288 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 427 states. [2018-11-18 15:50:26,289 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 427 states to 427 states and 626 transitions. [2018-11-18 15:50:26,289 INFO L78 Accepts]: Start accepts. Automaton has 427 states and 626 transitions. Word has length 60 [2018-11-18 15:50:26,289 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:26,289 INFO L480 AbstractCegarLoop]: Abstraction has 427 states and 626 transitions. [2018-11-18 15:50:26,289 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-18 15:50:26,289 INFO L276 IsEmpty]: Start isEmpty. Operand 427 states and 626 transitions. [2018-11-18 15:50:26,290 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2018-11-18 15:50:26,290 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:26,290 INFO L375 BasicCegarLoop]: trace histogram [6, 6, 5, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:26,290 INFO L423 AbstractCegarLoop]: === Iteration 18 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:26,290 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:26,290 INFO L82 PathProgramCache]: Analyzing trace with hash -743255307, now seen corresponding path program 1 times [2018-11-18 15:50:26,290 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:26,290 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:26,291 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:26,291 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:26,291 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:26,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:26,603 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 15 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:50:26,603 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:50:26,603 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:50:26,610 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:26,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:26,642 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:50:26,767 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 15 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:50:26,784 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:50:26,785 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 10 [2018-11-18 15:50:26,785 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-18 15:50:26,785 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-18 15:50:26,785 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=69, Unknown=0, NotChecked=0, Total=90 [2018-11-18 15:50:26,785 INFO L87 Difference]: Start difference. First operand 427 states and 626 transitions. Second operand 10 states. [2018-11-18 15:50:26,949 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:26,949 INFO L93 Difference]: Finished difference Result 431 states and 630 transitions. [2018-11-18 15:50:26,953 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-18 15:50:26,953 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 67 [2018-11-18 15:50:26,953 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:26,954 INFO L225 Difference]: With dead ends: 431 [2018-11-18 15:50:26,955 INFO L226 Difference]: Without dead ends: 429 [2018-11-18 15:50:26,955 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 76 GetRequests, 62 SyntacticMatches, 5 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=25, Invalid=85, Unknown=0, NotChecked=0, Total=110 [2018-11-18 15:50:26,955 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 429 states. [2018-11-18 15:50:26,971 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 429 to 428. [2018-11-18 15:50:26,972 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 428 states. [2018-11-18 15:50:26,973 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 428 states to 428 states and 627 transitions. [2018-11-18 15:50:26,974 INFO L78 Accepts]: Start accepts. Automaton has 428 states and 627 transitions. Word has length 67 [2018-11-18 15:50:26,974 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:26,974 INFO L480 AbstractCegarLoop]: Abstraction has 428 states and 627 transitions. [2018-11-18 15:50:26,974 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-18 15:50:26,974 INFO L276 IsEmpty]: Start isEmpty. Operand 428 states and 627 transitions. [2018-11-18 15:50:26,975 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-11-18 15:50:26,975 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:26,975 INFO L375 BasicCegarLoop]: trace histogram [7, 6, 6, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:26,975 INFO L423 AbstractCegarLoop]: === Iteration 19 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:26,975 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:26,975 INFO L82 PathProgramCache]: Analyzing trace with hash -1746386041, now seen corresponding path program 1 times [2018-11-18 15:50:26,975 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:26,975 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:26,976 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:26,976 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:26,976 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:26,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:27,132 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 38 proven. 50 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-18 15:50:27,132 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:50:27,133 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:50:27,145 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:27,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:27,195 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:50:27,203 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 38 proven. 50 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-18 15:50:27,229 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:50:27,229 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 6 [2018-11-18 15:50:27,230 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-18 15:50:27,230 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-18 15:50:27,230 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:50:27,230 INFO L87 Difference]: Start difference. First operand 428 states and 627 transitions. Second operand 6 states. [2018-11-18 15:50:27,396 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:27,397 INFO L93 Difference]: Finished difference Result 865 states and 1269 transitions. [2018-11-18 15:50:27,397 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 15:50:27,397 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 77 [2018-11-18 15:50:27,398 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:27,399 INFO L225 Difference]: With dead ends: 865 [2018-11-18 15:50:27,399 INFO L226 Difference]: Without dead ends: 545 [2018-11-18 15:50:27,400 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 84 GetRequests, 80 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-11-18 15:50:27,400 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 545 states. [2018-11-18 15:50:27,410 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 545 to 506. [2018-11-18 15:50:27,411 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 506 states. [2018-11-18 15:50:27,412 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 506 states to 506 states and 746 transitions. [2018-11-18 15:50:27,412 INFO L78 Accepts]: Start accepts. Automaton has 506 states and 746 transitions. Word has length 77 [2018-11-18 15:50:27,412 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:27,412 INFO L480 AbstractCegarLoop]: Abstraction has 506 states and 746 transitions. [2018-11-18 15:50:27,412 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-18 15:50:27,412 INFO L276 IsEmpty]: Start isEmpty. Operand 506 states and 746 transitions. [2018-11-18 15:50:27,415 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-11-18 15:50:27,415 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:27,415 INFO L375 BasicCegarLoop]: trace histogram [7, 7, 6, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:27,416 INFO L423 AbstractCegarLoop]: === Iteration 20 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:27,416 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:27,416 INFO L82 PathProgramCache]: Analyzing trace with hash -2139413051, now seen corresponding path program 1 times [2018-11-18 15:50:27,416 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:27,416 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:27,417 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:27,417 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:27,417 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:27,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:27,724 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 18 proven. 80 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:50:27,724 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:50:27,725 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:50:27,732 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:27,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:27,775 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:50:27,849 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 18 proven. 70 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-18 15:50:27,865 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:50:27,865 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 7] total 13 [2018-11-18 15:50:27,866 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-18 15:50:27,866 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-18 15:50:27,866 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=126, Unknown=0, NotChecked=0, Total=156 [2018-11-18 15:50:27,866 INFO L87 Difference]: Start difference. First operand 506 states and 746 transitions. Second operand 13 states. [2018-11-18 15:50:28,036 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:28,036 INFO L93 Difference]: Finished difference Result 529 states and 778 transitions. [2018-11-18 15:50:28,037 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-18 15:50:28,037 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 77 [2018-11-18 15:50:28,037 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:28,038 INFO L225 Difference]: With dead ends: 529 [2018-11-18 15:50:28,038 INFO L226 Difference]: Without dead ends: 525 [2018-11-18 15:50:28,039 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 86 GetRequests, 73 SyntacticMatches, 1 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=35, Invalid=147, Unknown=0, NotChecked=0, Total=182 [2018-11-18 15:50:28,039 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 525 states. [2018-11-18 15:50:28,050 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 525 to 525. [2018-11-18 15:50:28,050 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 525 states. [2018-11-18 15:50:28,051 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 525 states to 525 states and 772 transitions. [2018-11-18 15:50:28,051 INFO L78 Accepts]: Start accepts. Automaton has 525 states and 772 transitions. Word has length 77 [2018-11-18 15:50:28,051 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:28,051 INFO L480 AbstractCegarLoop]: Abstraction has 525 states and 772 transitions. [2018-11-18 15:50:28,051 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-18 15:50:28,051 INFO L276 IsEmpty]: Start isEmpty. Operand 525 states and 772 transitions. [2018-11-18 15:50:28,052 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-11-18 15:50:28,052 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:28,052 INFO L375 BasicCegarLoop]: trace histogram [8, 8, 7, 5, 5, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:28,052 INFO L423 AbstractCegarLoop]: === Iteration 21 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:28,056 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:28,056 INFO L82 PathProgramCache]: Analyzing trace with hash -1314627048, now seen corresponding path program 1 times [2018-11-18 15:50:28,056 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:28,056 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:28,056 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:28,057 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:28,057 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:28,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:28,623 WARN L180 SmtUtils]: Spent 198.00 ms on a formula simplification. DAG size of input: 13 DAG size of output: 10 [2018-11-18 15:50:28,676 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 26 proven. 99 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-11-18 15:50:28,676 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:50:28,676 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:50:28,682 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:28,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:28,738 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:50:28,841 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 21 proven. 99 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-18 15:50:28,863 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:50:28,863 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7] total 9 [2018-11-18 15:50:28,863 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-18 15:50:28,863 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-18 15:50:28,863 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2018-11-18 15:50:28,863 INFO L87 Difference]: Start difference. First operand 525 states and 772 transitions. Second operand 9 states. [2018-11-18 15:50:29,076 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:29,076 INFO L93 Difference]: Finished difference Result 555 states and 810 transitions. [2018-11-18 15:50:29,077 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-18 15:50:29,077 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 87 [2018-11-18 15:50:29,077 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:29,078 INFO L225 Difference]: With dead ends: 555 [2018-11-18 15:50:29,078 INFO L226 Difference]: Without dead ends: 551 [2018-11-18 15:50:29,079 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 99 GetRequests, 89 SyntacticMatches, 2 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2018-11-18 15:50:29,079 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 551 states. [2018-11-18 15:50:29,090 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 551 to 544. [2018-11-18 15:50:29,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 544 states. [2018-11-18 15:50:29,091 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 544 states to 544 states and 798 transitions. [2018-11-18 15:50:29,091 INFO L78 Accepts]: Start accepts. Automaton has 544 states and 798 transitions. Word has length 87 [2018-11-18 15:50:29,092 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:29,092 INFO L480 AbstractCegarLoop]: Abstraction has 544 states and 798 transitions. [2018-11-18 15:50:29,092 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-18 15:50:29,092 INFO L276 IsEmpty]: Start isEmpty. Operand 544 states and 798 transitions. [2018-11-18 15:50:29,092 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-11-18 15:50:29,095 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:29,095 INFO L375 BasicCegarLoop]: trace histogram [8, 8, 7, 5, 5, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:29,095 INFO L423 AbstractCegarLoop]: === Iteration 22 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:29,095 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:29,095 INFO L82 PathProgramCache]: Analyzing trace with hash 233904989, now seen corresponding path program 1 times [2018-11-18 15:50:29,095 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:29,095 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:29,096 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:29,096 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:29,096 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:29,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:29,412 INFO L134 CoverageAnalysis]: Checked inductivity of 141 backedges. 21 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:50:29,413 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:50:29,413 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:50:29,432 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:29,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:29,492 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:50:29,580 INFO L134 CoverageAnalysis]: Checked inductivity of 141 backedges. 21 proven. 110 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-18 15:50:29,596 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:50:29,596 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 8] total 14 [2018-11-18 15:50:29,597 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-11-18 15:50:29,597 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-11-18 15:50:29,597 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=150, Unknown=0, NotChecked=0, Total=182 [2018-11-18 15:50:29,597 INFO L87 Difference]: Start difference. First operand 544 states and 798 transitions. Second operand 14 states. [2018-11-18 15:50:29,857 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:29,857 INFO L93 Difference]: Finished difference Result 549 states and 803 transitions. [2018-11-18 15:50:29,858 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-18 15:50:29,858 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 90 [2018-11-18 15:50:29,858 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:29,859 INFO L225 Difference]: With dead ends: 549 [2018-11-18 15:50:29,859 INFO L226 Difference]: Without dead ends: 547 [2018-11-18 15:50:29,860 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 105 GetRequests, 85 SyntacticMatches, 5 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=46, Invalid=226, Unknown=0, NotChecked=0, Total=272 [2018-11-18 15:50:29,860 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 547 states. [2018-11-18 15:50:29,870 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 547 to 545. [2018-11-18 15:50:29,870 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 545 states. [2018-11-18 15:50:29,871 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 545 states to 545 states and 799 transitions. [2018-11-18 15:50:29,871 INFO L78 Accepts]: Start accepts. Automaton has 545 states and 799 transitions. Word has length 90 [2018-11-18 15:50:29,871 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:29,871 INFO L480 AbstractCegarLoop]: Abstraction has 545 states and 799 transitions. [2018-11-18 15:50:29,872 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-11-18 15:50:29,872 INFO L276 IsEmpty]: Start isEmpty. Operand 545 states and 799 transitions. [2018-11-18 15:50:29,872 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-11-18 15:50:29,875 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:29,875 INFO L375 BasicCegarLoop]: trace histogram [9, 8, 8, 6, 6, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:29,875 INFO L423 AbstractCegarLoop]: === Iteration 23 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:29,876 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:29,876 INFO L82 PathProgramCache]: Analyzing trace with hash -1342705169, now seen corresponding path program 1 times [2018-11-18 15:50:29,876 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:29,876 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:29,876 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:29,877 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:29,877 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:29,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:30,299 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 54 proven. 118 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-18 15:50:30,299 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:50:30,299 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:50:30,311 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:30,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:30,360 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:50:30,371 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 54 proven. 118 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-18 15:50:30,387 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:50:30,387 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 7 [2018-11-18 15:50:30,387 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-18 15:50:30,388 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-18 15:50:30,388 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2018-11-18 15:50:30,388 INFO L87 Difference]: Start difference. First operand 545 states and 799 transitions. Second operand 7 states. [2018-11-18 15:50:30,506 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:30,506 INFO L93 Difference]: Finished difference Result 1070 states and 1569 transitions. [2018-11-18 15:50:30,506 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-18 15:50:30,506 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 102 [2018-11-18 15:50:30,506 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:30,507 INFO L225 Difference]: With dead ends: 1070 [2018-11-18 15:50:30,508 INFO L226 Difference]: Without dead ends: 672 [2018-11-18 15:50:30,508 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 111 GetRequests, 106 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2018-11-18 15:50:30,508 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 672 states. [2018-11-18 15:50:30,520 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 672 to 623. [2018-11-18 15:50:30,520 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 623 states. [2018-11-18 15:50:30,521 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 623 states to 623 states and 918 transitions. [2018-11-18 15:50:30,521 INFO L78 Accepts]: Start accepts. Automaton has 623 states and 918 transitions. Word has length 102 [2018-11-18 15:50:30,522 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:30,522 INFO L480 AbstractCegarLoop]: Abstraction has 623 states and 918 transitions. [2018-11-18 15:50:30,522 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-18 15:50:30,522 INFO L276 IsEmpty]: Start isEmpty. Operand 623 states and 918 transitions. [2018-11-18 15:50:30,523 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-11-18 15:50:30,523 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:30,523 INFO L375 BasicCegarLoop]: trace histogram [9, 9, 8, 6, 6, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:30,523 INFO L423 AbstractCegarLoop]: === Iteration 24 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:30,523 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:30,523 INFO L82 PathProgramCache]: Analyzing trace with hash -1084539731, now seen corresponding path program 1 times [2018-11-18 15:50:30,523 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:30,524 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:30,524 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:30,524 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:30,524 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:30,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:30,698 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 24 proven. 148 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-18 15:50:30,698 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:50:30,698 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:50:30,706 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:30,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:30,753 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:50:30,792 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 24 proven. 148 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-18 15:50:30,808 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:50:30,808 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 7 [2018-11-18 15:50:30,808 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-18 15:50:30,809 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-18 15:50:30,809 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-11-18 15:50:30,809 INFO L87 Difference]: Start difference. First operand 623 states and 918 transitions. Second operand 7 states. [2018-11-18 15:50:30,889 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:30,889 INFO L93 Difference]: Finished difference Result 670 states and 984 transitions. [2018-11-18 15:50:30,889 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-18 15:50:30,890 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 102 [2018-11-18 15:50:30,890 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:30,891 INFO L225 Difference]: With dead ends: 670 [2018-11-18 15:50:30,891 INFO L226 Difference]: Without dead ends: 664 [2018-11-18 15:50:30,891 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 111 GetRequests, 104 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-11-18 15:50:30,892 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 664 states. [2018-11-18 15:50:30,899 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 664 to 661. [2018-11-18 15:50:30,900 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 661 states. [2018-11-18 15:50:30,900 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 661 states to 661 states and 972 transitions. [2018-11-18 15:50:30,900 INFO L78 Accepts]: Start accepts. Automaton has 661 states and 972 transitions. Word has length 102 [2018-11-18 15:50:30,901 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:30,901 INFO L480 AbstractCegarLoop]: Abstraction has 661 states and 972 transitions. [2018-11-18 15:50:30,901 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-18 15:50:30,901 INFO L276 IsEmpty]: Start isEmpty. Operand 661 states and 972 transitions. [2018-11-18 15:50:30,901 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 107 [2018-11-18 15:50:30,901 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:30,902 INFO L375 BasicCegarLoop]: trace histogram [9, 9, 8, 6, 6, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:30,902 INFO L423 AbstractCegarLoop]: === Iteration 25 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:30,902 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:30,902 INFO L82 PathProgramCache]: Analyzing trace with hash 35576591, now seen corresponding path program 1 times [2018-11-18 15:50:30,902 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:30,902 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:30,903 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:30,903 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:30,903 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:30,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:31,133 WARN L180 SmtUtils]: Spent 107.00 ms on a formula simplification that was a NOOP. DAG size: 8 [2018-11-18 15:50:31,413 INFO L134 CoverageAnalysis]: Checked inductivity of 194 backedges. 24 proven. 170 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:50:31,413 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:50:31,413 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:50:31,422 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:31,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:31,468 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:50:31,568 INFO L134 CoverageAnalysis]: Checked inductivity of 194 backedges. 24 proven. 160 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-18 15:50:31,584 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:50:31,584 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 9] total 15 [2018-11-18 15:50:31,584 INFO L459 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-11-18 15:50:31,585 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-11-18 15:50:31,585 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=176, Unknown=0, NotChecked=0, Total=210 [2018-11-18 15:50:31,585 INFO L87 Difference]: Start difference. First operand 661 states and 972 transitions. Second operand 15 states. [2018-11-18 15:50:31,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:31,849 INFO L93 Difference]: Finished difference Result 664 states and 974 transitions. [2018-11-18 15:50:31,850 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-18 15:50:31,850 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 106 [2018-11-18 15:50:31,850 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:31,852 INFO L225 Difference]: With dead ends: 664 [2018-11-18 15:50:31,852 INFO L226 Difference]: Without dead ends: 662 [2018-11-18 15:50:31,852 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 119 GetRequests, 101 SyntacticMatches, 3 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=44, Invalid=228, Unknown=0, NotChecked=0, Total=272 [2018-11-18 15:50:31,853 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 662 states. [2018-11-18 15:50:31,861 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 662 to 661. [2018-11-18 15:50:31,862 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 661 states. [2018-11-18 15:50:31,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 661 states to 661 states and 971 transitions. [2018-11-18 15:50:31,863 INFO L78 Accepts]: Start accepts. Automaton has 661 states and 971 transitions. Word has length 106 [2018-11-18 15:50:31,863 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:31,863 INFO L480 AbstractCegarLoop]: Abstraction has 661 states and 971 transitions. [2018-11-18 15:50:31,863 INFO L481 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-11-18 15:50:31,866 INFO L276 IsEmpty]: Start isEmpty. Operand 661 states and 971 transitions. [2018-11-18 15:50:31,866 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-11-18 15:50:31,866 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:31,867 INFO L375 BasicCegarLoop]: trace histogram [10, 10, 9, 6, 6, 4, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:31,867 INFO L423 AbstractCegarLoop]: === Iteration 26 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:31,867 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:31,867 INFO L82 PathProgramCache]: Analyzing trace with hash -234907228, now seen corresponding path program 2 times [2018-11-18 15:50:31,867 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:31,867 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:31,868 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:31,868 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:31,868 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:31,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:32,113 WARN L180 SmtUtils]: Spent 100.00 ms on a formula simplification that was a NOOP. DAG size: 8 [2018-11-18 15:50:32,289 WARN L180 SmtUtils]: Spent 120.00 ms on a formula simplification that was a NOOP. DAG size: 9 [2018-11-18 15:50:32,527 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 27 proven. 208 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:50:32,527 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:50:32,527 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:50:32,536 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-18 15:50:32,590 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 15:50:32,590 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:50:32,593 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:50:32,789 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 27 proven. 198 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-18 15:50:32,813 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:50:32,814 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 11] total 18 [2018-11-18 15:50:32,814 INFO L459 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-11-18 15:50:32,814 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-11-18 15:50:32,814 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=43, Invalid=263, Unknown=0, NotChecked=0, Total=306 [2018-11-18 15:50:32,814 INFO L87 Difference]: Start difference. First operand 661 states and 971 transitions. Second operand 18 states. [2018-11-18 15:50:33,236 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:33,236 INFO L93 Difference]: Finished difference Result 698 states and 1007 transitions. [2018-11-18 15:50:33,236 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-11-18 15:50:33,236 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 113 [2018-11-18 15:50:33,236 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:33,238 INFO L225 Difference]: With dead ends: 698 [2018-11-18 15:50:33,238 INFO L226 Difference]: Without dead ends: 696 [2018-11-18 15:50:33,238 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 134 GetRequests, 105 SyntacticMatches, 4 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 97 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=85, Invalid=617, Unknown=0, NotChecked=0, Total=702 [2018-11-18 15:50:33,238 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 696 states. [2018-11-18 15:50:33,251 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 696 to 662. [2018-11-18 15:50:33,251 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 662 states. [2018-11-18 15:50:33,252 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 662 states to 662 states and 972 transitions. [2018-11-18 15:50:33,253 INFO L78 Accepts]: Start accepts. Automaton has 662 states and 972 transitions. Word has length 113 [2018-11-18 15:50:33,253 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:33,253 INFO L480 AbstractCegarLoop]: Abstraction has 662 states and 972 transitions. [2018-11-18 15:50:33,253 INFO L481 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-11-18 15:50:33,253 INFO L276 IsEmpty]: Start isEmpty. Operand 662 states and 972 transitions. [2018-11-18 15:50:33,253 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 124 [2018-11-18 15:50:33,254 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:33,254 INFO L375 BasicCegarLoop]: trace histogram [11, 10, 10, 7, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:33,254 INFO L423 AbstractCegarLoop]: === Iteration 27 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:33,254 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:33,254 INFO L82 PathProgramCache]: Analyzing trace with hash -238306442, now seen corresponding path program 2 times [2018-11-18 15:50:33,254 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:33,254 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:33,255 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:33,255 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:50:33,255 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:33,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:33,746 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 68 proven. 206 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-11-18 15:50:33,747 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:50:33,747 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:50:33,763 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-18 15:50:33,861 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 15:50:33,861 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:50:33,865 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:50:33,880 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 68 proven. 206 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-11-18 15:50:33,905 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:50:33,905 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 8 [2018-11-18 15:50:33,906 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-18 15:50:33,906 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-18 15:50:33,906 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-11-18 15:50:33,906 INFO L87 Difference]: Start difference. First operand 662 states and 972 transitions. Second operand 8 states. [2018-11-18 15:50:34,067 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:34,068 INFO L93 Difference]: Finished difference Result 1275 states and 1870 transitions. [2018-11-18 15:50:34,068 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-18 15:50:34,069 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 123 [2018-11-18 15:50:34,069 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:34,071 INFO L225 Difference]: With dead ends: 1275 [2018-11-18 15:50:34,071 INFO L226 Difference]: Without dead ends: 799 [2018-11-18 15:50:34,072 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 134 GetRequests, 128 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-11-18 15:50:34,072 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 799 states. [2018-11-18 15:50:34,086 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 799 to 740. [2018-11-18 15:50:34,086 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 740 states. [2018-11-18 15:50:34,088 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 740 states to 740 states and 1091 transitions. [2018-11-18 15:50:34,088 INFO L78 Accepts]: Start accepts. Automaton has 740 states and 1091 transitions. Word has length 123 [2018-11-18 15:50:34,088 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:34,088 INFO L480 AbstractCegarLoop]: Abstraction has 740 states and 1091 transitions. [2018-11-18 15:50:34,088 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-18 15:50:34,088 INFO L276 IsEmpty]: Start isEmpty. Operand 740 states and 1091 transitions. [2018-11-18 15:50:34,089 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 124 [2018-11-18 15:50:34,089 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:34,089 INFO L375 BasicCegarLoop]: trace histogram [11, 11, 10, 7, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:34,089 INFO L423 AbstractCegarLoop]: === Iteration 28 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:34,089 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:34,089 INFO L82 PathProgramCache]: Analyzing trace with hash -631333452, now seen corresponding path program 2 times [2018-11-18 15:50:34,090 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:34,090 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:34,090 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:34,090 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:50:34,090 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:34,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:34,305 WARN L180 SmtUtils]: Spent 104.00 ms on a formula simplification that was a NOOP. DAG size: 5 [2018-11-18 15:50:34,604 WARN L180 SmtUtils]: Spent 109.00 ms on a formula simplification. DAG size of input: 28 DAG size of output: 9 [2018-11-18 15:50:34,745 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 35 proven. 254 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-11-18 15:50:34,745 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:50:34,746 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:50:34,752 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-18 15:50:34,804 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 15:50:34,804 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:50:34,808 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:50:34,905 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 30 proven. 244 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-11-18 15:50:34,930 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:50:34,930 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 9] total 17 [2018-11-18 15:50:34,930 INFO L459 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-11-18 15:50:34,930 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-11-18 15:50:34,931 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=41, Invalid=231, Unknown=0, NotChecked=0, Total=272 [2018-11-18 15:50:34,931 INFO L87 Difference]: Start difference. First operand 740 states and 1091 transitions. Second operand 17 states. [2018-11-18 15:50:35,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:35,338 INFO L93 Difference]: Finished difference Result 801 states and 1160 transitions. [2018-11-18 15:50:35,339 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-11-18 15:50:35,339 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 123 [2018-11-18 15:50:35,340 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:35,341 INFO L225 Difference]: With dead ends: 801 [2018-11-18 15:50:35,341 INFO L226 Difference]: Without dead ends: 797 [2018-11-18 15:50:35,342 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 147 GetRequests, 122 SyntacticMatches, 2 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 81 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=80, Invalid=520, Unknown=0, NotChecked=0, Total=600 [2018-11-18 15:50:35,342 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 797 states. [2018-11-18 15:50:35,355 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 797 to 759. [2018-11-18 15:50:35,355 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 759 states. [2018-11-18 15:50:35,356 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 759 states to 759 states and 1117 transitions. [2018-11-18 15:50:35,356 INFO L78 Accepts]: Start accepts. Automaton has 759 states and 1117 transitions. Word has length 123 [2018-11-18 15:50:35,356 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:35,356 INFO L480 AbstractCegarLoop]: Abstraction has 759 states and 1117 transitions. [2018-11-18 15:50:35,356 INFO L481 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-11-18 15:50:35,356 INFO L276 IsEmpty]: Start isEmpty. Operand 759 states and 1117 transitions. [2018-11-18 15:50:35,357 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 134 [2018-11-18 15:50:35,357 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:35,357 INFO L375 BasicCegarLoop]: trace histogram [12, 12, 11, 8, 8, 5, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:35,357 INFO L423 AbstractCegarLoop]: === Iteration 29 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:35,358 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:35,358 INFO L82 PathProgramCache]: Analyzing trace with hash -1671300281, now seen corresponding path program 2 times [2018-11-18 15:50:35,358 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:35,358 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:35,358 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:35,358 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:50:35,358 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:35,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:36,273 WARN L180 SmtUtils]: Spent 232.00 ms on a formula simplification. DAG size of input: 33 DAG size of output: 19 [2018-11-18 15:50:36,314 INFO L134 CoverageAnalysis]: Checked inductivity of 357 backedges. 33 proven. 298 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2018-11-18 15:50:36,315 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:50:36,315 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:50:36,327 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-18 15:50:36,401 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 15:50:36,401 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:50:36,404 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:50:36,559 INFO L134 CoverageAnalysis]: Checked inductivity of 357 backedges. 33 proven. 298 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2018-11-18 15:50:36,575 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:50:36,575 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 10 [2018-11-18 15:50:36,575 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-18 15:50:36,575 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-18 15:50:36,575 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=70, Unknown=0, NotChecked=0, Total=90 [2018-11-18 15:50:36,576 INFO L87 Difference]: Start difference. First operand 759 states and 1117 transitions. Second operand 10 states. [2018-11-18 15:50:37,557 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:37,558 INFO L93 Difference]: Finished difference Result 788 states and 1154 transitions. [2018-11-18 15:50:37,559 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-18 15:50:37,559 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 133 [2018-11-18 15:50:37,559 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:37,561 INFO L225 Difference]: With dead ends: 788 [2018-11-18 15:50:37,561 INFO L226 Difference]: Without dead ends: 784 [2018-11-18 15:50:37,562 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 148 GetRequests, 137 SyntacticMatches, 3 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=20, Invalid=70, Unknown=0, NotChecked=0, Total=90 [2018-11-18 15:50:37,562 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 784 states. [2018-11-18 15:50:37,581 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 784 to 778. [2018-11-18 15:50:37,581 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 778 states. [2018-11-18 15:50:37,582 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 778 states to 778 states and 1143 transitions. [2018-11-18 15:50:37,583 INFO L78 Accepts]: Start accepts. Automaton has 778 states and 1143 transitions. Word has length 133 [2018-11-18 15:50:37,583 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:37,583 INFO L480 AbstractCegarLoop]: Abstraction has 778 states and 1143 transitions. [2018-11-18 15:50:37,583 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-18 15:50:37,583 INFO L276 IsEmpty]: Start isEmpty. Operand 778 states and 1143 transitions. [2018-11-18 15:50:37,584 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 137 [2018-11-18 15:50:37,584 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:37,584 INFO L375 BasicCegarLoop]: trace histogram [12, 12, 11, 8, 8, 5, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:37,584 INFO L423 AbstractCegarLoop]: === Iteration 30 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:37,584 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:37,584 INFO L82 PathProgramCache]: Analyzing trace with hash 330710990, now seen corresponding path program 2 times [2018-11-18 15:50:37,584 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:37,589 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:37,590 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:37,590 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:50:37,590 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:37,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:37,827 WARN L180 SmtUtils]: Spent 102.00 ms on a formula simplification that was a NOOP. DAG size: 8 [2018-11-18 15:50:38,125 WARN L180 SmtUtils]: Spent 122.00 ms on a formula simplification. DAG size of input: 12 DAG size of output: 9 [2018-11-18 15:50:38,386 INFO L134 CoverageAnalysis]: Checked inductivity of 367 backedges. 33 proven. 334 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:50:38,386 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:50:38,386 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:50:38,392 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-18 15:50:38,455 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 15:50:38,456 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:50:38,460 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:50:38,581 INFO L134 CoverageAnalysis]: Checked inductivity of 367 backedges. 33 proven. 314 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-11-18 15:50:38,599 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:50:38,599 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 10] total 20 [2018-11-18 15:50:38,600 INFO L459 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-11-18 15:50:38,600 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-11-18 15:50:38,600 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=49, Invalid=331, Unknown=0, NotChecked=0, Total=380 [2018-11-18 15:50:38,600 INFO L87 Difference]: Start difference. First operand 778 states and 1143 transitions. Second operand 20 states. [2018-11-18 15:50:39,142 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:39,142 INFO L93 Difference]: Finished difference Result 821 states and 1185 transitions. [2018-11-18 15:50:39,142 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-11-18 15:50:39,143 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 136 [2018-11-18 15:50:39,143 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:39,144 INFO L225 Difference]: With dead ends: 821 [2018-11-18 15:50:39,144 INFO L226 Difference]: Without dead ends: 819 [2018-11-18 15:50:39,145 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 162 GetRequests, 129 SyntacticMatches, 4 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 105 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=104, Invalid=826, Unknown=0, NotChecked=0, Total=930 [2018-11-18 15:50:39,145 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 819 states. [2018-11-18 15:50:39,160 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 819 to 779. [2018-11-18 15:50:39,160 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 779 states. [2018-11-18 15:50:39,161 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 779 states to 779 states and 1144 transitions. [2018-11-18 15:50:39,161 INFO L78 Accepts]: Start accepts. Automaton has 779 states and 1144 transitions. Word has length 136 [2018-11-18 15:50:39,161 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:39,161 INFO L480 AbstractCegarLoop]: Abstraction has 779 states and 1144 transitions. [2018-11-18 15:50:39,161 INFO L481 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-11-18 15:50:39,161 INFO L276 IsEmpty]: Start isEmpty. Operand 779 states and 1144 transitions. [2018-11-18 15:50:39,162 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 149 [2018-11-18 15:50:39,162 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:39,162 INFO L375 BasicCegarLoop]: trace histogram [13, 12, 12, 9, 9, 6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:39,162 INFO L423 AbstractCegarLoop]: === Iteration 31 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:39,162 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:39,162 INFO L82 PathProgramCache]: Analyzing trace with hash -352520992, now seen corresponding path program 2 times [2018-11-18 15:50:39,162 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:39,162 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:39,163 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:39,163 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:50:39,163 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:39,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:39,610 INFO L134 CoverageAnalysis]: Checked inductivity of 441 backedges. 85 proven. 330 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2018-11-18 15:50:39,610 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:50:39,610 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:50:39,617 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-18 15:50:39,637 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-11-18 15:50:39,637 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:50:39,639 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:50:39,650 INFO L134 CoverageAnalysis]: Checked inductivity of 441 backedges. 50 proven. 0 refuted. 0 times theorem prover too weak. 391 trivial. 0 not checked. [2018-11-18 15:50:39,665 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-18 15:50:39,665 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [9] total 10 [2018-11-18 15:50:39,665 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-18 15:50:39,666 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-18 15:50:39,666 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-11-18 15:50:39,666 INFO L87 Difference]: Start difference. First operand 779 states and 1144 transitions. Second operand 10 states. [2018-11-18 15:50:40,063 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:40,063 INFO L93 Difference]: Finished difference Result 1568 states and 2302 transitions. [2018-11-18 15:50:40,064 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-18 15:50:40,064 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 148 [2018-11-18 15:50:40,064 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:40,066 INFO L225 Difference]: With dead ends: 1568 [2018-11-18 15:50:40,066 INFO L226 Difference]: Without dead ends: 1011 [2018-11-18 15:50:40,067 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 161 GetRequests, 153 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-11-18 15:50:40,068 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1011 states. [2018-11-18 15:50:40,083 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1011 to 935. [2018-11-18 15:50:40,083 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 935 states. [2018-11-18 15:50:40,084 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 935 states to 935 states and 1379 transitions. [2018-11-18 15:50:40,085 INFO L78 Accepts]: Start accepts. Automaton has 935 states and 1379 transitions. Word has length 148 [2018-11-18 15:50:40,085 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:40,085 INFO L480 AbstractCegarLoop]: Abstraction has 935 states and 1379 transitions. [2018-11-18 15:50:40,085 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-18 15:50:40,085 INFO L276 IsEmpty]: Start isEmpty. Operand 935 states and 1379 transitions. [2018-11-18 15:50:40,086 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 149 [2018-11-18 15:50:40,086 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:40,086 INFO L375 BasicCegarLoop]: trace histogram [13, 13, 12, 9, 9, 6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:40,086 INFO L423 AbstractCegarLoop]: === Iteration 32 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:40,087 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:40,087 INFO L82 PathProgramCache]: Analyzing trace with hash -94355554, now seen corresponding path program 2 times [2018-11-18 15:50:40,087 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:40,087 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:40,087 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:40,088 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:50:40,088 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:40,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:40,359 INFO L134 CoverageAnalysis]: Checked inductivity of 441 backedges. 36 proven. 379 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2018-11-18 15:50:40,359 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:50:40,359 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:50:40,366 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-18 15:50:40,433 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 15:50:40,433 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:50:40,437 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:50:40,482 INFO L134 CoverageAnalysis]: Checked inductivity of 441 backedges. 36 proven. 379 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2018-11-18 15:50:40,498 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:50:40,499 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 9 [2018-11-18 15:50:40,499 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-18 15:50:40,499 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-18 15:50:40,499 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2018-11-18 15:50:40,499 INFO L87 Difference]: Start difference. First operand 935 states and 1379 transitions. Second operand 9 states. [2018-11-18 15:50:40,623 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:40,623 INFO L93 Difference]: Finished difference Result 982 states and 1445 transitions. [2018-11-18 15:50:40,624 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-18 15:50:40,624 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 148 [2018-11-18 15:50:40,625 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:40,626 INFO L225 Difference]: With dead ends: 982 [2018-11-18 15:50:40,626 INFO L226 Difference]: Without dead ends: 976 [2018-11-18 15:50:40,627 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 161 GetRequests, 153 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2018-11-18 15:50:40,627 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 976 states. [2018-11-18 15:50:40,643 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 976 to 973. [2018-11-18 15:50:40,643 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 973 states. [2018-11-18 15:50:40,644 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 973 states to 973 states and 1433 transitions. [2018-11-18 15:50:40,644 INFO L78 Accepts]: Start accepts. Automaton has 973 states and 1433 transitions. Word has length 148 [2018-11-18 15:50:40,644 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:40,645 INFO L480 AbstractCegarLoop]: Abstraction has 973 states and 1433 transitions. [2018-11-18 15:50:40,645 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-18 15:50:40,645 INFO L276 IsEmpty]: Start isEmpty. Operand 973 states and 1433 transitions. [2018-11-18 15:50:40,645 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 153 [2018-11-18 15:50:40,645 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:40,646 INFO L375 BasicCegarLoop]: trace histogram [13, 13, 12, 9, 9, 6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:40,646 INFO L423 AbstractCegarLoop]: === Iteration 33 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:40,646 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:40,646 INFO L82 PathProgramCache]: Analyzing trace with hash 1545010560, now seen corresponding path program 2 times [2018-11-18 15:50:40,646 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:40,646 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:40,647 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:40,647 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:50:40,647 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:40,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:41,153 INFO L134 CoverageAnalysis]: Checked inductivity of 453 backedges. 36 proven. 417 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:50:41,153 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:50:41,153 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:50:41,161 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-18 15:50:41,228 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 15:50:41,228 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:50:41,232 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:50:41,369 INFO L134 CoverageAnalysis]: Checked inductivity of 453 backedges. 36 proven. 397 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-11-18 15:50:41,386 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:50:41,386 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 11] total 24 [2018-11-18 15:50:41,386 INFO L459 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-11-18 15:50:41,386 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-11-18 15:50:41,387 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=492, Unknown=0, NotChecked=0, Total=552 [2018-11-18 15:50:41,387 INFO L87 Difference]: Start difference. First operand 973 states and 1433 transitions. Second operand 24 states. [2018-11-18 15:50:41,878 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:41,878 INFO L93 Difference]: Finished difference Result 1025 states and 1483 transitions. [2018-11-18 15:50:41,879 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-11-18 15:50:41,879 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 152 [2018-11-18 15:50:41,879 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:41,881 INFO L225 Difference]: With dead ends: 1025 [2018-11-18 15:50:41,881 INFO L226 Difference]: Without dead ends: 1023 [2018-11-18 15:50:41,882 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 181 GetRequests, 144 SyntacticMatches, 3 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 161 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=122, Invalid=1138, Unknown=0, NotChecked=0, Total=1260 [2018-11-18 15:50:41,883 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1023 states. [2018-11-18 15:50:41,906 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1023 to 973. [2018-11-18 15:50:41,906 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 973 states. [2018-11-18 15:50:41,907 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 973 states to 973 states and 1432 transitions. [2018-11-18 15:50:41,907 INFO L78 Accepts]: Start accepts. Automaton has 973 states and 1432 transitions. Word has length 152 [2018-11-18 15:50:41,908 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:41,908 INFO L480 AbstractCegarLoop]: Abstraction has 973 states and 1432 transitions. [2018-11-18 15:50:41,908 INFO L481 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-11-18 15:50:41,908 INFO L276 IsEmpty]: Start isEmpty. Operand 973 states and 1432 transitions. [2018-11-18 15:50:41,911 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 160 [2018-11-18 15:50:41,911 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:41,912 INFO L375 BasicCegarLoop]: trace histogram [14, 14, 13, 9, 9, 6, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:41,912 INFO L423 AbstractCegarLoop]: === Iteration 34 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:41,912 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:41,912 INFO L82 PathProgramCache]: Analyzing trace with hash -1285421549, now seen corresponding path program 3 times [2018-11-18 15:50:41,912 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:41,912 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:41,913 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:41,913 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:50:41,913 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:41,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:42,378 INFO L134 CoverageAnalysis]: Checked inductivity of 513 backedges. 39 proven. 474 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:50:42,378 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:50:42,378 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:50:42,384 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 15:50:42,429 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2018-11-18 15:50:42,430 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:50:42,433 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:50:43,179 WARN L180 SmtUtils]: Spent 137.00 ms on a formula simplification. DAG size of input: 29 DAG size of output: 15 [2018-11-18 15:50:43,534 INFO L134 CoverageAnalysis]: Checked inductivity of 513 backedges. 249 proven. 31 refuted. 0 times theorem prover too weak. 233 trivial. 0 not checked. [2018-11-18 15:50:43,558 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:50:43,558 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 8] total 22 [2018-11-18 15:50:43,558 INFO L459 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-11-18 15:50:43,559 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-11-18 15:50:43,559 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=405, Unknown=0, NotChecked=0, Total=462 [2018-11-18 15:50:43,559 INFO L87 Difference]: Start difference. First operand 973 states and 1432 transitions. Second operand 22 states. [2018-11-18 15:50:44,598 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:44,598 INFO L93 Difference]: Finished difference Result 1505 states and 2201 transitions. [2018-11-18 15:50:44,598 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2018-11-18 15:50:44,599 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 159 [2018-11-18 15:50:44,599 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:44,600 INFO L225 Difference]: With dead ends: 1505 [2018-11-18 15:50:44,601 INFO L226 Difference]: Without dead ends: 787 [2018-11-18 15:50:44,602 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 203 GetRequests, 162 SyntacticMatches, 1 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 234 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=170, Invalid=1552, Unknown=0, NotChecked=0, Total=1722 [2018-11-18 15:50:44,602 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 787 states. [2018-11-18 15:50:44,621 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 787 to 738. [2018-11-18 15:50:44,621 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 738 states. [2018-11-18 15:50:44,622 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 738 states to 738 states and 1036 transitions. [2018-11-18 15:50:44,623 INFO L78 Accepts]: Start accepts. Automaton has 738 states and 1036 transitions. Word has length 159 [2018-11-18 15:50:44,623 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:44,623 INFO L480 AbstractCegarLoop]: Abstraction has 738 states and 1036 transitions. [2018-11-18 15:50:44,623 INFO L481 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-11-18 15:50:44,623 INFO L276 IsEmpty]: Start isEmpty. Operand 738 states and 1036 transitions. [2018-11-18 15:50:44,624 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 170 [2018-11-18 15:50:44,624 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:44,624 INFO L375 BasicCegarLoop]: trace histogram [15, 14, 14, 10, 10, 6, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:44,624 INFO L423 AbstractCegarLoop]: === Iteration 35 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:44,624 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:44,625 INFO L82 PathProgramCache]: Analyzing trace with hash -348083931, now seen corresponding path program 3 times [2018-11-18 15:50:44,625 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:44,625 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:44,625 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:44,625 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:50:44,625 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:44,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:44,791 INFO L134 CoverageAnalysis]: Checked inductivity of 598 backedges. 98 proven. 470 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-11-18 15:50:44,791 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:50:44,792 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:50:44,799 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 15:50:44,919 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2018-11-18 15:50:44,920 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:50:44,923 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:50:44,948 INFO L134 CoverageAnalysis]: Checked inductivity of 598 backedges. 98 proven. 470 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-11-18 15:50:44,965 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:50:44,965 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 10 [2018-11-18 15:50:44,965 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-18 15:50:44,965 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-18 15:50:44,965 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-11-18 15:50:44,965 INFO L87 Difference]: Start difference. First operand 738 states and 1036 transitions. Second operand 10 states. [2018-11-18 15:50:45,097 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:45,097 INFO L93 Difference]: Finished difference Result 886 states and 1229 transitions. [2018-11-18 15:50:45,097 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-18 15:50:45,097 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 169 [2018-11-18 15:50:45,097 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:45,098 INFO L225 Difference]: With dead ends: 886 [2018-11-18 15:50:45,098 INFO L226 Difference]: Without dead ends: 802 [2018-11-18 15:50:45,099 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 184 GetRequests, 176 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-11-18 15:50:45,099 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 802 states. [2018-11-18 15:50:45,116 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 802 to 722. [2018-11-18 15:50:45,116 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 722 states. [2018-11-18 15:50:45,117 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 722 states to 722 states and 1013 transitions. [2018-11-18 15:50:45,117 INFO L78 Accepts]: Start accepts. Automaton has 722 states and 1013 transitions. Word has length 169 [2018-11-18 15:50:45,117 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:45,117 INFO L480 AbstractCegarLoop]: Abstraction has 722 states and 1013 transitions. [2018-11-18 15:50:45,117 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-18 15:50:45,117 INFO L276 IsEmpty]: Start isEmpty. Operand 722 states and 1013 transitions. [2018-11-18 15:50:45,117 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 182 [2018-11-18 15:50:45,118 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:45,118 INFO L375 BasicCegarLoop]: trace histogram [16, 16, 15, 11, 11, 7, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:45,118 INFO L423 AbstractCegarLoop]: === Iteration 36 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:45,118 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:45,118 INFO L82 PathProgramCache]: Analyzing trace with hash -441432313, now seen corresponding path program 1 times [2018-11-18 15:50:45,118 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:45,118 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:45,118 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:45,119 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:50:45,119 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:45,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:45,594 INFO L134 CoverageAnalysis]: Checked inductivity of 692 backedges. 45 proven. 611 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-11-18 15:50:45,594 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:50:45,594 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:50:45,616 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:45,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:45,697 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:50:45,775 INFO L134 CoverageAnalysis]: Checked inductivity of 692 backedges. 656 proven. 0 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-11-18 15:50:45,791 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-18 15:50:45,792 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [10] total 18 [2018-11-18 15:50:45,792 INFO L459 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-11-18 15:50:45,792 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-11-18 15:50:45,792 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=97, Invalid=209, Unknown=0, NotChecked=0, Total=306 [2018-11-18 15:50:45,792 INFO L87 Difference]: Start difference. First operand 722 states and 1013 transitions. Second operand 18 states. [2018-11-18 15:50:45,967 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:45,967 INFO L93 Difference]: Finished difference Result 865 states and 1213 transitions. [2018-11-18 15:50:45,968 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-18 15:50:45,968 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 181 [2018-11-18 15:50:45,968 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:45,970 INFO L225 Difference]: With dead ends: 865 [2018-11-18 15:50:45,970 INFO L226 Difference]: Without dead ends: 860 [2018-11-18 15:50:45,971 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 201 GetRequests, 180 SyntacticMatches, 5 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 28 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=97, Invalid=209, Unknown=0, NotChecked=0, Total=306 [2018-11-18 15:50:45,971 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 860 states. [2018-11-18 15:50:45,998 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 860 to 855. [2018-11-18 15:50:45,999 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 855 states. [2018-11-18 15:50:46,001 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 855 states to 855 states and 1202 transitions. [2018-11-18 15:50:46,002 INFO L78 Accepts]: Start accepts. Automaton has 855 states and 1202 transitions. Word has length 181 [2018-11-18 15:50:46,002 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:46,002 INFO L480 AbstractCegarLoop]: Abstraction has 855 states and 1202 transitions. [2018-11-18 15:50:46,002 INFO L481 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-11-18 15:50:46,002 INFO L276 IsEmpty]: Start isEmpty. Operand 855 states and 1202 transitions. [2018-11-18 15:50:46,003 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 183 [2018-11-18 15:50:46,003 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:46,003 INFO L375 BasicCegarLoop]: trace histogram [16, 16, 15, 11, 11, 7, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:46,004 INFO L423 AbstractCegarLoop]: === Iteration 37 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:46,004 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:46,004 INFO L82 PathProgramCache]: Analyzing trace with hash -788052353, now seen corresponding path program 3 times [2018-11-18 15:50:46,004 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:46,004 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:46,009 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:46,010 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:46,010 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:46,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:46,572 INFO L134 CoverageAnalysis]: Checked inductivity of 701 backedges. 45 proven. 656 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:50:46,572 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:50:46,573 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:50:46,580 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 15:50:46,700 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 13 check-sat command(s) [2018-11-18 15:50:46,701 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:50:46,704 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:50:47,049 INFO L134 CoverageAnalysis]: Checked inductivity of 701 backedges. 665 proven. 6 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-11-18 15:50:47,074 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:50:47,074 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 12] total 28 [2018-11-18 15:50:47,075 INFO L459 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-11-18 15:50:47,075 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-11-18 15:50:47,075 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=167, Invalid=589, Unknown=0, NotChecked=0, Total=756 [2018-11-18 15:50:47,076 INFO L87 Difference]: Start difference. First operand 855 states and 1202 transitions. Second operand 28 states. [2018-11-18 15:50:47,828 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:47,828 INFO L93 Difference]: Finished difference Result 871 states and 1217 transitions. [2018-11-18 15:50:47,829 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-11-18 15:50:47,830 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 182 [2018-11-18 15:50:47,830 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:47,832 INFO L225 Difference]: With dead ends: 871 [2018-11-18 15:50:47,832 INFO L226 Difference]: Without dead ends: 869 [2018-11-18 15:50:47,833 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 214 GetRequests, 174 SyntacticMatches, 2 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 147 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=299, Invalid=1261, Unknown=0, NotChecked=0, Total=1560 [2018-11-18 15:50:47,833 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 869 states. [2018-11-18 15:50:47,861 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 869 to 855. [2018-11-18 15:50:47,861 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 855 states. [2018-11-18 15:50:47,862 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 855 states to 855 states and 1201 transitions. [2018-11-18 15:50:47,862 INFO L78 Accepts]: Start accepts. Automaton has 855 states and 1201 transitions. Word has length 182 [2018-11-18 15:50:47,862 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:47,862 INFO L480 AbstractCegarLoop]: Abstraction has 855 states and 1201 transitions. [2018-11-18 15:50:47,863 INFO L481 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-11-18 15:50:47,863 INFO L276 IsEmpty]: Start isEmpty. Operand 855 states and 1201 transitions. [2018-11-18 15:50:47,864 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 198 [2018-11-18 15:50:47,864 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:47,867 INFO L375 BasicCegarLoop]: trace histogram [17, 16, 16, 12, 12, 8, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:47,868 INFO L423 AbstractCegarLoop]: === Iteration 38 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:47,868 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:47,868 INFO L82 PathProgramCache]: Analyzing trace with hash -1339885547, now seen corresponding path program 1 times [2018-11-18 15:50:47,868 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:47,868 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:47,869 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:47,869 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:50:47,869 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:47,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:48,062 INFO L134 CoverageAnalysis]: Checked inductivity of 811 backedges. 125 proven. 650 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-11-18 15:50:48,062 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:50:48,062 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:50:48,069 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:48,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:48,153 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:50:48,172 INFO L134 CoverageAnalysis]: Checked inductivity of 811 backedges. 125 proven. 650 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-11-18 15:50:48,188 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:50:48,188 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 11 [2018-11-18 15:50:48,189 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-18 15:50:48,189 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-18 15:50:48,189 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=55, Invalid=55, Unknown=0, NotChecked=0, Total=110 [2018-11-18 15:50:48,189 INFO L87 Difference]: Start difference. First operand 855 states and 1201 transitions. Second operand 11 states. [2018-11-18 15:50:48,311 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:48,311 INFO L93 Difference]: Finished difference Result 1437 states and 2015 transitions. [2018-11-18 15:50:48,311 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-18 15:50:48,311 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 197 [2018-11-18 15:50:48,311 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:48,313 INFO L225 Difference]: With dead ends: 1437 [2018-11-18 15:50:48,313 INFO L226 Difference]: Without dead ends: 962 [2018-11-18 15:50:48,314 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 214 GetRequests, 205 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=55, Invalid=55, Unknown=0, NotChecked=0, Total=110 [2018-11-18 15:50:48,315 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 962 states. [2018-11-18 15:50:48,334 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 962 to 933. [2018-11-18 15:50:48,335 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 933 states. [2018-11-18 15:50:48,336 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1313 transitions. [2018-11-18 15:50:48,336 INFO L78 Accepts]: Start accepts. Automaton has 933 states and 1313 transitions. Word has length 197 [2018-11-18 15:50:48,336 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:48,336 INFO L480 AbstractCegarLoop]: Abstraction has 933 states and 1313 transitions. [2018-11-18 15:50:48,336 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-18 15:50:48,336 INFO L276 IsEmpty]: Start isEmpty. Operand 933 states and 1313 transitions. [2018-11-18 15:50:48,337 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 199 [2018-11-18 15:50:48,337 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:48,337 INFO L375 BasicCegarLoop]: trace histogram [17, 17, 16, 12, 12, 8, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:48,338 INFO L423 AbstractCegarLoop]: === Iteration 39 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:48,338 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:48,338 INFO L82 PathProgramCache]: Analyzing trace with hash 403604017, now seen corresponding path program 3 times [2018-11-18 15:50:48,338 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:48,338 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:48,338 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:48,339 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:50:48,339 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:48,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:48,998 INFO L134 CoverageAnalysis]: Checked inductivity of 820 backedges. 53 proven. 742 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-11-18 15:50:48,999 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:50:48,999 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:50:49,005 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 15:50:49,141 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 13 check-sat command(s) [2018-11-18 15:50:49,142 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:50:49,147 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:50:49,336 INFO L134 CoverageAnalysis]: Checked inductivity of 820 backedges. 48 proven. 742 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-11-18 15:50:49,360 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:50:49,361 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 13] total 17 [2018-11-18 15:50:49,361 INFO L459 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-11-18 15:50:49,361 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-11-18 15:50:49,361 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=236, Unknown=0, NotChecked=0, Total=272 [2018-11-18 15:50:49,361 INFO L87 Difference]: Start difference. First operand 933 states and 1313 transitions. Second operand 17 states. [2018-11-18 15:50:49,815 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:49,815 INFO L93 Difference]: Finished difference Result 982 states and 1360 transitions. [2018-11-18 15:50:49,816 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-11-18 15:50:49,816 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 198 [2018-11-18 15:50:49,817 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:49,819 INFO L225 Difference]: With dead ends: 982 [2018-11-18 15:50:49,819 INFO L226 Difference]: Without dead ends: 980 [2018-11-18 15:50:49,820 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 230 GetRequests, 202 SyntacticMatches, 4 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 92 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=75, Invalid=575, Unknown=0, NotChecked=0, Total=650 [2018-11-18 15:50:49,820 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 980 states. [2018-11-18 15:50:49,847 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 980 to 933. [2018-11-18 15:50:49,847 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 933 states. [2018-11-18 15:50:49,848 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1312 transitions. [2018-11-18 15:50:49,849 INFO L78 Accepts]: Start accepts. Automaton has 933 states and 1312 transitions. Word has length 198 [2018-11-18 15:50:49,849 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:49,849 INFO L480 AbstractCegarLoop]: Abstraction has 933 states and 1312 transitions. [2018-11-18 15:50:49,849 INFO L481 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-11-18 15:50:49,849 INFO L276 IsEmpty]: Start isEmpty. Operand 933 states and 1312 transitions. [2018-11-18 15:50:49,850 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 216 [2018-11-18 15:50:49,850 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:49,850 INFO L375 BasicCegarLoop]: trace histogram [19, 18, 18, 13, 13, 8, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:49,850 INFO L423 AbstractCegarLoop]: === Iteration 40 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:49,851 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:49,851 INFO L82 PathProgramCache]: Analyzing trace with hash -576783212, now seen corresponding path program 4 times [2018-11-18 15:50:49,851 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:49,851 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:49,851 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:49,851 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:50:49,852 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:49,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:49,997 INFO L134 CoverageAnalysis]: Checked inductivity of 1010 backedges. 128 proven. 842 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-11-18 15:50:49,997 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:50:49,997 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/z3 Starting monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:50:50,003 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 15:50:50,105 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 15:50:50,105 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:50:50,109 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:50:50,149 INFO L134 CoverageAnalysis]: Checked inductivity of 1010 backedges. 128 proven. 842 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-11-18 15:50:50,177 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:50:50,177 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12] total 12 [2018-11-18 15:50:50,177 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-11-18 15:50:50,177 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-11-18 15:50:50,178 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-11-18 15:50:50,178 INFO L87 Difference]: Start difference. First operand 933 states and 1312 transitions. Second operand 12 states. [2018-11-18 15:50:50,418 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:50,418 INFO L93 Difference]: Finished difference Result 1127 states and 1565 transitions. [2018-11-18 15:50:50,419 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-18 15:50:50,419 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 215 [2018-11-18 15:50:50,420 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:50,422 INFO L225 Difference]: With dead ends: 1127 [2018-11-18 15:50:50,422 INFO L226 Difference]: Without dead ends: 1043 [2018-11-18 15:50:50,424 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 234 GetRequests, 224 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-11-18 15:50:50,424 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1043 states. [2018-11-18 15:50:50,451 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1043 to 1011. [2018-11-18 15:50:50,451 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1011 states. [2018-11-18 15:50:50,452 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1011 states to 1011 states and 1419 transitions. [2018-11-18 15:50:50,453 INFO L78 Accepts]: Start accepts. Automaton has 1011 states and 1419 transitions. Word has length 215 [2018-11-18 15:50:50,453 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:50,453 INFO L480 AbstractCegarLoop]: Abstraction has 1011 states and 1419 transitions. [2018-11-18 15:50:50,453 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-11-18 15:50:50,453 INFO L276 IsEmpty]: Start isEmpty. Operand 1011 states and 1419 transitions. [2018-11-18 15:50:50,454 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 244 [2018-11-18 15:50:50,454 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:50,455 INFO L375 BasicCegarLoop]: trace histogram [21, 20, 20, 15, 15, 10, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:50,455 INFO L423 AbstractCegarLoop]: === Iteration 41 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:50,455 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:50,455 INFO L82 PathProgramCache]: Analyzing trace with hash 1513807620, now seen corresponding path program 2 times [2018-11-18 15:50:50,455 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:50,455 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:50,456 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:50,456 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:50:50,456 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:50,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:50,790 INFO L134 CoverageAnalysis]: Checked inductivity of 1283 backedges. 159 proven. 1078 refuted. 0 times theorem prover too weak. 46 trivial. 0 not checked. [2018-11-18 15:50:50,790 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:50:50,790 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:50:50,807 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-18 15:50:50,915 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-18 15:50:50,915 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:50:50,920 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:50:50,950 INFO L134 CoverageAnalysis]: Checked inductivity of 1283 backedges. 159 proven. 1078 refuted. 0 times theorem prover too weak. 46 trivial. 0 not checked. [2018-11-18 15:50:50,967 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:50:50,967 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 13 [2018-11-18 15:50:50,968 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-18 15:50:50,968 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-18 15:50:50,968 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2018-11-18 15:50:50,968 INFO L87 Difference]: Start difference. First operand 1011 states and 1419 transitions. Second operand 13 states. [2018-11-18 15:50:51,136 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:51,136 INFO L93 Difference]: Finished difference Result 1677 states and 2348 transitions. [2018-11-18 15:50:51,137 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-18 15:50:51,138 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 243 [2018-11-18 15:50:51,138 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:51,140 INFO L225 Difference]: With dead ends: 1677 [2018-11-18 15:50:51,140 INFO L226 Difference]: Without dead ends: 1124 [2018-11-18 15:50:51,141 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 264 GetRequests, 253 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2018-11-18 15:50:51,142 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1124 states. [2018-11-18 15:50:51,201 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1124 to 1089. [2018-11-18 15:50:51,201 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1089 states. [2018-11-18 15:50:51,204 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1089 states to 1089 states and 1531 transitions. [2018-11-18 15:50:51,204 INFO L78 Accepts]: Start accepts. Automaton has 1089 states and 1531 transitions. Word has length 243 [2018-11-18 15:50:51,204 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:51,204 INFO L480 AbstractCegarLoop]: Abstraction has 1089 states and 1531 transitions. [2018-11-18 15:50:51,204 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-18 15:50:51,205 INFO L276 IsEmpty]: Start isEmpty. Operand 1089 states and 1531 transitions. [2018-11-18 15:50:51,206 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 245 [2018-11-18 15:50:51,206 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:51,206 INFO L375 BasicCegarLoop]: trace histogram [21, 21, 20, 15, 15, 10, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:51,207 INFO L423 AbstractCegarLoop]: === Iteration 42 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:51,207 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:51,207 INFO L82 PathProgramCache]: Analyzing trace with hash -1326221022, now seen corresponding path program 4 times [2018-11-18 15:50:51,207 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:51,207 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:51,208 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:51,208 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:50:51,208 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:51,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:51,940 INFO L134 CoverageAnalysis]: Checked inductivity of 1295 backedges. 68 proven. 1215 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-11-18 15:50:51,940 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:50:51,941 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/z3 Starting monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:50:51,947 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-18 15:50:52,012 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-18 15:50:52,012 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:50:52,016 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:50:52,190 INFO L134 CoverageAnalysis]: Checked inductivity of 1295 backedges. 60 proven. 1195 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-11-18 15:50:52,205 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:50:52,205 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 15] total 26 [2018-11-18 15:50:52,206 INFO L459 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-11-18 15:50:52,206 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-11-18 15:50:52,206 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=63, Invalid=587, Unknown=0, NotChecked=0, Total=650 [2018-11-18 15:50:52,206 INFO L87 Difference]: Start difference. First operand 1089 states and 1531 transitions. Second operand 26 states. [2018-11-18 15:50:53,360 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:53,360 INFO L93 Difference]: Finished difference Result 1203 states and 1641 transitions. [2018-11-18 15:50:53,360 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2018-11-18 15:50:53,361 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 244 [2018-11-18 15:50:53,361 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:53,363 INFO L225 Difference]: With dead ends: 1203 [2018-11-18 15:50:53,363 INFO L226 Difference]: Without dead ends: 1201 [2018-11-18 15:50:53,364 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 303 GetRequests, 243 SyntacticMatches, 4 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 628 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=215, Invalid=3091, Unknown=0, NotChecked=0, Total=3306 [2018-11-18 15:50:53,364 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1201 states. [2018-11-18 15:50:53,389 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1201 to 1089. [2018-11-18 15:50:53,389 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1089 states. [2018-11-18 15:50:53,390 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1089 states to 1089 states and 1530 transitions. [2018-11-18 15:50:53,391 INFO L78 Accepts]: Start accepts. Automaton has 1089 states and 1530 transitions. Word has length 244 [2018-11-18 15:50:53,391 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:53,391 INFO L480 AbstractCegarLoop]: Abstraction has 1089 states and 1530 transitions. [2018-11-18 15:50:53,391 INFO L481 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-11-18 15:50:53,391 INFO L276 IsEmpty]: Start isEmpty. Operand 1089 states and 1530 transitions. [2018-11-18 15:50:53,392 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 262 [2018-11-18 15:50:53,392 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:53,392 INFO L375 BasicCegarLoop]: trace histogram [23, 22, 22, 16, 16, 10, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:53,392 INFO L423 AbstractCegarLoop]: === Iteration 43 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:53,392 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:53,393 INFO L82 PathProgramCache]: Analyzing trace with hash -438655549, now seen corresponding path program 5 times [2018-11-18 15:50:53,393 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:53,393 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:53,393 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:53,393 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:50:53,393 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:53,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:53,563 INFO L134 CoverageAnalysis]: Checked inductivity of 1530 backedges. 158 proven. 1322 refuted. 0 times theorem prover too weak. 50 trivial. 0 not checked. [2018-11-18 15:50:53,563 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:50:53,563 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:50:53,572 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-18 15:50:53,775 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 14 check-sat command(s) [2018-11-18 15:50:53,775 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:50:53,781 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:50:53,824 INFO L134 CoverageAnalysis]: Checked inductivity of 1530 backedges. 158 proven. 1322 refuted. 0 times theorem prover too weak. 50 trivial. 0 not checked. [2018-11-18 15:50:53,840 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:50:53,840 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 14 [2018-11-18 15:50:53,840 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-11-18 15:50:53,840 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-11-18 15:50:53,840 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-11-18 15:50:53,841 INFO L87 Difference]: Start difference. First operand 1089 states and 1530 transitions. Second operand 14 states. [2018-11-18 15:50:54,032 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:54,032 INFO L93 Difference]: Finished difference Result 1289 states and 1787 transitions. [2018-11-18 15:50:54,032 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-11-18 15:50:54,032 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 261 [2018-11-18 15:50:54,032 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:54,034 INFO L225 Difference]: With dead ends: 1289 [2018-11-18 15:50:54,034 INFO L226 Difference]: Without dead ends: 1205 [2018-11-18 15:50:54,035 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 284 GetRequests, 272 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-11-18 15:50:54,035 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1205 states. [2018-11-18 15:50:54,063 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1205 to 1167. [2018-11-18 15:50:54,063 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1167 states. [2018-11-18 15:50:54,064 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1167 states to 1167 states and 1637 transitions. [2018-11-18 15:50:54,064 INFO L78 Accepts]: Start accepts. Automaton has 1167 states and 1637 transitions. Word has length 261 [2018-11-18 15:50:54,065 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:54,065 INFO L480 AbstractCegarLoop]: Abstraction has 1167 states and 1637 transitions. [2018-11-18 15:50:54,065 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-11-18 15:50:54,065 INFO L276 IsEmpty]: Start isEmpty. Operand 1167 states and 1637 transitions. [2018-11-18 15:50:54,066 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 290 [2018-11-18 15:50:54,066 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:54,066 INFO L375 BasicCegarLoop]: trace histogram [25, 24, 24, 18, 18, 12, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:54,067 INFO L423 AbstractCegarLoop]: === Iteration 44 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:54,067 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:54,067 INFO L82 PathProgramCache]: Analyzing trace with hash 1601829811, now seen corresponding path program 3 times [2018-11-18 15:50:54,067 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:54,067 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:54,067 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:54,067 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:50:54,068 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:54,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:54,262 INFO L134 CoverageAnalysis]: Checked inductivity of 1863 backedges. 193 proven. 1614 refuted. 0 times theorem prover too weak. 56 trivial. 0 not checked. [2018-11-18 15:50:54,263 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:50:54,263 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/z3 Starting monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:50:54,276 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-18 15:50:54,344 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2018-11-18 15:50:54,344 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:50:54,347 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:50:54,545 INFO L134 CoverageAnalysis]: Checked inductivity of 1863 backedges. 469 proven. 4 refuted. 0 times theorem prover too weak. 1390 trivial. 0 not checked. [2018-11-18 15:50:54,561 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:50:54,561 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 6] total 19 [2018-11-18 15:50:54,562 INFO L459 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-11-18 15:50:54,562 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-11-18 15:50:54,562 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=114, Invalid=228, Unknown=0, NotChecked=0, Total=342 [2018-11-18 15:50:54,562 INFO L87 Difference]: Start difference. First operand 1167 states and 1637 transitions. Second operand 19 states. [2018-11-18 15:50:55,465 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:55,465 INFO L93 Difference]: Finished difference Result 1320 states and 1838 transitions. [2018-11-18 15:50:55,465 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-11-18 15:50:55,465 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 289 [2018-11-18 15:50:55,465 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:55,466 INFO L225 Difference]: With dead ends: 1320 [2018-11-18 15:50:55,466 INFO L226 Difference]: Without dead ends: 689 [2018-11-18 15:50:55,468 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 359 GetRequests, 312 SyntacticMatches, 0 SemanticMatches, 47 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 512 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=576, Invalid=1776, Unknown=0, NotChecked=0, Total=2352 [2018-11-18 15:50:55,468 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 689 states. [2018-11-18 15:50:55,489 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 689 to 662. [2018-11-18 15:50:55,489 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 662 states. [2018-11-18 15:50:55,490 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 662 states to 662 states and 911 transitions. [2018-11-18 15:50:55,490 INFO L78 Accepts]: Start accepts. Automaton has 662 states and 911 transitions. Word has length 289 [2018-11-18 15:50:55,490 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:55,490 INFO L480 AbstractCegarLoop]: Abstraction has 662 states and 911 transitions. [2018-11-18 15:50:55,490 INFO L481 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-11-18 15:50:55,490 INFO L276 IsEmpty]: Start isEmpty. Operand 662 states and 911 transitions. [2018-11-18 15:50:55,491 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 291 [2018-11-18 15:50:55,491 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:55,491 INFO L375 BasicCegarLoop]: trace histogram [25, 25, 24, 18, 18, 12, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:55,492 INFO L423 AbstractCegarLoop]: === Iteration 45 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:55,492 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:55,492 INFO L82 PathProgramCache]: Analyzing trace with hash 1402466899, now seen corresponding path program 5 times [2018-11-18 15:50:55,492 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:55,492 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:55,493 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:55,493 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:50:55,493 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:55,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:56,097 WARN L180 SmtUtils]: Spent 184.00 ms on a formula simplification. DAG size of input: 13 DAG size of output: 10 [2018-11-18 15:50:56,406 INFO L134 CoverageAnalysis]: Checked inductivity of 1878 backedges. 77 proven. 1766 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2018-11-18 15:50:56,406 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:50:56,406 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:50:56,413 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-18 15:50:56,653 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 17 check-sat command(s) [2018-11-18 15:50:56,653 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:50:56,660 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:50:56,867 INFO L134 CoverageAnalysis]: Checked inductivity of 1878 backedges. 72 proven. 1776 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-11-18 15:50:56,884 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:50:56,884 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 21] total 26 [2018-11-18 15:50:56,884 INFO L459 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-11-18 15:50:56,884 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-11-18 15:50:56,884 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=593, Unknown=0, NotChecked=0, Total=650 [2018-11-18 15:50:56,884 INFO L87 Difference]: Start difference. First operand 662 states and 911 transitions. Second operand 26 states. [2018-11-18 15:50:58,033 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:50:58,034 INFO L93 Difference]: Finished difference Result 697 states and 944 transitions. [2018-11-18 15:50:58,034 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2018-11-18 15:50:58,034 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 290 [2018-11-18 15:50:58,034 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:50:58,035 INFO L225 Difference]: With dead ends: 697 [2018-11-18 15:50:58,035 INFO L226 Difference]: Without dead ends: 695 [2018-11-18 15:50:58,036 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 339 GetRequests, 294 SyntacticMatches, 3 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 311 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=135, Invalid=1757, Unknown=0, NotChecked=0, Total=1892 [2018-11-18 15:50:58,036 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 695 states. [2018-11-18 15:50:58,054 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 695 to 662. [2018-11-18 15:50:58,054 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 662 states. [2018-11-18 15:50:58,055 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 662 states to 662 states and 910 transitions. [2018-11-18 15:50:58,055 INFO L78 Accepts]: Start accepts. Automaton has 662 states and 910 transitions. Word has length 290 [2018-11-18 15:50:58,055 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:50:58,055 INFO L480 AbstractCegarLoop]: Abstraction has 662 states and 910 transitions. [2018-11-18 15:50:58,055 INFO L481 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-11-18 15:50:58,055 INFO L276 IsEmpty]: Start isEmpty. Operand 662 states and 910 transitions. [2018-11-18 15:50:58,056 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 337 [2018-11-18 15:50:58,056 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:50:58,056 INFO L375 BasicCegarLoop]: trace histogram [29, 29, 28, 21, 21, 14, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:50:58,056 INFO L423 AbstractCegarLoop]: === Iteration 46 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:50:58,056 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:50:58,056 INFO L82 PathProgramCache]: Analyzing trace with hash 800193988, now seen corresponding path program 6 times [2018-11-18 15:50:58,056 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:50:58,057 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:50:58,057 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:58,057 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:50:58,057 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:50:58,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:50:58,997 INFO L134 CoverageAnalysis]: Checked inductivity of 2569 backedges. 87 proven. 2435 refuted. 0 times theorem prover too weak. 47 trivial. 0 not checked. [2018-11-18 15:50:58,998 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:50:58,998 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/z3 Starting monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:50:59,005 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-18 15:50:59,266 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 21 check-sat command(s) [2018-11-18 15:50:59,266 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:50:59,273 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:51:00,041 INFO L134 CoverageAnalysis]: Checked inductivity of 2569 backedges. 2490 proven. 19 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-11-18 15:51:00,057 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:51:00,057 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 19] total 39 [2018-11-18 15:51:00,058 INFO L459 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-11-18 15:51:00,058 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-11-18 15:51:00,058 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=375, Invalid=1107, Unknown=0, NotChecked=0, Total=1482 [2018-11-18 15:51:00,058 INFO L87 Difference]: Start difference. First operand 662 states and 910 transitions. Second operand 39 states. [2018-11-18 15:51:01,277 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:51:01,277 INFO L93 Difference]: Finished difference Result 764 states and 1033 transitions. [2018-11-18 15:51:01,277 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2018-11-18 15:51:01,277 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 336 [2018-11-18 15:51:01,278 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:51:01,279 INFO L225 Difference]: With dead ends: 764 [2018-11-18 15:51:01,279 INFO L226 Difference]: Without dead ends: 762 [2018-11-18 15:51:01,279 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 405 GetRequests, 334 SyntacticMatches, 5 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 740 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=840, Invalid=3716, Unknown=0, NotChecked=0, Total=4556 [2018-11-18 15:51:01,280 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 762 states. [2018-11-18 15:51:01,298 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 762 to 662. [2018-11-18 15:51:01,299 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 662 states. [2018-11-18 15:51:01,299 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 662 states to 662 states and 909 transitions. [2018-11-18 15:51:01,300 INFO L78 Accepts]: Start accepts. Automaton has 662 states and 909 transitions. Word has length 336 [2018-11-18 15:51:01,300 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:51:01,300 INFO L480 AbstractCegarLoop]: Abstraction has 662 states and 909 transitions. [2018-11-18 15:51:01,300 INFO L481 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-11-18 15:51:01,300 INFO L276 IsEmpty]: Start isEmpty. Operand 662 states and 909 transitions. [2018-11-18 15:51:01,302 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 354 [2018-11-18 15:51:01,302 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:51:01,302 INFO L375 BasicCegarLoop]: trace histogram [31, 30, 30, 22, 22, 14, 8, 8, 8, 8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:51:01,302 INFO L423 AbstractCegarLoop]: === Iteration 47 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:51:01,302 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:51:01,302 INFO L82 PathProgramCache]: Analyzing trace with hash -1748649631, now seen corresponding path program 6 times [2018-11-18 15:51:01,303 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:51:01,303 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:51:01,303 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:51:01,303 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:51:01,303 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:51:01,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:51:01,735 INFO L134 CoverageAnalysis]: Checked inductivity of 2894 backedges. 218 proven. 2606 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2018-11-18 15:51:01,735 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 15:51:01,735 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 15:51:01,742 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-18 15:51:01,993 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 21 check-sat command(s) [2018-11-18 15:51:01,993 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-18 15:51:02,000 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:51:02,058 INFO L134 CoverageAnalysis]: Checked inductivity of 2894 backedges. 218 proven. 2606 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2018-11-18 15:51:02,083 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 15:51:02,083 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18] total 18 [2018-11-18 15:51:02,084 INFO L459 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-11-18 15:51:02,084 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-11-18 15:51:02,084 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2018-11-18 15:51:02,084 INFO L87 Difference]: Start difference. First operand 662 states and 909 transitions. Second operand 18 states. [2018-11-18 15:51:02,213 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:51:02,213 INFO L93 Difference]: Finished difference Result 867 states and 1192 transitions. [2018-11-18 15:51:02,214 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-11-18 15:51:02,214 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 353 [2018-11-18 15:51:02,214 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 15:51:02,216 INFO L225 Difference]: With dead ends: 867 [2018-11-18 15:51:02,216 INFO L226 Difference]: Without dead ends: 783 [2018-11-18 15:51:02,216 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 384 GetRequests, 368 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2018-11-18 15:51:02,217 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 783 states. [2018-11-18 15:51:02,255 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 783 to 740. [2018-11-18 15:51:02,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 740 states. [2018-11-18 15:51:02,256 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 740 states to 740 states and 1016 transitions. [2018-11-18 15:51:02,256 INFO L78 Accepts]: Start accepts. Automaton has 740 states and 1016 transitions. Word has length 353 [2018-11-18 15:51:02,256 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 15:51:02,257 INFO L480 AbstractCegarLoop]: Abstraction has 740 states and 1016 transitions. [2018-11-18 15:51:02,257 INFO L481 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-11-18 15:51:02,257 INFO L276 IsEmpty]: Start isEmpty. Operand 740 states and 1016 transitions. [2018-11-18 15:51:02,258 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 400 [2018-11-18 15:51:02,258 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 15:51:02,259 INFO L375 BasicCegarLoop]: trace histogram [35, 34, 34, 25, 25, 16, 9, 9, 9, 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:51:02,259 INFO L423 AbstractCegarLoop]: === Iteration 48 === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 15:51:02,259 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:51:02,259 INFO L82 PathProgramCache]: Analyzing trace with hash -1805057072, now seen corresponding path program 7 times [2018-11-18 15:51:02,259 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:51:02,259 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:51:02,260 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:51:02,260 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:51:02,260 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:51:02,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:51:03,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:51:03,112 INFO L442 BasicCegarLoop]: Counterexample might be feasible [2018-11-18 15:51:03,246 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 18.11 03:51:03 BoogieIcfgContainer [2018-11-18 15:51:03,246 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-18 15:51:03,247 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-18 15:51:03,247 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-18 15:51:03,247 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-18 15:51:03,247 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 03:50:17" (3/4) ... [2018-11-18 15:51:03,252 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-11-18 15:51:03,439 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_9a7e6381-450e-4401-bd00-bcfe99045459/bin-2019/uautomizer/witness.graphml [2018-11-18 15:51:03,439 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-18 15:51:03,440 INFO L168 Benchmark]: Toolchain (without parser) took 47677.00 ms. Allocated memory was 1.0 GB in the beginning and 1.8 GB in the end (delta: 812.6 MB). Free memory was 962.3 MB in the beginning and 1.4 GB in the end (delta: -458.9 MB). Peak memory consumption was 353.7 MB. Max. memory is 11.5 GB. [2018-11-18 15:51:03,442 INFO L168 Benchmark]: CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 982.7 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 15:51:03,442 INFO L168 Benchmark]: CACSL2BoogieTranslator took 312.34 ms. Allocated memory is still 1.0 GB. Free memory was 957.0 MB in the beginning and 939.8 MB in the end (delta: 17.2 MB). Peak memory consumption was 17.2 MB. Max. memory is 11.5 GB. [2018-11-18 15:51:03,442 INFO L168 Benchmark]: Boogie Preprocessor took 107.48 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 112.2 MB). Free memory was 939.8 MB in the beginning and 1.1 GB in the end (delta: -166.5 MB). Peak memory consumption was 21.1 MB. Max. memory is 11.5 GB. [2018-11-18 15:51:03,442 INFO L168 Benchmark]: RCFGBuilder took 1194.60 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 53.0 MB). Peak memory consumption was 53.0 MB. Max. memory is 11.5 GB. [2018-11-18 15:51:03,443 INFO L168 Benchmark]: TraceAbstraction took 45866.21 ms. Allocated memory was 1.1 GB in the beginning and 1.8 GB in the end (delta: 700.4 MB). Free memory was 1.1 GB in the beginning and 1.5 GB in the end (delta: -406.7 MB). Peak memory consumption was 293.8 MB. Max. memory is 11.5 GB. [2018-11-18 15:51:03,443 INFO L168 Benchmark]: Witness Printer took 192.63 ms. Allocated memory is still 1.8 GB. Free memory was 1.5 GB in the beginning and 1.4 GB in the end (delta: 38.7 MB). Peak memory consumption was 38.7 MB. Max. memory is 11.5 GB. [2018-11-18 15:51:03,444 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 982.7 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 312.34 ms. Allocated memory is still 1.0 GB. Free memory was 957.0 MB in the beginning and 939.8 MB in the end (delta: 17.2 MB). Peak memory consumption was 17.2 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 107.48 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 112.2 MB). Free memory was 939.8 MB in the beginning and 1.1 GB in the end (delta: -166.5 MB). Peak memory consumption was 21.1 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1194.60 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 53.0 MB). Peak memory consumption was 53.0 MB. Max. memory is 11.5 GB. * TraceAbstraction took 45866.21 ms. Allocated memory was 1.1 GB in the beginning and 1.8 GB in the end (delta: 700.4 MB). Free memory was 1.1 GB in the beginning and 1.5 GB in the end (delta: -406.7 MB). Peak memory consumption was 293.8 MB. Max. memory is 11.5 GB. * Witness Printer took 192.63 ms. Allocated memory is still 1.8 GB. Free memory was 1.5 GB in the beginning and 1.4 GB in the end (delta: 38.7 MB). Peak memory consumption was 38.7 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 569]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L5] int m_Protocol = 1; [L6] int m_msg_2 = 2; [L7] int m_recv_ack_2 = 3; [L8] int m_msg_1_1 = 4; [L9] int m_msg_1_2 = 5; [L10] int m_recv_ack_1_1 = 6; [L11] int m_recv_ack_1_2 = 7; VAL [\old(m_msg_1_1)=23, \old(m_msg_1_2)=20, \old(m_msg_2)=21, \old(m_Protocol)=25, \old(m_recv_ack_1_1)=22, \old(m_recv_ack_1_2)=24, \old(m_recv_ack_2)=26, m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3] [L16] int q = 0; [L17] int method_id; [L20] int this_expect = 0; [L21] int this_buffer_empty = 0; VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, q=0, this_buffer_empty=0, this_expect=0] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, P1=3, P2=3, P3=0, P4=3, P5=0, P6=0, P7=0, P8=1, P9=3, q=0, this_buffer_empty=0, this_expect=0] [L43] COND TRUE q == 0 [L44] COND TRUE __VERIFIER_nondet_int() [L46] COND TRUE 1 [L48] method_id = 1 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=1, P1=3, P2=3, P3=0, P4=3, P5=0, P6=0, P7=0, P8=1, P9=3, q=0, this_buffer_empty=0, this_expect=0] [L50] COND FALSE !(0) [L54] q = 1 [L56] this_expect=0 [L56] this_buffer_empty=1 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=1, P1=3, P2=3, P3=0, P4=3, P5=0, P6=0, P7=0, P8=1, P9=3, q=1, this_buffer_empty=1, this_expect=0] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=1, P1=18, P2=3, P3=0, P4=3, P5=0, P6=0, P7=0, P8=3, P9=3, q=1, this_buffer_empty=1, this_expect=0] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=1, P1=18, P2=3, P3=0, P4=3, P5=0, P6=0, P7=0, P8=3, P9=3, q=1, this_buffer_empty=1, this_expect=0] [L63] COND TRUE q == 1 [L64] COND TRUE __VERIFIER_nondet_int() [L66] COND TRUE !((P1 % 2) != (0 % 2)) [L68] method_id = 2 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=18, P2=3, P3=0, P4=3, P5=0, P6=0, P7=0, P8=3, P9=3, q=1, this_buffer_empty=1, this_expect=0] [L70] COND FALSE !((((((P1 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && !((P1 % 2) != (0 % 2))) || ((this_buffer_empty != 1) && !((P1 % 2) != (0 % 2))))) [L74] q = 3 [L76] this_expect=(this_expect + 1) [L76] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=18, P2=3, P3=0, P4=3, P5=0, P6=0, P7=0, P8=3, P9=3, q=3, this_buffer_empty=0, this_expect=1] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=3, P3=0, P4=3, P5=0, P6=0, P7=0, P8=3, P9=0, q=3, this_buffer_empty=0, this_expect=1] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=3, P3=0, P4=3, P5=0, P6=0, P7=0, P8=3, P9=0, q=3, this_buffer_empty=0, this_expect=1] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=3, P3=0, P4=3, P5=0, P6=0, P7=0, P8=3, P9=0, q=3, this_buffer_empty=0, this_expect=1] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=3, P3=0, P4=3, P5=0, P6=0, P7=0, P8=3, P9=0, q=3, this_buffer_empty=0, this_expect=1] [L263] COND TRUE q == 3 [L264] COND FALSE !(__VERIFIER_nondet_int()) [L280] COND TRUE __VERIFIER_nondet_int() [L282] COND TRUE !(P1 != (((0 + 1) - 1) % 2)) [L284] method_id = 3 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=3, P3=0, P4=3, P5=0, P6=0, P7=0, P8=3, P9=0, q=3, this_buffer_empty=0, this_expect=1] [L286] COND FALSE !((((this_buffer_empty == 1) && !(P3 != (((0 + 1) - 1) % 2))) || (((P3 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && !(P3 != (((0 + 1) - 1) % 2))))) [L290] q = 4 [L292] this_expect=this_expect [L292] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=3, P3=0, P4=3, P5=0, P6=0, P7=0, P8=3, P9=0, q=4, this_buffer_empty=1, this_expect=1] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=7, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=1] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=7, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=1] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=7, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=1] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=7, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=1] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=7, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=1] [L363] COND TRUE q == 4 [L364] COND FALSE !(__VERIFIER_nondet_int()) [L380] COND FALSE !(__VERIFIER_nondet_int()) [L396] COND FALSE !(__VERIFIER_nondet_int()) [L412] COND TRUE __VERIFIER_nondet_int() [L414] COND TRUE (((P1 % 2) != (0 % 2)) && !(((P1 % 2) != ((0 + 1) % 2)) && ((P1 % 2) != (0 % 2)))) [L416] method_id = 5 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=7, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=1] [L418] COND FALSE !(((((((P6 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))) || (((this_buffer_empty != 1) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))))) [L422] q = 5 [L424] this_expect=(this_expect + 1) [L424] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=7, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=5, this_buffer_empty=0, this_expect=2] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-3, q=5, this_buffer_empty=0, this_expect=2] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-3, q=5, this_buffer_empty=0, this_expect=2] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-3, q=5, this_buffer_empty=0, this_expect=2] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-3, q=5, this_buffer_empty=0, this_expect=2] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-3, q=5, this_buffer_empty=0, this_expect=2] [L363] COND FALSE !(q == 4) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-3, q=5, this_buffer_empty=0, this_expect=2] [L463] COND TRUE q == 5 [L464] COND FALSE !(__VERIFIER_nondet_int()) [L480] COND FALSE !(__VERIFIER_nondet_int()) [L496] COND FALSE !(__VERIFIER_nondet_int()) [L512] COND FALSE !(__VERIFIER_nondet_int()) [L528] COND FALSE !(__VERIFIER_nondet_int()) [L544] COND TRUE __VERIFIER_nondet_int() [L546] COND TRUE ((P1 != (((0 + 1) - 1) % 2)) && !((P1 != ((((0 + 1) + 1) - 1) % 2)) && (P1 != (((0 + 1) - 1) % 2)))) [L548] method_id = 7 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-3, q=5, this_buffer_empty=0, this_expect=2] [L550] COND FALSE !(((((this_buffer_empty == 1) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))) || ((((P9 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))))) [L554] q = 1 [L556] this_expect=this_expect [L556] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-3, q=1, this_buffer_empty=1, this_expect=2] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=14, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=2] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=14, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=2] [L63] COND TRUE q == 1 [L64] COND TRUE __VERIFIER_nondet_int() [L66] COND TRUE !((P1 % 2) != (0 % 2)) [L68] method_id = 2 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=14, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=2] [L70] COND FALSE !((((((P1 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && !((P1 % 2) != (0 % 2))) || ((this_buffer_empty != 1) && !((P1 % 2) != (0 % 2))))) [L74] q = 3 [L76] this_expect=(this_expect + 1) [L76] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=14, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=3] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=3] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=3] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=3] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=3] [L263] COND TRUE q == 3 [L264] COND FALSE !(__VERIFIER_nondet_int()) [L280] COND TRUE __VERIFIER_nondet_int() [L282] COND TRUE !(P1 != (((0 + 1) - 1) % 2)) [L284] method_id = 3 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=3] [L286] COND FALSE !((((this_buffer_empty == 1) && !(P3 != (((0 + 1) - 1) % 2))) || (((P3 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && !(P3 != (((0 + 1) - 1) % 2))))) [L290] q = 4 [L292] this_expect=this_expect [L292] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=3] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=19, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=3] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=19, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=3] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=19, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=3] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=19, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=3] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=19, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=3] [L363] COND TRUE q == 4 [L364] COND FALSE !(__VERIFIER_nondet_int()) [L380] COND FALSE !(__VERIFIER_nondet_int()) [L396] COND FALSE !(__VERIFIER_nondet_int()) [L412] COND TRUE __VERIFIER_nondet_int() [L414] COND TRUE (((P1 % 2) != (0 % 2)) && !(((P1 % 2) != ((0 + 1) % 2)) && ((P1 % 2) != (0 % 2)))) [L416] method_id = 5 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=19, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=3] [L418] COND FALSE !(((((((P6 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))) || (((this_buffer_empty != 1) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))))) [L422] q = 5 [L424] this_expect=(this_expect + 1) [L424] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=19, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=5, this_buffer_empty=0, this_expect=4] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=0, q=5, this_buffer_empty=0, this_expect=4] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=0, q=5, this_buffer_empty=0, this_expect=4] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=0, q=5, this_buffer_empty=0, this_expect=4] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=0, q=5, this_buffer_empty=0, this_expect=4] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=0, q=5, this_buffer_empty=0, this_expect=4] [L363] COND FALSE !(q == 4) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=0, q=5, this_buffer_empty=0, this_expect=4] [L463] COND TRUE q == 5 [L464] COND FALSE !(__VERIFIER_nondet_int()) [L480] COND FALSE !(__VERIFIER_nondet_int()) [L496] COND FALSE !(__VERIFIER_nondet_int()) [L512] COND FALSE !(__VERIFIER_nondet_int()) [L528] COND FALSE !(__VERIFIER_nondet_int()) [L544] COND TRUE __VERIFIER_nondet_int() [L546] COND TRUE ((P1 != (((0 + 1) - 1) % 2)) && !((P1 != ((((0 + 1) + 1) - 1) % 2)) && (P1 != (((0 + 1) - 1) % 2)))) [L548] method_id = 7 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=0, q=5, this_buffer_empty=0, this_expect=4] [L550] COND FALSE !(((((this_buffer_empty == 1) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))) || ((((P9 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))))) [L554] q = 1 [L556] this_expect=this_expect [L556] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=0, q=1, this_buffer_empty=1, this_expect=4] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-10, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=4] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-10, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=4] [L63] COND TRUE q == 1 [L64] COND TRUE __VERIFIER_nondet_int() [L66] COND TRUE !((P1 % 2) != (0 % 2)) [L68] method_id = 2 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-10, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=4] [L70] COND FALSE !((((((P1 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && !((P1 % 2) != (0 % 2))) || ((this_buffer_empty != 1) && !((P1 % 2) != (0 % 2))))) [L74] q = 3 [L76] this_expect=(this_expect + 1) [L76] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-10, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=5] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=5] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=5] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=5] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=5] [L263] COND TRUE q == 3 [L264] COND FALSE !(__VERIFIER_nondet_int()) [L280] COND TRUE __VERIFIER_nondet_int() [L282] COND TRUE !(P1 != (((0 + 1) - 1) % 2)) [L284] method_id = 3 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=5] [L286] COND FALSE !((((this_buffer_empty == 1) && !(P3 != (((0 + 1) - 1) % 2))) || (((P3 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && !(P3 != (((0 + 1) - 1) % 2))))) [L290] q = 4 [L292] this_expect=this_expect [L292] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=5] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=5, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=5] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=5, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=5] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=5, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=5] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=5, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=5] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=5, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=5] [L363] COND TRUE q == 4 [L364] COND FALSE !(__VERIFIER_nondet_int()) [L380] COND FALSE !(__VERIFIER_nondet_int()) [L396] COND FALSE !(__VERIFIER_nondet_int()) [L412] COND TRUE __VERIFIER_nondet_int() [L414] COND TRUE (((P1 % 2) != (0 % 2)) && !(((P1 % 2) != ((0 + 1) % 2)) && ((P1 % 2) != (0 % 2)))) [L416] method_id = 5 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=5, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=5] [L418] COND FALSE !(((((((P6 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))) || (((this_buffer_empty != 1) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))))) [L422] q = 5 [L424] this_expect=(this_expect + 1) [L424] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=5, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=5, this_buffer_empty=0, this_expect=6] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=6] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=6] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=6] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=6] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=6] [L363] COND FALSE !(q == 4) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=6] [L463] COND TRUE q == 5 [L464] COND FALSE !(__VERIFIER_nondet_int()) [L480] COND FALSE !(__VERIFIER_nondet_int()) [L496] COND FALSE !(__VERIFIER_nondet_int()) [L512] COND FALSE !(__VERIFIER_nondet_int()) [L528] COND FALSE !(__VERIFIER_nondet_int()) [L544] COND TRUE __VERIFIER_nondet_int() [L546] COND TRUE ((P1 != (((0 + 1) - 1) % 2)) && !((P1 != ((((0 + 1) + 1) - 1) % 2)) && (P1 != (((0 + 1) - 1) % 2)))) [L548] method_id = 7 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=6] [L550] COND FALSE !(((((this_buffer_empty == 1) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))) || ((((P9 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))))) [L554] q = 1 [L556] this_expect=this_expect [L556] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=1, this_buffer_empty=1, this_expect=6] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-4, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=6] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-4, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=6] [L63] COND TRUE q == 1 [L64] COND TRUE __VERIFIER_nondet_int() [L66] COND TRUE !((P1 % 2) != (0 % 2)) [L68] method_id = 2 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-4, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=6] [L70] COND FALSE !((((((P1 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && !((P1 % 2) != (0 % 2))) || ((this_buffer_empty != 1) && !((P1 % 2) != (0 % 2))))) [L74] q = 3 [L76] this_expect=(this_expect + 1) [L76] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-4, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=7] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=7] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=7] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=7] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=7] [L263] COND TRUE q == 3 [L264] COND FALSE !(__VERIFIER_nondet_int()) [L280] COND TRUE __VERIFIER_nondet_int() [L282] COND TRUE !(P1 != (((0 + 1) - 1) % 2)) [L284] method_id = 3 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=7] [L286] COND FALSE !((((this_buffer_empty == 1) && !(P3 != (((0 + 1) - 1) % 2))) || (((P3 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && !(P3 != (((0 + 1) - 1) % 2))))) [L290] q = 4 [L292] this_expect=this_expect [L292] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=7] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=9, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=7] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=9, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=7] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=9, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=7] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=9, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=7] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=9, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=7] [L363] COND TRUE q == 4 [L364] COND FALSE !(__VERIFIER_nondet_int()) [L380] COND FALSE !(__VERIFIER_nondet_int()) [L396] COND FALSE !(__VERIFIER_nondet_int()) [L412] COND TRUE __VERIFIER_nondet_int() [L414] COND TRUE (((P1 % 2) != (0 % 2)) && !(((P1 % 2) != ((0 + 1) % 2)) && ((P1 % 2) != (0 % 2)))) [L416] method_id = 5 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=9, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=7] [L418] COND FALSE !(((((((P6 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))) || (((this_buffer_empty != 1) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))))) [L422] q = 5 [L424] this_expect=(this_expect + 1) [L424] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=9, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=5, this_buffer_empty=0, this_expect=8] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=8] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=8] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=8] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=8] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=8] [L363] COND FALSE !(q == 4) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=8] [L463] COND TRUE q == 5 [L464] COND FALSE !(__VERIFIER_nondet_int()) [L480] COND FALSE !(__VERIFIER_nondet_int()) [L496] COND FALSE !(__VERIFIER_nondet_int()) [L512] COND FALSE !(__VERIFIER_nondet_int()) [L528] COND FALSE !(__VERIFIER_nondet_int()) [L544] COND TRUE __VERIFIER_nondet_int() [L546] COND TRUE ((P1 != (((0 + 1) - 1) % 2)) && !((P1 != ((((0 + 1) + 1) - 1) % 2)) && (P1 != (((0 + 1) - 1) % 2)))) [L548] method_id = 7 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=8] [L550] COND FALSE !(((((this_buffer_empty == 1) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))) || ((((P9 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))))) [L554] q = 1 [L556] this_expect=this_expect [L556] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=1, this_buffer_empty=1, this_expect=8] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=2, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=8] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=2, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=8] [L63] COND TRUE q == 1 [L64] COND TRUE __VERIFIER_nondet_int() [L66] COND TRUE !((P1 % 2) != (0 % 2)) [L68] method_id = 2 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=2, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=8] [L70] COND FALSE !((((((P1 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && !((P1 % 2) != (0 % 2))) || ((this_buffer_empty != 1) && !((P1 % 2) != (0 % 2))))) [L74] q = 3 [L76] this_expect=(this_expect + 1) [L76] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=2, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=9] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=9] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=9] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=9] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=9] [L263] COND TRUE q == 3 [L264] COND FALSE !(__VERIFIER_nondet_int()) [L280] COND TRUE __VERIFIER_nondet_int() [L282] COND TRUE !(P1 != (((0 + 1) - 1) % 2)) [L284] method_id = 3 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=9] [L286] COND FALSE !((((this_buffer_empty == 1) && !(P3 != (((0 + 1) - 1) % 2))) || (((P3 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && !(P3 != (((0 + 1) - 1) % 2))))) [L290] q = 4 [L292] this_expect=this_expect [L292] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=9] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=11, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=9] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=11, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=9] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=11, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=9] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=11, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=9] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=11, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=9] [L363] COND TRUE q == 4 [L364] COND FALSE !(__VERIFIER_nondet_int()) [L380] COND FALSE !(__VERIFIER_nondet_int()) [L396] COND FALSE !(__VERIFIER_nondet_int()) [L412] COND TRUE __VERIFIER_nondet_int() [L414] COND TRUE (((P1 % 2) != (0 % 2)) && !(((P1 % 2) != ((0 + 1) % 2)) && ((P1 % 2) != (0 % 2)))) [L416] method_id = 5 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=11, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=9] [L418] COND FALSE !(((((((P6 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))) || (((this_buffer_empty != 1) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))))) [L422] q = 5 [L424] this_expect=(this_expect + 1) [L424] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=11, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=5, this_buffer_empty=0, this_expect=10] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=4, q=5, this_buffer_empty=0, this_expect=10] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=4, q=5, this_buffer_empty=0, this_expect=10] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=4, q=5, this_buffer_empty=0, this_expect=10] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=4, q=5, this_buffer_empty=0, this_expect=10] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=4, q=5, this_buffer_empty=0, this_expect=10] [L363] COND FALSE !(q == 4) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=4, q=5, this_buffer_empty=0, this_expect=10] [L463] COND TRUE q == 5 [L464] COND FALSE !(__VERIFIER_nondet_int()) [L480] COND FALSE !(__VERIFIER_nondet_int()) [L496] COND FALSE !(__VERIFIER_nondet_int()) [L512] COND FALSE !(__VERIFIER_nondet_int()) [L528] COND FALSE !(__VERIFIER_nondet_int()) [L544] COND TRUE __VERIFIER_nondet_int() [L546] COND TRUE ((P1 != (((0 + 1) - 1) % 2)) && !((P1 != ((((0 + 1) + 1) - 1) % 2)) && (P1 != (((0 + 1) - 1) % 2)))) [L548] method_id = 7 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=4, q=5, this_buffer_empty=0, this_expect=10] [L550] COND FALSE !(((((this_buffer_empty == 1) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))) || ((((P9 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))))) [L554] q = 1 [L556] this_expect=this_expect [L556] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=4, q=1, this_buffer_empty=1, this_expect=10] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-12, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=10] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-12, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=10] [L63] COND TRUE q == 1 [L64] COND TRUE __VERIFIER_nondet_int() [L66] COND TRUE !((P1 % 2) != (0 % 2)) [L68] method_id = 2 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-12, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=10] [L70] COND FALSE !((((((P1 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && !((P1 % 2) != (0 % 2))) || ((this_buffer_empty != 1) && !((P1 % 2) != (0 % 2))))) [L74] q = 3 [L76] this_expect=(this_expect + 1) [L76] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-12, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=11] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=11] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=11] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=11] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=11] [L263] COND TRUE q == 3 [L264] COND FALSE !(__VERIFIER_nondet_int()) [L280] COND TRUE __VERIFIER_nondet_int() [L282] COND TRUE !(P1 != (((0 + 1) - 1) % 2)) [L284] method_id = 3 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=11] [L286] COND FALSE !((((this_buffer_empty == 1) && !(P3 != (((0 + 1) - 1) % 2))) || (((P3 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && !(P3 != (((0 + 1) - 1) % 2))))) [L290] q = 4 [L292] this_expect=this_expect [L292] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=11] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=13, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=11] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=13, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=11] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=13, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=11] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=13, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=11] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=13, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=11] [L363] COND TRUE q == 4 [L364] COND FALSE !(__VERIFIER_nondet_int()) [L380] COND FALSE !(__VERIFIER_nondet_int()) [L396] COND FALSE !(__VERIFIER_nondet_int()) [L412] COND TRUE __VERIFIER_nondet_int() [L414] COND TRUE (((P1 % 2) != (0 % 2)) && !(((P1 % 2) != ((0 + 1) % 2)) && ((P1 % 2) != (0 % 2)))) [L416] method_id = 5 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=13, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=11] [L418] COND FALSE !(((((((P6 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))) || (((this_buffer_empty != 1) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))))) [L422] q = 5 [L424] this_expect=(this_expect + 1) [L424] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=13, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=5, this_buffer_empty=0, this_expect=12] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=12] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=12] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=12] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=12] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=12] [L363] COND FALSE !(q == 4) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=12] [L463] COND TRUE q == 5 [L464] COND FALSE !(__VERIFIER_nondet_int()) [L480] COND FALSE !(__VERIFIER_nondet_int()) [L496] COND FALSE !(__VERIFIER_nondet_int()) [L512] COND FALSE !(__VERIFIER_nondet_int()) [L528] COND FALSE !(__VERIFIER_nondet_int()) [L544] COND TRUE __VERIFIER_nondet_int() [L546] COND TRUE ((P1 != (((0 + 1) - 1) % 2)) && !((P1 != ((((0 + 1) + 1) - 1) % 2)) && (P1 != (((0 + 1) - 1) % 2)))) [L548] method_id = 7 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=12] [L550] COND FALSE !(((((this_buffer_empty == 1) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))) || ((((P9 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))))) [L554] q = 1 [L556] this_expect=this_expect [L556] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=1, this_buffer_empty=1, this_expect=12] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-6, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=12] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-6, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=12] [L63] COND TRUE q == 1 [L64] COND TRUE __VERIFIER_nondet_int() [L66] COND TRUE !((P1 % 2) != (0 % 2)) [L68] method_id = 2 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-6, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=12] [L70] COND FALSE !((((((P1 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && !((P1 % 2) != (0 % 2))) || ((this_buffer_empty != 1) && !((P1 % 2) != (0 % 2))))) [L74] q = 3 [L76] this_expect=(this_expect + 1) [L76] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-6, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=13] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=13] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=13] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=13] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=13] [L263] COND TRUE q == 3 [L264] COND FALSE !(__VERIFIER_nondet_int()) [L280] COND TRUE __VERIFIER_nondet_int() [L282] COND TRUE !(P1 != (((0 + 1) - 1) % 2)) [L284] method_id = 3 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=13] [L286] COND FALSE !((((this_buffer_empty == 1) && !(P3 != (((0 + 1) - 1) % 2))) || (((P3 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && !(P3 != (((0 + 1) - 1) % 2))))) [L290] q = 4 [L292] this_expect=this_expect [L292] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=13] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=15, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=13] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=15, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=13] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=15, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=13] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=15, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=13] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=15, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=13] [L363] COND TRUE q == 4 [L364] COND FALSE !(__VERIFIER_nondet_int()) [L380] COND FALSE !(__VERIFIER_nondet_int()) [L396] COND FALSE !(__VERIFIER_nondet_int()) [L412] COND TRUE __VERIFIER_nondet_int() [L414] COND TRUE (((P1 % 2) != (0 % 2)) && !(((P1 % 2) != ((0 + 1) % 2)) && ((P1 % 2) != (0 % 2)))) [L416] method_id = 5 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=15, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=13] [L418] COND FALSE !(((((((P6 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))) || (((this_buffer_empty != 1) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))))) [L422] q = 5 [L424] this_expect=(this_expect + 1) [L424] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=15, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=5, this_buffer_empty=0, this_expect=14] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=14] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=14] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=14] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=14] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=14] [L363] COND FALSE !(q == 4) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=14] [L463] COND TRUE q == 5 [L464] COND FALSE !(__VERIFIER_nondet_int()) [L480] COND FALSE !(__VERIFIER_nondet_int()) [L496] COND FALSE !(__VERIFIER_nondet_int()) [L512] COND FALSE !(__VERIFIER_nondet_int()) [L528] COND FALSE !(__VERIFIER_nondet_int()) [L544] COND TRUE __VERIFIER_nondet_int() [L546] COND TRUE ((P1 != (((0 + 1) - 1) % 2)) && !((P1 != ((((0 + 1) + 1) - 1) % 2)) && (P1 != (((0 + 1) - 1) % 2)))) [L548] method_id = 7 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=14] [L550] COND FALSE !(((((this_buffer_empty == 1) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))) || ((((P9 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))))) [L554] q = 1 [L556] this_expect=this_expect [L556] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=1, this_buffer_empty=1, this_expect=14] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-8, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=14] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-8, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=14] [L63] COND TRUE q == 1 [L64] COND TRUE __VERIFIER_nondet_int() [L66] COND TRUE !((P1 % 2) != (0 % 2)) [L68] method_id = 2 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-8, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=14] [L70] COND FALSE !((((((P1 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && !((P1 % 2) != (0 % 2))) || ((this_buffer_empty != 1) && !((P1 % 2) != (0 % 2))))) [L74] q = 3 [L76] this_expect=(this_expect + 1) [L76] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-8, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=15] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=15] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=15] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=15] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=15] [L263] COND TRUE q == 3 [L264] COND FALSE !(__VERIFIER_nondet_int()) [L280] COND TRUE __VERIFIER_nondet_int() [L282] COND TRUE !(P1 != (((0 + 1) - 1) % 2)) [L284] method_id = 3 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=15] [L286] COND FALSE !((((this_buffer_empty == 1) && !(P3 != (((0 + 1) - 1) % 2))) || (((P3 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && !(P3 != (((0 + 1) - 1) % 2))))) [L290] q = 4 [L292] this_expect=this_expect [L292] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=15] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=17, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=15] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=17, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=15] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=17, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=15] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=17, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=15] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=17, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=15] [L363] COND TRUE q == 4 [L364] COND FALSE !(__VERIFIER_nondet_int()) [L380] COND FALSE !(__VERIFIER_nondet_int()) [L396] COND FALSE !(__VERIFIER_nondet_int()) [L412] COND TRUE __VERIFIER_nondet_int() [L414] COND TRUE (((P1 % 2) != (0 % 2)) && !(((P1 % 2) != ((0 + 1) % 2)) && ((P1 % 2) != (0 % 2)))) [L416] method_id = 5 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=17, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=15] [L418] COND FALSE !(((((((P6 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))) || (((this_buffer_empty != 1) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))))) [L422] q = 5 [L424] this_expect=(this_expect + 1) [L424] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=17, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=5, this_buffer_empty=0, this_expect=16] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=16] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=16] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=16] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=16] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=16] [L363] COND FALSE !(q == 4) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=16] [L463] COND TRUE q == 5 [L464] COND FALSE !(__VERIFIER_nondet_int()) [L480] COND FALSE !(__VERIFIER_nondet_int()) [L496] COND FALSE !(__VERIFIER_nondet_int()) [L512] COND FALSE !(__VERIFIER_nondet_int()) [L528] COND FALSE !(__VERIFIER_nondet_int()) [L544] COND TRUE __VERIFIER_nondet_int() [L546] COND TRUE ((P1 != (((0 + 1) - 1) % 2)) && !((P1 != ((((0 + 1) + 1) - 1) % 2)) && (P1 != (((0 + 1) - 1) % 2)))) [L548] method_id = 7 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=16] [L550] COND FALSE !(((((this_buffer_empty == 1) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))) || ((((P9 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))))) [L554] q = 1 [L556] this_expect=this_expect [L556] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=1, this_buffer_empty=1, this_expect=16] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-14, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=16] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-14, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=16] [L63] COND TRUE q == 1 [L64] COND TRUE __VERIFIER_nondet_int() [L66] COND TRUE !((P1 % 2) != (0 % 2)) [L68] method_id = 2 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-14, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=16] [L70] COND FALSE !((((((P1 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && !((P1 % 2) != (0 % 2))) || ((this_buffer_empty != 1) && !((P1 % 2) != (0 % 2))))) [L74] q = 3 [L76] this_expect=(this_expect + 1) [L76] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-14, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=17] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND TRUE this_expect > 16 [L39] this_expect = -16 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=-16] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=-16] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=-16] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=-16] [L263] COND TRUE q == 3 [L264] COND FALSE !(__VERIFIER_nondet_int()) [L280] COND TRUE __VERIFIER_nondet_int() [L282] COND TRUE !(P1 != (((0 + 1) - 1) % 2)) [L284] method_id = 3 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=-16] [L286] COND TRUE (((this_buffer_empty == 1) && !(P3 != (((0 + 1) - 1) % 2))) || (((P3 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && !(P3 != (((0 + 1) - 1) % 2)))) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=-16] [L569] __VERIFIER_error() VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=-16] - StatisticsResult: Ultimate Automizer benchmark data CFG has 3 procedures, 115 locations, 1 error locations. UNSAFE Result, 45.8s OverallTime, 48 OverallIterations, 35 TraceHistogramMax, 16.9s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 11483 SDtfs, 20349 SDslu, 85865 SDs, 0 SdLazy, 13844 SolverSat, 1377 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 10.5s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 6302 GetRequests, 5573 SyntacticMatches, 69 SemanticMatches, 660 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3256 ImplicationChecksByTransitivity, 19.7s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=1167occurred in iteration=43, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.8s AutomataMinimizationTime, 47 MinimizatonAttempts, 1241 StatesRemovedByMinimization, 45 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.6s SsaConstructionTime, 4.2s SatisfiabilityAnalysisTime, 19.9s InterpolantComputationTime, 11621 NumberOfCodeBlocks, 11063 NumberOfCodeBlocksAsserted, 209 NumberOfCheckSat, 11136 ConstructedInterpolants, 133 QuantifiedInterpolants, 10724004 SizeOfPredicates, 88 NumberOfNonLiveVariables, 29287 ConjunctsInSsa, 822 ConjunctsInUnsatCore, 86 InterpolantComputations, 11 PerfectInterpolantSequences, 11912/45464 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...