./Ultimate.py --spec ../../sv-benchmarks/c/ReachSafety.prp --file ../../sv-benchmarks/c/systemc/toy1_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 5842f4b8 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_6927db1b-4eaa-477c-a665-46bbf54692a2/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_6927db1b-4eaa-477c-a665-46bbf54692a2/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_6927db1b-4eaa-477c-a665-46bbf54692a2/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_6927db1b-4eaa-477c-a665-46bbf54692a2/bin-2019/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/systemc/toy1_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_6927db1b-4eaa-477c-a665-46bbf54692a2/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_6927db1b-4eaa-477c-a665-46bbf54692a2/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 133c91eb4ca703e3ebf3582d43ed0be6dbefca67 ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-5842f4b [2018-11-18 17:03:33,339 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-18 17:03:33,341 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-18 17:03:33,348 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-18 17:03:33,348 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-18 17:03:33,348 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-18 17:03:33,349 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-18 17:03:33,350 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-18 17:03:33,351 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-18 17:03:33,352 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-18 17:03:33,353 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-18 17:03:33,353 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-18 17:03:33,354 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-18 17:03:33,354 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-18 17:03:33,355 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-18 17:03:33,356 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-18 17:03:33,356 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-18 17:03:33,357 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-18 17:03:33,359 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-18 17:03:33,360 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-18 17:03:33,360 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-18 17:03:33,361 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-18 17:03:33,363 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-18 17:03:33,363 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-18 17:03:33,363 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-18 17:03:33,364 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-18 17:03:33,365 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-18 17:03:33,365 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-18 17:03:33,366 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-18 17:03:33,366 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-18 17:03:33,367 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-18 17:03:33,367 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-18 17:03:33,367 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-18 17:03:33,367 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-18 17:03:33,368 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-18 17:03:33,369 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-18 17:03:33,369 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_6927db1b-4eaa-477c-a665-46bbf54692a2/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2018-11-18 17:03:33,378 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-18 17:03:33,378 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-18 17:03:33,379 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-18 17:03:33,379 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-11-18 17:03:33,379 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-18 17:03:33,380 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-18 17:03:33,380 INFO L133 SettingsManager]: * Use SBE=true [2018-11-18 17:03:33,380 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-18 17:03:33,380 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-18 17:03:33,380 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-18 17:03:33,380 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-18 17:03:33,380 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-18 17:03:33,380 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-18 17:03:33,381 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-18 17:03:33,381 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-18 17:03:33,381 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-18 17:03:33,381 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-18 17:03:33,381 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-18 17:03:33,381 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-18 17:03:33,381 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-18 17:03:33,382 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-18 17:03:33,382 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-18 17:03:33,382 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-18 17:03:33,382 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-18 17:03:33,382 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-18 17:03:33,382 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-18 17:03:33,382 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-18 17:03:33,382 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-18 17:03:33,383 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-18 17:03:33,383 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-18 17:03:33,383 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_6927db1b-4eaa-477c-a665-46bbf54692a2/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 133c91eb4ca703e3ebf3582d43ed0be6dbefca67 [2018-11-18 17:03:33,405 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-18 17:03:33,414 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-18 17:03:33,416 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-18 17:03:33,417 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-18 17:03:33,417 INFO L276 PluginConnector]: CDTParser initialized [2018-11-18 17:03:33,418 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_6927db1b-4eaa-477c-a665-46bbf54692a2/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/toy1_false-unreach-call_false-termination.cil.c [2018-11-18 17:03:33,453 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_6927db1b-4eaa-477c-a665-46bbf54692a2/bin-2019/uautomizer/data/ba0c897a6/5d6ec0e20c9d4daab54a0abc172d99c4/FLAG6584908a0 [2018-11-18 17:03:33,869 INFO L307 CDTParser]: Found 1 translation units. [2018-11-18 17:03:33,870 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_6927db1b-4eaa-477c-a665-46bbf54692a2/sv-benchmarks/c/systemc/toy1_false-unreach-call_false-termination.cil.c [2018-11-18 17:03:33,877 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_6927db1b-4eaa-477c-a665-46bbf54692a2/bin-2019/uautomizer/data/ba0c897a6/5d6ec0e20c9d4daab54a0abc172d99c4/FLAG6584908a0 [2018-11-18 17:03:33,887 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_6927db1b-4eaa-477c-a665-46bbf54692a2/bin-2019/uautomizer/data/ba0c897a6/5d6ec0e20c9d4daab54a0abc172d99c4 [2018-11-18 17:03:33,889 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-18 17:03:33,890 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-11-18 17:03:33,890 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-18 17:03:33,890 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-18 17:03:33,893 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-18 17:03:33,893 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 05:03:33" (1/1) ... [2018-11-18 17:03:33,895 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4959e04 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 05:03:33, skipping insertion in model container [2018-11-18 17:03:33,895 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 05:03:33" (1/1) ... [2018-11-18 17:03:33,902 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-18 17:03:33,928 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-18 17:03:34,075 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 17:03:34,079 INFO L191 MainTranslator]: Completed pre-run [2018-11-18 17:03:34,116 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 17:03:34,128 INFO L195 MainTranslator]: Completed translation [2018-11-18 17:03:34,128 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 05:03:34 WrapperNode [2018-11-18 17:03:34,128 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-18 17:03:34,128 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-18 17:03:34,128 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-18 17:03:34,128 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-18 17:03:34,136 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 05:03:34" (1/1) ... [2018-11-18 17:03:34,137 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 05:03:34" (1/1) ... [2018-11-18 17:03:34,142 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 05:03:34" (1/1) ... [2018-11-18 17:03:34,143 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 05:03:34" (1/1) ... [2018-11-18 17:03:34,148 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 05:03:34" (1/1) ... [2018-11-18 17:03:34,194 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 05:03:34" (1/1) ... [2018-11-18 17:03:34,196 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 05:03:34" (1/1) ... [2018-11-18 17:03:34,199 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-18 17:03:34,199 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-18 17:03:34,200 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-18 17:03:34,200 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-18 17:03:34,200 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 05:03:34" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6927db1b-4eaa-477c-a665-46bbf54692a2/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-18 17:03:34,232 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-18 17:03:34,232 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-18 17:03:34,232 INFO L138 BoogieDeclarations]: Found implementation of procedure error [2018-11-18 17:03:34,233 INFO L138 BoogieDeclarations]: Found implementation of procedure write_loop [2018-11-18 17:03:34,233 INFO L138 BoogieDeclarations]: Found implementation of procedure compute1 [2018-11-18 17:03:34,233 INFO L138 BoogieDeclarations]: Found implementation of procedure compute2 [2018-11-18 17:03:34,233 INFO L138 BoogieDeclarations]: Found implementation of procedure write_back [2018-11-18 17:03:34,233 INFO L138 BoogieDeclarations]: Found implementation of procedure read [2018-11-18 17:03:34,233 INFO L138 BoogieDeclarations]: Found implementation of procedure eval [2018-11-18 17:03:34,233 INFO L138 BoogieDeclarations]: Found implementation of procedure start_simulation [2018-11-18 17:03:34,233 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-18 17:03:34,233 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-11-18 17:03:34,233 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-11-18 17:03:34,233 INFO L130 BoogieDeclarations]: Found specification of procedure error [2018-11-18 17:03:34,233 INFO L130 BoogieDeclarations]: Found specification of procedure write_loop [2018-11-18 17:03:34,234 INFO L130 BoogieDeclarations]: Found specification of procedure compute1 [2018-11-18 17:03:34,234 INFO L130 BoogieDeclarations]: Found specification of procedure compute2 [2018-11-18 17:03:34,234 INFO L130 BoogieDeclarations]: Found specification of procedure write_back [2018-11-18 17:03:34,234 INFO L130 BoogieDeclarations]: Found specification of procedure read [2018-11-18 17:03:34,234 INFO L130 BoogieDeclarations]: Found specification of procedure eval [2018-11-18 17:03:34,234 INFO L130 BoogieDeclarations]: Found specification of procedure start_simulation [2018-11-18 17:03:34,234 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-18 17:03:34,234 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-18 17:03:34,234 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-18 17:03:34,621 INFO L278 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-18 17:03:34,621 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 05:03:34 BoogieIcfgContainer [2018-11-18 17:03:34,622 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-18 17:03:34,622 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-18 17:03:34,622 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-18 17:03:34,625 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-18 17:03:34,625 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 18.11 05:03:33" (1/3) ... [2018-11-18 17:03:34,626 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6c5baf30 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 18.11 05:03:34, skipping insertion in model container [2018-11-18 17:03:34,626 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 05:03:34" (2/3) ... [2018-11-18 17:03:34,626 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6c5baf30 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 18.11 05:03:34, skipping insertion in model container [2018-11-18 17:03:34,626 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 05:03:34" (3/3) ... [2018-11-18 17:03:34,627 INFO L112 eAbstractionObserver]: Analyzing ICFG toy1_false-unreach-call_false-termination.cil.c [2018-11-18 17:03:34,633 INFO L136 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-18 17:03:34,638 INFO L148 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-18 17:03:34,647 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-18 17:03:34,665 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-18 17:03:34,665 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-18 17:03:34,665 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-18 17:03:34,666 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-18 17:03:34,666 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-18 17:03:34,666 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-18 17:03:34,666 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-18 17:03:34,666 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-18 17:03:34,666 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-18 17:03:34,678 INFO L276 IsEmpty]: Start isEmpty. Operand 167 states. [2018-11-18 17:03:34,683 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-11-18 17:03:34,683 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 17:03:34,684 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 17:03:34,685 INFO L423 AbstractCegarLoop]: === Iteration 1 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 17:03:34,688 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 17:03:34,688 INFO L82 PathProgramCache]: Analyzing trace with hash 359976703, now seen corresponding path program 1 times [2018-11-18 17:03:34,689 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 17:03:34,690 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 17:03:34,719 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:34,720 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 17:03:34,720 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:34,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 17:03:34,889 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 17:03:34,891 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 17:03:34,892 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-18 17:03:34,896 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-18 17:03:34,905 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-18 17:03:34,906 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-18 17:03:34,907 INFO L87 Difference]: Start difference. First operand 167 states. Second operand 4 states. [2018-11-18 17:03:35,153 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 17:03:35,153 INFO L93 Difference]: Finished difference Result 465 states and 792 transitions. [2018-11-18 17:03:35,153 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-18 17:03:35,154 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 49 [2018-11-18 17:03:35,154 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 17:03:35,165 INFO L225 Difference]: With dead ends: 465 [2018-11-18 17:03:35,165 INFO L226 Difference]: Without dead ends: 301 [2018-11-18 17:03:35,169 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-18 17:03:35,181 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 301 states. [2018-11-18 17:03:35,222 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 301 to 290. [2018-11-18 17:03:35,222 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 290 states. [2018-11-18 17:03:35,225 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 290 states to 290 states and 468 transitions. [2018-11-18 17:03:35,226 INFO L78 Accepts]: Start accepts. Automaton has 290 states and 468 transitions. Word has length 49 [2018-11-18 17:03:35,226 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 17:03:35,227 INFO L480 AbstractCegarLoop]: Abstraction has 290 states and 468 transitions. [2018-11-18 17:03:35,227 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-18 17:03:35,227 INFO L276 IsEmpty]: Start isEmpty. Operand 290 states and 468 transitions. [2018-11-18 17:03:35,230 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-11-18 17:03:35,230 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 17:03:35,230 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 17:03:35,230 INFO L423 AbstractCegarLoop]: === Iteration 2 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 17:03:35,230 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 17:03:35,231 INFO L82 PathProgramCache]: Analyzing trace with hash -209269185, now seen corresponding path program 1 times [2018-11-18 17:03:35,231 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 17:03:35,231 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 17:03:35,232 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:35,232 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 17:03:35,232 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:35,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 17:03:35,308 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 17:03:35,308 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 17:03:35,308 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-18 17:03:35,310 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-18 17:03:35,310 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-18 17:03:35,310 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-18 17:03:35,310 INFO L87 Difference]: Start difference. First operand 290 states and 468 transitions. Second operand 4 states. [2018-11-18 17:03:35,521 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 17:03:35,521 INFO L93 Difference]: Finished difference Result 768 states and 1237 transitions. [2018-11-18 17:03:35,522 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 17:03:35,522 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 49 [2018-11-18 17:03:35,522 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 17:03:35,526 INFO L225 Difference]: With dead ends: 768 [2018-11-18 17:03:35,526 INFO L226 Difference]: Without dead ends: 504 [2018-11-18 17:03:35,528 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-18 17:03:35,528 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 504 states. [2018-11-18 17:03:35,562 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 504 to 493. [2018-11-18 17:03:35,562 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 493 states. [2018-11-18 17:03:35,565 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 493 states to 493 states and 790 transitions. [2018-11-18 17:03:35,565 INFO L78 Accepts]: Start accepts. Automaton has 493 states and 790 transitions. Word has length 49 [2018-11-18 17:03:35,566 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 17:03:35,566 INFO L480 AbstractCegarLoop]: Abstraction has 493 states and 790 transitions. [2018-11-18 17:03:35,566 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-18 17:03:35,566 INFO L276 IsEmpty]: Start isEmpty. Operand 493 states and 790 transitions. [2018-11-18 17:03:35,567 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-11-18 17:03:35,568 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 17:03:35,568 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 17:03:35,568 INFO L423 AbstractCegarLoop]: === Iteration 3 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 17:03:35,568 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 17:03:35,568 INFO L82 PathProgramCache]: Analyzing trace with hash 1841714813, now seen corresponding path program 1 times [2018-11-18 17:03:35,569 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 17:03:35,569 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 17:03:35,570 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:35,570 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 17:03:35,570 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:35,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 17:03:35,614 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 17:03:35,615 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 17:03:35,615 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-18 17:03:35,615 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-18 17:03:35,616 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-18 17:03:35,616 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-18 17:03:35,616 INFO L87 Difference]: Start difference. First operand 493 states and 790 transitions. Second operand 4 states. [2018-11-18 17:03:35,773 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 17:03:35,773 INFO L93 Difference]: Finished difference Result 1361 states and 2187 transitions. [2018-11-18 17:03:35,773 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 17:03:35,773 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 49 [2018-11-18 17:03:35,774 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 17:03:35,777 INFO L225 Difference]: With dead ends: 1361 [2018-11-18 17:03:35,777 INFO L226 Difference]: Without dead ends: 896 [2018-11-18 17:03:35,779 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-18 17:03:35,780 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 896 states. [2018-11-18 17:03:35,816 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 896 to 877. [2018-11-18 17:03:35,816 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 877 states. [2018-11-18 17:03:35,820 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 877 states to 877 states and 1404 transitions. [2018-11-18 17:03:35,820 INFO L78 Accepts]: Start accepts. Automaton has 877 states and 1404 transitions. Word has length 49 [2018-11-18 17:03:35,821 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 17:03:35,821 INFO L480 AbstractCegarLoop]: Abstraction has 877 states and 1404 transitions. [2018-11-18 17:03:35,821 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-18 17:03:35,821 INFO L276 IsEmpty]: Start isEmpty. Operand 877 states and 1404 transitions. [2018-11-18 17:03:35,823 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-11-18 17:03:35,823 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 17:03:35,824 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 17:03:35,824 INFO L423 AbstractCegarLoop]: === Iteration 4 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 17:03:35,824 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 17:03:35,824 INFO L82 PathProgramCache]: Analyzing trace with hash 1769328255, now seen corresponding path program 1 times [2018-11-18 17:03:35,824 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 17:03:35,825 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 17:03:35,825 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:35,825 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 17:03:35,826 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:35,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 17:03:35,888 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 17:03:35,888 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 17:03:35,888 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 17:03:35,889 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 17:03:35,889 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 17:03:35,889 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 17:03:35,889 INFO L87 Difference]: Start difference. First operand 877 states and 1404 transitions. Second operand 3 states. [2018-11-18 17:03:35,964 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 17:03:35,964 INFO L93 Difference]: Finished difference Result 2296 states and 3650 transitions. [2018-11-18 17:03:35,964 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 17:03:35,965 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 49 [2018-11-18 17:03:35,965 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 17:03:35,969 INFO L225 Difference]: With dead ends: 2296 [2018-11-18 17:03:35,970 INFO L226 Difference]: Without dead ends: 1451 [2018-11-18 17:03:35,972 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 17:03:35,973 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1451 states. [2018-11-18 17:03:36,011 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1451 to 1439. [2018-11-18 17:03:36,011 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1439 states. [2018-11-18 17:03:36,016 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1439 states to 1439 states and 2272 transitions. [2018-11-18 17:03:36,016 INFO L78 Accepts]: Start accepts. Automaton has 1439 states and 2272 transitions. Word has length 49 [2018-11-18 17:03:36,017 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 17:03:36,017 INFO L480 AbstractCegarLoop]: Abstraction has 1439 states and 2272 transitions. [2018-11-18 17:03:36,017 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 17:03:36,017 INFO L276 IsEmpty]: Start isEmpty. Operand 1439 states and 2272 transitions. [2018-11-18 17:03:36,019 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-11-18 17:03:36,019 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 17:03:36,020 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 17:03:36,020 INFO L423 AbstractCegarLoop]: === Iteration 5 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 17:03:36,020 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 17:03:36,020 INFO L82 PathProgramCache]: Analyzing trace with hash -1824039167, now seen corresponding path program 1 times [2018-11-18 17:03:36,020 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 17:03:36,021 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 17:03:36,021 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:36,021 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 17:03:36,022 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:36,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 17:03:36,080 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 17:03:36,080 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 17:03:36,080 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 17:03:36,080 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 17:03:36,080 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 17:03:36,081 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 17:03:36,081 INFO L87 Difference]: Start difference. First operand 1439 states and 2272 transitions. Second operand 3 states. [2018-11-18 17:03:36,244 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 17:03:36,245 INFO L93 Difference]: Finished difference Result 3876 states and 6291 transitions. [2018-11-18 17:03:36,246 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 17:03:36,246 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 49 [2018-11-18 17:03:36,246 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 17:03:36,255 INFO L225 Difference]: With dead ends: 3876 [2018-11-18 17:03:36,255 INFO L226 Difference]: Without dead ends: 2471 [2018-11-18 17:03:36,260 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 17:03:36,262 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2471 states. [2018-11-18 17:03:36,348 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2471 to 2451. [2018-11-18 17:03:36,348 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2451 states. [2018-11-18 17:03:36,361 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2451 states to 2451 states and 3922 transitions. [2018-11-18 17:03:36,361 INFO L78 Accepts]: Start accepts. Automaton has 2451 states and 3922 transitions. Word has length 49 [2018-11-18 17:03:36,362 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 17:03:36,362 INFO L480 AbstractCegarLoop]: Abstraction has 2451 states and 3922 transitions. [2018-11-18 17:03:36,362 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 17:03:36,362 INFO L276 IsEmpty]: Start isEmpty. Operand 2451 states and 3922 transitions. [2018-11-18 17:03:36,363 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-11-18 17:03:36,364 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 17:03:36,364 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 17:03:36,364 INFO L423 AbstractCegarLoop]: === Iteration 6 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 17:03:36,364 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 17:03:36,364 INFO L82 PathProgramCache]: Analyzing trace with hash 1459284106, now seen corresponding path program 1 times [2018-11-18 17:03:36,364 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 17:03:36,364 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 17:03:36,367 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:36,367 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 17:03:36,367 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:36,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 17:03:36,436 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 17:03:36,437 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 17:03:36,437 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-18 17:03:36,437 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-18 17:03:36,437 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-18 17:03:36,437 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-18 17:03:36,438 INFO L87 Difference]: Start difference. First operand 2451 states and 3922 transitions. Second operand 4 states. [2018-11-18 17:03:36,621 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 17:03:36,621 INFO L93 Difference]: Finished difference Result 5218 states and 8354 transitions. [2018-11-18 17:03:36,622 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 17:03:36,622 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 49 [2018-11-18 17:03:36,622 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 17:03:36,634 INFO L225 Difference]: With dead ends: 5218 [2018-11-18 17:03:36,634 INFO L226 Difference]: Without dead ends: 2820 [2018-11-18 17:03:36,642 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-18 17:03:36,645 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2820 states. [2018-11-18 17:03:36,752 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2820 to 2796. [2018-11-18 17:03:36,752 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2796 states. [2018-11-18 17:03:36,766 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2796 states to 2796 states and 4448 transitions. [2018-11-18 17:03:36,766 INFO L78 Accepts]: Start accepts. Automaton has 2796 states and 4448 transitions. Word has length 49 [2018-11-18 17:03:36,767 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 17:03:36,767 INFO L480 AbstractCegarLoop]: Abstraction has 2796 states and 4448 transitions. [2018-11-18 17:03:36,767 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-18 17:03:36,767 INFO L276 IsEmpty]: Start isEmpty. Operand 2796 states and 4448 transitions. [2018-11-18 17:03:36,768 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-11-18 17:03:36,769 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 17:03:36,769 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 17:03:36,769 INFO L423 AbstractCegarLoop]: === Iteration 7 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 17:03:36,769 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 17:03:36,769 INFO L82 PathProgramCache]: Analyzing trace with hash 1747972426, now seen corresponding path program 1 times [2018-11-18 17:03:36,769 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 17:03:36,769 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 17:03:36,770 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:36,770 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 17:03:36,770 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:36,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 17:03:36,801 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 17:03:36,802 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 17:03:36,802 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-18 17:03:36,802 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-18 17:03:36,802 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-18 17:03:36,802 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-18 17:03:36,802 INFO L87 Difference]: Start difference. First operand 2796 states and 4448 transitions. Second operand 4 states. [2018-11-18 17:03:37,093 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 17:03:37,093 INFO L93 Difference]: Finished difference Result 5590 states and 9012 transitions. [2018-11-18 17:03:37,094 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-18 17:03:37,094 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 49 [2018-11-18 17:03:37,094 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 17:03:37,105 INFO L225 Difference]: With dead ends: 5590 [2018-11-18 17:03:37,105 INFO L226 Difference]: Without dead ends: 2836 [2018-11-18 17:03:37,116 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-18 17:03:37,118 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2836 states. [2018-11-18 17:03:37,230 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2836 to 2800. [2018-11-18 17:03:37,230 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2800 states. [2018-11-18 17:03:37,241 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2800 states to 2800 states and 4384 transitions. [2018-11-18 17:03:37,242 INFO L78 Accepts]: Start accepts. Automaton has 2800 states and 4384 transitions. Word has length 49 [2018-11-18 17:03:37,242 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 17:03:37,243 INFO L480 AbstractCegarLoop]: Abstraction has 2800 states and 4384 transitions. [2018-11-18 17:03:37,243 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-18 17:03:37,243 INFO L276 IsEmpty]: Start isEmpty. Operand 2800 states and 4384 transitions. [2018-11-18 17:03:37,244 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-11-18 17:03:37,244 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 17:03:37,244 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 17:03:37,245 INFO L423 AbstractCegarLoop]: === Iteration 8 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 17:03:37,245 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 17:03:37,245 INFO L82 PathProgramCache]: Analyzing trace with hash -57465908, now seen corresponding path program 1 times [2018-11-18 17:03:37,245 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 17:03:37,245 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 17:03:37,246 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:37,246 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 17:03:37,246 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:37,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 17:03:37,308 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 17:03:37,308 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 17:03:37,308 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-18 17:03:37,309 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-18 17:03:37,309 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-18 17:03:37,309 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-18 17:03:37,309 INFO L87 Difference]: Start difference. First operand 2800 states and 4384 transitions. Second operand 4 states. [2018-11-18 17:03:37,593 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 17:03:37,594 INFO L93 Difference]: Finished difference Result 6272 states and 9828 transitions. [2018-11-18 17:03:37,594 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-18 17:03:37,594 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 49 [2018-11-18 17:03:37,594 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 17:03:37,608 INFO L225 Difference]: With dead ends: 6272 [2018-11-18 17:03:37,608 INFO L226 Difference]: Without dead ends: 3522 [2018-11-18 17:03:37,618 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-18 17:03:37,620 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3522 states. [2018-11-18 17:03:37,758 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3522 to 3482. [2018-11-18 17:03:37,758 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3482 states. [2018-11-18 17:03:37,768 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3482 states to 3482 states and 5426 transitions. [2018-11-18 17:03:37,769 INFO L78 Accepts]: Start accepts. Automaton has 3482 states and 5426 transitions. Word has length 49 [2018-11-18 17:03:37,769 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 17:03:37,769 INFO L480 AbstractCegarLoop]: Abstraction has 3482 states and 5426 transitions. [2018-11-18 17:03:37,769 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-18 17:03:37,769 INFO L276 IsEmpty]: Start isEmpty. Operand 3482 states and 5426 transitions. [2018-11-18 17:03:37,770 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-11-18 17:03:37,770 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 17:03:37,770 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 17:03:37,770 INFO L423 AbstractCegarLoop]: === Iteration 9 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 17:03:37,770 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 17:03:37,770 INFO L82 PathProgramCache]: Analyzing trace with hash 161388810, now seen corresponding path program 1 times [2018-11-18 17:03:37,771 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 17:03:37,771 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 17:03:37,771 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:37,771 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 17:03:37,771 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:37,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 17:03:37,820 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 17:03:37,820 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 17:03:37,821 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 17:03:37,821 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 17:03:37,821 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 17:03:37,821 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 17:03:37,821 INFO L87 Difference]: Start difference. First operand 3482 states and 5426 transitions. Second operand 3 states. [2018-11-18 17:03:37,969 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 17:03:37,970 INFO L93 Difference]: Finished difference Result 7213 states and 11390 transitions. [2018-11-18 17:03:37,970 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 17:03:37,970 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 49 [2018-11-18 17:03:37,971 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 17:03:37,986 INFO L225 Difference]: With dead ends: 7213 [2018-11-18 17:03:37,986 INFO L226 Difference]: Without dead ends: 3797 [2018-11-18 17:03:38,002 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 17:03:38,004 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3797 states. [2018-11-18 17:03:38,148 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3797 to 3797. [2018-11-18 17:03:38,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3797 states. [2018-11-18 17:03:38,158 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3797 states to 3797 states and 5819 transitions. [2018-11-18 17:03:38,159 INFO L78 Accepts]: Start accepts. Automaton has 3797 states and 5819 transitions. Word has length 49 [2018-11-18 17:03:38,159 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 17:03:38,160 INFO L480 AbstractCegarLoop]: Abstraction has 3797 states and 5819 transitions. [2018-11-18 17:03:38,160 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 17:03:38,160 INFO L276 IsEmpty]: Start isEmpty. Operand 3797 states and 5819 transitions. [2018-11-18 17:03:38,160 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-11-18 17:03:38,161 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 17:03:38,161 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 17:03:38,161 INFO L423 AbstractCegarLoop]: === Iteration 10 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 17:03:38,161 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 17:03:38,161 INFO L82 PathProgramCache]: Analyzing trace with hash -656259640, now seen corresponding path program 1 times [2018-11-18 17:03:38,161 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 17:03:38,161 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 17:03:38,162 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:38,162 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 17:03:38,162 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:38,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 17:03:38,190 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 17:03:38,190 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 17:03:38,190 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 17:03:38,190 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 17:03:38,190 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 17:03:38,190 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 17:03:38,191 INFO L87 Difference]: Start difference. First operand 3797 states and 5819 transitions. Second operand 3 states. [2018-11-18 17:03:38,393 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 17:03:38,393 INFO L93 Difference]: Finished difference Result 8172 states and 12801 transitions. [2018-11-18 17:03:38,394 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 17:03:38,394 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 49 [2018-11-18 17:03:38,394 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 17:03:38,413 INFO L225 Difference]: With dead ends: 8172 [2018-11-18 17:03:38,413 INFO L226 Difference]: Without dead ends: 4411 [2018-11-18 17:03:38,433 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 17:03:38,436 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4411 states. [2018-11-18 17:03:38,645 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4411 to 4311. [2018-11-18 17:03:38,645 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4311 states. [2018-11-18 17:03:38,653 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4311 states to 4311 states and 6534 transitions. [2018-11-18 17:03:38,654 INFO L78 Accepts]: Start accepts. Automaton has 4311 states and 6534 transitions. Word has length 49 [2018-11-18 17:03:38,654 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 17:03:38,655 INFO L480 AbstractCegarLoop]: Abstraction has 4311 states and 6534 transitions. [2018-11-18 17:03:38,655 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 17:03:38,655 INFO L276 IsEmpty]: Start isEmpty. Operand 4311 states and 6534 transitions. [2018-11-18 17:03:38,658 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-11-18 17:03:38,658 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 17:03:38,659 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 17:03:38,659 INFO L423 AbstractCegarLoop]: === Iteration 11 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 17:03:38,659 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 17:03:38,659 INFO L82 PathProgramCache]: Analyzing trace with hash -635363966, now seen corresponding path program 1 times [2018-11-18 17:03:38,659 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 17:03:38,659 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 17:03:38,660 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:38,660 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 17:03:38,660 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:38,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 17:03:38,729 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 21 proven. 7 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-11-18 17:03:38,729 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 17:03:38,729 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6927db1b-4eaa-477c-a665-46bbf54692a2/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 17:03:38,739 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 17:03:38,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 17:03:38,831 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 17:03:38,861 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 25 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-11-18 17:03:38,886 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-18 17:03:38,886 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [7] total 8 [2018-11-18 17:03:38,887 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-18 17:03:38,887 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-18 17:03:38,887 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-11-18 17:03:38,887 INFO L87 Difference]: Start difference. First operand 4311 states and 6534 transitions. Second operand 8 states. [2018-11-18 17:03:40,547 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 17:03:40,547 INFO L93 Difference]: Finished difference Result 14388 states and 23733 transitions. [2018-11-18 17:03:40,548 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-11-18 17:03:40,548 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 86 [2018-11-18 17:03:40,548 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 17:03:40,570 INFO L225 Difference]: With dead ends: 14388 [2018-11-18 17:03:40,571 INFO L226 Difference]: Without dead ends: 3674 [2018-11-18 17:03:40,665 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 120 GetRequests, 100 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 101 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=124, Invalid=338, Unknown=0, NotChecked=0, Total=462 [2018-11-18 17:03:40,668 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3674 states. [2018-11-18 17:03:40,821 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3674 to 2833. [2018-11-18 17:03:40,822 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2833 states. [2018-11-18 17:03:40,835 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2833 states to 2833 states and 4234 transitions. [2018-11-18 17:03:40,836 INFO L78 Accepts]: Start accepts. Automaton has 2833 states and 4234 transitions. Word has length 86 [2018-11-18 17:03:40,836 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 17:03:40,836 INFO L480 AbstractCegarLoop]: Abstraction has 2833 states and 4234 transitions. [2018-11-18 17:03:40,836 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-18 17:03:40,837 INFO L276 IsEmpty]: Start isEmpty. Operand 2833 states and 4234 transitions. [2018-11-18 17:03:40,844 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2018-11-18 17:03:40,844 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 17:03:40,844 INFO L375 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 17:03:40,844 INFO L423 AbstractCegarLoop]: === Iteration 12 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 17:03:40,845 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 17:03:40,845 INFO L82 PathProgramCache]: Analyzing trace with hash 1221244972, now seen corresponding path program 1 times [2018-11-18 17:03:40,845 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 17:03:40,845 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 17:03:40,846 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:40,846 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 17:03:40,846 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:40,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 17:03:40,917 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 38 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-11-18 17:03:40,917 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 17:03:40,917 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 17:03:40,917 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 17:03:40,918 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 17:03:40,918 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 17:03:40,918 INFO L87 Difference]: Start difference. First operand 2833 states and 4234 transitions. Second operand 3 states. [2018-11-18 17:03:41,128 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 17:03:41,128 INFO L93 Difference]: Finished difference Result 6546 states and 9872 transitions. [2018-11-18 17:03:41,128 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 17:03:41,128 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 129 [2018-11-18 17:03:41,129 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 17:03:41,144 INFO L225 Difference]: With dead ends: 6546 [2018-11-18 17:03:41,144 INFO L226 Difference]: Without dead ends: 3786 [2018-11-18 17:03:41,158 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 17:03:41,161 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3786 states. [2018-11-18 17:03:41,339 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3786 to 3582. [2018-11-18 17:03:41,339 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3582 states. [2018-11-18 17:03:41,350 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3582 states to 3582 states and 5115 transitions. [2018-11-18 17:03:41,351 INFO L78 Accepts]: Start accepts. Automaton has 3582 states and 5115 transitions. Word has length 129 [2018-11-18 17:03:41,351 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 17:03:41,351 INFO L480 AbstractCegarLoop]: Abstraction has 3582 states and 5115 transitions. [2018-11-18 17:03:41,351 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 17:03:41,351 INFO L276 IsEmpty]: Start isEmpty. Operand 3582 states and 5115 transitions. [2018-11-18 17:03:41,360 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 132 [2018-11-18 17:03:41,360 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 17:03:41,360 INFO L375 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 17:03:41,360 INFO L423 AbstractCegarLoop]: === Iteration 13 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 17:03:41,360 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 17:03:41,361 INFO L82 PathProgramCache]: Analyzing trace with hash -584093947, now seen corresponding path program 1 times [2018-11-18 17:03:41,361 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 17:03:41,361 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 17:03:41,361 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:41,361 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 17:03:41,362 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:41,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 17:03:41,431 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 32 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-11-18 17:03:41,431 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 17:03:41,431 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-18 17:03:41,432 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-18 17:03:41,432 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-18 17:03:41,432 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-18 17:03:41,432 INFO L87 Difference]: Start difference. First operand 3582 states and 5115 transitions. Second operand 4 states. [2018-11-18 17:03:42,072 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 17:03:42,072 INFO L93 Difference]: Finished difference Result 10045 states and 14435 transitions. [2018-11-18 17:03:42,073 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 17:03:42,073 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 131 [2018-11-18 17:03:42,074 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 17:03:42,107 INFO L225 Difference]: With dead ends: 10045 [2018-11-18 17:03:42,107 INFO L226 Difference]: Without dead ends: 6472 [2018-11-18 17:03:42,115 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-18 17:03:42,119 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6472 states. [2018-11-18 17:03:42,406 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6472 to 5991. [2018-11-18 17:03:42,406 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5991 states. [2018-11-18 17:03:42,424 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5991 states to 5991 states and 8614 transitions. [2018-11-18 17:03:42,425 INFO L78 Accepts]: Start accepts. Automaton has 5991 states and 8614 transitions. Word has length 131 [2018-11-18 17:03:42,426 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 17:03:42,426 INFO L480 AbstractCegarLoop]: Abstraction has 5991 states and 8614 transitions. [2018-11-18 17:03:42,426 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-18 17:03:42,426 INFO L276 IsEmpty]: Start isEmpty. Operand 5991 states and 8614 transitions. [2018-11-18 17:03:42,439 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-11-18 17:03:42,439 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 17:03:42,439 INFO L375 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 17:03:42,439 INFO L423 AbstractCegarLoop]: === Iteration 14 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 17:03:42,439 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 17:03:42,440 INFO L82 PathProgramCache]: Analyzing trace with hash -1666759494, now seen corresponding path program 1 times [2018-11-18 17:03:42,440 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 17:03:42,440 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 17:03:42,440 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:42,440 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 17:03:42,441 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:42,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 17:03:42,515 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 32 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-18 17:03:42,515 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 17:03:42,515 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6927db1b-4eaa-477c-a665-46bbf54692a2/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 17:03:42,527 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 17:03:42,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 17:03:42,628 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 17:03:42,650 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 36 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-18 17:03:42,675 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-18 17:03:42,675 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [5] total 6 [2018-11-18 17:03:42,675 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-18 17:03:42,676 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-18 17:03:42,676 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-18 17:03:42,676 INFO L87 Difference]: Start difference. First operand 5991 states and 8614 transitions. Second operand 6 states. [2018-11-18 17:03:43,563 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 17:03:43,563 INFO L93 Difference]: Finished difference Result 14988 states and 23043 transitions. [2018-11-18 17:03:43,564 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-18 17:03:43,564 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 141 [2018-11-18 17:03:43,564 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 17:03:43,603 INFO L225 Difference]: With dead ends: 14988 [2018-11-18 17:03:43,603 INFO L226 Difference]: Without dead ends: 9035 [2018-11-18 17:03:43,622 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 151 GetRequests, 145 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2018-11-18 17:03:43,629 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9035 states. [2018-11-18 17:03:44,070 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9035 to 8850. [2018-11-18 17:03:44,070 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8850 states. [2018-11-18 17:03:44,096 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8850 states to 8850 states and 12914 transitions. [2018-11-18 17:03:44,098 INFO L78 Accepts]: Start accepts. Automaton has 8850 states and 12914 transitions. Word has length 141 [2018-11-18 17:03:44,099 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 17:03:44,099 INFO L480 AbstractCegarLoop]: Abstraction has 8850 states and 12914 transitions. [2018-11-18 17:03:44,099 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-18 17:03:44,099 INFO L276 IsEmpty]: Start isEmpty. Operand 8850 states and 12914 transitions. [2018-11-18 17:03:44,116 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 156 [2018-11-18 17:03:44,116 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 17:03:44,116 INFO L375 BasicCegarLoop]: trace histogram [5, 5, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 17:03:44,117 INFO L423 AbstractCegarLoop]: === Iteration 15 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 17:03:44,117 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 17:03:44,117 INFO L82 PathProgramCache]: Analyzing trace with hash 576109116, now seen corresponding path program 1 times [2018-11-18 17:03:44,117 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 17:03:44,117 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 17:03:44,118 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:44,118 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 17:03:44,118 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:44,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 17:03:44,196 INFO L134 CoverageAnalysis]: Checked inductivity of 92 backedges. 45 proven. 0 refuted. 0 times theorem prover too weak. 47 trivial. 0 not checked. [2018-11-18 17:03:44,197 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 17:03:44,197 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-18 17:03:44,197 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-18 17:03:44,198 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-18 17:03:44,198 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-18 17:03:44,198 INFO L87 Difference]: Start difference. First operand 8850 states and 12914 transitions. Second operand 4 states. [2018-11-18 17:03:44,543 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 17:03:44,543 INFO L93 Difference]: Finished difference Result 13042 states and 19096 transitions. [2018-11-18 17:03:44,543 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 17:03:44,543 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 155 [2018-11-18 17:03:44,544 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 17:03:44,563 INFO L225 Difference]: With dead ends: 13042 [2018-11-18 17:03:44,563 INFO L226 Difference]: Without dead ends: 8904 [2018-11-18 17:03:44,571 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-18 17:03:44,576 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8904 states. [2018-11-18 17:03:44,854 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8904 to 8886. [2018-11-18 17:03:44,854 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8886 states. [2018-11-18 17:03:44,931 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8886 states to 8886 states and 12937 transitions. [2018-11-18 17:03:44,933 INFO L78 Accepts]: Start accepts. Automaton has 8886 states and 12937 transitions. Word has length 155 [2018-11-18 17:03:44,933 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 17:03:44,933 INFO L480 AbstractCegarLoop]: Abstraction has 8886 states and 12937 transitions. [2018-11-18 17:03:44,933 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-18 17:03:44,933 INFO L276 IsEmpty]: Start isEmpty. Operand 8886 states and 12937 transitions. [2018-11-18 17:03:44,943 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 160 [2018-11-18 17:03:44,943 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 17:03:44,944 INFO L375 BasicCegarLoop]: trace histogram [5, 5, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 17:03:44,944 INFO L423 AbstractCegarLoop]: === Iteration 16 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 17:03:44,944 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 17:03:44,944 INFO L82 PathProgramCache]: Analyzing trace with hash 1125661100, now seen corresponding path program 1 times [2018-11-18 17:03:44,944 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 17:03:44,944 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 17:03:44,945 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:44,945 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 17:03:44,945 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:44,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 17:03:44,984 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 49 proven. 0 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-11-18 17:03:44,984 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 17:03:44,984 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 17:03:44,985 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 17:03:44,985 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 17:03:44,985 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 17:03:44,985 INFO L87 Difference]: Start difference. First operand 8886 states and 12937 transitions. Second operand 3 states. [2018-11-18 17:03:45,320 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 17:03:45,320 INFO L93 Difference]: Finished difference Result 19111 states and 27950 transitions. [2018-11-18 17:03:45,321 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 17:03:45,321 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 159 [2018-11-18 17:03:45,321 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 17:03:45,345 INFO L225 Difference]: With dead ends: 19111 [2018-11-18 17:03:45,345 INFO L226 Difference]: Without dead ends: 10285 [2018-11-18 17:03:45,361 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 17:03:45,367 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10285 states. [2018-11-18 17:03:45,641 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10285 to 10281. [2018-11-18 17:03:45,641 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10281 states. [2018-11-18 17:03:45,658 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10281 states to 10281 states and 14412 transitions. [2018-11-18 17:03:45,660 INFO L78 Accepts]: Start accepts. Automaton has 10281 states and 14412 transitions. Word has length 159 [2018-11-18 17:03:45,660 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 17:03:45,660 INFO L480 AbstractCegarLoop]: Abstraction has 10281 states and 14412 transitions. [2018-11-18 17:03:45,660 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 17:03:45,660 INFO L276 IsEmpty]: Start isEmpty. Operand 10281 states and 14412 transitions. [2018-11-18 17:03:45,673 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 160 [2018-11-18 17:03:45,673 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 17:03:45,674 INFO L375 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 17:03:45,674 INFO L423 AbstractCegarLoop]: === Iteration 17 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 17:03:45,674 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 17:03:45,674 INFO L82 PathProgramCache]: Analyzing trace with hash -617866228, now seen corresponding path program 1 times [2018-11-18 17:03:45,674 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 17:03:45,674 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 17:03:45,675 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:45,675 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 17:03:45,675 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:45,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 17:03:45,758 INFO L134 CoverageAnalysis]: Checked inductivity of 79 backedges. 51 proven. 18 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-11-18 17:03:45,758 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 17:03:45,759 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6927db1b-4eaa-477c-a665-46bbf54692a2/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 17:03:45,765 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 17:03:45,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 17:03:45,903 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 17:03:45,925 INFO L134 CoverageAnalysis]: Checked inductivity of 79 backedges. 63 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-18 17:03:45,941 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-18 17:03:45,941 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [9] total 10 [2018-11-18 17:03:45,941 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-18 17:03:45,941 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-18 17:03:45,941 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2018-11-18 17:03:45,942 INFO L87 Difference]: Start difference. First operand 10281 states and 14412 transitions. Second operand 10 states. [2018-11-18 17:03:48,001 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 17:03:48,001 INFO L93 Difference]: Finished difference Result 31359 states and 46165 transitions. [2018-11-18 17:03:48,001 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-11-18 17:03:48,002 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 159 [2018-11-18 17:03:48,002 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 17:03:48,083 INFO L225 Difference]: With dead ends: 31359 [2018-11-18 17:03:48,084 INFO L226 Difference]: Without dead ends: 20349 [2018-11-18 17:03:48,125 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 184 GetRequests, 167 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 53 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=89, Invalid=253, Unknown=0, NotChecked=0, Total=342 [2018-11-18 17:03:48,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20349 states. [2018-11-18 17:03:48,854 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20349 to 16323. [2018-11-18 17:03:48,854 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16323 states. [2018-11-18 17:03:48,880 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16323 states to 16323 states and 23025 transitions. [2018-11-18 17:03:48,883 INFO L78 Accepts]: Start accepts. Automaton has 16323 states and 23025 transitions. Word has length 159 [2018-11-18 17:03:48,883 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 17:03:48,883 INFO L480 AbstractCegarLoop]: Abstraction has 16323 states and 23025 transitions. [2018-11-18 17:03:48,883 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-18 17:03:48,883 INFO L276 IsEmpty]: Start isEmpty. Operand 16323 states and 23025 transitions. [2018-11-18 17:03:48,898 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 165 [2018-11-18 17:03:48,898 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 17:03:48,898 INFO L375 BasicCegarLoop]: trace histogram [5, 5, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 17:03:48,899 INFO L423 AbstractCegarLoop]: === Iteration 18 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 17:03:48,899 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 17:03:48,899 INFO L82 PathProgramCache]: Analyzing trace with hash 1443570248, now seen corresponding path program 1 times [2018-11-18 17:03:48,899 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 17:03:48,899 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 17:03:48,900 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:48,900 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 17:03:48,900 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:48,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 17:03:48,962 INFO L134 CoverageAnalysis]: Checked inductivity of 92 backedges. 25 proven. 0 refuted. 0 times theorem prover too weak. 67 trivial. 0 not checked. [2018-11-18 17:03:48,962 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 17:03:48,962 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 17:03:48,963 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 17:03:48,963 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 17:03:48,963 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 17:03:48,963 INFO L87 Difference]: Start difference. First operand 16323 states and 23025 transitions. Second operand 3 states. [2018-11-18 17:03:49,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 17:03:49,419 INFO L93 Difference]: Finished difference Result 28663 states and 40695 transitions. [2018-11-18 17:03:49,419 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 17:03:49,419 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 164 [2018-11-18 17:03:49,420 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 17:03:49,469 INFO L225 Difference]: With dead ends: 28663 [2018-11-18 17:03:49,469 INFO L226 Difference]: Without dead ends: 14097 [2018-11-18 17:03:49,497 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 17:03:49,507 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14097 states. [2018-11-18 17:03:50,045 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14097 to 14097. [2018-11-18 17:03:50,045 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14097 states. [2018-11-18 17:03:50,067 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14097 states to 14097 states and 20065 transitions. [2018-11-18 17:03:50,069 INFO L78 Accepts]: Start accepts. Automaton has 14097 states and 20065 transitions. Word has length 164 [2018-11-18 17:03:50,070 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 17:03:50,070 INFO L480 AbstractCegarLoop]: Abstraction has 14097 states and 20065 transitions. [2018-11-18 17:03:50,070 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 17:03:50,070 INFO L276 IsEmpty]: Start isEmpty. Operand 14097 states and 20065 transitions. [2018-11-18 17:03:50,077 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 165 [2018-11-18 17:03:50,077 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 17:03:50,077 INFO L375 BasicCegarLoop]: trace histogram [5, 5, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 17:03:50,077 INFO L423 AbstractCegarLoop]: === Iteration 19 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 17:03:50,077 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 17:03:50,078 INFO L82 PathProgramCache]: Analyzing trace with hash 2054839306, now seen corresponding path program 1 times [2018-11-18 17:03:50,078 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 17:03:50,078 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 17:03:50,078 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:50,078 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 17:03:50,078 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:50,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 17:03:50,140 INFO L134 CoverageAnalysis]: Checked inductivity of 92 backedges. 25 proven. 0 refuted. 0 times theorem prover too weak. 67 trivial. 0 not checked. [2018-11-18 17:03:50,141 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 17:03:50,141 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 17:03:50,142 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 17:03:50,142 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 17:03:50,142 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 17:03:50,142 INFO L87 Difference]: Start difference. First operand 14097 states and 20065 transitions. Second operand 3 states. [2018-11-18 17:03:50,442 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 17:03:50,442 INFO L93 Difference]: Finished difference Result 21218 states and 30016 transitions. [2018-11-18 17:03:50,442 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 17:03:50,443 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 164 [2018-11-18 17:03:50,443 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 17:03:50,457 INFO L225 Difference]: With dead ends: 21218 [2018-11-18 17:03:50,457 INFO L226 Difference]: Without dead ends: 7158 [2018-11-18 17:03:50,473 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 17:03:50,477 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7158 states. [2018-11-18 17:03:50,671 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7158 to 7158. [2018-11-18 17:03:50,671 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7158 states. [2018-11-18 17:03:50,682 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7158 states to 7158 states and 9996 transitions. [2018-11-18 17:03:50,684 INFO L78 Accepts]: Start accepts. Automaton has 7158 states and 9996 transitions. Word has length 164 [2018-11-18 17:03:50,684 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 17:03:50,684 INFO L480 AbstractCegarLoop]: Abstraction has 7158 states and 9996 transitions. [2018-11-18 17:03:50,684 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 17:03:50,684 INFO L276 IsEmpty]: Start isEmpty. Operand 7158 states and 9996 transitions. [2018-11-18 17:03:50,688 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 173 [2018-11-18 17:03:50,688 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 17:03:50,688 INFO L375 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 17:03:50,688 INFO L423 AbstractCegarLoop]: === Iteration 20 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 17:03:50,689 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 17:03:50,689 INFO L82 PathProgramCache]: Analyzing trace with hash -229524030, now seen corresponding path program 1 times [2018-11-18 17:03:50,689 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 17:03:50,689 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 17:03:50,689 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:50,690 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 17:03:50,690 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:50,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 17:03:50,737 INFO L134 CoverageAnalysis]: Checked inductivity of 79 backedges. 55 proven. 4 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-11-18 17:03:50,737 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 17:03:50,737 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6927db1b-4eaa-477c-a665-46bbf54692a2/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 17:03:50,744 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 17:03:50,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 17:03:50,820 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 17:03:50,855 INFO L134 CoverageAnalysis]: Checked inductivity of 79 backedges. 63 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-11-18 17:03:50,871 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-18 17:03:50,871 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [4] total 5 [2018-11-18 17:03:50,872 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 17:03:50,872 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 17:03:50,872 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 17:03:50,872 INFO L87 Difference]: Start difference. First operand 7158 states and 9996 transitions. Second operand 5 states. [2018-11-18 17:03:51,628 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 17:03:51,628 INFO L93 Difference]: Finished difference Result 20384 states and 29018 transitions. [2018-11-18 17:03:51,629 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-18 17:03:51,629 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 172 [2018-11-18 17:03:51,629 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 17:03:51,649 INFO L225 Difference]: With dead ends: 20384 [2018-11-18 17:03:51,649 INFO L226 Difference]: Without dead ends: 12857 [2018-11-18 17:03:51,663 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 184 GetRequests, 177 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2018-11-18 17:03:51,669 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12857 states. [2018-11-18 17:03:52,032 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12857 to 12463. [2018-11-18 17:03:52,032 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12463 states. [2018-11-18 17:03:52,050 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12463 states to 12463 states and 16486 transitions. [2018-11-18 17:03:52,051 INFO L78 Accepts]: Start accepts. Automaton has 12463 states and 16486 transitions. Word has length 172 [2018-11-18 17:03:52,051 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 17:03:52,052 INFO L480 AbstractCegarLoop]: Abstraction has 12463 states and 16486 transitions. [2018-11-18 17:03:52,052 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 17:03:52,052 INFO L276 IsEmpty]: Start isEmpty. Operand 12463 states and 16486 transitions. [2018-11-18 17:03:52,057 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 174 [2018-11-18 17:03:52,057 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 17:03:52,057 INFO L375 BasicCegarLoop]: trace histogram [5, 5, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 17:03:52,057 INFO L423 AbstractCegarLoop]: === Iteration 21 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 17:03:52,057 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 17:03:52,057 INFO L82 PathProgramCache]: Analyzing trace with hash -126062305, now seen corresponding path program 1 times [2018-11-18 17:03:52,057 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 17:03:52,058 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 17:03:52,058 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:52,058 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 17:03:52,058 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:52,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 17:03:52,130 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 44 proven. 12 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2018-11-18 17:03:52,131 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 17:03:52,131 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6927db1b-4eaa-477c-a665-46bbf54692a2/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 17:03:52,138 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 17:03:52,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 17:03:52,221 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 17:03:52,243 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 63 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-11-18 17:03:52,259 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-18 17:03:52,259 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [5] total 6 [2018-11-18 17:03:52,259 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-18 17:03:52,259 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-18 17:03:52,259 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-18 17:03:52,260 INFO L87 Difference]: Start difference. First operand 12463 states and 16486 transitions. Second operand 6 states. [2018-11-18 17:03:53,094 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 17:03:53,094 INFO L93 Difference]: Finished difference Result 27988 states and 37481 transitions. [2018-11-18 17:03:53,094 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-18 17:03:53,094 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 173 [2018-11-18 17:03:53,095 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 17:03:53,118 INFO L225 Difference]: With dead ends: 27988 [2018-11-18 17:03:53,118 INFO L226 Difference]: Without dead ends: 15557 [2018-11-18 17:03:53,135 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 183 GetRequests, 177 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2018-11-18 17:03:53,143 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15557 states. [2018-11-18 17:03:53,604 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15557 to 15493. [2018-11-18 17:03:53,604 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15493 states. [2018-11-18 17:03:53,626 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15493 states to 15493 states and 19802 transitions. [2018-11-18 17:03:53,627 INFO L78 Accepts]: Start accepts. Automaton has 15493 states and 19802 transitions. Word has length 173 [2018-11-18 17:03:53,628 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 17:03:53,628 INFO L480 AbstractCegarLoop]: Abstraction has 15493 states and 19802 transitions. [2018-11-18 17:03:53,628 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-18 17:03:53,628 INFO L276 IsEmpty]: Start isEmpty. Operand 15493 states and 19802 transitions. [2018-11-18 17:03:53,632 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 177 [2018-11-18 17:03:53,632 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 17:03:53,632 INFO L375 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 17:03:53,632 INFO L423 AbstractCegarLoop]: === Iteration 22 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 17:03:53,632 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 17:03:53,632 INFO L82 PathProgramCache]: Analyzing trace with hash -1332504416, now seen corresponding path program 1 times [2018-11-18 17:03:53,633 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 17:03:53,633 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 17:03:53,633 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:53,633 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 17:03:53,633 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:53,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 17:03:53,710 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 42 proven. 0 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-11-18 17:03:53,710 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 17:03:53,710 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 17:03:53,711 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 17:03:53,712 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 17:03:53,712 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 17:03:53,712 INFO L87 Difference]: Start difference. First operand 15493 states and 19802 transitions. Second operand 3 states. [2018-11-18 17:03:54,231 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 17:03:54,231 INFO L93 Difference]: Finished difference Result 25709 states and 32804 transitions. [2018-11-18 17:03:54,232 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 17:03:54,232 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 176 [2018-11-18 17:03:54,232 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 17:03:54,254 INFO L225 Difference]: With dead ends: 25709 [2018-11-18 17:03:54,254 INFO L226 Difference]: Without dead ends: 13812 [2018-11-18 17:03:54,268 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 17:03:54,274 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13812 states. [2018-11-18 17:03:54,808 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13812 to 13805. [2018-11-18 17:03:54,808 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13805 states. [2018-11-18 17:03:54,823 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13805 states to 13805 states and 17441 transitions. [2018-11-18 17:03:54,825 INFO L78 Accepts]: Start accepts. Automaton has 13805 states and 17441 transitions. Word has length 176 [2018-11-18 17:03:54,825 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 17:03:54,825 INFO L480 AbstractCegarLoop]: Abstraction has 13805 states and 17441 transitions. [2018-11-18 17:03:54,825 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 17:03:54,825 INFO L276 IsEmpty]: Start isEmpty. Operand 13805 states and 17441 transitions. [2018-11-18 17:03:54,827 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 202 [2018-11-18 17:03:54,827 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 17:03:54,827 INFO L375 BasicCegarLoop]: trace histogram [5, 5, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 17:03:54,827 INFO L423 AbstractCegarLoop]: === Iteration 23 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 17:03:54,828 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 17:03:54,828 INFO L82 PathProgramCache]: Analyzing trace with hash -1547013108, now seen corresponding path program 1 times [2018-11-18 17:03:54,828 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 17:03:54,828 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 17:03:54,828 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:54,828 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 17:03:54,828 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:54,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 17:03:54,912 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 45 proven. 0 refuted. 0 times theorem prover too weak. 65 trivial. 0 not checked. [2018-11-18 17:03:54,913 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 17:03:54,913 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 17:03:54,913 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 17:03:54,913 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 17:03:54,913 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 17:03:54,913 INFO L87 Difference]: Start difference. First operand 13805 states and 17441 transitions. Second operand 5 states. [2018-11-18 17:03:55,310 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 17:03:55,310 INFO L93 Difference]: Finished difference Result 16557 states and 20741 transitions. [2018-11-18 17:03:55,311 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-18 17:03:55,311 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 201 [2018-11-18 17:03:55,311 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 17:03:55,318 INFO L225 Difference]: With dead ends: 16557 [2018-11-18 17:03:55,318 INFO L226 Difference]: Without dead ends: 4982 [2018-11-18 17:03:55,328 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 8 SyntacticMatches, 1 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-11-18 17:03:55,330 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4982 states. [2018-11-18 17:03:55,498 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4982 to 4505. [2018-11-18 17:03:55,498 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4505 states. [2018-11-18 17:03:55,502 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4505 states to 4505 states and 5292 transitions. [2018-11-18 17:03:55,503 INFO L78 Accepts]: Start accepts. Automaton has 4505 states and 5292 transitions. Word has length 201 [2018-11-18 17:03:55,503 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 17:03:55,503 INFO L480 AbstractCegarLoop]: Abstraction has 4505 states and 5292 transitions. [2018-11-18 17:03:55,503 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 17:03:55,503 INFO L276 IsEmpty]: Start isEmpty. Operand 4505 states and 5292 transitions. [2018-11-18 17:03:55,505 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 227 [2018-11-18 17:03:55,505 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 17:03:55,505 INFO L375 BasicCegarLoop]: trace histogram [6, 6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 17:03:55,505 INFO L423 AbstractCegarLoop]: === Iteration 24 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 17:03:55,506 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 17:03:55,506 INFO L82 PathProgramCache]: Analyzing trace with hash 1036488373, now seen corresponding path program 1 times [2018-11-18 17:03:55,506 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 17:03:55,506 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 17:03:55,506 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:55,506 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 17:03:55,506 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:55,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 17:03:55,569 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 55 proven. 0 refuted. 0 times theorem prover too weak. 89 trivial. 0 not checked. [2018-11-18 17:03:55,569 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 17:03:55,569 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 17:03:55,570 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 17:03:55,570 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 17:03:55,570 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 17:03:55,570 INFO L87 Difference]: Start difference. First operand 4505 states and 5292 transitions. Second operand 3 states. [2018-11-18 17:03:55,740 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 17:03:55,740 INFO L93 Difference]: Finished difference Result 5682 states and 6646 transitions. [2018-11-18 17:03:55,741 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 17:03:55,741 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 226 [2018-11-18 17:03:55,741 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 17:03:55,746 INFO L225 Difference]: With dead ends: 5682 [2018-11-18 17:03:55,746 INFO L226 Difference]: Without dead ends: 4482 [2018-11-18 17:03:55,748 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 17:03:55,749 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4482 states. [2018-11-18 17:03:55,887 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4482 to 4482. [2018-11-18 17:03:55,887 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4482 states. [2018-11-18 17:03:55,891 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4482 states to 4482 states and 5266 transitions. [2018-11-18 17:03:55,891 INFO L78 Accepts]: Start accepts. Automaton has 4482 states and 5266 transitions. Word has length 226 [2018-11-18 17:03:55,891 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 17:03:55,892 INFO L480 AbstractCegarLoop]: Abstraction has 4482 states and 5266 transitions. [2018-11-18 17:03:55,892 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 17:03:55,892 INFO L276 IsEmpty]: Start isEmpty. Operand 4482 states and 5266 transitions. [2018-11-18 17:03:55,893 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 227 [2018-11-18 17:03:55,893 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 17:03:55,894 INFO L375 BasicCegarLoop]: trace histogram [6, 6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 17:03:55,894 INFO L423 AbstractCegarLoop]: === Iteration 25 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 17:03:55,894 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 17:03:55,894 INFO L82 PathProgramCache]: Analyzing trace with hash 1038322739, now seen corresponding path program 1 times [2018-11-18 17:03:55,894 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 17:03:55,894 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 17:03:55,895 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:55,895 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 17:03:55,895 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:55,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 17:03:55,952 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-11-18 17:03:55,952 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 17:03:55,952 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 17:03:55,952 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 17:03:55,952 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 17:03:55,953 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 17:03:55,953 INFO L87 Difference]: Start difference. First operand 4482 states and 5266 transitions. Second operand 3 states. [2018-11-18 17:03:56,122 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 17:03:56,122 INFO L93 Difference]: Finished difference Result 4494 states and 5286 transitions. [2018-11-18 17:03:56,122 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 17:03:56,122 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 226 [2018-11-18 17:03:56,123 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 17:03:56,128 INFO L225 Difference]: With dead ends: 4494 [2018-11-18 17:03:56,128 INFO L226 Difference]: Without dead ends: 4491 [2018-11-18 17:03:56,129 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 17:03:56,131 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4491 states. [2018-11-18 17:03:56,281 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4491 to 4491. [2018-11-18 17:03:56,281 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4491 states. [2018-11-18 17:03:56,285 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4491 states to 4491 states and 5275 transitions. [2018-11-18 17:03:56,286 INFO L78 Accepts]: Start accepts. Automaton has 4491 states and 5275 transitions. Word has length 226 [2018-11-18 17:03:56,286 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 17:03:56,286 INFO L480 AbstractCegarLoop]: Abstraction has 4491 states and 5275 transitions. [2018-11-18 17:03:56,286 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 17:03:56,286 INFO L276 IsEmpty]: Start isEmpty. Operand 4491 states and 5275 transitions. [2018-11-18 17:03:56,289 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 227 [2018-11-18 17:03:56,289 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 17:03:56,289 INFO L375 BasicCegarLoop]: trace histogram [6, 6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 17:03:56,289 INFO L423 AbstractCegarLoop]: === Iteration 26 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 17:03:56,289 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 17:03:56,290 INFO L82 PathProgramCache]: Analyzing trace with hash 1038375532, now seen corresponding path program 1 times [2018-11-18 17:03:56,290 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 17:03:56,290 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 17:03:56,290 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:56,290 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 17:03:56,291 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:03:56,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 17:03:56,524 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 47 proven. 77 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-11-18 17:03:56,524 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 17:03:56,524 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6927db1b-4eaa-477c-a665-46bbf54692a2/bin-2019/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 17:03:56,530 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 17:03:56,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 17:03:56,642 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 17:03:56,725 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 84 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-11-18 17:03:56,741 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-18 17:03:56,741 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [16] total 20 [2018-11-18 17:03:56,742 INFO L459 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-11-18 17:03:56,742 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-11-18 17:03:56,742 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=340, Unknown=0, NotChecked=0, Total=380 [2018-11-18 17:03:56,742 INFO L87 Difference]: Start difference. First operand 4491 states and 5275 transitions. Second operand 20 states. [2018-11-18 17:04:04,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 17:04:04,263 INFO L93 Difference]: Finished difference Result 14762 states and 18129 transitions. [2018-11-18 17:04:04,263 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 136 states. [2018-11-18 17:04:04,264 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 226 [2018-11-18 17:04:04,264 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 17:04:04,280 INFO L225 Difference]: With dead ends: 14762 [2018-11-18 17:04:04,280 INFO L226 Difference]: Without dead ends: 11785 [2018-11-18 17:04:04,288 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 451 GetRequests, 299 SyntacticMatches, 1 SemanticMatches, 151 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8926 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=2271, Invalid=20985, Unknown=0, NotChecked=0, Total=23256 [2018-11-18 17:04:04,292 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11785 states. [2018-11-18 17:04:04,646 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11785 to 8604. [2018-11-18 17:04:04,646 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8604 states. [2018-11-18 17:04:04,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8604 states to 8604 states and 10234 transitions. [2018-11-18 17:04:04,656 INFO L78 Accepts]: Start accepts. Automaton has 8604 states and 10234 transitions. Word has length 226 [2018-11-18 17:04:04,656 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 17:04:04,656 INFO L480 AbstractCegarLoop]: Abstraction has 8604 states and 10234 transitions. [2018-11-18 17:04:04,657 INFO L481 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-11-18 17:04:04,657 INFO L276 IsEmpty]: Start isEmpty. Operand 8604 states and 10234 transitions. [2018-11-18 17:04:04,659 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 251 [2018-11-18 17:04:04,659 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 17:04:04,659 INFO L375 BasicCegarLoop]: trace histogram [6, 6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 17:04:04,659 INFO L423 AbstractCegarLoop]: === Iteration 27 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 17:04:04,660 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 17:04:04,660 INFO L82 PathProgramCache]: Analyzing trace with hash -1794556031, now seen corresponding path program 1 times [2018-11-18 17:04:04,660 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 17:04:04,660 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 17:04:04,660 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:04:04,661 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 17:04:04,661 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:04:04,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 17:04:04,895 INFO L134 CoverageAnalysis]: Checked inductivity of 153 backedges. 54 proven. 79 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-11-18 17:04:04,895 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 17:04:04,895 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_6927db1b-4eaa-477c-a665-46bbf54692a2/bin-2019/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 17:04:04,902 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 17:04:04,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 17:04:04,994 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 17:04:05,144 INFO L134 CoverageAnalysis]: Checked inductivity of 153 backedges. 116 proven. 18 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2018-11-18 17:04:05,170 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-18 17:04:05,170 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 15] total 22 [2018-11-18 17:04:05,171 INFO L459 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-11-18 17:04:05,171 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-11-18 17:04:05,171 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=52, Invalid=410, Unknown=0, NotChecked=0, Total=462 [2018-11-18 17:04:05,171 INFO L87 Difference]: Start difference. First operand 8604 states and 10234 transitions. Second operand 22 states. [2018-11-18 17:04:09,599 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 17:04:09,599 INFO L93 Difference]: Finished difference Result 18794 states and 22842 transitions. [2018-11-18 17:04:09,599 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 80 states. [2018-11-18 17:04:09,599 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 250 [2018-11-18 17:04:09,600 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 17:04:09,617 INFO L225 Difference]: With dead ends: 18794 [2018-11-18 17:04:09,617 INFO L226 Difference]: Without dead ends: 11875 [2018-11-18 17:04:09,627 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 409 GetRequests, 310 SyntacticMatches, 5 SemanticMatches, 94 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2818 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=939, Invalid=8181, Unknown=0, NotChecked=0, Total=9120 [2018-11-18 17:04:09,632 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11875 states. [2018-11-18 17:04:10,016 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11875 to 9117. [2018-11-18 17:04:10,016 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9117 states. [2018-11-18 17:04:10,026 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9117 states to 9117 states and 10822 transitions. [2018-11-18 17:04:10,027 INFO L78 Accepts]: Start accepts. Automaton has 9117 states and 10822 transitions. Word has length 250 [2018-11-18 17:04:10,027 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 17:04:10,027 INFO L480 AbstractCegarLoop]: Abstraction has 9117 states and 10822 transitions. [2018-11-18 17:04:10,027 INFO L481 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-11-18 17:04:10,027 INFO L276 IsEmpty]: Start isEmpty. Operand 9117 states and 10822 transitions. [2018-11-18 17:04:10,029 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 252 [2018-11-18 17:04:10,029 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 17:04:10,029 INFO L375 BasicCegarLoop]: trace histogram [6, 6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 17:04:10,030 INFO L423 AbstractCegarLoop]: === Iteration 28 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 17:04:10,030 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 17:04:10,030 INFO L82 PathProgramCache]: Analyzing trace with hash 202938263, now seen corresponding path program 1 times [2018-11-18 17:04:10,030 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 17:04:10,030 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 17:04:10,030 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:04:10,030 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 17:04:10,031 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 17:04:10,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 17:04:10,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 17:04:10,165 INFO L442 BasicCegarLoop]: Counterexample might be feasible [2018-11-18 17:04:10,312 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 18.11 05:04:10 BoogieIcfgContainer [2018-11-18 17:04:10,312 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-18 17:04:10,312 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-18 17:04:10,312 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-18 17:04:10,313 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-18 17:04:10,313 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 05:03:34" (3/4) ... [2018-11-18 17:04:10,315 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-11-18 17:04:10,466 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_6927db1b-4eaa-477c-a665-46bbf54692a2/bin-2019/uautomizer/witness.graphml [2018-11-18 17:04:10,466 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-18 17:04:10,467 INFO L168 Benchmark]: Toolchain (without parser) took 36577.90 ms. Allocated memory was 1.0 GB in the beginning and 3.3 GB in the end (delta: 2.2 GB). Free memory was 953.8 MB in the beginning and 1.8 GB in the end (delta: -877.2 MB). Peak memory consumption was 1.4 GB. Max. memory is 11.5 GB. [2018-11-18 17:04:10,468 INFO L168 Benchmark]: CDTParser took 0.12 ms. Allocated memory is still 1.0 GB. Free memory is still 980.1 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 17:04:10,468 INFO L168 Benchmark]: CACSL2BoogieTranslator took 237.93 ms. Allocated memory is still 1.0 GB. Free memory was 953.8 MB in the beginning and 935.0 MB in the end (delta: 18.8 MB). Peak memory consumption was 18.8 MB. Max. memory is 11.5 GB. [2018-11-18 17:04:10,468 INFO L168 Benchmark]: Boogie Preprocessor took 70.80 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 146.8 MB). Free memory was 935.0 MB in the beginning and 1.1 GB in the end (delta: -209.9 MB). Peak memory consumption was 15.2 MB. Max. memory is 11.5 GB. [2018-11-18 17:04:10,469 INFO L168 Benchmark]: RCFGBuilder took 422.25 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 49.9 MB). Peak memory consumption was 49.9 MB. Max. memory is 11.5 GB. [2018-11-18 17:04:10,469 INFO L168 Benchmark]: TraceAbstraction took 35689.97 ms. Allocated memory was 1.2 GB in the beginning and 3.3 GB in the end (delta: 2.1 GB). Free memory was 1.1 GB in the beginning and 1.9 GB in the end (delta: -782.1 MB). Peak memory consumption was 1.3 GB. Max. memory is 11.5 GB. [2018-11-18 17:04:10,469 INFO L168 Benchmark]: Witness Printer took 154.11 ms. Allocated memory is still 3.3 GB. Free memory was 1.9 GB in the beginning and 1.8 GB in the end (delta: 46.1 MB). Peak memory consumption was 46.1 MB. Max. memory is 11.5 GB. [2018-11-18 17:04:10,470 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.12 ms. Allocated memory is still 1.0 GB. Free memory is still 980.1 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 237.93 ms. Allocated memory is still 1.0 GB. Free memory was 953.8 MB in the beginning and 935.0 MB in the end (delta: 18.8 MB). Peak memory consumption was 18.8 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 70.80 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 146.8 MB). Free memory was 935.0 MB in the beginning and 1.1 GB in the end (delta: -209.9 MB). Peak memory consumption was 15.2 MB. Max. memory is 11.5 GB. * RCFGBuilder took 422.25 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 49.9 MB). Peak memory consumption was 49.9 MB. Max. memory is 11.5 GB. * TraceAbstraction took 35689.97 ms. Allocated memory was 1.2 GB in the beginning and 3.3 GB in the end (delta: 2.1 GB). Free memory was 1.1 GB in the beginning and 1.9 GB in the end (delta: -782.1 MB). Peak memory consumption was 1.3 GB. Max. memory is 11.5 GB. * Witness Printer took 154.11 ms. Allocated memory is still 3.3 GB. Free memory was 1.9 GB in the beginning and 1.8 GB in the end (delta: 46.1 MB). Peak memory consumption was 46.1 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 13]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L18] int c ; [L19] int c_t ; [L20] int c_req_up ; [L21] int p_in ; [L22] int p_out ; [L23] int wl_st ; [L24] int c1_st ; [L25] int c2_st ; [L26] int wb_st ; [L27] int r_st ; [L28] int wl_i ; [L29] int c1_i ; [L30] int c2_i ; [L31] int wb_i ; [L32] int r_i ; [L33] int wl_pc ; [L34] int c1_pc ; [L35] int c2_pc ; [L36] int wb_pc ; [L37] int e_e ; [L38] int e_f ; [L39] int e_g ; [L40] int e_c ; [L41] int e_p_in ; [L42] int e_wl ; [L48] int d ; [L49] int data ; [L50] int processed ; [L51] static int t_b ; VAL [\old(c)=17, \old(c1_i)=4, \old(c1_pc)=29, \old(c1_st)=24, \old(c2_i)=14, \old(c2_pc)=28, \old(c2_st)=25, \old(c_req_up)=30, \old(c_t)=20, \old(d)=23, \old(data)=18, \old(e_c)=11, \old(e_e)=31, \old(e_f)=21, \old(e_g)=10, \old(e_p_in)=8, \old(e_wl)=13, \old(p_in)=15, \old(p_out)=9, \old(processed)=16, \old(r_i)=26, \old(r_st)=7, \old(t_b)=12, \old(wb_i)=5, \old(wb_pc)=19, \old(wb_st)=3, \old(wl_i)=27, \old(wl_pc)=22, \old(wl_st)=6, c=0, c1_i=0, c1_pc=0, c1_st=0, c2_i=0, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=0, e_e=0, e_f=0, e_g=0, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=0, wb_pc=0, wb_st=0, wl_i=0, wl_pc=0, wl_st=0] [L691] int __retres1 ; [L695] e_wl = 2 [L696] e_c = e_wl [L697] e_g = e_c [L698] e_f = e_g [L699] e_e = e_f [L700] wl_pc = 0 [L701] c1_pc = 0 [L702] c2_pc = 0 [L703] wb_pc = 0 [L704] wb_i = 1 [L705] c2_i = wb_i [L706] c1_i = c2_i [L707] wl_i = c1_i [L708] r_i = 0 [L709] c_req_up = 0 [L710] d = 0 [L711] c = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=0, \old(e_e)=0, \old(e_f)=0, \old(e_g)=0, \old(e_wl)=0, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L712] CALL start_simulation() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L402] int kernel_st ; [L405] kernel_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L406] COND FALSE !((int )c_req_up == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L417] COND TRUE (int )wl_i == 1 [L418] wl_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L422] COND TRUE (int )c1_i == 1 [L423] c1_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L427] COND TRUE (int )c2_i == 1 [L428] c2_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L432] COND TRUE (int )wb_i == 1 [L433] wb_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L437] COND FALSE !((int )r_i == 1) [L440] r_st = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L442] COND FALSE !((int )e_f == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L447] COND FALSE !((int )e_g == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L452] COND FALSE !((int )e_e == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L457] COND FALSE !((int )e_c == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L462] COND FALSE !((int )e_wl == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L467] COND FALSE !((int )wl_pc == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L475] COND FALSE !((int )wl_pc == 2) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L485] COND FALSE !((int )c1_pc == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L494] COND FALSE !((int )c2_pc == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L503] COND FALSE !((int )wb_pc == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L512] COND FALSE !((int )e_c == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L517] COND FALSE !((int )e_e == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L522] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L527] COND FALSE !((int )e_g == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L532] COND FALSE !((int )e_c == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L537] COND FALSE !((int )e_wl == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L543] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L546] kernel_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L547] CALL eval() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L288] int tmp ; [L289] int tmp___0 ; [L290] int tmp___1 ; [L291] int tmp___2 ; [L292] int tmp___3 ; VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L296] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L298] COND TRUE (int )wl_st == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L319] COND TRUE (int )wl_st == 0 [L321] tmp = __VERIFIER_nondet_int() [L323] COND TRUE \read(tmp) [L325] wl_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L326] CALL write_loop() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=1, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L53] int t ; VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=1, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L56] COND TRUE (int )wl_pc == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=1, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L70] wl_st = 2 [L71] wl_pc = 1 [L72] RET e_wl = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=1, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L326] write_loop() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L334] COND TRUE (int )c1_st == 0 [L336] tmp___0 = __VERIFIER_nondet_int() [L338] COND TRUE \read(tmp___0) [L340] c1_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L341] CALL compute1() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L139] COND TRUE (int )c1_pc == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L150] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L152] c1_st = 2 [L153] RET c1_pc = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L341] compute1() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L349] COND TRUE (int )c2_st == 0 [L351] tmp___1 = __VERIFIER_nondet_int() [L353] COND TRUE \read(tmp___1) [L355] c2_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L356] CALL compute2() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L184] COND TRUE (int )c2_pc == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L195] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L197] c2_st = 2 [L198] RET c2_pc = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L356] compute2() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L364] COND TRUE (int )wb_st == 0 [L366] tmp___2 = __VERIFIER_nondet_int() [L368] COND TRUE \read(tmp___2) [L370] wb_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L371] CALL write_back() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L229] COND TRUE (int )wb_pc == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L240] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L242] wb_st = 2 [L243] RET wb_pc = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L371] write_back() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L379] COND FALSE !((int )r_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L296] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L298] COND FALSE !((int )wl_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L301] COND FALSE !((int )c1_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L304] COND FALSE !((int )c2_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L307] COND FALSE !((int )wb_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L310] COND FALSE, RET !((int )r_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L547] eval() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L549] kernel_st = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L550] COND FALSE !((int )c_req_up == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L561] kernel_st = 3 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L562] COND FALSE !((int )e_f == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L567] COND FALSE !((int )e_g == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L572] COND FALSE !((int )e_e == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L577] COND FALSE !((int )e_c == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L582] COND TRUE (int )e_wl == 0 [L583] e_wl = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L587] COND TRUE (int )wl_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L588] COND TRUE (int )e_wl == 1 [L589] wl_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L605] COND TRUE (int )c1_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L606] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L614] COND TRUE (int )c2_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L615] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L623] COND TRUE (int )wb_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L624] COND FALSE !((int )e_g == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L632] COND FALSE !((int )e_c == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L637] COND FALSE !((int )e_e == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L642] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L647] COND FALSE !((int )e_g == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L652] COND FALSE !((int )e_c == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L657] COND TRUE (int )e_wl == 1 [L658] e_wl = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L662] COND TRUE (int )wl_st == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L543] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L546] kernel_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L547] CALL eval() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L288] int tmp ; [L289] int tmp___0 ; [L290] int tmp___1 ; [L291] int tmp___2 ; [L292] int tmp___3 ; VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L296] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L298] COND TRUE (int )wl_st == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L319] COND TRUE (int )wl_st == 0 [L321] tmp = __VERIFIER_nondet_int() [L323] COND TRUE \read(tmp) [L325] wl_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L326] CALL write_loop() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L53] int t ; VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L56] COND FALSE !((int )wl_pc == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L59] COND FALSE !((int )wl_pc == 2) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L62] COND TRUE (int )wl_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L77] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L79] t = d [L80] data = d [L81] processed = 0 [L82] e_f = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L83] COND TRUE (int )c1_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L84] COND TRUE (int )e_f == 1 [L85] c1_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L92] COND TRUE (int )c2_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L93] COND TRUE (int )e_f == 1 [L94] c2_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L101] e_f = 2 [L102] wl_st = 2 [L103] wl_pc = 2 [L104] RET t_b = t VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=1, c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L326] write_loop() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L334] COND TRUE (int )c1_st == 0 [L336] tmp___0 = __VERIFIER_nondet_int() [L338] COND TRUE \read(tmp___0) [L340] c1_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L341] CALL compute1() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L139] COND FALSE !((int )c1_pc == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L142] COND TRUE (int )c1_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L157] COND TRUE ! processed [L158] data += 1 [L159] e_g = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L160] COND TRUE (int )wb_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L161] COND TRUE (int )e_g == 1 [L162] wb_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L169] e_g = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L150] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L152] c1_st = 2 [L153] RET c1_pc = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=1, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L341] compute1() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L349] COND TRUE (int )c2_st == 0 [L351] tmp___1 = __VERIFIER_nondet_int() [L353] COND TRUE \read(tmp___1) [L355] c2_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L356] CALL compute2() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L184] COND FALSE !((int )c2_pc == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L187] COND TRUE (int )c2_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L202] COND TRUE ! processed [L203] data += 1 [L204] e_g = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L205] COND TRUE (int )wb_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L206] COND TRUE (int )e_g == 1 [L207] wb_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L214] e_g = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L195] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L197] c2_st = 2 [L198] RET c2_pc = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=1, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=1, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L356] compute2() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L364] COND TRUE (int )wb_st == 0 [L366] tmp___2 = __VERIFIER_nondet_int() [L368] COND TRUE \read(tmp___2) [L370] wb_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L371] CALL write_back() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L229] COND FALSE !((int )wb_pc == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L232] COND TRUE (int )wb_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L247] c_t = data [L248] c_req_up = 1 [L249] processed = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L240] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L242] wb_st = 2 [L243] RET wb_pc = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=1, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L371] write_back() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L379] COND FALSE !((int )r_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L296] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L298] COND FALSE !((int )wl_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L301] COND FALSE !((int )c1_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L304] COND FALSE !((int )c2_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L307] COND FALSE !((int )wb_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L310] COND FALSE, RET !((int )r_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=2, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=1, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___0=1, tmp___1=1, tmp___2=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L547] eval() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=1, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L549] kernel_st = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L550] COND TRUE (int )c_req_up == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L551] COND TRUE c != c_t [L552] c = c_t [L553] e_c = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L557] c_req_up = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L561] kernel_st = 3 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L562] COND FALSE !((int )e_f == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L567] COND FALSE !((int )e_g == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L572] COND FALSE !((int )e_e == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L577] COND TRUE (int )e_c == 0 [L578] e_c = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L582] COND FALSE !((int )e_wl == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L587] COND FALSE !((int )wl_pc == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L595] COND TRUE (int )wl_pc == 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L596] COND FALSE !((int )e_e == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L605] COND TRUE (int )c1_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L606] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L614] COND TRUE (int )c2_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L615] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L623] COND TRUE (int )wb_pc == 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L624] COND FALSE !((int )e_g == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L632] COND TRUE (int )e_c == 1 [L633] r_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L637] COND FALSE !((int )e_e == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L642] COND FALSE !((int )e_f == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L647] COND FALSE !((int )e_g == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L652] COND TRUE (int )e_c == 1 [L653] e_c = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L657] COND FALSE !((int )e_wl == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L662] COND FALSE !((int )wl_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L665] COND FALSE !((int )c1_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L668] COND FALSE !((int )c2_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L671] COND FALSE !((int )wb_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L674] COND TRUE (int )r_st == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L543] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=3, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L546] kernel_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=0, \old(c1_st)=0, \old(c2_i)=0, \old(c2_pc)=0, \old(c2_st)=0, \old(c_req_up)=0, \old(c_t)=0, \old(d)=0, \old(data)=0, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=0, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=0, \old(wb_st)=0, \old(wl_i)=0, \old(wl_pc)=0, \old(wl_st)=0, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, kernel_st=1, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L547] CALL eval() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L288] int tmp ; [L289] int tmp___0 ; [L290] int tmp___1 ; [L291] int tmp___2 ; [L292] int tmp___3 ; VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L296] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L298] COND FALSE !((int )wl_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L301] COND FALSE !((int )c1_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L304] COND FALSE !((int )c2_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L307] COND FALSE !((int )wb_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L310] COND TRUE (int )r_st == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L319] COND FALSE !((int )wl_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L334] COND FALSE !((int )c1_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L349] COND FALSE !((int )c2_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L364] COND FALSE !((int )wb_st == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L379] COND TRUE (int )r_st == 0 [L381] tmp___3 = __VERIFIER_nondet_int() [L383] COND TRUE \read(tmp___3) [L385] r_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, tmp___3=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L386] CALL read() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=1, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L261] d = c [L262] e_e = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=1, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L263] COND FALSE !((int )wl_pc == 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=1, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L271] COND TRUE (int )wl_pc == 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=1, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L272] COND TRUE (int )e_e == 1 [L273] wl_st = 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=1, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L281] e_e = 2 [L282] RET r_st = 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=1, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L386] read() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp___3=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L296] COND TRUE 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp___3=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L298] COND TRUE (int )wl_st == 0 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp___3=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L319] COND TRUE (int )wl_st == 0 [L321] tmp = __VERIFIER_nondet_int() [L323] COND TRUE \read(tmp) [L325] wl_st = 1 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=2, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, tmp=1, tmp___3=1, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L326] CALL write_loop() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L53] int t ; VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L56] COND FALSE !((int )wl_pc == 0) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L59] COND TRUE (int )wl_pc == 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L108] t = t_b VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L109] COND FALSE !(d == t + 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L112] COND TRUE d == t + 2 VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L120] COND FALSE !(d == t + 1) VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L124] CALL error() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L13] __VERIFIER_error() VAL [\old(c)=0, \old(c1_i)=0, \old(c1_pc)=1, \old(c1_st)=2, \old(c2_i)=0, \old(c2_pc)=1, \old(c2_st)=2, \old(c_req_up)=0, \old(c_t)=2, \old(d)=0, \old(data)=2, \old(e_c)=2, \old(e_e)=2, \old(e_f)=2, \old(e_g)=2, \old(e_wl)=2, \old(processed)=1, \old(r_i)=0, \old(r_st)=0, \old(t_b)=0, \old(wb_i)=0, \old(wb_pc)=1, \old(wb_st)=2, \old(wl_i)=0, \old(wl_pc)=2, \old(wl_st)=1, c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 11 procedures, 167 locations, 1 error locations. UNSAFE Result, 35.6s OverallTime, 28 OverallIterations, 6 TraceHistogramMax, 24.6s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 9420 SDtfs, 25906 SDslu, 24671 SDs, 0 SdLazy, 19480 SolverSat, 4423 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 10.1s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 1786 GetRequests, 1432 SyntacticMatches, 14 SemanticMatches, 340 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11905 ImplicationChecksByTransitivity, 5.0s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=16323occurred in iteration=17, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 7.0s AutomataMinimizationTime, 27 MinimizatonAttempts, 12913 StatesRemovedByMinimization, 22 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.2s SsaConstructionTime, 0.7s SatisfiabilityAnalysisTime, 1.9s InterpolantComputationTime, 4886 NumberOfCodeBlocks, 4886 NumberOfCodeBlocksAsserted, 35 NumberOfCheckSat, 4601 ConstructedInterpolants, 0 QuantifiedInterpolants, 1918893 SizeOfPredicates, 12 NumberOfNonLiveVariables, 7440 ConjunctsInSsa, 59 ConjunctsInUnsatCore, 34 InterpolantComputations, 26 PerfectInterpolantSequences, 1921/2139 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...