./Ultimate.py --spec ../../sv-benchmarks/c/ReachSafety.prp --file ../../sv-benchmarks/c/systemc/transmitter.02_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 5842f4b8 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_88f74cf4-b90d-49ed-8344-6ac0367bcb2b/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_88f74cf4-b90d-49ed-8344-6ac0367bcb2b/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_88f74cf4-b90d-49ed-8344-6ac0367bcb2b/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_88f74cf4-b90d-49ed-8344-6ac0367bcb2b/bin-2019/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.02_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_88f74cf4-b90d-49ed-8344-6ac0367bcb2b/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_88f74cf4-b90d-49ed-8344-6ac0367bcb2b/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 0c244c639ec9718adcbacffa967b748c52a23cd0 ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-5842f4b [2018-11-18 12:48:15,313 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-18 12:48:15,314 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-18 12:48:15,320 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-18 12:48:15,320 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-18 12:48:15,321 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-18 12:48:15,322 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-18 12:48:15,323 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-18 12:48:15,324 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-18 12:48:15,325 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-18 12:48:15,325 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-18 12:48:15,325 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-18 12:48:15,326 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-18 12:48:15,326 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-18 12:48:15,327 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-18 12:48:15,327 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-18 12:48:15,328 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-18 12:48:15,329 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-18 12:48:15,330 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-18 12:48:15,331 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-18 12:48:15,332 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-18 12:48:15,333 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-18 12:48:15,334 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-18 12:48:15,334 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-18 12:48:15,334 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-18 12:48:15,335 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-18 12:48:15,336 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-18 12:48:15,336 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-18 12:48:15,337 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-18 12:48:15,337 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-18 12:48:15,337 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-18 12:48:15,337 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-18 12:48:15,338 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-18 12:48:15,338 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-18 12:48:15,338 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-18 12:48:15,339 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-18 12:48:15,339 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_88f74cf4-b90d-49ed-8344-6ac0367bcb2b/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2018-11-18 12:48:15,346 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-18 12:48:15,346 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-18 12:48:15,346 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-18 12:48:15,346 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-11-18 12:48:15,347 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-18 12:48:15,347 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-18 12:48:15,347 INFO L133 SettingsManager]: * Use SBE=true [2018-11-18 12:48:15,347 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-18 12:48:15,347 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-18 12:48:15,348 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-18 12:48:15,348 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-18 12:48:15,348 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-18 12:48:15,348 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-18 12:48:15,348 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-18 12:48:15,348 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-18 12:48:15,348 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-18 12:48:15,348 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-18 12:48:15,349 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-18 12:48:15,349 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-18 12:48:15,349 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-18 12:48:15,349 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-18 12:48:15,349 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-18 12:48:15,349 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-18 12:48:15,349 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-18 12:48:15,350 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-18 12:48:15,350 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-18 12:48:15,350 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-18 12:48:15,350 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-18 12:48:15,350 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-18 12:48:15,350 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-18 12:48:15,350 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_88f74cf4-b90d-49ed-8344-6ac0367bcb2b/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 0c244c639ec9718adcbacffa967b748c52a23cd0 [2018-11-18 12:48:15,377 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-18 12:48:15,385 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-18 12:48:15,388 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-18 12:48:15,389 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-18 12:48:15,389 INFO L276 PluginConnector]: CDTParser initialized [2018-11-18 12:48:15,390 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_88f74cf4-b90d-49ed-8344-6ac0367bcb2b/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/transmitter.02_false-unreach-call_false-termination.cil.c [2018-11-18 12:48:15,435 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_88f74cf4-b90d-49ed-8344-6ac0367bcb2b/bin-2019/uautomizer/data/d7d63fda4/24325a5408534871b26c60abb230ed08/FLAG5053a53a4 [2018-11-18 12:48:15,753 INFO L307 CDTParser]: Found 1 translation units. [2018-11-18 12:48:15,753 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_88f74cf4-b90d-49ed-8344-6ac0367bcb2b/sv-benchmarks/c/systemc/transmitter.02_false-unreach-call_false-termination.cil.c [2018-11-18 12:48:15,760 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_88f74cf4-b90d-49ed-8344-6ac0367bcb2b/bin-2019/uautomizer/data/d7d63fda4/24325a5408534871b26c60abb230ed08/FLAG5053a53a4 [2018-11-18 12:48:15,771 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_88f74cf4-b90d-49ed-8344-6ac0367bcb2b/bin-2019/uautomizer/data/d7d63fda4/24325a5408534871b26c60abb230ed08 [2018-11-18 12:48:15,773 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-18 12:48:15,774 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-11-18 12:48:15,774 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-18 12:48:15,775 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-18 12:48:15,777 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-18 12:48:15,777 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 12:48:15" (1/1) ... [2018-11-18 12:48:15,779 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@44c74022 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 12:48:15, skipping insertion in model container [2018-11-18 12:48:15,779 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 12:48:15" (1/1) ... [2018-11-18 12:48:15,785 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-18 12:48:15,808 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-18 12:48:15,946 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 12:48:15,951 INFO L191 MainTranslator]: Completed pre-run [2018-11-18 12:48:15,973 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 12:48:15,983 INFO L195 MainTranslator]: Completed translation [2018-11-18 12:48:15,983 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 12:48:15 WrapperNode [2018-11-18 12:48:15,983 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-18 12:48:15,983 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-18 12:48:15,983 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-18 12:48:15,984 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-18 12:48:15,993 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 12:48:15" (1/1) ... [2018-11-18 12:48:15,993 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 12:48:15" (1/1) ... [2018-11-18 12:48:16,034 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 12:48:15" (1/1) ... [2018-11-18 12:48:16,035 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 12:48:15" (1/1) ... [2018-11-18 12:48:16,039 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 12:48:15" (1/1) ... [2018-11-18 12:48:16,045 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 12:48:15" (1/1) ... [2018-11-18 12:48:16,046 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 12:48:15" (1/1) ... [2018-11-18 12:48:16,048 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-18 12:48:16,048 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-18 12:48:16,048 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-18 12:48:16,048 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-18 12:48:16,049 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 12:48:15" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_88f74cf4-b90d-49ed-8344-6ac0367bcb2b/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-18 12:48:16,080 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-18 12:48:16,080 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-18 12:48:16,080 INFO L138 BoogieDeclarations]: Found implementation of procedure error [2018-11-18 12:48:16,081 INFO L138 BoogieDeclarations]: Found implementation of procedure master [2018-11-18 12:48:16,081 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit1 [2018-11-18 12:48:16,081 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit2 [2018-11-18 12:48:16,081 INFO L138 BoogieDeclarations]: Found implementation of procedure is_master_triggered [2018-11-18 12:48:16,081 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit1_triggered [2018-11-18 12:48:16,081 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit2_triggered [2018-11-18 12:48:16,081 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels [2018-11-18 12:48:16,081 INFO L138 BoogieDeclarations]: Found implementation of procedure init_threads [2018-11-18 12:48:16,082 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread [2018-11-18 12:48:16,082 INFO L138 BoogieDeclarations]: Found implementation of procedure eval [2018-11-18 12:48:16,082 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events [2018-11-18 12:48:16,082 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events [2018-11-18 12:48:16,082 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads [2018-11-18 12:48:16,082 INFO L138 BoogieDeclarations]: Found implementation of procedure immediate_notify [2018-11-18 12:48:16,082 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_time_events [2018-11-18 12:48:16,082 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_time_events [2018-11-18 12:48:16,082 INFO L138 BoogieDeclarations]: Found implementation of procedure init_model [2018-11-18 12:48:16,082 INFO L138 BoogieDeclarations]: Found implementation of procedure stop_simulation [2018-11-18 12:48:16,082 INFO L138 BoogieDeclarations]: Found implementation of procedure start_simulation [2018-11-18 12:48:16,083 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-18 12:48:16,083 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-11-18 12:48:16,083 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-11-18 12:48:16,083 INFO L130 BoogieDeclarations]: Found specification of procedure error [2018-11-18 12:48:16,083 INFO L130 BoogieDeclarations]: Found specification of procedure is_master_triggered [2018-11-18 12:48:16,083 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit1_triggered [2018-11-18 12:48:16,083 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit2_triggered [2018-11-18 12:48:16,083 INFO L130 BoogieDeclarations]: Found specification of procedure immediate_notify [2018-11-18 12:48:16,083 INFO L130 BoogieDeclarations]: Found specification of procedure master [2018-11-18 12:48:16,083 INFO L130 BoogieDeclarations]: Found specification of procedure transmit1 [2018-11-18 12:48:16,083 INFO L130 BoogieDeclarations]: Found specification of procedure transmit2 [2018-11-18 12:48:16,083 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels [2018-11-18 12:48:16,084 INFO L130 BoogieDeclarations]: Found specification of procedure init_threads [2018-11-18 12:48:16,084 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread [2018-11-18 12:48:16,084 INFO L130 BoogieDeclarations]: Found specification of procedure eval [2018-11-18 12:48:16,084 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events [2018-11-18 12:48:16,084 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events [2018-11-18 12:48:16,084 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads [2018-11-18 12:48:16,084 INFO L130 BoogieDeclarations]: Found specification of procedure fire_time_events [2018-11-18 12:48:16,084 INFO L130 BoogieDeclarations]: Found specification of procedure reset_time_events [2018-11-18 12:48:16,084 INFO L130 BoogieDeclarations]: Found specification of procedure init_model [2018-11-18 12:48:16,085 INFO L130 BoogieDeclarations]: Found specification of procedure stop_simulation [2018-11-18 12:48:16,085 INFO L130 BoogieDeclarations]: Found specification of procedure start_simulation [2018-11-18 12:48:16,085 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-18 12:48:16,085 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-18 12:48:16,085 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-18 12:48:16,463 INFO L278 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-18 12:48:16,463 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 12:48:16 BoogieIcfgContainer [2018-11-18 12:48:16,463 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-18 12:48:16,464 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-18 12:48:16,464 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-18 12:48:16,467 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-18 12:48:16,467 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 18.11 12:48:15" (1/3) ... [2018-11-18 12:48:16,467 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@16cd130e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 18.11 12:48:16, skipping insertion in model container [2018-11-18 12:48:16,468 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 12:48:15" (2/3) ... [2018-11-18 12:48:16,468 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@16cd130e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 18.11 12:48:16, skipping insertion in model container [2018-11-18 12:48:16,468 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 12:48:16" (3/3) ... [2018-11-18 12:48:16,469 INFO L112 eAbstractionObserver]: Analyzing ICFG transmitter.02_false-unreach-call_false-termination.cil.c [2018-11-18 12:48:16,475 INFO L136 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-18 12:48:16,480 INFO L148 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-18 12:48:16,493 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-18 12:48:16,518 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-18 12:48:16,519 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-18 12:48:16,519 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-18 12:48:16,519 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-18 12:48:16,519 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-18 12:48:16,519 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-18 12:48:16,519 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-18 12:48:16,519 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-18 12:48:16,519 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-18 12:48:16,537 INFO L276 IsEmpty]: Start isEmpty. Operand 175 states. [2018-11-18 12:48:16,543 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-11-18 12:48:16,543 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 12:48:16,544 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 12:48:16,546 INFO L423 AbstractCegarLoop]: === Iteration 1 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 12:48:16,550 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 12:48:16,551 INFO L82 PathProgramCache]: Analyzing trace with hash -613658526, now seen corresponding path program 1 times [2018-11-18 12:48:16,552 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 12:48:16,553 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 12:48:16,585 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:16,585 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 12:48:16,585 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:16,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:48:16,771 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:48:16,773 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 12:48:16,774 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 12:48:16,778 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 12:48:16,790 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 12:48:16,790 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 12:48:16,792 INFO L87 Difference]: Start difference. First operand 175 states. Second operand 5 states. [2018-11-18 12:48:17,168 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 12:48:17,168 INFO L93 Difference]: Finished difference Result 362 states and 521 transitions. [2018-11-18 12:48:17,169 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 12:48:17,169 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 92 [2018-11-18 12:48:17,170 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 12:48:17,180 INFO L225 Difference]: With dead ends: 362 [2018-11-18 12:48:17,180 INFO L226 Difference]: Without dead ends: 195 [2018-11-18 12:48:17,184 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-18 12:48:17,196 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 195 states. [2018-11-18 12:48:17,229 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 195 to 166. [2018-11-18 12:48:17,230 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 166 states. [2018-11-18 12:48:17,232 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 166 states to 166 states and 218 transitions. [2018-11-18 12:48:17,234 INFO L78 Accepts]: Start accepts. Automaton has 166 states and 218 transitions. Word has length 92 [2018-11-18 12:48:17,234 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 12:48:17,234 INFO L480 AbstractCegarLoop]: Abstraction has 166 states and 218 transitions. [2018-11-18 12:48:17,234 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 12:48:17,235 INFO L276 IsEmpty]: Start isEmpty. Operand 166 states and 218 transitions. [2018-11-18 12:48:17,237 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-11-18 12:48:17,237 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 12:48:17,237 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 12:48:17,237 INFO L423 AbstractCegarLoop]: === Iteration 2 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 12:48:17,237 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 12:48:17,237 INFO L82 PathProgramCache]: Analyzing trace with hash -1106284700, now seen corresponding path program 1 times [2018-11-18 12:48:17,237 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 12:48:17,238 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 12:48:17,238 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:17,238 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 12:48:17,238 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:17,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:48:17,334 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:48:17,334 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 12:48:17,334 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 12:48:17,335 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 12:48:17,336 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 12:48:17,336 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 12:48:17,336 INFO L87 Difference]: Start difference. First operand 166 states and 218 transitions. Second operand 5 states. [2018-11-18 12:48:17,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 12:48:17,608 INFO L93 Difference]: Finished difference Result 339 states and 459 transitions. [2018-11-18 12:48:17,608 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 12:48:17,608 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 92 [2018-11-18 12:48:17,609 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 12:48:17,611 INFO L225 Difference]: With dead ends: 339 [2018-11-18 12:48:17,611 INFO L226 Difference]: Without dead ends: 193 [2018-11-18 12:48:17,612 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-18 12:48:17,613 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 193 states. [2018-11-18 12:48:17,628 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 193 to 166. [2018-11-18 12:48:17,628 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 166 states. [2018-11-18 12:48:17,630 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 166 states to 166 states and 217 transitions. [2018-11-18 12:48:17,630 INFO L78 Accepts]: Start accepts. Automaton has 166 states and 217 transitions. Word has length 92 [2018-11-18 12:48:17,631 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 12:48:17,631 INFO L480 AbstractCegarLoop]: Abstraction has 166 states and 217 transitions. [2018-11-18 12:48:17,631 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 12:48:17,631 INFO L276 IsEmpty]: Start isEmpty. Operand 166 states and 217 transitions. [2018-11-18 12:48:17,632 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-11-18 12:48:17,633 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 12:48:17,633 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 12:48:17,633 INFO L423 AbstractCegarLoop]: === Iteration 3 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 12:48:17,633 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 12:48:17,633 INFO L82 PathProgramCache]: Analyzing trace with hash -152344542, now seen corresponding path program 1 times [2018-11-18 12:48:17,633 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 12:48:17,634 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 12:48:17,634 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:17,634 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 12:48:17,634 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:17,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:48:17,712 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:48:17,712 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 12:48:17,713 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 12:48:17,713 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 12:48:17,713 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 12:48:17,713 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 12:48:17,713 INFO L87 Difference]: Start difference. First operand 166 states and 217 transitions. Second operand 5 states. [2018-11-18 12:48:17,947 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 12:48:17,947 INFO L93 Difference]: Finished difference Result 358 states and 487 transitions. [2018-11-18 12:48:17,948 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 12:48:17,948 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 92 [2018-11-18 12:48:17,948 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 12:48:17,950 INFO L225 Difference]: With dead ends: 358 [2018-11-18 12:48:17,950 INFO L226 Difference]: Without dead ends: 212 [2018-11-18 12:48:17,951 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-18 12:48:17,951 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 212 states. [2018-11-18 12:48:17,965 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 212 to 166. [2018-11-18 12:48:17,965 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 166 states. [2018-11-18 12:48:17,966 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 166 states to 166 states and 216 transitions. [2018-11-18 12:48:17,967 INFO L78 Accepts]: Start accepts. Automaton has 166 states and 216 transitions. Word has length 92 [2018-11-18 12:48:17,967 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 12:48:17,967 INFO L480 AbstractCegarLoop]: Abstraction has 166 states and 216 transitions. [2018-11-18 12:48:17,967 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 12:48:17,967 INFO L276 IsEmpty]: Start isEmpty. Operand 166 states and 216 transitions. [2018-11-18 12:48:17,968 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-11-18 12:48:17,968 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 12:48:17,968 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 12:48:17,968 INFO L423 AbstractCegarLoop]: === Iteration 4 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 12:48:17,969 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 12:48:17,969 INFO L82 PathProgramCache]: Analyzing trace with hash -1368498268, now seen corresponding path program 1 times [2018-11-18 12:48:17,969 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 12:48:17,969 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 12:48:17,970 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:17,970 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 12:48:17,970 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:17,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:48:18,030 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:48:18,031 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 12:48:18,031 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 12:48:18,031 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 12:48:18,031 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 12:48:18,031 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 12:48:18,032 INFO L87 Difference]: Start difference. First operand 166 states and 216 transitions. Second operand 5 states. [2018-11-18 12:48:18,270 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 12:48:18,270 INFO L93 Difference]: Finished difference Result 356 states and 481 transitions. [2018-11-18 12:48:18,271 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 12:48:18,271 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 92 [2018-11-18 12:48:18,271 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 12:48:18,273 INFO L225 Difference]: With dead ends: 356 [2018-11-18 12:48:18,273 INFO L226 Difference]: Without dead ends: 210 [2018-11-18 12:48:18,274 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-18 12:48:18,274 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 210 states. [2018-11-18 12:48:18,293 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 210 to 166. [2018-11-18 12:48:18,293 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 166 states. [2018-11-18 12:48:18,294 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 166 states to 166 states and 215 transitions. [2018-11-18 12:48:18,295 INFO L78 Accepts]: Start accepts. Automaton has 166 states and 215 transitions. Word has length 92 [2018-11-18 12:48:18,296 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 12:48:18,296 INFO L480 AbstractCegarLoop]: Abstraction has 166 states and 215 transitions. [2018-11-18 12:48:18,296 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 12:48:18,296 INFO L276 IsEmpty]: Start isEmpty. Operand 166 states and 215 transitions. [2018-11-18 12:48:18,298 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-11-18 12:48:18,298 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 12:48:18,298 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 12:48:18,298 INFO L423 AbstractCegarLoop]: === Iteration 5 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 12:48:18,298 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 12:48:18,298 INFO L82 PathProgramCache]: Analyzing trace with hash -2100465694, now seen corresponding path program 1 times [2018-11-18 12:48:18,299 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 12:48:18,299 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 12:48:18,299 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:18,299 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 12:48:18,300 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:18,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:48:18,335 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:48:18,336 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 12:48:18,336 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-18 12:48:18,336 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-18 12:48:18,338 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-18 12:48:18,338 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-18 12:48:18,338 INFO L87 Difference]: Start difference. First operand 166 states and 215 transitions. Second operand 6 states. [2018-11-18 12:48:18,370 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 12:48:18,370 INFO L93 Difference]: Finished difference Result 324 states and 433 transitions. [2018-11-18 12:48:18,371 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 12:48:18,371 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 92 [2018-11-18 12:48:18,371 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 12:48:18,372 INFO L225 Difference]: With dead ends: 324 [2018-11-18 12:48:18,372 INFO L226 Difference]: Without dead ends: 179 [2018-11-18 12:48:18,373 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-18 12:48:18,373 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179 states. [2018-11-18 12:48:18,386 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179 to 171. [2018-11-18 12:48:18,387 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 171 states. [2018-11-18 12:48:18,388 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 171 states to 171 states and 220 transitions. [2018-11-18 12:48:18,388 INFO L78 Accepts]: Start accepts. Automaton has 171 states and 220 transitions. Word has length 92 [2018-11-18 12:48:18,388 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 12:48:18,388 INFO L480 AbstractCegarLoop]: Abstraction has 171 states and 220 transitions. [2018-11-18 12:48:18,388 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-18 12:48:18,388 INFO L276 IsEmpty]: Start isEmpty. Operand 171 states and 220 transitions. [2018-11-18 12:48:18,389 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-11-18 12:48:18,389 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 12:48:18,389 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 12:48:18,390 INFO L423 AbstractCegarLoop]: === Iteration 6 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 12:48:18,390 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 12:48:18,390 INFO L82 PathProgramCache]: Analyzing trace with hash -1656565020, now seen corresponding path program 1 times [2018-11-18 12:48:18,390 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 12:48:18,390 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 12:48:18,391 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:18,391 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 12:48:18,391 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:18,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:48:18,453 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:48:18,453 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 12:48:18,453 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-18 12:48:18,453 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-18 12:48:18,453 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-18 12:48:18,453 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-18 12:48:18,454 INFO L87 Difference]: Start difference. First operand 171 states and 220 transitions. Second operand 6 states. [2018-11-18 12:48:18,489 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 12:48:18,489 INFO L93 Difference]: Finished difference Result 331 states and 438 transitions. [2018-11-18 12:48:18,489 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 12:48:18,490 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 92 [2018-11-18 12:48:18,490 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 12:48:18,491 INFO L225 Difference]: With dead ends: 331 [2018-11-18 12:48:18,491 INFO L226 Difference]: Without dead ends: 181 [2018-11-18 12:48:18,492 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-18 12:48:18,492 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 181 states. [2018-11-18 12:48:18,505 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 181 to 176. [2018-11-18 12:48:18,506 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 176 states. [2018-11-18 12:48:18,507 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 176 states to 176 states and 225 transitions. [2018-11-18 12:48:18,508 INFO L78 Accepts]: Start accepts. Automaton has 176 states and 225 transitions. Word has length 92 [2018-11-18 12:48:18,508 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 12:48:18,508 INFO L480 AbstractCegarLoop]: Abstraction has 176 states and 225 transitions. [2018-11-18 12:48:18,508 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-18 12:48:18,508 INFO L276 IsEmpty]: Start isEmpty. Operand 176 states and 225 transitions. [2018-11-18 12:48:18,509 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-11-18 12:48:18,509 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 12:48:18,509 INFO L375 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 12:48:18,509 INFO L423 AbstractCegarLoop]: === Iteration 7 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 12:48:18,510 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 12:48:18,510 INFO L82 PathProgramCache]: Analyzing trace with hash 589014434, now seen corresponding path program 1 times [2018-11-18 12:48:18,510 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 12:48:18,510 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 12:48:18,510 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:18,511 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 12:48:18,511 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:18,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:48:18,568 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:48:18,569 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 12:48:18,569 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-18 12:48:18,569 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-18 12:48:18,569 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-18 12:48:18,569 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-18 12:48:18,569 INFO L87 Difference]: Start difference. First operand 176 states and 225 transitions. Second operand 4 states. [2018-11-18 12:48:18,732 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 12:48:18,732 INFO L93 Difference]: Finished difference Result 476 states and 631 transitions. [2018-11-18 12:48:18,733 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-18 12:48:18,733 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 92 [2018-11-18 12:48:18,733 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 12:48:18,734 INFO L225 Difference]: With dead ends: 476 [2018-11-18 12:48:18,734 INFO L226 Difference]: Without dead ends: 321 [2018-11-18 12:48:18,735 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-18 12:48:18,735 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 321 states. [2018-11-18 12:48:18,762 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 321 to 321. [2018-11-18 12:48:18,762 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 321 states. [2018-11-18 12:48:18,764 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 321 states to 321 states and 408 transitions. [2018-11-18 12:48:18,764 INFO L78 Accepts]: Start accepts. Automaton has 321 states and 408 transitions. Word has length 92 [2018-11-18 12:48:18,764 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 12:48:18,765 INFO L480 AbstractCegarLoop]: Abstraction has 321 states and 408 transitions. [2018-11-18 12:48:18,765 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-18 12:48:18,765 INFO L276 IsEmpty]: Start isEmpty. Operand 321 states and 408 transitions. [2018-11-18 12:48:18,766 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-11-18 12:48:18,766 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 12:48:18,766 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 12:48:18,766 INFO L423 AbstractCegarLoop]: === Iteration 8 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 12:48:18,767 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 12:48:18,767 INFO L82 PathProgramCache]: Analyzing trace with hash -307321518, now seen corresponding path program 1 times [2018-11-18 12:48:18,767 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 12:48:18,767 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 12:48:18,768 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:18,768 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 12:48:18,768 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:18,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:48:18,807 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-11-18 12:48:18,807 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 12:48:18,808 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-18 12:48:18,808 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-18 12:48:18,808 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-18 12:48:18,808 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-18 12:48:18,808 INFO L87 Difference]: Start difference. First operand 321 states and 408 transitions. Second operand 6 states. [2018-11-18 12:48:18,852 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 12:48:18,853 INFO L93 Difference]: Finished difference Result 628 states and 817 transitions. [2018-11-18 12:48:18,854 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 12:48:18,854 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 113 [2018-11-18 12:48:18,854 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 12:48:18,856 INFO L225 Difference]: With dead ends: 628 [2018-11-18 12:48:18,856 INFO L226 Difference]: Without dead ends: 328 [2018-11-18 12:48:18,857 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-18 12:48:18,857 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 328 states. [2018-11-18 12:48:18,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 328 to 326. [2018-11-18 12:48:18,878 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 326 states. [2018-11-18 12:48:18,880 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 326 states to 326 states and 412 transitions. [2018-11-18 12:48:18,880 INFO L78 Accepts]: Start accepts. Automaton has 326 states and 412 transitions. Word has length 113 [2018-11-18 12:48:18,881 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 12:48:18,881 INFO L480 AbstractCegarLoop]: Abstraction has 326 states and 412 transitions. [2018-11-18 12:48:18,881 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-18 12:48:18,881 INFO L276 IsEmpty]: Start isEmpty. Operand 326 states and 412 transitions. [2018-11-18 12:48:18,882 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-11-18 12:48:18,882 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 12:48:18,882 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 12:48:18,882 INFO L423 AbstractCegarLoop]: === Iteration 9 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 12:48:18,883 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 12:48:18,883 INFO L82 PathProgramCache]: Analyzing trace with hash -266646768, now seen corresponding path program 1 times [2018-11-18 12:48:18,883 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 12:48:18,883 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 12:48:18,883 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:18,884 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 12:48:18,884 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:18,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:48:18,972 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-11-18 12:48:18,972 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 12:48:18,973 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 12:48:18,973 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 12:48:18,973 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 12:48:18,973 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 12:48:18,973 INFO L87 Difference]: Start difference. First operand 326 states and 412 transitions. Second operand 5 states. [2018-11-18 12:48:19,334 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 12:48:19,334 INFO L93 Difference]: Finished difference Result 852 states and 1129 transitions. [2018-11-18 12:48:19,335 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-18 12:48:19,335 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 113 [2018-11-18 12:48:19,336 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 12:48:19,338 INFO L225 Difference]: With dead ends: 852 [2018-11-18 12:48:19,338 INFO L226 Difference]: Without dead ends: 547 [2018-11-18 12:48:19,340 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-18 12:48:19,340 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 547 states. [2018-11-18 12:48:19,374 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 547 to 454. [2018-11-18 12:48:19,374 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 454 states. [2018-11-18 12:48:19,377 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 454 states to 454 states and 581 transitions. [2018-11-18 12:48:19,377 INFO L78 Accepts]: Start accepts. Automaton has 454 states and 581 transitions. Word has length 113 [2018-11-18 12:48:19,378 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 12:48:19,378 INFO L480 AbstractCegarLoop]: Abstraction has 454 states and 581 transitions. [2018-11-18 12:48:19,378 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 12:48:19,378 INFO L276 IsEmpty]: Start isEmpty. Operand 454 states and 581 transitions. [2018-11-18 12:48:19,379 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-11-18 12:48:19,380 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 12:48:19,380 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 12:48:19,380 INFO L423 AbstractCegarLoop]: === Iteration 10 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 12:48:19,380 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 12:48:19,380 INFO L82 PathProgramCache]: Analyzing trace with hash 1271693262, now seen corresponding path program 1 times [2018-11-18 12:48:19,380 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 12:48:19,380 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 12:48:19,381 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:19,381 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 12:48:19,381 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:19,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:48:19,429 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-11-18 12:48:19,429 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 12:48:19,429 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 12:48:19,430 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 12:48:19,430 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 12:48:19,430 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 12:48:19,430 INFO L87 Difference]: Start difference. First operand 454 states and 581 transitions. Second operand 5 states. [2018-11-18 12:48:19,664 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 12:48:19,664 INFO L93 Difference]: Finished difference Result 884 states and 1141 transitions. [2018-11-18 12:48:19,665 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 12:48:19,665 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 113 [2018-11-18 12:48:19,665 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 12:48:19,668 INFO L225 Difference]: With dead ends: 884 [2018-11-18 12:48:19,668 INFO L226 Difference]: Without dead ends: 454 [2018-11-18 12:48:19,669 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-18 12:48:19,670 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 454 states. [2018-11-18 12:48:19,703 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 454 to 454. [2018-11-18 12:48:19,704 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 454 states. [2018-11-18 12:48:19,706 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 454 states to 454 states and 573 transitions. [2018-11-18 12:48:19,706 INFO L78 Accepts]: Start accepts. Automaton has 454 states and 573 transitions. Word has length 113 [2018-11-18 12:48:19,707 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 12:48:19,707 INFO L480 AbstractCegarLoop]: Abstraction has 454 states and 573 transitions. [2018-11-18 12:48:19,707 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 12:48:19,707 INFO L276 IsEmpty]: Start isEmpty. Operand 454 states and 573 transitions. [2018-11-18 12:48:19,709 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 115 [2018-11-18 12:48:19,709 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 12:48:19,709 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 12:48:19,709 INFO L423 AbstractCegarLoop]: === Iteration 11 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 12:48:19,709 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 12:48:19,709 INFO L82 PathProgramCache]: Analyzing trace with hash -1703462857, now seen corresponding path program 1 times [2018-11-18 12:48:19,710 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 12:48:19,710 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 12:48:19,710 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:19,710 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 12:48:19,710 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:19,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:48:19,772 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-11-18 12:48:19,772 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 12:48:19,772 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 12:48:19,773 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 12:48:19,773 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 12:48:19,773 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 12:48:19,773 INFO L87 Difference]: Start difference. First operand 454 states and 573 transitions. Second operand 5 states. [2018-11-18 12:48:19,964 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 12:48:19,964 INFO L93 Difference]: Finished difference Result 889 states and 1125 transitions. [2018-11-18 12:48:19,964 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 12:48:19,965 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 114 [2018-11-18 12:48:19,965 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 12:48:19,966 INFO L225 Difference]: With dead ends: 889 [2018-11-18 12:48:19,966 INFO L226 Difference]: Without dead ends: 456 [2018-11-18 12:48:19,967 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-18 12:48:19,968 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 456 states. [2018-11-18 12:48:19,986 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 456 to 422. [2018-11-18 12:48:19,986 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 422 states. [2018-11-18 12:48:19,987 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 422 states to 422 states and 520 transitions. [2018-11-18 12:48:19,988 INFO L78 Accepts]: Start accepts. Automaton has 422 states and 520 transitions. Word has length 114 [2018-11-18 12:48:19,988 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 12:48:19,988 INFO L480 AbstractCegarLoop]: Abstraction has 422 states and 520 transitions. [2018-11-18 12:48:19,988 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 12:48:19,988 INFO L276 IsEmpty]: Start isEmpty. Operand 422 states and 520 transitions. [2018-11-18 12:48:19,989 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-11-18 12:48:19,989 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 12:48:19,989 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 12:48:19,990 INFO L423 AbstractCegarLoop]: === Iteration 12 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 12:48:19,990 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 12:48:19,990 INFO L82 PathProgramCache]: Analyzing trace with hash -756892848, now seen corresponding path program 1 times [2018-11-18 12:48:19,990 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 12:48:19,990 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 12:48:19,990 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:19,991 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 12:48:19,991 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:19,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:48:20,036 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-11-18 12:48:20,037 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 12:48:20,037 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 12:48:20,037 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 12:48:20,037 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 12:48:20,037 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 12:48:20,037 INFO L87 Difference]: Start difference. First operand 422 states and 520 transitions. Second operand 5 states. [2018-11-18 12:48:20,220 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 12:48:20,220 INFO L93 Difference]: Finished difference Result 822 states and 1020 transitions. [2018-11-18 12:48:20,220 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-18 12:48:20,220 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 113 [2018-11-18 12:48:20,221 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 12:48:20,222 INFO L225 Difference]: With dead ends: 822 [2018-11-18 12:48:20,222 INFO L226 Difference]: Without dead ends: 422 [2018-11-18 12:48:20,223 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-18 12:48:20,223 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 422 states. [2018-11-18 12:48:20,239 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 422 to 422. [2018-11-18 12:48:20,239 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 422 states. [2018-11-18 12:48:20,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 422 states to 422 states and 514 transitions. [2018-11-18 12:48:20,241 INFO L78 Accepts]: Start accepts. Automaton has 422 states and 514 transitions. Word has length 113 [2018-11-18 12:48:20,241 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 12:48:20,241 INFO L480 AbstractCegarLoop]: Abstraction has 422 states and 514 transitions. [2018-11-18 12:48:20,241 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 12:48:20,241 INFO L276 IsEmpty]: Start isEmpty. Operand 422 states and 514 transitions. [2018-11-18 12:48:20,242 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-11-18 12:48:20,242 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 12:48:20,242 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 12:48:20,243 INFO L423 AbstractCegarLoop]: === Iteration 13 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 12:48:20,243 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 12:48:20,243 INFO L82 PathProgramCache]: Analyzing trace with hash -1237973106, now seen corresponding path program 1 times [2018-11-18 12:48:20,243 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 12:48:20,243 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 12:48:20,244 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:20,244 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 12:48:20,244 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:20,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:48:20,296 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-11-18 12:48:20,296 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 12:48:20,296 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 12:48:20,296 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-18 12:48:20,297 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 12:48:20,297 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 12:48:20,297 INFO L87 Difference]: Start difference. First operand 422 states and 514 transitions. Second operand 5 states. [2018-11-18 12:48:20,562 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 12:48:20,562 INFO L93 Difference]: Finished difference Result 975 states and 1250 transitions. [2018-11-18 12:48:20,562 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 12:48:20,562 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 113 [2018-11-18 12:48:20,563 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 12:48:20,564 INFO L225 Difference]: With dead ends: 975 [2018-11-18 12:48:20,564 INFO L226 Difference]: Without dead ends: 575 [2018-11-18 12:48:20,565 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-18 12:48:20,566 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 575 states. [2018-11-18 12:48:20,585 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 575 to 492. [2018-11-18 12:48:20,585 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 492 states. [2018-11-18 12:48:20,587 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 492 states to 492 states and 585 transitions. [2018-11-18 12:48:20,587 INFO L78 Accepts]: Start accepts. Automaton has 492 states and 585 transitions. Word has length 113 [2018-11-18 12:48:20,587 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 12:48:20,587 INFO L480 AbstractCegarLoop]: Abstraction has 492 states and 585 transitions. [2018-11-18 12:48:20,587 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-18 12:48:20,587 INFO L276 IsEmpty]: Start isEmpty. Operand 492 states and 585 transitions. [2018-11-18 12:48:20,588 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-11-18 12:48:20,588 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 12:48:20,588 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 12:48:20,589 INFO L423 AbstractCegarLoop]: === Iteration 14 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 12:48:20,589 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 12:48:20,589 INFO L82 PathProgramCache]: Analyzing trace with hash 701188940, now seen corresponding path program 1 times [2018-11-18 12:48:20,589 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 12:48:20,589 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 12:48:20,590 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:20,590 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 12:48:20,590 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:20,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:48:20,613 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 7 proven. 3 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-11-18 12:48:20,613 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 12:48:20,613 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_88f74cf4-b90d-49ed-8344-6ac0367bcb2b/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 12:48:20,621 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 12:48:20,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:48:20,671 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 12:48:20,684 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-11-18 12:48:20,700 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-18 12:48:20,700 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [3] total 3 [2018-11-18 12:48:20,701 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 12:48:20,701 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 12:48:20,701 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 12:48:20,701 INFO L87 Difference]: Start difference. First operand 492 states and 585 transitions. Second operand 3 states. [2018-11-18 12:48:20,756 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 12:48:20,756 INFO L93 Difference]: Finished difference Result 1403 states and 1690 transitions. [2018-11-18 12:48:20,757 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 12:48:20,757 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 113 [2018-11-18 12:48:20,757 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 12:48:20,759 INFO L225 Difference]: With dead ends: 1403 [2018-11-18 12:48:20,759 INFO L226 Difference]: Without dead ends: 933 [2018-11-18 12:48:20,760 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 115 GetRequests, 114 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 12:48:20,761 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states. [2018-11-18 12:48:20,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 925. [2018-11-18 12:48:20,796 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 925 states. [2018-11-18 12:48:20,798 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 925 states to 925 states and 1109 transitions. [2018-11-18 12:48:20,798 INFO L78 Accepts]: Start accepts. Automaton has 925 states and 1109 transitions. Word has length 113 [2018-11-18 12:48:20,799 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 12:48:20,799 INFO L480 AbstractCegarLoop]: Abstraction has 925 states and 1109 transitions. [2018-11-18 12:48:20,799 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 12:48:20,799 INFO L276 IsEmpty]: Start isEmpty. Operand 925 states and 1109 transitions. [2018-11-18 12:48:20,800 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2018-11-18 12:48:20,800 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 12:48:20,801 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 12:48:20,801 INFO L423 AbstractCegarLoop]: === Iteration 15 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 12:48:20,801 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 12:48:20,801 INFO L82 PathProgramCache]: Analyzing trace with hash 787920672, now seen corresponding path program 1 times [2018-11-18 12:48:20,801 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 12:48:20,801 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 12:48:20,802 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:20,802 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 12:48:20,802 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:20,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:48:20,838 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-11-18 12:48:20,838 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 12:48:20,838 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 12:48:20,838 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 12:48:20,838 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 12:48:20,839 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 12:48:20,839 INFO L87 Difference]: Start difference. First operand 925 states and 1109 transitions. Second operand 3 states. [2018-11-18 12:48:20,926 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 12:48:20,927 INFO L93 Difference]: Finished difference Result 2701 states and 3264 transitions. [2018-11-18 12:48:20,927 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 12:48:20,927 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 115 [2018-11-18 12:48:20,927 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 12:48:20,931 INFO L225 Difference]: With dead ends: 2701 [2018-11-18 12:48:20,931 INFO L226 Difference]: Without dead ends: 1362 [2018-11-18 12:48:20,934 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 12:48:20,935 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1362 states. [2018-11-18 12:48:20,990 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1362 to 1362. [2018-11-18 12:48:20,990 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1362 states. [2018-11-18 12:48:20,993 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1362 states to 1362 states and 1641 transitions. [2018-11-18 12:48:20,993 INFO L78 Accepts]: Start accepts. Automaton has 1362 states and 1641 transitions. Word has length 115 [2018-11-18 12:48:20,994 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 12:48:20,994 INFO L480 AbstractCegarLoop]: Abstraction has 1362 states and 1641 transitions. [2018-11-18 12:48:20,994 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 12:48:20,994 INFO L276 IsEmpty]: Start isEmpty. Operand 1362 states and 1641 transitions. [2018-11-18 12:48:20,996 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 161 [2018-11-18 12:48:20,996 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 12:48:20,996 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 12:48:20,996 INFO L423 AbstractCegarLoop]: === Iteration 16 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 12:48:20,996 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 12:48:20,996 INFO L82 PathProgramCache]: Analyzing trace with hash -2045966145, now seen corresponding path program 1 times [2018-11-18 12:48:20,996 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 12:48:20,996 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 12:48:20,997 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:20,997 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 12:48:20,997 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:21,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:48:21,039 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2018-11-18 12:48:21,040 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 12:48:21,040 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-18 12:48:21,040 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-18 12:48:21,040 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-18 12:48:21,040 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-18 12:48:21,041 INFO L87 Difference]: Start difference. First operand 1362 states and 1641 transitions. Second operand 4 states. [2018-11-18 12:48:21,211 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 12:48:21,212 INFO L93 Difference]: Finished difference Result 2695 states and 3243 transitions. [2018-11-18 12:48:21,213 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-18 12:48:21,213 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 160 [2018-11-18 12:48:21,213 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 12:48:21,218 INFO L225 Difference]: With dead ends: 2695 [2018-11-18 12:48:21,219 INFO L226 Difference]: Without dead ends: 1355 [2018-11-18 12:48:21,221 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-18 12:48:21,223 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1355 states. [2018-11-18 12:48:21,313 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1355 to 1355. [2018-11-18 12:48:21,313 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1355 states. [2018-11-18 12:48:21,318 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1355 states to 1355 states and 1629 transitions. [2018-11-18 12:48:21,318 INFO L78 Accepts]: Start accepts. Automaton has 1355 states and 1629 transitions. Word has length 160 [2018-11-18 12:48:21,319 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 12:48:21,319 INFO L480 AbstractCegarLoop]: Abstraction has 1355 states and 1629 transitions. [2018-11-18 12:48:21,319 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-18 12:48:21,319 INFO L276 IsEmpty]: Start isEmpty. Operand 1355 states and 1629 transitions. [2018-11-18 12:48:21,321 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 161 [2018-11-18 12:48:21,321 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 12:48:21,321 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 12:48:21,322 INFO L423 AbstractCegarLoop]: === Iteration 17 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 12:48:21,322 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 12:48:21,322 INFO L82 PathProgramCache]: Analyzing trace with hash 1910713601, now seen corresponding path program 1 times [2018-11-18 12:48:21,322 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 12:48:21,322 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 12:48:21,323 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:21,323 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 12:48:21,323 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:21,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:48:21,360 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 34 trivial. 0 not checked. [2018-11-18 12:48:21,360 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 12:48:21,360 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 12:48:21,360 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-18 12:48:21,360 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 12:48:21,361 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 12:48:21,361 INFO L87 Difference]: Start difference. First operand 1355 states and 1629 transitions. Second operand 3 states. [2018-11-18 12:48:21,548 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 12:48:21,548 INFO L93 Difference]: Finished difference Result 3814 states and 4734 transitions. [2018-11-18 12:48:21,549 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 12:48:21,549 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 160 [2018-11-18 12:48:21,549 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 12:48:21,559 INFO L225 Difference]: With dead ends: 3814 [2018-11-18 12:48:21,559 INFO L226 Difference]: Without dead ends: 2481 [2018-11-18 12:48:21,563 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 12:48:21,565 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2481 states. [2018-11-18 12:48:21,736 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2481 to 2401. [2018-11-18 12:48:21,736 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2401 states. [2018-11-18 12:48:21,743 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2401 states to 2401 states and 2976 transitions. [2018-11-18 12:48:21,744 INFO L78 Accepts]: Start accepts. Automaton has 2401 states and 2976 transitions. Word has length 160 [2018-11-18 12:48:21,744 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 12:48:21,744 INFO L480 AbstractCegarLoop]: Abstraction has 2401 states and 2976 transitions. [2018-11-18 12:48:21,744 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-18 12:48:21,744 INFO L276 IsEmpty]: Start isEmpty. Operand 2401 states and 2976 transitions. [2018-11-18 12:48:21,749 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 162 [2018-11-18 12:48:21,749 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 12:48:21,749 INFO L375 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 12:48:21,749 INFO L423 AbstractCegarLoop]: === Iteration 18 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 12:48:21,749 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 12:48:21,749 INFO L82 PathProgramCache]: Analyzing trace with hash 976193949, now seen corresponding path program 1 times [2018-11-18 12:48:21,750 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 12:48:21,750 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 12:48:21,750 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:21,750 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 12:48:21,750 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:21,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:48:21,830 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 4 proven. 11 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-11-18 12:48:21,831 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 12:48:21,831 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_88f74cf4-b90d-49ed-8344-6ac0367bcb2b/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 12:48:21,840 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 12:48:21,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:48:21,920 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 12:48:21,954 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 33 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-11-18 12:48:21,977 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-18 12:48:21,977 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [6] total 7 [2018-11-18 12:48:21,978 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-18 12:48:21,978 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-18 12:48:21,978 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2018-11-18 12:48:21,978 INFO L87 Difference]: Start difference. First operand 2401 states and 2976 transitions. Second operand 7 states. [2018-11-18 12:48:22,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 12:48:22,693 INFO L93 Difference]: Finished difference Result 6231 states and 8161 transitions. [2018-11-18 12:48:22,694 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-18 12:48:22,695 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 161 [2018-11-18 12:48:22,695 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 12:48:22,709 INFO L225 Difference]: With dead ends: 6231 [2018-11-18 12:48:22,710 INFO L226 Difference]: Without dead ends: 3218 [2018-11-18 12:48:22,721 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 169 GetRequests, 163 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2018-11-18 12:48:22,724 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3218 states. [2018-11-18 12:48:22,973 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3218 to 3217. [2018-11-18 12:48:22,974 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3217 states. [2018-11-18 12:48:22,984 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3217 states to 3217 states and 3975 transitions. [2018-11-18 12:48:22,985 INFO L78 Accepts]: Start accepts. Automaton has 3217 states and 3975 transitions. Word has length 161 [2018-11-18 12:48:22,985 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 12:48:22,985 INFO L480 AbstractCegarLoop]: Abstraction has 3217 states and 3975 transitions. [2018-11-18 12:48:22,985 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-18 12:48:22,986 INFO L276 IsEmpty]: Start isEmpty. Operand 3217 states and 3975 transitions. [2018-11-18 12:48:22,997 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 334 [2018-11-18 12:48:22,997 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 12:48:22,997 INFO L375 BasicCegarLoop]: trace histogram [6, 6, 6, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 12:48:22,998 INFO L423 AbstractCegarLoop]: === Iteration 19 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 12:48:22,998 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 12:48:22,998 INFO L82 PathProgramCache]: Analyzing trace with hash -1542696181, now seen corresponding path program 1 times [2018-11-18 12:48:22,998 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 12:48:22,998 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 12:48:22,999 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:22,999 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 12:48:22,999 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:23,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:48:23,134 INFO L134 CoverageAnalysis]: Checked inductivity of 341 backedges. 38 proven. 53 refuted. 0 times theorem prover too weak. 250 trivial. 0 not checked. [2018-11-18 12:48:23,134 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-18 12:48:23,134 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_88f74cf4-b90d-49ed-8344-6ac0367bcb2b/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-18 12:48:23,145 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 12:48:23,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:48:23,250 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 12:48:23,300 INFO L134 CoverageAnalysis]: Checked inductivity of 341 backedges. 208 proven. 0 refuted. 0 times theorem prover too weak. 133 trivial. 0 not checked. [2018-11-18 12:48:23,316 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-18 12:48:23,316 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [5] total 6 [2018-11-18 12:48:23,317 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-18 12:48:23,317 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-18 12:48:23,317 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-18 12:48:23,317 INFO L87 Difference]: Start difference. First operand 3217 states and 3975 transitions. Second operand 6 states. [2018-11-18 12:48:23,970 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 12:48:23,970 INFO L93 Difference]: Finished difference Result 8311 states and 10656 transitions. [2018-11-18 12:48:23,970 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-18 12:48:23,970 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 333 [2018-11-18 12:48:23,971 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 12:48:23,985 INFO L225 Difference]: With dead ends: 8311 [2018-11-18 12:48:23,985 INFO L226 Difference]: Without dead ends: 5115 [2018-11-18 12:48:23,993 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 343 GetRequests, 337 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2018-11-18 12:48:23,996 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5115 states. [2018-11-18 12:48:24,219 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5115 to 5054. [2018-11-18 12:48:24,219 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5054 states. [2018-11-18 12:48:24,226 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5054 states to 5054 states and 6038 transitions. [2018-11-18 12:48:24,227 INFO L78 Accepts]: Start accepts. Automaton has 5054 states and 6038 transitions. Word has length 333 [2018-11-18 12:48:24,228 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 12:48:24,228 INFO L480 AbstractCegarLoop]: Abstraction has 5054 states and 6038 transitions. [2018-11-18 12:48:24,228 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-18 12:48:24,228 INFO L276 IsEmpty]: Start isEmpty. Operand 5054 states and 6038 transitions. [2018-11-18 12:48:24,232 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 216 [2018-11-18 12:48:24,232 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 12:48:24,232 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 12:48:24,233 INFO L423 AbstractCegarLoop]: === Iteration 20 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 12:48:24,233 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 12:48:24,233 INFO L82 PathProgramCache]: Analyzing trace with hash 1199111557, now seen corresponding path program 1 times [2018-11-18 12:48:24,233 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 12:48:24,233 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 12:48:24,234 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:24,234 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 12:48:24,234 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:24,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:48:24,281 INFO L134 CoverageAnalysis]: Checked inductivity of 115 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 81 trivial. 0 not checked. [2018-11-18 12:48:24,281 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 12:48:24,281 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-18 12:48:24,281 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-18 12:48:24,282 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-18 12:48:24,282 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-18 12:48:24,282 INFO L87 Difference]: Start difference. First operand 5054 states and 6038 transitions. Second operand 4 states. [2018-11-18 12:48:24,643 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 12:48:24,643 INFO L93 Difference]: Finished difference Result 8570 states and 10456 transitions. [2018-11-18 12:48:24,644 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-18 12:48:24,644 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 215 [2018-11-18 12:48:24,644 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-18 12:48:24,651 INFO L225 Difference]: With dead ends: 8570 [2018-11-18 12:48:24,652 INFO L226 Difference]: Without dead ends: 1852 [2018-11-18 12:48:24,664 INFO L604 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-18 12:48:24,665 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1852 states. [2018-11-18 12:48:24,804 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1852 to 1852. [2018-11-18 12:48:24,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1852 states. [2018-11-18 12:48:24,808 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1852 states to 1852 states and 2112 transitions. [2018-11-18 12:48:24,809 INFO L78 Accepts]: Start accepts. Automaton has 1852 states and 2112 transitions. Word has length 215 [2018-11-18 12:48:24,809 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-18 12:48:24,809 INFO L480 AbstractCegarLoop]: Abstraction has 1852 states and 2112 transitions. [2018-11-18 12:48:24,809 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-18 12:48:24,809 INFO L276 IsEmpty]: Start isEmpty. Operand 1852 states and 2112 transitions. [2018-11-18 12:48:24,813 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 217 [2018-11-18 12:48:24,813 INFO L367 BasicCegarLoop]: Found error trace [2018-11-18 12:48:24,813 INFO L375 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 12:48:24,813 INFO L423 AbstractCegarLoop]: === Iteration 21 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-18 12:48:24,813 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 12:48:24,814 INFO L82 PathProgramCache]: Analyzing trace with hash 652423787, now seen corresponding path program 1 times [2018-11-18 12:48:24,814 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 12:48:24,814 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 12:48:24,814 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:24,814 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 12:48:24,814 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 12:48:24,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 12:48:24,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 12:48:24,889 INFO L442 BasicCegarLoop]: Counterexample might be feasible [2018-11-18 12:48:24,976 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 18.11 12:48:24 BoogieIcfgContainer [2018-11-18 12:48:24,976 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-18 12:48:24,976 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-18 12:48:24,976 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-18 12:48:24,978 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-18 12:48:24,978 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 12:48:16" (3/4) ... [2018-11-18 12:48:24,980 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-11-18 12:48:25,076 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_88f74cf4-b90d-49ed-8344-6ac0367bcb2b/bin-2019/uautomizer/witness.graphml [2018-11-18 12:48:25,076 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-18 12:48:25,077 INFO L168 Benchmark]: Toolchain (without parser) took 9303.17 ms. Allocated memory was 1.0 GB in the beginning and 1.5 GB in the end (delta: 443.5 MB). Free memory was 959.2 MB in the beginning and 1.3 GB in the end (delta: -312.6 MB). Peak memory consumption was 131.0 MB. Max. memory is 11.5 GB. [2018-11-18 12:48:25,078 INFO L168 Benchmark]: CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 985.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 12:48:25,078 INFO L168 Benchmark]: CACSL2BoogieTranslator took 208.75 ms. Allocated memory is still 1.0 GB. Free memory was 959.2 MB in the beginning and 943.1 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. [2018-11-18 12:48:25,079 INFO L168 Benchmark]: Boogie Preprocessor took 64.68 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 141.0 MB). Free memory was 943.1 MB in the beginning and 1.1 GB in the end (delta: -195.4 MB). Peak memory consumption was 14.4 MB. Max. memory is 11.5 GB. [2018-11-18 12:48:25,080 INFO L168 Benchmark]: RCFGBuilder took 415.24 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 38.7 MB). Peak memory consumption was 38.7 MB. Max. memory is 11.5 GB. [2018-11-18 12:48:25,080 INFO L168 Benchmark]: TraceAbstraction took 8511.84 ms. Allocated memory was 1.2 GB in the beginning and 1.5 GB in the end (delta: 302.5 MB). Free memory was 1.1 GB in the beginning and 1.3 GB in the end (delta: -195.1 MB). Peak memory consumption was 107.4 MB. Max. memory is 11.5 GB. [2018-11-18 12:48:25,080 INFO L168 Benchmark]: Witness Printer took 99.75 ms. Allocated memory is still 1.5 GB. Free memory was 1.3 GB in the beginning and 1.3 GB in the end (delta: 23.1 MB). Peak memory consumption was 23.1 MB. Max. memory is 11.5 GB. [2018-11-18 12:48:25,082 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 985.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 208.75 ms. Allocated memory is still 1.0 GB. Free memory was 959.2 MB in the beginning and 943.1 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 64.68 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 141.0 MB). Free memory was 943.1 MB in the beginning and 1.1 GB in the end (delta: -195.4 MB). Peak memory consumption was 14.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 415.24 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 38.7 MB). Peak memory consumption was 38.7 MB. Max. memory is 11.5 GB. * TraceAbstraction took 8511.84 ms. Allocated memory was 1.2 GB in the beginning and 1.5 GB in the end (delta: 302.5 MB). Free memory was 1.1 GB in the beginning and 1.3 GB in the end (delta: -195.1 MB). Peak memory consumption was 107.4 MB. Max. memory is 11.5 GB. * Witness Printer took 99.75 ms. Allocated memory is still 1.5 GB. Free memory was 1.3 GB in the beginning and 1.3 GB in the end (delta: 23.1 MB). Peak memory consumption was 23.1 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 11]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int m_st ; [L19] int t1_st ; [L20] int t2_st ; [L21] int m_i ; [L22] int t1_i ; [L23] int t2_i ; [L24] int M_E = 2; [L25] int T1_E = 2; [L26] int T2_E = 2; [L27] int E_1 = 2; [L28] int E_2 = 2; VAL [\old(E_1)=16, \old(E_2)=5, \old(M_E)=13, \old(m_i)=7, \old(m_pc)=11, \old(m_st)=12, \old(T1_E)=3, \old(t1_i)=15, \old(t1_pc)=8, \old(t1_st)=4, \old(T2_E)=14, \old(t2_i)=6, \old(t2_pc)=9, \old(t2_st)=10, E_1=2, E_2=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0] [L563] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0] [L567] CALL init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0] [L477] m_i = 1 [L478] t1_i = 1 [L479] RET t2_i = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L567] init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L568] CALL start_simulation() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L504] int kernel_st ; [L505] int tmp ; [L506] int tmp___0 ; [L510] kernel_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L511] FCALL update_channels() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L512] CALL init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L211] COND TRUE m_i == 1 [L212] m_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L216] COND TRUE t1_i == 1 [L217] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L221] COND TRUE t2_i == 1 [L222] RET t2_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L512] init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L513] CALL fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L324] COND FALSE !(M_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L329] COND FALSE !(T1_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L334] COND FALSE !(T2_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L339] COND FALSE !(E_1 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L344] COND FALSE, RET !(E_2 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L513] fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L514] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L387] int tmp ; [L388] int tmp___0 ; [L389] int tmp___1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L393] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L143] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L146] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L156] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, __retres1=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L158] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L393] EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L393] tmp = is_master_triggered() [L395] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0] [L401] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L162] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L165] COND FALSE !(t1_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L175] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, __retres1=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L177] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L401] EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0] [L401] tmp___0 = is_transmit1_triggered() [L403] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0, tmp___0=0] [L409] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L181] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L184] COND FALSE !(t2_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L194] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, __retres1=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L196] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L409] EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0, tmp___0=0] [L409] tmp___1 = is_transmit2_triggered() [L411] COND FALSE, RET !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0, tmp___0=0, tmp___1=0] [L514] activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L515] CALL reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L357] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L362] COND FALSE !(T1_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L367] COND FALSE !(T2_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L372] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L377] COND FALSE, RET !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L515] reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L518] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L521] kernel_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L522] CALL eval() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L257] int tmp ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L261] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L264] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L231] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L234] COND TRUE m_st == 0 [L235] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, __retres1=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L252] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L264] EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L264] tmp = exists_runnable_thread() [L266] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=1] [L271] COND TRUE m_st == 0 [L272] int tmp_ndt_1; [L273] tmp_ndt_1 = __VERIFIER_nondet_int() [L274] COND FALSE !(\read(tmp_ndt_1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=1, tmp_ndt_1=0] [L285] COND TRUE t1_st == 0 [L286] int tmp_ndt_2; [L287] tmp_ndt_2 = __VERIFIER_nondet_int() [L288] COND TRUE \read(tmp_ndt_2) [L290] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1] [L291] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L78] COND TRUE t1_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L89] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L91] t1_pc = 1 [L92] RET t1_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L291] transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1] [L299] COND TRUE t2_st == 0 [L300] int tmp_ndt_3; [L301] tmp_ndt_3 = __VERIFIER_nondet_int() [L302] COND TRUE \read(tmp_ndt_3) [L304] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L305] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1] [L113] COND TRUE t2_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1] [L124] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1] [L126] t2_pc = 1 [L127] RET t2_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L305] transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L261] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L264] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L231] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L234] COND TRUE m_st == 0 [L235] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, __retres1=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L252] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L264] EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L264] tmp = exists_runnable_thread() [L266] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=1, tmp_ndt_3=1] [L271] COND TRUE m_st == 0 [L272] int tmp_ndt_1; [L273] tmp_ndt_1 = __VERIFIER_nondet_int() [L274] COND TRUE \read(tmp_ndt_1) [L276] m_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1] [L277] CALL master() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L37] COND TRUE m_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L48] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L51] E_1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L52] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L425] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L387] int tmp ; [L388] int tmp___0 ; [L389] int tmp___1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L393] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L143] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L146] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L156] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=0, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L158] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L393] EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L393] tmp = is_master_triggered() [L395] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0] [L401] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L162] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L165] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L166] COND TRUE E_1 == 1 [L167] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=1, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L177] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \result=1, __retres1=1, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L401] EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, is_transmit1_triggered()=1, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0] [L401] tmp___0 = is_transmit1_triggered() [L403] COND TRUE \read(tmp___0) [L404] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0, tmp___0=1] [L409] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L181] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L184] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L185] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L194] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=0, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L196] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L409] EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0, tmp___0=1] [L409] tmp___1 = is_transmit2_triggered() [L411] COND FALSE, RET !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0, tmp___0=1, tmp___1=0] [L425] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L52] immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L53] E_1 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L56] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L58] m_pc = 1 [L59] RET m_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L277] master() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1] [L285] COND TRUE t1_st == 0 [L286] int tmp_ndt_2; [L287] tmp_ndt_2 = __VERIFIER_nondet_int() [L288] COND TRUE \read(tmp_ndt_2) [L290] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1] [L291] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L78] COND FALSE !(t1_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L81] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L97] E_2 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L98] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L425] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L387] int tmp ; [L388] int tmp___0 ; [L389] int tmp___1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L393] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L143] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L146] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L147] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L156] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=0, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L158] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L393] EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L393] tmp = is_master_triggered() [L395] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0] [L401] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L162] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L165] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L166] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L175] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=0, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L177] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L401] EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0] [L401] tmp___0 = is_transmit1_triggered() [L403] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0, tmp___0=0] [L409] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L181] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L184] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L185] COND TRUE E_2 == 1 [L186] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=1, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L196] RET return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \result=1, __retres1=1, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L409] EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, is_transmit2_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0, tmp___0=0] [L409] tmp___1 = is_transmit2_triggered() [L411] COND TRUE \read(tmp___1) [L412] RET t2_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, tmp=0, tmp___0=0, tmp___1=1] [L425] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0] [L98] immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0] [L99] E_2 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0] [L89] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0] [L91] t1_pc = 1 [L92] RET t1_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0] [L291] transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1] [L299] COND TRUE t2_st == 0 [L300] int tmp_ndt_3; [L301] tmp_ndt_3 = __VERIFIER_nondet_int() [L302] COND TRUE \read(tmp_ndt_3) [L304] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, tmp=1, tmp_ndt_1=1, tmp_ndt_2=1, tmp_ndt_3=1] [L305] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1] [L113] COND FALSE !(t2_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1] [L116] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1] [L132] CALL error() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1] [L11] __VERIFIER_error() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 23 procedures, 175 locations, 1 error locations. UNSAFE Result, 8.4s OverallTime, 21 OverallIterations, 6 TraceHistogramMax, 5.0s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 4895 SDtfs, 5502 SDslu, 4897 SDs, 0 SdLazy, 3729 SolverSat, 1423 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 2.5s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 762 GetRequests, 663 SyntacticMatches, 24 SemanticMatches, 75 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.5s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=5054occurred in iteration=19, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 1.3s AutomataMinimizationTime, 20 MinimizatonAttempts, 521 StatesRemovedByMinimization, 14 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.1s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 1.0s InterpolantComputationTime, 3403 NumberOfCodeBlocks, 3403 NumberOfCodeBlocksAsserted, 24 NumberOfCheckSat, 3164 ConstructedInterpolants, 0 QuantifiedInterpolants, 717044 SizeOfPredicates, 0 NumberOfNonLiveVariables, 2315 ConjunctsInSsa, 9 ConjunctsInUnsatCore, 23 InterpolantComputations, 20 PerfectInterpolantSequences, 1061/1128 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...