./Ultimate.py --spec ../../sv-benchmarks/c/Termination.prp --file ../../sv-benchmarks/c/systemc/pc_sfifo_3_true-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 5842f4b8 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_95d36298-be4d-4da0-9c15-8f225f569199/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_95d36298-be4d-4da0-9c15-8f225f569199/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_95d36298-be4d-4da0-9c15-8f225f569199/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_95d36298-be4d-4da0-9c15-8f225f569199/bin-2019/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/pc_sfifo_3_true-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_95d36298-be4d-4da0-9c15-8f225f569199/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_95d36298-be4d-4da0-9c15-8f225f569199/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 0cd94be4ea5743b633f1f4a5c7ddfdb38e323c6d ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.23-5842f4b [2018-11-18 11:44:33,844 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-18 11:44:33,845 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-18 11:44:33,853 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-18 11:44:33,854 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-18 11:44:33,854 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-18 11:44:33,855 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-18 11:44:33,856 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-18 11:44:33,857 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-18 11:44:33,858 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-18 11:44:33,859 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-18 11:44:33,859 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-18 11:44:33,859 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-18 11:44:33,860 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-18 11:44:33,861 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-18 11:44:33,861 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-18 11:44:33,862 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-18 11:44:33,863 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-18 11:44:33,864 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-18 11:44:33,866 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-18 11:44:33,866 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-18 11:44:33,867 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-18 11:44:33,869 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-18 11:44:33,869 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-18 11:44:33,869 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-18 11:44:33,870 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-18 11:44:33,871 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-18 11:44:33,871 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-18 11:44:33,872 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-18 11:44:33,872 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-18 11:44:33,873 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-18 11:44:33,874 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-18 11:44:33,874 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-18 11:44:33,874 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-18 11:44:33,874 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-18 11:44:33,875 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-18 11:44:33,875 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_95d36298-be4d-4da0-9c15-8f225f569199/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2018-11-18 11:44:33,886 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-18 11:44:33,886 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-18 11:44:33,887 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-18 11:44:33,887 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-18 11:44:33,887 INFO L133 SettingsManager]: * Use SBE=true [2018-11-18 11:44:33,888 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2018-11-18 11:44:33,888 INFO L133 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2018-11-18 11:44:33,888 INFO L133 SettingsManager]: * Use old map elimination=false [2018-11-18 11:44:33,888 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false [2018-11-18 11:44:33,888 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true [2018-11-18 11:44:33,888 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2018-11-18 11:44:33,888 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-18 11:44:33,889 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-18 11:44:33,889 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-18 11:44:33,889 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-18 11:44:33,890 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-18 11:44:33,890 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-18 11:44:33,890 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2018-11-18 11:44:33,891 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2018-11-18 11:44:33,891 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2018-11-18 11:44:33,891 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-18 11:44:33,891 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-18 11:44:33,891 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false [2018-11-18 11:44:33,891 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-18 11:44:33,891 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2018-11-18 11:44:33,892 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-18 11:44:33,892 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-18 11:44:33,892 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2018-11-18 11:44:33,892 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-18 11:44:33,892 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-18 11:44:33,892 INFO L133 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2018-11-18 11:44:33,893 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-11-18 11:44:33,893 INFO L133 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_95d36298-be4d-4da0-9c15-8f225f569199/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 0cd94be4ea5743b633f1f4a5c7ddfdb38e323c6d [2018-11-18 11:44:33,915 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-18 11:44:33,924 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-18 11:44:33,927 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-18 11:44:33,928 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-18 11:44:33,928 INFO L276 PluginConnector]: CDTParser initialized [2018-11-18 11:44:33,929 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_95d36298-be4d-4da0-9c15-8f225f569199/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/pc_sfifo_3_true-unreach-call_false-termination.cil.c [2018-11-18 11:44:33,972 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_95d36298-be4d-4da0-9c15-8f225f569199/bin-2019/uautomizer/data/842db12ff/74b917a1b066483795e28f968c161b74/FLAG11ed73cdd [2018-11-18 11:44:34,317 INFO L307 CDTParser]: Found 1 translation units. [2018-11-18 11:44:34,318 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_95d36298-be4d-4da0-9c15-8f225f569199/sv-benchmarks/c/systemc/pc_sfifo_3_true-unreach-call_false-termination.cil.c [2018-11-18 11:44:34,325 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_95d36298-be4d-4da0-9c15-8f225f569199/bin-2019/uautomizer/data/842db12ff/74b917a1b066483795e28f968c161b74/FLAG11ed73cdd [2018-11-18 11:44:34,731 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_95d36298-be4d-4da0-9c15-8f225f569199/bin-2019/uautomizer/data/842db12ff/74b917a1b066483795e28f968c161b74 [2018-11-18 11:44:34,733 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-18 11:44:34,733 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-18 11:44:34,734 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-18 11:44:34,734 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-18 11:44:34,737 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-18 11:44:34,737 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 11:44:34" (1/1) ... [2018-11-18 11:44:34,739 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@77c97579 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 11:44:34, skipping insertion in model container [2018-11-18 11:44:34,740 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 11:44:34" (1/1) ... [2018-11-18 11:44:34,745 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-18 11:44:34,768 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-18 11:44:34,919 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 11:44:34,922 INFO L191 MainTranslator]: Completed pre-run [2018-11-18 11:44:34,945 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 11:44:34,955 INFO L195 MainTranslator]: Completed translation [2018-11-18 11:44:34,955 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 11:44:34 WrapperNode [2018-11-18 11:44:34,955 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-18 11:44:34,955 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-18 11:44:34,956 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-18 11:44:34,956 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-18 11:44:34,960 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 11:44:34" (1/1) ... [2018-11-18 11:44:34,964 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 11:44:34" (1/1) ... [2018-11-18 11:44:35,021 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-18 11:44:35,021 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-18 11:44:35,021 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-18 11:44:35,021 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-18 11:44:35,026 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 11:44:34" (1/1) ... [2018-11-18 11:44:35,027 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 11:44:34" (1/1) ... [2018-11-18 11:44:35,028 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 11:44:34" (1/1) ... [2018-11-18 11:44:35,029 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 11:44:34" (1/1) ... [2018-11-18 11:44:35,033 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 11:44:34" (1/1) ... [2018-11-18 11:44:35,039 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 11:44:34" (1/1) ... [2018-11-18 11:44:35,041 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 11:44:34" (1/1) ... [2018-11-18 11:44:35,043 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-18 11:44:35,044 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-18 11:44:35,044 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-18 11:44:35,044 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-18 11:44:35,045 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 11:44:34" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_95d36298-be4d-4da0-9c15-8f225f569199/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 11:44:35,085 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-18 11:44:35,085 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-18 11:44:35,446 INFO L278 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-18 11:44:35,446 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 11:44:35 BoogieIcfgContainer [2018-11-18 11:44:35,446 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-18 11:44:35,447 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2018-11-18 11:44:35,447 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2018-11-18 11:44:35,449 INFO L276 PluginConnector]: BuchiAutomizer initialized [2018-11-18 11:44:35,449 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 11:44:35,450 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 18.11 11:44:34" (1/3) ... [2018-11-18 11:44:35,450 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@13a79437 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 11:44:35, skipping insertion in model container [2018-11-18 11:44:35,450 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 11:44:35,450 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 11:44:34" (2/3) ... [2018-11-18 11:44:35,451 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@13a79437 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 11:44:35, skipping insertion in model container [2018-11-18 11:44:35,451 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 11:44:35,451 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 11:44:35" (3/3) ... [2018-11-18 11:44:35,452 INFO L375 chiAutomizerObserver]: Analyzing ICFG pc_sfifo_3_true-unreach-call_false-termination.cil.c [2018-11-18 11:44:35,483 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-18 11:44:35,484 INFO L374 BuchiCegarLoop]: Interprodecural is true [2018-11-18 11:44:35,484 INFO L375 BuchiCegarLoop]: Hoare is false [2018-11-18 11:44:35,484 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2018-11-18 11:44:35,484 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-18 11:44:35,484 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-18 11:44:35,484 INFO L379 BuchiCegarLoop]: Difference is false [2018-11-18 11:44:35,484 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-18 11:44:35,484 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2018-11-18 11:44:35,497 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 146 states. [2018-11-18 11:44:35,518 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 106 [2018-11-18 11:44:35,518 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:44:35,518 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:44:35,524 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:44:35,524 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:44:35,525 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ [2018-11-18 11:44:35,525 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 146 states. [2018-11-18 11:44:35,528 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 106 [2018-11-18 11:44:35,528 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:44:35,528 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:44:35,529 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:44:35,529 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:44:35,535 INFO L794 eck$LassoCheckResult]: Stem: 105#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 14#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 16#L541true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~4, start_simulation_~tmp___0~3;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~4;havoc start_simulation_~tmp___0~3;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 84#L248true assume !(1 == ~q_req_up~0); 79#L248-2true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9#L263true assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 5#L263-2true assume !(1 == ~c_dr_i~0);~c_dr_st~0 := 2; 47#L268-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 54#L301true assume !(0 == ~q_read_ev~0); 48#L301-2true assume !(0 == ~q_write_ev~0); 68#L306-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 56#L56true assume 1 == ~p_dw_pc~0; 148#L57true assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0 := 1; 112#L77true is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 58#L78true activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 90#L377true assume !(0 != activate_threads_~tmp~1); 95#L377-2true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 127#L85true assume 1 == ~c_dr_pc~0; 67#L86true assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1 := 1; 25#L106true is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 130#L107true activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 122#L385true assume !(0 != activate_threads_~tmp___0~1); 123#L385-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 124#L319true assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 107#L319-2true assume !(1 == ~q_write_ev~0); 133#L324-1true assume { :end_inline_reset_delta_events } true; 128#L481-3true [2018-11-18 11:44:35,535 INFO L796 eck$LassoCheckResult]: Loop: 128#L481-3true assume true; 139#L481-1true assume !false; 72#L482true start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5, eval_#t~nondet6, eval_#t~nondet7, eval_~tmp~2, eval_~tmp___0~2, eval_~tmp___1~0;havoc eval_~tmp~2;havoc eval_~tmp___0~2;havoc eval_~tmp___1~0; 26#L425true assume !true; 60#L441true assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 77#L248-3true assume !(1 == ~q_req_up~0); 63#L248-5true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 44#L301-3true assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 23#L301-5true assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 70#L306-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 45#L56-3true assume 1 == ~p_dw_pc~0; 147#L57-1true assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0 := 1; 109#L77-1true is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 55#L78-1true activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 98#L377-3true assume 0 != activate_threads_~tmp~1;~p_dw_st~0 := 0; 76#L377-5true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 96#L85-3true assume 1 == ~c_dr_pc~0; 65#L86-1true assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1 := 1; 13#L106-1true is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 126#L107-1true activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 104#L385-3true assume 0 != activate_threads_~tmp___0~1;~c_dr_st~0 := 0; 110#L385-5true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 111#L319-3true assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 117#L319-5true assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 136#L324-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 85#L281-1true assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2 := 1; 35#L293-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 118#L294-1true start_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 141#L500true assume !(0 == start_simulation_~tmp~4); 144#L500-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~3, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~3;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 82#L281-2true assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2 := 1; 33#L293-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 132#L294-2true stop_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 51#L455true assume 0 != stop_simulation_~tmp~3;stop_simulation_~__retres2~0 := 0; 119#L462true stop_simulation_#res := stop_simulation_~__retres2~0; 71#L463true start_simulation_#t~ret10 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 38#L513true assume !(0 != start_simulation_~tmp___0~3); 128#L481-3true [2018-11-18 11:44:35,539 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:44:35,539 INFO L82 PathProgramCache]: Analyzing trace with hash 854607455, now seen corresponding path program 1 times [2018-11-18 11:44:35,540 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:44:35,541 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:44:35,570 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:35,570 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:44:35,570 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:35,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:44:35,637 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:44:35,639 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:44:35,639 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 11:44:35,643 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 11:44:35,643 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:44:35,643 INFO L82 PathProgramCache]: Analyzing trace with hash -2110002708, now seen corresponding path program 1 times [2018-11-18 11:44:35,643 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:44:35,644 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:44:35,644 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:35,644 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:44:35,645 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:35,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:44:35,655 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:44:35,655 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:44:35,655 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 11:44:35,656 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 11:44:35,672 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 11:44:35,672 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 11:44:35,674 INFO L87 Difference]: Start difference. First operand 146 states. Second operand 3 states. [2018-11-18 11:44:35,691 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:44:35,691 INFO L93 Difference]: Finished difference Result 144 states and 211 transitions. [2018-11-18 11:44:35,692 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 11:44:35,693 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 144 states and 211 transitions. [2018-11-18 11:44:35,695 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 102 [2018-11-18 11:44:35,698 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 144 states to 138 states and 205 transitions. [2018-11-18 11:44:35,699 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 138 [2018-11-18 11:44:35,699 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 138 [2018-11-18 11:44:35,700 INFO L73 IsDeterministic]: Start isDeterministic. Operand 138 states and 205 transitions. [2018-11-18 11:44:35,700 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:44:35,701 INFO L705 BuchiCegarLoop]: Abstraction has 138 states and 205 transitions. [2018-11-18 11:44:35,715 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 138 states and 205 transitions. [2018-11-18 11:44:35,723 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 138 to 138. [2018-11-18 11:44:35,724 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 138 states. [2018-11-18 11:44:35,725 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 138 states to 138 states and 205 transitions. [2018-11-18 11:44:35,726 INFO L728 BuchiCegarLoop]: Abstraction has 138 states and 205 transitions. [2018-11-18 11:44:35,726 INFO L608 BuchiCegarLoop]: Abstraction has 138 states and 205 transitions. [2018-11-18 11:44:35,726 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ [2018-11-18 11:44:35,726 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 138 states and 205 transitions. [2018-11-18 11:44:35,728 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 102 [2018-11-18 11:44:35,728 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:44:35,728 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:44:35,729 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:44:35,729 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:44:35,730 INFO L794 eck$LassoCheckResult]: Stem: 422#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 318#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 319#L541 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~4, start_simulation_~tmp___0~3;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~4;havoc start_simulation_~tmp___0~3;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 320#L248 assume !(1 == ~q_req_up~0); 389#L248-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 311#L263 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 303#L263-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 304#L268-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 366#L301 assume !(0 == ~q_read_ev~0); 367#L301-2 assume !(0 == ~q_write_ev~0); 368#L306-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 380#L56 assume 1 == ~p_dw_pc~0; 381#L57 assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0 := 1; 382#L77 is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 383#L78 activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 384#L377 assume !(0 != activate_threads_~tmp~1); 411#L377-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 415#L85 assume 1 == ~c_dr_pc~0; 395#L86 assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1 := 1; 316#L106 is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 337#L107 activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 431#L385 assume !(0 != activate_threads_~tmp___0~1); 432#L385-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 433#L319 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 423#L319-2 assume !(1 == ~q_write_ev~0); 424#L324-1 assume { :end_inline_reset_delta_events } true; 356#L481-3 [2018-11-18 11:44:35,730 INFO L796 eck$LassoCheckResult]: Loop: 356#L481-3 assume true; 434#L481-1 assume !false; 398#L482 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5, eval_#t~nondet6, eval_#t~nondet7, eval_~tmp~2, eval_~tmp___0~2, eval_~tmp___1~0;havoc eval_~tmp~2;havoc eval_~tmp___0~2;havoc eval_~tmp___1~0; 338#L425 assume true; 339#L400-1 assume !false; 385#L401 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 408#L281 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2 := 1; 313#L293 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 326#L294 eval_#t~ret5 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0 := eval_#t~ret5;havoc eval_#t~ret5; 399#L405 assume !(0 != eval_~tmp___1~0); 386#L441 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 387#L248-3 assume !(1 == ~q_req_up~0); 388#L248-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 362#L301-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 332#L301-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 333#L306-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 363#L56-3 assume 1 == ~p_dw_pc~0; 364#L57-1 assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0 := 1; 377#L77-1 is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 378#L78-1 activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 379#L377-3 assume 0 != activate_threads_~tmp~1;~p_dw_st~0 := 0; 401#L377-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 402#L85-3 assume 1 == ~c_dr_pc~0; 391#L86-1 assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1 := 1; 310#L106-1 is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 317#L107-1 activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 420#L385-3 assume 0 != activate_threads_~tmp___0~1;~c_dr_st~0 := 0; 421#L385-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 425#L319-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 426#L319-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 427#L324-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 407#L281-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2 := 1; 308#L293-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 351#L294-1 start_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 429#L500 assume !(0 == start_simulation_~tmp~4); 435#L500-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~3, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~3;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 405#L281-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2 := 1; 306#L293-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 349#L294-2 stop_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 373#L455 assume 0 != stop_simulation_~tmp~3;stop_simulation_~__retres2~0 := 0; 374#L462 stop_simulation_#res := stop_simulation_~__retres2~0; 397#L463 start_simulation_#t~ret10 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 355#L513 assume !(0 != start_simulation_~tmp___0~3); 356#L481-3 [2018-11-18 11:44:35,730 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:44:35,730 INFO L82 PathProgramCache]: Analyzing trace with hash 1672255905, now seen corresponding path program 1 times [2018-11-18 11:44:35,730 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:44:35,730 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:44:35,731 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:35,731 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:44:35,731 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:35,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:44:35,767 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:44:35,767 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:44:35,767 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 11:44:35,767 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 11:44:35,767 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:44:35,767 INFO L82 PathProgramCache]: Analyzing trace with hash -6188398, now seen corresponding path program 1 times [2018-11-18 11:44:35,767 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:44:35,767 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:44:35,768 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:35,768 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:44:35,768 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:35,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:44:35,823 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:44:35,823 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:44:35,823 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 11:44:35,824 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 11:44:35,824 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 11:44:35,824 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 11:44:35,824 INFO L87 Difference]: Start difference. First operand 138 states and 205 transitions. cyclomatic complexity: 68 Second operand 3 states. [2018-11-18 11:44:35,867 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:44:35,867 INFO L93 Difference]: Finished difference Result 231 states and 332 transitions. [2018-11-18 11:44:35,868 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 11:44:35,868 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 231 states and 332 transitions. [2018-11-18 11:44:35,870 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 194 [2018-11-18 11:44:35,872 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 231 states to 231 states and 332 transitions. [2018-11-18 11:44:35,872 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 231 [2018-11-18 11:44:35,872 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 231 [2018-11-18 11:44:35,872 INFO L73 IsDeterministic]: Start isDeterministic. Operand 231 states and 332 transitions. [2018-11-18 11:44:35,874 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:44:35,874 INFO L705 BuchiCegarLoop]: Abstraction has 231 states and 332 transitions. [2018-11-18 11:44:35,875 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 231 states and 332 transitions. [2018-11-18 11:44:35,884 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 231 to 228. [2018-11-18 11:44:35,884 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 228 states. [2018-11-18 11:44:35,886 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 228 states to 228 states and 329 transitions. [2018-11-18 11:44:35,886 INFO L728 BuchiCegarLoop]: Abstraction has 228 states and 329 transitions. [2018-11-18 11:44:35,886 INFO L608 BuchiCegarLoop]: Abstraction has 228 states and 329 transitions. [2018-11-18 11:44:35,886 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ [2018-11-18 11:44:35,886 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 228 states and 329 transitions. [2018-11-18 11:44:35,887 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 191 [2018-11-18 11:44:35,888 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:44:35,888 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:44:35,889 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:44:35,889 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:44:35,890 INFO L794 eck$LassoCheckResult]: Stem: 804#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 696#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 697#L541 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~4, start_simulation_~tmp___0~3;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~4;havoc start_simulation_~tmp___0~3;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 698#L248 assume !(1 == ~q_req_up~0); 765#L248-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 689#L263 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 681#L263-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 682#L268-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 740#L301 assume !(0 == ~q_read_ev~0); 741#L301-2 assume !(0 == ~q_write_ev~0); 742#L306-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 757#L56 assume !(1 == ~p_dw_pc~0); 743#L56-2 assume !(2 == ~p_dw_pc~0); 744#L66-1 is_do_write_p_triggered_~__retres1~0 := 0; 807#L77 is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 758#L78 activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 759#L377 assume !(0 != activate_threads_~tmp~1); 790#L377-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 795#L85 assume 1 == ~c_dr_pc~0; 771#L86 assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1 := 1; 694#L106 is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 714#L107 activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 815#L385 assume !(0 != activate_threads_~tmp___0~1); 816#L385-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 817#L319 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 805#L319-2 assume !(1 == ~q_write_ev~0); 806#L324-1 assume { :end_inline_reset_delta_events } true; 731#L481-3 [2018-11-18 11:44:35,890 INFO L796 eck$LassoCheckResult]: Loop: 731#L481-3 assume true; 819#L481-1 assume !false; 774#L482 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5, eval_#t~nondet6, eval_#t~nondet7, eval_~tmp~2, eval_~tmp___0~2, eval_~tmp___1~0;havoc eval_~tmp~2;havoc eval_~tmp___0~2;havoc eval_~tmp___1~0; 712#L425 assume true; 713#L400-1 assume !false; 861#L401 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 858#L281 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2 := 1; 703#L293 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 704#L294 eval_#t~ret5 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0 := eval_#t~ret5;havoc eval_#t~ret5; 776#L405 assume !(0 != eval_~tmp___1~0); 762#L441 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 763#L248-3 assume !(1 == ~q_req_up~0); 764#L248-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 737#L301-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 708#L301-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 709#L306-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 738#L56-3 assume !(1 == ~p_dw_pc~0); 710#L56-5 assume !(2 == ~p_dw_pc~0); 711#L66-3 is_do_write_p_triggered_~__retres1~0 := 0; 801#L77-1 is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 755#L78-1 activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 756#L377-3 assume 0 != activate_threads_~tmp~1;~p_dw_st~0 := 0; 778#L377-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 779#L85-3 assume 1 == ~c_dr_pc~0; 796#L86-1 assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1 := 1; 900#L106-1 is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 863#L107-1 activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 862#L385-3 assume 0 != activate_threads_~tmp___0~1;~c_dr_st~0 := 0; 808#L385-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 809#L319-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 810#L319-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 812#L324-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 784#L281-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2 := 1; 688#L293-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 726#L294-1 start_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 813#L500 assume !(0 == start_simulation_~tmp~4); 820#L500-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~3, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~3;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 782#L281-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2 := 1; 684#L293-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 724#L294-2 stop_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 748#L455 assume 0 != stop_simulation_~tmp~3;stop_simulation_~__retres2~0 := 0; 749#L462 stop_simulation_#res := stop_simulation_~__retres2~0; 773#L463 start_simulation_#t~ret10 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 730#L513 assume !(0 != start_simulation_~tmp___0~3); 731#L481-3 [2018-11-18 11:44:35,891 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:44:35,891 INFO L82 PathProgramCache]: Analyzing trace with hash -841270075, now seen corresponding path program 1 times [2018-11-18 11:44:35,891 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:44:35,891 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:44:35,892 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:35,892 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:44:35,892 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:35,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:44:35,920 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:44:35,920 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:44:35,920 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 11:44:35,920 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 11:44:35,921 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:44:35,921 INFO L82 PathProgramCache]: Analyzing trace with hash 390716959, now seen corresponding path program 1 times [2018-11-18 11:44:35,921 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:44:35,921 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:44:35,922 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:35,922 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:44:35,922 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:35,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:44:35,957 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:44:35,958 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:44:35,958 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 11:44:35,958 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 11:44:35,958 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 11:44:35,958 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 11:44:35,959 INFO L87 Difference]: Start difference. First operand 228 states and 329 transitions. cyclomatic complexity: 103 Second operand 3 states. [2018-11-18 11:44:36,013 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:44:36,014 INFO L93 Difference]: Finished difference Result 402 states and 568 transitions. [2018-11-18 11:44:36,014 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 11:44:36,014 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 402 states and 568 transitions. [2018-11-18 11:44:36,017 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 360 [2018-11-18 11:44:36,019 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 402 states to 402 states and 568 transitions. [2018-11-18 11:44:36,019 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 402 [2018-11-18 11:44:36,020 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 402 [2018-11-18 11:44:36,020 INFO L73 IsDeterministic]: Start isDeterministic. Operand 402 states and 568 transitions. [2018-11-18 11:44:36,021 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:44:36,021 INFO L705 BuchiCegarLoop]: Abstraction has 402 states and 568 transitions. [2018-11-18 11:44:36,022 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 402 states and 568 transitions. [2018-11-18 11:44:36,030 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 402 to 396. [2018-11-18 11:44:36,031 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 396 states. [2018-11-18 11:44:36,032 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 396 states to 396 states and 562 transitions. [2018-11-18 11:44:36,032 INFO L728 BuchiCegarLoop]: Abstraction has 396 states and 562 transitions. [2018-11-18 11:44:36,032 INFO L608 BuchiCegarLoop]: Abstraction has 396 states and 562 transitions. [2018-11-18 11:44:36,032 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ [2018-11-18 11:44:36,032 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 396 states and 562 transitions. [2018-11-18 11:44:36,034 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 354 [2018-11-18 11:44:36,034 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:44:36,034 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:44:36,035 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:44:36,035 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:44:36,035 INFO L794 eck$LassoCheckResult]: Stem: 1445#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 1335#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 1336#L541 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~4, start_simulation_~tmp___0~3;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~4;havoc start_simulation_~tmp___0~3;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 1337#L248 assume !(1 == ~q_req_up~0); 1405#L248-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1328#L263 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 1320#L263-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 1321#L268-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1381#L301 assume !(0 == ~q_read_ev~0); 1382#L301-2 assume !(0 == ~q_write_ev~0); 1383#L306-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 1398#L56 assume !(1 == ~p_dw_pc~0); 1384#L56-2 assume !(2 == ~p_dw_pc~0); 1385#L66-1 is_do_write_p_triggered_~__retres1~0 := 0; 1448#L77 is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 1399#L78 activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 1400#L377 assume !(0 != activate_threads_~tmp~1); 1432#L377-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 1435#L85 assume !(1 == ~c_dr_pc~0); 1438#L85-2 assume !(2 == ~c_dr_pc~0); 1332#L95-1 is_do_read_c_triggered_~__retres1~1 := 0; 1333#L106 is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 1350#L107 activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 1455#L385 assume !(0 != activate_threads_~tmp___0~1); 1456#L385-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1457#L319 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 1446#L319-2 assume !(1 == ~q_write_ev~0); 1447#L324-1 assume { :end_inline_reset_delta_events } true; 1462#L481-3 [2018-11-18 11:44:36,035 INFO L796 eck$LassoCheckResult]: Loop: 1462#L481-3 assume true; 1649#L481-1 assume !false; 1643#L482 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5, eval_#t~nondet6, eval_#t~nondet7, eval_~tmp~2, eval_~tmp___0~2, eval_~tmp___1~0;havoc eval_~tmp~2;havoc eval_~tmp___0~2;havoc eval_~tmp___1~0; 1642#L425 assume true; 1641#L400-1 assume !false; 1640#L401 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 1493#L281 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2 := 1; 1494#L293 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 1486#L294 eval_#t~ret5 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0 := eval_#t~ret5;havoc eval_#t~ret5; 1487#L405 assume !(0 != eval_~tmp___1~0); 1520#L441 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 1685#L248-3 assume !(1 == ~q_req_up~0); 1682#L248-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 1680#L301-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 1679#L301-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 1678#L306-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 1677#L56-3 assume !(1 == ~p_dw_pc~0); 1676#L56-5 assume !(2 == ~p_dw_pc~0); 1675#L66-3 is_do_write_p_triggered_~__retres1~0 := 0; 1670#L77-1 is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 1668#L78-1 activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 1666#L377-3 assume 0 != activate_threads_~tmp~1;~p_dw_st~0 := 0; 1419#L377-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 1420#L85-3 assume !(1 == ~c_dr_pc~0); 1433#L85-5 assume !(2 == ~c_dr_pc~0); 1326#L95-3 is_do_read_c_triggered_~__retres1~1 := 0; 1327#L106-1 is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 1334#L107-1 activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 1443#L385-3 assume 0 != activate_threads_~tmp___0~1;~c_dr_st~0 := 0; 1444#L385-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1449#L319-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 1450#L319-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 1452#L324-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 1425#L281-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2 := 1; 1325#L293-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 1366#L294-1 start_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 1453#L500 assume !(0 == start_simulation_~tmp~4); 1466#L500-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~3, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~3;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 1690#L281-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2 := 1; 1660#L293-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 1659#L294-2 stop_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 1658#L455 assume 0 != stop_simulation_~tmp~3;stop_simulation_~__retres2~0 := 0; 1656#L462 stop_simulation_#res := stop_simulation_~__retres2~0; 1654#L463 start_simulation_#t~ret10 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 1653#L513 assume !(0 != start_simulation_~tmp___0~3); 1462#L481-3 [2018-11-18 11:44:36,035 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:44:36,035 INFO L82 PathProgramCache]: Analyzing trace with hash 156116973, now seen corresponding path program 1 times [2018-11-18 11:44:36,035 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:44:36,035 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:44:36,036 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:36,036 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:44:36,036 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:36,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:44:36,058 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:44:36,059 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:44:36,059 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 11:44:36,059 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 11:44:36,059 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:44:36,059 INFO L82 PathProgramCache]: Analyzing trace with hash -1312034622, now seen corresponding path program 1 times [2018-11-18 11:44:36,059 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:44:36,059 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:44:36,060 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:36,060 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:44:36,060 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:36,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:44:36,095 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:44:36,096 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:44:36,096 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 11:44:36,097 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 11:44:36,097 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 11:44:36,097 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 11:44:36,097 INFO L87 Difference]: Start difference. First operand 396 states and 562 transitions. cyclomatic complexity: 170 Second operand 3 states. [2018-11-18 11:44:36,135 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:44:36,135 INFO L93 Difference]: Finished difference Result 786 states and 1101 transitions. [2018-11-18 11:44:36,135 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 11:44:36,136 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 786 states and 1101 transitions. [2018-11-18 11:44:36,139 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 708 [2018-11-18 11:44:36,142 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 786 states to 786 states and 1101 transitions. [2018-11-18 11:44:36,142 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 786 [2018-11-18 11:44:36,143 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 786 [2018-11-18 11:44:36,143 INFO L73 IsDeterministic]: Start isDeterministic. Operand 786 states and 1101 transitions. [2018-11-18 11:44:36,144 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:44:36,144 INFO L705 BuchiCegarLoop]: Abstraction has 786 states and 1101 transitions. [2018-11-18 11:44:36,144 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 786 states and 1101 transitions. [2018-11-18 11:44:36,156 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 786 to 786. [2018-11-18 11:44:36,156 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 786 states. [2018-11-18 11:44:36,157 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 786 states to 786 states and 1101 transitions. [2018-11-18 11:44:36,158 INFO L728 BuchiCegarLoop]: Abstraction has 786 states and 1101 transitions. [2018-11-18 11:44:36,158 INFO L608 BuchiCegarLoop]: Abstraction has 786 states and 1101 transitions. [2018-11-18 11:44:36,158 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ [2018-11-18 11:44:36,158 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 786 states and 1101 transitions. [2018-11-18 11:44:36,160 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 708 [2018-11-18 11:44:36,161 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:44:36,161 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:44:36,161 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:44:36,161 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:44:36,162 INFO L794 eck$LassoCheckResult]: Stem: 2648#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 2527#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 2528#L541 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~4, start_simulation_~tmp___0~3;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~4;havoc start_simulation_~tmp___0~3;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 2529#L248 assume !(1 == ~q_req_up~0); 2603#L248-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2519#L263 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 2520#L263-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 2577#L268-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2578#L301 assume !(0 == ~q_read_ev~0); 2594#L301-2 assume !(0 == ~q_write_ev~0); 2610#L306-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 2611#L56 assume !(1 == ~p_dw_pc~0); 2581#L56-2 assume !(2 == ~p_dw_pc~0); 2582#L66-1 is_do_write_p_triggered_~__retres1~0 := 0; 2657#L77 is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 2658#L78 activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 2633#L377 assume !(0 != activate_threads_~tmp~1); 2634#L377-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 2675#L85 assume !(1 == ~c_dr_pc~0); 2676#L85-2 assume !(2 == ~c_dr_pc~0); 2524#L95-1 is_do_read_c_triggered_~__retres1~1 := 0; 2525#L106 is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 2677#L107 activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 2678#L385 assume !(0 != activate_threads_~tmp___0~1); 2694#L385-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2671#L319 assume !(1 == ~q_read_ev~0); 2650#L319-2 assume !(1 == ~q_write_ev~0); 2651#L324-1 assume { :end_inline_reset_delta_events } true; 2680#L481-3 [2018-11-18 11:44:36,162 INFO L796 eck$LassoCheckResult]: Loop: 2680#L481-3 assume true; 3136#L481-1 assume !false; 3133#L482 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5, eval_#t~nondet6, eval_#t~nondet7, eval_~tmp~2, eval_~tmp___0~2, eval_~tmp___1~0;havoc eval_~tmp~2;havoc eval_~tmp___0~2;havoc eval_~tmp___1~0; 3099#L425 assume true; 3129#L400-1 assume !false; 3127#L401 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 3124#L281 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2 := 1; 3118#L293 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 3115#L294 eval_#t~ret5 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0 := eval_#t~ret5;havoc eval_#t~ret5; 3111#L405 assume !(0 != eval_~tmp___1~0); 3112#L441 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 3238#L248-3 assume !(1 == ~q_req_up~0); 2602#L248-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 2574#L301-3 assume !(0 == ~q_read_ev~0); 2539#L301-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 2540#L306-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 2575#L56-3 assume !(1 == ~p_dw_pc~0); 2541#L56-5 assume !(2 == ~p_dw_pc~0); 2542#L66-3 is_do_write_p_triggered_~__retres1~0 := 0; 2645#L77-1 is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 2592#L78-1 activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 2593#L377-3 assume 0 != activate_threads_~tmp~1;~p_dw_st~0 := 0; 2618#L377-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 2619#L85-3 assume !(1 == ~c_dr_pc~0); 2636#L85-5 assume !(2 == ~c_dr_pc~0); 2517#L95-3 is_do_read_c_triggered_~__retres1~1 := 0; 2518#L106-1 is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 2526#L107-1 activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 2646#L385-3 assume 0 != activate_threads_~tmp___0~1;~c_dr_st~0 := 0; 2647#L385-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2654#L319-3 assume !(1 == ~q_read_ev~0); 2655#L319-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 3201#L324-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 3196#L281-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2 := 1; 3190#L293-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 3185#L294-1 start_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 3179#L500 assume !(0 == start_simulation_~tmp~4); 3174#L500-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~3, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~3;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 3170#L281-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2 := 1; 3165#L293-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 3161#L294-2 stop_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 3157#L455 assume 0 != stop_simulation_~tmp~3;stop_simulation_~__retres2~0 := 0; 3152#L462 stop_simulation_#res := stop_simulation_~__retres2~0; 3148#L463 start_simulation_#t~ret10 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 3144#L513 assume !(0 != start_simulation_~tmp___0~3); 2680#L481-3 [2018-11-18 11:44:36,162 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:44:36,162 INFO L82 PathProgramCache]: Analyzing trace with hash 156118895, now seen corresponding path program 1 times [2018-11-18 11:44:36,162 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:44:36,162 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:44:36,163 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:36,163 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:44:36,163 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:36,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:44:36,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:44:36,193 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:44:36,193 INFO L82 PathProgramCache]: Analyzing trace with hash 1977828610, now seen corresponding path program 1 times [2018-11-18 11:44:36,193 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:44:36,193 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:44:36,194 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:36,194 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:44:36,194 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:36,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:44:36,232 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:44:36,232 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:44:36,232 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 11:44:36,232 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 11:44:36,232 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 11:44:36,232 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 11:44:36,233 INFO L87 Difference]: Start difference. First operand 786 states and 1101 transitions. cyclomatic complexity: 319 Second operand 5 states. [2018-11-18 11:44:36,295 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:44:36,295 INFO L93 Difference]: Finished difference Result 1306 states and 1787 transitions. [2018-11-18 11:44:36,295 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-18 11:44:36,296 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1306 states and 1787 transitions. [2018-11-18 11:44:36,300 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1208 [2018-11-18 11:44:36,304 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1306 states to 1306 states and 1787 transitions. [2018-11-18 11:44:36,304 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1306 [2018-11-18 11:44:36,305 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1306 [2018-11-18 11:44:36,305 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1306 states and 1787 transitions. [2018-11-18 11:44:36,306 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:44:36,306 INFO L705 BuchiCegarLoop]: Abstraction has 1306 states and 1787 transitions. [2018-11-18 11:44:36,307 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1306 states and 1787 transitions. [2018-11-18 11:44:36,316 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1306 to 810. [2018-11-18 11:44:36,316 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 810 states. [2018-11-18 11:44:36,318 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 810 states to 810 states and 1125 transitions. [2018-11-18 11:44:36,318 INFO L728 BuchiCegarLoop]: Abstraction has 810 states and 1125 transitions. [2018-11-18 11:44:36,318 INFO L608 BuchiCegarLoop]: Abstraction has 810 states and 1125 transitions. [2018-11-18 11:44:36,319 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ [2018-11-18 11:44:36,319 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 810 states and 1125 transitions. [2018-11-18 11:44:36,321 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 732 [2018-11-18 11:44:36,321 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:44:36,322 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:44:36,322 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:44:36,322 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:44:36,323 INFO L794 eck$LassoCheckResult]: Stem: 4769#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 4637#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 4638#L541 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~4, start_simulation_~tmp___0~3;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~4;havoc start_simulation_~tmp___0~3;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 4639#L248 assume !(1 == ~q_req_up~0); 4716#L248-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4627#L263 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 4628#L263-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 4689#L268-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4690#L301 assume !(0 == ~q_read_ev~0); 4704#L301-2 assume !(0 == ~q_write_ev~0); 4722#L306-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 4723#L56 assume !(1 == ~p_dw_pc~0); 4693#L56-2 assume !(2 == ~p_dw_pc~0); 4694#L66-1 is_do_write_p_triggered_~__retres1~0 := 0; 4779#L77 is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 4780#L78 activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 4747#L377 assume !(0 != activate_threads_~tmp~1); 4748#L377-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 4795#L85 assume !(1 == ~c_dr_pc~0); 4796#L85-2 assume !(2 == ~c_dr_pc~0); 4633#L95-1 is_do_read_c_triggered_~__retres1~1 := 0; 4634#L106 is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 4797#L107 activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 4798#L385 assume !(0 != activate_threads_~tmp___0~1); 4811#L385-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4790#L319 assume !(1 == ~q_read_ev~0); 4791#L319-2 assume !(1 == ~q_write_ev~0); 4800#L324-1 assume { :end_inline_reset_delta_events } true; 4678#L481-3 [2018-11-18 11:44:36,323 INFO L796 eck$LassoCheckResult]: Loop: 4678#L481-3 assume true; 4794#L481-1 assume !false; 4726#L482 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5, eval_#t~nondet6, eval_#t~nondet7, eval_~tmp~2, eval_~tmp___0~2, eval_~tmp___1~0;havoc eval_~tmp~2;havoc eval_~tmp___0~2;havoc eval_~tmp___1~0; 4652#L425 assume true; 4653#L400-1 assume !false; 4940#L401 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 4936#L281 assume !(0 == ~p_dw_st~0); 4931#L285 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2 := 0; 4924#L293 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 4920#L294 eval_#t~ret5 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0 := eval_#t~ret5;havoc eval_#t~ret5; 4918#L405 assume !(0 != eval_~tmp___1~0); 4917#L441 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 4915#L248-3 assume !(1 == ~q_req_up~0); 4916#L248-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 4958#L301-3 assume !(0 == ~q_read_ev~0); 4956#L301-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 4725#L306-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 4687#L56-3 assume !(1 == ~p_dw_pc~0); 4650#L56-5 assume !(2 == ~p_dw_pc~0); 4651#L66-3 is_do_write_p_triggered_~__retres1~0 := 0; 4971#L77-1 is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 4970#L78-1 activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 4969#L377-3 assume 0 != activate_threads_~tmp~1;~p_dw_st~0 := 0; 4968#L377-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 4967#L85-3 assume !(1 == ~c_dr_pc~0); 4966#L85-5 assume !(2 == ~c_dr_pc~0); 4943#L95-3 is_do_read_c_triggered_~__retres1~1 := 0; 4944#L106-1 is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 4848#L107-1 activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 4849#L385-3 assume 0 != activate_threads_~tmp___0~1;~c_dr_st~0 := 0; 4840#L385-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4841#L319-3 assume !(1 == ~q_read_ev~0); 4832#L319-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 4833#L324-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 4741#L281-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2 := 1; 4626#L293-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 4672#L294-1 start_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 4785#L500 assume !(0 == start_simulation_~tmp~4); 4804#L500-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~3, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~3;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 4805#L281-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2 := 1; 4668#L293-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 4669#L294-2 stop_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 4698#L455 assume 0 != stop_simulation_~tmp~3;stop_simulation_~__retres2~0 := 0; 4699#L462 stop_simulation_#res := stop_simulation_~__retres2~0; 4724#L463 start_simulation_#t~ret10 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 4677#L513 assume !(0 != start_simulation_~tmp___0~3); 4678#L481-3 [2018-11-18 11:44:36,323 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:44:36,323 INFO L82 PathProgramCache]: Analyzing trace with hash 156118895, now seen corresponding path program 2 times [2018-11-18 11:44:36,323 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:44:36,323 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:44:36,324 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:36,324 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:44:36,324 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:36,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:44:36,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:44:36,337 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:44:36,337 INFO L82 PathProgramCache]: Analyzing trace with hash 1159042172, now seen corresponding path program 1 times [2018-11-18 11:44:36,337 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:44:36,337 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:44:36,338 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:36,338 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 11:44:36,338 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:36,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:44:36,410 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:44:36,410 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:44:36,410 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 11:44:36,410 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 11:44:36,411 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 11:44:36,411 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 11:44:36,411 INFO L87 Difference]: Start difference. First operand 810 states and 1125 transitions. cyclomatic complexity: 319 Second operand 5 states. [2018-11-18 11:44:36,467 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:44:36,467 INFO L93 Difference]: Finished difference Result 1498 states and 2071 transitions. [2018-11-18 11:44:36,468 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 11:44:36,468 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1498 states and 2071 transitions. [2018-11-18 11:44:36,473 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1412 [2018-11-18 11:44:36,478 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1498 states to 1498 states and 2071 transitions. [2018-11-18 11:44:36,478 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1498 [2018-11-18 11:44:36,479 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1498 [2018-11-18 11:44:36,479 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1498 states and 2071 transitions. [2018-11-18 11:44:36,481 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:44:36,481 INFO L705 BuchiCegarLoop]: Abstraction has 1498 states and 2071 transitions. [2018-11-18 11:44:36,482 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1498 states and 2071 transitions. [2018-11-18 11:44:36,492 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1498 to 834. [2018-11-18 11:44:36,492 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 834 states. [2018-11-18 11:44:36,494 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 834 states to 834 states and 1139 transitions. [2018-11-18 11:44:36,494 INFO L728 BuchiCegarLoop]: Abstraction has 834 states and 1139 transitions. [2018-11-18 11:44:36,494 INFO L608 BuchiCegarLoop]: Abstraction has 834 states and 1139 transitions. [2018-11-18 11:44:36,494 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ [2018-11-18 11:44:36,494 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 834 states and 1139 transitions. [2018-11-18 11:44:36,497 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 756 [2018-11-18 11:44:36,497 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:44:36,497 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:44:36,498 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:44:36,498 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:44:36,498 INFO L794 eck$LassoCheckResult]: Stem: 7088#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 6957#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 6958#L541 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~4, start_simulation_~tmp___0~3;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~4;havoc start_simulation_~tmp___0~3;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 6959#L248 assume !(1 == ~q_req_up~0); 7033#L248-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6948#L263 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 6949#L263-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 7008#L268-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7009#L301 assume !(0 == ~q_read_ev~0); 7022#L301-2 assume !(0 == ~q_write_ev~0); 7043#L306-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 7044#L56 assume !(1 == ~p_dw_pc~0); 7012#L56-2 assume !(2 == ~p_dw_pc~0); 7013#L66-1 is_do_write_p_triggered_~__retres1~0 := 0; 7097#L77 is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 7098#L78 activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 7070#L377 assume !(0 != activate_threads_~tmp~1); 7071#L377-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 7113#L85 assume !(1 == ~c_dr_pc~0); 7114#L85-2 assume !(2 == ~c_dr_pc~0); 6954#L95-1 is_do_read_c_triggered_~__retres1~1 := 0; 6955#L106 is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 7115#L107 activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 7116#L385 assume !(0 != activate_threads_~tmp___0~1); 7133#L385-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7109#L319 assume !(1 == ~q_read_ev~0); 7090#L319-2 assume !(1 == ~q_write_ev~0); 7091#L324-1 assume { :end_inline_reset_delta_events } true; 7422#L481-3 [2018-11-18 11:44:36,498 INFO L796 eck$LassoCheckResult]: Loop: 7422#L481-3 assume true; 7421#L481-1 assume !false; 7420#L482 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5, eval_#t~nondet6, eval_#t~nondet7, eval_~tmp~2, eval_~tmp___0~2, eval_~tmp___1~0;havoc eval_~tmp~2;havoc eval_~tmp___0~2;havoc eval_~tmp___1~0; 7311#L425 assume true; 7419#L400-1 assume !false; 7418#L401 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 7415#L281 assume !(0 == ~p_dw_st~0); 7416#L285 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2 := 0; 7417#L293 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 7404#L294 eval_#t~ret5 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0 := eval_#t~ret5;havoc eval_#t~ret5; 7405#L405 assume !(0 != eval_~tmp___1~0); 7498#L441 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 7495#L248-3 assume !(1 == ~q_req_up~0); 7496#L248-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 7003#L301-3 assume !(0 == ~q_read_ev~0); 7004#L301-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 7046#L306-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 7047#L56-3 assume !(1 == ~p_dw_pc~0); 6971#L56-5 assume !(2 == ~p_dw_pc~0); 6972#L66-3 is_do_write_p_triggered_~__retres1~0 := 0; 7480#L77-1 is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 7477#L78-1 activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 7475#L377-3 assume !(0 != activate_threads_~tmp~1); 7473#L377-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 7470#L85-3 assume !(1 == ~c_dr_pc~0); 7467#L85-5 assume !(2 == ~c_dr_pc~0); 7464#L95-3 is_do_read_c_triggered_~__retres1~1 := 0; 7461#L106-1 is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 7458#L107-1 activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 7455#L385-3 assume 0 != activate_threads_~tmp___0~1;~c_dr_st~0 := 0; 7452#L385-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7449#L319-3 assume !(1 == ~q_read_ev~0); 7445#L319-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 7443#L324-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 7441#L281-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2 := 1; 7438#L293-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 7436#L294-1 start_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 7433#L500 assume !(0 == start_simulation_~tmp~4); 7431#L500-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~3, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~3;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 7430#L281-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2 := 1; 7428#L293-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 7427#L294-2 stop_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 7426#L455 assume 0 != stop_simulation_~tmp~3;stop_simulation_~__retres2~0 := 0; 7425#L462 stop_simulation_#res := stop_simulation_~__retres2~0; 7424#L463 start_simulation_#t~ret10 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 7423#L513 assume !(0 != start_simulation_~tmp___0~3); 7422#L481-3 [2018-11-18 11:44:36,499 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:44:36,499 INFO L82 PathProgramCache]: Analyzing trace with hash 156118895, now seen corresponding path program 3 times [2018-11-18 11:44:36,499 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:44:36,499 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:44:36,500 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:36,500 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:44:36,500 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:36,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:44:36,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:44:36,511 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:44:36,512 INFO L82 PathProgramCache]: Analyzing trace with hash 1025028666, now seen corresponding path program 1 times [2018-11-18 11:44:36,512 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:44:36,512 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:44:36,512 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:36,513 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 11:44:36,513 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:36,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:44:36,533 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:44:36,534 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:44:36,534 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 11:44:36,534 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 11:44:36,534 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 11:44:36,534 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 11:44:36,534 INFO L87 Difference]: Start difference. First operand 834 states and 1139 transitions. cyclomatic complexity: 309 Second operand 3 states. [2018-11-18 11:44:36,565 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:44:36,566 INFO L93 Difference]: Finished difference Result 1220 states and 1621 transitions. [2018-11-18 11:44:36,566 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 11:44:36,566 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1220 states and 1621 transitions. [2018-11-18 11:44:36,571 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1084 [2018-11-18 11:44:36,574 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1220 states to 1220 states and 1621 transitions. [2018-11-18 11:44:36,575 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1220 [2018-11-18 11:44:36,576 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1220 [2018-11-18 11:44:36,576 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1220 states and 1621 transitions. [2018-11-18 11:44:36,578 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:44:36,578 INFO L705 BuchiCegarLoop]: Abstraction has 1220 states and 1621 transitions. [2018-11-18 11:44:36,579 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1220 states and 1621 transitions. [2018-11-18 11:44:36,589 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1220 to 1220. [2018-11-18 11:44:36,590 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1220 states. [2018-11-18 11:44:36,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1220 states to 1220 states and 1621 transitions. [2018-11-18 11:44:36,592 INFO L728 BuchiCegarLoop]: Abstraction has 1220 states and 1621 transitions. [2018-11-18 11:44:36,592 INFO L608 BuchiCegarLoop]: Abstraction has 1220 states and 1621 transitions. [2018-11-18 11:44:36,592 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ [2018-11-18 11:44:36,592 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1220 states and 1621 transitions. [2018-11-18 11:44:36,597 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1084 [2018-11-18 11:44:36,597 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:44:36,597 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:44:36,598 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:44:36,598 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:44:36,598 INFO L794 eck$LassoCheckResult]: Stem: 9143#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 9017#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 9018#L541 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~4, start_simulation_~tmp___0~3;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~4;havoc start_simulation_~tmp___0~3;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 9019#L248 assume !(1 == ~q_req_up~0); 9093#L248-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9008#L263 assume !(1 == ~p_dw_i~0);~p_dw_st~0 := 2; 9009#L263-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 9196#L268-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9197#L301 assume !(0 == ~q_read_ev~0); 9068#L301-2 assume !(0 == ~q_write_ev~0); 9069#L306-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 9251#L56 assume !(1 == ~p_dw_pc~0); 9252#L56-2 assume !(2 == ~p_dw_pc~0); 9247#L66-1 is_do_write_p_triggered_~__retres1~0 := 0; 9248#L77 is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 9243#L78 activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 9244#L377 assume !(0 != activate_threads_~tmp~1); 9239#L377-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 9240#L85 assume !(1 == ~c_dr_pc~0); 9235#L85-2 assume !(2 == ~c_dr_pc~0); 9236#L95-1 is_do_read_c_triggered_~__retres1~1 := 0; 9231#L106 is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 9232#L107 activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 9227#L385 assume !(0 != activate_threads_~tmp___0~1); 9228#L385-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9165#L319 assume !(1 == ~q_read_ev~0); 9166#L319-2 assume !(1 == ~q_write_ev~0); 9175#L324-1 assume { :end_inline_reset_delta_events } true; 9056#L481-3 [2018-11-18 11:44:36,598 INFO L796 eck$LassoCheckResult]: Loop: 9056#L481-3 assume true; 9169#L481-1 assume !false; 9106#L482 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5, eval_#t~nondet6, eval_#t~nondet7, eval_~tmp~2, eval_~tmp___0~2, eval_~tmp___1~0;havoc eval_~tmp~2;havoc eval_~tmp___0~2;havoc eval_~tmp___1~0; 9033#L425 assume true; 9034#L400-1 assume !false; 9088#L401 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 9120#L281 assume !(0 == ~p_dw_st~0); 9121#L285 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2 := 0; 10160#L293 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 10158#L294 eval_#t~ret5 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0 := eval_#t~ret5;havoc eval_#t~ret5; 10156#L405 assume !(0 != eval_~tmp___1~0); 10154#L441 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 10152#L248-3 assume !(1 == ~q_req_up~0); 9094#L248-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 9063#L301-3 assume !(0 == ~q_read_ev~0); 9029#L301-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 9030#L306-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 9064#L56-3 assume !(1 == ~p_dw_pc~0); 9031#L56-5 assume !(2 == ~p_dw_pc~0); 9032#L66-3 is_do_write_p_triggered_~__retres1~0 := 0; 9140#L77-1 is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 9080#L78-1 activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 9081#L377-3 assume !(0 != activate_threads_~tmp~1); 9111#L377-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 9112#L85-3 assume !(1 == ~c_dr_pc~0); 9129#L85-5 assume !(2 == ~c_dr_pc~0); 9006#L95-3 is_do_read_c_triggered_~__retres1~1 := 0; 9007#L106-1 is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 9016#L107-1 activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 9141#L385-3 assume 0 != activate_threads_~tmp___0~1;~c_dr_st~0 := 0; 9142#L385-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9148#L319-3 assume !(1 == ~q_read_ev~0); 9149#L319-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 10199#L324-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 10198#L281-1 assume !(0 == ~p_dw_st~0); 10197#L285-1 assume 0 == ~c_dr_st~0;exists_runnable_thread_~__retres1~2 := 1; 10196#L293-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 10195#L294-1 start_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 10194#L500 assume !(0 == start_simulation_~tmp~4); 10192#L500-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~3, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~3;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 10191#L281-2 assume !(0 == ~p_dw_st~0); 10190#L285-2 assume 0 == ~c_dr_st~0;exists_runnable_thread_~__retres1~2 := 1; 10189#L293-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 10188#L294-2 stop_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 10187#L455 assume 0 != stop_simulation_~tmp~3;stop_simulation_~__retres2~0 := 0; 9156#L462 stop_simulation_#res := stop_simulation_~__retres2~0; 9157#L463 start_simulation_#t~ret10 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 9055#L513 assume !(0 != start_simulation_~tmp___0~3); 9056#L481-3 [2018-11-18 11:44:36,599 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:44:36,599 INFO L82 PathProgramCache]: Analyzing trace with hash -1649319439, now seen corresponding path program 1 times [2018-11-18 11:44:36,599 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:44:36,599 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:44:36,599 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:36,600 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:44:36,600 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:36,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:44:36,618 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:44:36,618 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:44:36,618 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 11:44:36,619 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 11:44:36,619 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:44:36,619 INFO L82 PathProgramCache]: Analyzing trace with hash -1151142120, now seen corresponding path program 1 times [2018-11-18 11:44:36,619 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:44:36,619 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:44:36,620 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:36,620 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:44:36,620 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:36,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:44:36,662 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:44:36,663 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:44:36,663 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 11:44:36,663 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 11:44:36,663 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 11:44:36,663 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 11:44:36,663 INFO L87 Difference]: Start difference. First operand 1220 states and 1621 transitions. cyclomatic complexity: 409 Second operand 3 states. [2018-11-18 11:44:36,672 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:44:36,673 INFO L93 Difference]: Finished difference Result 1176 states and 1567 transitions. [2018-11-18 11:44:36,673 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 11:44:36,673 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1176 states and 1567 transitions. [2018-11-18 11:44:36,677 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1084 [2018-11-18 11:44:36,679 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1176 states to 1176 states and 1567 transitions. [2018-11-18 11:44:36,679 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1176 [2018-11-18 11:44:36,680 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1176 [2018-11-18 11:44:36,680 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1176 states and 1567 transitions. [2018-11-18 11:44:36,681 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:44:36,681 INFO L705 BuchiCegarLoop]: Abstraction has 1176 states and 1567 transitions. [2018-11-18 11:44:36,682 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1176 states and 1567 transitions. [2018-11-18 11:44:36,689 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1176 to 1176. [2018-11-18 11:44:36,689 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1176 states. [2018-11-18 11:44:36,691 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1176 states to 1176 states and 1567 transitions. [2018-11-18 11:44:36,691 INFO L728 BuchiCegarLoop]: Abstraction has 1176 states and 1567 transitions. [2018-11-18 11:44:36,691 INFO L608 BuchiCegarLoop]: Abstraction has 1176 states and 1567 transitions. [2018-11-18 11:44:36,691 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ [2018-11-18 11:44:36,691 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1176 states and 1567 transitions. [2018-11-18 11:44:36,694 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1084 [2018-11-18 11:44:36,694 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:44:36,694 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:44:36,695 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:44:36,695 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:44:36,695 INFO L794 eck$LassoCheckResult]: Stem: 11553#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 11422#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 11423#L541 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~4, start_simulation_~tmp___0~3;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~4;havoc start_simulation_~tmp___0~3;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 11424#L248 assume !(1 == ~q_req_up~0); 11500#L248-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11413#L263 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 11414#L263-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 11478#L268-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11479#L301 assume !(0 == ~q_read_ev~0); 11488#L301-2 assume !(0 == ~q_write_ev~0); 11507#L306-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 11508#L56 assume !(1 == ~p_dw_pc~0); 11480#L56-2 assume !(2 == ~p_dw_pc~0); 11481#L66-1 is_do_write_p_triggered_~__retres1~0 := 0; 11562#L77 is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 11563#L78 activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 11534#L377 assume !(0 != activate_threads_~tmp~1); 11535#L377-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 11575#L85 assume !(1 == ~c_dr_pc~0); 11576#L85-2 assume !(2 == ~c_dr_pc~0); 11419#L95-1 is_do_read_c_triggered_~__retres1~1 := 0; 11420#L106 is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 11578#L107 activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 11579#L385 assume !(0 != activate_threads_~tmp___0~1); 11594#L385-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11573#L319 assume !(1 == ~q_read_ev~0); 11574#L319-2 assume !(1 == ~q_write_ev~0); 11583#L324-1 assume { :end_inline_reset_delta_events } true; 11584#L481-3 assume true; 11703#L481-1 assume !false; 11697#L482 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5, eval_#t~nondet6, eval_#t~nondet7, eval_~tmp~2, eval_~tmp___0~2, eval_~tmp___1~0;havoc eval_~tmp~2;havoc eval_~tmp___0~2;havoc eval_~tmp___1~0; 11696#L425 [2018-11-18 11:44:36,695 INFO L796 eck$LassoCheckResult]: Loop: 11696#L425 assume true; 11674#L400-1 assume !false; 11654#L401 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 11655#L281 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2 := 1; 11664#L293 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 11665#L294 eval_#t~ret5 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0 := eval_#t~ret5;havoc eval_#t~ret5; 11650#L405 assume 0 != eval_~tmp___1~0; 11651#L405-1 assume 0 == ~p_dw_st~0;eval_~tmp~2 := eval_#t~nondet6;havoc eval_#t~nondet6; 11749#L414 assume !(0 != eval_~tmp~2); 11702#L410 assume !(0 == ~c_dr_st~0); 11696#L425 [2018-11-18 11:44:36,695 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:44:36,695 INFO L82 PathProgramCache]: Analyzing trace with hash -511439423, now seen corresponding path program 1 times [2018-11-18 11:44:36,696 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:44:36,696 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:44:36,696 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:36,696 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:44:36,696 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:36,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:44:36,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:44:36,707 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:44:36,707 INFO L82 PathProgramCache]: Analyzing trace with hash 1001016536, now seen corresponding path program 1 times [2018-11-18 11:44:36,707 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:44:36,707 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:44:36,708 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:36,708 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:44:36,708 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:36,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:44:36,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:44:36,712 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:44:36,713 INFO L82 PathProgramCache]: Analyzing trace with hash 1355295384, now seen corresponding path program 1 times [2018-11-18 11:44:36,713 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:44:36,713 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:44:36,713 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:36,713 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:44:36,714 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:36,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:44:36,729 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:44:36,729 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:44:36,729 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 11:44:36,767 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 11:44:36,767 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 11:44:36,768 INFO L87 Difference]: Start difference. First operand 1176 states and 1567 transitions. cyclomatic complexity: 399 Second operand 3 states. [2018-11-18 11:44:36,915 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:44:36,916 INFO L93 Difference]: Finished difference Result 1116 states and 1478 transitions. [2018-11-18 11:44:36,916 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 11:44:36,916 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1116 states and 1478 transitions. [2018-11-18 11:44:36,920 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 1014 [2018-11-18 11:44:36,922 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1116 states to 1116 states and 1478 transitions. [2018-11-18 11:44:36,922 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1116 [2018-11-18 11:44:36,923 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1116 [2018-11-18 11:44:36,923 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1116 states and 1478 transitions. [2018-11-18 11:44:36,924 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:44:36,924 INFO L705 BuchiCegarLoop]: Abstraction has 1116 states and 1478 transitions. [2018-11-18 11:44:36,925 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1116 states and 1478 transitions. [2018-11-18 11:44:36,932 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1116 to 1116. [2018-11-18 11:44:36,933 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1116 states. [2018-11-18 11:44:36,934 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1116 states to 1116 states and 1478 transitions. [2018-11-18 11:44:36,934 INFO L728 BuchiCegarLoop]: Abstraction has 1116 states and 1478 transitions. [2018-11-18 11:44:36,935 INFO L608 BuchiCegarLoop]: Abstraction has 1116 states and 1478 transitions. [2018-11-18 11:44:36,935 INFO L442 BuchiCegarLoop]: ======== Iteration 10============ [2018-11-18 11:44:36,935 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1116 states and 1478 transitions. [2018-11-18 11:44:36,937 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 1014 [2018-11-18 11:44:36,937 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:44:36,938 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:44:36,938 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:44:36,938 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:44:36,938 INFO L794 eck$LassoCheckResult]: Stem: 13846#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 13721#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 13722#L541 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~4, start_simulation_~tmp___0~3;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~4;havoc start_simulation_~tmp___0~3;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 13723#L248 assume !(1 == ~q_req_up~0); 13798#L248-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13713#L263 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 13714#L263-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 13773#L268-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13774#L301 assume !(0 == ~q_read_ev~0); 13786#L301-2 assume !(0 == ~q_write_ev~0); 13805#L306-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~1;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res;havoc is_do_write_p_triggered_~__retres1~0;havoc is_do_write_p_triggered_~__retres1~0; 13806#L56 assume !(1 == ~p_dw_pc~0); 13777#L56-2 assume !(2 == ~p_dw_pc~0); 13778#L66-1 is_do_write_p_triggered_~__retres1~0 := 0; 14262#L77 is_do_write_p_triggered_#res := is_do_write_p_triggered_~__retres1~0; 14261#L78 activate_threads_#t~ret3 := is_do_write_p_triggered_#res;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 14260#L377 assume !(0 != activate_threads_~tmp~1); 14259#L377-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res;havoc is_do_read_c_triggered_~__retres1~1;havoc is_do_read_c_triggered_~__retres1~1; 13869#L85 assume !(1 == ~c_dr_pc~0); 13870#L85-2 assume !(2 == ~c_dr_pc~0); 13718#L95-1 is_do_read_c_triggered_~__retres1~1 := 0; 13719#L106 is_do_read_c_triggered_#res := is_do_read_c_triggered_~__retres1~1; 13739#L107 activate_threads_#t~ret4 := is_do_read_c_triggered_#res;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 13864#L385 assume !(0 != activate_threads_~tmp___0~1); 13865#L385-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13868#L319 assume !(1 == ~q_read_ev~0); 13848#L319-2 assume !(1 == ~q_write_ev~0); 13849#L324-1 assume { :end_inline_reset_delta_events } true; 14107#L481-3 assume true; 14104#L481-1 assume !false; 14097#L482 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5, eval_#t~nondet6, eval_#t~nondet7, eval_~tmp~2, eval_~tmp___0~2, eval_~tmp___1~0;havoc eval_~tmp~2;havoc eval_~tmp___0~2;havoc eval_~tmp___1~0; 14093#L425 [2018-11-18 11:44:36,938 INFO L796 eck$LassoCheckResult]: Loop: 14093#L425 assume true; 14090#L400-1 assume !false; 14086#L401 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 14081#L281 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2 := 1; 14077#L293 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 14074#L294 eval_#t~ret5 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0 := eval_#t~ret5;havoc eval_#t~ret5; 14070#L405 assume 0 != eval_~tmp___1~0; 14064#L405-1 assume 0 == ~p_dw_st~0;eval_~tmp~2 := eval_#t~nondet6;havoc eval_#t~nondet6; 14060#L414 assume !(0 != eval_~tmp~2); 14061#L410 assume 0 == ~c_dr_st~0;eval_~tmp___0~2 := eval_#t~nondet7;havoc eval_#t~nondet7; 14098#L429 assume !(0 != eval_~tmp___0~2); 14093#L425 [2018-11-18 11:44:36,939 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:44:36,939 INFO L82 PathProgramCache]: Analyzing trace with hash -511439423, now seen corresponding path program 2 times [2018-11-18 11:44:36,939 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:44:36,939 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:44:36,939 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:36,940 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:44:36,940 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:36,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:44:36,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:44:36,964 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:44:36,964 INFO L82 PathProgramCache]: Analyzing trace with hash 966739889, now seen corresponding path program 1 times [2018-11-18 11:44:36,965 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:44:36,965 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:44:36,965 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:36,965 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 11:44:36,965 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:36,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:44:36,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:44:36,970 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:44:36,970 INFO L82 PathProgramCache]: Analyzing trace with hash -935517711, now seen corresponding path program 1 times [2018-11-18 11:44:36,970 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:44:36,970 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:44:36,971 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:36,971 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:44:36,971 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:44:36,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:44:36,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:44:37,199 WARN L180 SmtUtils]: Spent 171.00 ms on a formula simplification. DAG size of input: 106 DAG size of output: 86 [2018-11-18 11:44:37,262 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 18.11 11:44:37 BoogieIcfgContainer [2018-11-18 11:44:37,262 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2018-11-18 11:44:37,262 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-18 11:44:37,262 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-18 11:44:37,262 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-18 11:44:37,263 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 11:44:35" (3/4) ... [2018-11-18 11:44:37,265 INFO L141 WitnessPrinter]: Generating witness for non-termination counterexample [2018-11-18 11:44:37,304 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_95d36298-be4d-4da0-9c15-8f225f569199/bin-2019/uautomizer/witness.graphml [2018-11-18 11:44:37,304 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-18 11:44:37,305 INFO L168 Benchmark]: Toolchain (without parser) took 2571.97 ms. Allocated memory was 1.0 GB in the beginning and 1.3 GB in the end (delta: 222.3 MB). Free memory was 958.0 MB in the beginning and 1.1 GB in the end (delta: -160.9 MB). Peak memory consumption was 61.4 MB. Max. memory is 11.5 GB. [2018-11-18 11:44:37,305 INFO L168 Benchmark]: CDTParser took 0.13 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 11:44:37,305 INFO L168 Benchmark]: CACSL2BoogieTranslator took 221.26 ms. Allocated memory is still 1.0 GB. Free memory was 958.0 MB in the beginning and 941.9 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. [2018-11-18 11:44:37,305 INFO L168 Benchmark]: Boogie Procedure Inliner took 65.28 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 157.3 MB). Free memory was 941.9 MB in the beginning and 1.2 GB in the end (delta: -210.9 MB). Peak memory consumption was 17.1 MB. Max. memory is 11.5 GB. [2018-11-18 11:44:37,306 INFO L168 Benchmark]: Boogie Preprocessor took 22.62 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 6.3 MB). Peak memory consumption was 6.3 MB. Max. memory is 11.5 GB. [2018-11-18 11:44:37,306 INFO L168 Benchmark]: RCFGBuilder took 402.55 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 39.0 MB). Peak memory consumption was 39.0 MB. Max. memory is 11.5 GB. [2018-11-18 11:44:37,306 INFO L168 Benchmark]: BuchiAutomizer took 1815.22 ms. Allocated memory was 1.2 GB in the beginning and 1.3 GB in the end (delta: 65.0 MB). Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: -16.5 MB). Peak memory consumption was 48.5 MB. Max. memory is 11.5 GB. [2018-11-18 11:44:37,306 INFO L168 Benchmark]: Witness Printer took 42.29 ms. Allocated memory is still 1.3 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.0 MB). Peak memory consumption was 5.0 MB. Max. memory is 11.5 GB. [2018-11-18 11:44:37,307 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.13 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 221.26 ms. Allocated memory is still 1.0 GB. Free memory was 958.0 MB in the beginning and 941.9 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 65.28 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 157.3 MB). Free memory was 941.9 MB in the beginning and 1.2 GB in the end (delta: -210.9 MB). Peak memory consumption was 17.1 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 22.62 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 6.3 MB). Peak memory consumption was 6.3 MB. Max. memory is 11.5 GB. * RCFGBuilder took 402.55 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 39.0 MB). Peak memory consumption was 39.0 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 1815.22 ms. Allocated memory was 1.2 GB in the beginning and 1.3 GB in the end (delta: 65.0 MB). Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: -16.5 MB). Peak memory consumption was 48.5 MB. Max. memory is 11.5 GB. * Witness Printer took 42.29 ms. Allocated memory is still 1.3 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.0 MB). Peak memory consumption was 5.0 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 9 terminating modules (9 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.9 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 1116 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 1.7s and 10 iterations. TraceHistogramMax:1. Analysis of lassos took 0.9s. Construction of modules took 0.3s. Büchi inclusion checks took 0.1s. Highest rank in rank-based complementation 0. Minimization of det autom 9. Minimization of nondet autom 0. Automata minimization 0.1s AutomataMinimizationTime, 9 MinimizatonAttempts, 1169 StatesRemovedByMinimization, 4 NontrivialMinimizations. Non-live state removal took 0.0s Buchi closure took 0.0s. Biggest automaton had 1220 states and ocurred in iteration 7. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 1727 SDtfs, 1881 SDslu, 2011 SDs, 0 SdLazy, 171 SolverSat, 63 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.3s Time LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc1 concLT0 SILN0 SILU0 SILI5 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 400]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {p_last_write=0, c_dr_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1726000d=0, c_dr_pc=0, a_t=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@70f400f2=0, \result=0, \result=0, c_num_read=0, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@58ed86ff=0, c_dr_st=0, kernel_st=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4ded7211=0, q_read_ev=2, p_dw_i=1, tmp___1=1, q_req_up=0, tmp___0=0, q_write_ev=2, __retres1=1, t=0, p_dw_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@469dba24=0, q_free=1, fast_clk_edge=2, __retres1=0, p_dw_st=0, \result=0, tmp___0=0, q_ev=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5c711403=0, slow_clk_edge=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@31e0a617=0, c_last_read=0, tmp___0=0, __retres1=0, tmp=0, p_num_write=0, q_buf_0=0, __retres1=0, tmp=0, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 400]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L14] int fast_clk_edge ; [L15] int slow_clk_edge ; [L16] int q_buf_0 ; [L17] int q_free ; [L18] int q_read_ev ; [L19] int q_write_ev ; [L20] int q_req_up ; [L21] int q_ev ; [L42] int p_num_write ; [L43] int p_last_write ; [L44] int p_dw_st ; [L45] int p_dw_pc ; [L46] int p_dw_i ; [L47] int c_num_read ; [L48] int c_last_read ; [L49] int c_dr_st ; [L50] int c_dr_pc ; [L51] int c_dr_i ; [L184] static int a_t ; [L334] static int t = 0; [L545] int __retres1 ; [L549] CALL init_model() [L529] fast_clk_edge = 2 [L530] slow_clk_edge = 2 [L531] q_free = 1 [L532] q_write_ev = 2 [L533] q_read_ev = q_write_ev [L534] p_num_write = 0 [L535] p_dw_pc = 0 [L536] p_dw_i = 1 [L537] c_num_read = 0 [L538] c_dr_pc = 0 [L539] RET c_dr_i = 1 [L549] init_model() [L550] CALL start_simulation() [L467] int kernel_st ; [L468] int tmp ; [L469] int tmp___0 ; [L473] kernel_st = 0 [L474] CALL update_channels() [L248] COND FALSE, RET !((int )q_req_up == 1) [L474] update_channels() [L475] CALL init_threads() [L263] COND TRUE (int )p_dw_i == 1 [L264] p_dw_st = 0 [L268] COND TRUE (int )c_dr_i == 1 [L269] RET c_dr_st = 0 [L475] init_threads() [L476] CALL fire_delta_events() [L301] COND FALSE !((int )q_read_ev == 0) [L306] COND FALSE, RET !((int )q_write_ev == 0) [L476] fire_delta_events() [L477] CALL activate_threads() [L370] int tmp ; [L371] int tmp___0 ; [L375] CALL, EXPR is_do_write_p_triggered() [L53] int __retres1 ; [L56] COND FALSE !((int )p_dw_pc == 1) [L66] COND FALSE !((int )p_dw_pc == 2) [L76] __retres1 = 0 [L78] RET return (__retres1); [L375] EXPR is_do_write_p_triggered() [L375] tmp = is_do_write_p_triggered() [L377] COND FALSE !(\read(tmp)) [L383] CALL, EXPR is_do_read_c_triggered() [L82] int __retres1 ; [L85] COND FALSE !((int )c_dr_pc == 1) [L95] COND FALSE !((int )c_dr_pc == 2) [L105] __retres1 = 0 [L107] RET return (__retres1); [L383] EXPR is_do_read_c_triggered() [L383] tmp___0 = is_do_read_c_triggered() [L385] COND FALSE, RET !(\read(tmp___0)) [L477] activate_threads() [L478] CALL reset_delta_events() [L319] COND FALSE !((int )q_read_ev == 1) [L324] COND FALSE, RET !((int )q_write_ev == 1) [L478] reset_delta_events() [L481] COND TRUE 1 [L484] kernel_st = 1 [L485] CALL eval() [L395] int tmp ; [L396] int tmp___0 ; [L397] int tmp___1 ; Loop: [L400] COND TRUE 1 [L403] CALL, EXPR exists_runnable_thread() [L278] int __retres1 ; [L281] COND TRUE (int )p_dw_st == 0 [L282] __retres1 = 1 [L294] RET return (__retres1); [L403] EXPR exists_runnable_thread() [L403] tmp___1 = exists_runnable_thread() [L405] COND TRUE \read(tmp___1) [L410] COND TRUE (int )p_dw_st == 0 [L412] tmp = __VERIFIER_nondet_int() [L414] COND FALSE !(\read(tmp)) [L425] COND TRUE (int )c_dr_st == 0 [L427] tmp___0 = __VERIFIER_nondet_int() [L429] COND FALSE !(\read(tmp___0)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...