./Ultimate.py --spec ../../sv-benchmarks/c/Termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.01_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 5842f4b8 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_7d89a2d0-913b-4150-bbcb-0d978a79b953/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_7d89a2d0-913b-4150-bbcb-0d978a79b953/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_7d89a2d0-913b-4150-bbcb-0d978a79b953/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_7d89a2d0-913b-4150-bbcb-0d978a79b953/bin-2019/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.01_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_7d89a2d0-913b-4150-bbcb-0d978a79b953/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_7d89a2d0-913b-4150-bbcb-0d978a79b953/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 59598ef74ac7afb6c962e2cc2ba26af488759b7c ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.23-5842f4b [2018-11-18 09:24:13,439 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-18 09:24:13,440 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-18 09:24:13,447 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-18 09:24:13,447 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-18 09:24:13,448 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-18 09:24:13,449 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-18 09:24:13,450 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-18 09:24:13,451 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-18 09:24:13,451 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-18 09:24:13,452 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-18 09:24:13,452 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-18 09:24:13,453 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-18 09:24:13,454 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-18 09:24:13,455 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-18 09:24:13,455 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-18 09:24:13,456 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-18 09:24:13,457 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-18 09:24:13,458 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-18 09:24:13,459 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-18 09:24:13,460 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-18 09:24:13,461 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-18 09:24:13,462 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-18 09:24:13,462 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-18 09:24:13,463 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-18 09:24:13,463 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-18 09:24:13,464 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-18 09:24:13,465 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-18 09:24:13,465 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-18 09:24:13,466 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-18 09:24:13,466 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-18 09:24:13,467 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-18 09:24:13,467 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-18 09:24:13,467 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-18 09:24:13,468 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-18 09:24:13,468 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-18 09:24:13,468 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_7d89a2d0-913b-4150-bbcb-0d978a79b953/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2018-11-18 09:24:13,478 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-18 09:24:13,478 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-18 09:24:13,479 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-18 09:24:13,479 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-18 09:24:13,479 INFO L133 SettingsManager]: * Use SBE=true [2018-11-18 09:24:13,479 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2018-11-18 09:24:13,479 INFO L133 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2018-11-18 09:24:13,479 INFO L133 SettingsManager]: * Use old map elimination=false [2018-11-18 09:24:13,479 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false [2018-11-18 09:24:13,480 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true [2018-11-18 09:24:13,480 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2018-11-18 09:24:13,480 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-18 09:24:13,480 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-18 09:24:13,480 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-18 09:24:13,480 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-18 09:24:13,480 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-18 09:24:13,480 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-18 09:24:13,481 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2018-11-18 09:24:13,481 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2018-11-18 09:24:13,481 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2018-11-18 09:24:13,481 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-18 09:24:13,481 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-18 09:24:13,481 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false [2018-11-18 09:24:13,481 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-18 09:24:13,482 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2018-11-18 09:24:13,482 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-18 09:24:13,482 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-18 09:24:13,482 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2018-11-18 09:24:13,482 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-18 09:24:13,482 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-18 09:24:13,482 INFO L133 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2018-11-18 09:24:13,483 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-11-18 09:24:13,483 INFO L133 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_7d89a2d0-913b-4150-bbcb-0d978a79b953/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 59598ef74ac7afb6c962e2cc2ba26af488759b7c [2018-11-18 09:24:13,504 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-18 09:24:13,513 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-18 09:24:13,514 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-18 09:24:13,515 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-18 09:24:13,515 INFO L276 PluginConnector]: CDTParser initialized [2018-11-18 09:24:13,516 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_7d89a2d0-913b-4150-bbcb-0d978a79b953/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/token_ring.01_false-unreach-call_false-termination.cil.c [2018-11-18 09:24:13,551 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_7d89a2d0-913b-4150-bbcb-0d978a79b953/bin-2019/uautomizer/data/104cd9f02/07312c1532c047ec9c663342b9da3d70/FLAG3383885e0 [2018-11-18 09:24:13,953 INFO L307 CDTParser]: Found 1 translation units. [2018-11-18 09:24:13,954 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_7d89a2d0-913b-4150-bbcb-0d978a79b953/sv-benchmarks/c/systemc/token_ring.01_false-unreach-call_false-termination.cil.c [2018-11-18 09:24:13,960 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_7d89a2d0-913b-4150-bbcb-0d978a79b953/bin-2019/uautomizer/data/104cd9f02/07312c1532c047ec9c663342b9da3d70/FLAG3383885e0 [2018-11-18 09:24:13,969 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_7d89a2d0-913b-4150-bbcb-0d978a79b953/bin-2019/uautomizer/data/104cd9f02/07312c1532c047ec9c663342b9da3d70 [2018-11-18 09:24:13,971 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-18 09:24:13,972 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-18 09:24:13,972 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-18 09:24:13,972 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-18 09:24:13,975 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-18 09:24:13,975 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 09:24:13" (1/1) ... [2018-11-18 09:24:13,977 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@15a95fe6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:24:13, skipping insertion in model container [2018-11-18 09:24:13,977 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 09:24:13" (1/1) ... [2018-11-18 09:24:13,984 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-18 09:24:14,004 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-18 09:24:14,132 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 09:24:14,136 INFO L191 MainTranslator]: Completed pre-run [2018-11-18 09:24:14,163 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 09:24:14,175 INFO L195 MainTranslator]: Completed translation [2018-11-18 09:24:14,175 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:24:14 WrapperNode [2018-11-18 09:24:14,176 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-18 09:24:14,176 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-18 09:24:14,176 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-18 09:24:14,176 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-18 09:24:14,181 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:24:14" (1/1) ... [2018-11-18 09:24:14,185 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:24:14" (1/1) ... [2018-11-18 09:24:14,245 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-18 09:24:14,245 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-18 09:24:14,245 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-18 09:24:14,246 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-18 09:24:14,253 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:24:14" (1/1) ... [2018-11-18 09:24:14,254 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:24:14" (1/1) ... [2018-11-18 09:24:14,256 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:24:14" (1/1) ... [2018-11-18 09:24:14,256 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:24:14" (1/1) ... [2018-11-18 09:24:14,260 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:24:14" (1/1) ... [2018-11-18 09:24:14,267 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:24:14" (1/1) ... [2018-11-18 09:24:14,269 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:24:14" (1/1) ... [2018-11-18 09:24:14,271 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-18 09:24:14,272 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-18 09:24:14,272 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-18 09:24:14,272 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-18 09:24:14,273 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:24:14" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_7d89a2d0-913b-4150-bbcb-0d978a79b953/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 09:24:14,314 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-18 09:24:14,314 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-18 09:24:14,765 INFO L278 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-18 09:24:14,765 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 09:24:14 BoogieIcfgContainer [2018-11-18 09:24:14,765 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-18 09:24:14,766 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2018-11-18 09:24:14,766 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2018-11-18 09:24:14,768 INFO L276 PluginConnector]: BuchiAutomizer initialized [2018-11-18 09:24:14,769 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 09:24:14,769 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 18.11 09:24:13" (1/3) ... [2018-11-18 09:24:14,770 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@d7b5421 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 09:24:14, skipping insertion in model container [2018-11-18 09:24:14,770 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 09:24:14,770 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:24:14" (2/3) ... [2018-11-18 09:24:14,770 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@d7b5421 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 09:24:14, skipping insertion in model container [2018-11-18 09:24:14,770 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 09:24:14,770 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 09:24:14" (3/3) ... [2018-11-18 09:24:14,771 INFO L375 chiAutomizerObserver]: Analyzing ICFG token_ring.01_false-unreach-call_false-termination.cil.c [2018-11-18 09:24:14,802 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-18 09:24:14,803 INFO L374 BuchiCegarLoop]: Interprodecural is true [2018-11-18 09:24:14,803 INFO L375 BuchiCegarLoop]: Hoare is false [2018-11-18 09:24:14,803 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2018-11-18 09:24:14,803 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-18 09:24:14,803 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-18 09:24:14,803 INFO L379 BuchiCegarLoop]: Difference is false [2018-11-18 09:24:14,804 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-18 09:24:14,804 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2018-11-18 09:24:14,815 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 163 states. [2018-11-18 09:24:14,832 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 128 [2018-11-18 09:24:14,832 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:24:14,832 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:24:14,838 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:24:14,838 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:24:14,838 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ [2018-11-18 09:24:14,838 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 163 states. [2018-11-18 09:24:14,842 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 128 [2018-11-18 09:24:14,843 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:24:14,843 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:24:14,844 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:24:14,844 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:24:14,849 INFO L794 eck$LassoCheckResult]: Stem: 90#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 9#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 116#L393true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 82#L165true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28#L172true assume !(1 == ~m_i~0);~m_st~0 := 2; 25#L172-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 34#L177-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 95#L261true assume !(0 == ~M_E~0); 124#L261-2true assume !(0 == ~T1_E~0); 145#L266-1true assume !(0 == ~E_M~0); 31#L271-1true assume !(0 == ~E_1~0); 36#L276-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 111#L126true assume 1 == ~m_pc~0; 75#L127true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 112#L137true is_master_triggered_#res := is_master_triggered_~__retres1~0; 77#L138true activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 5#L321true assume !(0 != activate_threads_~tmp~1); 8#L321-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 138#L145true assume 1 == ~t1_pc~0; 67#L146true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 139#L156true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 69#L157true activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 10#L329true assume !(0 != activate_threads_~tmp___0~0); 15#L329-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 92#L289true assume !(1 == ~M_E~0); 88#L289-2true assume !(1 == ~T1_E~0); 96#L294-1true assume !(1 == ~E_M~0); 11#L299-1true assume !(1 == ~E_1~0); 32#L304-1true assume { :end_inline_reset_delta_events } true; 49#L430-3true [2018-11-18 09:24:14,849 INFO L796 eck$LassoCheckResult]: Loop: 49#L430-3true assume true; 44#L430-1true assume !false; 17#L431true start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_~tmp~0;havoc eval_~tmp~0; 154#L236true assume !true; 42#L251true assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 93#L165-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 121#L261-3true assume 0 == ~M_E~0;~M_E~0 := 1; 118#L261-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 140#L266-3true assume 0 == ~E_M~0;~E_M~0 := 1; 29#L271-3true assume 0 == ~E_1~0;~E_1~0 := 1; 35#L276-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 117#L126-9true assume !(1 == ~m_pc~0); 87#L126-11true is_master_triggered_~__retres1~0 := 0; 101#L137-3true is_master_triggered_#res := is_master_triggered_~__retres1~0; 47#L138-3true activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 136#L321-9true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 141#L321-11true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 108#L145-9true assume !(1 == ~t1_pc~0); 103#L145-11true is_transmit1_triggered_~__retres1~1 := 0; 164#L156-3true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 59#L157-3true activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 7#L329-9true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 149#L329-11true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 73#L289-3true assume 1 == ~M_E~0;~M_E~0 := 2; 64#L289-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 125#L294-3true assume 1 == ~E_M~0;~E_M~0 := 2; 142#L299-3true assume 1 == ~E_1~0;~E_1~0 := 2; 21#L304-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 70#L190-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 23#L202-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 147#L203-1true start_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 68#L449true assume !(0 == start_simulation_~tmp~3); 74#L449-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 66#L190-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 22#L202-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 114#L203-2true stop_simulation_#t~ret7 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 115#L404true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 41#L411true stop_simulation_#res := stop_simulation_~__retres2~0; 157#L412true start_simulation_#t~ret9 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 99#L462true assume !(0 != start_simulation_~tmp___0~1); 49#L430-3true [2018-11-18 09:24:14,853 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:24:14,853 INFO L82 PathProgramCache]: Analyzing trace with hash -704910459, now seen corresponding path program 1 times [2018-11-18 09:24:14,854 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:24:14,855 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:24:14,889 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:24:14,889 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:24:14,890 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:24:14,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:24:14,949 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:24:14,951 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:24:14,952 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:24:14,954 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 09:24:14,955 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:24:14,955 INFO L82 PathProgramCache]: Analyzing trace with hash 886580424, now seen corresponding path program 1 times [2018-11-18 09:24:14,955 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:24:14,955 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:24:14,956 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:24:14,956 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:24:14,956 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:24:14,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:24:14,964 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:24:14,964 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:24:14,964 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 09:24:14,966 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:24:14,977 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:24:14,977 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:24:14,978 INFO L87 Difference]: Start difference. First operand 163 states. Second operand 3 states. [2018-11-18 09:24:14,998 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:24:14,999 INFO L93 Difference]: Finished difference Result 161 states and 233 transitions. [2018-11-18 09:24:14,999 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:24:15,000 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 161 states and 233 transitions. [2018-11-18 09:24:15,003 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 124 [2018-11-18 09:24:15,006 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 161 states to 155 states and 227 transitions. [2018-11-18 09:24:15,007 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 155 [2018-11-18 09:24:15,008 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 155 [2018-11-18 09:24:15,008 INFO L73 IsDeterministic]: Start isDeterministic. Operand 155 states and 227 transitions. [2018-11-18 09:24:15,009 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:24:15,009 INFO L705 BuchiCegarLoop]: Abstraction has 155 states and 227 transitions. [2018-11-18 09:24:15,020 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 155 states and 227 transitions. [2018-11-18 09:24:15,030 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 155 to 155. [2018-11-18 09:24:15,030 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 155 states. [2018-11-18 09:24:15,031 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 155 states to 155 states and 227 transitions. [2018-11-18 09:24:15,032 INFO L728 BuchiCegarLoop]: Abstraction has 155 states and 227 transitions. [2018-11-18 09:24:15,032 INFO L608 BuchiCegarLoop]: Abstraction has 155 states and 227 transitions. [2018-11-18 09:24:15,032 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ [2018-11-18 09:24:15,032 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 155 states and 227 transitions. [2018-11-18 09:24:15,033 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 124 [2018-11-18 09:24:15,034 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:24:15,034 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:24:15,035 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:24:15,035 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:24:15,035 INFO L794 eck$LassoCheckResult]: Stem: 459#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 343#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 344#L393 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 455#L165 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 372#L172 assume 1 == ~m_i~0;~m_st~0 := 0; 368#L172-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 369#L177-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 381#L261 assume !(0 == ~M_E~0); 465#L261-2 assume !(0 == ~T1_E~0); 478#L266-1 assume !(0 == ~E_M~0); 377#L271-1 assume !(0 == ~E_1~0); 378#L276-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 383#L126 assume 1 == ~m_pc~0; 446#L127 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 447#L137 is_master_triggered_#res := is_master_triggered_~__retres1~0; 449#L138 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 338#L321 assume !(0 != activate_threads_~tmp~1); 339#L321-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 342#L145 assume 1 == ~t1_pc~0; 440#L146 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 441#L156 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 443#L157 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 345#L329 assume !(0 != activate_threads_~tmp___0~0); 346#L329-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 353#L289 assume !(1 == ~M_E~0); 457#L289-2 assume !(1 == ~T1_E~0); 458#L294-1 assume !(1 == ~E_M~0); 347#L299-1 assume !(1 == ~E_1~0); 348#L304-1 assume { :end_inline_reset_delta_events } true; 379#L430-3 [2018-11-18 09:24:15,035 INFO L796 eck$LassoCheckResult]: Loop: 379#L430-3 assume true; 398#L430-1 assume !false; 355#L431 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_~tmp~0;havoc eval_~tmp~0; 356#L236 assume true; 444#L212-1 assume !false; 385#L213 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 386#L190 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 376#L202 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 384#L203 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 479#L217 assume !(0 != eval_~tmp~0); 394#L251 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 395#L165-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 460#L261-3 assume 0 == ~M_E~0;~M_E~0 := 1; 472#L261-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 473#L266-3 assume 0 == ~E_M~0;~E_M~0 := 1; 373#L271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 374#L276-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 382#L126-9 assume !(1 == ~m_pc~0); 401#L126-11 is_master_triggered_~__retres1~0 := 0; 400#L137-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 402#L138-3 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 403#L321-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 484#L321-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 469#L145-9 assume 1 == ~t1_pc~0; 420#L146-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 422#L156-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 423#L157-3 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 340#L329-9 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 341#L329-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 445#L289-3 assume 1 == ~M_E~0;~M_E~0 := 2; 434#L289-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 435#L294-3 assume 1 == ~E_M~0;~E_M~0 := 2; 477#L299-3 assume 1 == ~E_1~0;~E_1~0 := 2; 360#L304-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 361#L190-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 365#L202-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 366#L203-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 437#L449 assume !(0 == start_simulation_~tmp~3); 438#L449-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 436#L190-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 363#L202-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 364#L203-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 470#L404 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 389#L411 stop_simulation_#res := stop_simulation_~__retres2~0; 390#L412 start_simulation_#t~ret9 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 463#L462 assume !(0 != start_simulation_~tmp___0~1); 379#L430-3 [2018-11-18 09:24:15,035 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:24:15,035 INFO L82 PathProgramCache]: Analyzing trace with hash -845459069, now seen corresponding path program 1 times [2018-11-18 09:24:15,036 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:24:15,036 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:24:15,036 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:24:15,036 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:24:15,037 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:24:15,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:24:15,074 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:24:15,075 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:24:15,075 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 09:24:15,075 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 09:24:15,075 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:24:15,075 INFO L82 PathProgramCache]: Analyzing trace with hash 352714075, now seen corresponding path program 1 times [2018-11-18 09:24:15,076 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:24:15,076 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:24:15,076 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:24:15,076 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:24:15,076 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:24:15,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:24:15,122 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:24:15,122 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:24:15,122 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 09:24:15,122 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:24:15,123 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:24:15,123 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:24:15,123 INFO L87 Difference]: Start difference. First operand 155 states and 227 transitions. cyclomatic complexity: 73 Second operand 3 states. [2018-11-18 09:24:15,159 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:24:15,159 INFO L93 Difference]: Finished difference Result 267 states and 381 transitions. [2018-11-18 09:24:15,160 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:24:15,160 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 267 states and 381 transitions. [2018-11-18 09:24:15,163 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 235 [2018-11-18 09:24:15,165 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 267 states to 267 states and 381 transitions. [2018-11-18 09:24:15,165 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 267 [2018-11-18 09:24:15,165 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 267 [2018-11-18 09:24:15,165 INFO L73 IsDeterministic]: Start isDeterministic. Operand 267 states and 381 transitions. [2018-11-18 09:24:15,166 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:24:15,167 INFO L705 BuchiCegarLoop]: Abstraction has 267 states and 381 transitions. [2018-11-18 09:24:15,167 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 267 states and 381 transitions. [2018-11-18 09:24:15,176 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 267 to 254. [2018-11-18 09:24:15,176 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 254 states. [2018-11-18 09:24:15,177 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 254 states to 254 states and 364 transitions. [2018-11-18 09:24:15,177 INFO L728 BuchiCegarLoop]: Abstraction has 254 states and 364 transitions. [2018-11-18 09:24:15,177 INFO L608 BuchiCegarLoop]: Abstraction has 254 states and 364 transitions. [2018-11-18 09:24:15,177 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ [2018-11-18 09:24:15,177 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 254 states and 364 transitions. [2018-11-18 09:24:15,179 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 222 [2018-11-18 09:24:15,179 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:24:15,179 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:24:15,180 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:24:15,180 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:24:15,181 INFO L794 eck$LassoCheckResult]: Stem: 894#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 774#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 775#L393 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 889#L165 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 804#L172 assume 1 == ~m_i~0;~m_st~0 := 0; 798#L172-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 799#L177-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 811#L261 assume !(0 == ~M_E~0); 901#L261-2 assume !(0 == ~T1_E~0); 924#L266-1 assume !(0 == ~E_M~0); 807#L271-1 assume !(0 == ~E_1~0); 808#L276-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 813#L126 assume !(1 == ~m_pc~0); 904#L126-2 is_master_triggered_~__retres1~0 := 0; 905#L137 is_master_triggered_#res := is_master_triggered_~__retres1~0; 883#L138 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 768#L321 assume !(0 != activate_threads_~tmp~1); 769#L321-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 773#L145 assume 1 == ~t1_pc~0; 871#L146 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 872#L156 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 877#L157 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 776#L329 assume !(0 != activate_threads_~tmp___0~0); 777#L329-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 784#L289 assume !(1 == ~M_E~0); 892#L289-2 assume !(1 == ~T1_E~0); 893#L294-1 assume !(1 == ~E_M~0); 778#L299-1 assume !(1 == ~E_1~0); 779#L304-1 assume { :end_inline_reset_delta_events } true; 809#L430-3 [2018-11-18 09:24:15,181 INFO L796 eck$LassoCheckResult]: Loop: 809#L430-3 assume true; 984#L430-1 assume !false; 983#L431 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_~tmp~0;havoc eval_~tmp~0; 898#L236 assume true; 878#L212-1 assume !false; 879#L213 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 880#L190 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 806#L202 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 934#L203 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 925#L217 assume !(0 != eval_~tmp~0); 822#L251 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 823#L165-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 895#L261-3 assume 0 == ~M_E~0;~M_E~0 := 1; 916#L261-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 917#L266-3 assume 0 == ~E_M~0;~E_M~0 := 1; 802#L271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 803#L276-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 812#L126-9 assume !(1 == ~m_pc~0); 915#L126-11 is_master_triggered_~__retres1~0 := 0; 982#L137-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 981#L138-3 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 979#L321-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 978#L321-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 977#L145-9 assume 1 == ~t1_pc~0; 853#L146-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 855#L156-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 856#L157-3 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 771#L329-9 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 772#L329-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 881#L289-3 assume 1 == ~M_E~0;~M_E~0 := 2; 868#L289-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 869#L294-3 assume 1 == ~E_M~0;~E_M~0 := 2; 923#L299-3 assume 1 == ~E_1~0;~E_1~0 := 2; 791#L304-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 792#L190-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 795#L202-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 796#L203-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 874#L449 assume !(0 == start_simulation_~tmp~3); 875#L449-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 1000#L190-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 998#L202-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 996#L203-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 994#L404 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 820#L411 stop_simulation_#res := stop_simulation_~__retres2~0; 821#L412 start_simulation_#t~ret9 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 938#L462 assume !(0 != start_simulation_~tmp___0~1); 809#L430-3 [2018-11-18 09:24:15,181 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:24:15,181 INFO L82 PathProgramCache]: Analyzing trace with hash 1269536452, now seen corresponding path program 1 times [2018-11-18 09:24:15,181 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:24:15,181 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:24:15,182 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:24:15,182 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:24:15,182 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:24:15,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:24:15,212 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:24:15,212 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:24:15,212 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 09:24:15,213 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 09:24:15,213 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:24:15,213 INFO L82 PathProgramCache]: Analyzing trace with hash 352714075, now seen corresponding path program 2 times [2018-11-18 09:24:15,213 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:24:15,213 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:24:15,214 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:24:15,214 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:24:15,214 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:24:15,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:24:15,258 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:24:15,258 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:24:15,258 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 09:24:15,258 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:24:15,259 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:24:15,259 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:24:15,259 INFO L87 Difference]: Start difference. First operand 254 states and 364 transitions. cyclomatic complexity: 112 Second operand 3 states. [2018-11-18 09:24:15,304 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:24:15,304 INFO L93 Difference]: Finished difference Result 439 states and 622 transitions. [2018-11-18 09:24:15,305 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:24:15,305 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 439 states and 622 transitions. [2018-11-18 09:24:15,308 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 402 [2018-11-18 09:24:15,310 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 439 states to 439 states and 622 transitions. [2018-11-18 09:24:15,310 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 439 [2018-11-18 09:24:15,311 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 439 [2018-11-18 09:24:15,311 INFO L73 IsDeterministic]: Start isDeterministic. Operand 439 states and 622 transitions. [2018-11-18 09:24:15,312 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:24:15,312 INFO L705 BuchiCegarLoop]: Abstraction has 439 states and 622 transitions. [2018-11-18 09:24:15,313 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 439 states and 622 transitions. [2018-11-18 09:24:15,320 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 439 to 433. [2018-11-18 09:24:15,320 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 433 states. [2018-11-18 09:24:15,321 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 433 states to 433 states and 616 transitions. [2018-11-18 09:24:15,321 INFO L728 BuchiCegarLoop]: Abstraction has 433 states and 616 transitions. [2018-11-18 09:24:15,321 INFO L608 BuchiCegarLoop]: Abstraction has 433 states and 616 transitions. [2018-11-18 09:24:15,321 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ [2018-11-18 09:24:15,321 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 433 states and 616 transitions. [2018-11-18 09:24:15,322 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 396 [2018-11-18 09:24:15,323 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:24:15,323 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:24:15,323 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:24:15,323 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:24:15,323 INFO L794 eck$LassoCheckResult]: Stem: 1593#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 1476#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 1477#L393 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 1584#L165 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1505#L172 assume 1 == ~m_i~0;~m_st~0 := 0; 1500#L172-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1501#L177-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1514#L261 assume !(0 == ~M_E~0); 1597#L261-2 assume !(0 == ~T1_E~0); 1621#L266-1 assume !(0 == ~E_M~0); 1510#L271-1 assume !(0 == ~E_1~0); 1511#L276-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1516#L126 assume !(1 == ~m_pc~0); 1606#L126-2 is_master_triggered_~__retres1~0 := 0; 1607#L137 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1578#L138 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 1470#L321 assume !(0 != activate_threads_~tmp~1); 1471#L321-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1475#L145 assume !(1 == ~t1_pc~0); 1626#L145-2 is_transmit1_triggered_~__retres1~1 := 0; 1627#L156 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1574#L157 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1478#L329 assume !(0 != activate_threads_~tmp___0~0); 1479#L329-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1486#L289 assume !(1 == ~M_E~0); 1591#L289-2 assume !(1 == ~T1_E~0); 1592#L294-1 assume !(1 == ~E_M~0); 1480#L299-1 assume !(1 == ~E_1~0); 1481#L304-1 assume { :end_inline_reset_delta_events } true; 1512#L430-3 [2018-11-18 09:24:15,323 INFO L796 eck$LassoCheckResult]: Loop: 1512#L430-3 assume true; 1529#L430-1 assume !false; 1488#L431 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_~tmp~0;havoc eval_~tmp~0; 1489#L236 assume true; 1576#L212-1 assume !false; 1518#L213 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 1519#L190 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 1509#L202 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 1517#L203 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 1624#L217 assume !(0 != eval_~tmp~0); 1625#L251 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 1875#L165-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 1873#L261-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1871#L261-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1870#L266-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1869#L271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1868#L276-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1867#L126-9 assume !(1 == ~m_pc~0); 1866#L126-11 is_master_triggered_~__retres1~0 := 0; 1865#L137-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1864#L138-3 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 1863#L321-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1862#L321-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1611#L145-9 assume !(1 == ~t1_pc~0); 1603#L145-11 is_transmit1_triggered_~__retres1~1 := 0; 1604#L156-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1557#L157-3 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1473#L329-9 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1474#L329-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1577#L289-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1568#L289-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1569#L294-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1622#L299-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1493#L304-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 1494#L190-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 1497#L202-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 1498#L203-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 1571#L449 assume !(0 == start_simulation_~tmp~3); 1572#L449-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 1570#L190-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 1495#L202-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 1496#L203-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 1613#L404 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1522#L411 stop_simulation_#res := stop_simulation_~__retres2~0; 1523#L412 start_simulation_#t~ret9 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 1598#L462 assume !(0 != start_simulation_~tmp___0~1); 1512#L430-3 [2018-11-18 09:24:15,324 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:24:15,324 INFO L82 PathProgramCache]: Analyzing trace with hash 396697797, now seen corresponding path program 1 times [2018-11-18 09:24:15,324 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:24:15,324 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:24:15,325 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:24:15,325 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 09:24:15,325 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:24:15,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:24:15,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:24:15,353 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:24:15,353 INFO L82 PathProgramCache]: Analyzing trace with hash 1132695004, now seen corresponding path program 1 times [2018-11-18 09:24:15,353 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:24:15,353 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:24:15,354 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:24:15,354 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:24:15,354 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:24:15,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:24:15,392 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:24:15,392 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:24:15,392 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 09:24:15,393 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:24:15,393 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 09:24:15,393 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 09:24:15,393 INFO L87 Difference]: Start difference. First operand 433 states and 616 transitions. cyclomatic complexity: 187 Second operand 5 states. [2018-11-18 09:24:15,483 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:24:15,484 INFO L93 Difference]: Finished difference Result 749 states and 1036 transitions. [2018-11-18 09:24:15,484 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-18 09:24:15,484 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 749 states and 1036 transitions. [2018-11-18 09:24:15,487 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 704 [2018-11-18 09:24:15,489 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 749 states to 749 states and 1036 transitions. [2018-11-18 09:24:15,490 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 749 [2018-11-18 09:24:15,490 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 749 [2018-11-18 09:24:15,490 INFO L73 IsDeterministic]: Start isDeterministic. Operand 749 states and 1036 transitions. [2018-11-18 09:24:15,491 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:24:15,491 INFO L705 BuchiCegarLoop]: Abstraction has 749 states and 1036 transitions. [2018-11-18 09:24:15,492 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 749 states and 1036 transitions. [2018-11-18 09:24:15,499 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 749 to 445. [2018-11-18 09:24:15,499 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 445 states. [2018-11-18 09:24:15,500 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 445 states to 445 states and 628 transitions. [2018-11-18 09:24:15,500 INFO L728 BuchiCegarLoop]: Abstraction has 445 states and 628 transitions. [2018-11-18 09:24:15,500 INFO L608 BuchiCegarLoop]: Abstraction has 445 states and 628 transitions. [2018-11-18 09:24:15,500 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ [2018-11-18 09:24:15,500 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 445 states and 628 transitions. [2018-11-18 09:24:15,502 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 408 [2018-11-18 09:24:15,502 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:24:15,502 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:24:15,503 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:24:15,503 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:24:15,503 INFO L794 eck$LassoCheckResult]: Stem: 2793#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 2674#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 2675#L393 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 2786#L165 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2704#L172 assume 1 == ~m_i~0;~m_st~0 := 0; 2698#L172-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2699#L177-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2712#L261 assume !(0 == ~M_E~0); 2800#L261-2 assume !(0 == ~T1_E~0); 2819#L266-1 assume !(0 == ~E_M~0); 2708#L271-1 assume !(0 == ~E_1~0); 2709#L276-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2715#L126 assume !(1 == ~m_pc~0); 2803#L126-2 is_master_triggered_~__retres1~0 := 0; 2804#L137 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2780#L138 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 2669#L321 assume !(0 != activate_threads_~tmp~1); 2670#L321-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2673#L145 assume !(1 == ~t1_pc~0); 2822#L145-2 is_transmit1_triggered_~__retres1~1 := 0; 2823#L156 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2775#L157 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2676#L329 assume !(0 != activate_threads_~tmp___0~0); 2677#L329-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2684#L289 assume !(1 == ~M_E~0); 2791#L289-2 assume !(1 == ~T1_E~0); 2792#L294-1 assume !(1 == ~E_M~0); 2678#L299-1 assume !(1 == ~E_1~0); 2679#L304-1 assume { :end_inline_reset_delta_events } true; 2710#L430-3 [2018-11-18 09:24:15,504 INFO L796 eck$LassoCheckResult]: Loop: 2710#L430-3 assume true; 2959#L430-1 assume !false; 2957#L431 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_~tmp~0;havoc eval_~tmp~0; 2954#L236 assume true; 2952#L212-1 assume !false; 2911#L213 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 2909#L190 assume !(0 == ~m_st~0); 2896#L194 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2 := 0; 2893#L202 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 2883#L203 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 2878#L217 assume !(0 != eval_~tmp~0); 2873#L251 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 2874#L165-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 2866#L261-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2867#L261-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2859#L266-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2860#L271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2713#L276-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2714#L126-9 assume !(1 == ~m_pc~0); 2789#L126-11 is_master_triggered_~__retres1~0 := 0; 2790#L137-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2734#L138-3 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 2735#L321-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2996#L321-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2995#L145-9 assume !(1 == ~t1_pc~0); 2994#L145-11 is_transmit1_triggered_~__retres1~1 := 0; 2993#L156-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2992#L157-3 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2991#L329-9 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2990#L329-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2989#L289-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2988#L289-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2987#L294-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2986#L299-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2985#L304-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 2984#L190-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 2980#L202-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 2977#L203-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 2972#L449 assume !(0 == start_simulation_~tmp~3); 2968#L449-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 2967#L190-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 2965#L202-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 2964#L203-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 2963#L404 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2962#L411 stop_simulation_#res := stop_simulation_~__retres2~0; 2961#L412 start_simulation_#t~ret9 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 2960#L462 assume !(0 != start_simulation_~tmp___0~1); 2710#L430-3 [2018-11-18 09:24:15,504 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:24:15,504 INFO L82 PathProgramCache]: Analyzing trace with hash 396697797, now seen corresponding path program 2 times [2018-11-18 09:24:15,504 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:24:15,504 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:24:15,505 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:24:15,505 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:24:15,505 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:24:15,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:24:15,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:24:15,517 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:24:15,517 INFO L82 PathProgramCache]: Analyzing trace with hash -1567992113, now seen corresponding path program 1 times [2018-11-18 09:24:15,517 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:24:15,517 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:24:15,518 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:24:15,518 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 09:24:15,518 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:24:15,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:24:15,593 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:24:15,593 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:24:15,593 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 09:24:15,594 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:24:15,594 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 09:24:15,594 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 09:24:15,594 INFO L87 Difference]: Start difference. First operand 445 states and 628 transitions. cyclomatic complexity: 187 Second operand 5 states. [2018-11-18 09:24:15,668 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:24:15,668 INFO L93 Difference]: Finished difference Result 856 states and 1193 transitions. [2018-11-18 09:24:15,669 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 09:24:15,669 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 856 states and 1193 transitions. [2018-11-18 09:24:15,673 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 815 [2018-11-18 09:24:15,675 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 856 states to 856 states and 1193 transitions. [2018-11-18 09:24:15,675 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 856 [2018-11-18 09:24:15,676 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 856 [2018-11-18 09:24:15,676 INFO L73 IsDeterministic]: Start isDeterministic. Operand 856 states and 1193 transitions. [2018-11-18 09:24:15,677 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:24:15,677 INFO L705 BuchiCegarLoop]: Abstraction has 856 states and 1193 transitions. [2018-11-18 09:24:15,678 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 856 states and 1193 transitions. [2018-11-18 09:24:15,683 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 856 to 466. [2018-11-18 09:24:15,683 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 466 states. [2018-11-18 09:24:15,684 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 466 states to 466 states and 643 transitions. [2018-11-18 09:24:15,684 INFO L728 BuchiCegarLoop]: Abstraction has 466 states and 643 transitions. [2018-11-18 09:24:15,684 INFO L608 BuchiCegarLoop]: Abstraction has 466 states and 643 transitions. [2018-11-18 09:24:15,684 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ [2018-11-18 09:24:15,684 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 466 states and 643 transitions. [2018-11-18 09:24:15,686 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 429 [2018-11-18 09:24:15,686 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:24:15,686 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:24:15,687 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:24:15,687 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:24:15,687 INFO L794 eck$LassoCheckResult]: Stem: 4106#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 3988#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 3989#L393 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 4098#L165 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4016#L172 assume 1 == ~m_i~0;~m_st~0 := 0; 4012#L172-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4013#L177-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4026#L261 assume !(0 == ~M_E~0); 4110#L261-2 assume !(0 == ~T1_E~0); 4141#L266-1 assume !(0 == ~E_M~0); 4022#L271-1 assume !(0 == ~E_1~0); 4023#L276-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4029#L126 assume !(1 == ~m_pc~0); 4120#L126-2 is_master_triggered_~__retres1~0 := 0; 4121#L137 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4092#L138 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 3982#L321 assume !(0 != activate_threads_~tmp~1); 3983#L321-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3987#L145 assume !(1 == ~t1_pc~0); 4145#L145-2 is_transmit1_triggered_~__retres1~1 := 0; 4146#L156 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4089#L157 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 3990#L329 assume !(0 != activate_threads_~tmp___0~0); 3991#L329-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3998#L289 assume !(1 == ~M_E~0); 4104#L289-2 assume !(1 == ~T1_E~0); 4105#L294-1 assume !(1 == ~E_M~0); 3992#L299-1 assume !(1 == ~E_1~0); 3993#L304-1 assume { :end_inline_reset_delta_events } true; 4024#L430-3 [2018-11-18 09:24:15,687 INFO L796 eck$LassoCheckResult]: Loop: 4024#L430-3 assume true; 4291#L430-1 assume !false; 4290#L431 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_~tmp~0;havoc eval_~tmp~0; 4210#L236 assume true; 4289#L212-1 assume !false; 4288#L213 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 4285#L190 assume !(0 == ~m_st~0); 4286#L194 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2 := 0; 4287#L202 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 4281#L203 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 4282#L217 assume !(0 != eval_~tmp~0); 4343#L251 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 4342#L165-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 4341#L261-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4340#L261-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4339#L266-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4338#L271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4027#L276-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4028#L126-9 assume !(1 == ~m_pc~0); 4131#L126-11 is_master_triggered_~__retres1~0 := 0; 4335#L137-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4334#L138-3 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 4333#L321-9 assume !(0 != activate_threads_~tmp~1); 4332#L321-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4331#L145-9 assume !(1 == ~t1_pc~0); 4329#L145-11 is_transmit1_triggered_~__retres1~1 := 0; 4327#L156-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4325#L157-3 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 4323#L329-9 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4321#L329-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4319#L289-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4317#L289-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4315#L294-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4313#L299-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4311#L304-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 4309#L190-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 4306#L202-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 4304#L203-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 4302#L449 assume !(0 == start_simulation_~tmp~3); 4300#L449-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 4299#L190-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 4297#L202-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 4296#L203-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 4295#L404 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4294#L411 stop_simulation_#res := stop_simulation_~__retres2~0; 4293#L412 start_simulation_#t~ret9 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 4292#L462 assume !(0 != start_simulation_~tmp___0~1); 4024#L430-3 [2018-11-18 09:24:15,688 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:24:15,688 INFO L82 PathProgramCache]: Analyzing trace with hash 396697797, now seen corresponding path program 3 times [2018-11-18 09:24:15,688 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:24:15,688 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:24:15,689 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:24:15,689 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:24:15,689 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:24:15,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:24:15,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:24:15,699 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:24:15,699 INFO L82 PathProgramCache]: Analyzing trace with hash -1427443503, now seen corresponding path program 1 times [2018-11-18 09:24:15,699 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:24:15,699 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:24:15,700 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:24:15,700 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 09:24:15,700 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:24:15,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:24:15,736 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:24:15,736 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:24:15,736 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:24:15,736 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:24:15,736 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:24:15,737 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:24:15,737 INFO L87 Difference]: Start difference. First operand 466 states and 643 transitions. cyclomatic complexity: 181 Second operand 3 states. [2018-11-18 09:24:15,768 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:24:15,769 INFO L93 Difference]: Finished difference Result 676 states and 910 transitions. [2018-11-18 09:24:15,769 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:24:15,769 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 676 states and 910 transitions. [2018-11-18 09:24:15,772 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 632 [2018-11-18 09:24:15,774 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 676 states to 676 states and 910 transitions. [2018-11-18 09:24:15,774 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 676 [2018-11-18 09:24:15,774 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 676 [2018-11-18 09:24:15,775 INFO L73 IsDeterministic]: Start isDeterministic. Operand 676 states and 910 transitions. [2018-11-18 09:24:15,776 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:24:15,776 INFO L705 BuchiCegarLoop]: Abstraction has 676 states and 910 transitions. [2018-11-18 09:24:15,776 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 676 states and 910 transitions. [2018-11-18 09:24:15,781 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 676 to 659. [2018-11-18 09:24:15,781 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 659 states. [2018-11-18 09:24:15,783 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 659 states to 659 states and 889 transitions. [2018-11-18 09:24:15,783 INFO L728 BuchiCegarLoop]: Abstraction has 659 states and 889 transitions. [2018-11-18 09:24:15,783 INFO L608 BuchiCegarLoop]: Abstraction has 659 states and 889 transitions. [2018-11-18 09:24:15,783 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ [2018-11-18 09:24:15,783 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 659 states and 889 transitions. [2018-11-18 09:24:15,785 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 615 [2018-11-18 09:24:15,785 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:24:15,785 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:24:15,786 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:24:15,786 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:24:15,786 INFO L794 eck$LassoCheckResult]: Stem: 5256#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 5136#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 5137#L393 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 5247#L165 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5166#L172 assume 1 == ~m_i~0;~m_st~0 := 0; 5161#L172-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5162#L177-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5176#L261 assume !(0 == ~M_E~0); 5260#L261-2 assume !(0 == ~T1_E~0); 5287#L266-1 assume !(0 == ~E_M~0); 5172#L271-1 assume !(0 == ~E_1~0); 5173#L276-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5178#L126 assume !(1 == ~m_pc~0); 5268#L126-2 is_master_triggered_~__retres1~0 := 0; 5269#L137 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5241#L138 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 5130#L321 assume !(0 != activate_threads_~tmp~1); 5131#L321-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5135#L145 assume !(1 == ~t1_pc~0); 5291#L145-2 is_transmit1_triggered_~__retres1~1 := 0; 5292#L156 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5238#L157 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 5138#L329 assume !(0 != activate_threads_~tmp___0~0); 5139#L329-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5146#L289 assume !(1 == ~M_E~0); 5254#L289-2 assume !(1 == ~T1_E~0); 5255#L294-1 assume !(1 == ~E_M~0); 5140#L299-1 assume !(1 == ~E_1~0); 5141#L304-1 assume { :end_inline_reset_delta_events } true; 5174#L430-3 assume true; 5382#L430-1 assume !false; 5376#L431 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_~tmp~0;havoc eval_~tmp~0; 5373#L236 [2018-11-18 09:24:15,787 INFO L796 eck$LassoCheckResult]: Loop: 5373#L236 assume true; 5371#L212-1 assume !false; 5368#L213 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 5366#L190 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 5364#L202 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 5359#L203 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 5356#L217 assume 0 != eval_~tmp~0; 5355#L217-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 5353#L225 assume !(0 != eval_~tmp_ndt_1~0); 5354#L222 assume !(0 == ~t1_st~0); 5373#L236 [2018-11-18 09:24:15,787 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:24:15,787 INFO L82 PathProgramCache]: Analyzing trace with hash -1725805832, now seen corresponding path program 1 times [2018-11-18 09:24:15,787 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:24:15,787 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:24:15,788 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:24:15,788 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:24:15,788 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:24:15,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:24:15,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:24:15,798 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:24:15,798 INFO L82 PathProgramCache]: Analyzing trace with hash 1423260399, now seen corresponding path program 1 times [2018-11-18 09:24:15,798 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:24:15,798 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:24:15,799 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:24:15,799 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:24:15,799 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:24:15,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:24:15,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:24:15,804 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:24:15,804 INFO L82 PathProgramCache]: Analyzing trace with hash 801864998, now seen corresponding path program 1 times [2018-11-18 09:24:15,804 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:24:15,804 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:24:15,805 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:24:15,805 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:24:15,805 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:24:15,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:24:15,831 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:24:15,831 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:24:15,832 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 09:24:15,876 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:24:15,876 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:24:15,876 INFO L87 Difference]: Start difference. First operand 659 states and 889 transitions. cyclomatic complexity: 236 Second operand 3 states. [2018-11-18 09:24:16,010 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:24:16,010 INFO L93 Difference]: Finished difference Result 1105 states and 1468 transitions. [2018-11-18 09:24:16,014 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:24:16,014 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1105 states and 1468 transitions. [2018-11-18 09:24:16,020 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 869 [2018-11-18 09:24:16,024 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1105 states to 1105 states and 1468 transitions. [2018-11-18 09:24:16,024 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1105 [2018-11-18 09:24:16,025 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1105 [2018-11-18 09:24:16,026 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1105 states and 1468 transitions. [2018-11-18 09:24:16,027 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:24:16,027 INFO L705 BuchiCegarLoop]: Abstraction has 1105 states and 1468 transitions. [2018-11-18 09:24:16,028 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1105 states and 1468 transitions. [2018-11-18 09:24:16,042 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1105 to 1085. [2018-11-18 09:24:16,042 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1085 states. [2018-11-18 09:24:16,045 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1085 states to 1085 states and 1448 transitions. [2018-11-18 09:24:16,045 INFO L728 BuchiCegarLoop]: Abstraction has 1085 states and 1448 transitions. [2018-11-18 09:24:16,045 INFO L608 BuchiCegarLoop]: Abstraction has 1085 states and 1448 transitions. [2018-11-18 09:24:16,045 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ [2018-11-18 09:24:16,046 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1085 states and 1448 transitions. [2018-11-18 09:24:16,050 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 849 [2018-11-18 09:24:16,050 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:24:16,051 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:24:16,051 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:24:16,051 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:24:16,051 INFO L794 eck$LassoCheckResult]: Stem: 7030#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 6909#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 6910#L393 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 7021#L165 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6941#L172 assume 1 == ~m_i~0;~m_st~0 := 0; 6933#L172-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 6934#L177-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7635#L261 assume !(0 == ~M_E~0); 7634#L261-2 assume !(0 == ~T1_E~0); 7633#L266-1 assume !(0 == ~E_M~0); 7632#L271-1 assume !(0 == ~E_1~0); 7631#L276-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7630#L126 assume !(1 == ~m_pc~0); 7629#L126-2 is_master_triggered_~__retres1~0 := 0; 7628#L137 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7627#L138 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 7626#L321 assume !(0 != activate_threads_~tmp~1); 7625#L321-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7624#L145 assume !(1 == ~t1_pc~0); 7623#L145-2 is_transmit1_triggered_~__retres1~1 := 0; 7622#L156 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7621#L157 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 7620#L329 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6912#L329-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6919#L289 assume !(1 == ~M_E~0); 7028#L289-2 assume !(1 == ~T1_E~0); 7029#L294-1 assume !(1 == ~E_M~0); 6913#L299-1 assume !(1 == ~E_1~0); 6914#L304-1 assume { :end_inline_reset_delta_events } true; 6946#L430-3 assume true; 7852#L430-1 assume !false; 7832#L431 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_~tmp~0;havoc eval_~tmp~0; 7816#L236 [2018-11-18 09:24:16,052 INFO L796 eck$LassoCheckResult]: Loop: 7816#L236 assume true; 7813#L212-1 assume !false; 7811#L213 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 7809#L190 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 7807#L202 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 7806#L203 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 7804#L217 assume 0 != eval_~tmp~0; 7802#L217-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 7089#L225 assume !(0 != eval_~tmp_ndt_1~0); 7090#L222 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 7207#L239 assume !(0 != eval_~tmp_ndt_2~0); 7816#L236 [2018-11-18 09:24:16,052 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:24:16,052 INFO L82 PathProgramCache]: Analyzing trace with hash 590449212, now seen corresponding path program 1 times [2018-11-18 09:24:16,052 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:24:16,052 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:24:16,053 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:24:16,053 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:24:16,053 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:24:16,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:24:16,086 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:24:16,086 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:24:16,086 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:24:16,087 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 09:24:16,087 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:24:16,087 INFO L82 PathProgramCache]: Analyzing trace with hash 1171397124, now seen corresponding path program 1 times [2018-11-18 09:24:16,088 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:24:16,088 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:24:16,089 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:24:16,089 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:24:16,089 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:24:16,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:24:16,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:24:16,148 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:24:16,148 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:24:16,148 INFO L87 Difference]: Start difference. First operand 1085 states and 1448 transitions. cyclomatic complexity: 373 Second operand 3 states. [2018-11-18 09:24:16,155 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:24:16,155 INFO L93 Difference]: Finished difference Result 651 states and 865 transitions. [2018-11-18 09:24:16,156 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:24:16,156 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 651 states and 865 transitions. [2018-11-18 09:24:16,159 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 590 [2018-11-18 09:24:16,162 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 651 states to 651 states and 865 transitions. [2018-11-18 09:24:16,162 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 651 [2018-11-18 09:24:16,163 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 651 [2018-11-18 09:24:16,163 INFO L73 IsDeterministic]: Start isDeterministic. Operand 651 states and 865 transitions. [2018-11-18 09:24:16,164 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:24:16,164 INFO L705 BuchiCegarLoop]: Abstraction has 651 states and 865 transitions. [2018-11-18 09:24:16,164 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 651 states and 865 transitions. [2018-11-18 09:24:16,171 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 651 to 651. [2018-11-18 09:24:16,171 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 651 states. [2018-11-18 09:24:16,172 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 651 states to 651 states and 865 transitions. [2018-11-18 09:24:16,172 INFO L728 BuchiCegarLoop]: Abstraction has 651 states and 865 transitions. [2018-11-18 09:24:16,173 INFO L608 BuchiCegarLoop]: Abstraction has 651 states and 865 transitions. [2018-11-18 09:24:16,173 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ [2018-11-18 09:24:16,173 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 651 states and 865 transitions. [2018-11-18 09:24:16,175 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 590 [2018-11-18 09:24:16,175 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:24:16,175 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:24:16,175 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:24:16,176 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:24:16,176 INFO L794 eck$LassoCheckResult]: Stem: 8770#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 8651#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 8652#L393 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 8761#L165 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8681#L172 assume 1 == ~m_i~0;~m_st~0 := 0; 8675#L172-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8676#L177-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8688#L261 assume !(0 == ~M_E~0); 8777#L261-2 assume !(0 == ~T1_E~0); 8800#L266-1 assume !(0 == ~E_M~0); 8684#L271-1 assume !(0 == ~E_1~0); 8685#L276-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8690#L126 assume !(1 == ~m_pc~0); 8782#L126-2 is_master_triggered_~__retres1~0 := 0; 8783#L137 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8755#L138 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 8645#L321 assume !(0 != activate_threads_~tmp~1); 8646#L321-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8650#L145 assume !(1 == ~t1_pc~0); 8805#L145-2 is_transmit1_triggered_~__retres1~1 := 0; 8806#L156 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8750#L157 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 8653#L329 assume !(0 != activate_threads_~tmp___0~0); 8654#L329-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8661#L289 assume !(1 == ~M_E~0); 8768#L289-2 assume !(1 == ~T1_E~0); 8769#L294-1 assume !(1 == ~E_M~0); 8655#L299-1 assume !(1 == ~E_1~0); 8656#L304-1 assume { :end_inline_reset_delta_events } true; 8686#L430-3 assume true; 8705#L430-1 assume !false; 8663#L431 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_~tmp~0;havoc eval_~tmp~0; 8664#L236 [2018-11-18 09:24:16,176 INFO L796 eck$LassoCheckResult]: Loop: 8664#L236 assume true; 9235#L212-1 assume !false; 9234#L213 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 9233#L190 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 9232#L202 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 9230#L203 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 9227#L217 assume 0 != eval_~tmp~0; 9226#L217-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 8818#L225 assume !(0 != eval_~tmp_ndt_1~0); 8813#L222 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 8772#L239 assume !(0 != eval_~tmp_ndt_2~0); 8664#L236 [2018-11-18 09:24:16,176 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:24:16,176 INFO L82 PathProgramCache]: Analyzing trace with hash -1725805832, now seen corresponding path program 2 times [2018-11-18 09:24:16,176 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:24:16,176 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:24:16,177 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:24:16,177 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:24:16,177 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:24:16,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:24:16,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:24:16,185 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:24:16,185 INFO L82 PathProgramCache]: Analyzing trace with hash 1171397124, now seen corresponding path program 2 times [2018-11-18 09:24:16,185 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:24:16,185 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:24:16,186 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:24:16,186 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 09:24:16,186 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:24:16,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:24:16,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:24:16,190 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:24:16,190 INFO L82 PathProgramCache]: Analyzing trace with hash -911991123, now seen corresponding path program 1 times [2018-11-18 09:24:16,191 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:24:16,191 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:24:16,191 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:24:16,191 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 09:24:16,191 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:24:16,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:24:16,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:24:16,355 WARN L180 SmtUtils]: Spent 114.00 ms on a formula simplification. DAG size of input: 74 DAG size of output: 52 [2018-11-18 09:24:16,467 WARN L180 SmtUtils]: Spent 106.00 ms on a formula simplification that was a NOOP. DAG size: 42 [2018-11-18 09:24:16,491 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 18.11 09:24:16 BoogieIcfgContainer [2018-11-18 09:24:16,491 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2018-11-18 09:24:16,492 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-18 09:24:16,492 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-18 09:24:16,492 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-18 09:24:16,492 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 09:24:14" (3/4) ... [2018-11-18 09:24:16,495 INFO L141 WitnessPrinter]: Generating witness for non-termination counterexample [2018-11-18 09:24:16,539 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_7d89a2d0-913b-4150-bbcb-0d978a79b953/bin-2019/uautomizer/witness.graphml [2018-11-18 09:24:16,539 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-18 09:24:16,540 INFO L168 Benchmark]: Toolchain (without parser) took 2568.74 ms. Allocated memory was 1.0 GB in the beginning and 1.3 GB in the end (delta: 252.2 MB). Free memory was 956.4 MB in the beginning and 1.2 GB in the end (delta: -281.4 MB). There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 09:24:16,541 INFO L168 Benchmark]: CDTParser took 0.12 ms. Allocated memory is still 1.0 GB. Free memory is still 982.7 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 09:24:16,541 INFO L168 Benchmark]: CACSL2BoogieTranslator took 203.46 ms. Allocated memory is still 1.0 GB. Free memory was 956.4 MB in the beginning and 940.3 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. [2018-11-18 09:24:16,541 INFO L168 Benchmark]: Boogie Procedure Inliner took 69.24 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 181.4 MB). Free memory was 940.3 MB in the beginning and 1.2 GB in the end (delta: -233.0 MB). Peak memory consumption was 14.7 MB. Max. memory is 11.5 GB. [2018-11-18 09:24:16,541 INFO L168 Benchmark]: Boogie Preprocessor took 26.14 ms. Allocated memory is still 1.2 GB. Free memory is still 1.2 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 09:24:16,542 INFO L168 Benchmark]: RCFGBuilder took 493.81 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 46.3 MB). Peak memory consumption was 46.3 MB. Max. memory is 11.5 GB. [2018-11-18 09:24:16,542 INFO L168 Benchmark]: BuchiAutomizer took 1725.60 ms. Allocated memory was 1.2 GB in the beginning and 1.3 GB in the end (delta: 70.8 MB). Free memory was 1.1 GB in the beginning and 1.2 GB in the end (delta: -110.7 MB). Peak memory consumption was 271.6 MB. Max. memory is 11.5 GB. [2018-11-18 09:24:16,542 INFO L168 Benchmark]: Witness Printer took 47.68 ms. Allocated memory is still 1.3 GB. Free memory is still 1.2 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 09:24:16,543 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.12 ms. Allocated memory is still 1.0 GB. Free memory is still 982.7 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 203.46 ms. Allocated memory is still 1.0 GB. Free memory was 956.4 MB in the beginning and 940.3 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 69.24 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 181.4 MB). Free memory was 940.3 MB in the beginning and 1.2 GB in the end (delta: -233.0 MB). Peak memory consumption was 14.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 26.14 ms. Allocated memory is still 1.2 GB. Free memory is still 1.2 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 493.81 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 46.3 MB). Peak memory consumption was 46.3 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 1725.60 ms. Allocated memory was 1.2 GB in the beginning and 1.3 GB in the end (delta: 70.8 MB). Free memory was 1.1 GB in the beginning and 1.2 GB in the end (delta: -110.7 MB). Peak memory consumption was 271.6 MB. Max. memory is 11.5 GB. * Witness Printer took 47.68 ms. Allocated memory is still 1.3 GB. Free memory is still 1.2 GB. There was no memory consumed. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 8 terminating modules (8 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.8 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 651 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 1.6s and 9 iterations. TraceHistogramMax:1. Analysis of lassos took 0.9s. Construction of modules took 0.2s. Büchi inclusion checks took 0.1s. Highest rank in rank-based complementation 0. Minimization of det autom 8. Minimization of nondet autom 0. Automata minimization 0.0s AutomataMinimizationTime, 8 MinimizatonAttempts, 750 StatesRemovedByMinimization, 6 NontrivialMinimizations. Non-live state removal took 0.0s Buchi closure took 0.0s. Biggest automaton had 1085 states and ocurred in iteration 7. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 1801 SDtfs, 2041 SDslu, 2156 SDs, 0 SdLazy, 173 SolverSat, 62 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.2s Time LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc1 concLT0 SILN1 SILU0 SILI3 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 212]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {\result=0, token=0, __retres1=0, tmp=1, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@373538ad=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1a65d89e=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2d682768=0, kernel_st=1, __retres1=0, tmp___0=0, t1_pc=0, __retres1=1, T1_E=2, \result=0, E_1=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6f84f9ac=0, tmp_ndt_1=0, M_E=2, tmp_ndt_2=0, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@71eb9305=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@343fc7b1=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3e0a1e77=0, t1_st=0, local=0, m_st=0, E_M=2, tmp___0=0, tmp=0, __retres1=0, t1_i=1, m_pc=0, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 212]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int m_st ; [L17] int t1_st ; [L18] int m_i ; [L19] int t1_i ; [L20] int M_E = 2; [L21] int T1_E = 2; [L22] int E_M = 2; [L23] int E_1 = 2; [L27] int token ; [L29] int local ; [L475] int __retres1 ; [L479] CALL init_model() [L390] m_i = 1 [L391] RET t1_i = 1 [L479] init_model() [L480] CALL start_simulation() [L416] int kernel_st ; [L417] int tmp ; [L418] int tmp___0 ; [L422] kernel_st = 0 [L423] FCALL update_channels() [L424] CALL init_threads() [L172] COND TRUE m_i == 1 [L173] m_st = 0 [L177] COND TRUE t1_i == 1 [L178] RET t1_st = 0 [L424] init_threads() [L425] CALL fire_delta_events() [L261] COND FALSE !(M_E == 0) [L266] COND FALSE !(T1_E == 0) [L271] COND FALSE !(E_M == 0) [L276] COND FALSE, RET !(E_1 == 0) [L425] fire_delta_events() [L426] CALL activate_threads() [L314] int tmp ; [L315] int tmp___0 ; [L319] CALL, EXPR is_master_triggered() [L123] int __retres1 ; [L126] COND FALSE !(m_pc == 1) [L136] __retres1 = 0 [L138] RET return (__retres1); [L319] EXPR is_master_triggered() [L319] tmp = is_master_triggered() [L321] COND FALSE !(\read(tmp)) [L327] CALL, EXPR is_transmit1_triggered() [L142] int __retres1 ; [L145] COND FALSE !(t1_pc == 1) [L155] __retres1 = 0 [L157] RET return (__retres1); [L327] EXPR is_transmit1_triggered() [L327] tmp___0 = is_transmit1_triggered() [L329] COND FALSE, RET !(\read(tmp___0)) [L426] activate_threads() [L427] CALL reset_delta_events() [L289] COND FALSE !(M_E == 1) [L294] COND FALSE !(T1_E == 1) [L299] COND FALSE !(E_M == 1) [L304] COND FALSE, RET !(E_1 == 1) [L427] reset_delta_events() [L430] COND TRUE 1 [L433] kernel_st = 1 [L434] CALL eval() [L208] int tmp ; Loop: [L212] COND TRUE 1 [L215] CALL, EXPR exists_runnable_thread() [L187] int __retres1 ; [L190] COND TRUE m_st == 0 [L191] __retres1 = 1 [L203] RET return (__retres1); [L215] EXPR exists_runnable_thread() [L215] tmp = exists_runnable_thread() [L217] COND TRUE \read(tmp) [L222] COND TRUE m_st == 0 [L223] int tmp_ndt_1; [L224] tmp_ndt_1 = __VERIFIER_nondet_int() [L225] COND FALSE !(\read(tmp_ndt_1)) [L236] COND TRUE t1_st == 0 [L237] int tmp_ndt_2; [L238] tmp_ndt_2 = __VERIFIER_nondet_int() [L239] COND FALSE !(\read(tmp_ndt_2)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...