./Ultimate.py --spec ../../sv-benchmarks/c/Termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.03_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 5842f4b8 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_7f1434c4-8cda-4b7d-9907-b179c1c37dd0/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_7f1434c4-8cda-4b7d-9907-b179c1c37dd0/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_7f1434c4-8cda-4b7d-9907-b179c1c37dd0/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_7f1434c4-8cda-4b7d-9907-b179c1c37dd0/bin-2019/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.03_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_7f1434c4-8cda-4b7d-9907-b179c1c37dd0/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_7f1434c4-8cda-4b7d-9907-b179c1c37dd0/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 69fb30bd96659b6c61b59030d7ea8c3053fedc35 ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.23-5842f4b [2018-11-18 11:32:13,003 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-18 11:32:13,004 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-18 11:32:13,011 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-18 11:32:13,011 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-18 11:32:13,011 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-18 11:32:13,012 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-18 11:32:13,013 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-18 11:32:13,014 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-18 11:32:13,015 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-18 11:32:13,015 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-18 11:32:13,015 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-18 11:32:13,016 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-18 11:32:13,017 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-18 11:32:13,017 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-18 11:32:13,018 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-18 11:32:13,018 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-18 11:32:13,020 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-18 11:32:13,021 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-18 11:32:13,022 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-18 11:32:13,023 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-18 11:32:13,023 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-18 11:32:13,025 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-18 11:32:13,025 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-18 11:32:13,025 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-18 11:32:13,026 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-18 11:32:13,026 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-18 11:32:13,027 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-18 11:32:13,028 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-18 11:32:13,028 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-18 11:32:13,028 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-18 11:32:13,029 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-18 11:32:13,029 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-18 11:32:13,029 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-18 11:32:13,030 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-18 11:32:13,030 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-18 11:32:13,030 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_7f1434c4-8cda-4b7d-9907-b179c1c37dd0/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2018-11-18 11:32:13,040 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-18 11:32:13,041 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-18 11:32:13,042 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-18 11:32:13,042 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-18 11:32:13,042 INFO L133 SettingsManager]: * Use SBE=true [2018-11-18 11:32:13,042 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2018-11-18 11:32:13,042 INFO L133 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2018-11-18 11:32:13,042 INFO L133 SettingsManager]: * Use old map elimination=false [2018-11-18 11:32:13,042 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false [2018-11-18 11:32:13,043 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true [2018-11-18 11:32:13,043 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2018-11-18 11:32:13,043 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-18 11:32:13,043 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-18 11:32:13,043 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-18 11:32:13,043 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-18 11:32:13,043 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-18 11:32:13,043 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-18 11:32:13,044 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2018-11-18 11:32:13,044 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2018-11-18 11:32:13,044 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2018-11-18 11:32:13,044 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-18 11:32:13,044 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-18 11:32:13,044 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false [2018-11-18 11:32:13,044 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-18 11:32:13,044 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2018-11-18 11:32:13,045 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-18 11:32:13,045 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-18 11:32:13,045 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2018-11-18 11:32:13,045 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-18 11:32:13,045 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-18 11:32:13,045 INFO L133 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2018-11-18 11:32:13,046 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-11-18 11:32:13,046 INFO L133 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_7f1434c4-8cda-4b7d-9907-b179c1c37dd0/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 69fb30bd96659b6c61b59030d7ea8c3053fedc35 [2018-11-18 11:32:13,071 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-18 11:32:13,080 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-18 11:32:13,082 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-18 11:32:13,083 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-18 11:32:13,083 INFO L276 PluginConnector]: CDTParser initialized [2018-11-18 11:32:13,084 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_7f1434c4-8cda-4b7d-9907-b179c1c37dd0/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/token_ring.03_false-unreach-call_false-termination.cil.c [2018-11-18 11:32:13,124 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_7f1434c4-8cda-4b7d-9907-b179c1c37dd0/bin-2019/uautomizer/data/221e49d43/edbedd7bc3e946efae39ebe0ebb422f7/FLAGfc6ada384 [2018-11-18 11:32:13,529 INFO L307 CDTParser]: Found 1 translation units. [2018-11-18 11:32:13,530 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_7f1434c4-8cda-4b7d-9907-b179c1c37dd0/sv-benchmarks/c/systemc/token_ring.03_false-unreach-call_false-termination.cil.c [2018-11-18 11:32:13,537 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_7f1434c4-8cda-4b7d-9907-b179c1c37dd0/bin-2019/uautomizer/data/221e49d43/edbedd7bc3e946efae39ebe0ebb422f7/FLAGfc6ada384 [2018-11-18 11:32:13,546 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_7f1434c4-8cda-4b7d-9907-b179c1c37dd0/bin-2019/uautomizer/data/221e49d43/edbedd7bc3e946efae39ebe0ebb422f7 [2018-11-18 11:32:13,549 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-18 11:32:13,549 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-18 11:32:13,550 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-18 11:32:13,550 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-18 11:32:13,552 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-18 11:32:13,552 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 11:32:13" (1/1) ... [2018-11-18 11:32:13,554 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@252e0cb5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 11:32:13, skipping insertion in model container [2018-11-18 11:32:13,554 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 11:32:13" (1/1) ... [2018-11-18 11:32:13,560 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-18 11:32:13,584 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-18 11:32:13,714 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 11:32:13,717 INFO L191 MainTranslator]: Completed pre-run [2018-11-18 11:32:13,742 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 11:32:13,752 INFO L195 MainTranslator]: Completed translation [2018-11-18 11:32:13,753 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 11:32:13 WrapperNode [2018-11-18 11:32:13,753 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-18 11:32:13,753 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-18 11:32:13,753 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-18 11:32:13,753 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-18 11:32:13,758 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 11:32:13" (1/1) ... [2018-11-18 11:32:13,762 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 11:32:13" (1/1) ... [2018-11-18 11:32:13,825 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-18 11:32:13,825 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-18 11:32:13,825 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-18 11:32:13,825 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-18 11:32:13,833 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 11:32:13" (1/1) ... [2018-11-18 11:32:13,834 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 11:32:13" (1/1) ... [2018-11-18 11:32:13,837 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 11:32:13" (1/1) ... [2018-11-18 11:32:13,837 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 11:32:13" (1/1) ... [2018-11-18 11:32:13,845 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 11:32:13" (1/1) ... [2018-11-18 11:32:13,856 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 11:32:13" (1/1) ... [2018-11-18 11:32:13,858 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 11:32:13" (1/1) ... [2018-11-18 11:32:13,862 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-18 11:32:13,863 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-18 11:32:13,863 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-18 11:32:13,863 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-18 11:32:13,864 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 11:32:13" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_7f1434c4-8cda-4b7d-9907-b179c1c37dd0/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 11:32:13,900 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-18 11:32:13,900 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-18 11:32:14,569 INFO L278 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-18 11:32:14,569 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 11:32:14 BoogieIcfgContainer [2018-11-18 11:32:14,569 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-18 11:32:14,570 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2018-11-18 11:32:14,570 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2018-11-18 11:32:14,572 INFO L276 PluginConnector]: BuchiAutomizer initialized [2018-11-18 11:32:14,573 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 11:32:14,573 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 18.11 11:32:13" (1/3) ... [2018-11-18 11:32:14,573 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7273be04 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 11:32:14, skipping insertion in model container [2018-11-18 11:32:14,573 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 11:32:14,574 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 11:32:13" (2/3) ... [2018-11-18 11:32:14,574 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7273be04 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 11:32:14, skipping insertion in model container [2018-11-18 11:32:14,574 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 11:32:14,574 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 11:32:14" (3/3) ... [2018-11-18 11:32:14,576 INFO L375 chiAutomizerObserver]: Analyzing ICFG token_ring.03_false-unreach-call_false-termination.cil.c [2018-11-18 11:32:14,607 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-18 11:32:14,608 INFO L374 BuchiCegarLoop]: Interprodecural is true [2018-11-18 11:32:14,608 INFO L375 BuchiCegarLoop]: Hoare is false [2018-11-18 11:32:14,608 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2018-11-18 11:32:14,608 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-18 11:32:14,608 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-18 11:32:14,608 INFO L379 BuchiCegarLoop]: Difference is false [2018-11-18 11:32:14,608 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-18 11:32:14,608 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2018-11-18 11:32:14,625 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 337 states. [2018-11-18 11:32:14,652 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 278 [2018-11-18 11:32:14,652 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:32:14,653 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:32:14,660 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:32:14,660 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:32:14,660 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ [2018-11-18 11:32:14,660 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 337 states. [2018-11-18 11:32:14,667 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 278 [2018-11-18 11:32:14,667 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:32:14,667 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:32:14,669 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:32:14,669 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:32:14,675 INFO L794 eck$LassoCheckResult]: Stem: 127#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 16#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 8#L643true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 266#L287true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 310#L294true assume !(1 == ~m_i~0);~m_st~0 := 2; 312#L294-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 176#L299-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 223#L304-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 244#L309-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 187#L431true assume !(0 == ~M_E~0); 165#L431-2true assume !(0 == ~T1_E~0); 200#L436-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 255#L441-1true assume !(0 == ~T3_E~0); 112#L446-1true assume !(0 == ~E_M~0); 135#L451-1true assume !(0 == ~E_1~0); 156#L456-1true assume !(0 == ~E_2~0); 39#L461-1true assume !(0 == ~E_3~0); 76#L466-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 238#L210true assume 1 == ~m_pc~0; 326#L211true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 239#L221true is_master_triggered_#res := is_master_triggered_~__retres1~0; 327#L222true activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 15#L533true assume !(0 != activate_threads_~tmp~1); 152#L533-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 84#L229true assume !(1 == ~t1_pc~0); 99#L229-2true is_transmit1_triggered_~__retres1~1 := 0; 85#L240true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11#L241true activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 179#L541true assume !(0 != activate_threads_~tmp___0~0); 183#L541-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 118#L248true assume 1 == ~t2_pc~0; 222#L249true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 120#L259true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 224#L260true activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 57#L549true assume !(0 != activate_threads_~tmp___1~0); 33#L549-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 304#L267true assume !(1 == ~t3_pc~0); 285#L267-2true is_transmit3_triggered_~__retres1~3 := 0; 305#L278true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 74#L279true activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 231#L557true assume !(0 != activate_threads_~tmp___2~0); 240#L557-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 124#L479true assume !(1 == ~M_E~0); 114#L479-2true assume !(1 == ~T1_E~0); 133#L484-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 154#L489-1true assume !(1 == ~T3_E~0); 34#L494-1true assume !(1 == ~E_M~0); 72#L499-1true assume !(1 == ~E_1~0); 280#L504-1true assume !(1 == ~E_2~0); 306#L509-1true assume !(1 == ~E_3~0); 321#L514-1true assume { :end_inline_reset_delta_events } true; 295#L680-3true [2018-11-18 11:32:14,676 INFO L796 eck$LassoCheckResult]: Loop: 295#L680-3true assume true; 289#L680-1true assume !false; 55#L681true start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 43#L406true assume !true; 307#L421true assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 241#L287-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 167#L431-3true assume 0 == ~M_E~0;~M_E~0 := 1; 173#L431-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 213#L436-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 259#L441-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 119#L446-3true assume 0 == ~E_M~0;~E_M~0 := 1; 140#L451-3true assume 0 == ~E_1~0;~E_1~0 := 1; 160#L456-3true assume !(0 == ~E_2~0); 50#L461-3true assume 0 == ~E_3~0;~E_3~0 := 1; 81#L466-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 218#L210-15true assume !(1 == ~m_pc~0); 208#L210-17true is_master_triggered_~__retres1~0 := 0; 250#L221-5true is_master_triggered_#res := is_master_triggered_~__retres1~0; 338#L222-5true activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 146#L533-15true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 132#L533-17true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 70#L229-15true assume !(1 == ~t1_pc~0); 52#L229-17true is_transmit1_triggered_~__retres1~1 := 0; 92#L240-5true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 24#L241-5true activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 315#L541-15true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 320#L541-17true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 242#L248-15true assume !(1 == ~t2_pc~0); 236#L248-17true is_transmit2_triggered_~__retres1~2 := 0; 264#L259-5true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 197#L260-5true activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 14#L549-15true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 151#L549-17true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 86#L267-15true assume !(1 == ~t3_pc~0); 83#L267-17true is_transmit3_triggered_~__retres1~3 := 0; 279#L278-5true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 42#L279-5true activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 177#L557-15true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 181#L557-17true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 116#L479-3true assume 1 == ~M_E~0;~M_E~0 := 2; 121#L479-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 138#L484-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 158#L489-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 46#L494-3true assume 1 == ~E_M~0;~E_M~0 := 2; 77#L499-3true assume 1 == ~E_1~0;~E_1~0 := 2; 284#L504-3true assume !(1 == ~E_2~0); 308#L509-3true assume 1 == ~E_3~0;~E_3~0 := 2; 328#L514-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 300#L322-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 299#L344-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 61#L345-1true start_simulation_#t~ret12 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 131#L699true assume !(0 == start_simulation_~tmp~3); 122#L699-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 302#L322-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 301#L344-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 64#L345-2true stop_simulation_#t~ret11 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 7#L654true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 105#L661true stop_simulation_#res := stop_simulation_~__retres2~0; 194#L662true start_simulation_#t~ret13 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 330#L712true assume !(0 != start_simulation_~tmp___0~1); 295#L680-3true [2018-11-18 11:32:14,681 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:32:14,681 INFO L82 PathProgramCache]: Analyzing trace with hash 1917692997, now seen corresponding path program 1 times [2018-11-18 11:32:14,682 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:32:14,683 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:32:14,712 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:14,712 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:32:14,712 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:14,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:32:14,778 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:32:14,780 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:32:14,780 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 11:32:14,784 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 11:32:14,784 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:32:14,785 INFO L82 PathProgramCache]: Analyzing trace with hash -1429506716, now seen corresponding path program 1 times [2018-11-18 11:32:14,785 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:32:14,785 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:32:14,785 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:14,786 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:32:14,786 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:14,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:32:14,798 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:32:14,798 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:32:14,798 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 11:32:14,799 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 11:32:14,813 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 11:32:14,814 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 11:32:14,816 INFO L87 Difference]: Start difference. First operand 337 states. Second operand 3 states. [2018-11-18 11:32:14,847 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:32:14,848 INFO L93 Difference]: Finished difference Result 335 states and 497 transitions. [2018-11-18 11:32:14,848 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 11:32:14,850 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 335 states and 497 transitions. [2018-11-18 11:32:14,853 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 274 [2018-11-18 11:32:14,859 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 335 states to 329 states and 491 transitions. [2018-11-18 11:32:14,860 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 329 [2018-11-18 11:32:14,860 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 329 [2018-11-18 11:32:14,861 INFO L73 IsDeterministic]: Start isDeterministic. Operand 329 states and 491 transitions. [2018-11-18 11:32:14,862 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:32:14,863 INFO L705 BuchiCegarLoop]: Abstraction has 329 states and 491 transitions. [2018-11-18 11:32:14,877 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 329 states and 491 transitions. [2018-11-18 11:32:14,895 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 329 to 329. [2018-11-18 11:32:14,895 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 329 states. [2018-11-18 11:32:14,896 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 329 states to 329 states and 491 transitions. [2018-11-18 11:32:14,897 INFO L728 BuchiCegarLoop]: Abstraction has 329 states and 491 transitions. [2018-11-18 11:32:14,897 INFO L608 BuchiCegarLoop]: Abstraction has 329 states and 491 transitions. [2018-11-18 11:32:14,897 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ [2018-11-18 11:32:14,897 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 329 states and 491 transitions. [2018-11-18 11:32:14,899 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 274 [2018-11-18 11:32:14,900 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:32:14,900 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:32:14,901 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:32:14,901 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:32:14,901 INFO L794 eck$LassoCheckResult]: Stem: 873#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 708#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 694#L643 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 695#L287 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 993#L294 assume 1 == ~m_i~0;~m_st~0 := 0; 1005#L294-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 921#L299-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 922#L304-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 965#L309-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 931#L431 assume !(0 == ~M_E~0); 903#L431-2 assume !(0 == ~T1_E~0); 904#L436-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 948#L441-1 assume !(0 == ~T3_E~0); 849#L446-1 assume !(0 == ~E_M~0); 850#L451-1 assume !(0 == ~E_1~0); 880#L456-1 assume !(0 == ~E_2~0); 758#L461-1 assume !(0 == ~E_3~0); 759#L466-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 818#L210 assume 1 == ~m_pc~0; 982#L211 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 973#L221 is_master_triggered_#res := is_master_triggered_~__retres1~0; 983#L222 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 706#L533 assume !(0 != activate_threads_~tmp~1); 707#L533-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 826#L229 assume !(1 == ~t1_pc~0); 697#L229-2 is_transmit1_triggered_~__retres1~1 := 0; 698#L240 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 699#L241 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 700#L541 assume !(0 != activate_threads_~tmp___0~0); 928#L541-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 861#L248 assume 1 == ~t2_pc~0; 862#L249 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 852#L259 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 865#L260 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 788#L549 assume !(0 != activate_threads_~tmp___1~0); 744#L549-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 745#L267 assume !(1 == ~t3_pc~0); 815#L267-2 is_transmit3_triggered_~__retres1~3 := 0; 814#L278 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 816#L279 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 817#L557 assume !(0 != activate_threads_~tmp___2~0); 977#L557-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 871#L479 assume !(1 == ~M_E~0); 853#L479-2 assume !(1 == ~T1_E~0); 854#L484-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 879#L489-1 assume !(1 == ~T3_E~0); 749#L494-1 assume !(1 == ~E_M~0); 750#L499-1 assume !(1 == ~E_1~0); 812#L504-1 assume !(1 == ~E_2~0); 997#L509-1 assume !(1 == ~E_3~0); 1003#L514-1 assume { :end_inline_reset_delta_events } true; 1000#L680-3 [2018-11-18 11:32:14,902 INFO L796 eck$LassoCheckResult]: Loop: 1000#L680-3 assume true; 999#L680-1 assume !false; 786#L681 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 764#L406 assume true; 765#L354-1 assume !false; 908#L355 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1001#L322 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 792#L344 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 789#L345 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 790#L359 assume !(0 != eval_~tmp~0); 958#L421 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 984#L287-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 906#L431-3 assume 0 == ~M_E~0;~M_E~0 := 1; 907#L431-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 916#L436-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 961#L441-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 863#L446-3 assume 0 == ~E_M~0;~E_M~0 := 1; 864#L451-3 assume 0 == ~E_1~0;~E_1~0 := 1; 885#L456-3 assume !(0 == ~E_2~0); 781#L461-3 assume 0 == ~E_3~0;~E_3~0 := 1; 782#L466-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 825#L210-15 assume 1 == ~m_pc~0; 963#L211-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 955#L221-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 989#L222-5 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 890#L533-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 876#L533-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 809#L229-15 assume !(1 == ~t1_pc~0); 721#L229-17 is_transmit1_triggered_~__retres1~1 := 0; 720#L240-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 722#L241-5 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 723#L541-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1007#L541-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 985#L248-15 assume 1 == ~t2_pc~0; 917#L249-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 919#L259-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 942#L260-5 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 704#L549-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 705#L549-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 827#L267-15 assume 1 == ~t3_pc~0; 755#L268-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 756#L278-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 760#L279-5 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 761#L557-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 925#L557-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 857#L479-3 assume 1 == ~M_E~0;~M_E~0 := 2; 858#L479-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 866#L484-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 883#L489-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 769#L494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 770#L499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 819#L504-3 assume !(1 == ~E_2~0); 998#L509-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1004#L514-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1002#L322-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 796#L344-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 793#L345-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 794#L699 assume !(0 == start_simulation_~tmp~3); 867#L699-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 868#L322-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 800#L344-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 797#L345-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 687#L654 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 688#L661 stop_simulation_#res := stop_simulation_~__retres2~0; 839#L662 start_simulation_#t~ret13 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 940#L712 assume !(0 != start_simulation_~tmp___0~1); 1000#L680-3 [2018-11-18 11:32:14,902 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:32:14,902 INFO L82 PathProgramCache]: Analyzing trace with hash -2024185917, now seen corresponding path program 1 times [2018-11-18 11:32:14,902 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:32:14,903 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:32:14,903 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:14,904 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:32:14,904 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:14,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:32:14,947 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:32:14,947 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:32:14,947 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 11:32:14,948 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 11:32:14,948 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:32:14,948 INFO L82 PathProgramCache]: Analyzing trace with hash 189917321, now seen corresponding path program 1 times [2018-11-18 11:32:14,948 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:32:14,948 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:32:14,949 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:14,949 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:32:14,949 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:14,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:32:15,001 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:32:15,002 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:32:15,002 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 11:32:15,002 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 11:32:15,002 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 11:32:15,002 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 11:32:15,003 INFO L87 Difference]: Start difference. First operand 329 states and 491 transitions. cyclomatic complexity: 163 Second operand 3 states. [2018-11-18 11:32:15,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:32:15,016 INFO L93 Difference]: Finished difference Result 329 states and 490 transitions. [2018-11-18 11:32:15,017 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 11:32:15,017 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 329 states and 490 transitions. [2018-11-18 11:32:15,020 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 274 [2018-11-18 11:32:15,022 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 329 states to 329 states and 490 transitions. [2018-11-18 11:32:15,023 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 329 [2018-11-18 11:32:15,023 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 329 [2018-11-18 11:32:15,024 INFO L73 IsDeterministic]: Start isDeterministic. Operand 329 states and 490 transitions. [2018-11-18 11:32:15,025 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:32:15,026 INFO L705 BuchiCegarLoop]: Abstraction has 329 states and 490 transitions. [2018-11-18 11:32:15,026 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 329 states and 490 transitions. [2018-11-18 11:32:15,035 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 329 to 329. [2018-11-18 11:32:15,035 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 329 states. [2018-11-18 11:32:15,037 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 329 states to 329 states and 490 transitions. [2018-11-18 11:32:15,037 INFO L728 BuchiCegarLoop]: Abstraction has 329 states and 490 transitions. [2018-11-18 11:32:15,037 INFO L608 BuchiCegarLoop]: Abstraction has 329 states and 490 transitions. [2018-11-18 11:32:15,037 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ [2018-11-18 11:32:15,037 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 329 states and 490 transitions. [2018-11-18 11:32:15,039 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 274 [2018-11-18 11:32:15,039 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:32:15,039 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:32:15,041 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:32:15,041 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:32:15,041 INFO L794 eck$LassoCheckResult]: Stem: 1538#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 1373#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1359#L643 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 1360#L287 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1658#L294 assume 1 == ~m_i~0;~m_st~0 := 0; 1670#L294-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1586#L299-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1587#L304-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1630#L309-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1596#L431 assume !(0 == ~M_E~0); 1568#L431-2 assume !(0 == ~T1_E~0); 1569#L436-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1612#L441-1 assume !(0 == ~T3_E~0); 1514#L446-1 assume !(0 == ~E_M~0); 1515#L451-1 assume !(0 == ~E_1~0); 1545#L456-1 assume !(0 == ~E_2~0); 1420#L461-1 assume !(0 == ~E_3~0); 1421#L466-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1483#L210 assume 1 == ~m_pc~0; 1647#L211 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1638#L221 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1648#L222 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1371#L533 assume !(0 != activate_threads_~tmp~1); 1372#L533-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1491#L229 assume !(1 == ~t1_pc~0); 1362#L229-2 is_transmit1_triggered_~__retres1~1 := 0; 1363#L240 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1364#L241 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1365#L541 assume !(0 != activate_threads_~tmp___0~0); 1591#L541-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1526#L248 assume 1 == ~t2_pc~0; 1527#L249 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1517#L259 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1530#L260 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1453#L549 assume !(0 != activate_threads_~tmp___1~0); 1409#L549-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1410#L267 assume !(1 == ~t3_pc~0); 1480#L267-2 is_transmit3_triggered_~__retres1~3 := 0; 1479#L278 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1481#L279 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1482#L557 assume !(0 != activate_threads_~tmp___2~0); 1641#L557-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1536#L479 assume !(1 == ~M_E~0); 1518#L479-2 assume !(1 == ~T1_E~0); 1519#L484-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1542#L489-1 assume !(1 == ~T3_E~0); 1411#L494-1 assume !(1 == ~E_M~0); 1412#L499-1 assume !(1 == ~E_1~0); 1477#L504-1 assume !(1 == ~E_2~0); 1662#L509-1 assume !(1 == ~E_3~0); 1668#L514-1 assume { :end_inline_reset_delta_events } true; 1665#L680-3 [2018-11-18 11:32:15,041 INFO L796 eck$LassoCheckResult]: Loop: 1665#L680-3 assume true; 1664#L680-1 assume !false; 1451#L681 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 1429#L406 assume true; 1430#L354-1 assume !false; 1573#L355 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1666#L322 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1457#L344 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1454#L345 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 1455#L359 assume !(0 != eval_~tmp~0); 1622#L421 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 1649#L287-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 1571#L431-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1572#L431-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1581#L436-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1626#L441-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1528#L446-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1529#L451-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1550#L456-3 assume !(0 == ~E_2~0); 1443#L461-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1444#L466-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1490#L210-15 assume !(1 == ~m_pc~0); 1619#L210-17 is_master_triggered_~__retres1~0 := 0; 1620#L221-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1654#L222-5 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1555#L533-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1541#L533-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1474#L229-15 assume 1 == ~t1_pc~0; 1384#L230-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1385#L240-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1389#L241-5 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1390#L541-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1672#L541-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1650#L248-15 assume !(1 == ~t2_pc~0); 1584#L248-17 is_transmit2_triggered_~__retres1~2 := 0; 1585#L259-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1607#L260-5 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1369#L549-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1370#L549-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1492#L267-15 assume !(1 == ~t3_pc~0); 1424#L267-17 is_transmit3_triggered_~__retres1~3 := 0; 1423#L278-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1427#L279-5 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1428#L557-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1590#L557-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1522#L479-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1523#L479-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1531#L484-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1549#L489-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1437#L494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1438#L499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1484#L504-3 assume !(1 == ~E_2~0); 1663#L509-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1669#L514-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1667#L322-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1461#L344-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1458#L345-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 1459#L699 assume !(0 == start_simulation_~tmp~3); 1532#L699-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1533#L322-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1465#L344-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1463#L345-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 1355#L654 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1356#L661 stop_simulation_#res := stop_simulation_~__retres2~0; 1504#L662 start_simulation_#t~ret13 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 1605#L712 assume !(0 != start_simulation_~tmp___0~1); 1665#L680-3 [2018-11-18 11:32:15,042 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:32:15,042 INFO L82 PathProgramCache]: Analyzing trace with hash 1377295041, now seen corresponding path program 1 times [2018-11-18 11:32:15,042 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:32:15,042 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:32:15,043 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:15,043 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:32:15,043 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:15,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:32:15,079 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:32:15,079 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:32:15,079 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 11:32:15,080 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 11:32:15,080 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:32:15,080 INFO L82 PathProgramCache]: Analyzing trace with hash 1319259915, now seen corresponding path program 1 times [2018-11-18 11:32:15,080 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:32:15,080 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:32:15,081 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:15,081 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:32:15,081 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:15,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:32:15,140 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:32:15,141 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:32:15,141 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 11:32:15,141 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 11:32:15,141 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 11:32:15,141 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 11:32:15,142 INFO L87 Difference]: Start difference. First operand 329 states and 490 transitions. cyclomatic complexity: 162 Second operand 3 states. [2018-11-18 11:32:15,150 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:32:15,150 INFO L93 Difference]: Finished difference Result 329 states and 489 transitions. [2018-11-18 11:32:15,151 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 11:32:15,151 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 329 states and 489 transitions. [2018-11-18 11:32:15,153 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 274 [2018-11-18 11:32:15,154 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 329 states to 329 states and 489 transitions. [2018-11-18 11:32:15,154 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 329 [2018-11-18 11:32:15,155 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 329 [2018-11-18 11:32:15,155 INFO L73 IsDeterministic]: Start isDeterministic. Operand 329 states and 489 transitions. [2018-11-18 11:32:15,155 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:32:15,155 INFO L705 BuchiCegarLoop]: Abstraction has 329 states and 489 transitions. [2018-11-18 11:32:15,156 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 329 states and 489 transitions. [2018-11-18 11:32:15,161 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 329 to 329. [2018-11-18 11:32:15,162 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 329 states. [2018-11-18 11:32:15,163 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 329 states to 329 states and 489 transitions. [2018-11-18 11:32:15,163 INFO L728 BuchiCegarLoop]: Abstraction has 329 states and 489 transitions. [2018-11-18 11:32:15,163 INFO L608 BuchiCegarLoop]: Abstraction has 329 states and 489 transitions. [2018-11-18 11:32:15,163 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ [2018-11-18 11:32:15,163 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 329 states and 489 transitions. [2018-11-18 11:32:15,165 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 274 [2018-11-18 11:32:15,165 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:32:15,165 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:32:15,166 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:32:15,166 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:32:15,167 INFO L794 eck$LassoCheckResult]: Stem: 2205#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 2040#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2024#L643 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 2025#L287 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2325#L294 assume 1 == ~m_i~0;~m_st~0 := 0; 2337#L294-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2253#L299-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2254#L304-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2297#L309-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2263#L431 assume !(0 == ~M_E~0); 2235#L431-2 assume !(0 == ~T1_E~0); 2236#L436-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2279#L441-1 assume !(0 == ~T3_E~0); 2181#L446-1 assume !(0 == ~E_M~0); 2182#L451-1 assume !(0 == ~E_1~0); 2212#L456-1 assume !(0 == ~E_2~0); 2087#L461-1 assume !(0 == ~E_3~0); 2088#L466-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2150#L210 assume 1 == ~m_pc~0; 2314#L211 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2305#L221 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2315#L222 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2038#L533 assume !(0 != activate_threads_~tmp~1); 2039#L533-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2158#L229 assume !(1 == ~t1_pc~0); 2029#L229-2 is_transmit1_triggered_~__retres1~1 := 0; 2030#L240 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2031#L241 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2032#L541 assume !(0 != activate_threads_~tmp___0~0); 2258#L541-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2193#L248 assume 1 == ~t2_pc~0; 2194#L249 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2184#L259 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2197#L260 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2120#L549 assume !(0 != activate_threads_~tmp___1~0); 2076#L549-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2077#L267 assume !(1 == ~t3_pc~0); 2147#L267-2 is_transmit3_triggered_~__retres1~3 := 0; 2146#L278 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2148#L279 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2149#L557 assume !(0 != activate_threads_~tmp___2~0); 2308#L557-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2203#L479 assume !(1 == ~M_E~0); 2185#L479-2 assume !(1 == ~T1_E~0); 2186#L484-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2209#L489-1 assume !(1 == ~T3_E~0); 2078#L494-1 assume !(1 == ~E_M~0); 2079#L499-1 assume !(1 == ~E_1~0); 2144#L504-1 assume !(1 == ~E_2~0); 2329#L509-1 assume !(1 == ~E_3~0); 2335#L514-1 assume { :end_inline_reset_delta_events } true; 2332#L680-3 [2018-11-18 11:32:15,167 INFO L796 eck$LassoCheckResult]: Loop: 2332#L680-3 assume true; 2331#L680-1 assume !false; 2118#L681 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 2096#L406 assume true; 2097#L354-1 assume !false; 2240#L355 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2333#L322 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 2124#L344 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2121#L345 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 2122#L359 assume !(0 != eval_~tmp~0); 2289#L421 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 2316#L287-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 2238#L431-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2239#L431-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2248#L436-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2293#L441-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2195#L446-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2196#L451-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2217#L456-3 assume !(0 == ~E_2~0); 2110#L461-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2111#L466-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2157#L210-15 assume 1 == ~m_pc~0; 2295#L211-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2287#L221-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2321#L222-5 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2222#L533-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2208#L533-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2141#L229-15 assume 1 == ~t1_pc~0; 2051#L230-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2052#L240-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2056#L241-5 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2057#L541-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2339#L541-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2317#L248-15 assume 1 == ~t2_pc~0; 2250#L249-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2252#L259-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2274#L260-5 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2036#L549-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2037#L549-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2159#L267-15 assume 1 == ~t3_pc~0; 2089#L268-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2090#L278-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2094#L279-5 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2095#L557-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2257#L557-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2189#L479-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2190#L479-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2198#L484-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2216#L489-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2104#L494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2105#L499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2151#L504-3 assume !(1 == ~E_2~0); 2330#L509-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2336#L514-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2334#L322-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 2128#L344-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2125#L345-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 2126#L699 assume !(0 == start_simulation_~tmp~3); 2199#L699-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2200#L322-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 2132#L344-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2130#L345-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 2022#L654 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2023#L661 stop_simulation_#res := stop_simulation_~__retres2~0; 2171#L662 start_simulation_#t~ret13 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 2272#L712 assume !(0 != start_simulation_~tmp___0~1); 2332#L680-3 [2018-11-18 11:32:15,167 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:32:15,167 INFO L82 PathProgramCache]: Analyzing trace with hash -868284413, now seen corresponding path program 1 times [2018-11-18 11:32:15,168 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:32:15,168 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:32:15,168 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:15,169 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:32:15,169 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:15,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:32:15,186 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:32:15,187 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:32:15,187 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 11:32:15,187 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 11:32:15,187 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:32:15,187 INFO L82 PathProgramCache]: Analyzing trace with hash 1146845704, now seen corresponding path program 1 times [2018-11-18 11:32:15,187 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:32:15,188 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:32:15,188 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:15,188 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:32:15,188 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:15,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:32:15,226 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:32:15,227 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:32:15,227 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 11:32:15,227 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 11:32:15,227 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 11:32:15,227 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 11:32:15,228 INFO L87 Difference]: Start difference. First operand 329 states and 489 transitions. cyclomatic complexity: 161 Second operand 3 states. [2018-11-18 11:32:15,244 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:32:15,244 INFO L93 Difference]: Finished difference Result 329 states and 484 transitions. [2018-11-18 11:32:15,245 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 11:32:15,245 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 329 states and 484 transitions. [2018-11-18 11:32:15,248 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 274 [2018-11-18 11:32:15,249 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 329 states to 329 states and 484 transitions. [2018-11-18 11:32:15,250 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 329 [2018-11-18 11:32:15,250 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 329 [2018-11-18 11:32:15,250 INFO L73 IsDeterministic]: Start isDeterministic. Operand 329 states and 484 transitions. [2018-11-18 11:32:15,251 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:32:15,251 INFO L705 BuchiCegarLoop]: Abstraction has 329 states and 484 transitions. [2018-11-18 11:32:15,253 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 329 states and 484 transitions. [2018-11-18 11:32:15,257 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 329 to 329. [2018-11-18 11:32:15,258 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 329 states. [2018-11-18 11:32:15,259 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 329 states to 329 states and 484 transitions. [2018-11-18 11:32:15,259 INFO L728 BuchiCegarLoop]: Abstraction has 329 states and 484 transitions. [2018-11-18 11:32:15,259 INFO L608 BuchiCegarLoop]: Abstraction has 329 states and 484 transitions. [2018-11-18 11:32:15,259 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ [2018-11-18 11:32:15,259 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 329 states and 484 transitions. [2018-11-18 11:32:15,261 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 274 [2018-11-18 11:32:15,261 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:32:15,261 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:32:15,262 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:32:15,262 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:32:15,263 INFO L794 eck$LassoCheckResult]: Stem: 2870#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 2705#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2689#L643 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 2690#L287 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2990#L294 assume 1 == ~m_i~0;~m_st~0 := 0; 3002#L294-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2918#L299-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2919#L304-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2962#L309-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2928#L431 assume !(0 == ~M_E~0); 2900#L431-2 assume !(0 == ~T1_E~0); 2901#L436-1 assume !(0 == ~T2_E~0); 2945#L441-1 assume !(0 == ~T3_E~0); 2846#L446-1 assume !(0 == ~E_M~0); 2847#L451-1 assume !(0 == ~E_1~0); 2877#L456-1 assume !(0 == ~E_2~0); 2755#L461-1 assume !(0 == ~E_3~0); 2756#L466-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2815#L210 assume 1 == ~m_pc~0; 2979#L211 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2970#L221 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2980#L222 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2703#L533 assume !(0 != activate_threads_~tmp~1); 2704#L533-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2823#L229 assume !(1 == ~t1_pc~0); 2694#L229-2 is_transmit1_triggered_~__retres1~1 := 0; 2695#L240 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2696#L241 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2697#L541 assume !(0 != activate_threads_~tmp___0~0); 2925#L541-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2858#L248 assume 1 == ~t2_pc~0; 2859#L249 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2849#L259 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2862#L260 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2785#L549 assume !(0 != activate_threads_~tmp___1~0); 2741#L549-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2742#L267 assume !(1 == ~t3_pc~0); 2812#L267-2 is_transmit3_triggered_~__retres1~3 := 0; 2811#L278 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2813#L279 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2814#L557 assume !(0 != activate_threads_~tmp___2~0); 2974#L557-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2868#L479 assume !(1 == ~M_E~0); 2850#L479-2 assume !(1 == ~T1_E~0); 2851#L484-1 assume !(1 == ~T2_E~0); 2876#L489-1 assume !(1 == ~T3_E~0); 2746#L494-1 assume !(1 == ~E_M~0); 2747#L499-1 assume !(1 == ~E_1~0); 2809#L504-1 assume !(1 == ~E_2~0); 2994#L509-1 assume !(1 == ~E_3~0); 3000#L514-1 assume { :end_inline_reset_delta_events } true; 2997#L680-3 [2018-11-18 11:32:15,263 INFO L796 eck$LassoCheckResult]: Loop: 2997#L680-3 assume true; 2996#L680-1 assume !false; 2783#L681 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 2761#L406 assume true; 2762#L354-1 assume !false; 2905#L355 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2998#L322 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 2789#L344 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2786#L345 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 2787#L359 assume !(0 != eval_~tmp~0); 2955#L421 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 2981#L287-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 2903#L431-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2904#L431-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2913#L436-3 assume !(0 == ~T2_E~0); 2958#L441-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2860#L446-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2861#L451-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2882#L456-3 assume !(0 == ~E_2~0); 2778#L461-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2779#L466-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2822#L210-15 assume 1 == ~m_pc~0; 2960#L211-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2952#L221-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2986#L222-5 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2887#L533-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2873#L533-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2808#L229-15 assume 1 == ~t1_pc~0; 2716#L230-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2717#L240-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2721#L241-5 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2722#L541-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3004#L541-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2982#L248-15 assume 1 == ~t2_pc~0; 2914#L249-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2916#L259-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2939#L260-5 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2701#L549-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2702#L549-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2824#L267-15 assume 1 == ~t3_pc~0; 2752#L268-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2753#L278-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2757#L279-5 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2758#L557-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2922#L557-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2854#L479-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2855#L479-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2863#L484-3 assume !(1 == ~T2_E~0); 2880#L489-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2766#L494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2767#L499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2816#L504-3 assume !(1 == ~E_2~0); 2995#L509-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3001#L514-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2999#L322-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 2793#L344-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2790#L345-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 2791#L699 assume !(0 == start_simulation_~tmp~3); 2864#L699-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2865#L322-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 2797#L344-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2794#L345-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 2684#L654 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2685#L661 stop_simulation_#res := stop_simulation_~__retres2~0; 2836#L662 start_simulation_#t~ret13 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 2937#L712 assume !(0 != start_simulation_~tmp___0~1); 2997#L680-3 [2018-11-18 11:32:15,263 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:32:15,263 INFO L82 PathProgramCache]: Analyzing trace with hash -465084349, now seen corresponding path program 1 times [2018-11-18 11:32:15,263 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:32:15,264 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:32:15,268 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:15,268 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:32:15,268 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:15,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:32:15,291 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:32:15,291 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:32:15,291 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 11:32:15,291 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 11:32:15,292 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:32:15,292 INFO L82 PathProgramCache]: Analyzing trace with hash 996241992, now seen corresponding path program 1 times [2018-11-18 11:32:15,292 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:32:15,292 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:32:15,293 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:15,293 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:32:15,293 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:15,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:32:15,320 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:32:15,320 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:32:15,320 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 11:32:15,321 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 11:32:15,321 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 11:32:15,321 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 11:32:15,321 INFO L87 Difference]: Start difference. First operand 329 states and 484 transitions. cyclomatic complexity: 156 Second operand 3 states. [2018-11-18 11:32:15,371 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:32:15,372 INFO L93 Difference]: Finished difference Result 589 states and 853 transitions. [2018-11-18 11:32:15,372 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 11:32:15,372 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 589 states and 853 transitions. [2018-11-18 11:32:15,375 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 533 [2018-11-18 11:32:15,378 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 589 states to 589 states and 853 transitions. [2018-11-18 11:32:15,378 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 589 [2018-11-18 11:32:15,379 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 589 [2018-11-18 11:32:15,379 INFO L73 IsDeterministic]: Start isDeterministic. Operand 589 states and 853 transitions. [2018-11-18 11:32:15,380 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:32:15,380 INFO L705 BuchiCegarLoop]: Abstraction has 589 states and 853 transitions. [2018-11-18 11:32:15,381 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 589 states and 853 transitions. [2018-11-18 11:32:15,388 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 589 to 562. [2018-11-18 11:32:15,388 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 562 states. [2018-11-18 11:32:15,390 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 562 states to 562 states and 816 transitions. [2018-11-18 11:32:15,390 INFO L728 BuchiCegarLoop]: Abstraction has 562 states and 816 transitions. [2018-11-18 11:32:15,390 INFO L608 BuchiCegarLoop]: Abstraction has 562 states and 816 transitions. [2018-11-18 11:32:15,390 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ [2018-11-18 11:32:15,391 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 562 states and 816 transitions. [2018-11-18 11:32:15,393 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 506 [2018-11-18 11:32:15,393 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:32:15,393 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:32:15,394 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:32:15,394 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:32:15,395 INFO L794 eck$LassoCheckResult]: Stem: 3796#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 3630#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 3616#L643 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 3617#L287 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3931#L294 assume 1 == ~m_i~0;~m_st~0 := 0; 3943#L294-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3846#L299-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3847#L304-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3896#L309-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3856#L431 assume !(0 == ~M_E~0); 3828#L431-2 assume !(0 == ~T1_E~0); 3829#L436-1 assume !(0 == ~T2_E~0); 3874#L441-1 assume !(0 == ~T3_E~0); 3772#L446-1 assume !(0 == ~E_M~0); 3773#L451-1 assume !(0 == ~E_1~0); 3805#L456-1 assume !(0 == ~E_2~0); 3680#L461-1 assume !(0 == ~E_3~0); 3681#L466-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3740#L210 assume !(1 == ~m_pc~0); 3902#L210-2 is_master_triggered_~__retres1~0 := 0; 3903#L221 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3913#L222 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 3628#L533 assume !(0 != activate_threads_~tmp~1); 3629#L533-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3748#L229 assume !(1 == ~t1_pc~0); 3619#L229-2 is_transmit1_triggered_~__retres1~1 := 0; 3620#L240 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3621#L241 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3622#L541 assume !(0 != activate_threads_~tmp___0~0); 3853#L541-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3786#L248 assume 1 == ~t2_pc~0; 3787#L249 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3775#L259 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3788#L260 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3710#L549 assume !(0 != activate_threads_~tmp___1~0); 3666#L549-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3667#L267 assume !(1 == ~t3_pc~0); 3737#L267-2 is_transmit3_triggered_~__retres1~3 := 0; 3736#L278 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3738#L279 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3739#L557 assume !(0 != activate_threads_~tmp___2~0); 3907#L557-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3794#L479 assume !(1 == ~M_E~0); 3776#L479-2 assume !(1 == ~T1_E~0); 3777#L484-1 assume !(1 == ~T2_E~0); 3802#L489-1 assume !(1 == ~T3_E~0); 3671#L494-1 assume !(1 == ~E_M~0); 3672#L499-1 assume !(1 == ~E_1~0); 3734#L504-1 assume !(1 == ~E_2~0); 3935#L509-1 assume !(1 == ~E_3~0); 3941#L514-1 assume { :end_inline_reset_delta_events } true; 3938#L680-3 [2018-11-18 11:32:15,395 INFO L796 eck$LassoCheckResult]: Loop: 3938#L680-3 assume true; 3937#L680-1 assume !false; 3708#L681 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 3686#L406 assume true; 3687#L354-1 assume !false; 3833#L355 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 3939#L322 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 3714#L344 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 3711#L345 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 3712#L359 assume !(0 != eval_~tmp~0); 3982#L421 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 4164#L287-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 4163#L431-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4162#L431-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4161#L436-3 assume !(0 == ~T2_E~0); 4160#L441-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4159#L446-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4158#L451-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4157#L456-3 assume !(0 == ~E_2~0); 3700#L461-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3701#L466-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3747#L210-15 assume !(1 == ~m_pc~0); 3881#L210-17 is_master_triggered_~__retres1~0 := 0; 3882#L221-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3919#L222-5 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 3814#L533-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3799#L533-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3731#L229-15 assume 1 == ~t1_pc~0; 3641#L230-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3642#L240-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3644#L241-5 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3645#L541-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3948#L541-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3915#L248-15 assume 1 == ~t2_pc~0; 3842#L249-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3844#L259-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3866#L260-5 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3626#L549-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3627#L549-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3749#L267-15 assume 1 == ~t3_pc~0; 3677#L268-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3678#L278-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3684#L279-5 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3685#L557-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3850#L557-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3780#L479-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3781#L479-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3789#L484-3 assume !(1 == ~T2_E~0); 3807#L489-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3694#L494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3695#L499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3741#L504-3 assume !(1 == ~E_2~0); 3936#L509-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3942#L514-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 3940#L322-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 3718#L344-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 3715#L345-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 3716#L699 assume !(0 == start_simulation_~tmp~3); 3790#L699-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 3791#L322-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 3722#L344-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 3720#L345-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 3612#L654 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3613#L661 stop_simulation_#res := stop_simulation_~__retres2~0; 3762#L662 start_simulation_#t~ret13 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 3864#L712 assume !(0 != start_simulation_~tmp___0~1); 3938#L680-3 [2018-11-18 11:32:15,395 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:32:15,395 INFO L82 PathProgramCache]: Analyzing trace with hash -2041642108, now seen corresponding path program 1 times [2018-11-18 11:32:15,395 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:32:15,395 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:32:15,396 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:15,396 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:32:15,396 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:15,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:32:15,438 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:32:15,439 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:32:15,439 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 11:32:15,439 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 11:32:15,439 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:32:15,439 INFO L82 PathProgramCache]: Analyzing trace with hash 122764297, now seen corresponding path program 1 times [2018-11-18 11:32:15,439 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:32:15,440 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:32:15,440 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:15,440 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:32:15,440 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:15,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:32:15,472 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:32:15,472 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:32:15,472 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 11:32:15,473 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 11:32:15,473 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 11:32:15,473 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 11:32:15,473 INFO L87 Difference]: Start difference. First operand 562 states and 816 transitions. cyclomatic complexity: 256 Second operand 3 states. [2018-11-18 11:32:15,521 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:32:15,521 INFO L93 Difference]: Finished difference Result 999 states and 1438 transitions. [2018-11-18 11:32:15,521 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 11:32:15,521 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 999 states and 1438 transitions. [2018-11-18 11:32:15,526 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 938 [2018-11-18 11:32:15,530 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 999 states to 999 states and 1438 transitions. [2018-11-18 11:32:15,530 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 999 [2018-11-18 11:32:15,531 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 999 [2018-11-18 11:32:15,531 INFO L73 IsDeterministic]: Start isDeterministic. Operand 999 states and 1438 transitions. [2018-11-18 11:32:15,533 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:32:15,533 INFO L705 BuchiCegarLoop]: Abstraction has 999 states and 1438 transitions. [2018-11-18 11:32:15,534 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 999 states and 1438 transitions. [2018-11-18 11:32:15,545 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 999 to 993. [2018-11-18 11:32:15,545 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 993 states. [2018-11-18 11:32:15,547 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 993 states to 993 states and 1432 transitions. [2018-11-18 11:32:15,547 INFO L728 BuchiCegarLoop]: Abstraction has 993 states and 1432 transitions. [2018-11-18 11:32:15,547 INFO L608 BuchiCegarLoop]: Abstraction has 993 states and 1432 transitions. [2018-11-18 11:32:15,547 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ [2018-11-18 11:32:15,547 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 993 states and 1432 transitions. [2018-11-18 11:32:15,551 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 932 [2018-11-18 11:32:15,551 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:32:15,551 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:32:15,552 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:32:15,552 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:32:15,552 INFO L794 eck$LassoCheckResult]: Stem: 5364#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 5198#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 5182#L643 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 5183#L287 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5496#L294 assume 1 == ~m_i~0;~m_st~0 := 0; 5515#L294-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5414#L299-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5415#L304-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5461#L309-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5424#L431 assume !(0 == ~M_E~0); 5395#L431-2 assume !(0 == ~T1_E~0); 5396#L436-1 assume !(0 == ~T2_E~0); 5439#L441-1 assume !(0 == ~T3_E~0); 5341#L446-1 assume !(0 == ~E_M~0); 5342#L451-1 assume !(0 == ~E_1~0); 5372#L456-1 assume !(0 == ~E_2~0); 5245#L461-1 assume !(0 == ~E_3~0); 5246#L466-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5308#L210 assume !(1 == ~m_pc~0); 5468#L210-2 is_master_triggered_~__retres1~0 := 0; 5469#L221 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5481#L222 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 5196#L533 assume !(0 != activate_threads_~tmp~1); 5197#L533-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5316#L229 assume !(1 == ~t1_pc~0); 5187#L229-2 is_transmit1_triggered_~__retres1~1 := 0; 5188#L240 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5189#L241 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 5190#L541 assume !(0 != activate_threads_~tmp___0~0); 5419#L541-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5353#L248 assume !(1 == ~t2_pc~0); 5343#L248-2 is_transmit2_triggered_~__retres1~2 := 0; 5344#L259 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5356#L260 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5278#L549 assume !(0 != activate_threads_~tmp___1~0); 5234#L549-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5235#L267 assume !(1 == ~t3_pc~0); 5305#L267-2 is_transmit3_triggered_~__retres1~3 := 0; 5304#L278 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5306#L279 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5307#L557 assume !(0 != activate_threads_~tmp___2~0); 5472#L557-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5362#L479 assume !(1 == ~M_E~0); 5345#L479-2 assume !(1 == ~T1_E~0); 5346#L484-1 assume !(1 == ~T2_E~0); 5369#L489-1 assume !(1 == ~T3_E~0); 5236#L494-1 assume !(1 == ~E_M~0); 5237#L499-1 assume !(1 == ~E_1~0); 5302#L504-1 assume !(1 == ~E_2~0); 5502#L509-1 assume !(1 == ~E_3~0); 5513#L514-1 assume { :end_inline_reset_delta_events } true; 5509#L680-3 [2018-11-18 11:32:15,552 INFO L796 eck$LassoCheckResult]: Loop: 5509#L680-3 assume true; 5508#L680-1 assume !false; 5276#L681 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 5254#L406 assume true; 5255#L354-1 assume !false; 5401#L355 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 5510#L322 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 5282#L344 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 5279#L345 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 5280#L359 assume !(0 != eval_~tmp~0); 5453#L421 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 5482#L287-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 5399#L431-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5400#L431-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5409#L436-3 assume !(0 == ~T2_E~0); 5458#L441-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5354#L446-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5355#L451-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5377#L456-3 assume !(0 == ~E_2~0); 5268#L461-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5269#L466-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5315#L210-15 assume !(1 == ~m_pc~0); 5450#L210-17 is_master_triggered_~__retres1~0 := 0; 5451#L221-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5487#L222-5 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 5382#L533-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5368#L533-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5299#L229-15 assume 1 == ~t1_pc~0; 5209#L230-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5210#L240-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5212#L241-5 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 5213#L541-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5518#L541-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5483#L248-15 assume !(1 == ~t2_pc~0); 5478#L248-17 is_transmit2_triggered_~__retres1~2 := 0; 5479#L259-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5433#L260-5 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5194#L549-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5195#L549-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5317#L267-15 assume !(1 == ~t3_pc~0); 5249#L267-17 is_transmit3_triggered_~__retres1~3 := 0; 5248#L278-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5252#L279-5 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5253#L557-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5418#L557-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5349#L479-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5350#L479-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5357#L484-3 assume !(1 == ~T2_E~0); 5376#L489-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5262#L494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5263#L499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5309#L504-3 assume !(1 == ~E_2~0); 5507#L509-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5514#L514-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 5511#L322-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 5286#L344-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 5283#L345-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 5284#L699 assume !(0 == start_simulation_~tmp~3); 5367#L699-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 5512#L322-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 5290#L344-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 5288#L345-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 5180#L654 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5181#L661 stop_simulation_#res := stop_simulation_~__retres2~0; 5330#L662 start_simulation_#t~ret13 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 5432#L712 assume !(0 != start_simulation_~tmp___0~1); 5509#L680-3 [2018-11-18 11:32:15,553 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:32:15,553 INFO L82 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 1 times [2018-11-18 11:32:15,553 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:32:15,553 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:32:15,554 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:15,554 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:32:15,554 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:15,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:32:15,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:32:15,582 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:32:15,582 INFO L82 PathProgramCache]: Analyzing trace with hash 1168656203, now seen corresponding path program 1 times [2018-11-18 11:32:15,583 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:32:15,583 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:32:15,583 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:15,584 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:32:15,584 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:15,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:32:15,636 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:32:15,637 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:32:15,637 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 11:32:15,637 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 11:32:15,637 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 11:32:15,637 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 11:32:15,638 INFO L87 Difference]: Start difference. First operand 993 states and 1432 transitions. cyclomatic complexity: 443 Second operand 5 states. [2018-11-18 11:32:15,769 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:32:15,769 INFO L93 Difference]: Finished difference Result 1741 states and 2464 transitions. [2018-11-18 11:32:15,770 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-18 11:32:15,770 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1741 states and 2464 transitions. [2018-11-18 11:32:15,775 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1672 [2018-11-18 11:32:15,780 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1741 states to 1741 states and 2464 transitions. [2018-11-18 11:32:15,780 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1741 [2018-11-18 11:32:15,781 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1741 [2018-11-18 11:32:15,781 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1741 states and 2464 transitions. [2018-11-18 11:32:15,783 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:32:15,783 INFO L705 BuchiCegarLoop]: Abstraction has 1741 states and 2464 transitions. [2018-11-18 11:32:15,784 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1741 states and 2464 transitions. [2018-11-18 11:32:15,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1741 to 1005. [2018-11-18 11:32:15,796 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1005 states. [2018-11-18 11:32:15,798 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1005 states to 1005 states and 1444 transitions. [2018-11-18 11:32:15,798 INFO L728 BuchiCegarLoop]: Abstraction has 1005 states and 1444 transitions. [2018-11-18 11:32:15,798 INFO L608 BuchiCegarLoop]: Abstraction has 1005 states and 1444 transitions. [2018-11-18 11:32:15,798 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ [2018-11-18 11:32:15,798 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1005 states and 1444 transitions. [2018-11-18 11:32:15,801 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 944 [2018-11-18 11:32:15,801 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:32:15,801 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:32:15,802 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:32:15,802 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:32:15,802 INFO L794 eck$LassoCheckResult]: Stem: 8120#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 7948#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 7932#L643 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 7933#L287 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8254#L294 assume 1 == ~m_i~0;~m_st~0 := 0; 8279#L294-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8176#L299-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8177#L304-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8223#L309-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8189#L431 assume !(0 == ~M_E~0); 8157#L431-2 assume !(0 == ~T1_E~0); 8158#L436-1 assume !(0 == ~T2_E~0); 8204#L441-1 assume !(0 == ~T3_E~0); 8096#L446-1 assume !(0 == ~E_M~0); 8097#L451-1 assume !(0 == ~E_1~0); 8128#L456-1 assume !(0 == ~E_2~0); 7995#L461-1 assume !(0 == ~E_3~0); 7996#L466-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8060#L210 assume !(1 == ~m_pc~0); 8229#L210-2 is_master_triggered_~__retres1~0 := 0; 8230#L221 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8240#L222 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 7946#L533 assume !(0 != activate_threads_~tmp~1); 7947#L533-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8069#L229 assume !(1 == ~t1_pc~0); 7937#L229-2 is_transmit1_triggered_~__retres1~1 := 0; 7938#L240 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7939#L241 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 7940#L541 assume !(0 != activate_threads_~tmp___0~0); 8182#L541-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8108#L248 assume !(1 == ~t2_pc~0); 8098#L248-2 is_transmit2_triggered_~__retres1~2 := 0; 8099#L259 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8111#L260 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 8029#L549 assume !(0 != activate_threads_~tmp___1~0); 7984#L549-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7985#L267 assume !(1 == ~t3_pc~0); 8057#L267-2 is_transmit3_triggered_~__retres1~3 := 0; 8056#L278 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8058#L279 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 8059#L557 assume !(0 != activate_threads_~tmp___2~0); 8233#L557-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8118#L479 assume !(1 == ~M_E~0); 8100#L479-2 assume !(1 == ~T1_E~0); 8101#L484-1 assume !(1 == ~T2_E~0); 8125#L489-1 assume !(1 == ~T3_E~0); 7986#L494-1 assume !(1 == ~E_M~0); 7987#L499-1 assume !(1 == ~E_1~0); 8054#L504-1 assume !(1 == ~E_2~0); 8263#L509-1 assume !(1 == ~E_3~0); 8276#L514-1 assume { :end_inline_reset_delta_events } true; 8291#L680-3 [2018-11-18 11:32:15,803 INFO L796 eck$LassoCheckResult]: Loop: 8291#L680-3 assume true; 8877#L680-1 assume !false; 8875#L681 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 8004#L406 assume true; 8005#L354-1 assume !false; 8162#L355 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 8271#L322 assume !(0 == ~m_st~0); 8217#L326 assume !(0 == ~t1_st~0); 8135#L330 assume !(0 == ~t2_st~0); 8032#L334 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4 := 0; 8034#L344 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 8272#L345 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 8722#L359 assume !(0 != eval_~tmp~0); 8277#L421 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 8241#L287-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 8160#L431-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8161#L431-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8171#L436-3 assume !(0 == ~T2_E~0); 8216#L441-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8109#L446-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8110#L451-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8134#L456-3 assume !(0 == ~E_2~0); 8018#L461-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8019#L466-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8068#L210-15 assume !(1 == ~m_pc~0); 8210#L210-17 is_master_triggered_~__retres1~0 := 0; 8211#L221-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8246#L222-5 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 8140#L533-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 8123#L533-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8124#L229-15 assume 1 == ~t1_pc~0; 8773#L230-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 8772#L240-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7962#L241-5 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 7963#L541-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 8284#L541-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8242#L248-15 assume !(1 == ~t2_pc~0); 8243#L248-17 is_transmit2_triggered_~__retres1~2 := 0; 8251#L259-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8252#L260-5 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 7944#L549-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7945#L549-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8070#L267-15 assume 1 == ~t3_pc~0; 8071#L268-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 8261#L278-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8262#L279-5 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 8180#L557-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 8181#L557-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8104#L479-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8105#L479-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8132#L484-3 assume !(1 == ~T2_E~0); 8133#L489-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8012#L494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8013#L499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8266#L504-3 assume !(1 == ~E_2~0); 8267#L509-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8278#L514-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 8273#L322-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 8038#L344-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 8035#L345-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 8036#L699 assume !(0 == start_simulation_~tmp~3); 8114#L699-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 8115#L322-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 8889#L344-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 8887#L345-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 8885#L654 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 8883#L661 stop_simulation_#res := stop_simulation_~__retres2~0; 8881#L662 start_simulation_#t~ret13 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 8879#L712 assume !(0 != start_simulation_~tmp___0~1); 8291#L680-3 [2018-11-18 11:32:15,803 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:32:15,803 INFO L82 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 2 times [2018-11-18 11:32:15,803 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:32:15,803 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:32:15,804 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:15,804 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:32:15,804 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:15,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:32:15,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:32:15,825 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:32:15,825 INFO L82 PathProgramCache]: Analyzing trace with hash 530541314, now seen corresponding path program 1 times [2018-11-18 11:32:15,825 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:32:15,825 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:32:15,826 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:15,826 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 11:32:15,826 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:15,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:32:15,900 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:32:15,900 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:32:15,901 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 11:32:15,901 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 11:32:15,901 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 11:32:15,901 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 11:32:15,901 INFO L87 Difference]: Start difference. First operand 1005 states and 1444 transitions. cyclomatic complexity: 443 Second operand 5 states. [2018-11-18 11:32:15,993 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:32:15,993 INFO L93 Difference]: Finished difference Result 1948 states and 2777 transitions. [2018-11-18 11:32:15,994 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 11:32:15,994 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1948 states and 2777 transitions. [2018-11-18 11:32:15,999 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1883 [2018-11-18 11:32:16,003 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1948 states to 1948 states and 2777 transitions. [2018-11-18 11:32:16,003 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1948 [2018-11-18 11:32:16,004 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1948 [2018-11-18 11:32:16,004 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1948 states and 2777 transitions. [2018-11-18 11:32:16,006 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:32:16,006 INFO L705 BuchiCegarLoop]: Abstraction has 1948 states and 2777 transitions. [2018-11-18 11:32:16,007 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1948 states and 2777 transitions. [2018-11-18 11:32:16,016 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1948 to 1038. [2018-11-18 11:32:16,016 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1038 states. [2018-11-18 11:32:16,017 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1038 states to 1038 states and 1467 transitions. [2018-11-18 11:32:16,018 INFO L728 BuchiCegarLoop]: Abstraction has 1038 states and 1467 transitions. [2018-11-18 11:32:16,018 INFO L608 BuchiCegarLoop]: Abstraction has 1038 states and 1467 transitions. [2018-11-18 11:32:16,018 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ [2018-11-18 11:32:16,018 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1038 states and 1467 transitions. [2018-11-18 11:32:16,021 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 977 [2018-11-18 11:32:16,021 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:32:16,021 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:32:16,022 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:32:16,022 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:32:16,022 INFO L794 eck$LassoCheckResult]: Stem: 11080#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 10914#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 10898#L643 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 10899#L287 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11213#L294 assume 1 == ~m_i~0;~m_st~0 := 0; 11229#L294-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11132#L299-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11133#L304-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11179#L309-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11143#L431 assume !(0 == ~M_E~0); 11114#L431-2 assume !(0 == ~T1_E~0); 11115#L436-1 assume !(0 == ~T2_E~0); 11158#L441-1 assume !(0 == ~T3_E~0); 11057#L446-1 assume !(0 == ~E_M~0); 11058#L451-1 assume !(0 == ~E_1~0); 11088#L456-1 assume !(0 == ~E_2~0); 10962#L461-1 assume !(0 == ~E_3~0); 10963#L466-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11026#L210 assume !(1 == ~m_pc~0); 11186#L210-2 is_master_triggered_~__retres1~0 := 0; 11187#L221 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11197#L222 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 10912#L533 assume !(0 != activate_threads_~tmp~1); 10913#L533-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11034#L229 assume !(1 == ~t1_pc~0); 10903#L229-2 is_transmit1_triggered_~__retres1~1 := 0; 10904#L240 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10905#L241 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 10906#L541 assume !(0 != activate_threads_~tmp___0~0); 11138#L541-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11069#L248 assume !(1 == ~t2_pc~0); 11059#L248-2 is_transmit2_triggered_~__retres1~2 := 0; 11060#L259 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11072#L260 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 10995#L549 assume !(0 != activate_threads_~tmp___1~0); 10951#L549-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10952#L267 assume !(1 == ~t3_pc~0); 11023#L267-2 is_transmit3_triggered_~__retres1~3 := 0; 11022#L278 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11024#L279 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 11025#L557 assume !(0 != activate_threads_~tmp___2~0); 11190#L557-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11078#L479 assume !(1 == ~M_E~0); 11061#L479-2 assume !(1 == ~T1_E~0); 11062#L484-1 assume !(1 == ~T2_E~0); 11085#L489-1 assume !(1 == ~T3_E~0); 10953#L494-1 assume !(1 == ~E_M~0); 10954#L499-1 assume !(1 == ~E_1~0); 11020#L504-1 assume !(1 == ~E_2~0); 11219#L509-1 assume !(1 == ~E_3~0); 11226#L514-1 assume { :end_inline_reset_delta_events } true; 11242#L680-3 [2018-11-18 11:32:16,022 INFO L796 eck$LassoCheckResult]: Loop: 11242#L680-3 assume true; 11568#L680-1 assume !false; 11565#L681 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 11562#L406 assume true; 11561#L354-1 assume !false; 11560#L355 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 11559#L322 assume !(0 == ~m_st~0); 11555#L326 assume !(0 == ~t1_st~0); 11556#L330 assume !(0 == ~t2_st~0); 11557#L334 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4 := 0; 11558#L344 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 11549#L345 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 11550#L359 assume !(0 != eval_~tmp~0); 11227#L421 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 11198#L287-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 11117#L431-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11118#L431-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11127#L436-3 assume !(0 == ~T2_E~0); 11172#L441-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11070#L446-3 assume 0 == ~E_M~0;~E_M~0 := 1; 11071#L451-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11093#L456-3 assume !(0 == ~E_2~0); 10985#L461-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10986#L466-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11033#L210-15 assume !(1 == ~m_pc~0); 11177#L210-17 is_master_triggered_~__retres1~0 := 0; 11680#L221-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11679#L222-5 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 11678#L533-15 assume !(0 != activate_threads_~tmp~1); 11677#L533-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11676#L229-15 assume 1 == ~t1_pc~0; 11673#L230-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 11671#L240-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11669#L241-5 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 11667#L541-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 11665#L541-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11662#L248-15 assume !(1 == ~t2_pc~0); 11660#L248-17 is_transmit2_triggered_~__retres1~2 := 0; 11658#L259-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11656#L260-5 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 11654#L549-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 11652#L549-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11650#L267-15 assume !(1 == ~t3_pc~0); 11648#L267-17 is_transmit3_triggered_~__retres1~3 := 0; 11645#L278-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11643#L279-5 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 11640#L557-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 11637#L557-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11633#L479-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11630#L479-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11627#L484-3 assume !(1 == ~T2_E~0); 11623#L489-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11620#L494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 11617#L499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11614#L504-3 assume !(1 == ~E_2~0); 11611#L509-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11608#L514-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 11605#L322-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 11599#L344-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 11596#L345-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 11593#L699 assume !(0 == start_simulation_~tmp~3); 11590#L699-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 11588#L322-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 11582#L344-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 11580#L345-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 11578#L654 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 11576#L661 stop_simulation_#res := stop_simulation_~__retres2~0; 11574#L662 start_simulation_#t~ret13 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 11571#L712 assume !(0 != start_simulation_~tmp___0~1); 11242#L680-3 [2018-11-18 11:32:16,022 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:32:16,022 INFO L82 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 3 times [2018-11-18 11:32:16,022 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:32:16,022 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:32:16,023 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:16,023 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:32:16,023 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:16,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:32:16,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:32:16,034 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:32:16,035 INFO L82 PathProgramCache]: Analyzing trace with hash -718329595, now seen corresponding path program 1 times [2018-11-18 11:32:16,035 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:32:16,035 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:32:16,035 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:16,035 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 11:32:16,036 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:16,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:32:16,054 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:32:16,054 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:32:16,054 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 11:32:16,055 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 11:32:16,055 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 11:32:16,055 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 11:32:16,055 INFO L87 Difference]: Start difference. First operand 1038 states and 1467 transitions. cyclomatic complexity: 433 Second operand 3 states. [2018-11-18 11:32:16,083 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:32:16,083 INFO L93 Difference]: Finished difference Result 1684 states and 2338 transitions. [2018-11-18 11:32:16,083 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 11:32:16,084 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1684 states and 2338 transitions. [2018-11-18 11:32:16,087 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1616 [2018-11-18 11:32:16,091 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1684 states to 1684 states and 2338 transitions. [2018-11-18 11:32:16,091 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1684 [2018-11-18 11:32:16,092 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1684 [2018-11-18 11:32:16,092 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1684 states and 2338 transitions. [2018-11-18 11:32:16,093 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:32:16,093 INFO L705 BuchiCegarLoop]: Abstraction has 1684 states and 2338 transitions. [2018-11-18 11:32:16,094 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1684 states and 2338 transitions. [2018-11-18 11:32:16,103 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1684 to 1639. [2018-11-18 11:32:16,103 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1639 states. [2018-11-18 11:32:16,106 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1639 states to 1639 states and 2277 transitions. [2018-11-18 11:32:16,106 INFO L728 BuchiCegarLoop]: Abstraction has 1639 states and 2277 transitions. [2018-11-18 11:32:16,106 INFO L608 BuchiCegarLoop]: Abstraction has 1639 states and 2277 transitions. [2018-11-18 11:32:16,106 INFO L442 BuchiCegarLoop]: ======== Iteration 10============ [2018-11-18 11:32:16,106 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1639 states and 2277 transitions. [2018-11-18 11:32:16,109 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1571 [2018-11-18 11:32:16,109 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:32:16,110 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:32:16,110 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:32:16,110 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:32:16,110 INFO L794 eck$LassoCheckResult]: Stem: 13821#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 13642#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 13628#L643 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 13629#L287 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13970#L294 assume 1 == ~m_i~0;~m_st~0 := 0; 13997#L294-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13878#L299-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13879#L304-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13931#L309-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13889#L431 assume !(0 == ~M_E~0); 13859#L431-2 assume !(0 == ~T1_E~0); 13860#L436-1 assume !(0 == ~T2_E~0); 13908#L441-1 assume !(0 == ~T3_E~0); 13797#L446-1 assume !(0 == ~E_M~0); 13798#L451-1 assume !(0 == ~E_1~0); 13831#L456-1 assume !(0 == ~E_2~0); 13693#L461-1 assume !(0 == ~E_3~0); 13694#L466-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13757#L210 assume !(1 == ~m_pc~0); 13937#L210-2 is_master_triggered_~__retres1~0 := 0; 13938#L221 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13952#L222 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 13640#L533 assume !(0 != activate_threads_~tmp~1); 13641#L533-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13765#L229 assume !(1 == ~t1_pc~0); 13631#L229-2 is_transmit1_triggered_~__retres1~1 := 0; 13632#L240 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13633#L241 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 13634#L541 assume !(0 != activate_threads_~tmp___0~0); 13885#L541-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13811#L248 assume !(1 == ~t2_pc~0); 13799#L248-2 is_transmit2_triggered_~__retres1~2 := 0; 13800#L259 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13812#L260 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 13725#L549 assume !(0 != activate_threads_~tmp___1~0); 13679#L549-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13680#L267 assume !(1 == ~t3_pc~0); 13754#L267-2 is_transmit3_triggered_~__retres1~3 := 0; 13753#L278 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 13755#L279 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 13756#L557 assume !(0 != activate_threads_~tmp___2~0); 13943#L557-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13819#L479 assume !(1 == ~M_E~0); 13801#L479-2 assume !(1 == ~T1_E~0); 13802#L484-1 assume !(1 == ~T2_E~0); 13828#L489-1 assume !(1 == ~T3_E~0); 13684#L494-1 assume !(1 == ~E_M~0); 13685#L499-1 assume !(1 == ~E_1~0); 13751#L504-1 assume !(1 == ~E_2~0); 13978#L509-1 assume !(1 == ~E_3~0); 13994#L514-1 assume { :end_inline_reset_delta_events } true; 14013#L680-3 assume true; 14856#L680-1 assume !false; 14852#L681 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 14847#L406 [2018-11-18 11:32:16,110 INFO L796 eck$LassoCheckResult]: Loop: 14847#L406 assume true; 14844#L354-1 assume !false; 14842#L355 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 14840#L322 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 14838#L344 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 14836#L345 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 14834#L359 assume 0 != eval_~tmp~0; 14833#L359-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 13762#L367 assume !(0 != eval_~tmp_ndt_1~0); 13763#L364 assume !(0 == ~t1_st~0); 14862#L378 assume !(0 == ~t2_st~0); 14849#L392 assume !(0 == ~t3_st~0); 14847#L406 [2018-11-18 11:32:16,111 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:32:16,111 INFO L82 PathProgramCache]: Analyzing trace with hash 1176639138, now seen corresponding path program 1 times [2018-11-18 11:32:16,111 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:32:16,111 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:32:16,111 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:16,112 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:32:16,112 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:16,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:32:16,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:32:16,123 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:32:16,124 INFO L82 PathProgramCache]: Analyzing trace with hash -1402040539, now seen corresponding path program 1 times [2018-11-18 11:32:16,124 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:32:16,124 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:32:16,124 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:16,124 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:32:16,124 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:16,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:32:16,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:32:16,129 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:32:16,129 INFO L82 PathProgramCache]: Analyzing trace with hash 310819910, now seen corresponding path program 1 times [2018-11-18 11:32:16,129 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:32:16,129 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:32:16,130 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:16,130 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:32:16,130 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:16,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:32:16,165 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:32:16,166 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:32:16,166 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 11:32:16,215 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 11:32:16,215 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 11:32:16,216 INFO L87 Difference]: Start difference. First operand 1639 states and 2277 transitions. cyclomatic complexity: 644 Second operand 3 states. [2018-11-18 11:32:16,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:32:16,339 INFO L93 Difference]: Finished difference Result 2970 states and 4085 transitions. [2018-11-18 11:32:16,339 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 11:32:16,340 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2970 states and 4085 transitions. [2018-11-18 11:32:16,348 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2840 [2018-11-18 11:32:16,354 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2970 states to 2970 states and 4085 transitions. [2018-11-18 11:32:16,354 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2970 [2018-11-18 11:32:16,356 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2970 [2018-11-18 11:32:16,356 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2970 states and 4085 transitions. [2018-11-18 11:32:16,359 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:32:16,359 INFO L705 BuchiCegarLoop]: Abstraction has 2970 states and 4085 transitions. [2018-11-18 11:32:16,360 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2970 states and 4085 transitions. [2018-11-18 11:32:16,378 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2970 to 2822. [2018-11-18 11:32:16,378 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2822 states. [2018-11-18 11:32:16,382 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2822 states to 2822 states and 3897 transitions. [2018-11-18 11:32:16,382 INFO L728 BuchiCegarLoop]: Abstraction has 2822 states and 3897 transitions. [2018-11-18 11:32:16,382 INFO L608 BuchiCegarLoop]: Abstraction has 2822 states and 3897 transitions. [2018-11-18 11:32:16,382 INFO L442 BuchiCegarLoop]: ======== Iteration 11============ [2018-11-18 11:32:16,383 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2822 states and 3897 transitions. [2018-11-18 11:32:16,388 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2692 [2018-11-18 11:32:16,389 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:32:16,389 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:32:16,389 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:32:16,389 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:32:16,389 INFO L794 eck$LassoCheckResult]: Stem: 18446#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 18259#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 18243#L643 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 18244#L287 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18622#L294 assume 1 == ~m_i~0;~m_st~0 := 0; 18658#L294-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 18510#L299-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18511#L304-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18608#L309-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18609#L431 assume !(0 == ~M_E~0); 18490#L431-2 assume !(0 == ~T1_E~0); 18491#L436-1 assume !(0 == ~T2_E~0); 18617#L441-1 assume !(0 == ~T3_E~0); 18618#L446-1 assume !(0 == ~E_M~0); 18457#L451-1 assume !(0 == ~E_1~0); 18458#L456-1 assume !(0 == ~E_2~0); 18309#L461-1 assume !(0 == ~E_3~0); 18310#L466-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 18598#L210 assume !(1 == ~m_pc~0); 18599#L210-2 is_master_triggered_~__retres1~0 := 0; 18600#L221 is_master_triggered_#res := is_master_triggered_~__retres1~0; 18601#L222 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 18257#L533 assume !(0 != activate_threads_~tmp~1); 18258#L533-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 18387#L229 assume !(1 == ~t1_pc~0); 18388#L229-2 is_transmit1_triggered_~__retres1~1 := 0; 18390#L240 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 18391#L241 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 18517#L541 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 18518#L541-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 18523#L248 assume !(1 == ~t2_pc~0); 18421#L248-2 is_transmit2_triggered_~__retres1~2 := 0; 18422#L259 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 18577#L260 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 18578#L549 assume !(0 != activate_threads_~tmp___1~0); 18295#L549-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 18296#L267 assume !(1 == ~t3_pc~0); 18372#L267-2 is_transmit3_triggered_~__retres1~3 := 0; 18371#L278 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 18373#L279 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 18374#L557 assume !(0 != activate_threads_~tmp___2~0); 18602#L557-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18603#L479 assume !(1 == ~M_E~0); 18423#L479-2 assume !(1 == ~T1_E~0); 18424#L484-1 assume !(1 == ~T2_E~0); 18476#L489-1 assume !(1 == ~T3_E~0); 18477#L494-1 assume !(1 == ~E_M~0); 18368#L499-1 assume !(1 == ~E_1~0); 18369#L504-1 assume !(1 == ~E_2~0); 18632#L509-1 assume !(1 == ~E_3~0); 18843#L514-1 assume { :end_inline_reset_delta_events } true; 18841#L680-3 assume true; 18839#L680-1 assume !false; 18828#L681 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 18823#L406 [2018-11-18 11:32:16,390 INFO L796 eck$LassoCheckResult]: Loop: 18823#L406 assume true; 18821#L354-1 assume !false; 18819#L355 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 18816#L322 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 18817#L344 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 18809#L345 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 18806#L359 assume 0 != eval_~tmp~0; 18800#L359-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 18794#L367 assume !(0 != eval_~tmp_ndt_1~0); 18795#L364 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 18852#L381 assume !(0 != eval_~tmp_ndt_2~0); 18837#L378 assume !(0 == ~t2_st~0); 18825#L392 assume !(0 == ~t3_st~0); 18823#L406 [2018-11-18 11:32:16,390 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:32:16,390 INFO L82 PathProgramCache]: Analyzing trace with hash 1099080806, now seen corresponding path program 1 times [2018-11-18 11:32:16,390 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:32:16,390 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:32:16,391 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:16,391 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:32:16,391 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:16,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:32:16,404 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:32:16,404 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:32:16,405 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 11:32:16,405 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 11:32:16,405 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:32:16,405 INFO L82 PathProgramCache]: Analyzing trace with hash -517653092, now seen corresponding path program 1 times [2018-11-18 11:32:16,405 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:32:16,405 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:32:16,406 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:16,406 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:32:16,406 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:16,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:32:16,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:32:16,469 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 11:32:16,469 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 11:32:16,469 INFO L87 Difference]: Start difference. First operand 2822 states and 3897 transitions. cyclomatic complexity: 1081 Second operand 3 states. [2018-11-18 11:32:16,477 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:32:16,477 INFO L93 Difference]: Finished difference Result 2772 states and 3825 transitions. [2018-11-18 11:32:16,478 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 11:32:16,478 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2772 states and 3825 transitions. [2018-11-18 11:32:16,484 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2692 [2018-11-18 11:32:16,489 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2772 states to 2772 states and 3825 transitions. [2018-11-18 11:32:16,489 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2772 [2018-11-18 11:32:16,491 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2772 [2018-11-18 11:32:16,491 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2772 states and 3825 transitions. [2018-11-18 11:32:16,493 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:32:16,493 INFO L705 BuchiCegarLoop]: Abstraction has 2772 states and 3825 transitions. [2018-11-18 11:32:16,495 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2772 states and 3825 transitions. [2018-11-18 11:32:16,511 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2772 to 2772. [2018-11-18 11:32:16,511 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2772 states. [2018-11-18 11:32:16,515 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2772 states to 2772 states and 3825 transitions. [2018-11-18 11:32:16,515 INFO L728 BuchiCegarLoop]: Abstraction has 2772 states and 3825 transitions. [2018-11-18 11:32:16,515 INFO L608 BuchiCegarLoop]: Abstraction has 2772 states and 3825 transitions. [2018-11-18 11:32:16,515 INFO L442 BuchiCegarLoop]: ======== Iteration 12============ [2018-11-18 11:32:16,515 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2772 states and 3825 transitions. [2018-11-18 11:32:16,521 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2692 [2018-11-18 11:32:16,521 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:32:16,521 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:32:16,521 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:32:16,521 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:32:16,522 INFO L794 eck$LassoCheckResult]: Stem: 24030#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 23859#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 23843#L643 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 23844#L287 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24175#L294 assume 1 == ~m_i~0;~m_st~0 := 0; 24204#L294-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24082#L299-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24083#L304-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24138#L309-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24092#L431 assume !(0 == ~M_E~0); 24062#L431-2 assume !(0 == ~T1_E~0); 24063#L436-1 assume !(0 == ~T2_E~0); 24108#L441-1 assume !(0 == ~T3_E~0); 24007#L446-1 assume !(0 == ~E_M~0); 24008#L451-1 assume !(0 == ~E_1~0); 24038#L456-1 assume !(0 == ~E_2~0); 23908#L461-1 assume !(0 == ~E_3~0); 23909#L466-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 23972#L210 assume !(1 == ~m_pc~0); 24144#L210-2 is_master_triggered_~__retres1~0 := 0; 24145#L221 is_master_triggered_#res := is_master_triggered_~__retres1~0; 24157#L222 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 23857#L533 assume !(0 != activate_threads_~tmp~1); 23858#L533-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 23980#L229 assume !(1 == ~t1_pc~0); 23848#L229-2 is_transmit1_triggered_~__retres1~1 := 0; 23849#L240 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 23850#L241 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 23851#L541 assume !(0 != activate_threads_~tmp___0~0); 24087#L541-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 24019#L248 assume !(1 == ~t2_pc~0); 24009#L248-2 is_transmit2_triggered_~__retres1~2 := 0; 24010#L259 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 24022#L260 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 23941#L549 assume !(0 != activate_threads_~tmp___1~0); 23897#L549-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 23898#L267 assume !(1 == ~t3_pc~0); 23969#L267-2 is_transmit3_triggered_~__retres1~3 := 0; 23968#L278 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 23970#L279 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 23971#L557 assume !(0 != activate_threads_~tmp___2~0); 24148#L557-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24028#L479 assume !(1 == ~M_E~0); 24011#L479-2 assume !(1 == ~T1_E~0); 24012#L484-1 assume !(1 == ~T2_E~0); 24035#L489-1 assume !(1 == ~T3_E~0); 23899#L494-1 assume !(1 == ~E_M~0); 23900#L499-1 assume !(1 == ~E_1~0); 23966#L504-1 assume !(1 == ~E_2~0); 24183#L509-1 assume !(1 == ~E_3~0); 24200#L514-1 assume { :end_inline_reset_delta_events } true; 24218#L680-3 assume true; 25666#L680-1 assume !false; 25661#L681 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 25654#L406 [2018-11-18 11:32:16,522 INFO L796 eck$LassoCheckResult]: Loop: 25654#L406 assume true; 25649#L354-1 assume !false; 25644#L355 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 25639#L322 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 25635#L344 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 25629#L345 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 25625#L359 assume 0 != eval_~tmp~0; 25619#L359-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 25613#L367 assume !(0 != eval_~tmp_ndt_1~0); 25543#L364 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 25533#L381 assume !(0 != eval_~tmp_ndt_2~0); 25528#L378 assume !(0 == ~t2_st~0); 25521#L392 assume !(0 == ~t3_st~0); 25654#L406 [2018-11-18 11:32:16,522 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:32:16,522 INFO L82 PathProgramCache]: Analyzing trace with hash 1176639138, now seen corresponding path program 2 times [2018-11-18 11:32:16,522 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:32:16,522 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:32:16,523 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:16,523 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:32:16,523 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:16,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:32:16,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:32:16,534 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:32:16,534 INFO L82 PathProgramCache]: Analyzing trace with hash -517653092, now seen corresponding path program 2 times [2018-11-18 11:32:16,534 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:32:16,535 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:32:16,535 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:16,535 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 11:32:16,535 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:16,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:32:16,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:32:16,540 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:32:16,540 INFO L82 PathProgramCache]: Analyzing trace with hash 1041413275, now seen corresponding path program 1 times [2018-11-18 11:32:16,540 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:32:16,540 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:32:16,541 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:16,541 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 11:32:16,541 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:16,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:32:16,566 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:32:16,566 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:32:16,566 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 11:32:16,651 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 11:32:16,651 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 11:32:16,651 INFO L87 Difference]: Start difference. First operand 2772 states and 3825 transitions. cyclomatic complexity: 1059 Second operand 3 states. [2018-11-18 11:32:16,700 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:32:16,700 INFO L93 Difference]: Finished difference Result 3423 states and 4684 transitions. [2018-11-18 11:32:16,701 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 11:32:16,701 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3423 states and 4684 transitions. [2018-11-18 11:32:16,710 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 3339 [2018-11-18 11:32:16,718 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3423 states to 3423 states and 4684 transitions. [2018-11-18 11:32:16,718 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3423 [2018-11-18 11:32:16,720 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3423 [2018-11-18 11:32:16,720 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3423 states and 4684 transitions. [2018-11-18 11:32:16,722 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:32:16,722 INFO L705 BuchiCegarLoop]: Abstraction has 3423 states and 4684 transitions. [2018-11-18 11:32:16,724 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3423 states and 4684 transitions. [2018-11-18 11:32:16,744 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3423 to 3327. [2018-11-18 11:32:16,744 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3327 states. [2018-11-18 11:32:16,748 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3327 states to 3327 states and 4564 transitions. [2018-11-18 11:32:16,748 INFO L728 BuchiCegarLoop]: Abstraction has 3327 states and 4564 transitions. [2018-11-18 11:32:16,748 INFO L608 BuchiCegarLoop]: Abstraction has 3327 states and 4564 transitions. [2018-11-18 11:32:16,748 INFO L442 BuchiCegarLoop]: ======== Iteration 13============ [2018-11-18 11:32:16,749 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3327 states and 4564 transitions. [2018-11-18 11:32:16,754 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 3243 [2018-11-18 11:32:16,755 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:32:16,755 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:32:16,755 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:32:16,755 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:32:16,755 INFO L794 eck$LassoCheckResult]: Stem: 30234#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 30063#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 30046#L643 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 30047#L287 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30381#L294 assume 1 == ~m_i~0;~m_st~0 := 0; 30402#L294-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30292#L299-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30293#L304-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30347#L309-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30302#L431 assume !(0 == ~M_E~0); 30274#L431-2 assume !(0 == ~T1_E~0); 30275#L436-1 assume !(0 == ~T2_E~0); 30319#L441-1 assume !(0 == ~T3_E~0); 30210#L446-1 assume !(0 == ~E_M~0); 30211#L451-1 assume !(0 == ~E_1~0); 30243#L456-1 assume !(0 == ~E_2~0); 30110#L461-1 assume !(0 == ~E_3~0); 30111#L466-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 30174#L210 assume !(1 == ~m_pc~0); 30354#L210-2 is_master_triggered_~__retres1~0 := 0; 30355#L221 is_master_triggered_#res := is_master_triggered_~__retres1~0; 30365#L222 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 30061#L533 assume !(0 != activate_threads_~tmp~1); 30062#L533-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 30183#L229 assume !(1 == ~t1_pc~0); 30051#L229-2 is_transmit1_triggered_~__retres1~1 := 0; 30052#L240 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 30053#L241 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 30054#L541 assume !(0 != activate_threads_~tmp___0~0); 30297#L541-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 30222#L248 assume !(1 == ~t2_pc~0); 30212#L248-2 is_transmit2_triggered_~__retres1~2 := 0; 30213#L259 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 30225#L260 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 30143#L549 assume !(0 != activate_threads_~tmp___1~0); 30099#L549-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 30100#L267 assume !(1 == ~t3_pc~0); 30171#L267-2 is_transmit3_triggered_~__retres1~3 := 0; 30170#L278 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 30172#L279 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 30173#L557 assume !(0 != activate_threads_~tmp___2~0); 30358#L557-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30231#L479 assume !(1 == ~M_E~0); 30214#L479-2 assume !(1 == ~T1_E~0); 30215#L484-1 assume !(1 == ~T2_E~0); 30240#L489-1 assume !(1 == ~T3_E~0); 30101#L494-1 assume !(1 == ~E_M~0); 30102#L499-1 assume !(1 == ~E_1~0); 30168#L504-1 assume !(1 == ~E_2~0); 30387#L509-1 assume !(1 == ~E_3~0); 30399#L514-1 assume { :end_inline_reset_delta_events } true; 30417#L680-3 assume true; 31750#L680-1 assume !false; 31746#L681 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 31741#L406 [2018-11-18 11:32:16,756 INFO L796 eck$LassoCheckResult]: Loop: 31741#L406 assume true; 31738#L354-1 assume !false; 31703#L355 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 31700#L322 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 31698#L344 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 31695#L345 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 31692#L359 assume 0 != eval_~tmp~0; 31693#L359-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 31685#L367 assume !(0 != eval_~tmp_ndt_1~0); 31683#L364 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 31678#L381 assume !(0 != eval_~tmp_ndt_2~0); 31679#L378 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 31671#L395 assume !(0 != eval_~tmp_ndt_3~0); 31672#L392 assume !(0 == ~t3_st~0); 31741#L406 [2018-11-18 11:32:16,756 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:32:16,756 INFO L82 PathProgramCache]: Analyzing trace with hash 1176639138, now seen corresponding path program 3 times [2018-11-18 11:32:16,756 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:32:16,756 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:32:16,756 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:16,757 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:32:16,757 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:16,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:32:16,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:32:16,768 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:32:16,768 INFO L82 PathProgramCache]: Analyzing trace with hash 1132493035, now seen corresponding path program 1 times [2018-11-18 11:32:16,768 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:32:16,768 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:32:16,769 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:16,769 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 11:32:16,769 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:16,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:32:16,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:32:16,773 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:32:16,773 INFO L82 PathProgramCache]: Analyzing trace with hash -2076057140, now seen corresponding path program 1 times [2018-11-18 11:32:16,773 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:32:16,773 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:32:16,774 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:16,774 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:32:16,774 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:16,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:32:16,798 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:32:16,798 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:32:16,798 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 11:32:16,856 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 11:32:16,856 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 11:32:16,857 INFO L87 Difference]: Start difference. First operand 3327 states and 4564 transitions. cyclomatic complexity: 1243 Second operand 3 states. [2018-11-18 11:32:16,888 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:32:16,888 INFO L93 Difference]: Finished difference Result 5619 states and 7652 transitions. [2018-11-18 11:32:16,889 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 11:32:16,889 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5619 states and 7652 transitions. [2018-11-18 11:32:16,900 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5507 [2018-11-18 11:32:16,914 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5619 states to 5619 states and 7652 transitions. [2018-11-18 11:32:16,914 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5619 [2018-11-18 11:32:16,917 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5619 [2018-11-18 11:32:16,917 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5619 states and 7652 transitions. [2018-11-18 11:32:16,921 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:32:16,921 INFO L705 BuchiCegarLoop]: Abstraction has 5619 states and 7652 transitions. [2018-11-18 11:32:16,924 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5619 states and 7652 transitions. [2018-11-18 11:32:16,961 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5619 to 5499. [2018-11-18 11:32:16,961 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5499 states. [2018-11-18 11:32:16,969 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5499 states to 5499 states and 7532 transitions. [2018-11-18 11:32:16,969 INFO L728 BuchiCegarLoop]: Abstraction has 5499 states and 7532 transitions. [2018-11-18 11:32:16,969 INFO L608 BuchiCegarLoop]: Abstraction has 5499 states and 7532 transitions. [2018-11-18 11:32:16,969 INFO L442 BuchiCegarLoop]: ======== Iteration 14============ [2018-11-18 11:32:16,969 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5499 states and 7532 transitions. [2018-11-18 11:32:16,980 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5387 [2018-11-18 11:32:16,981 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:32:16,981 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:32:16,981 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:32:16,981 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:32:16,981 INFO L794 eck$LassoCheckResult]: Stem: 39192#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 39018#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 39000#L643 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 39001#L287 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39338#L294 assume 1 == ~m_i~0;~m_st~0 := 0; 39359#L294-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39252#L299-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39253#L304-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39306#L309-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 39265#L431 assume !(0 == ~M_E~0); 39233#L431-2 assume !(0 == ~T1_E~0); 39234#L436-1 assume !(0 == ~T2_E~0); 39282#L441-1 assume !(0 == ~T3_E~0); 39167#L446-1 assume !(0 == ~E_M~0); 39168#L451-1 assume !(0 == ~E_1~0); 39201#L456-1 assume !(0 == ~E_2~0); 39065#L461-1 assume !(0 == ~E_3~0); 39066#L466-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 39129#L210 assume !(1 == ~m_pc~0); 39313#L210-2 is_master_triggered_~__retres1~0 := 0; 39314#L221 is_master_triggered_#res := is_master_triggered_~__retres1~0; 39324#L222 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 39016#L533 assume !(0 != activate_threads_~tmp~1); 39017#L533-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 39139#L229 assume !(1 == ~t1_pc~0); 39005#L229-2 is_transmit1_triggered_~__retres1~1 := 0; 39006#L240 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 39007#L241 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 39008#L541 assume !(0 != activate_threads_~tmp___0~0); 39258#L541-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 39179#L248 assume !(1 == ~t2_pc~0); 39169#L248-2 is_transmit2_triggered_~__retres1~2 := 0; 39170#L259 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 39182#L260 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 39098#L549 assume !(0 != activate_threads_~tmp___1~0); 39054#L549-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 39055#L267 assume !(1 == ~t3_pc~0); 39126#L267-2 is_transmit3_triggered_~__retres1~3 := 0; 39125#L278 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 39127#L279 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 39128#L557 assume !(0 != activate_threads_~tmp___2~0); 39317#L557-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39189#L479 assume !(1 == ~M_E~0); 39171#L479-2 assume !(1 == ~T1_E~0); 39172#L484-1 assume !(1 == ~T2_E~0); 39198#L489-1 assume !(1 == ~T3_E~0); 39056#L494-1 assume !(1 == ~E_M~0); 39057#L499-1 assume !(1 == ~E_1~0); 39123#L504-1 assume !(1 == ~E_2~0); 39346#L509-1 assume !(1 == ~E_3~0); 39356#L514-1 assume { :end_inline_reset_delta_events } true; 39371#L680-3 assume true; 42335#L680-1 assume !false; 42332#L681 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 42330#L406 [2018-11-18 11:32:16,982 INFO L796 eck$LassoCheckResult]: Loop: 42330#L406 assume true; 42328#L354-1 assume !false; 42326#L355 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 42324#L322 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 42322#L344 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 42320#L345 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 42316#L359 assume 0 != eval_~tmp~0; 42313#L359-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 42309#L367 assume !(0 != eval_~tmp_ndt_1~0); 42306#L364 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 42287#L381 assume !(0 != eval_~tmp_ndt_2~0); 42303#L378 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 42338#L395 assume !(0 != eval_~tmp_ndt_3~0); 42336#L392 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 40539#L409 assume !(0 != eval_~tmp_ndt_4~0); 42330#L406 [2018-11-18 11:32:16,982 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:32:16,982 INFO L82 PathProgramCache]: Analyzing trace with hash 1176639138, now seen corresponding path program 4 times [2018-11-18 11:32:16,982 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:32:16,982 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:32:16,983 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:16,983 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:32:16,983 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:16,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:32:16,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:32:16,994 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:32:16,995 INFO L82 PathProgramCache]: Analyzing trace with hash 747542486, now seen corresponding path program 1 times [2018-11-18 11:32:16,995 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:32:16,995 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:32:16,995 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:16,996 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 11:32:16,996 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:16,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:32:16,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:32:17,001 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:32:17,001 INFO L82 PathProgramCache]: Analyzing trace with hash 66734869, now seen corresponding path program 1 times [2018-11-18 11:32:17,001 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:32:17,001 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:32:17,002 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:17,002 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:32:17,002 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:32:17,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:32:17,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:32:17,356 WARN L180 SmtUtils]: Spent 267.00 ms on a formula simplification. DAG size of input: 136 DAG size of output: 92 [2018-11-18 11:32:17,448 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 18.11 11:32:17 BoogieIcfgContainer [2018-11-18 11:32:17,448 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2018-11-18 11:32:17,449 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-18 11:32:17,449 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-18 11:32:17,449 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-18 11:32:17,449 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 11:32:14" (3/4) ... [2018-11-18 11:32:17,452 INFO L141 WitnessPrinter]: Generating witness for non-termination counterexample [2018-11-18 11:32:17,496 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_7f1434c4-8cda-4b7d-9907-b179c1c37dd0/bin-2019/uautomizer/witness.graphml [2018-11-18 11:32:17,496 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-18 11:32:17,497 INFO L168 Benchmark]: Toolchain (without parser) took 3948.00 ms. Allocated memory was 1.0 GB in the beginning and 1.4 GB in the end (delta: 348.7 MB). Free memory was 959.1 MB in the beginning and 1.2 GB in the end (delta: -279.3 MB). Peak memory consumption was 69.4 MB. Max. memory is 11.5 GB. [2018-11-18 11:32:17,497 INFO L168 Benchmark]: CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 11:32:17,497 INFO L168 Benchmark]: CACSL2BoogieTranslator took 203.05 ms. Allocated memory is still 1.0 GB. Free memory was 959.1 MB in the beginning and 940.3 MB in the end (delta: 18.8 MB). Peak memory consumption was 18.8 MB. Max. memory is 11.5 GB. [2018-11-18 11:32:17,498 INFO L168 Benchmark]: Boogie Procedure Inliner took 71.70 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 157.8 MB). Free memory was 940.3 MB in the beginning and 1.2 GB in the end (delta: -212.0 MB). Peak memory consumption was 15.1 MB. Max. memory is 11.5 GB. [2018-11-18 11:32:17,498 INFO L168 Benchmark]: Boogie Preprocessor took 37.54 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 3.3 MB). Peak memory consumption was 3.3 MB. Max. memory is 11.5 GB. [2018-11-18 11:32:17,498 INFO L168 Benchmark]: RCFGBuilder took 706.51 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 81.5 MB). Peak memory consumption was 81.5 MB. Max. memory is 11.5 GB. [2018-11-18 11:32:17,498 INFO L168 Benchmark]: BuchiAutomizer took 2878.84 ms. Allocated memory was 1.2 GB in the beginning and 1.4 GB in the end (delta: 190.8 MB). Free memory was 1.1 GB in the beginning and 1.2 GB in the end (delta: -178.5 MB). Peak memory consumption was 325.9 MB. Max. memory is 11.5 GB. [2018-11-18 11:32:17,499 INFO L168 Benchmark]: Witness Printer took 47.55 ms. Allocated memory is still 1.4 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 7.6 MB). Peak memory consumption was 7.6 MB. Max. memory is 11.5 GB. [2018-11-18 11:32:17,500 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 203.05 ms. Allocated memory is still 1.0 GB. Free memory was 959.1 MB in the beginning and 940.3 MB in the end (delta: 18.8 MB). Peak memory consumption was 18.8 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 71.70 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 157.8 MB). Free memory was 940.3 MB in the beginning and 1.2 GB in the end (delta: -212.0 MB). Peak memory consumption was 15.1 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 37.54 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 3.3 MB). Peak memory consumption was 3.3 MB. Max. memory is 11.5 GB. * RCFGBuilder took 706.51 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 81.5 MB). Peak memory consumption was 81.5 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 2878.84 ms. Allocated memory was 1.2 GB in the beginning and 1.4 GB in the end (delta: 190.8 MB). Free memory was 1.1 GB in the beginning and 1.2 GB in the end (delta: -178.5 MB). Peak memory consumption was 325.9 MB. Max. memory is 11.5 GB. * Witness Printer took 47.55 ms. Allocated memory is still 1.4 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 7.6 MB). Peak memory consumption was 7.6 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 13 terminating modules (13 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.13 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 5499 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 2.8s and 14 iterations. TraceHistogramMax:1. Analysis of lassos took 1.6s. Construction of modules took 0.3s. Büchi inclusion checks took 0.2s. Highest rank in rank-based complementation 0. Minimization of det autom 13. Minimization of nondet autom 0. Automata minimization 0.2s AutomataMinimizationTime, 13 MinimizatonAttempts, 2088 StatesRemovedByMinimization, 8 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had 5499 states and ocurred in iteration 13. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 6361 SDtfs, 6892 SDslu, 5690 SDs, 0 SdLazy, 244 SolverSat, 126 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.3s Time LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc3 concLT0 SILN1 SILU0 SILI6 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 354]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {__retres1=0, t3_st=0, token=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@60f94235=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@bff5d6a=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@925b286=0, tmp=1, __retres1=0, kernel_st=1, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4300542f=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@32d0492=0, E_3=2, \result=0, E_1=2, tmp_ndt_2=0, \result=0, \result=0, tmp_ndt_4=0, m_st=0, tmp___2=0, tmp___0=0, t3_pc=0, tmp=0, __retres1=0, m_pc=0, \result=0, __retres1=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4d69e479=0, T2_E=2, tmp___0=0, t1_pc=0, E_2=2, T1_E=2, __retres1=1, tmp_ndt_1=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, t2_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1c8850e3=0, t3_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6b14975e=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@272b0ee0=0, t1_st=0, local=0, t2_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@718e0d3b=0, E_M=2, tmp___1=0, T3_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@18509bbf=0, t1_i=1, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 354]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int m_st ; [L19] int t1_st ; [L20] int t2_st ; [L21] int t3_st ; [L22] int m_i ; [L23] int t1_i ; [L24] int t2_i ; [L25] int t3_i ; [L26] int M_E = 2; [L27] int T1_E = 2; [L28] int T2_E = 2; [L29] int T3_E = 2; [L30] int E_M = 2; [L31] int E_1 = 2; [L32] int E_2 = 2; [L33] int E_3 = 2; [L39] int token ; [L41] int local ; [L725] int __retres1 ; [L729] CALL init_model() [L638] m_i = 1 [L639] t1_i = 1 [L640] t2_i = 1 [L641] RET t3_i = 1 [L729] init_model() [L730] CALL start_simulation() [L666] int kernel_st ; [L667] int tmp ; [L668] int tmp___0 ; [L672] kernel_st = 0 [L673] FCALL update_channels() [L674] CALL init_threads() [L294] COND TRUE m_i == 1 [L295] m_st = 0 [L299] COND TRUE t1_i == 1 [L300] t1_st = 0 [L304] COND TRUE t2_i == 1 [L305] t2_st = 0 [L309] COND TRUE t3_i == 1 [L310] RET t3_st = 0 [L674] init_threads() [L675] CALL fire_delta_events() [L431] COND FALSE !(M_E == 0) [L436] COND FALSE !(T1_E == 0) [L441] COND FALSE !(T2_E == 0) [L446] COND FALSE !(T3_E == 0) [L451] COND FALSE !(E_M == 0) [L456] COND FALSE !(E_1 == 0) [L461] COND FALSE !(E_2 == 0) [L466] COND FALSE, RET !(E_3 == 0) [L675] fire_delta_events() [L676] CALL activate_threads() [L524] int tmp ; [L525] int tmp___0 ; [L526] int tmp___1 ; [L527] int tmp___2 ; [L531] CALL, EXPR is_master_triggered() [L207] int __retres1 ; [L210] COND FALSE !(m_pc == 1) [L220] __retres1 = 0 [L222] RET return (__retres1); [L531] EXPR is_master_triggered() [L531] tmp = is_master_triggered() [L533] COND FALSE !(\read(tmp)) [L539] CALL, EXPR is_transmit1_triggered() [L226] int __retres1 ; [L229] COND FALSE !(t1_pc == 1) [L239] __retres1 = 0 [L241] RET return (__retres1); [L539] EXPR is_transmit1_triggered() [L539] tmp___0 = is_transmit1_triggered() [L541] COND FALSE !(\read(tmp___0)) [L547] CALL, EXPR is_transmit2_triggered() [L245] int __retres1 ; [L248] COND FALSE !(t2_pc == 1) [L258] __retres1 = 0 [L260] RET return (__retres1); [L547] EXPR is_transmit2_triggered() [L547] tmp___1 = is_transmit2_triggered() [L549] COND FALSE !(\read(tmp___1)) [L555] CALL, EXPR is_transmit3_triggered() [L264] int __retres1 ; [L267] COND FALSE !(t3_pc == 1) [L277] __retres1 = 0 [L279] RET return (__retres1); [L555] EXPR is_transmit3_triggered() [L555] tmp___2 = is_transmit3_triggered() [L557] COND FALSE, RET !(\read(tmp___2)) [L676] activate_threads() [L677] CALL reset_delta_events() [L479] COND FALSE !(M_E == 1) [L484] COND FALSE !(T1_E == 1) [L489] COND FALSE !(T2_E == 1) [L494] COND FALSE !(T3_E == 1) [L499] COND FALSE !(E_M == 1) [L504] COND FALSE !(E_1 == 1) [L509] COND FALSE !(E_2 == 1) [L514] COND FALSE, RET !(E_3 == 1) [L677] reset_delta_events() [L680] COND TRUE 1 [L683] kernel_st = 1 [L684] CALL eval() [L350] int tmp ; Loop: [L354] COND TRUE 1 [L357] CALL, EXPR exists_runnable_thread() [L319] int __retres1 ; [L322] COND TRUE m_st == 0 [L323] __retres1 = 1 [L345] RET return (__retres1); [L357] EXPR exists_runnable_thread() [L357] tmp = exists_runnable_thread() [L359] COND TRUE \read(tmp) [L364] COND TRUE m_st == 0 [L365] int tmp_ndt_1; [L366] tmp_ndt_1 = __VERIFIER_nondet_int() [L367] COND FALSE !(\read(tmp_ndt_1)) [L378] COND TRUE t1_st == 0 [L379] int tmp_ndt_2; [L380] tmp_ndt_2 = __VERIFIER_nondet_int() [L381] COND FALSE !(\read(tmp_ndt_2)) [L392] COND TRUE t2_st == 0 [L393] int tmp_ndt_3; [L394] tmp_ndt_3 = __VERIFIER_nondet_int() [L395] COND FALSE !(\read(tmp_ndt_3)) [L406] COND TRUE t3_st == 0 [L407] int tmp_ndt_4; [L408] tmp_ndt_4 = __VERIFIER_nondet_int() [L409] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...