./Ultimate.py --spec ../../sv-benchmarks/c/Termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.04_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 5842f4b8 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_15d9ffa9-9d9e-4b80-b795-6423af48da6b/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_15d9ffa9-9d9e-4b80-b795-6423af48da6b/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_15d9ffa9-9d9e-4b80-b795-6423af48da6b/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_15d9ffa9-9d9e-4b80-b795-6423af48da6b/bin-2019/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.04_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_15d9ffa9-9d9e-4b80-b795-6423af48da6b/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_15d9ffa9-9d9e-4b80-b795-6423af48da6b/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 5e27a879cb97b2b6600a7b4379c4e090f4fa709a ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.23-5842f4b [2018-11-18 11:59:34,860 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-18 11:59:34,861 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-18 11:59:34,871 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-18 11:59:34,874 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-18 11:59:34,875 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-18 11:59:34,877 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-18 11:59:34,879 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-18 11:59:34,881 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-18 11:59:34,884 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-18 11:59:34,886 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-18 11:59:34,887 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-18 11:59:34,888 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-18 11:59:34,888 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-18 11:59:34,889 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-18 11:59:34,889 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-18 11:59:34,890 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-18 11:59:34,891 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-18 11:59:34,897 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-18 11:59:34,898 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-18 11:59:34,899 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-18 11:59:34,900 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-18 11:59:34,902 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-18 11:59:34,902 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-18 11:59:34,902 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-18 11:59:34,903 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-18 11:59:34,904 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-18 11:59:34,904 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-18 11:59:34,905 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-18 11:59:34,906 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-18 11:59:34,906 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-18 11:59:34,907 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-18 11:59:34,907 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-18 11:59:34,907 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-18 11:59:34,908 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-18 11:59:34,909 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-18 11:59:34,909 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_15d9ffa9-9d9e-4b80-b795-6423af48da6b/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2018-11-18 11:59:34,925 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-18 11:59:34,925 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-18 11:59:34,926 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-18 11:59:34,926 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-18 11:59:34,927 INFO L133 SettingsManager]: * Use SBE=true [2018-11-18 11:59:34,927 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2018-11-18 11:59:34,927 INFO L133 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2018-11-18 11:59:34,927 INFO L133 SettingsManager]: * Use old map elimination=false [2018-11-18 11:59:34,927 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false [2018-11-18 11:59:34,928 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true [2018-11-18 11:59:34,928 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2018-11-18 11:59:34,928 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-18 11:59:34,928 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-18 11:59:34,929 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-18 11:59:34,929 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-18 11:59:34,929 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-18 11:59:34,929 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-18 11:59:34,929 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2018-11-18 11:59:34,929 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2018-11-18 11:59:34,929 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2018-11-18 11:59:34,930 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-18 11:59:34,930 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-18 11:59:34,930 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false [2018-11-18 11:59:34,930 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-18 11:59:34,930 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2018-11-18 11:59:34,930 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-18 11:59:34,930 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-18 11:59:34,931 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2018-11-18 11:59:34,931 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-18 11:59:34,931 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-18 11:59:34,931 INFO L133 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2018-11-18 11:59:34,935 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-11-18 11:59:34,936 INFO L133 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_15d9ffa9-9d9e-4b80-b795-6423af48da6b/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 5e27a879cb97b2b6600a7b4379c4e090f4fa709a [2018-11-18 11:59:34,966 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-18 11:59:34,975 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-18 11:59:34,978 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-18 11:59:34,979 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-18 11:59:34,979 INFO L276 PluginConnector]: CDTParser initialized [2018-11-18 11:59:34,980 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_15d9ffa9-9d9e-4b80-b795-6423af48da6b/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/token_ring.04_false-unreach-call_false-termination.cil.c [2018-11-18 11:59:35,030 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_15d9ffa9-9d9e-4b80-b795-6423af48da6b/bin-2019/uautomizer/data/d0f02f02e/eac24e13eaa84edeb0a32eab199b08a9/FLAGf68586f93 [2018-11-18 11:59:35,412 INFO L307 CDTParser]: Found 1 translation units. [2018-11-18 11:59:35,412 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_15d9ffa9-9d9e-4b80-b795-6423af48da6b/sv-benchmarks/c/systemc/token_ring.04_false-unreach-call_false-termination.cil.c [2018-11-18 11:59:35,420 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_15d9ffa9-9d9e-4b80-b795-6423af48da6b/bin-2019/uautomizer/data/d0f02f02e/eac24e13eaa84edeb0a32eab199b08a9/FLAGf68586f93 [2018-11-18 11:59:35,430 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_15d9ffa9-9d9e-4b80-b795-6423af48da6b/bin-2019/uautomizer/data/d0f02f02e/eac24e13eaa84edeb0a32eab199b08a9 [2018-11-18 11:59:35,433 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-18 11:59:35,434 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-18 11:59:35,435 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-18 11:59:35,435 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-18 11:59:35,438 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-18 11:59:35,439 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 11:59:35" (1/1) ... [2018-11-18 11:59:35,441 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7072fde6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 11:59:35, skipping insertion in model container [2018-11-18 11:59:35,441 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 11:59:35" (1/1) ... [2018-11-18 11:59:35,447 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-18 11:59:35,477 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-18 11:59:35,637 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 11:59:35,642 INFO L191 MainTranslator]: Completed pre-run [2018-11-18 11:59:35,672 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 11:59:35,684 INFO L195 MainTranslator]: Completed translation [2018-11-18 11:59:35,685 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 11:59:35 WrapperNode [2018-11-18 11:59:35,685 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-18 11:59:35,685 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-18 11:59:35,685 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-18 11:59:35,686 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-18 11:59:35,690 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 11:59:35" (1/1) ... [2018-11-18 11:59:35,696 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 11:59:35" (1/1) ... [2018-11-18 11:59:35,778 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-18 11:59:35,778 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-18 11:59:35,779 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-18 11:59:35,779 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-18 11:59:35,787 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 11:59:35" (1/1) ... [2018-11-18 11:59:35,787 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 11:59:35" (1/1) ... [2018-11-18 11:59:35,795 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 11:59:35" (1/1) ... [2018-11-18 11:59:35,796 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 11:59:35" (1/1) ... [2018-11-18 11:59:35,806 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 11:59:35" (1/1) ... [2018-11-18 11:59:35,820 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 11:59:35" (1/1) ... [2018-11-18 11:59:35,823 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 11:59:35" (1/1) ... [2018-11-18 11:59:35,832 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-18 11:59:35,840 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-18 11:59:35,840 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-18 11:59:35,840 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-18 11:59:35,841 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 11:59:35" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_15d9ffa9-9d9e-4b80-b795-6423af48da6b/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 11:59:35,892 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-18 11:59:35,892 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-18 11:59:37,177 INFO L278 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-18 11:59:37,177 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 11:59:37 BoogieIcfgContainer [2018-11-18 11:59:37,177 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-18 11:59:37,178 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2018-11-18 11:59:37,178 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2018-11-18 11:59:37,180 INFO L276 PluginConnector]: BuchiAutomizer initialized [2018-11-18 11:59:37,181 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 11:59:37,181 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 18.11 11:59:35" (1/3) ... [2018-11-18 11:59:37,183 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@64ee486 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 11:59:37, skipping insertion in model container [2018-11-18 11:59:37,183 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 11:59:37,183 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 11:59:35" (2/3) ... [2018-11-18 11:59:37,183 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@64ee486 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 11:59:37, skipping insertion in model container [2018-11-18 11:59:37,183 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 11:59:37,184 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 11:59:37" (3/3) ... [2018-11-18 11:59:37,185 INFO L375 chiAutomizerObserver]: Analyzing ICFG token_ring.04_false-unreach-call_false-termination.cil.c [2018-11-18 11:59:37,234 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-18 11:59:37,234 INFO L374 BuchiCegarLoop]: Interprodecural is true [2018-11-18 11:59:37,234 INFO L375 BuchiCegarLoop]: Hoare is false [2018-11-18 11:59:37,234 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2018-11-18 11:59:37,234 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-18 11:59:37,235 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-18 11:59:37,235 INFO L379 BuchiCegarLoop]: Difference is false [2018-11-18 11:59:37,235 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-18 11:59:37,235 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2018-11-18 11:59:37,255 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 445 states. [2018-11-18 11:59:37,292 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 374 [2018-11-18 11:59:37,292 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:59:37,292 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:59:37,301 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:37,301 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:37,301 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ [2018-11-18 11:59:37,302 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 445 states. [2018-11-18 11:59:37,309 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 374 [2018-11-18 11:59:37,309 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:59:37,309 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:59:37,311 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:37,311 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:37,319 INFO L794 eck$LassoCheckResult]: Stem: 303#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 212#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 411#L768true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 367#L348true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 168#L355true assume !(1 == ~m_i~0);~m_st~0 := 2; 172#L355-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 429#L360-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 90#L365-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 370#L370-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 147#L375-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 234#L516true assume !(0 == ~M_E~0); 237#L516-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 33#L521-1true assume !(0 == ~T2_E~0); 395#L526-1true assume !(0 == ~T3_E~0); 176#L531-1true assume !(0 == ~T4_E~0); 440#L536-1true assume !(0 == ~E_M~0); 98#L541-1true assume !(0 == ~E_1~0); 380#L546-1true assume !(0 == ~E_2~0); 155#L551-1true assume !(0 == ~E_3~0); 61#L556-1true assume 0 == ~E_4~0;~E_4~0 := 1; 332#L561-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 210#L252true assume 1 == ~m_pc~0; 297#L253true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 211#L263true is_master_triggered_#res := is_master_triggered_~__retres1~0; 298#L264true activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 285#L639true assume !(0 != activate_threads_~tmp~1); 152#L639-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 357#L271true assume !(1 == ~t1_pc~0); 371#L271-2true is_transmit1_triggered_~__retres1~1 := 0; 358#L282true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 418#L283true activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 405#L647true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 408#L647-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 38#L290true assume 1 == ~t2_pc~0; 87#L291true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 39#L301true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 88#L302true activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 66#L655true assume !(0 != activate_threads_~tmp___1~0); 56#L655-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 150#L309true assume !(1 == ~t3_pc~0); 127#L309-2true is_transmit3_triggered_~__retres1~3 := 0; 149#L320true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 91#L321true activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 182#L663true assume !(0 != activate_threads_~tmp___2~0); 183#L663-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 272#L328true assume 1 == ~t4_pc~0; 214#L329true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 270#L339true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 213#L340true activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 341#L671true assume !(0 != activate_threads_~tmp___3~0); 329#L671-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 96#L574true assume !(1 == ~M_E~0); 99#L574-2true assume !(1 == ~T1_E~0); 379#L579-1true assume !(1 == ~T2_E~0); 153#L584-1true assume !(1 == ~T3_E~0); 58#L589-1true assume !(1 == ~T4_E~0); 331#L594-1true assume !(1 == ~E_M~0); 6#L599-1true assume 1 == ~E_1~0;~E_1~0 := 2; 244#L604-1true assume !(1 == ~E_2~0); 45#L609-1true assume !(1 == ~E_3~0); 409#L614-1true assume !(1 == ~E_4~0); 184#L619-1true assume { :end_inline_reset_delta_events } true; 105#L805-3true [2018-11-18 11:59:37,320 INFO L796 eck$LassoCheckResult]: Loop: 105#L805-3true assume true; 102#L805-1true assume !false; 185#L806true start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 381#L491true assume !true; 333#L506true assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 374#L348-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 238#L516-3true assume 0 == ~M_E~0;~M_E~0 := 1; 239#L516-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 40#L521-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 400#L526-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 179#L531-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 442#L536-3true assume !(0 == ~E_M~0); 101#L541-3true assume 0 == ~E_1~0;~E_1~0 := 1; 384#L546-3true assume 0 == ~E_2~0;~E_2~0 := 1; 142#L551-3true assume 0 == ~E_3~0;~E_3~0 := 1; 50#L556-3true assume 0 == ~E_4~0;~E_4~0 := 1; 319#L561-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 343#L252-18true assume !(1 == ~m_pc~0); 325#L252-20true is_master_triggered_~__retres1~0 := 0; 220#L263-6true is_master_triggered_#res := is_master_triggered_~__retres1~0; 310#L264-6true activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 119#L639-18true assume !(0 != activate_threads_~tmp~1); 122#L639-20true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 441#L271-18true assume 1 == ~t1_pc~0; 421#L272-6true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 352#L282-6true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 422#L283-6true activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 265#L647-18true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 250#L647-20true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4#L290-18true assume 1 == ~t2_pc~0; 72#L291-6true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 16#L301-6true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 73#L302-6true activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 390#L655-18true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 391#L655-20true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 104#L309-18true assume 1 == ~t3_pc~0; 197#L310-6true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 139#L320-6true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 196#L321-6true activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 165#L663-18true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 159#L663-20true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 248#L328-18true assume !(1 == ~t4_pc~0); 240#L328-20true is_transmit4_triggered_~__retres1~4 := 0; 260#L339-6true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 203#L340-6true activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 293#L671-18true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 299#L671-20true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 100#L574-3true assume 1 == ~M_E~0;~M_E~0 := 2; 89#L574-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 383#L579-3true assume !(1 == ~T2_E~0); 156#L584-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 63#L589-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 335#L594-3true assume 1 == ~E_M~0;~E_M~0 := 2; 78#L599-3true assume 1 == ~E_1~0;~E_1~0 := 2; 235#L604-3true assume 1 == ~E_2~0;~E_2~0 := 2; 31#L609-3true assume 1 == ~E_3~0;~E_3~0 := 2; 394#L614-3true assume 1 == ~E_4~0;~E_4~0 := 2; 175#L619-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 169#L388-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 423#L415-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 403#L416-1true start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 246#L824true assume !(0 == start_simulation_~tmp~3); 249#L824-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 170#L388-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 427#L415-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 269#L416-2true stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 410#L779true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 10#L786true stop_simulation_#res := stop_simulation_~__retres2~0; 64#L787true start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 287#L837true assume !(0 != start_simulation_~tmp___0~1); 105#L805-3true [2018-11-18 11:59:37,324 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:37,327 INFO L82 PathProgramCache]: Analyzing trace with hash 1553035642, now seen corresponding path program 1 times [2018-11-18 11:59:37,329 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:37,329 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:37,371 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:37,371 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:59:37,371 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:37,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:59:37,459 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:59:37,461 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:59:37,461 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 11:59:37,464 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 11:59:37,464 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:37,464 INFO L82 PathProgramCache]: Analyzing trace with hash 969640682, now seen corresponding path program 1 times [2018-11-18 11:59:37,464 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:37,464 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:37,465 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:37,465 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:59:37,465 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:37,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:59:37,485 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:59:37,485 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:59:37,485 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 11:59:37,491 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 11:59:37,505 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 11:59:37,506 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 11:59:37,508 INFO L87 Difference]: Start difference. First operand 445 states. Second operand 3 states. [2018-11-18 11:59:37,541 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:59:37,541 INFO L93 Difference]: Finished difference Result 443 states and 659 transitions. [2018-11-18 11:59:37,543 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 11:59:37,545 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 443 states and 659 transitions. [2018-11-18 11:59:37,549 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 370 [2018-11-18 11:59:37,555 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 443 states to 437 states and 653 transitions. [2018-11-18 11:59:37,559 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 437 [2018-11-18 11:59:37,560 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 437 [2018-11-18 11:59:37,560 INFO L73 IsDeterministic]: Start isDeterministic. Operand 437 states and 653 transitions. [2018-11-18 11:59:37,563 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:59:37,563 INFO L705 BuchiCegarLoop]: Abstraction has 437 states and 653 transitions. [2018-11-18 11:59:37,576 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 437 states and 653 transitions. [2018-11-18 11:59:37,601 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 437 to 437. [2018-11-18 11:59:37,602 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 437 states. [2018-11-18 11:59:37,604 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 437 states to 437 states and 653 transitions. [2018-11-18 11:59:37,604 INFO L728 BuchiCegarLoop]: Abstraction has 437 states and 653 transitions. [2018-11-18 11:59:37,605 INFO L608 BuchiCegarLoop]: Abstraction has 437 states and 653 transitions. [2018-11-18 11:59:37,605 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ [2018-11-18 11:59:37,605 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 437 states and 653 transitions. [2018-11-18 11:59:37,607 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 370 [2018-11-18 11:59:37,607 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:59:37,608 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:59:37,609 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:37,609 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:37,610 INFO L794 eck$LassoCheckResult]: Stem: 1263#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 1188#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1189#L768 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 1313#L348 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1139#L355 assume 1 == ~m_i~0;~m_st~0 := 0; 1140#L355-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1146#L360-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1029#L365-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1030#L370-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1112#L375-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1113#L516 assume !(0 == ~M_E~0); 1233#L516-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 953#L521-1 assume !(0 == ~T2_E~0); 954#L526-1 assume !(0 == ~T3_E~0); 1150#L531-1 assume !(0 == ~T4_E~0); 1151#L536-1 assume !(0 == ~E_M~0); 1047#L541-1 assume !(0 == ~E_1~0); 1048#L546-1 assume !(0 == ~E_2~0); 1120#L551-1 assume !(0 == ~E_3~0); 1005#L556-1 assume 0 == ~E_4~0;~E_4~0 := 1; 1006#L561-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1185#L252 assume 1 == ~m_pc~0; 1186#L253 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1167#L263 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1187#L264 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1254#L639 assume !(0 != activate_threads_~tmp~1); 1115#L639-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1116#L271 assume !(1 == ~t1_pc~0); 1300#L271-2 is_transmit1_triggered_~__retres1~1 := 0; 1302#L282 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1303#L283 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1328#L647 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1329#L647-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 962#L290 assume 1 == ~t2_pc~0; 963#L291 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 952#L301 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 964#L302 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1013#L655 assume !(0 != activate_threads_~tmp___1~0); 996#L655-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 997#L309 assume !(1 == ~t3_pc~0); 1034#L309-2 is_transmit3_triggered_~__retres1~3 := 0; 1035#L320 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1031#L321 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1032#L663 assume !(0 != activate_threads_~tmp___2~0); 1159#L663-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1160#L328 assume 1 == ~t4_pc~0; 1192#L329 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1193#L339 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1190#L340 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1191#L671 assume !(0 != activate_threads_~tmp___3~0); 1281#L671-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1043#L574 assume !(1 == ~M_E~0); 1044#L574-2 assume !(1 == ~T1_E~0); 1049#L579-1 assume !(1 == ~T2_E~0); 1117#L584-1 assume !(1 == ~T3_E~0); 999#L589-1 assume !(1 == ~T4_E~0); 1000#L594-1 assume !(1 == ~E_M~0); 904#L599-1 assume 1 == ~E_1~0;~E_1~0 := 2; 905#L604-1 assume !(1 == ~E_2~0); 977#L609-1 assume !(1 == ~E_3~0); 978#L614-1 assume !(1 == ~E_4~0); 1161#L619-1 assume { :end_inline_reset_delta_events } true; 1060#L805-3 [2018-11-18 11:59:37,610 INFO L796 eck$LassoCheckResult]: Loop: 1060#L805-3 assume true; 1053#L805-1 assume !false; 1054#L806 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 957#L491 assume true; 1308#L425-1 assume !false; 1309#L426 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1135#L388 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 968#L415 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1326#L416 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 1107#L430 assume !(0 != eval_~tmp~0); 1108#L506 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 1283#L348-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 1235#L516-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1236#L516-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 965#L521-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 966#L526-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1154#L531-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1155#L536-3 assume !(0 == ~E_M~0); 1051#L541-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1052#L546-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1104#L551-3 assume 0 == ~E_3~0;~E_3~0 := 1; 986#L556-3 assume 0 == ~E_4~0;~E_4~0 := 1; 987#L561-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1276#L252-18 assume 1 == ~m_pc~0; 1268#L253-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1204#L263-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1205#L264-6 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1081#L639-18 assume !(0 != activate_threads_~tmp~1); 1082#L639-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1087#L271-18 assume 1 == ~t1_pc~0; 1332#L272-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1292#L282-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1293#L283-6 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1245#L647-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1239#L647-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 899#L290-18 assume !(1 == ~t2_pc~0); 900#L290-20 is_transmit2_triggered_~__retres1~2 := 0; 916#L301-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 922#L302-6 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1022#L655-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1320#L655-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1057#L309-18 assume 1 == ~t3_pc~0; 1058#L310-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1063#L320-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1101#L321-6 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1134#L663-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1124#L663-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1125#L328-18 assume 1 == ~t4_pc~0; 1172#L329-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1173#L339-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1170#L340-6 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1171#L671-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1260#L671-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1050#L574-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1027#L574-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1028#L579-3 assume !(1 == ~T2_E~0); 1121#L584-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1008#L589-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1009#L594-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1024#L599-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1025#L604-3 assume 1 == ~E_2~0;~E_2~0 := 2; 949#L609-3 assume 1 == ~E_3~0;~E_3~0 := 2; 950#L614-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1149#L619-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1141#L388-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 972#L415-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1327#L416-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 1237#L824 assume !(0 == start_simulation_~tmp~3); 1238#L824-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1143#L388-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 943#L415-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1249#L416-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 1250#L779 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 912#L786 stop_simulation_#res := stop_simulation_~__retres2~0; 913#L787 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 1010#L837 assume !(0 != start_simulation_~tmp___0~1); 1060#L805-3 [2018-11-18 11:59:37,610 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:37,611 INFO L82 PathProgramCache]: Analyzing trace with hash 1119306556, now seen corresponding path program 1 times [2018-11-18 11:59:37,611 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:37,611 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:37,612 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:37,612 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:59:37,612 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:37,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:59:37,656 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:59:37,657 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:59:37,657 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 11:59:37,657 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 11:59:37,657 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:37,657 INFO L82 PathProgramCache]: Analyzing trace with hash 1810778070, now seen corresponding path program 1 times [2018-11-18 11:59:37,658 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:37,658 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:37,658 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:37,659 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:59:37,659 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:37,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:59:37,744 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:59:37,744 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:59:37,744 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 11:59:37,744 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 11:59:37,745 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 11:59:37,745 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 11:59:37,745 INFO L87 Difference]: Start difference. First operand 437 states and 653 transitions. cyclomatic complexity: 217 Second operand 3 states. [2018-11-18 11:59:37,757 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:59:37,758 INFO L93 Difference]: Finished difference Result 437 states and 652 transitions. [2018-11-18 11:59:37,767 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 11:59:37,768 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 437 states and 652 transitions. [2018-11-18 11:59:37,772 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 370 [2018-11-18 11:59:37,774 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 437 states to 437 states and 652 transitions. [2018-11-18 11:59:37,774 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 437 [2018-11-18 11:59:37,775 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 437 [2018-11-18 11:59:37,775 INFO L73 IsDeterministic]: Start isDeterministic. Operand 437 states and 652 transitions. [2018-11-18 11:59:37,776 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:59:37,776 INFO L705 BuchiCegarLoop]: Abstraction has 437 states and 652 transitions. [2018-11-18 11:59:37,777 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 437 states and 652 transitions. [2018-11-18 11:59:37,794 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 437 to 437. [2018-11-18 11:59:37,795 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 437 states. [2018-11-18 11:59:37,796 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 437 states to 437 states and 652 transitions. [2018-11-18 11:59:37,796 INFO L728 BuchiCegarLoop]: Abstraction has 437 states and 652 transitions. [2018-11-18 11:59:37,796 INFO L608 BuchiCegarLoop]: Abstraction has 437 states and 652 transitions. [2018-11-18 11:59:37,797 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ [2018-11-18 11:59:37,797 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 437 states and 652 transitions. [2018-11-18 11:59:37,799 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 370 [2018-11-18 11:59:37,799 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:59:37,799 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:59:37,800 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:37,800 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:37,801 INFO L794 eck$LassoCheckResult]: Stem: 2144#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 2069#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2070#L768 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 2194#L348 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2020#L355 assume 1 == ~m_i~0;~m_st~0 := 0; 2021#L355-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2027#L360-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1910#L365-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1911#L370-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1993#L375-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1994#L516 assume !(0 == ~M_E~0); 2114#L516-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1834#L521-1 assume !(0 == ~T2_E~0); 1835#L526-1 assume !(0 == ~T3_E~0); 2031#L531-1 assume !(0 == ~T4_E~0); 2032#L536-1 assume !(0 == ~E_M~0); 1928#L541-1 assume !(0 == ~E_1~0); 1929#L546-1 assume !(0 == ~E_2~0); 2001#L551-1 assume !(0 == ~E_3~0); 1886#L556-1 assume 0 == ~E_4~0;~E_4~0 := 1; 1887#L561-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2066#L252 assume 1 == ~m_pc~0; 2067#L253 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2048#L263 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2068#L264 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2135#L639 assume !(0 != activate_threads_~tmp~1); 1996#L639-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1997#L271 assume !(1 == ~t1_pc~0); 2181#L271-2 is_transmit1_triggered_~__retres1~1 := 0; 2183#L282 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2184#L283 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2209#L647 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2210#L647-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1843#L290 assume 1 == ~t2_pc~0; 1844#L291 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1833#L301 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1845#L302 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1894#L655 assume !(0 != activate_threads_~tmp___1~0); 1877#L655-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1878#L309 assume !(1 == ~t3_pc~0); 1915#L309-2 is_transmit3_triggered_~__retres1~3 := 0; 1916#L320 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1912#L321 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1913#L663 assume !(0 != activate_threads_~tmp___2~0); 2040#L663-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2041#L328 assume 1 == ~t4_pc~0; 2073#L329 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2074#L339 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2071#L340 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2072#L671 assume !(0 != activate_threads_~tmp___3~0); 2162#L671-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1924#L574 assume !(1 == ~M_E~0); 1925#L574-2 assume !(1 == ~T1_E~0); 1930#L579-1 assume !(1 == ~T2_E~0); 1998#L584-1 assume !(1 == ~T3_E~0); 1880#L589-1 assume !(1 == ~T4_E~0); 1881#L594-1 assume !(1 == ~E_M~0); 1785#L599-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1786#L604-1 assume !(1 == ~E_2~0); 1858#L609-1 assume !(1 == ~E_3~0); 1859#L614-1 assume !(1 == ~E_4~0); 2042#L619-1 assume { :end_inline_reset_delta_events } true; 1941#L805-3 [2018-11-18 11:59:37,801 INFO L796 eck$LassoCheckResult]: Loop: 1941#L805-3 assume true; 1934#L805-1 assume !false; 1935#L806 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 1838#L491 assume true; 2189#L425-1 assume !false; 2190#L426 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2016#L388 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1849#L415 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2207#L416 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 1988#L430 assume !(0 != eval_~tmp~0); 1989#L506 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 2164#L348-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 2116#L516-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2117#L516-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1846#L521-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1847#L526-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2035#L531-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2036#L536-3 assume !(0 == ~E_M~0); 1932#L541-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1933#L546-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1985#L551-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1867#L556-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1868#L561-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2157#L252-18 assume 1 == ~m_pc~0; 2149#L253-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2085#L263-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2086#L264-6 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1962#L639-18 assume !(0 != activate_threads_~tmp~1); 1963#L639-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1968#L271-18 assume 1 == ~t1_pc~0; 2213#L272-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2173#L282-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2174#L283-6 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2126#L647-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2120#L647-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1780#L290-18 assume !(1 == ~t2_pc~0); 1781#L290-20 is_transmit2_triggered_~__retres1~2 := 0; 1797#L301-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1803#L302-6 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1903#L655-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2201#L655-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1938#L309-18 assume 1 == ~t3_pc~0; 1939#L310-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1944#L320-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1982#L321-6 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2015#L663-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2005#L663-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2006#L328-18 assume 1 == ~t4_pc~0; 2053#L329-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2054#L339-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2051#L340-6 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2052#L671-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2141#L671-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1931#L574-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1908#L574-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1909#L579-3 assume !(1 == ~T2_E~0); 2002#L584-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1889#L589-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1890#L594-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1905#L599-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1906#L604-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1830#L609-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1831#L614-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2030#L619-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2022#L388-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1853#L415-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2208#L416-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 2118#L824 assume !(0 == start_simulation_~tmp~3); 2119#L824-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2024#L388-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1824#L415-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2130#L416-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 2131#L779 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1793#L786 stop_simulation_#res := stop_simulation_~__retres2~0; 1794#L787 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 1891#L837 assume !(0 != start_simulation_~tmp___0~1); 1941#L805-3 [2018-11-18 11:59:37,801 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:37,801 INFO L82 PathProgramCache]: Analyzing trace with hash 1078631806, now seen corresponding path program 1 times [2018-11-18 11:59:37,801 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:37,802 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:37,802 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:37,802 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:59:37,803 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:37,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:59:37,868 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:59:37,869 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:59:37,869 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 11:59:37,869 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 11:59:37,869 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:37,870 INFO L82 PathProgramCache]: Analyzing trace with hash 1810778070, now seen corresponding path program 2 times [2018-11-18 11:59:37,870 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:37,870 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:37,871 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:37,871 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:59:37,871 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:37,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:59:37,919 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:59:37,920 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:59:37,920 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 11:59:37,920 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 11:59:37,920 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 11:59:37,920 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 11:59:37,921 INFO L87 Difference]: Start difference. First operand 437 states and 652 transitions. cyclomatic complexity: 216 Second operand 3 states. [2018-11-18 11:59:37,942 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:59:37,942 INFO L93 Difference]: Finished difference Result 437 states and 651 transitions. [2018-11-18 11:59:37,946 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 11:59:37,947 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 437 states and 651 transitions. [2018-11-18 11:59:37,949 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 370 [2018-11-18 11:59:37,951 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 437 states to 437 states and 651 transitions. [2018-11-18 11:59:37,952 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 437 [2018-11-18 11:59:37,952 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 437 [2018-11-18 11:59:37,952 INFO L73 IsDeterministic]: Start isDeterministic. Operand 437 states and 651 transitions. [2018-11-18 11:59:37,953 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:59:37,953 INFO L705 BuchiCegarLoop]: Abstraction has 437 states and 651 transitions. [2018-11-18 11:59:37,954 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 437 states and 651 transitions. [2018-11-18 11:59:37,964 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 437 to 437. [2018-11-18 11:59:37,964 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 437 states. [2018-11-18 11:59:37,965 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 437 states to 437 states and 651 transitions. [2018-11-18 11:59:37,965 INFO L728 BuchiCegarLoop]: Abstraction has 437 states and 651 transitions. [2018-11-18 11:59:37,966 INFO L608 BuchiCegarLoop]: Abstraction has 437 states and 651 transitions. [2018-11-18 11:59:37,966 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ [2018-11-18 11:59:37,966 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 437 states and 651 transitions. [2018-11-18 11:59:37,968 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 370 [2018-11-18 11:59:37,968 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:59:37,968 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:59:37,969 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:37,969 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:37,970 INFO L794 eck$LassoCheckResult]: Stem: 3025#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 2950#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2951#L768 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 3075#L348 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2901#L355 assume 1 == ~m_i~0;~m_st~0 := 0; 2902#L355-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2908#L360-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2791#L365-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2792#L370-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2874#L375-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2875#L516 assume !(0 == ~M_E~0); 2995#L516-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2715#L521-1 assume !(0 == ~T2_E~0); 2716#L526-1 assume !(0 == ~T3_E~0); 2912#L531-1 assume !(0 == ~T4_E~0); 2913#L536-1 assume !(0 == ~E_M~0); 2809#L541-1 assume !(0 == ~E_1~0); 2810#L546-1 assume !(0 == ~E_2~0); 2882#L551-1 assume !(0 == ~E_3~0); 2767#L556-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2768#L561-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2947#L252 assume 1 == ~m_pc~0; 2948#L253 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2929#L263 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2949#L264 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3016#L639 assume !(0 != activate_threads_~tmp~1); 2877#L639-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2878#L271 assume !(1 == ~t1_pc~0); 3062#L271-2 is_transmit1_triggered_~__retres1~1 := 0; 3064#L282 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3065#L283 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3090#L647 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3091#L647-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2724#L290 assume 1 == ~t2_pc~0; 2725#L291 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2714#L301 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2726#L302 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2775#L655 assume !(0 != activate_threads_~tmp___1~0); 2758#L655-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2759#L309 assume !(1 == ~t3_pc~0); 2796#L309-2 is_transmit3_triggered_~__retres1~3 := 0; 2797#L320 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2793#L321 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2794#L663 assume !(0 != activate_threads_~tmp___2~0); 2921#L663-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2922#L328 assume 1 == ~t4_pc~0; 2954#L329 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2955#L339 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2952#L340 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2953#L671 assume !(0 != activate_threads_~tmp___3~0); 3043#L671-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2805#L574 assume !(1 == ~M_E~0); 2806#L574-2 assume !(1 == ~T1_E~0); 2811#L579-1 assume !(1 == ~T2_E~0); 2879#L584-1 assume !(1 == ~T3_E~0); 2761#L589-1 assume !(1 == ~T4_E~0); 2762#L594-1 assume !(1 == ~E_M~0); 2666#L599-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2667#L604-1 assume !(1 == ~E_2~0); 2739#L609-1 assume !(1 == ~E_3~0); 2740#L614-1 assume !(1 == ~E_4~0); 2923#L619-1 assume { :end_inline_reset_delta_events } true; 2822#L805-3 [2018-11-18 11:59:37,970 INFO L796 eck$LassoCheckResult]: Loop: 2822#L805-3 assume true; 2815#L805-1 assume !false; 2816#L806 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 2719#L491 assume true; 3070#L425-1 assume !false; 3071#L426 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2897#L388 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 2730#L415 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3088#L416 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 2869#L430 assume !(0 != eval_~tmp~0); 2870#L506 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 3045#L348-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 2997#L516-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2998#L516-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2727#L521-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2728#L526-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2916#L531-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2917#L536-3 assume !(0 == ~E_M~0); 2813#L541-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2814#L546-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2866#L551-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2748#L556-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2749#L561-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3038#L252-18 assume 1 == ~m_pc~0; 3030#L253-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2966#L263-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2967#L264-6 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2843#L639-18 assume !(0 != activate_threads_~tmp~1); 2844#L639-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2849#L271-18 assume 1 == ~t1_pc~0; 3094#L272-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3054#L282-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3055#L283-6 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3007#L647-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3001#L647-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2661#L290-18 assume !(1 == ~t2_pc~0); 2662#L290-20 is_transmit2_triggered_~__retres1~2 := 0; 2678#L301-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2684#L302-6 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2784#L655-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3082#L655-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2819#L309-18 assume 1 == ~t3_pc~0; 2820#L310-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2825#L320-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2863#L321-6 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2896#L663-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2886#L663-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2887#L328-18 assume 1 == ~t4_pc~0; 2934#L329-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2935#L339-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2932#L340-6 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2933#L671-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 3022#L671-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2812#L574-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2789#L574-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2790#L579-3 assume !(1 == ~T2_E~0); 2883#L584-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2770#L589-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2771#L594-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2786#L599-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2787#L604-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2711#L609-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2712#L614-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2911#L619-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2903#L388-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 2734#L415-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3089#L416-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 2999#L824 assume !(0 == start_simulation_~tmp~3); 3000#L824-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2905#L388-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 2705#L415-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3011#L416-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 3012#L779 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2674#L786 stop_simulation_#res := stop_simulation_~__retres2~0; 2675#L787 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 2772#L837 assume !(0 != start_simulation_~tmp___0~1); 2822#L805-3 [2018-11-18 11:59:37,970 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:37,970 INFO L82 PathProgramCache]: Analyzing trace with hash -308153604, now seen corresponding path program 1 times [2018-11-18 11:59:37,970 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:37,970 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:37,971 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:37,971 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 11:59:37,971 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:37,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:59:38,003 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:59:38,003 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:59:38,003 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 11:59:38,003 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 11:59:38,004 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:38,004 INFO L82 PathProgramCache]: Analyzing trace with hash 1810778070, now seen corresponding path program 3 times [2018-11-18 11:59:38,004 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:38,004 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:38,005 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:38,005 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:59:38,005 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:38,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:59:38,069 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:59:38,069 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:59:38,069 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 11:59:38,069 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 11:59:38,070 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 11:59:38,070 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 11:59:38,070 INFO L87 Difference]: Start difference. First operand 437 states and 651 transitions. cyclomatic complexity: 215 Second operand 3 states. [2018-11-18 11:59:38,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:59:38,079 INFO L93 Difference]: Finished difference Result 437 states and 650 transitions. [2018-11-18 11:59:38,080 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 11:59:38,080 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 437 states and 650 transitions. [2018-11-18 11:59:38,082 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 370 [2018-11-18 11:59:38,085 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 437 states to 437 states and 650 transitions. [2018-11-18 11:59:38,085 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 437 [2018-11-18 11:59:38,086 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 437 [2018-11-18 11:59:38,086 INFO L73 IsDeterministic]: Start isDeterministic. Operand 437 states and 650 transitions. [2018-11-18 11:59:38,087 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:59:38,087 INFO L705 BuchiCegarLoop]: Abstraction has 437 states and 650 transitions. [2018-11-18 11:59:38,089 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 437 states and 650 transitions. [2018-11-18 11:59:38,094 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 437 to 437. [2018-11-18 11:59:38,094 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 437 states. [2018-11-18 11:59:38,096 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 437 states to 437 states and 650 transitions. [2018-11-18 11:59:38,096 INFO L728 BuchiCegarLoop]: Abstraction has 437 states and 650 transitions. [2018-11-18 11:59:38,096 INFO L608 BuchiCegarLoop]: Abstraction has 437 states and 650 transitions. [2018-11-18 11:59:38,096 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ [2018-11-18 11:59:38,097 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 437 states and 650 transitions. [2018-11-18 11:59:38,098 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 370 [2018-11-18 11:59:38,098 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:59:38,099 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:59:38,101 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:38,101 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:38,102 INFO L794 eck$LassoCheckResult]: Stem: 3906#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 3831#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3832#L768 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 3956#L348 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3782#L355 assume 1 == ~m_i~0;~m_st~0 := 0; 3783#L355-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3789#L360-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3672#L365-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3673#L370-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3755#L375-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3756#L516 assume !(0 == ~M_E~0); 3876#L516-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3596#L521-1 assume !(0 == ~T2_E~0); 3597#L526-1 assume !(0 == ~T3_E~0); 3793#L531-1 assume !(0 == ~T4_E~0); 3794#L536-1 assume !(0 == ~E_M~0); 3690#L541-1 assume !(0 == ~E_1~0); 3691#L546-1 assume !(0 == ~E_2~0); 3763#L551-1 assume !(0 == ~E_3~0); 3648#L556-1 assume 0 == ~E_4~0;~E_4~0 := 1; 3649#L561-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3828#L252 assume 1 == ~m_pc~0; 3829#L253 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3810#L263 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3830#L264 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3897#L639 assume !(0 != activate_threads_~tmp~1); 3758#L639-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3759#L271 assume !(1 == ~t1_pc~0); 3943#L271-2 is_transmit1_triggered_~__retres1~1 := 0; 3945#L282 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3946#L283 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3971#L647 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3972#L647-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3605#L290 assume 1 == ~t2_pc~0; 3606#L291 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3595#L301 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3607#L302 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3656#L655 assume !(0 != activate_threads_~tmp___1~0); 3639#L655-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3640#L309 assume !(1 == ~t3_pc~0); 3677#L309-2 is_transmit3_triggered_~__retres1~3 := 0; 3678#L320 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3674#L321 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3675#L663 assume !(0 != activate_threads_~tmp___2~0); 3802#L663-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3803#L328 assume 1 == ~t4_pc~0; 3835#L329 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3836#L339 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3833#L340 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3834#L671 assume !(0 != activate_threads_~tmp___3~0); 3924#L671-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3686#L574 assume !(1 == ~M_E~0); 3687#L574-2 assume !(1 == ~T1_E~0); 3692#L579-1 assume !(1 == ~T2_E~0); 3760#L584-1 assume !(1 == ~T3_E~0); 3642#L589-1 assume !(1 == ~T4_E~0); 3643#L594-1 assume !(1 == ~E_M~0); 3547#L599-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3548#L604-1 assume !(1 == ~E_2~0); 3620#L609-1 assume !(1 == ~E_3~0); 3621#L614-1 assume !(1 == ~E_4~0); 3804#L619-1 assume { :end_inline_reset_delta_events } true; 3703#L805-3 [2018-11-18 11:59:38,102 INFO L796 eck$LassoCheckResult]: Loop: 3703#L805-3 assume true; 3696#L805-1 assume !false; 3697#L806 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 3600#L491 assume true; 3951#L425-1 assume !false; 3952#L426 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3778#L388 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3611#L415 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3969#L416 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 3750#L430 assume !(0 != eval_~tmp~0); 3751#L506 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 3926#L348-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 3878#L516-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3879#L516-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3608#L521-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3609#L526-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3797#L531-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3798#L536-3 assume !(0 == ~E_M~0); 3694#L541-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3695#L546-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3747#L551-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3629#L556-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3630#L561-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3919#L252-18 assume 1 == ~m_pc~0; 3911#L253-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3847#L263-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3848#L264-6 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3724#L639-18 assume !(0 != activate_threads_~tmp~1); 3725#L639-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3730#L271-18 assume 1 == ~t1_pc~0; 3975#L272-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3935#L282-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3936#L283-6 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3888#L647-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3882#L647-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3542#L290-18 assume !(1 == ~t2_pc~0); 3543#L290-20 is_transmit2_triggered_~__retres1~2 := 0; 3559#L301-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3565#L302-6 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3665#L655-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3963#L655-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3700#L309-18 assume 1 == ~t3_pc~0; 3701#L310-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3706#L320-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3744#L321-6 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3777#L663-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3767#L663-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3768#L328-18 assume 1 == ~t4_pc~0; 3815#L329-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3816#L339-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3813#L340-6 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3814#L671-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 3903#L671-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3693#L574-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3670#L574-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3671#L579-3 assume !(1 == ~T2_E~0); 3764#L584-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3651#L589-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3652#L594-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3667#L599-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3668#L604-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3592#L609-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3593#L614-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3792#L619-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3784#L388-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3615#L415-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3970#L416-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 3880#L824 assume !(0 == start_simulation_~tmp~3); 3881#L824-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3786#L388-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3586#L415-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3892#L416-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 3893#L779 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3555#L786 stop_simulation_#res := stop_simulation_~__retres2~0; 3556#L787 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 3653#L837 assume !(0 != start_simulation_~tmp___0~1); 3703#L805-3 [2018-11-18 11:59:38,102 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:38,102 INFO L82 PathProgramCache]: Analyzing trace with hash -1184172610, now seen corresponding path program 1 times [2018-11-18 11:59:38,103 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:38,103 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:38,103 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:38,103 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 11:59:38,104 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:38,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:59:38,199 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:59:38,200 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:59:38,200 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 11:59:38,200 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 11:59:38,200 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:38,201 INFO L82 PathProgramCache]: Analyzing trace with hash 1810778070, now seen corresponding path program 4 times [2018-11-18 11:59:38,201 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:38,201 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:38,201 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:38,202 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:59:38,202 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:38,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:59:38,244 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:59:38,244 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:59:38,244 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 11:59:38,245 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 11:59:38,245 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 11:59:38,245 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 11:59:38,245 INFO L87 Difference]: Start difference. First operand 437 states and 650 transitions. cyclomatic complexity: 214 Second operand 3 states. [2018-11-18 11:59:38,320 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:59:38,320 INFO L93 Difference]: Finished difference Result 437 states and 645 transitions. [2018-11-18 11:59:38,320 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 11:59:38,320 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 437 states and 645 transitions. [2018-11-18 11:59:38,323 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 370 [2018-11-18 11:59:38,325 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 437 states to 437 states and 645 transitions. [2018-11-18 11:59:38,325 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 437 [2018-11-18 11:59:38,325 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 437 [2018-11-18 11:59:38,325 INFO L73 IsDeterministic]: Start isDeterministic. Operand 437 states and 645 transitions. [2018-11-18 11:59:38,326 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:59:38,326 INFO L705 BuchiCegarLoop]: Abstraction has 437 states and 645 transitions. [2018-11-18 11:59:38,327 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 437 states and 645 transitions. [2018-11-18 11:59:38,331 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 437 to 437. [2018-11-18 11:59:38,331 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 437 states. [2018-11-18 11:59:38,332 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 437 states to 437 states and 645 transitions. [2018-11-18 11:59:38,333 INFO L728 BuchiCegarLoop]: Abstraction has 437 states and 645 transitions. [2018-11-18 11:59:38,333 INFO L608 BuchiCegarLoop]: Abstraction has 437 states and 645 transitions. [2018-11-18 11:59:38,333 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ [2018-11-18 11:59:38,333 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 437 states and 645 transitions. [2018-11-18 11:59:38,334 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 370 [2018-11-18 11:59:38,334 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:59:38,335 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:59:38,335 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:38,336 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:38,336 INFO L794 eck$LassoCheckResult]: Stem: 4788#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 4712#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 4713#L768 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 4839#L348 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4665#L355 assume 1 == ~m_i~0;~m_st~0 := 0; 4666#L355-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4670#L360-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4553#L365-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4554#L370-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4637#L375-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4638#L516 assume !(0 == ~M_E~0); 4757#L516-2 assume !(0 == ~T1_E~0); 4478#L521-1 assume !(0 == ~T2_E~0); 4479#L526-1 assume !(0 == ~T3_E~0); 4675#L531-1 assume !(0 == ~T4_E~0); 4676#L536-1 assume !(0 == ~E_M~0); 4571#L541-1 assume !(0 == ~E_1~0); 4572#L546-1 assume !(0 == ~E_2~0); 4644#L551-1 assume !(0 == ~E_3~0); 4529#L556-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4530#L561-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4709#L252 assume 1 == ~m_pc~0; 4710#L253 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4691#L263 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4711#L264 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 4778#L639 assume !(0 != activate_threads_~tmp~1); 4639#L639-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4640#L271 assume !(1 == ~t1_pc~0); 4824#L271-2 is_transmit1_triggered_~__retres1~1 := 0; 4826#L282 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4827#L283 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 4852#L647 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4853#L647-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4486#L290 assume 1 == ~t2_pc~0; 4487#L291 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4476#L301 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4488#L302 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4539#L655 assume !(0 != activate_threads_~tmp___1~0); 4521#L655-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4522#L309 assume !(1 == ~t3_pc~0); 4558#L309-2 is_transmit3_triggered_~__retres1~3 := 0; 4559#L320 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4555#L321 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4556#L663 assume !(0 != activate_threads_~tmp___2~0); 4683#L663-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4684#L328 assume 1 == ~t4_pc~0; 4716#L329 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4717#L339 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4714#L340 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4715#L671 assume !(0 != activate_threads_~tmp___3~0); 4805#L671-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4569#L574 assume !(1 == ~M_E~0); 4570#L574-2 assume !(1 == ~T1_E~0); 4573#L579-1 assume !(1 == ~T2_E~0); 4641#L584-1 assume !(1 == ~T3_E~0); 4527#L589-1 assume !(1 == ~T4_E~0); 4528#L594-1 assume !(1 == ~E_M~0); 4428#L599-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4429#L604-1 assume !(1 == ~E_2~0); 4501#L609-1 assume !(1 == ~E_3~0); 4502#L614-1 assume !(1 == ~E_4~0); 4685#L619-1 assume { :end_inline_reset_delta_events } true; 4586#L805-3 [2018-11-18 11:59:38,336 INFO L796 eck$LassoCheckResult]: Loop: 4586#L805-3 assume true; 4579#L805-1 assume !false; 4580#L806 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 4481#L491 assume true; 4832#L425-1 assume !false; 4833#L426 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 4659#L388 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 4492#L415 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 4850#L416 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 4631#L430 assume !(0 != eval_~tmp~0); 4632#L506 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 4807#L348-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 4759#L516-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4760#L516-5 assume !(0 == ~T1_E~0); 4489#L521-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4490#L526-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4678#L531-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4679#L536-3 assume !(0 == ~E_M~0); 4575#L541-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4576#L546-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4627#L551-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4510#L556-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4511#L561-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4800#L252-18 assume 1 == ~m_pc~0; 4791#L253-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4728#L263-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4729#L264-6 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 4605#L639-18 assume !(0 != activate_threads_~tmp~1); 4606#L639-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4611#L271-18 assume 1 == ~t1_pc~0; 4856#L272-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4816#L282-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4817#L283-6 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 4769#L647-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4763#L647-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4423#L290-18 assume !(1 == ~t2_pc~0); 4424#L290-20 is_transmit2_triggered_~__retres1~2 := 0; 4440#L301-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4446#L302-6 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4546#L655-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4844#L655-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4581#L309-18 assume 1 == ~t3_pc~0; 4582#L310-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4587#L320-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4625#L321-6 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4658#L663-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4648#L663-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4649#L328-18 assume 1 == ~t4_pc~0; 4696#L329-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4697#L339-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4694#L340-6 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4695#L671-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 4784#L671-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4574#L574-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4551#L574-5 assume !(1 == ~T1_E~0); 4552#L579-3 assume !(1 == ~T2_E~0); 4645#L584-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4532#L589-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4533#L594-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4548#L599-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4549#L604-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4473#L609-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4474#L614-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4673#L619-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 4663#L388-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 4496#L415-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 4851#L416-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 4761#L824 assume !(0 == start_simulation_~tmp~3); 4762#L824-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 4667#L388-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 4467#L415-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 4772#L416-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 4773#L779 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4436#L786 stop_simulation_#res := stop_simulation_~__retres2~0; 4437#L787 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 4534#L837 assume !(0 != start_simulation_~tmp___0~1); 4586#L805-3 [2018-11-18 11:59:38,336 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:38,336 INFO L82 PathProgramCache]: Analyzing trace with hash 1082208576, now seen corresponding path program 1 times [2018-11-18 11:59:38,337 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:38,337 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:38,337 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:38,337 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 11:59:38,337 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:38,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:59:38,387 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:59:38,387 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:59:38,387 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 11:59:38,387 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 11:59:38,388 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:38,388 INFO L82 PathProgramCache]: Analyzing trace with hash 1612236182, now seen corresponding path program 1 times [2018-11-18 11:59:38,388 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:38,388 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:38,389 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:38,389 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:59:38,389 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:38,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:59:38,437 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:59:38,437 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:59:38,438 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 11:59:38,438 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 11:59:38,438 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 11:59:38,438 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 11:59:38,438 INFO L87 Difference]: Start difference. First operand 437 states and 645 transitions. cyclomatic complexity: 209 Second operand 3 states. [2018-11-18 11:59:38,562 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:59:38,562 INFO L93 Difference]: Finished difference Result 437 states and 633 transitions. [2018-11-18 11:59:38,563 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 11:59:38,563 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 437 states and 633 transitions. [2018-11-18 11:59:38,565 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 370 [2018-11-18 11:59:38,567 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 437 states to 437 states and 633 transitions. [2018-11-18 11:59:38,567 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 437 [2018-11-18 11:59:38,568 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 437 [2018-11-18 11:59:38,568 INFO L73 IsDeterministic]: Start isDeterministic. Operand 437 states and 633 transitions. [2018-11-18 11:59:38,569 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:59:38,569 INFO L705 BuchiCegarLoop]: Abstraction has 437 states and 633 transitions. [2018-11-18 11:59:38,569 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 437 states and 633 transitions. [2018-11-18 11:59:38,574 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 437 to 437. [2018-11-18 11:59:38,575 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 437 states. [2018-11-18 11:59:38,576 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 437 states to 437 states and 633 transitions. [2018-11-18 11:59:38,576 INFO L728 BuchiCegarLoop]: Abstraction has 437 states and 633 transitions. [2018-11-18 11:59:38,576 INFO L608 BuchiCegarLoop]: Abstraction has 437 states and 633 transitions. [2018-11-18 11:59:38,576 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ [2018-11-18 11:59:38,576 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 437 states and 633 transitions. [2018-11-18 11:59:38,578 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 370 [2018-11-18 11:59:38,578 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:59:38,578 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:59:38,579 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:38,579 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:38,580 INFO L794 eck$LassoCheckResult]: Stem: 5669#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 5590#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 5591#L768 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 5718#L348 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5546#L355 assume 1 == ~m_i~0;~m_st~0 := 0; 5547#L355-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5551#L360-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5434#L365-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5435#L370-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5517#L375-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5518#L516 assume !(0 == ~M_E~0); 5631#L516-2 assume !(0 == ~T1_E~0); 5358#L521-1 assume !(0 == ~T2_E~0); 5359#L526-1 assume !(0 == ~T3_E~0); 5556#L531-1 assume !(0 == ~T4_E~0); 5557#L536-1 assume !(0 == ~E_M~0); 5452#L541-1 assume !(0 == ~E_1~0); 5453#L546-1 assume !(0 == ~E_2~0); 5525#L551-1 assume !(0 == ~E_3~0); 5410#L556-1 assume !(0 == ~E_4~0); 5411#L561-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5587#L252 assume 1 == ~m_pc~0; 5588#L253 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 5571#L263 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5589#L264 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 5659#L639 assume !(0 != activate_threads_~tmp~1); 5520#L639-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5521#L271 assume !(1 == ~t1_pc~0); 5705#L271-2 is_transmit1_triggered_~__retres1~1 := 0; 5707#L282 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5708#L283 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5733#L647 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5734#L647-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5367#L290 assume 1 == ~t2_pc~0; 5368#L291 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5357#L301 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5369#L302 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5420#L655 assume !(0 != activate_threads_~tmp___1~0); 5402#L655-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5403#L309 assume !(1 == ~t3_pc~0); 5439#L309-2 is_transmit3_triggered_~__retres1~3 := 0; 5440#L320 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5436#L321 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5437#L663 assume !(0 != activate_threads_~tmp___2~0); 5564#L663-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5565#L328 assume !(1 == ~t4_pc~0); 5595#L328-2 is_transmit4_triggered_~__retres1~4 := 0; 5655#L339 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5592#L340 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5593#L671 assume !(0 != activate_threads_~tmp___3~0); 5686#L671-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5450#L574 assume !(1 == ~M_E~0); 5451#L574-2 assume !(1 == ~T1_E~0); 5454#L579-1 assume !(1 == ~T2_E~0); 5522#L584-1 assume !(1 == ~T3_E~0); 5406#L589-1 assume !(1 == ~T4_E~0); 5407#L594-1 assume !(1 == ~E_M~0); 5309#L599-1 assume 1 == ~E_1~0;~E_1~0 := 2; 5310#L604-1 assume !(1 == ~E_2~0); 5382#L609-1 assume !(1 == ~E_3~0); 5383#L614-1 assume !(1 == ~E_4~0); 5566#L619-1 assume { :end_inline_reset_delta_events } true; 5467#L805-3 [2018-11-18 11:59:38,580 INFO L796 eck$LassoCheckResult]: Loop: 5467#L805-3 assume true; 5460#L805-1 assume !false; 5461#L806 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 5362#L491 assume true; 5713#L425-1 assume !false; 5714#L426 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 5540#L388 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 5373#L415 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 5731#L416 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 5512#L430 assume !(0 != eval_~tmp~0); 5513#L506 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 5688#L348-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 5633#L516-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5634#L516-5 assume !(0 == ~T1_E~0); 5370#L521-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5371#L526-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5559#L531-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5560#L536-3 assume !(0 == ~E_M~0); 5456#L541-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5457#L546-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5509#L551-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5391#L556-3 assume !(0 == ~E_4~0); 5392#L561-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5681#L252-18 assume 1 == ~m_pc~0; 5673#L253-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 5606#L263-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5607#L264-6 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 5488#L639-18 assume !(0 != activate_threads_~tmp~1); 5489#L639-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5492#L271-18 assume 1 == ~t1_pc~0; 5737#L272-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5697#L282-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5698#L283-6 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5649#L647-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5640#L647-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5304#L290-18 assume !(1 == ~t2_pc~0); 5305#L290-20 is_transmit2_triggered_~__retres1~2 := 0; 5321#L301-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5327#L302-6 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5427#L655-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5725#L655-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5462#L309-18 assume 1 == ~t3_pc~0; 5463#L310-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5468#L320-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5505#L321-6 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5539#L663-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5529#L663-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5530#L328-18 assume !(1 == ~t4_pc~0); 5577#L328-20 is_transmit4_triggered_~__retres1~4 := 0; 5635#L339-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5572#L340-6 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5573#L671-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5665#L671-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5455#L574-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5432#L574-5 assume !(1 == ~T1_E~0); 5433#L579-3 assume !(1 == ~T2_E~0); 5526#L584-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5412#L589-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5413#L594-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5429#L599-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5430#L604-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5354#L609-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5355#L614-3 assume !(1 == ~E_4~0); 5554#L619-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 5544#L388-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 5377#L415-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 5732#L416-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 5637#L824 assume !(0 == start_simulation_~tmp~3); 5638#L824-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 5548#L388-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 5348#L415-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 5650#L416-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 5651#L779 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5317#L786 stop_simulation_#res := stop_simulation_~__retres2~0; 5318#L787 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 5415#L837 assume !(0 != start_simulation_~tmp___0~1); 5467#L805-3 [2018-11-18 11:59:38,580 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:38,580 INFO L82 PathProgramCache]: Analyzing trace with hash -1995156477, now seen corresponding path program 1 times [2018-11-18 11:59:38,580 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:38,580 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:38,581 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:38,581 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:59:38,581 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:38,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:59:38,630 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:59:38,631 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:59:38,631 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 11:59:38,631 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 11:59:38,631 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:38,632 INFO L82 PathProgramCache]: Analyzing trace with hash 1016229655, now seen corresponding path program 1 times [2018-11-18 11:59:38,632 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:38,632 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:38,632 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:38,633 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:59:38,633 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:38,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:59:38,672 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:59:38,673 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:59:38,673 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 11:59:38,673 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 11:59:38,673 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 11:59:38,673 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 11:59:38,674 INFO L87 Difference]: Start difference. First operand 437 states and 633 transitions. cyclomatic complexity: 197 Second operand 3 states. [2018-11-18 11:59:38,865 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:59:38,865 INFO L93 Difference]: Finished difference Result 792 states and 1132 transitions. [2018-11-18 11:59:38,866 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 11:59:38,866 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 792 states and 1132 transitions. [2018-11-18 11:59:38,869 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 724 [2018-11-18 11:59:38,872 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 792 states to 792 states and 1132 transitions. [2018-11-18 11:59:38,872 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 792 [2018-11-18 11:59:38,872 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 792 [2018-11-18 11:59:38,873 INFO L73 IsDeterministic]: Start isDeterministic. Operand 792 states and 1132 transitions. [2018-11-18 11:59:38,874 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:59:38,874 INFO L705 BuchiCegarLoop]: Abstraction has 792 states and 1132 transitions. [2018-11-18 11:59:38,875 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 792 states and 1132 transitions. [2018-11-18 11:59:38,888 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 792 to 758. [2018-11-18 11:59:38,888 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 758 states. [2018-11-18 11:59:38,890 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 758 states to 758 states and 1086 transitions. [2018-11-18 11:59:38,890 INFO L728 BuchiCegarLoop]: Abstraction has 758 states and 1086 transitions. [2018-11-18 11:59:38,890 INFO L608 BuchiCegarLoop]: Abstraction has 758 states and 1086 transitions. [2018-11-18 11:59:38,890 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ [2018-11-18 11:59:38,890 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 758 states and 1086 transitions. [2018-11-18 11:59:38,893 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 690 [2018-11-18 11:59:38,893 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:59:38,893 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:59:38,894 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:38,895 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:38,895 INFO L794 eck$LassoCheckResult]: Stem: 6915#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 6829#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 6830#L768 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 6975#L348 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6783#L355 assume 1 == ~m_i~0;~m_st~0 := 0; 6784#L355-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6789#L360-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6670#L365-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6671#L370-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6755#L375-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6756#L516 assume !(0 == ~M_E~0); 6869#L516-2 assume !(0 == ~T1_E~0); 6595#L521-1 assume !(0 == ~T2_E~0); 6596#L526-1 assume !(0 == ~T3_E~0); 6794#L531-1 assume !(0 == ~T4_E~0); 6795#L536-1 assume !(0 == ~E_M~0); 6688#L541-1 assume !(0 == ~E_1~0); 6689#L546-1 assume !(0 == ~E_2~0); 6762#L551-1 assume !(0 == ~E_3~0); 6646#L556-1 assume !(0 == ~E_4~0); 6647#L561-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6827#L252 assume !(1 == ~m_pc~0); 6809#L252-2 is_master_triggered_~__retres1~0 := 0; 6810#L263 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6828#L264 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 6900#L639 assume !(0 != activate_threads_~tmp~1); 6757#L639-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6758#L271 assume !(1 == ~t1_pc~0); 6961#L271-2 is_transmit1_triggered_~__retres1~1 := 0; 6963#L282 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6964#L283 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 6990#L647 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6991#L647-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6603#L290 assume 1 == ~t2_pc~0; 6604#L291 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6593#L301 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6607#L302 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 6656#L655 assume !(0 != activate_threads_~tmp___1~0); 6638#L655-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6639#L309 assume !(1 == ~t3_pc~0); 6675#L309-2 is_transmit3_triggered_~__retres1~3 := 0; 6676#L320 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6672#L321 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 6673#L663 assume !(0 != activate_threads_~tmp___2~0); 6802#L663-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6803#L328 assume !(1 == ~t4_pc~0); 6834#L328-2 is_transmit4_triggered_~__retres1~4 := 0; 6895#L339 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6831#L340 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6832#L671 assume !(0 != activate_threads_~tmp___3~0); 6935#L671-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6686#L574 assume !(1 == ~M_E~0); 6687#L574-2 assume !(1 == ~T1_E~0); 6690#L579-1 assume !(1 == ~T2_E~0); 6759#L584-1 assume !(1 == ~T3_E~0); 6644#L589-1 assume !(1 == ~T4_E~0); 6645#L594-1 assume !(1 == ~E_M~0); 6545#L599-1 assume 1 == ~E_1~0;~E_1~0 := 2; 6546#L604-1 assume !(1 == ~E_2~0); 6618#L609-1 assume !(1 == ~E_3~0); 6619#L614-1 assume !(1 == ~E_4~0); 6804#L619-1 assume { :end_inline_reset_delta_events } true; 6805#L805-3 [2018-11-18 11:59:38,895 INFO L796 eck$LassoCheckResult]: Loop: 6805#L805-3 assume true; 7040#L805-1 assume !false; 7031#L806 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 7028#L491 assume true; 7026#L425-1 assume !false; 7024#L426 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 7017#L388 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 7013#L415 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 7011#L416 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 7009#L430 assume !(0 != eval_~tmp~0); 6937#L506 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 6938#L348-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 6871#L516-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6872#L516-5 assume !(0 == ~T1_E~0); 6605#L521-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6606#L526-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6797#L531-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6798#L536-3 assume !(0 == ~E_M~0); 6692#L541-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6693#L546-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6745#L551-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6629#L556-3 assume !(0 == ~E_4~0); 6630#L561-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6928#L252-18 assume !(1 == ~m_pc~0); 6943#L252-20 is_master_triggered_~__retres1~0 := 0; 7182#L263-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7180#L264-6 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 7177#L639-18 assume !(0 != activate_threads_~tmp~1); 7175#L639-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7173#L271-18 assume 1 == ~t1_pc~0; 7170#L272-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 7168#L282-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7166#L283-6 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 7163#L647-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7161#L647-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7159#L290-18 assume !(1 == ~t2_pc~0); 7156#L290-20 is_transmit2_triggered_~__retres1~2 := 0; 7154#L301-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7152#L302-6 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 7149#L655-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7147#L655-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7145#L309-18 assume 1 == ~t3_pc~0; 7142#L310-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 7140#L320-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7137#L321-6 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7135#L663-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 7133#L663-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7129#L328-18 assume !(1 == ~t4_pc~0); 7127#L328-20 is_transmit4_triggered_~__retres1~4 := 0; 7125#L339-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7123#L340-6 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7121#L671-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 7119#L671-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7117#L574-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7115#L574-5 assume !(1 == ~T1_E~0); 7113#L579-3 assume !(1 == ~T2_E~0); 7111#L584-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7109#L589-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7107#L594-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7106#L599-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7105#L604-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7104#L609-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7102#L614-3 assume !(1 == ~E_4~0); 7100#L619-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 7085#L388-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 7083#L415-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 7080#L416-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 7077#L824 assume !(0 == start_simulation_~tmp~3); 7074#L824-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 7060#L388-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 7055#L415-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 7052#L416-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 7050#L779 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7048#L786 stop_simulation_#res := stop_simulation_~__retres2~0; 7046#L787 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 7044#L837 assume !(0 != start_simulation_~tmp___0~1); 6805#L805-3 [2018-11-18 11:59:38,896 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:38,896 INFO L82 PathProgramCache]: Analyzing trace with hash 1814636100, now seen corresponding path program 1 times [2018-11-18 11:59:38,896 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:38,896 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:38,897 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:38,897 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:59:38,897 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:38,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:59:38,994 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:59:38,995 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:59:38,995 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 11:59:38,995 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 11:59:38,995 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:38,995 INFO L82 PathProgramCache]: Analyzing trace with hash 742451160, now seen corresponding path program 1 times [2018-11-18 11:59:38,995 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:38,996 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:38,996 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:38,996 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:59:38,996 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:39,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:59:39,065 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:59:39,065 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:59:39,065 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 11:59:39,065 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 11:59:39,066 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 11:59:39,066 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 11:59:39,066 INFO L87 Difference]: Start difference. First operand 758 states and 1086 transitions. cyclomatic complexity: 330 Second operand 3 states. [2018-11-18 11:59:39,457 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:59:39,458 INFO L93 Difference]: Finished difference Result 1363 states and 1938 transitions. [2018-11-18 11:59:39,459 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 11:59:39,459 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1363 states and 1938 transitions. [2018-11-18 11:59:39,465 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1290 [2018-11-18 11:59:39,470 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1363 states to 1363 states and 1938 transitions. [2018-11-18 11:59:39,470 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1363 [2018-11-18 11:59:39,471 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1363 [2018-11-18 11:59:39,471 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1363 states and 1938 transitions. [2018-11-18 11:59:39,473 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:59:39,473 INFO L705 BuchiCegarLoop]: Abstraction has 1363 states and 1938 transitions. [2018-11-18 11:59:39,474 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1363 states and 1938 transitions. [2018-11-18 11:59:39,490 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1363 to 1357. [2018-11-18 11:59:39,490 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1357 states. [2018-11-18 11:59:39,493 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1357 states to 1357 states and 1932 transitions. [2018-11-18 11:59:39,493 INFO L728 BuchiCegarLoop]: Abstraction has 1357 states and 1932 transitions. [2018-11-18 11:59:39,493 INFO L608 BuchiCegarLoop]: Abstraction has 1357 states and 1932 transitions. [2018-11-18 11:59:39,493 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ [2018-11-18 11:59:39,493 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1357 states and 1932 transitions. [2018-11-18 11:59:39,496 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1284 [2018-11-18 11:59:39,497 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:59:39,497 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:59:39,497 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:39,498 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:39,498 INFO L794 eck$LassoCheckResult]: Stem: 9069#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 8977#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 8978#L768 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 9139#L348 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8930#L355 assume 1 == ~m_i~0;~m_st~0 := 0; 8931#L355-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8935#L360-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8809#L365-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8810#L370-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8901#L375-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8902#L516 assume !(0 == ~M_E~0); 9016#L516-2 assume !(0 == ~T1_E~0); 8719#L521-1 assume !(0 == ~T2_E~0); 8720#L526-1 assume !(0 == ~T3_E~0); 8939#L531-1 assume !(0 == ~T4_E~0); 8940#L536-1 assume !(0 == ~E_M~0); 8827#L541-1 assume !(0 == ~E_1~0); 8828#L546-1 assume !(0 == ~E_2~0); 8909#L551-1 assume !(0 == ~E_3~0); 8771#L556-1 assume !(0 == ~E_4~0); 8772#L561-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8975#L252 assume !(1 == ~m_pc~0); 8957#L252-2 is_master_triggered_~__retres1~0 := 0; 8958#L263 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8976#L264 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 9055#L639 assume !(0 != activate_threads_~tmp~1); 8904#L639-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8905#L271 assume !(1 == ~t1_pc~0); 9125#L271-2 is_transmit1_triggered_~__retres1~1 := 0; 9127#L282 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9128#L283 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 9154#L647 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9155#L647-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8728#L290 assume !(1 == ~t2_pc~0); 8716#L290-2 is_transmit2_triggered_~__retres1~2 := 0; 8717#L301 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8729#L302 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 8781#L655 assume !(0 != activate_threads_~tmp___1~0); 8763#L655-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8764#L309 assume !(1 == ~t3_pc~0); 8814#L309-2 is_transmit3_triggered_~__retres1~3 := 0; 8815#L320 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8811#L321 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 8812#L663 assume !(0 != activate_threads_~tmp___2~0); 8948#L663-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8949#L328 assume !(1 == ~t4_pc~0); 8982#L328-2 is_transmit4_triggered_~__retres1~4 := 0; 9048#L339 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8979#L340 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 8980#L671 assume !(0 != activate_threads_~tmp___3~0); 9099#L671-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8825#L574 assume !(1 == ~M_E~0); 8826#L574-2 assume !(1 == ~T1_E~0); 8829#L579-1 assume !(1 == ~T2_E~0); 8906#L584-1 assume !(1 == ~T3_E~0); 8767#L589-1 assume !(1 == ~T4_E~0); 8768#L594-1 assume !(1 == ~E_M~0); 8672#L599-1 assume 1 == ~E_1~0;~E_1~0 := 2; 8673#L604-1 assume !(1 == ~E_2~0); 8742#L609-1 assume !(1 == ~E_3~0); 8743#L614-1 assume !(1 == ~E_4~0); 8950#L619-1 assume { :end_inline_reset_delta_events } true; 8951#L805-3 [2018-11-18 11:59:39,498 INFO L796 eck$LassoCheckResult]: Loop: 8951#L805-3 assume true; 9825#L805-1 assume !false; 8952#L806 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 8722#L491 assume true; 9133#L425-1 assume !false; 9134#L426 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 8924#L388 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 8733#L415 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 9152#L416 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 8894#L430 assume !(0 != eval_~tmp~0); 8895#L506 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 9102#L348-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 9018#L516-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9019#L516-5 assume !(0 == ~T1_E~0); 8730#L521-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8731#L526-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8943#L531-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8944#L536-3 assume !(0 == ~E_M~0); 8831#L541-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8832#L546-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8891#L551-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8751#L556-3 assume !(0 == ~E_4~0); 8752#L561-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9091#L252-18 assume !(1 == ~m_pc~0); 9107#L252-20 is_master_triggered_~__retres1~0 := 0; 8990#L263-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8991#L264-6 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 8863#L639-18 assume !(0 != activate_threads_~tmp~1); 8864#L639-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8869#L271-18 assume 1 == ~t1_pc~0; 9159#L272-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 9160#L282-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9758#L283-6 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 9040#L647-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9041#L647-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8668#L290-18 assume !(1 == ~t2_pc~0); 8669#L290-20 is_transmit2_triggered_~__retres1~2 := 0; 8683#L301-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8689#L302-6 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 8792#L655-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 9146#L655-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8837#L309-18 assume 1 == ~t3_pc~0; 8838#L310-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 8843#L320-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8885#L321-6 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 8923#L663-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 8913#L663-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8914#L328-18 assume !(1 == ~t4_pc~0); 8964#L328-20 is_transmit4_triggered_~__retres1~4 := 0; 9020#L339-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8959#L340-6 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 8960#L671-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 9064#L671-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8830#L574-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8807#L574-5 assume !(1 == ~T1_E~0); 8808#L579-3 assume !(1 == ~T2_E~0); 8910#L584-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8773#L589-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8774#L594-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8798#L599-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8799#L604-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8714#L609-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8715#L614-3 assume !(1 == ~E_4~0); 8938#L619-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 8928#L388-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 8737#L415-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 9153#L416-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 9022#L824 assume !(0 == start_simulation_~tmp~3); 9023#L824-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 9835#L388-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 9831#L415-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 9830#L416-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 9829#L779 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 9828#L786 stop_simulation_#res := stop_simulation_~__retres2~0; 9827#L787 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 9826#L837 assume !(0 != start_simulation_~tmp___0~1); 8951#L805-3 [2018-11-18 11:59:39,498 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:39,498 INFO L82 PathProgramCache]: Analyzing trace with hash 842961413, now seen corresponding path program 1 times [2018-11-18 11:59:39,498 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:39,498 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:39,499 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:39,499 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:59:39,499 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:39,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:59:39,575 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:59:39,575 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:59:39,575 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 11:59:39,575 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 11:59:39,575 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:39,576 INFO L82 PathProgramCache]: Analyzing trace with hash 742451160, now seen corresponding path program 2 times [2018-11-18 11:59:39,576 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:39,576 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:39,576 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:39,576 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:59:39,576 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:39,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:59:39,641 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:59:39,642 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:59:39,642 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 11:59:39,642 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 11:59:39,642 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 11:59:39,642 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 11:59:39,642 INFO L87 Difference]: Start difference. First operand 1357 states and 1932 transitions. cyclomatic complexity: 579 Second operand 3 states. [2018-11-18 11:59:39,852 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:59:39,852 INFO L93 Difference]: Finished difference Result 1357 states and 1895 transitions. [2018-11-18 11:59:39,853 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 11:59:39,853 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1357 states and 1895 transitions. [2018-11-18 11:59:39,857 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1284 [2018-11-18 11:59:39,862 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1357 states to 1357 states and 1895 transitions. [2018-11-18 11:59:39,862 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1357 [2018-11-18 11:59:39,863 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1357 [2018-11-18 11:59:39,863 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1357 states and 1895 transitions. [2018-11-18 11:59:39,864 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:59:39,865 INFO L705 BuchiCegarLoop]: Abstraction has 1357 states and 1895 transitions. [2018-11-18 11:59:39,865 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1357 states and 1895 transitions. [2018-11-18 11:59:39,879 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1357 to 1357. [2018-11-18 11:59:39,879 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1357 states. [2018-11-18 11:59:39,882 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1357 states to 1357 states and 1895 transitions. [2018-11-18 11:59:39,882 INFO L728 BuchiCegarLoop]: Abstraction has 1357 states and 1895 transitions. [2018-11-18 11:59:39,882 INFO L608 BuchiCegarLoop]: Abstraction has 1357 states and 1895 transitions. [2018-11-18 11:59:39,882 INFO L442 BuchiCegarLoop]: ======== Iteration 10============ [2018-11-18 11:59:39,882 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1357 states and 1895 transitions. [2018-11-18 11:59:39,885 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1284 [2018-11-18 11:59:39,886 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:59:39,886 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:59:39,886 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:39,887 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:39,887 INFO L794 eck$LassoCheckResult]: Stem: 11776#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 11691#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 11692#L768 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 11839#L348 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11645#L355 assume 1 == ~m_i~0;~m_st~0 := 0; 11646#L355-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11650#L360-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11529#L365-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11530#L370-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11615#L375-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11616#L516 assume !(0 == ~M_E~0); 11730#L516-2 assume !(0 == ~T1_E~0); 11440#L521-1 assume !(0 == ~T2_E~0); 11441#L526-1 assume !(0 == ~T3_E~0); 11655#L531-1 assume !(0 == ~T4_E~0); 11656#L536-1 assume !(0 == ~E_M~0); 11547#L541-1 assume !(0 == ~E_1~0); 11548#L546-1 assume !(0 == ~E_2~0); 11623#L551-1 assume !(0 == ~E_3~0); 11491#L556-1 assume !(0 == ~E_4~0); 11492#L561-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11689#L252 assume !(1 == ~m_pc~0); 11672#L252-2 is_master_triggered_~__retres1~0 := 0; 11673#L263 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11690#L264 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 11762#L639 assume !(0 != activate_threads_~tmp~1); 11618#L639-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11619#L271 assume !(1 == ~t1_pc~0); 11824#L271-2 is_transmit1_triggered_~__retres1~1 := 0; 11826#L282 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11827#L283 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 11853#L647 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 11854#L647-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11449#L290 assume !(1 == ~t2_pc~0); 11437#L290-2 is_transmit2_triggered_~__retres1~2 := 0; 11438#L301 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11452#L302 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 11501#L655 assume !(0 != activate_threads_~tmp___1~0); 11483#L655-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11484#L309 assume !(1 == ~t3_pc~0); 11534#L309-2 is_transmit3_triggered_~__retres1~3 := 0; 11535#L320 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11531#L321 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 11532#L663 assume !(0 != activate_threads_~tmp___2~0); 11663#L663-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11664#L328 assume !(1 == ~t4_pc~0); 11696#L328-2 is_transmit4_triggered_~__retres1~4 := 0; 11757#L339 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11693#L340 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 11694#L671 assume !(0 != activate_threads_~tmp___3~0); 11801#L671-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11545#L574 assume !(1 == ~M_E~0); 11546#L574-2 assume !(1 == ~T1_E~0); 11549#L579-1 assume !(1 == ~T2_E~0); 11620#L584-1 assume !(1 == ~T3_E~0); 11489#L589-1 assume !(1 == ~T4_E~0); 11490#L594-1 assume !(1 == ~E_M~0); 11393#L599-1 assume !(1 == ~E_1~0); 11394#L604-1 assume !(1 == ~E_2~0); 11463#L609-1 assume !(1 == ~E_3~0); 11464#L614-1 assume !(1 == ~E_4~0); 11665#L619-1 assume { :end_inline_reset_delta_events } true; 11560#L805-3 [2018-11-18 11:59:39,887 INFO L796 eck$LassoCheckResult]: Loop: 11560#L805-3 assume true; 11555#L805-1 assume !false; 11556#L806 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 11443#L491 assume true; 11832#L425-1 assume !false; 11833#L426 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 11639#L388 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 11454#L415 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 11851#L416 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 11609#L430 assume !(0 != eval_~tmp~0); 11610#L506 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 11804#L348-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 11732#L516-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11733#L516-5 assume !(0 == ~T1_E~0); 11450#L521-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11451#L526-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11658#L531-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11659#L536-3 assume !(0 == ~E_M~0); 11551#L541-3 assume !(0 == ~E_1~0); 11552#L546-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11606#L551-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11474#L556-3 assume !(0 == ~E_4~0); 11475#L561-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11793#L252-18 assume !(1 == ~m_pc~0); 11797#L252-20 is_master_triggered_~__retres1~0 := 0; 11704#L263-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11705#L264-6 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 11581#L639-18 assume !(0 != activate_threads_~tmp~1); 11582#L639-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11587#L271-18 assume !(1 == ~t1_pc~0); 11858#L271-20 is_transmit1_triggered_~__retres1~1 := 0; 11816#L282-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11817#L283-6 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 11750#L647-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 11741#L647-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11389#L290-18 assume !(1 == ~t2_pc~0); 11390#L290-20 is_transmit2_triggered_~__retres1~2 := 0; 11404#L301-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11409#L302-6 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 11513#L655-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 11844#L655-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11557#L309-18 assume 1 == ~t3_pc~0; 11558#L310-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 11563#L320-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11602#L321-6 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 11667#L663-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 12630#L663-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12626#L328-18 assume !(1 == ~t4_pc~0); 12624#L328-20 is_transmit4_triggered_~__retres1~4 := 0; 12622#L339-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12620#L340-6 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 12618#L671-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 12616#L671-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12614#L574-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12612#L574-5 assume !(1 == ~T1_E~0); 12610#L579-3 assume !(1 == ~T2_E~0); 12608#L584-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12606#L589-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12601#L594-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12600#L599-3 assume !(1 == ~E_1~0); 12596#L604-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12591#L609-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12590#L614-3 assume !(1 == ~E_4~0); 12589#L619-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 12584#L388-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 12583#L415-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 12582#L416-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 12579#L824 assume !(0 == start_simulation_~tmp~3); 11740#L824-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 11647#L388-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 11429#L415-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 11754#L416-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 11755#L779 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 11400#L786 stop_simulation_#res := stop_simulation_~__retres2~0; 11401#L787 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 11496#L837 assume !(0 != start_simulation_~tmp___0~1); 11560#L805-3 [2018-11-18 11:59:39,887 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:39,887 INFO L82 PathProgramCache]: Analyzing trace with hash 844808455, now seen corresponding path program 1 times [2018-11-18 11:59:39,887 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:39,887 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:39,888 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:39,888 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 11:59:39,888 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:39,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:59:40,063 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:59:40,064 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:59:40,064 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 11:59:40,064 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 11:59:40,064 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:40,064 INFO L82 PathProgramCache]: Analyzing trace with hash 1989357465, now seen corresponding path program 1 times [2018-11-18 11:59:40,064 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:40,064 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:40,065 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:40,065 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:59:40,065 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:40,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:59:40,155 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:59:40,156 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:59:40,156 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 11:59:40,156 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 11:59:40,157 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 11:59:40,157 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 11:59:40,157 INFO L87 Difference]: Start difference. First operand 1357 states and 1895 transitions. cyclomatic complexity: 542 Second operand 5 states. [2018-11-18 11:59:40,845 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:59:40,845 INFO L93 Difference]: Finished difference Result 1830 states and 2552 transitions. [2018-11-18 11:59:40,846 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 11:59:40,846 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1830 states and 2552 transitions. [2018-11-18 11:59:40,852 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1753 [2018-11-18 11:59:40,858 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1830 states to 1830 states and 2552 transitions. [2018-11-18 11:59:40,858 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1830 [2018-11-18 11:59:40,859 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1830 [2018-11-18 11:59:40,859 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1830 states and 2552 transitions. [2018-11-18 11:59:40,861 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:59:40,861 INFO L705 BuchiCegarLoop]: Abstraction has 1830 states and 2552 transitions. [2018-11-18 11:59:40,862 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1830 states and 2552 transitions. [2018-11-18 11:59:40,877 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1830 to 1363. [2018-11-18 11:59:40,878 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1363 states. [2018-11-18 11:59:40,880 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1363 states to 1363 states and 1878 transitions. [2018-11-18 11:59:40,880 INFO L728 BuchiCegarLoop]: Abstraction has 1363 states and 1878 transitions. [2018-11-18 11:59:40,881 INFO L608 BuchiCegarLoop]: Abstraction has 1363 states and 1878 transitions. [2018-11-18 11:59:40,881 INFO L442 BuchiCegarLoop]: ======== Iteration 11============ [2018-11-18 11:59:40,881 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1363 states and 1878 transitions. [2018-11-18 11:59:40,884 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1290 [2018-11-18 11:59:40,884 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:59:40,884 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:59:40,885 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:40,885 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:40,885 INFO L794 eck$LassoCheckResult]: Stem: 15026#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 14920#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 14921#L768 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 15106#L348 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14863#L355 assume 1 == ~m_i~0;~m_st~0 := 0; 14864#L355-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14871#L360-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14740#L365-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14741#L370-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14834#L375-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14835#L516 assume !(0 == ~M_E~0); 14960#L516-2 assume !(0 == ~T1_E~0); 14643#L521-1 assume !(0 == ~T2_E~0); 14644#L526-1 assume !(0 == ~T3_E~0); 14875#L531-1 assume !(0 == ~T4_E~0); 14876#L536-1 assume !(0 == ~E_M~0); 14758#L541-1 assume !(0 == ~E_1~0); 14759#L546-1 assume !(0 == ~E_2~0); 14842#L551-1 assume !(0 == ~E_3~0); 14697#L556-1 assume !(0 == ~E_4~0); 14698#L561-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14918#L252 assume !(1 == ~m_pc~0); 14901#L252-2 is_master_triggered_~__retres1~0 := 0; 14902#L263 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14919#L264 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 15009#L639 assume !(0 != activate_threads_~tmp~1); 14837#L639-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14838#L271 assume !(1 == ~t1_pc~0); 15091#L271-2 is_transmit1_triggered_~__retres1~1 := 0; 15093#L282 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15094#L283 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 15130#L647 assume !(0 != activate_threads_~tmp___0~0); 15131#L647-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14654#L290 assume !(1 == ~t2_pc~0); 14641#L290-2 is_transmit2_triggered_~__retres1~2 := 0; 14642#L301 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14655#L302 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 14706#L655 assume !(0 != activate_threads_~tmp___1~0); 14688#L655-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14689#L309 assume !(1 == ~t3_pc~0); 14745#L309-2 is_transmit3_triggered_~__retres1~3 := 0; 14746#L320 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14742#L321 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 14743#L663 assume !(0 != activate_threads_~tmp___2~0); 14885#L663-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 14886#L328 assume !(1 == ~t4_pc~0); 14925#L328-2 is_transmit4_triggered_~__retres1~4 := 0; 14996#L339 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 14922#L340 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 14923#L671 assume !(0 != activate_threads_~tmp___3~0); 15063#L671-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14754#L574 assume !(1 == ~M_E~0); 14755#L574-2 assume !(1 == ~T1_E~0); 14760#L579-1 assume !(1 == ~T2_E~0); 14839#L584-1 assume !(1 == ~T3_E~0); 14691#L589-1 assume !(1 == ~T4_E~0); 14692#L594-1 assume !(1 == ~E_M~0); 14593#L599-1 assume !(1 == ~E_1~0); 14594#L604-1 assume !(1 == ~E_2~0); 14668#L609-1 assume !(1 == ~E_3~0); 14669#L614-1 assume !(1 == ~E_4~0); 14887#L619-1 assume { :end_inline_reset_delta_events } true; 14888#L805-3 [2018-11-18 11:59:40,885 INFO L796 eck$LassoCheckResult]: Loop: 14888#L805-3 assume true; 15602#L805-1 assume !false; 15595#L806 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 15592#L491 assume true; 15590#L425-1 assume !false; 15588#L426 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 15584#L388 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 15580#L415 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 15576#L416 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 15573#L430 assume !(0 != eval_~tmp~0); 15574#L506 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 15851#L348-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 15850#L516-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15849#L516-5 assume !(0 == ~T1_E~0); 15848#L521-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15847#L526-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15846#L531-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15845#L536-3 assume !(0 == ~E_M~0); 15844#L541-3 assume !(0 == ~E_1~0); 15843#L546-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15842#L551-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14677#L556-3 assume !(0 == ~E_4~0); 14678#L561-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15051#L252-18 assume !(1 == ~m_pc~0); 15059#L252-20 is_master_triggered_~__retres1~0 := 0; 14933#L263-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14934#L264-6 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 14795#L639-18 assume !(0 != activate_threads_~tmp~1); 14796#L639-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14802#L271-18 assume !(1 == ~t1_pc~0); 15144#L271-20 is_transmit1_triggered_~__retres1~1 := 0; 15080#L282-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15081#L283-6 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 14989#L647-18 assume !(0 != activate_threads_~tmp___0~0); 14973#L647-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14589#L290-18 assume !(1 == ~t2_pc~0); 14590#L290-20 is_transmit2_triggered_~__retres1~2 := 0; 14604#L301-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14609#L302-6 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 14719#L655-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 15122#L655-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14768#L309-18 assume 1 == ~t3_pc~0; 14769#L310-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 14774#L320-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14819#L321-6 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 14857#L663-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 14858#L663-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 15353#L328-18 assume !(1 == ~t4_pc~0); 15351#L328-20 is_transmit4_triggered_~__retres1~4 := 0; 15349#L339-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 15347#L340-6 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 15019#L671-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 15020#L671-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14761#L574-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14738#L574-5 assume !(1 == ~T1_E~0); 14739#L579-3 assume !(1 == ~T2_E~0); 15118#L584-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15331#L589-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15329#L594-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14727#L599-3 assume !(1 == ~E_1~0); 14728#L604-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14639#L609-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14640#L614-3 assume !(1 == ~E_4~0); 14874#L619-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 14865#L388-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 14663#L415-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 15129#L416-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 14967#L824 assume !(0 == start_simulation_~tmp~3); 14968#L824-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 15641#L388-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 15634#L415-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 15630#L416-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 15626#L779 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 15620#L786 stop_simulation_#res := stop_simulation_~__retres2~0; 15616#L787 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 15611#L837 assume !(0 != start_simulation_~tmp___0~1); 14888#L805-3 [2018-11-18 11:59:40,886 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:40,886 INFO L82 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 1 times [2018-11-18 11:59:40,886 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:40,886 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:40,887 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:40,887 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:59:40,887 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:40,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:59:40,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:59:40,934 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:40,934 INFO L82 PathProgramCache]: Analyzing trace with hash 1091964187, now seen corresponding path program 1 times [2018-11-18 11:59:40,935 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:40,935 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:40,935 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:40,936 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:59:40,936 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:40,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:59:40,991 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:59:40,991 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:59:40,991 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 11:59:40,991 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 11:59:40,991 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 11:59:40,991 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 11:59:40,992 INFO L87 Difference]: Start difference. First operand 1363 states and 1878 transitions. cyclomatic complexity: 519 Second operand 3 states. [2018-11-18 11:59:41,136 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:59:41,136 INFO L93 Difference]: Finished difference Result 1587 states and 2180 transitions. [2018-11-18 11:59:41,137 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 11:59:41,138 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1587 states and 2180 transitions. [2018-11-18 11:59:41,143 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1470 [2018-11-18 11:59:41,147 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1587 states to 1587 states and 2180 transitions. [2018-11-18 11:59:41,148 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1587 [2018-11-18 11:59:41,148 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1587 [2018-11-18 11:59:41,148 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1587 states and 2180 transitions. [2018-11-18 11:59:41,150 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:59:41,150 INFO L705 BuchiCegarLoop]: Abstraction has 1587 states and 2180 transitions. [2018-11-18 11:59:41,151 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1587 states and 2180 transitions. [2018-11-18 11:59:41,169 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1587 to 1587. [2018-11-18 11:59:41,169 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1587 states. [2018-11-18 11:59:41,173 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1587 states to 1587 states and 2180 transitions. [2018-11-18 11:59:41,174 INFO L728 BuchiCegarLoop]: Abstraction has 1587 states and 2180 transitions. [2018-11-18 11:59:41,174 INFO L608 BuchiCegarLoop]: Abstraction has 1587 states and 2180 transitions. [2018-11-18 11:59:41,174 INFO L442 BuchiCegarLoop]: ======== Iteration 12============ [2018-11-18 11:59:41,174 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1587 states and 2180 transitions. [2018-11-18 11:59:41,177 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1470 [2018-11-18 11:59:41,178 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:59:41,178 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:59:41,178 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:41,178 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:41,179 INFO L794 eck$LassoCheckResult]: Stem: 17940#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 17849#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 17850#L768 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 18004#L348 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17802#L355 assume 1 == ~m_i~0;~m_st~0 := 0; 17803#L355-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17807#L360-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17687#L365-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17688#L370-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17774#L375-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17775#L516 assume !(0 == ~M_E~0); 17888#L516-2 assume !(0 == ~T1_E~0); 17595#L521-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17596#L526-1 assume !(0 == ~T3_E~0); 17812#L531-1 assume !(0 == ~T4_E~0); 17813#L536-1 assume !(0 == ~E_M~0); 17705#L541-1 assume !(0 == ~E_1~0); 17706#L546-1 assume !(0 == ~E_2~0); 17781#L551-1 assume !(0 == ~E_3~0); 17648#L556-1 assume !(0 == ~E_4~0); 17649#L561-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 17847#L252 assume !(1 == ~m_pc~0); 17829#L252-2 is_master_triggered_~__retres1~0 := 0; 17830#L263 is_master_triggered_#res := is_master_triggered_~__retres1~0; 17848#L264 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 17922#L639 assume !(0 != activate_threads_~tmp~1); 17776#L639-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 17777#L271 assume !(1 == ~t1_pc~0); 17988#L271-2 is_transmit1_triggered_~__retres1~1 := 0; 17990#L282 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17991#L283 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 18024#L647 assume !(0 != activate_threads_~tmp___0~0); 18025#L647-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 19112#L290 assume !(1 == ~t2_pc~0); 19111#L290-2 is_transmit2_triggered_~__retres1~2 := 0; 19110#L301 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 19109#L302 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 19108#L655 assume !(0 != activate_threads_~tmp___1~0); 19107#L655-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 19106#L309 assume !(1 == ~t3_pc~0); 19104#L309-2 is_transmit3_triggered_~__retres1~3 := 0; 19103#L320 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 19102#L321 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 18986#L663 assume !(0 != activate_threads_~tmp___2~0); 17821#L663-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 17822#L328 assume !(1 == ~t4_pc~0); 18072#L328-2 is_transmit4_triggered_~__retres1~4 := 0; 18067#L339 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 18061#L340 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 18057#L671 assume !(0 != activate_threads_~tmp___3~0); 18052#L671-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18047#L574 assume !(1 == ~M_E~0); 17707#L574-2 assume !(1 == ~T1_E~0); 17708#L579-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17778#L584-1 assume !(1 == ~T3_E~0); 17646#L589-1 assume !(1 == ~T4_E~0); 17647#L594-1 assume !(1 == ~E_M~0); 17549#L599-1 assume !(1 == ~E_1~0); 17550#L604-1 assume !(1 == ~E_2~0); 17620#L609-1 assume !(1 == ~E_3~0); 17621#L614-1 assume !(1 == ~E_4~0); 17823#L619-1 assume { :end_inline_reset_delta_events } true; 17824#L805-3 [2018-11-18 11:59:41,179 INFO L796 eck$LassoCheckResult]: Loop: 17824#L805-3 assume true; 18239#L805-1 assume !false; 18236#L806 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 17599#L491 assume true; 18232#L425-1 assume !false; 18230#L426 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 18222#L388 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 18220#L415 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 18434#L416 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 18431#L430 assume !(0 != eval_~tmp~0); 18432#L506 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 18984#L348-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 18983#L516-3 assume 0 == ~M_E~0;~M_E~0 := 1; 18982#L516-5 assume !(0 == ~T1_E~0); 18981#L521-3 assume !(0 == ~T2_E~0); 18979#L526-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18977#L531-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18975#L536-3 assume !(0 == ~E_M~0); 18973#L541-3 assume !(0 == ~E_1~0); 18971#L546-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18969#L551-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18967#L556-3 assume !(0 == ~E_4~0); 18965#L561-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 18963#L252-18 assume !(1 == ~m_pc~0); 18961#L252-20 is_master_triggered_~__retres1~0 := 0; 18959#L263-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 18957#L264-6 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 18955#L639-18 assume !(0 != activate_threads_~tmp~1); 18953#L639-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 18950#L271-18 assume !(1 == ~t1_pc~0); 18947#L271-20 is_transmit1_triggered_~__retres1~1 := 0; 18945#L282-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 18943#L283-6 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 18941#L647-18 assume !(0 != activate_threads_~tmp___0~0); 18939#L647-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 18937#L290-18 assume !(1 == ~t2_pc~0); 18935#L290-20 is_transmit2_triggered_~__retres1~2 := 0; 18933#L301-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 18931#L302-6 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 18929#L655-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 18927#L655-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 18925#L309-18 assume 1 == ~t3_pc~0; 18921#L310-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 18919#L320-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 18917#L321-6 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 18915#L663-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 18913#L663-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 18911#L328-18 assume !(1 == ~t4_pc~0); 18908#L328-20 is_transmit4_triggered_~__retres1~4 := 0; 18906#L339-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 18904#L340-6 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 18902#L671-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 18900#L671-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18898#L574-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18896#L574-5 assume !(1 == ~T1_E~0); 18893#L579-3 assume !(1 == ~T2_E~0); 18892#L584-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18891#L589-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18890#L594-3 assume 1 == ~E_M~0;~E_M~0 := 2; 18889#L599-3 assume !(1 == ~E_1~0); 18888#L604-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18887#L609-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18886#L614-3 assume !(1 == ~E_4~0); 18885#L619-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 18880#L388-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 18879#L415-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 18022#L416-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 18023#L824 assume !(0 == start_simulation_~tmp~3); 18262#L824-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 18257#L388-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 18252#L415-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 18251#L416-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 18248#L779 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 18246#L786 stop_simulation_#res := stop_simulation_~__retres2~0; 18244#L787 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 18242#L837 assume !(0 != start_simulation_~tmp___0~1); 17824#L805-3 [2018-11-18 11:59:41,179 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:41,179 INFO L82 PathProgramCache]: Analyzing trace with hash 1347430217, now seen corresponding path program 1 times [2018-11-18 11:59:41,179 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:41,179 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:41,193 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:41,193 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:59:41,193 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:41,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:59:41,261 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:59:41,261 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:59:41,262 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 11:59:41,262 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 11:59:41,262 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:41,262 INFO L82 PathProgramCache]: Analyzing trace with hash 1771236441, now seen corresponding path program 1 times [2018-11-18 11:59:41,262 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:41,262 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:41,263 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:41,263 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:59:41,263 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:41,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:59:41,369 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:59:41,369 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:59:41,369 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 11:59:41,370 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 11:59:41,370 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 11:59:41,370 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 11:59:41,370 INFO L87 Difference]: Start difference. First operand 1587 states and 2180 transitions. cyclomatic complexity: 597 Second operand 3 states. [2018-11-18 11:59:41,452 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:59:41,452 INFO L93 Difference]: Finished difference Result 1363 states and 1864 transitions. [2018-11-18 11:59:41,453 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 11:59:41,454 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1363 states and 1864 transitions. [2018-11-18 11:59:41,457 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1290 [2018-11-18 11:59:41,463 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1363 states to 1363 states and 1864 transitions. [2018-11-18 11:59:41,464 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1363 [2018-11-18 11:59:41,466 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1363 [2018-11-18 11:59:41,466 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1363 states and 1864 transitions. [2018-11-18 11:59:41,468 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:59:41,468 INFO L705 BuchiCegarLoop]: Abstraction has 1363 states and 1864 transitions. [2018-11-18 11:59:41,470 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1363 states and 1864 transitions. [2018-11-18 11:59:41,481 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1363 to 1363. [2018-11-18 11:59:41,481 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1363 states. [2018-11-18 11:59:41,484 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1363 states to 1363 states and 1864 transitions. [2018-11-18 11:59:41,485 INFO L728 BuchiCegarLoop]: Abstraction has 1363 states and 1864 transitions. [2018-11-18 11:59:41,485 INFO L608 BuchiCegarLoop]: Abstraction has 1363 states and 1864 transitions. [2018-11-18 11:59:41,485 INFO L442 BuchiCegarLoop]: ======== Iteration 13============ [2018-11-18 11:59:41,486 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1363 states and 1864 transitions. [2018-11-18 11:59:41,488 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1290 [2018-11-18 11:59:41,488 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:59:41,488 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:59:41,492 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:41,494 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:41,494 INFO L794 eck$LassoCheckResult]: Stem: 20884#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 20799#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 20800#L768 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 20942#L348 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20753#L355 assume 1 == ~m_i~0;~m_st~0 := 0; 20754#L355-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20760#L360-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20639#L365-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20640#L370-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20726#L375-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20727#L516 assume !(0 == ~M_E~0); 20838#L516-2 assume !(0 == ~T1_E~0); 20556#L521-1 assume !(0 == ~T2_E~0); 20557#L526-1 assume !(0 == ~T3_E~0); 20764#L531-1 assume !(0 == ~T4_E~0); 20765#L536-1 assume !(0 == ~E_M~0); 20657#L541-1 assume !(0 == ~E_1~0); 20658#L546-1 assume !(0 == ~E_2~0); 20734#L551-1 assume !(0 == ~E_3~0); 20607#L556-1 assume !(0 == ~E_4~0); 20608#L561-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 20797#L252 assume !(1 == ~m_pc~0); 20780#L252-2 is_master_triggered_~__retres1~0 := 0; 20781#L263 is_master_triggered_#res := is_master_triggered_~__retres1~0; 20798#L264 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 20869#L639 assume !(0 != activate_threads_~tmp~1); 20729#L639-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20730#L271 assume !(1 == ~t1_pc~0); 20928#L271-2 is_transmit1_triggered_~__retres1~1 := 0; 20930#L282 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 20931#L283 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 20957#L647 assume !(0 != activate_threads_~tmp___0~0); 20958#L647-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 20565#L290 assume !(1 == ~t2_pc~0); 20554#L290-2 is_transmit2_triggered_~__retres1~2 := 0; 20555#L301 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 20566#L302 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 20615#L655 assume !(0 != activate_threads_~tmp___1~0); 20598#L655-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 20599#L309 assume !(1 == ~t3_pc~0); 20644#L309-2 is_transmit3_triggered_~__retres1~3 := 0; 20645#L320 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 20641#L321 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 20642#L663 assume !(0 != activate_threads_~tmp___2~0); 20773#L663-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 20774#L328 assume !(1 == ~t4_pc~0); 20804#L328-2 is_transmit4_triggered_~__retres1~4 := 0; 20864#L339 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 20801#L340 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 20802#L671 assume !(0 != activate_threads_~tmp___3~0); 20905#L671-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20653#L574 assume !(1 == ~M_E~0); 20654#L574-2 assume !(1 == ~T1_E~0); 20659#L579-1 assume !(1 == ~T2_E~0); 20731#L584-1 assume !(1 == ~T3_E~0); 20601#L589-1 assume !(1 == ~T4_E~0); 20602#L594-1 assume !(1 == ~E_M~0); 20508#L599-1 assume !(1 == ~E_1~0); 20509#L604-1 assume !(1 == ~E_2~0); 20579#L609-1 assume !(1 == ~E_3~0); 20580#L614-1 assume !(1 == ~E_4~0); 20775#L619-1 assume { :end_inline_reset_delta_events } true; 20776#L805-3 [2018-11-18 11:59:41,494 INFO L796 eck$LassoCheckResult]: Loop: 20776#L805-3 assume true; 21325#L805-1 assume !false; 21250#L806 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 21244#L491 assume true; 21181#L425-1 assume !false; 21180#L426 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 21129#L388 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 21125#L415 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 21123#L416 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 21120#L430 assume !(0 != eval_~tmp~0); 21121#L506 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 21573#L348-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 21571#L516-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21569#L516-5 assume !(0 == ~T1_E~0); 21568#L521-3 assume !(0 == ~T2_E~0); 21565#L526-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21563#L531-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21561#L536-3 assume !(0 == ~E_M~0); 21559#L541-3 assume !(0 == ~E_1~0); 21557#L546-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21555#L551-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21553#L556-3 assume !(0 == ~E_4~0); 21551#L561-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 21549#L252-18 assume !(1 == ~m_pc~0); 21547#L252-20 is_master_triggered_~__retres1~0 := 0; 21545#L263-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 21543#L264-6 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 21541#L639-18 assume !(0 != activate_threads_~tmp~1); 21538#L639-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 21536#L271-18 assume !(1 == ~t1_pc~0); 21533#L271-20 is_transmit1_triggered_~__retres1~1 := 0; 21531#L282-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 21529#L283-6 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 21526#L647-18 assume !(0 != activate_threads_~tmp___0~0); 21524#L647-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 21522#L290-18 assume !(1 == ~t2_pc~0); 21520#L290-20 is_transmit2_triggered_~__retres1~2 := 0; 21518#L301-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 21516#L302-6 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 21514#L655-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 21512#L655-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 21510#L309-18 assume 1 == ~t3_pc~0; 21507#L310-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 21505#L320-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 21503#L321-6 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 21501#L663-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 21499#L663-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 21495#L328-18 assume !(1 == ~t4_pc~0); 21494#L328-20 is_transmit4_triggered_~__retres1~4 := 0; 21493#L339-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 21492#L340-6 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 21491#L671-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 21489#L671-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21487#L574-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21485#L574-5 assume !(1 == ~T1_E~0); 21483#L579-3 assume !(1 == ~T2_E~0); 21481#L584-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21479#L589-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21476#L594-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21474#L599-3 assume !(1 == ~E_1~0); 21472#L604-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21470#L609-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21468#L614-3 assume !(1 == ~E_4~0); 21466#L619-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 21456#L388-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 21454#L415-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 21452#L416-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 21448#L824 assume !(0 == start_simulation_~tmp~3); 21445#L824-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 21438#L388-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 21433#L415-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 21431#L416-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 21429#L779 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 21427#L786 stop_simulation_#res := stop_simulation_~__retres2~0; 21425#L787 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 21359#L837 assume !(0 != start_simulation_~tmp___0~1); 20776#L805-3 [2018-11-18 11:59:41,495 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:41,495 INFO L82 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 2 times [2018-11-18 11:59:41,495 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:41,495 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:41,506 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:41,506 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:59:41,506 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:41,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:59:41,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:59:41,536 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:41,539 INFO L82 PathProgramCache]: Analyzing trace with hash 1771236441, now seen corresponding path program 2 times [2018-11-18 11:59:41,539 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:41,539 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:41,540 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:41,540 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 11:59:41,540 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:41,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:59:41,793 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:59:41,793 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:59:41,793 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 11:59:41,793 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 11:59:41,793 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 11:59:41,794 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 11:59:41,794 INFO L87 Difference]: Start difference. First operand 1363 states and 1864 transitions. cyclomatic complexity: 505 Second operand 5 states. [2018-11-18 11:59:41,937 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:59:41,938 INFO L93 Difference]: Finished difference Result 2417 states and 3266 transitions. [2018-11-18 11:59:41,938 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-18 11:59:41,938 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2417 states and 3266 transitions. [2018-11-18 11:59:41,945 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2336 [2018-11-18 11:59:41,952 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2417 states to 2417 states and 3266 transitions. [2018-11-18 11:59:41,953 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2417 [2018-11-18 11:59:41,954 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2417 [2018-11-18 11:59:41,954 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2417 states and 3266 transitions. [2018-11-18 11:59:41,958 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:59:41,958 INFO L705 BuchiCegarLoop]: Abstraction has 2417 states and 3266 transitions. [2018-11-18 11:59:41,961 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2417 states and 3266 transitions. [2018-11-18 11:59:41,975 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2417 to 1375. [2018-11-18 11:59:41,975 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1375 states. [2018-11-18 11:59:41,978 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1375 states to 1375 states and 1876 transitions. [2018-11-18 11:59:41,978 INFO L728 BuchiCegarLoop]: Abstraction has 1375 states and 1876 transitions. [2018-11-18 11:59:41,978 INFO L608 BuchiCegarLoop]: Abstraction has 1375 states and 1876 transitions. [2018-11-18 11:59:41,978 INFO L442 BuchiCegarLoop]: ======== Iteration 14============ [2018-11-18 11:59:41,978 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1375 states and 1876 transitions. [2018-11-18 11:59:41,981 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1302 [2018-11-18 11:59:41,981 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:59:41,981 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:59:41,982 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:41,982 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:41,982 INFO L794 eck$LassoCheckResult]: Stem: 24696#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 24610#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 24611#L768 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 24760#L348 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24557#L355 assume 1 == ~m_i~0;~m_st~0 := 0; 24558#L355-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24564#L360-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24439#L365-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24440#L370-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 24529#L375-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24530#L516 assume !(0 == ~M_E~0); 24649#L516-2 assume !(0 == ~T1_E~0); 24353#L521-1 assume !(0 == ~T2_E~0); 24354#L526-1 assume !(0 == ~T3_E~0); 24568#L531-1 assume !(0 == ~T4_E~0); 24569#L536-1 assume !(0 == ~E_M~0); 24457#L541-1 assume !(0 == ~E_1~0); 24458#L546-1 assume !(0 == ~E_2~0); 24537#L551-1 assume !(0 == ~E_3~0); 24405#L556-1 assume !(0 == ~E_4~0); 24406#L561-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 24608#L252 assume !(1 == ~m_pc~0); 24591#L252-2 is_master_triggered_~__retres1~0 := 0; 24592#L263 is_master_triggered_#res := is_master_triggered_~__retres1~0; 24609#L264 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 24681#L639 assume !(0 != activate_threads_~tmp~1); 24532#L639-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 24533#L271 assume !(1 == ~t1_pc~0); 24747#L271-2 is_transmit1_triggered_~__retres1~1 := 0; 24749#L282 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 24750#L283 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 24783#L647 assume !(0 != activate_threads_~tmp___0~0); 24784#L647-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 24363#L290 assume !(1 == ~t2_pc~0); 24351#L290-2 is_transmit2_triggered_~__retres1~2 := 0; 24352#L301 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 24364#L302 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 24413#L655 assume !(0 != activate_threads_~tmp___1~0); 24396#L655-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 24397#L309 assume !(1 == ~t3_pc~0); 24444#L309-2 is_transmit3_triggered_~__retres1~3 := 0; 24445#L320 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 24441#L321 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 24442#L663 assume !(0 != activate_threads_~tmp___2~0); 24577#L663-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 24578#L328 assume !(1 == ~t4_pc~0); 24615#L328-2 is_transmit4_triggered_~__retres1~4 := 0; 24675#L339 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 24612#L340 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 24613#L671 assume !(0 != activate_threads_~tmp___3~0); 24723#L671-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24453#L574 assume !(1 == ~M_E~0); 24454#L574-2 assume !(1 == ~T1_E~0); 24459#L579-1 assume !(1 == ~T2_E~0); 24534#L584-1 assume !(1 == ~T3_E~0); 24399#L589-1 assume !(1 == ~T4_E~0); 24400#L594-1 assume !(1 == ~E_M~0); 24304#L599-1 assume !(1 == ~E_1~0); 24305#L604-1 assume !(1 == ~E_2~0); 24377#L609-1 assume !(1 == ~E_3~0); 24378#L614-1 assume !(1 == ~E_4~0); 24579#L619-1 assume { :end_inline_reset_delta_events } true; 24580#L805-3 [2018-11-18 11:59:41,987 INFO L796 eck$LassoCheckResult]: Loop: 24580#L805-3 assume true; 25269#L805-1 assume !false; 25261#L806 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 25257#L491 assume true; 24755#L425-1 assume !false; 24756#L426 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 24553#L388 assume !(0 == ~m_st~0); 24554#L392 assume !(0 == ~t1_st~0); 24718#L396 assume !(0 == ~t2_st~0); 24367#L400 assume !(0 == ~t3_st~0); 24369#L404 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5 := 0; 24789#L415 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 25248#L416 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 25247#L430 assume !(0 != eval_~tmp~0); 24725#L506 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 24726#L348-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 24652#L516-3 assume 0 == ~M_E~0;~M_E~0 := 1; 24653#L516-5 assume !(0 == ~T1_E~0); 24365#L521-3 assume !(0 == ~T2_E~0); 24366#L526-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24780#L531-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24839#L536-3 assume !(0 == ~E_M~0); 24840#L541-3 assume !(0 == ~E_1~0); 24769#L546-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24521#L551-3 assume 0 == ~E_3~0;~E_3~0 := 1; 24386#L556-3 assume !(0 == ~E_4~0); 24387#L561-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 24716#L252-18 assume !(1 == ~m_pc~0); 24719#L252-20 is_master_triggered_~__retres1~0 := 0; 24623#L263-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 24624#L264-6 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 24497#L639-18 assume !(0 != activate_threads_~tmp~1); 24498#L639-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 24503#L271-18 assume !(1 == ~t1_pc~0); 24791#L271-20 is_transmit1_triggered_~__retres1~1 := 0; 24739#L282-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 24740#L283-6 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 24669#L647-18 assume !(0 != activate_threads_~tmp___0~0); 24659#L647-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 24300#L290-18 assume !(1 == ~t2_pc~0); 24301#L290-20 is_transmit2_triggered_~__retres1~2 := 0; 25376#L301-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 25375#L302-6 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 25374#L655-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 25373#L655-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 25372#L309-18 assume 1 == ~t3_pc~0; 25370#L310-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 25369#L320-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 25368#L321-6 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 25367#L663-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 25366#L663-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 25364#L328-18 assume !(1 == ~t4_pc~0); 25363#L328-20 is_transmit4_triggered_~__retres1~4 := 0; 25362#L339-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 25361#L340-6 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 25360#L671-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 25359#L671-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25358#L574-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25357#L574-5 assume !(1 == ~T1_E~0); 25356#L579-3 assume !(1 == ~T2_E~0); 25355#L584-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25354#L589-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25353#L594-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25352#L599-3 assume !(1 == ~E_1~0); 25351#L604-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25350#L609-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25349#L614-3 assume !(1 == ~E_4~0); 25348#L619-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 25343#L388-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 25338#L415-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 25333#L416-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 25327#L824 assume !(0 == start_simulation_~tmp~3); 25309#L824-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 25307#L388-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 25302#L415-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 25300#L416-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 25298#L779 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 25294#L786 stop_simulation_#res := stop_simulation_~__retres2~0; 25292#L787 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 25283#L837 assume !(0 != start_simulation_~tmp___0~1); 24580#L805-3 [2018-11-18 11:59:41,988 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:41,988 INFO L82 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 3 times [2018-11-18 11:59:41,988 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:41,988 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:41,988 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:41,989 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 11:59:41,989 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:41,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:59:41,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:59:42,008 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:42,008 INFO L82 PathProgramCache]: Analyzing trace with hash -1725635379, now seen corresponding path program 1 times [2018-11-18 11:59:42,008 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:42,009 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:42,009 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:42,009 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 11:59:42,009 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:42,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:59:42,051 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:59:42,051 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:59:42,051 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 11:59:42,051 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 11:59:42,051 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 11:59:42,051 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 11:59:42,052 INFO L87 Difference]: Start difference. First operand 1375 states and 1876 transitions. cyclomatic complexity: 505 Second operand 3 states. [2018-11-18 11:59:42,084 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:59:42,085 INFO L93 Difference]: Finished difference Result 2499 states and 3356 transitions. [2018-11-18 11:59:42,086 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 11:59:42,086 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2499 states and 3356 transitions. [2018-11-18 11:59:42,091 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2422 [2018-11-18 11:59:42,095 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2499 states to 2499 states and 3356 transitions. [2018-11-18 11:59:42,095 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2499 [2018-11-18 11:59:42,096 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2499 [2018-11-18 11:59:42,096 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2499 states and 3356 transitions. [2018-11-18 11:59:42,098 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:59:42,098 INFO L705 BuchiCegarLoop]: Abstraction has 2499 states and 3356 transitions. [2018-11-18 11:59:42,099 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2499 states and 3356 transitions. [2018-11-18 11:59:42,117 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2499 to 2434. [2018-11-18 11:59:42,118 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2434 states. [2018-11-18 11:59:42,122 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2434 states to 2434 states and 3271 transitions. [2018-11-18 11:59:42,122 INFO L728 BuchiCegarLoop]: Abstraction has 2434 states and 3271 transitions. [2018-11-18 11:59:42,122 INFO L608 BuchiCegarLoop]: Abstraction has 2434 states and 3271 transitions. [2018-11-18 11:59:42,122 INFO L442 BuchiCegarLoop]: ======== Iteration 15============ [2018-11-18 11:59:42,122 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2434 states and 3271 transitions. [2018-11-18 11:59:42,127 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2357 [2018-11-18 11:59:42,127 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:59:42,127 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:59:42,128 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:42,128 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:42,128 INFO L794 eck$LassoCheckResult]: Stem: 28572#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 28481#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 28482#L768 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 28640#L348 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28435#L355 assume 1 == ~m_i~0;~m_st~0 := 0; 28436#L355-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28442#L360-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28319#L365-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28320#L370-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28407#L375-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28408#L516 assume !(0 == ~M_E~0); 28520#L516-2 assume !(0 == ~T1_E~0); 28232#L521-1 assume !(0 == ~T2_E~0); 28233#L526-1 assume !(0 == ~T3_E~0); 28446#L531-1 assume !(0 == ~T4_E~0); 28447#L536-1 assume !(0 == ~E_M~0); 28337#L541-1 assume !(0 == ~E_1~0); 28338#L546-1 assume !(0 == ~E_2~0); 28415#L551-1 assume !(0 == ~E_3~0); 28284#L556-1 assume !(0 == ~E_4~0); 28285#L561-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 28479#L252 assume !(1 == ~m_pc~0); 28462#L252-2 is_master_triggered_~__retres1~0 := 0; 28463#L263 is_master_triggered_#res := is_master_triggered_~__retres1~0; 28480#L264 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 28556#L639 assume !(0 != activate_threads_~tmp~1); 28410#L639-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 28411#L271 assume !(1 == ~t1_pc~0); 28625#L271-2 is_transmit1_triggered_~__retres1~1 := 0; 28627#L282 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 28628#L283 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 28662#L647 assume !(0 != activate_threads_~tmp___0~0); 28663#L647-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 28241#L290 assume !(1 == ~t2_pc~0); 28230#L290-2 is_transmit2_triggered_~__retres1~2 := 0; 28231#L301 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 28242#L302 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 28292#L655 assume !(0 != activate_threads_~tmp___1~0); 28275#L655-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 28276#L309 assume !(1 == ~t3_pc~0); 28324#L309-2 is_transmit3_triggered_~__retres1~3 := 0; 28325#L320 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 28321#L321 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 28322#L663 assume !(0 != activate_threads_~tmp___2~0); 28455#L663-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 28456#L328 assume !(1 == ~t4_pc~0); 28486#L328-2 is_transmit4_triggered_~__retres1~4 := 0; 28548#L339 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 28483#L340 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 28484#L671 assume !(0 != activate_threads_~tmp___3~0); 28598#L671-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28333#L574 assume !(1 == ~M_E~0); 28334#L574-2 assume !(1 == ~T1_E~0); 28339#L579-1 assume !(1 == ~T2_E~0); 28412#L584-1 assume !(1 == ~T3_E~0); 28278#L589-1 assume !(1 == ~T4_E~0); 28279#L594-1 assume !(1 == ~E_M~0); 28184#L599-1 assume !(1 == ~E_1~0); 28185#L604-1 assume !(1 == ~E_2~0); 28255#L609-1 assume !(1 == ~E_3~0); 28256#L614-1 assume !(1 == ~E_4~0); 28457#L619-1 assume { :end_inline_reset_delta_events } true; 28458#L805-3 [2018-11-18 11:59:42,128 INFO L796 eck$LassoCheckResult]: Loop: 28458#L805-3 assume true; 30529#L805-1 assume !false; 30484#L806 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 30482#L491 assume true; 30481#L425-1 assume !false; 30480#L426 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 30479#L388 assume !(0 == ~m_st~0); 28432#L392 assume !(0 == ~t1_st~0); 29880#L396 assume !(0 == ~t2_st~0); 29879#L400 assume !(0 == ~t3_st~0); 28667#L404 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5 := 0; 28669#L415 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 29821#L416 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 29822#L430 assume !(0 != eval_~tmp~0); 28600#L506 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 28601#L348-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 29878#L516-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29877#L516-5 assume !(0 == ~T1_E~0); 29876#L521-3 assume !(0 == ~T2_E~0); 29875#L526-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29874#L531-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29873#L536-3 assume !(0 == ~E_M~0); 28341#L541-3 assume !(0 == ~E_1~0); 28342#L546-3 assume 0 == ~E_2~0;~E_2~0 := 1; 28650#L551-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29871#L556-3 assume !(0 == ~E_4~0); 29870#L561-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 28607#L252-18 assume !(1 == ~m_pc~0); 28594#L252-20 is_master_triggered_~__retres1~0 := 0; 28494#L263-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 28495#L264-6 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 28373#L639-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 28375#L639-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 28380#L271-18 assume !(1 == ~t1_pc~0); 28671#L271-20 is_transmit1_triggered_~__retres1~1 := 0; 28674#L282-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 30214#L283-6 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 30213#L647-18 assume !(0 != activate_threads_~tmp___0~0); 30212#L647-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 30211#L290-18 assume !(1 == ~t2_pc~0); 30210#L290-20 is_transmit2_triggered_~__retres1~2 := 0; 30209#L301-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 30208#L302-6 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 30207#L655-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 30206#L655-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 30205#L309-18 assume 1 == ~t3_pc~0; 30203#L310-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 30202#L320-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 30201#L321-6 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 30200#L663-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 30199#L663-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 30197#L328-18 assume !(1 == ~t4_pc~0); 30196#L328-20 is_transmit4_triggered_~__retres1~4 := 0; 30195#L339-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 30194#L340-6 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 30193#L671-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 30192#L671-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30191#L574-3 assume 1 == ~M_E~0;~M_E~0 := 2; 30190#L574-5 assume !(1 == ~T1_E~0); 30189#L579-3 assume !(1 == ~T2_E~0); 30188#L584-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30187#L589-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30186#L594-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30185#L599-3 assume !(1 == ~E_1~0); 30184#L604-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30183#L609-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30182#L614-3 assume !(1 == ~E_4~0); 30181#L619-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 30179#L388-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 30180#L415-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 30239#L416-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 30236#L824 assume !(0 == start_simulation_~tmp~3); 30233#L824-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 30229#L388-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 30230#L415-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 30534#L416-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 30533#L779 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 30532#L786 stop_simulation_#res := stop_simulation_~__retres2~0; 30531#L787 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 30530#L837 assume !(0 != start_simulation_~tmp___0~1); 28458#L805-3 [2018-11-18 11:59:42,128 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:42,129 INFO L82 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 4 times [2018-11-18 11:59:42,129 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:42,129 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:42,129 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:42,129 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:59:42,130 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:42,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:59:42,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:59:42,152 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:42,152 INFO L82 PathProgramCache]: Analyzing trace with hash -1710116661, now seen corresponding path program 1 times [2018-11-18 11:59:42,152 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:42,152 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:42,152 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:42,153 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 11:59:42,153 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:42,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:59:42,225 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:59:42,225 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:59:42,225 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 11:59:42,226 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 11:59:42,226 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 11:59:42,226 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 11:59:42,226 INFO L87 Difference]: Start difference. First operand 2434 states and 3271 transitions. cyclomatic complexity: 841 Second operand 5 states. [2018-11-18 11:59:42,330 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:59:42,330 INFO L93 Difference]: Finished difference Result 3984 states and 5317 transitions. [2018-11-18 11:59:42,330 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 11:59:42,330 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3984 states and 5317 transitions. [2018-11-18 11:59:42,341 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 3896 [2018-11-18 11:59:42,352 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3984 states to 3984 states and 5317 transitions. [2018-11-18 11:59:42,353 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3984 [2018-11-18 11:59:42,354 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3984 [2018-11-18 11:59:42,354 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3984 states and 5317 transitions. [2018-11-18 11:59:42,357 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:59:42,357 INFO L705 BuchiCegarLoop]: Abstraction has 3984 states and 5317 transitions. [2018-11-18 11:59:42,358 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3984 states and 5317 transitions. [2018-11-18 11:59:42,381 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3984 to 2303. [2018-11-18 11:59:42,381 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2303 states. [2018-11-18 11:59:42,385 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2303 states to 2303 states and 3055 transitions. [2018-11-18 11:59:42,385 INFO L728 BuchiCegarLoop]: Abstraction has 2303 states and 3055 transitions. [2018-11-18 11:59:42,386 INFO L608 BuchiCegarLoop]: Abstraction has 2303 states and 3055 transitions. [2018-11-18 11:59:42,386 INFO L442 BuchiCegarLoop]: ======== Iteration 16============ [2018-11-18 11:59:42,386 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2303 states and 3055 transitions. [2018-11-18 11:59:42,392 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2223 [2018-11-18 11:59:42,392 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:59:42,392 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:59:42,393 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:42,393 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:42,393 INFO L794 eck$LassoCheckResult]: Stem: 35007#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 34910#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 34911#L768 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 35086#L348 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34863#L355 assume 1 == ~m_i~0;~m_st~0 := 0; 34864#L355-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34868#L360-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34753#L365-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34754#L370-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34835#L375-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34836#L516 assume !(0 == ~M_E~0); 34952#L516-2 assume !(0 == ~T1_E~0); 34659#L521-1 assume !(0 == ~T2_E~0); 34660#L526-1 assume !(0 == ~T3_E~0); 34873#L531-1 assume !(0 == ~T4_E~0); 34874#L536-1 assume !(0 == ~E_M~0); 34771#L541-1 assume !(0 == ~E_1~0); 34772#L546-1 assume !(0 == ~E_2~0); 34842#L551-1 assume !(0 == ~E_3~0); 34710#L556-1 assume !(0 == ~E_4~0); 34711#L561-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 34908#L252 assume !(1 == ~m_pc~0); 34891#L252-2 is_master_triggered_~__retres1~0 := 0; 34892#L263 is_master_triggered_#res := is_master_triggered_~__retres1~0; 34909#L264 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 34983#L639 assume !(0 != activate_threads_~tmp~1); 34837#L639-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 34838#L271 assume !(1 == ~t1_pc~0); 35070#L271-2 is_transmit1_triggered_~__retres1~1 := 0; 35072#L282 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 35073#L283 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 35103#L647 assume !(0 != activate_threads_~tmp___0~0); 35104#L647-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 34668#L290 assume !(1 == ~t2_pc~0); 34656#L290-2 is_transmit2_triggered_~__retres1~2 := 0; 34657#L301 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 34671#L302 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 34720#L655 assume !(0 != activate_threads_~tmp___1~0); 34702#L655-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 34703#L309 assume !(1 == ~t3_pc~0); 34758#L309-2 is_transmit3_triggered_~__retres1~3 := 0; 34759#L320 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 34755#L321 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 34756#L663 assume !(0 != activate_threads_~tmp___2~0); 34881#L663-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 34882#L328 assume !(1 == ~t4_pc~0); 34915#L328-2 is_transmit4_triggered_~__retres1~4 := 0; 34980#L339 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 34912#L340 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 34913#L671 assume !(0 != activate_threads_~tmp___3~0); 35041#L671-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34769#L574 assume !(1 == ~M_E~0); 34770#L574-2 assume !(1 == ~T1_E~0); 34773#L579-1 assume !(1 == ~T2_E~0); 34839#L584-1 assume !(1 == ~T3_E~0); 34708#L589-1 assume !(1 == ~T4_E~0); 34709#L594-1 assume !(1 == ~E_M~0); 34615#L599-1 assume !(1 == ~E_1~0); 34616#L604-1 assume !(1 == ~E_2~0); 34682#L609-1 assume !(1 == ~E_3~0); 34683#L614-1 assume !(1 == ~E_4~0); 34883#L619-1 assume { :end_inline_reset_delta_events } true; 34884#L805-3 assume true; 35436#L805-1 assume !false; 35430#L806 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 35426#L491 [2018-11-18 11:59:42,393 INFO L796 eck$LassoCheckResult]: Loop: 35426#L491 assume true; 35424#L425-1 assume !false; 35422#L426 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 35419#L388 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 35417#L415 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 35415#L416 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 35411#L430 assume 0 != eval_~tmp~0; 35408#L430-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 35406#L438 assume !(0 != eval_~tmp_ndt_1~0); 35404#L435 assume !(0 == ~t1_st~0); 35400#L449 assume !(0 == ~t2_st~0); 35398#L463 assume !(0 == ~t3_st~0); 35433#L477 assume !(0 == ~t4_st~0); 35426#L491 [2018-11-18 11:59:42,393 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:42,393 INFO L82 PathProgramCache]: Analyzing trace with hash 1231592563, now seen corresponding path program 1 times [2018-11-18 11:59:42,394 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:42,394 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:42,394 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:42,394 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:59:42,395 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:42,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:59:42,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:59:42,412 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:42,412 INFO L82 PathProgramCache]: Analyzing trace with hash -987311198, now seen corresponding path program 1 times [2018-11-18 11:59:42,412 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:42,412 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:42,412 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:42,413 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:59:42,413 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:42,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:59:42,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:59:42,417 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:42,417 INFO L82 PathProgramCache]: Analyzing trace with hash -1067483024, now seen corresponding path program 1 times [2018-11-18 11:59:42,418 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:42,418 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:42,418 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:42,418 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:59:42,418 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:42,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:59:42,482 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:59:42,482 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:59:42,482 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 11:59:42,545 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 11:59:42,545 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 11:59:42,545 INFO L87 Difference]: Start difference. First operand 2303 states and 3055 transitions. cyclomatic complexity: 758 Second operand 3 states. [2018-11-18 11:59:42,563 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:59:42,563 INFO L93 Difference]: Finished difference Result 3843 states and 5062 transitions. [2018-11-18 11:59:42,563 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 11:59:42,563 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3843 states and 5062 transitions. [2018-11-18 11:59:42,573 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 3689 [2018-11-18 11:59:42,584 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3843 states to 3843 states and 5062 transitions. [2018-11-18 11:59:42,584 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3843 [2018-11-18 11:59:42,586 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3843 [2018-11-18 11:59:42,586 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3843 states and 5062 transitions. [2018-11-18 11:59:42,589 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:59:42,589 INFO L705 BuchiCegarLoop]: Abstraction has 3843 states and 5062 transitions. [2018-11-18 11:59:42,591 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3843 states and 5062 transitions. [2018-11-18 11:59:42,616 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3843 to 3843. [2018-11-18 11:59:42,616 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3843 states. [2018-11-18 11:59:42,622 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3843 states to 3843 states and 5062 transitions. [2018-11-18 11:59:42,622 INFO L728 BuchiCegarLoop]: Abstraction has 3843 states and 5062 transitions. [2018-11-18 11:59:42,622 INFO L608 BuchiCegarLoop]: Abstraction has 3843 states and 5062 transitions. [2018-11-18 11:59:42,622 INFO L442 BuchiCegarLoop]: ======== Iteration 17============ [2018-11-18 11:59:42,622 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3843 states and 5062 transitions. [2018-11-18 11:59:42,631 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 3689 [2018-11-18 11:59:42,631 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:59:42,631 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:59:42,631 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:42,631 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:42,632 INFO L794 eck$LassoCheckResult]: Stem: 41153#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 41062#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 41063#L768 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 41223#L348 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41012#L355 assume 1 == ~m_i~0;~m_st~0 := 0; 41013#L355-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 41019#L360-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40898#L365-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40899#L370-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40983#L375-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40984#L516 assume !(0 == ~M_E~0); 41103#L516-2 assume !(0 == ~T1_E~0); 40817#L521-1 assume !(0 == ~T2_E~0); 40818#L526-1 assume !(0 == ~T3_E~0); 41024#L531-1 assume !(0 == ~T4_E~0); 41025#L536-1 assume !(0 == ~E_M~0); 40916#L541-1 assume !(0 == ~E_1~0); 40917#L546-1 assume !(0 == ~E_2~0); 40993#L551-1 assume !(0 == ~E_3~0); 40867#L556-1 assume !(0 == ~E_4~0); 40868#L561-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 41060#L252 assume !(1 == ~m_pc~0); 41043#L252-2 is_master_triggered_~__retres1~0 := 0; 41044#L263 is_master_triggered_#res := is_master_triggered_~__retres1~0; 41061#L264 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 41137#L639 assume !(0 != activate_threads_~tmp~1); 40988#L639-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 40989#L271 assume !(1 == ~t1_pc~0); 41208#L271-2 is_transmit1_triggered_~__retres1~1 := 0; 41226#L282 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 42886#L283 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 42884#L647 assume !(0 != activate_threads_~tmp___0~0); 42882#L647-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 42880#L290 assume !(1 == ~t2_pc~0); 42878#L290-2 is_transmit2_triggered_~__retres1~2 := 0; 42876#L301 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 42874#L302 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 42872#L655 assume !(0 != activate_threads_~tmp___1~0); 42870#L655-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 42868#L309 assume !(1 == ~t3_pc~0); 42865#L309-2 is_transmit3_triggered_~__retres1~3 := 0; 42863#L320 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 42860#L321 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 42858#L663 assume !(0 != activate_threads_~tmp___2~0); 42856#L663-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 42854#L328 assume !(1 == ~t4_pc~0); 42851#L328-2 is_transmit4_triggered_~__retres1~4 := 0; 42848#L339 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 42846#L340 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 42844#L671 assume !(0 != activate_threads_~tmp___3~0); 42842#L671-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42840#L574 assume !(1 == ~M_E~0); 42838#L574-2 assume !(1 == ~T1_E~0); 42836#L579-1 assume !(1 == ~T2_E~0); 42834#L584-1 assume !(1 == ~T3_E~0); 42832#L589-1 assume !(1 == ~T4_E~0); 42830#L594-1 assume !(1 == ~E_M~0); 42828#L599-1 assume !(1 == ~E_1~0); 42826#L604-1 assume !(1 == ~E_2~0); 42824#L609-1 assume !(1 == ~E_3~0); 41252#L614-1 assume !(1 == ~E_4~0); 41035#L619-1 assume { :end_inline_reset_delta_events } true; 41036#L805-3 assume true; 42963#L805-1 assume !false; 41791#L806 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 41790#L491 [2018-11-18 11:59:42,632 INFO L796 eck$LassoCheckResult]: Loop: 41790#L491 assume true; 41782#L425-1 assume !false; 41783#L426 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 41772#L388 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 41773#L415 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 41764#L416 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 41765#L430 assume 0 != eval_~tmp~0; 41756#L430-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 41757#L438 assume !(0 != eval_~tmp_ndt_1~0); 42730#L435 assume !(0 == ~t1_st~0); 43043#L449 assume !(0 == ~t2_st~0); 43035#L463 assume !(0 == ~t3_st~0); 41794#L477 assume !(0 == ~t4_st~0); 41790#L491 [2018-11-18 11:59:42,632 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:42,632 INFO L82 PathProgramCache]: Analyzing trace with hash 1433416497, now seen corresponding path program 1 times [2018-11-18 11:59:42,632 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:42,632 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:42,633 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:42,633 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:59:42,633 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:42,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:59:42,690 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:59:42,690 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:59:42,690 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 11:59:42,690 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 11:59:42,690 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:42,690 INFO L82 PathProgramCache]: Analyzing trace with hash -987311198, now seen corresponding path program 2 times [2018-11-18 11:59:42,690 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:42,691 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:42,691 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:42,691 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:59:42,691 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:42,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:59:42,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:59:42,773 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 11:59:42,773 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 11:59:42,774 INFO L87 Difference]: Start difference. First operand 3843 states and 5062 transitions. cyclomatic complexity: 1225 Second operand 3 states. [2018-11-18 11:59:42,781 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:59:42,781 INFO L93 Difference]: Finished difference Result 3781 states and 4980 transitions. [2018-11-18 11:59:42,782 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 11:59:42,782 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3781 states and 4980 transitions. [2018-11-18 11:59:42,792 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 3689 [2018-11-18 11:59:42,803 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3781 states to 3781 states and 4980 transitions. [2018-11-18 11:59:42,804 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3781 [2018-11-18 11:59:42,805 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3781 [2018-11-18 11:59:42,805 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3781 states and 4980 transitions. [2018-11-18 11:59:42,808 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:59:42,808 INFO L705 BuchiCegarLoop]: Abstraction has 3781 states and 4980 transitions. [2018-11-18 11:59:42,810 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3781 states and 4980 transitions. [2018-11-18 11:59:42,829 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3781 to 3781. [2018-11-18 11:59:42,829 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3781 states. [2018-11-18 11:59:42,834 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3781 states to 3781 states and 4980 transitions. [2018-11-18 11:59:42,834 INFO L728 BuchiCegarLoop]: Abstraction has 3781 states and 4980 transitions. [2018-11-18 11:59:42,834 INFO L608 BuchiCegarLoop]: Abstraction has 3781 states and 4980 transitions. [2018-11-18 11:59:42,834 INFO L442 BuchiCegarLoop]: ======== Iteration 18============ [2018-11-18 11:59:42,834 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3781 states and 4980 transitions. [2018-11-18 11:59:42,839 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 3689 [2018-11-18 11:59:42,839 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:59:42,839 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:59:42,839 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:42,839 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:42,839 INFO L794 eck$LassoCheckResult]: Stem: 48784#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 48696#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 48697#L768 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 48850#L348 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 48647#L355 assume 1 == ~m_i~0;~m_st~0 := 0; 48648#L355-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 48654#L360-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 48536#L365-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 48537#L370-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 48619#L375-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 48620#L516 assume !(0 == ~M_E~0); 48735#L516-2 assume !(0 == ~T1_E~0); 48443#L521-1 assume !(0 == ~T2_E~0); 48444#L526-1 assume !(0 == ~T3_E~0); 48659#L531-1 assume !(0 == ~T4_E~0); 48660#L536-1 assume !(0 == ~E_M~0); 48554#L541-1 assume !(0 == ~E_1~0); 48555#L546-1 assume !(0 == ~E_2~0); 48627#L551-1 assume !(0 == ~E_3~0); 48494#L556-1 assume !(0 == ~E_4~0); 48495#L561-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 48694#L252 assume !(1 == ~m_pc~0); 48677#L252-2 is_master_triggered_~__retres1~0 := 0; 48678#L263 is_master_triggered_#res := is_master_triggered_~__retres1~0; 48695#L264 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 48767#L639 assume !(0 != activate_threads_~tmp~1); 48622#L639-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 48623#L271 assume !(1 == ~t1_pc~0); 48835#L271-2 is_transmit1_triggered_~__retres1~1 := 0; 48837#L282 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 48838#L283 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 48876#L647 assume !(0 != activate_threads_~tmp___0~0); 48877#L647-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 48453#L290 assume !(1 == ~t2_pc~0); 48441#L290-2 is_transmit2_triggered_~__retres1~2 := 0; 48442#L301 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 48454#L302 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 48502#L655 assume !(0 != activate_threads_~tmp___1~0); 48485#L655-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 48486#L309 assume !(1 == ~t3_pc~0); 48541#L309-2 is_transmit3_triggered_~__retres1~3 := 0; 48542#L320 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 48538#L321 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 48539#L663 assume !(0 != activate_threads_~tmp___2~0); 48668#L663-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 48669#L328 assume !(1 == ~t4_pc~0); 48701#L328-2 is_transmit4_triggered_~__retres1~4 := 0; 48762#L339 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 48698#L340 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 48699#L671 assume !(0 != activate_threads_~tmp___3~0); 48812#L671-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48550#L574 assume !(1 == ~M_E~0); 48551#L574-2 assume !(1 == ~T1_E~0); 48556#L579-1 assume !(1 == ~T2_E~0); 48624#L584-1 assume !(1 == ~T3_E~0); 48488#L589-1 assume !(1 == ~T4_E~0); 48489#L594-1 assume !(1 == ~E_M~0); 48399#L599-1 assume !(1 == ~E_1~0); 48400#L604-1 assume !(1 == ~E_2~0); 48467#L609-1 assume !(1 == ~E_3~0); 48468#L614-1 assume !(1 == ~E_4~0); 48670#L619-1 assume { :end_inline_reset_delta_events } true; 48671#L805-3 assume true; 50411#L805-1 assume !false; 50379#L806 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 50372#L491 [2018-11-18 11:59:42,840 INFO L796 eck$LassoCheckResult]: Loop: 50372#L491 assume true; 50366#L425-1 assume !false; 50361#L426 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 50355#L388 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 50351#L415 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 50346#L416 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 50342#L430 assume 0 != eval_~tmp~0; 50339#L430-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 50335#L438 assume !(0 != eval_~tmp_ndt_1~0); 50336#L435 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 50497#L452 assume !(0 != eval_~tmp_ndt_2~0); 50493#L449 assume !(0 == ~t2_st~0); 50456#L463 assume !(0 == ~t3_st~0); 50382#L477 assume !(0 == ~t4_st~0); 50372#L491 [2018-11-18 11:59:42,840 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:42,840 INFO L82 PathProgramCache]: Analyzing trace with hash 1231592563, now seen corresponding path program 2 times [2018-11-18 11:59:42,840 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:42,840 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:42,840 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:42,840 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 11:59:42,840 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:42,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:59:42,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:59:42,854 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:42,854 INFO L82 PathProgramCache]: Analyzing trace with hash -690004518, now seen corresponding path program 1 times [2018-11-18 11:59:42,854 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:42,854 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:42,855 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:42,855 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 11:59:42,855 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:42,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:59:42,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:59:42,859 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:42,859 INFO L82 PathProgramCache]: Analyzing trace with hash 1119636172, now seen corresponding path program 1 times [2018-11-18 11:59:42,859 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:42,859 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:42,860 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:42,860 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:59:42,860 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:42,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:59:42,928 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:59:42,928 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:59:42,928 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 11:59:43,231 WARN L180 SmtUtils]: Spent 301.00 ms on a formula simplification. DAG size of input: 32 DAG size of output: 30 [2018-11-18 11:59:43,247 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 11:59:43,248 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 11:59:43,248 INFO L87 Difference]: Start difference. First operand 3781 states and 4980 transitions. cyclomatic complexity: 1205 Second operand 3 states. [2018-11-18 11:59:43,318 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:59:43,319 INFO L93 Difference]: Finished difference Result 4968 states and 6524 transitions. [2018-11-18 11:59:43,319 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 11:59:43,319 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4968 states and 6524 transitions. [2018-11-18 11:59:43,331 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4872 [2018-11-18 11:59:43,342 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4968 states to 4968 states and 6524 transitions. [2018-11-18 11:59:43,342 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4968 [2018-11-18 11:59:43,346 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4968 [2018-11-18 11:59:43,347 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4968 states and 6524 transitions. [2018-11-18 11:59:43,351 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:59:43,351 INFO L705 BuchiCegarLoop]: Abstraction has 4968 states and 6524 transitions. [2018-11-18 11:59:43,354 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4968 states and 6524 transitions. [2018-11-18 11:59:43,383 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4968 to 4816. [2018-11-18 11:59:43,384 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4816 states. [2018-11-18 11:59:43,389 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4816 states to 4816 states and 6332 transitions. [2018-11-18 11:59:43,389 INFO L728 BuchiCegarLoop]: Abstraction has 4816 states and 6332 transitions. [2018-11-18 11:59:43,389 INFO L608 BuchiCegarLoop]: Abstraction has 4816 states and 6332 transitions. [2018-11-18 11:59:43,389 INFO L442 BuchiCegarLoop]: ======== Iteration 19============ [2018-11-18 11:59:43,389 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4816 states and 6332 transitions. [2018-11-18 11:59:43,400 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4720 [2018-11-18 11:59:43,400 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:59:43,400 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:59:43,400 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:43,401 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:43,401 INFO L794 eck$LassoCheckResult]: Stem: 57552#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 57459#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 57460#L768 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 57629#L348 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 57408#L355 assume 1 == ~m_i~0;~m_st~0 := 0; 57409#L355-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 57415#L360-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 57293#L365-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 57294#L370-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 57381#L375-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 57382#L516 assume !(0 == ~M_E~0); 57501#L516-2 assume !(0 == ~T1_E~0); 57204#L521-1 assume !(0 == ~T2_E~0); 57205#L526-1 assume !(0 == ~T3_E~0); 57420#L531-1 assume !(0 == ~T4_E~0); 57421#L536-1 assume !(0 == ~E_M~0); 57311#L541-1 assume !(0 == ~E_1~0); 57312#L546-1 assume !(0 == ~E_2~0); 57389#L551-1 assume !(0 == ~E_3~0); 57257#L556-1 assume !(0 == ~E_4~0); 57258#L561-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 57457#L252 assume !(1 == ~m_pc~0); 57440#L252-2 is_master_triggered_~__retres1~0 := 0; 57441#L263 is_master_triggered_#res := is_master_triggered_~__retres1~0; 57458#L264 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 57537#L639 assume !(0 != activate_threads_~tmp~1); 57384#L639-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 57385#L271 assume !(1 == ~t1_pc~0); 57610#L271-2 is_transmit1_triggered_~__retres1~1 := 0; 57612#L282 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 57613#L283 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 57653#L647 assume !(0 != activate_threads_~tmp___0~0); 57654#L647-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 57215#L290 assume !(1 == ~t2_pc~0); 57202#L290-2 is_transmit2_triggered_~__retres1~2 := 0; 57203#L301 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 57216#L302 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 57265#L655 assume !(0 != activate_threads_~tmp___1~0); 57248#L655-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 57249#L309 assume !(1 == ~t3_pc~0); 57298#L309-2 is_transmit3_triggered_~__retres1~3 := 0; 57299#L320 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 57295#L321 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 57296#L663 assume !(0 != activate_threads_~tmp___2~0); 57429#L663-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 57430#L328 assume !(1 == ~t4_pc~0); 57464#L328-2 is_transmit4_triggered_~__retres1~4 := 0; 57531#L339 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 57461#L340 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 57462#L671 assume !(0 != activate_threads_~tmp___3~0); 57581#L671-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57307#L574 assume !(1 == ~M_E~0); 57308#L574-2 assume !(1 == ~T1_E~0); 57313#L579-1 assume !(1 == ~T2_E~0); 57386#L584-1 assume !(1 == ~T3_E~0); 57251#L589-1 assume !(1 == ~T4_E~0); 57252#L594-1 assume !(1 == ~E_M~0); 57157#L599-1 assume !(1 == ~E_1~0); 57158#L604-1 assume !(1 == ~E_2~0); 57229#L609-1 assume !(1 == ~E_3~0); 57230#L614-1 assume !(1 == ~E_4~0); 57431#L619-1 assume { :end_inline_reset_delta_events } true; 57432#L805-3 assume true; 60123#L805-1 assume !false; 60113#L806 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 60108#L491 [2018-11-18 11:59:43,401 INFO L796 eck$LassoCheckResult]: Loop: 60108#L491 assume true; 60105#L425-1 assume !false; 60102#L426 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 60099#L388 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 60096#L415 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 60093#L416 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 60090#L430 assume 0 != eval_~tmp~0; 60068#L430-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 60062#L438 assume !(0 != eval_~tmp_ndt_1~0); 60058#L435 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 59360#L452 assume !(0 != eval_~tmp_ndt_2~0); 60054#L449 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 60146#L466 assume !(0 != eval_~tmp_ndt_3~0); 60127#L463 assume !(0 == ~t3_st~0); 60116#L477 assume !(0 == ~t4_st~0); 60108#L491 [2018-11-18 11:59:43,401 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:43,401 INFO L82 PathProgramCache]: Analyzing trace with hash 1231592563, now seen corresponding path program 3 times [2018-11-18 11:59:43,401 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:43,401 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:43,402 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:43,402 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:59:43,402 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:43,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:59:43,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:59:43,423 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:43,423 INFO L82 PathProgramCache]: Analyzing trace with hash 79919379, now seen corresponding path program 1 times [2018-11-18 11:59:43,424 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:43,424 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:43,424 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:43,424 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 11:59:43,424 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:43,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:59:43,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:59:43,428 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:43,428 INFO L82 PathProgramCache]: Analyzing trace with hash 344205921, now seen corresponding path program 1 times [2018-11-18 11:59:43,428 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:43,428 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:43,429 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:43,429 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:59:43,429 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:43,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:59:43,478 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:59:43,479 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:59:43,479 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 11:59:43,540 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 11:59:43,540 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 11:59:43,540 INFO L87 Difference]: Start difference. First operand 4816 states and 6332 transitions. cyclomatic complexity: 1522 Second operand 3 states. [2018-11-18 11:59:43,678 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:59:43,678 INFO L93 Difference]: Finished difference Result 8644 states and 11314 transitions. [2018-11-18 11:59:43,679 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 11:59:43,679 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8644 states and 11314 transitions. [2018-11-18 11:59:43,703 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 8520 [2018-11-18 11:59:43,734 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8644 states to 8644 states and 11314 transitions. [2018-11-18 11:59:43,734 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8644 [2018-11-18 11:59:43,739 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8644 [2018-11-18 11:59:43,739 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8644 states and 11314 transitions. [2018-11-18 11:59:43,743 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:59:43,744 INFO L705 BuchiCegarLoop]: Abstraction has 8644 states and 11314 transitions. [2018-11-18 11:59:43,748 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8644 states and 11314 transitions. [2018-11-18 11:59:43,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8644 to 8356. [2018-11-18 11:59:43,796 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8356 states. [2018-11-18 11:59:43,806 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8356 states to 8356 states and 10954 transitions. [2018-11-18 11:59:43,806 INFO L728 BuchiCegarLoop]: Abstraction has 8356 states and 10954 transitions. [2018-11-18 11:59:43,806 INFO L608 BuchiCegarLoop]: Abstraction has 8356 states and 10954 transitions. [2018-11-18 11:59:43,806 INFO L442 BuchiCegarLoop]: ======== Iteration 20============ [2018-11-18 11:59:43,806 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8356 states and 10954 transitions. [2018-11-18 11:59:43,825 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 8232 [2018-11-18 11:59:43,825 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:59:43,825 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:59:43,825 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:43,825 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:43,826 INFO L794 eck$LassoCheckResult]: Stem: 71023#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 70924#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 70925#L768 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 71096#L348 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 70875#L355 assume 1 == ~m_i~0;~m_st~0 := 0; 70876#L355-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 70880#L360-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 70755#L365-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 70756#L370-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 70845#L375-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 70846#L516 assume !(0 == ~M_E~0); 70965#L516-2 assume !(0 == ~T1_E~0); 70673#L521-1 assume !(0 == ~T2_E~0); 70674#L526-1 assume !(0 == ~T3_E~0); 70885#L531-1 assume !(0 == ~T4_E~0); 70886#L536-1 assume !(0 == ~E_M~0); 70773#L541-1 assume !(0 == ~E_1~0); 70774#L546-1 assume !(0 == ~E_2~0); 70852#L551-1 assume !(0 == ~E_3~0); 70722#L556-1 assume !(0 == ~E_4~0); 70723#L561-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 70922#L252 assume !(1 == ~m_pc~0); 70904#L252-2 is_master_triggered_~__retres1~0 := 0; 70905#L263 is_master_triggered_#res := is_master_triggered_~__retres1~0; 70923#L264 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 71004#L639 assume !(0 != activate_threads_~tmp~1); 70847#L639-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 70848#L271 assume !(1 == ~t1_pc~0); 71077#L271-2 is_transmit1_triggered_~__retres1~1 := 0; 71079#L282 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 71080#L283 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 71123#L647 assume !(0 != activate_threads_~tmp___0~0); 71124#L647-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 70682#L290 assume !(1 == ~t2_pc~0); 70670#L290-2 is_transmit2_triggered_~__retres1~2 := 0; 70671#L301 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 70685#L302 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 70732#L655 assume !(0 != activate_threads_~tmp___1~0); 70714#L655-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 70715#L309 assume !(1 == ~t3_pc~0); 70760#L309-2 is_transmit3_triggered_~__retres1~3 := 0; 70761#L320 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 70757#L321 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 70758#L663 assume !(0 != activate_threads_~tmp___2~0); 70893#L663-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 70894#L328 assume !(1 == ~t4_pc~0); 70929#L328-2 is_transmit4_triggered_~__retres1~4 := 0; 70997#L339 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 70926#L340 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 70927#L671 assume !(0 != activate_threads_~tmp___3~0); 71052#L671-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 70771#L574 assume !(1 == ~M_E~0); 70772#L574-2 assume !(1 == ~T1_E~0); 70775#L579-1 assume !(1 == ~T2_E~0); 70849#L584-1 assume !(1 == ~T3_E~0); 70720#L589-1 assume !(1 == ~T4_E~0); 70721#L594-1 assume !(1 == ~E_M~0); 70625#L599-1 assume !(1 == ~E_1~0); 70626#L604-1 assume !(1 == ~E_2~0); 70694#L609-1 assume !(1 == ~E_3~0); 70695#L614-1 assume !(1 == ~E_4~0); 70895#L619-1 assume { :end_inline_reset_delta_events } true; 70896#L805-3 assume true; 74279#L805-1 assume !false; 74080#L806 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 74075#L491 [2018-11-18 11:59:43,826 INFO L796 eck$LassoCheckResult]: Loop: 74075#L491 assume true; 74068#L425-1 assume !false; 74060#L426 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 74053#L388 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 74045#L415 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 74044#L416 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 74043#L430 assume 0 != eval_~tmp~0; 74041#L430-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 74038#L438 assume !(0 != eval_~tmp_ndt_1~0); 74036#L435 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 73884#L452 assume !(0 != eval_~tmp_ndt_2~0); 74034#L449 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 74051#L466 assume !(0 != eval_~tmp_ndt_3~0); 74052#L463 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 74085#L480 assume !(0 != eval_~tmp_ndt_4~0); 74083#L477 assume !(0 == ~t4_st~0); 74075#L491 [2018-11-18 11:59:43,826 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:43,826 INFO L82 PathProgramCache]: Analyzing trace with hash 1231592563, now seen corresponding path program 4 times [2018-11-18 11:59:43,826 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:43,826 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:43,827 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:43,827 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:59:43,827 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:43,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:59:43,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:59:43,841 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:43,841 INFO L82 PathProgramCache]: Analyzing trace with hash -1817619351, now seen corresponding path program 1 times [2018-11-18 11:59:43,841 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:43,841 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:43,842 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:43,842 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 11:59:43,842 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:43,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:59:43,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:59:43,846 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:43,846 INFO L82 PathProgramCache]: Analyzing trace with hash 2080296155, now seen corresponding path program 1 times [2018-11-18 11:59:43,846 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:43,846 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:43,846 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:43,846 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:59:43,847 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:43,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 11:59:43,912 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 11:59:43,912 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 11:59:43,912 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 11:59:44,029 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 11:59:44,030 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 11:59:44,030 INFO L87 Difference]: Start difference. First operand 8356 states and 10954 transitions. cyclomatic complexity: 2604 Second operand 3 states. [2018-11-18 11:59:44,113 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 11:59:44,113 INFO L93 Difference]: Finished difference Result 14520 states and 18956 transitions. [2018-11-18 11:59:44,113 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 11:59:44,114 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14520 states and 18956 transitions. [2018-11-18 11:59:44,142 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 14340 [2018-11-18 11:59:44,169 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14520 states to 14520 states and 18956 transitions. [2018-11-18 11:59:44,169 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14520 [2018-11-18 11:59:44,178 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14520 [2018-11-18 11:59:44,178 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14520 states and 18956 transitions. [2018-11-18 11:59:44,187 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 11:59:44,187 INFO L705 BuchiCegarLoop]: Abstraction has 14520 states and 18956 transitions. [2018-11-18 11:59:44,196 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14520 states and 18956 transitions. [2018-11-18 11:59:44,303 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14520 to 14280. [2018-11-18 11:59:44,303 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14280 states. [2018-11-18 11:59:44,395 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14280 states to 14280 states and 18716 transitions. [2018-11-18 11:59:44,395 INFO L728 BuchiCegarLoop]: Abstraction has 14280 states and 18716 transitions. [2018-11-18 11:59:44,396 INFO L608 BuchiCegarLoop]: Abstraction has 14280 states and 18716 transitions. [2018-11-18 11:59:44,396 INFO L442 BuchiCegarLoop]: ======== Iteration 21============ [2018-11-18 11:59:44,396 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14280 states and 18716 transitions. [2018-11-18 11:59:44,425 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 14100 [2018-11-18 11:59:44,425 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 11:59:44,425 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 11:59:44,425 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:44,425 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 11:59:44,426 INFO L794 eck$LassoCheckResult]: Stem: 93913#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 93820#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 93821#L768 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 93993#L348 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 93764#L355 assume 1 == ~m_i~0;~m_st~0 := 0; 93765#L355-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 93771#L360-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 93643#L365-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 93644#L370-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 93734#L375-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 93735#L516 assume !(0 == ~M_E~0); 93861#L516-2 assume !(0 == ~T1_E~0); 93555#L521-1 assume !(0 == ~T2_E~0); 93556#L526-1 assume !(0 == ~T3_E~0); 93776#L531-1 assume !(0 == ~T4_E~0); 93777#L536-1 assume !(0 == ~E_M~0); 93661#L541-1 assume !(0 == ~E_1~0); 93662#L546-1 assume !(0 == ~E_2~0); 93742#L551-1 assume !(0 == ~E_3~0); 93604#L556-1 assume !(0 == ~E_4~0); 93605#L561-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 93818#L252 assume !(1 == ~m_pc~0); 93799#L252-2 is_master_triggered_~__retres1~0 := 0; 93800#L263 is_master_triggered_#res := is_master_triggered_~__retres1~0; 93819#L264 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 93898#L639 assume !(0 != activate_threads_~tmp~1); 93737#L639-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 93738#L271 assume !(1 == ~t1_pc~0); 93977#L271-2 is_transmit1_triggered_~__retres1~1 := 0; 93979#L282 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 93980#L283 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 94026#L647 assume !(0 != activate_threads_~tmp___0~0); 94027#L647-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 93564#L290 assume !(1 == ~t2_pc~0); 93553#L290-2 is_transmit2_triggered_~__retres1~2 := 0; 93554#L301 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 93565#L302 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 93612#L655 assume !(0 != activate_threads_~tmp___1~0); 93595#L655-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 93596#L309 assume !(1 == ~t3_pc~0); 93648#L309-2 is_transmit3_triggered_~__retres1~3 := 0; 93649#L320 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 93645#L321 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 93646#L663 assume !(0 != activate_threads_~tmp___2~0); 93786#L663-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 93787#L328 assume !(1 == ~t4_pc~0); 93825#L328-2 is_transmit4_triggered_~__retres1~4 := 0; 93891#L339 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 93822#L340 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 93823#L671 assume !(0 != activate_threads_~tmp___3~0); 93943#L671-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 93657#L574 assume !(1 == ~M_E~0); 93658#L574-2 assume !(1 == ~T1_E~0); 93663#L579-1 assume !(1 == ~T2_E~0); 93739#L584-1 assume !(1 == ~T3_E~0); 93598#L589-1 assume !(1 == ~T4_E~0); 93599#L594-1 assume !(1 == ~E_M~0); 93509#L599-1 assume !(1 == ~E_1~0); 93510#L604-1 assume !(1 == ~E_2~0); 93576#L609-1 assume !(1 == ~E_3~0); 93577#L614-1 assume !(1 == ~E_4~0); 93788#L619-1 assume { :end_inline_reset_delta_events } true; 93789#L805-3 assume true; 101321#L805-1 assume !false; 101310#L806 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 101308#L491 [2018-11-18 11:59:44,426 INFO L796 eck$LassoCheckResult]: Loop: 101308#L491 assume true; 101306#L425-1 assume !false; 101303#L426 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 101301#L388 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 101299#L415 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 101295#L416 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 101293#L430 assume 0 != eval_~tmp~0; 101290#L430-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 101287#L438 assume !(0 != eval_~tmp_ndt_1~0); 101285#L435 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 101163#L452 assume !(0 != eval_~tmp_ndt_2~0); 101283#L449 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 101896#L466 assume !(0 != eval_~tmp_ndt_3~0); 101318#L463 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 101315#L480 assume !(0 != eval_~tmp_ndt_4~0); 101313#L477 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 97672#L494 assume !(0 != eval_~tmp_ndt_5~0); 101308#L491 [2018-11-18 11:59:44,426 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:44,426 INFO L82 PathProgramCache]: Analyzing trace with hash 1231592563, now seen corresponding path program 5 times [2018-11-18 11:59:44,426 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:44,426 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:44,427 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:44,427 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:59:44,427 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:44,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:59:44,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:59:44,440 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:44,440 INFO L82 PathProgramCache]: Analyzing trace with hash -511628668, now seen corresponding path program 1 times [2018-11-18 11:59:44,440 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:44,440 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:44,441 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:44,441 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 11:59:44,441 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:44,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:59:44,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:59:44,445 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 11:59:44,445 INFO L82 PathProgramCache]: Analyzing trace with hash 64667730, now seen corresponding path program 1 times [2018-11-18 11:59:44,445 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 11:59:44,445 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 11:59:44,446 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:44,446 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 11:59:44,446 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 11:59:44,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:59:44,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 11:59:44,853 WARN L180 SmtUtils]: Spent 388.00 ms on a formula simplification. DAG size of input: 41 DAG size of output: 39 [2018-11-18 11:59:45,220 WARN L180 SmtUtils]: Spent 327.00 ms on a formula simplification. DAG size of input: 167 DAG size of output: 112 [2018-11-18 11:59:45,328 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 18.11 11:59:45 BoogieIcfgContainer [2018-11-18 11:59:45,328 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2018-11-18 11:59:45,329 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-18 11:59:45,329 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-18 11:59:45,329 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-18 11:59:45,329 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 11:59:37" (3/4) ... [2018-11-18 11:59:45,332 INFO L141 WitnessPrinter]: Generating witness for non-termination counterexample [2018-11-18 11:59:45,402 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_15d9ffa9-9d9e-4b80-b795-6423af48da6b/bin-2019/uautomizer/witness.graphml [2018-11-18 11:59:45,402 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-18 11:59:45,402 INFO L168 Benchmark]: Toolchain (without parser) took 9968.90 ms. Allocated memory was 1.0 GB in the beginning and 1.3 GB in the end (delta: 317.7 MB). Free memory was 953.1 MB in the beginning and 1.0 GB in the end (delta: -71.2 MB). Peak memory consumption was 246.6 MB. Max. memory is 11.5 GB. [2018-11-18 11:59:45,403 INFO L168 Benchmark]: CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 979.9 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 11:59:45,403 INFO L168 Benchmark]: CACSL2BoogieTranslator took 249.97 ms. Allocated memory is still 1.0 GB. Free memory was 953.1 MB in the beginning and 934.3 MB in the end (delta: 18.8 MB). Peak memory consumption was 18.8 MB. Max. memory is 11.5 GB. [2018-11-18 11:59:45,406 INFO L168 Benchmark]: Boogie Procedure Inliner took 92.82 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 138.9 MB). Free memory was 934.3 MB in the beginning and 1.1 GB in the end (delta: -202.2 MB). Peak memory consumption was 17.6 MB. Max. memory is 11.5 GB. [2018-11-18 11:59:45,406 INFO L168 Benchmark]: Boogie Preprocessor took 60.88 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 10.4 MB). Peak memory consumption was 10.4 MB. Max. memory is 11.5 GB. [2018-11-18 11:59:45,406 INFO L168 Benchmark]: RCFGBuilder took 1337.63 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 94.7 MB). Peak memory consumption was 94.7 MB. Max. memory is 11.5 GB. [2018-11-18 11:59:45,406 INFO L168 Benchmark]: BuchiAutomizer took 8150.77 ms. Allocated memory was 1.2 GB in the beginning and 1.3 GB in the end (delta: 178.8 MB). Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: -1.2 MB). Peak memory consumption was 177.5 MB. Max. memory is 11.5 GB. [2018-11-18 11:59:45,407 INFO L168 Benchmark]: Witness Printer took 73.16 ms. Allocated memory is still 1.3 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 8.4 MB). Peak memory consumption was 8.4 MB. Max. memory is 11.5 GB. [2018-11-18 11:59:45,408 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 979.9 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 249.97 ms. Allocated memory is still 1.0 GB. Free memory was 953.1 MB in the beginning and 934.3 MB in the end (delta: 18.8 MB). Peak memory consumption was 18.8 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 92.82 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 138.9 MB). Free memory was 934.3 MB in the beginning and 1.1 GB in the end (delta: -202.2 MB). Peak memory consumption was 17.6 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 60.88 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 10.4 MB). Peak memory consumption was 10.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1337.63 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 94.7 MB). Peak memory consumption was 94.7 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 8150.77 ms. Allocated memory was 1.2 GB in the beginning and 1.3 GB in the end (delta: 178.8 MB). Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: -1.2 MB). Peak memory consumption was 177.5 MB. Max. memory is 11.5 GB. * Witness Printer took 73.16 ms. Allocated memory is still 1.3 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 8.4 MB). Peak memory consumption was 8.4 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 20 terminating modules (20 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.20 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 14280 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 8.0s and 21 iterations. TraceHistogramMax:1. Analysis of lassos took 4.1s. Construction of modules took 2.0s. Büchi inclusion checks took 0.5s. Highest rank in rank-based complementation 0. Minimization of det autom 20. Minimization of nondet autom 0. Automata minimization 0.6s AutomataMinimizationTime, 20 MinimizatonAttempts, 3975 StatesRemovedByMinimization, 9 NontrivialMinimizations. Non-live state removal took 0.3s Buchi closure took 0.0s. Biggest automaton had 14280 states and ocurred in iteration 20. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 13046 SDtfs, 13392 SDslu, 9514 SDs, 0 SdLazy, 384 SolverSat, 210 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 2.0s Time LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc4 concLT0 SILN1 SILU0 SILI11 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 425]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {__retres1=0, t3_st=0, token=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@ec7a1a=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1feb029f=0, tmp=1, __retres1=0, kernel_st=1, t2_st=0, t4_i=1, E_3=2, t4_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1d8fd79=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5106e8d9=0, \result=0, E_1=2, tmp_ndt_2=0, \result=0, __retres1=0, \result=0, tmp_ndt_4=0, m_st=0, tmp___2=0, tmp___0=0, t3_pc=0, tmp=0, \result=0, __retres1=0, m_pc=0, \result=0, __retres1=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@37c4f37c=0, T2_E=2, tmp___0=0, t1_pc=0, E_2=2, E_4=2, __retres1=1, T1_E=2, tmp_ndt_1=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, t2_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3e94c84e=0, T4_E=2, t3_i=1, t4_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@401388a=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@33d3ed85=0, t1_st=0, tmp_ndt_5=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6827e49a=0, local=0, t2_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@44b4964c=0, tmp___3=0, E_M=2, tmp___1=0, T3_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@21a4a5bf=0, t1_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1f200860=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@467b17da=0, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 425]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int t4_pc = 0; [L19] int m_st ; [L20] int t1_st ; [L21] int t2_st ; [L22] int t3_st ; [L23] int t4_st ; [L24] int m_i ; [L25] int t1_i ; [L26] int t2_i ; [L27] int t3_i ; [L28] int t4_i ; [L29] int M_E = 2; [L30] int T1_E = 2; [L31] int T2_E = 2; [L32] int T3_E = 2; [L33] int T4_E = 2; [L34] int E_M = 2; [L35] int E_1 = 2; [L36] int E_2 = 2; [L37] int E_3 = 2; [L38] int E_4 = 2; [L45] int token ; [L47] int local ; [L850] int __retres1 ; [L854] CALL init_model() [L762] m_i = 1 [L763] t1_i = 1 [L764] t2_i = 1 [L765] t3_i = 1 [L766] RET t4_i = 1 [L854] init_model() [L855] CALL start_simulation() [L791] int kernel_st ; [L792] int tmp ; [L793] int tmp___0 ; [L797] kernel_st = 0 [L798] FCALL update_channels() [L799] CALL init_threads() [L355] COND TRUE m_i == 1 [L356] m_st = 0 [L360] COND TRUE t1_i == 1 [L361] t1_st = 0 [L365] COND TRUE t2_i == 1 [L366] t2_st = 0 [L370] COND TRUE t3_i == 1 [L371] t3_st = 0 [L375] COND TRUE t4_i == 1 [L376] RET t4_st = 0 [L799] init_threads() [L800] CALL fire_delta_events() [L516] COND FALSE !(M_E == 0) [L521] COND FALSE !(T1_E == 0) [L526] COND FALSE !(T2_E == 0) [L531] COND FALSE !(T3_E == 0) [L536] COND FALSE !(T4_E == 0) [L541] COND FALSE !(E_M == 0) [L546] COND FALSE !(E_1 == 0) [L551] COND FALSE !(E_2 == 0) [L556] COND FALSE !(E_3 == 0) [L561] COND FALSE, RET !(E_4 == 0) [L800] fire_delta_events() [L801] CALL activate_threads() [L629] int tmp ; [L630] int tmp___0 ; [L631] int tmp___1 ; [L632] int tmp___2 ; [L633] int tmp___3 ; [L637] CALL, EXPR is_master_triggered() [L249] int __retres1 ; [L252] COND FALSE !(m_pc == 1) [L262] __retres1 = 0 [L264] RET return (__retres1); [L637] EXPR is_master_triggered() [L637] tmp = is_master_triggered() [L639] COND FALSE !(\read(tmp)) [L645] CALL, EXPR is_transmit1_triggered() [L268] int __retres1 ; [L271] COND FALSE !(t1_pc == 1) [L281] __retres1 = 0 [L283] RET return (__retres1); [L645] EXPR is_transmit1_triggered() [L645] tmp___0 = is_transmit1_triggered() [L647] COND FALSE !(\read(tmp___0)) [L653] CALL, EXPR is_transmit2_triggered() [L287] int __retres1 ; [L290] COND FALSE !(t2_pc == 1) [L300] __retres1 = 0 [L302] RET return (__retres1); [L653] EXPR is_transmit2_triggered() [L653] tmp___1 = is_transmit2_triggered() [L655] COND FALSE !(\read(tmp___1)) [L661] CALL, EXPR is_transmit3_triggered() [L306] int __retres1 ; [L309] COND FALSE !(t3_pc == 1) [L319] __retres1 = 0 [L321] RET return (__retres1); [L661] EXPR is_transmit3_triggered() [L661] tmp___2 = is_transmit3_triggered() [L663] COND FALSE !(\read(tmp___2)) [L669] CALL, EXPR is_transmit4_triggered() [L325] int __retres1 ; [L328] COND FALSE !(t4_pc == 1) [L338] __retres1 = 0 [L340] RET return (__retres1); [L669] EXPR is_transmit4_triggered() [L669] tmp___3 = is_transmit4_triggered() [L671] COND FALSE, RET !(\read(tmp___3)) [L801] activate_threads() [L802] CALL reset_delta_events() [L574] COND FALSE !(M_E == 1) [L579] COND FALSE !(T1_E == 1) [L584] COND FALSE !(T2_E == 1) [L589] COND FALSE !(T3_E == 1) [L594] COND FALSE !(T4_E == 1) [L599] COND FALSE !(E_M == 1) [L604] COND FALSE !(E_1 == 1) [L609] COND FALSE !(E_2 == 1) [L614] COND FALSE !(E_3 == 1) [L619] COND FALSE, RET !(E_4 == 1) [L802] reset_delta_events() [L805] COND TRUE 1 [L808] kernel_st = 1 [L809] CALL eval() [L421] int tmp ; Loop: [L425] COND TRUE 1 [L428] CALL, EXPR exists_runnable_thread() [L385] int __retres1 ; [L388] COND TRUE m_st == 0 [L389] __retres1 = 1 [L416] RET return (__retres1); [L428] EXPR exists_runnable_thread() [L428] tmp = exists_runnable_thread() [L430] COND TRUE \read(tmp) [L435] COND TRUE m_st == 0 [L436] int tmp_ndt_1; [L437] tmp_ndt_1 = __VERIFIER_nondet_int() [L438] COND FALSE !(\read(tmp_ndt_1)) [L449] COND TRUE t1_st == 0 [L450] int tmp_ndt_2; [L451] tmp_ndt_2 = __VERIFIER_nondet_int() [L452] COND FALSE !(\read(tmp_ndt_2)) [L463] COND TRUE t2_st == 0 [L464] int tmp_ndt_3; [L465] tmp_ndt_3 = __VERIFIER_nondet_int() [L466] COND FALSE !(\read(tmp_ndt_3)) [L477] COND TRUE t3_st == 0 [L478] int tmp_ndt_4; [L479] tmp_ndt_4 = __VERIFIER_nondet_int() [L480] COND FALSE !(\read(tmp_ndt_4)) [L491] COND TRUE t4_st == 0 [L492] int tmp_ndt_5; [L493] tmp_ndt_5 = __VERIFIER_nondet_int() [L494] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...