./Ultimate.py --spec ../../sv-benchmarks/c/Termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.05_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 5842f4b8 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_d6bfc3eb-9043-4962-ad04-a405114524f4/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_d6bfc3eb-9043-4962-ad04-a405114524f4/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_d6bfc3eb-9043-4962-ad04-a405114524f4/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_d6bfc3eb-9043-4962-ad04-a405114524f4/bin-2019/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.05_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_d6bfc3eb-9043-4962-ad04-a405114524f4/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_d6bfc3eb-9043-4962-ad04-a405114524f4/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 27d160802d278384ef6d8db395ef2d19702d5645 ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.23-5842f4b [2018-11-18 15:17:48,001 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-18 15:17:48,003 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-18 15:17:48,011 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-18 15:17:48,011 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-18 15:17:48,011 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-18 15:17:48,012 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-18 15:17:48,013 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-18 15:17:48,014 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-18 15:17:48,015 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-18 15:17:48,016 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-18 15:17:48,016 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-18 15:17:48,016 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-18 15:17:48,017 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-18 15:17:48,018 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-18 15:17:48,018 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-18 15:17:48,019 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-18 15:17:48,020 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-18 15:17:48,021 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-18 15:17:48,023 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-18 15:17:48,023 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-18 15:17:48,024 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-18 15:17:48,026 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-18 15:17:48,026 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-18 15:17:48,026 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-18 15:17:48,026 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-18 15:17:48,027 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-18 15:17:48,027 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-18 15:17:48,028 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-18 15:17:48,029 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-18 15:17:48,029 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-18 15:17:48,030 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-18 15:17:48,030 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-18 15:17:48,030 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-18 15:17:48,031 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-18 15:17:48,031 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-18 15:17:48,031 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_d6bfc3eb-9043-4962-ad04-a405114524f4/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2018-11-18 15:17:48,041 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-18 15:17:48,041 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-18 15:17:48,042 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-18 15:17:48,042 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-18 15:17:48,042 INFO L133 SettingsManager]: * Use SBE=true [2018-11-18 15:17:48,043 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2018-11-18 15:17:48,043 INFO L133 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2018-11-18 15:17:48,043 INFO L133 SettingsManager]: * Use old map elimination=false [2018-11-18 15:17:48,043 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false [2018-11-18 15:17:48,043 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true [2018-11-18 15:17:48,043 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2018-11-18 15:17:48,043 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-18 15:17:48,043 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-18 15:17:48,044 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-18 15:17:48,044 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-18 15:17:48,044 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-18 15:17:48,044 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-18 15:17:48,044 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2018-11-18 15:17:48,044 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2018-11-18 15:17:48,044 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2018-11-18 15:17:48,044 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-18 15:17:48,045 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-18 15:17:48,045 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false [2018-11-18 15:17:48,045 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-18 15:17:48,045 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2018-11-18 15:17:48,047 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-18 15:17:48,047 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-18 15:17:48,047 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2018-11-18 15:17:48,047 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-18 15:17:48,047 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-18 15:17:48,047 INFO L133 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2018-11-18 15:17:48,048 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-11-18 15:17:48,048 INFO L133 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_d6bfc3eb-9043-4962-ad04-a405114524f4/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 27d160802d278384ef6d8db395ef2d19702d5645 [2018-11-18 15:17:48,070 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-18 15:17:48,079 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-18 15:17:48,082 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-18 15:17:48,083 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-18 15:17:48,083 INFO L276 PluginConnector]: CDTParser initialized [2018-11-18 15:17:48,084 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_d6bfc3eb-9043-4962-ad04-a405114524f4/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/token_ring.05_false-unreach-call_false-termination.cil.c [2018-11-18 15:17:48,130 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_d6bfc3eb-9043-4962-ad04-a405114524f4/bin-2019/uautomizer/data/2797e1b4b/b8c4c5a9b86c4383abfc6d5cfa3525d6/FLAG55a711d33 [2018-11-18 15:17:48,471 INFO L307 CDTParser]: Found 1 translation units. [2018-11-18 15:17:48,472 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_d6bfc3eb-9043-4962-ad04-a405114524f4/sv-benchmarks/c/systemc/token_ring.05_false-unreach-call_false-termination.cil.c [2018-11-18 15:17:48,480 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_d6bfc3eb-9043-4962-ad04-a405114524f4/bin-2019/uautomizer/data/2797e1b4b/b8c4c5a9b86c4383abfc6d5cfa3525d6/FLAG55a711d33 [2018-11-18 15:17:48,490 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_d6bfc3eb-9043-4962-ad04-a405114524f4/bin-2019/uautomizer/data/2797e1b4b/b8c4c5a9b86c4383abfc6d5cfa3525d6 [2018-11-18 15:17:48,493 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-18 15:17:48,494 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-18 15:17:48,495 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-18 15:17:48,495 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-18 15:17:48,498 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-18 15:17:48,498 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 03:17:48" (1/1) ... [2018-11-18 15:17:48,500 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@58ae4871 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:17:48, skipping insertion in model container [2018-11-18 15:17:48,500 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 03:17:48" (1/1) ... [2018-11-18 15:17:48,507 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-18 15:17:48,535 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-18 15:17:48,686 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 15:17:48,690 INFO L191 MainTranslator]: Completed pre-run [2018-11-18 15:17:48,723 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 15:17:48,734 INFO L195 MainTranslator]: Completed translation [2018-11-18 15:17:48,734 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:17:48 WrapperNode [2018-11-18 15:17:48,734 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-18 15:17:48,735 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-18 15:17:48,735 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-18 15:17:48,735 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-18 15:17:48,776 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:17:48" (1/1) ... [2018-11-18 15:17:48,783 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:17:48" (1/1) ... [2018-11-18 15:17:48,822 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-18 15:17:48,822 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-18 15:17:48,822 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-18 15:17:48,822 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-18 15:17:48,831 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:17:48" (1/1) ... [2018-11-18 15:17:48,831 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:17:48" (1/1) ... [2018-11-18 15:17:48,834 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:17:48" (1/1) ... [2018-11-18 15:17:48,834 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:17:48" (1/1) ... [2018-11-18 15:17:48,846 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:17:48" (1/1) ... [2018-11-18 15:17:48,859 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:17:48" (1/1) ... [2018-11-18 15:17:48,862 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:17:48" (1/1) ... [2018-11-18 15:17:48,867 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-18 15:17:48,867 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-18 15:17:48,867 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-18 15:17:48,867 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-18 15:17:48,868 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:17:48" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d6bfc3eb-9043-4962-ad04-a405114524f4/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 15:17:48,920 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-18 15:17:48,920 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-18 15:17:49,766 INFO L278 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-18 15:17:49,766 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 03:17:49 BoogieIcfgContainer [2018-11-18 15:17:49,767 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-18 15:17:49,767 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2018-11-18 15:17:49,767 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2018-11-18 15:17:49,770 INFO L276 PluginConnector]: BuchiAutomizer initialized [2018-11-18 15:17:49,770 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 15:17:49,770 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 18.11 03:17:48" (1/3) ... [2018-11-18 15:17:49,771 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@552ef9ed and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 03:17:49, skipping insertion in model container [2018-11-18 15:17:49,771 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 15:17:49,772 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:17:48" (2/3) ... [2018-11-18 15:17:49,772 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@552ef9ed and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 03:17:49, skipping insertion in model container [2018-11-18 15:17:49,772 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 15:17:49,772 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 03:17:49" (3/3) ... [2018-11-18 15:17:49,774 INFO L375 chiAutomizerObserver]: Analyzing ICFG token_ring.05_false-unreach-call_false-termination.cil.c [2018-11-18 15:17:49,810 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-18 15:17:49,810 INFO L374 BuchiCegarLoop]: Interprodecural is true [2018-11-18 15:17:49,811 INFO L375 BuchiCegarLoop]: Hoare is false [2018-11-18 15:17:49,811 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2018-11-18 15:17:49,811 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-18 15:17:49,811 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-18 15:17:49,811 INFO L379 BuchiCegarLoop]: Difference is false [2018-11-18 15:17:49,811 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-18 15:17:49,811 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2018-11-18 15:17:49,832 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 567 states. [2018-11-18 15:17:49,866 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 484 [2018-11-18 15:17:49,867 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:17:49,867 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:17:49,876 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:49,876 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:49,876 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ [2018-11-18 15:17:49,876 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 567 states. [2018-11-18 15:17:49,885 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 484 [2018-11-18 15:17:49,885 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:17:49,885 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:17:49,887 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:49,888 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:49,894 INFO L794 eck$LassoCheckResult]: Stem: 362#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 292#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 194#L893true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 167#L409true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 480#L416true assume !(1 == ~m_i~0);~m_st~0 := 2; 341#L416-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 221#L421-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 526#L426-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 168#L431-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 433#L436-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 198#L441-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 449#L601true assume 0 == ~M_E~0;~M_E~0 := 1; 454#L601-2true assume !(0 == ~T1_E~0); 201#L606-1true assume !(0 == ~T2_E~0); 94#L611-1true assume !(0 == ~T3_E~0); 383#L616-1true assume !(0 == ~T4_E~0); 8#L621-1true assume !(0 == ~T5_E~0); 320#L626-1true assume !(0 == ~E_M~0); 67#L631-1true assume !(0 == ~E_1~0); 487#L636-1true assume 0 == ~E_2~0;~E_2~0 := 1; 245#L641-1true assume !(0 == ~E_3~0); 567#L646-1true assume !(0 == ~E_4~0); 192#L651-1true assume !(0 == ~E_5~0); 463#L656-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 513#L294true assume !(1 == ~m_pc~0); 548#L294-2true is_master_triggered_~__retres1~0 := 0; 538#L305true is_master_triggered_#res := is_master_triggered_~__retres1~0; 343#L306true activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 560#L745true assume !(0 != activate_threads_~tmp~1); 563#L745-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 130#L313true assume 1 == ~t1_pc~0; 91#L314true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 128#L324true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 89#L325true activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 16#L753true assume !(0 != activate_threads_~tmp___0~0); 19#L753-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 173#L332true assume 1 == ~t2_pc~0; 224#L333true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 172#L343true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 223#L344true activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 188#L761true assume !(0 != activate_threads_~tmp___1~0); 189#L761-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 313#L351true assume !(1 == ~t3_pc~0); 297#L351-2true is_transmit3_triggered_~__retres1~3 := 0; 312#L362true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 377#L363true activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 325#L769true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 328#L769-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 439#L370true assume 1 == ~t4_pc~0; 529#L371true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 436#L381true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 527#L382true activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 459#L777true assume !(0 != activate_threads_~tmp___3~0); 460#L777-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 60#L389true assume !(1 == ~t5_pc~0); 40#L389-2true is_transmit5_triggered_~__retres1~5 := 0; 58#L400true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 157#L401true activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 73#L785true assume !(0 != activate_threads_~tmp___4~0); 75#L785-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 483#L669true assume !(1 == ~M_E~0); 488#L669-2true assume !(1 == ~T1_E~0); 244#L674-1true assume !(1 == ~T2_E~0); 564#L679-1true assume !(1 == ~T3_E~0); 191#L684-1true assume !(1 == ~T4_E~0); 462#L689-1true assume !(1 == ~T5_E~0); 351#L694-1true assume !(1 == ~E_M~0); 106#L699-1true assume 1 == ~E_1~0;~E_1~0 := 2; 394#L704-1true assume !(1 == ~E_2~0); 3#L709-1true assume !(1 == ~E_3~0); 314#L714-1true assume !(1 == ~E_4~0); 63#L719-1true assume !(1 == ~E_5~0); 482#L724-1true assume { :end_inline_reset_delta_events } true; 115#L930-3true [2018-11-18 15:17:49,895 INFO L796 eck$LassoCheckResult]: Loop: 115#L930-3true assume true; 111#L930-1true assume !false; 464#L931true start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 69#L576true assume !true; 569#L591true assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 170#L409-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 456#L601-3true assume 0 == ~M_E~0;~M_E~0 := 1; 427#L601-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 204#L606-3true assume !(0 == ~T2_E~0); 99#L611-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 385#L616-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 12#L621-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 322#L626-3true assume 0 == ~E_M~0;~E_M~0 := 1; 52#L631-3true assume 0 == ~E_1~0;~E_1~0 := 1; 476#L636-3true assume 0 == ~E_2~0;~E_2~0 := 1; 233#L641-3true assume 0 == ~E_3~0;~E_3~0 := 1; 553#L646-3true assume !(0 == ~E_4~0); 182#L651-3true assume 0 == ~E_5~0;~E_5~0 := 1; 453#L656-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 478#L294-21true assume 1 == ~m_pc~0; 342#L295-7true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 524#L305-7true is_master_triggered_#res := is_master_triggered_~__retres1~0; 338#L306-7true activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 497#L745-21true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 500#L745-23true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 92#L313-21true assume 1 == ~t1_pc~0; 470#L314-7true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 121#L324-7true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 469#L325-7true activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 123#L753-21true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 127#L753-23true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 243#L332-21true assume !(1 == ~t2_pc~0); 246#L332-23true is_transmit2_triggered_~__retres1~2 := 0; 277#L343-7true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 217#L344-7true activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 255#L761-21true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 257#L761-23true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 393#L351-21true assume 1 == ~t3_pc~0; 355#L352-7true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 285#L362-7true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 353#L363-7true activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 289#L769-21true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 291#L769-23true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 562#L370-21true assume !(1 == ~t4_pc~0); 566#L370-23true is_transmit4_triggered_~__retres1~4 := 0; 423#L381-7true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 517#L382-7true activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 409#L777-21true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 411#L777-23true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 18#L389-21true assume !(1 == ~t5_pc~0); 5#L389-23true is_transmit5_triggered_~__retres1~5 := 0; 31#L400-7true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 148#L401-7true activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 36#L785-21true assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 38#L785-23true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 491#L669-3true assume 1 == ~M_E~0;~M_E~0 := 2; 477#L669-5true assume !(1 == ~T1_E~0); 247#L674-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 552#L679-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 180#L684-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 450#L689-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 200#L694-3true assume 1 == ~E_M~0;~E_M~0 := 2; 93#L699-3true assume 1 == ~E_1~0;~E_1~0 := 2; 382#L704-3true assume 1 == ~E_2~0;~E_2~0 := 2; 7#L709-3true assume !(1 == ~E_3~0); 318#L714-3true assume 1 == ~E_4~0;~E_4~0 := 2; 66#L719-3true assume 1 == ~E_5~0;~E_5~0 := 2; 486#L724-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 240#L454-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 187#L486-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 239#L487-1true start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 265#L949true assume !(0 == start_simulation_~tmp~3); 249#L949-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 222#L454-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 166#L486-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 241#L487-2true stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 193#L904true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 504#L911true stop_simulation_#res := stop_simulation_~__retres2~0; 330#L912true start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 24#L962true assume !(0 != start_simulation_~tmp___0~1); 115#L930-3true [2018-11-18 15:17:49,899 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:49,900 INFO L82 PathProgramCache]: Analyzing trace with hash 907431560, now seen corresponding path program 1 times [2018-11-18 15:17:49,901 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:49,902 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:49,935 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:49,935 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:49,935 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:49,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:50,018 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:17:50,020 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:17:50,020 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:17:50,023 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:17:50,024 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:50,024 INFO L82 PathProgramCache]: Analyzing trace with hash -1656824467, now seen corresponding path program 1 times [2018-11-18 15:17:50,024 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:50,024 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:50,025 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:50,025 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:50,025 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:50,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:50,042 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:17:50,042 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:17:50,043 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 15:17:50,044 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:17:50,053 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:17:50,054 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:17:50,055 INFO L87 Difference]: Start difference. First operand 567 states. Second operand 3 states. [2018-11-18 15:17:50,091 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:17:50,092 INFO L93 Difference]: Finished difference Result 565 states and 841 transitions. [2018-11-18 15:17:50,093 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:17:50,095 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 565 states and 841 transitions. [2018-11-18 15:17:50,099 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 480 [2018-11-18 15:17:50,106 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 565 states to 559 states and 835 transitions. [2018-11-18 15:17:50,107 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 559 [2018-11-18 15:17:50,108 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 559 [2018-11-18 15:17:50,109 INFO L73 IsDeterministic]: Start isDeterministic. Operand 559 states and 835 transitions. [2018-11-18 15:17:50,111 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:17:50,112 INFO L705 BuchiCegarLoop]: Abstraction has 559 states and 835 transitions. [2018-11-18 15:17:50,124 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 559 states and 835 transitions. [2018-11-18 15:17:50,147 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 559 to 559. [2018-11-18 15:17:50,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 559 states. [2018-11-18 15:17:50,150 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 559 states to 559 states and 835 transitions. [2018-11-18 15:17:50,150 INFO L728 BuchiCegarLoop]: Abstraction has 559 states and 835 transitions. [2018-11-18 15:17:50,151 INFO L608 BuchiCegarLoop]: Abstraction has 559 states and 835 transitions. [2018-11-18 15:17:50,151 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ [2018-11-18 15:17:50,151 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 559 states and 835 transitions. [2018-11-18 15:17:50,153 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 480 [2018-11-18 15:17:50,153 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:17:50,153 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:17:50,156 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:50,156 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:50,157 INFO L794 eck$LassoCheckResult]: Stem: 1609#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1514#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1411#L893 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 1366#L409 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1367#L416 assume 1 == ~m_i~0;~m_st~0 := 0; 1577#L416-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1457#L421-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1458#L426-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1368#L431-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1369#L436-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1418#L441-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1419#L601 assume 0 == ~M_E~0;~M_E~0 := 1; 1675#L601-2 assume !(0 == ~T1_E~0); 1421#L606-1 assume !(0 == ~T2_E~0); 1308#L611-1 assume !(0 == ~T3_E~0); 1309#L616-1 assume !(0 == ~T4_E~0); 1152#L621-1 assume !(0 == ~T5_E~0); 1153#L626-1 assume !(0 == ~E_M~0); 1253#L631-1 assume !(0 == ~E_1~0); 1254#L636-1 assume 0 == ~E_2~0;~E_2~0 := 1; 1477#L641-1 assume !(0 == ~E_3~0); 1478#L646-1 assume !(0 == ~E_4~0); 1407#L651-1 assume !(0 == ~E_5~0); 1408#L656-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1683#L294 assume !(1 == ~m_pc~0); 1567#L294-2 is_master_triggered_~__retres1~0 := 0; 1566#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1581#L306 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1582#L745 assume !(0 != activate_threads_~tmp~1); 1699#L745-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1349#L313 assume 1 == ~t1_pc~0; 1300#L314 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1301#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1297#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1167#L753 assume !(0 != activate_threads_~tmp___0~0); 1168#L753-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1172#L332 assume 1 == ~t2_pc~0; 1378#L333 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1376#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1377#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1401#L761 assume !(0 != activate_threads_~tmp___1~0); 1402#L761-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1403#L351 assume !(1 == ~t3_pc~0); 1520#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 1521#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1543#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1549#L769 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1550#L769-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1551#L370 assume 1 == ~t4_pc~0; 1666#L371 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1661#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1662#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1680#L777 assume !(0 != activate_threads_~tmp___3~0); 1681#L777-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1242#L389 assume !(1 == ~t5_pc~0); 1209#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 1210#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1241#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1264#L785 assume !(0 != activate_threads_~tmp___4~0); 1265#L785-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1267#L669 assume !(1 == ~M_E~0); 1685#L669-2 assume !(1 == ~T1_E~0); 1475#L674-1 assume !(1 == ~T2_E~0); 1476#L679-1 assume !(1 == ~T3_E~0); 1405#L684-1 assume !(1 == ~T4_E~0); 1406#L689-1 assume !(1 == ~T5_E~0); 1601#L694-1 assume !(1 == ~E_M~0); 1330#L699-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1331#L704-1 assume !(1 == ~E_2~0); 1141#L709-1 assume !(1 == ~E_3~0); 1142#L714-1 assume !(1 == ~E_4~0); 1246#L719-1 assume !(1 == ~E_5~0); 1247#L724-1 assume { :end_inline_reset_delta_events } true; 1183#L930-3 [2018-11-18 15:17:50,157 INFO L796 eck$LassoCheckResult]: Loop: 1183#L930-3 assume true; 1336#L930-1 assume !false; 1337#L931 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 1256#L576 assume true; 1257#L496-1 assume !false; 1395#L497 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1396#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1232#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1398#L487 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 1321#L501 assume !(0 != eval_~tmp~0); 1322#L591 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 1372#L409-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 1373#L601-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1656#L601-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1424#L606-3 assume !(0 == ~T2_E~0); 1319#L611-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1320#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1158#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1159#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1225#L631-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1226#L636-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1468#L641-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1469#L646-3 assume !(0 == ~E_4~0); 1393#L651-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1394#L656-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1678#L294-21 assume 1 == ~m_pc~0; 1578#L295-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1579#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1570#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1571#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1686#L745-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1303#L313-21 assume 1 == ~t1_pc~0; 1304#L314-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1310#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1343#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1345#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1346#L753-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1348#L332-21 assume 1 == ~t2_pc~0; 1447#L333-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1449#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1445#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1446#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1483#L761-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1484#L351-21 assume 1 == ~t3_pc~0; 1604#L352-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1502#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1503#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1509#L769-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1510#L769-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1513#L370-21 assume 1 == ~t4_pc~0; 1690#L371-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1651#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1652#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1632#L777-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1633#L777-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1170#L389-21 assume 1 == ~t5_pc~0; 1171#L390-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1144#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1193#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1199#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1200#L785-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1204#L669-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1684#L669-5 assume !(1 == ~T1_E~0); 1479#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1480#L679-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1389#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1390#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1420#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1306#L699-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1307#L704-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1150#L709-3 assume !(1 == ~E_3~0); 1151#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1250#L719-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1251#L724-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1473#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1235#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1400#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 1471#L949 assume !(0 == start_simulation_~tmp~3); 1262#L949-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1455#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1239#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1365#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 1409#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1410#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 1552#L912 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 1182#L962 assume !(0 != start_simulation_~tmp___0~1); 1183#L930-3 [2018-11-18 15:17:50,158 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:50,158 INFO L82 PathProgramCache]: Analyzing trace with hash 1400057734, now seen corresponding path program 1 times [2018-11-18 15:17:50,158 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:50,158 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:50,159 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:50,159 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:50,159 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:50,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:50,200 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:17:50,200 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:17:50,200 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:17:50,201 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:17:50,201 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:50,201 INFO L82 PathProgramCache]: Analyzing trace with hash 1619187822, now seen corresponding path program 1 times [2018-11-18 15:17:50,201 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:50,201 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:50,202 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:50,202 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:50,202 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:50,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:50,275 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:17:50,276 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:17:50,276 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:17:50,276 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:17:50,276 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:17:50,276 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:17:50,277 INFO L87 Difference]: Start difference. First operand 559 states and 835 transitions. cyclomatic complexity: 277 Second operand 3 states. [2018-11-18 15:17:50,287 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:17:50,287 INFO L93 Difference]: Finished difference Result 559 states and 834 transitions. [2018-11-18 15:17:50,287 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:17:50,288 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 559 states and 834 transitions. [2018-11-18 15:17:50,290 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 480 [2018-11-18 15:17:50,292 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 559 states to 559 states and 834 transitions. [2018-11-18 15:17:50,292 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 559 [2018-11-18 15:17:50,293 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 559 [2018-11-18 15:17:50,293 INFO L73 IsDeterministic]: Start isDeterministic. Operand 559 states and 834 transitions. [2018-11-18 15:17:50,295 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:17:50,295 INFO L705 BuchiCegarLoop]: Abstraction has 559 states and 834 transitions. [2018-11-18 15:17:50,296 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 559 states and 834 transitions. [2018-11-18 15:17:50,305 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 559 to 559. [2018-11-18 15:17:50,305 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 559 states. [2018-11-18 15:17:50,307 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 559 states to 559 states and 834 transitions. [2018-11-18 15:17:50,307 INFO L728 BuchiCegarLoop]: Abstraction has 559 states and 834 transitions. [2018-11-18 15:17:50,308 INFO L608 BuchiCegarLoop]: Abstraction has 559 states and 834 transitions. [2018-11-18 15:17:50,308 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ [2018-11-18 15:17:50,308 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 559 states and 834 transitions. [2018-11-18 15:17:50,310 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 480 [2018-11-18 15:17:50,311 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:17:50,311 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:17:50,312 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:50,312 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:50,313 INFO L794 eck$LassoCheckResult]: Stem: 2734#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 2639#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2536#L893 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 2491#L409 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2492#L416 assume 1 == ~m_i~0;~m_st~0 := 0; 2702#L416-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2582#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2583#L426-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2493#L431-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2494#L436-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2543#L441-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2544#L601 assume 0 == ~M_E~0;~M_E~0 := 1; 2800#L601-2 assume !(0 == ~T1_E~0); 2546#L606-1 assume !(0 == ~T2_E~0); 2433#L611-1 assume !(0 == ~T3_E~0); 2434#L616-1 assume !(0 == ~T4_E~0); 2277#L621-1 assume !(0 == ~T5_E~0); 2278#L626-1 assume !(0 == ~E_M~0); 2378#L631-1 assume !(0 == ~E_1~0); 2379#L636-1 assume 0 == ~E_2~0;~E_2~0 := 1; 2602#L641-1 assume !(0 == ~E_3~0); 2603#L646-1 assume !(0 == ~E_4~0); 2532#L651-1 assume !(0 == ~E_5~0); 2533#L656-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2808#L294 assume !(1 == ~m_pc~0); 2692#L294-2 is_master_triggered_~__retres1~0 := 0; 2691#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2706#L306 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2707#L745 assume !(0 != activate_threads_~tmp~1); 2824#L745-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2474#L313 assume 1 == ~t1_pc~0; 2425#L314 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2426#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2422#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2293#L753 assume !(0 != activate_threads_~tmp___0~0); 2294#L753-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2297#L332 assume 1 == ~t2_pc~0; 2503#L333 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2501#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2502#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2526#L761 assume !(0 != activate_threads_~tmp___1~0); 2527#L761-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2528#L351 assume !(1 == ~t3_pc~0); 2645#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 2646#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2668#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2674#L769 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2675#L769-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2676#L370 assume 1 == ~t4_pc~0; 2791#L371 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2788#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2789#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2805#L777 assume !(0 != activate_threads_~tmp___3~0); 2806#L777-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2368#L389 assume !(1 == ~t5_pc~0); 2334#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 2335#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2366#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2389#L785 assume !(0 != activate_threads_~tmp___4~0); 2390#L785-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2392#L669 assume !(1 == ~M_E~0); 2810#L669-2 assume !(1 == ~T1_E~0); 2600#L674-1 assume !(1 == ~T2_E~0); 2601#L679-1 assume !(1 == ~T3_E~0); 2530#L684-1 assume !(1 == ~T4_E~0); 2531#L689-1 assume !(1 == ~T5_E~0); 2726#L694-1 assume !(1 == ~E_M~0); 2455#L699-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2456#L704-1 assume !(1 == ~E_2~0); 2266#L709-1 assume !(1 == ~E_3~0); 2267#L714-1 assume !(1 == ~E_4~0); 2373#L719-1 assume !(1 == ~E_5~0); 2374#L724-1 assume { :end_inline_reset_delta_events } true; 2308#L930-3 [2018-11-18 15:17:50,313 INFO L796 eck$LassoCheckResult]: Loop: 2308#L930-3 assume true; 2461#L930-1 assume !false; 2462#L931 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 2381#L576 assume true; 2382#L496-1 assume !false; 2520#L497 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2521#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2357#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2523#L487 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 2446#L501 assume !(0 != eval_~tmp~0); 2447#L591 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 2497#L409-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 2498#L601-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2781#L601-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2549#L606-3 assume !(0 == ~T2_E~0); 2444#L611-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2445#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2283#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2284#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2350#L631-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2351#L636-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2593#L641-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2594#L646-3 assume !(0 == ~E_4~0); 2518#L651-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2519#L656-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2803#L294-21 assume !(1 == ~m_pc~0); 2705#L294-23 is_master_triggered_~__retres1~0 := 0; 2704#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2695#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2696#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2811#L745-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2428#L313-21 assume 1 == ~t1_pc~0; 2429#L314-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2435#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2468#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2470#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2471#L753-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2473#L332-21 assume 1 == ~t2_pc~0; 2572#L333-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2574#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2570#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2571#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2608#L761-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2609#L351-21 assume 1 == ~t3_pc~0; 2728#L352-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2627#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2628#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2634#L769-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2635#L769-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2638#L370-21 assume !(1 == ~t4_pc~0); 2816#L370-23 is_transmit4_triggered_~__retres1~4 := 0; 2776#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2777#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2757#L777-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2758#L777-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2295#L389-21 assume 1 == ~t5_pc~0; 2296#L390-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 2269#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2318#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2327#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 2328#L785-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2330#L669-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2809#L669-5 assume !(1 == ~T1_E~0); 2604#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2605#L679-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2514#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2515#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2545#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2431#L699-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2432#L704-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2275#L709-3 assume !(1 == ~E_3~0); 2276#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2376#L719-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2377#L724-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2598#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2360#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2525#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 2596#L949 assume !(0 == start_simulation_~tmp~3); 2387#L949-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2580#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2364#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2490#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 2534#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2535#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 2677#L912 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 2307#L962 assume !(0 != start_simulation_~tmp___0~1); 2308#L930-3 [2018-11-18 15:17:50,313 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:50,314 INFO L82 PathProgramCache]: Analyzing trace with hash -1678755836, now seen corresponding path program 1 times [2018-11-18 15:17:50,314 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:50,314 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:50,314 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:50,314 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:50,315 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:50,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:50,344 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:17:50,344 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:17:50,345 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:17:50,345 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:17:50,345 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:50,345 INFO L82 PathProgramCache]: Analyzing trace with hash -521987344, now seen corresponding path program 1 times [2018-11-18 15:17:50,346 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:50,346 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:50,346 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:50,346 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:50,347 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:50,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:50,404 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:17:50,404 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:17:50,404 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:17:50,404 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:17:50,404 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:17:50,405 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:17:50,405 INFO L87 Difference]: Start difference. First operand 559 states and 834 transitions. cyclomatic complexity: 276 Second operand 3 states. [2018-11-18 15:17:50,423 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:17:50,423 INFO L93 Difference]: Finished difference Result 559 states and 833 transitions. [2018-11-18 15:17:50,424 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:17:50,424 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 559 states and 833 transitions. [2018-11-18 15:17:50,427 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 480 [2018-11-18 15:17:50,430 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 559 states to 559 states and 833 transitions. [2018-11-18 15:17:50,430 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 559 [2018-11-18 15:17:50,430 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 559 [2018-11-18 15:17:50,431 INFO L73 IsDeterministic]: Start isDeterministic. Operand 559 states and 833 transitions. [2018-11-18 15:17:50,432 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:17:50,432 INFO L705 BuchiCegarLoop]: Abstraction has 559 states and 833 transitions. [2018-11-18 15:17:50,432 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 559 states and 833 transitions. [2018-11-18 15:17:50,439 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 559 to 559. [2018-11-18 15:17:50,439 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 559 states. [2018-11-18 15:17:50,441 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 559 states to 559 states and 833 transitions. [2018-11-18 15:17:50,441 INFO L728 BuchiCegarLoop]: Abstraction has 559 states and 833 transitions. [2018-11-18 15:17:50,441 INFO L608 BuchiCegarLoop]: Abstraction has 559 states and 833 transitions. [2018-11-18 15:17:50,441 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ [2018-11-18 15:17:50,441 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 559 states and 833 transitions. [2018-11-18 15:17:50,443 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 480 [2018-11-18 15:17:50,443 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:17:50,444 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:17:50,445 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:50,445 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:50,445 INFO L794 eck$LassoCheckResult]: Stem: 3859#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 3764#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3661#L893 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 3616#L409 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3617#L416 assume 1 == ~m_i~0;~m_st~0 := 0; 3827#L416-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3707#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3708#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3620#L431-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3621#L436-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3668#L441-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3669#L601 assume 0 == ~M_E~0;~M_E~0 := 1; 3925#L601-2 assume !(0 == ~T1_E~0); 3671#L606-1 assume !(0 == ~T2_E~0); 3559#L611-1 assume !(0 == ~T3_E~0); 3560#L616-1 assume !(0 == ~T4_E~0); 3403#L621-1 assume !(0 == ~T5_E~0); 3404#L626-1 assume !(0 == ~E_M~0); 3503#L631-1 assume !(0 == ~E_1~0); 3504#L636-1 assume 0 == ~E_2~0;~E_2~0 := 1; 3727#L641-1 assume !(0 == ~E_3~0); 3728#L646-1 assume !(0 == ~E_4~0); 3657#L651-1 assume !(0 == ~E_5~0); 3658#L656-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3933#L294 assume !(1 == ~m_pc~0); 3817#L294-2 is_master_triggered_~__retres1~0 := 0; 3816#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3831#L306 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3832#L745 assume !(0 != activate_threads_~tmp~1); 3949#L745-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3599#L313 assume 1 == ~t1_pc~0; 3550#L314 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3551#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3547#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3418#L753 assume !(0 != activate_threads_~tmp___0~0); 3419#L753-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3422#L332 assume 1 == ~t2_pc~0; 3628#L333 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3626#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3627#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3651#L761 assume !(0 != activate_threads_~tmp___1~0); 3652#L761-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3653#L351 assume !(1 == ~t3_pc~0); 3770#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 3771#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3793#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3799#L769 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3800#L769-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3801#L370 assume 1 == ~t4_pc~0; 3916#L371 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3913#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3914#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3930#L777 assume !(0 != activate_threads_~tmp___3~0); 3931#L777-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3493#L389 assume !(1 == ~t5_pc~0); 3459#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 3460#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3491#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3514#L785 assume !(0 != activate_threads_~tmp___4~0); 3515#L785-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3517#L669 assume !(1 == ~M_E~0); 3935#L669-2 assume !(1 == ~T1_E~0); 3725#L674-1 assume !(1 == ~T2_E~0); 3726#L679-1 assume !(1 == ~T3_E~0); 3655#L684-1 assume !(1 == ~T4_E~0); 3656#L689-1 assume !(1 == ~T5_E~0); 3851#L694-1 assume !(1 == ~E_M~0); 3580#L699-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3581#L704-1 assume !(1 == ~E_2~0); 3391#L709-1 assume !(1 == ~E_3~0); 3392#L714-1 assume !(1 == ~E_4~0); 3498#L719-1 assume !(1 == ~E_5~0); 3499#L724-1 assume { :end_inline_reset_delta_events } true; 3433#L930-3 [2018-11-18 15:17:50,446 INFO L796 eck$LassoCheckResult]: Loop: 3433#L930-3 assume true; 3586#L930-1 assume !false; 3587#L931 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 3506#L576 assume true; 3507#L496-1 assume !false; 3646#L497 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3647#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3482#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3648#L487 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 3571#L501 assume !(0 != eval_~tmp~0); 3572#L591 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 3622#L409-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 3623#L601-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3906#L601-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3674#L606-3 assume !(0 == ~T2_E~0); 3569#L611-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3570#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3408#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3409#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3475#L631-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3476#L636-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3718#L641-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3719#L646-3 assume !(0 == ~E_4~0); 3643#L651-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3644#L656-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3928#L294-21 assume 1 == ~m_pc~0; 3828#L295-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3829#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3820#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3821#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3936#L745-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3553#L313-21 assume 1 == ~t1_pc~0; 3554#L314-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3558#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3593#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3594#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3595#L753-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3598#L332-21 assume 1 == ~t2_pc~0; 3697#L333-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3699#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3695#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3696#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3733#L761-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3734#L351-21 assume 1 == ~t3_pc~0; 3853#L352-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3752#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3753#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3759#L769-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3760#L769-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3763#L370-21 assume 1 == ~t4_pc~0; 3940#L371-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3901#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3902#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3882#L777-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 3883#L777-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3420#L389-21 assume !(1 == ~t5_pc~0); 3393#L389-23 is_transmit5_triggered_~__retres1~5 := 0; 3394#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3443#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3452#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 3453#L785-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3455#L669-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3934#L669-5 assume !(1 == ~T1_E~0); 3729#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3730#L679-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3639#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3640#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3670#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3556#L699-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3557#L704-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3400#L709-3 assume !(1 == ~E_3~0); 3401#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3501#L719-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3502#L724-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3723#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3485#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3650#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 3721#L949 assume !(0 == start_simulation_~tmp~3); 3512#L949-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3705#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3489#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3615#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 3659#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3660#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 3802#L912 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 3432#L962 assume !(0 != start_simulation_~tmp___0~1); 3433#L930-3 [2018-11-18 15:17:50,446 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:50,446 INFO L82 PathProgramCache]: Analyzing trace with hash -946788410, now seen corresponding path program 1 times [2018-11-18 15:17:50,446 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:50,446 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:50,447 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:50,447 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:50,447 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:50,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:50,485 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:17:50,485 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:17:50,485 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:17:50,485 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:17:50,485 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:50,486 INFO L82 PathProgramCache]: Analyzing trace with hash -152283153, now seen corresponding path program 1 times [2018-11-18 15:17:50,486 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:50,486 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:50,486 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:50,487 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:50,487 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:50,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:50,512 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:17:50,512 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:17:50,512 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:17:50,512 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:17:50,513 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:17:50,513 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:17:50,513 INFO L87 Difference]: Start difference. First operand 559 states and 833 transitions. cyclomatic complexity: 275 Second operand 3 states. [2018-11-18 15:17:50,525 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:17:50,525 INFO L93 Difference]: Finished difference Result 559 states and 832 transitions. [2018-11-18 15:17:50,526 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:17:50,526 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 559 states and 832 transitions. [2018-11-18 15:17:50,528 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 480 [2018-11-18 15:17:50,529 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 559 states to 559 states and 832 transitions. [2018-11-18 15:17:50,529 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 559 [2018-11-18 15:17:50,530 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 559 [2018-11-18 15:17:50,530 INFO L73 IsDeterministic]: Start isDeterministic. Operand 559 states and 832 transitions. [2018-11-18 15:17:50,531 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:17:50,531 INFO L705 BuchiCegarLoop]: Abstraction has 559 states and 832 transitions. [2018-11-18 15:17:50,532 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 559 states and 832 transitions. [2018-11-18 15:17:50,535 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 559 to 559. [2018-11-18 15:17:50,536 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 559 states. [2018-11-18 15:17:50,537 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 559 states to 559 states and 832 transitions. [2018-11-18 15:17:50,537 INFO L728 BuchiCegarLoop]: Abstraction has 559 states and 832 transitions. [2018-11-18 15:17:50,537 INFO L608 BuchiCegarLoop]: Abstraction has 559 states and 832 transitions. [2018-11-18 15:17:50,537 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ [2018-11-18 15:17:50,537 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 559 states and 832 transitions. [2018-11-18 15:17:50,539 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 480 [2018-11-18 15:17:50,539 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:17:50,539 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:17:50,541 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:50,541 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:50,541 INFO L794 eck$LassoCheckResult]: Stem: 4984#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 4889#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4786#L893 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 4741#L409 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4742#L416 assume 1 == ~m_i~0;~m_st~0 := 0; 4952#L416-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4832#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4833#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4745#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4746#L436-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4793#L441-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4794#L601 assume 0 == ~M_E~0;~M_E~0 := 1; 5050#L601-2 assume !(0 == ~T1_E~0); 4796#L606-1 assume !(0 == ~T2_E~0); 4684#L611-1 assume !(0 == ~T3_E~0); 4685#L616-1 assume !(0 == ~T4_E~0); 4528#L621-1 assume !(0 == ~T5_E~0); 4529#L626-1 assume !(0 == ~E_M~0); 4628#L631-1 assume !(0 == ~E_1~0); 4629#L636-1 assume 0 == ~E_2~0;~E_2~0 := 1; 4852#L641-1 assume !(0 == ~E_3~0); 4853#L646-1 assume !(0 == ~E_4~0); 4782#L651-1 assume !(0 == ~E_5~0); 4783#L656-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5058#L294 assume !(1 == ~m_pc~0); 4944#L294-2 is_master_triggered_~__retres1~0 := 0; 4943#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4959#L306 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 4960#L745 assume !(0 != activate_threads_~tmp~1); 5074#L745-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4724#L313 assume 1 == ~t1_pc~0; 4675#L314 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4676#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4674#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4543#L753 assume !(0 != activate_threads_~tmp___0~0); 4544#L753-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4547#L332 assume 1 == ~t2_pc~0; 4753#L333 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4751#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4752#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4776#L761 assume !(0 != activate_threads_~tmp___1~0); 4777#L761-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4778#L351 assume !(1 == ~t3_pc~0); 4895#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 4896#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4918#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4924#L769 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4925#L769-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4926#L370 assume 1 == ~t4_pc~0; 5041#L371 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5038#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5039#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5055#L777 assume !(0 != activate_threads_~tmp___3~0); 5056#L777-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4618#L389 assume !(1 == ~t5_pc~0); 4584#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 4585#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4616#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4639#L785 assume !(0 != activate_threads_~tmp___4~0); 4640#L785-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4642#L669 assume !(1 == ~M_E~0); 5060#L669-2 assume !(1 == ~T1_E~0); 4850#L674-1 assume !(1 == ~T2_E~0); 4851#L679-1 assume !(1 == ~T3_E~0); 4780#L684-1 assume !(1 == ~T4_E~0); 4781#L689-1 assume !(1 == ~T5_E~0); 4976#L694-1 assume !(1 == ~E_M~0); 4705#L699-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4706#L704-1 assume !(1 == ~E_2~0); 4516#L709-1 assume !(1 == ~E_3~0); 4517#L714-1 assume !(1 == ~E_4~0); 4623#L719-1 assume !(1 == ~E_5~0); 4624#L724-1 assume { :end_inline_reset_delta_events } true; 4558#L930-3 [2018-11-18 15:17:50,541 INFO L796 eck$LassoCheckResult]: Loop: 4558#L930-3 assume true; 4711#L930-1 assume !false; 4712#L931 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 4631#L576 assume true; 4632#L496-1 assume !false; 4771#L497 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4772#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4607#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4773#L487 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 4696#L501 assume !(0 != eval_~tmp~0); 4697#L591 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 4747#L409-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 4748#L601-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5032#L601-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4799#L606-3 assume !(0 == ~T2_E~0); 4694#L611-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4695#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4533#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4534#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4600#L631-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4601#L636-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4843#L641-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4844#L646-3 assume !(0 == ~E_4~0); 4768#L651-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4769#L656-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5053#L294-21 assume 1 == ~m_pc~0; 4953#L295-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4954#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4945#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 4946#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5061#L745-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4678#L313-21 assume 1 == ~t1_pc~0; 4679#L314-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4683#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4718#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4719#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4720#L753-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4723#L332-21 assume 1 == ~t2_pc~0; 4822#L333-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4824#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4820#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4821#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4858#L761-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4859#L351-21 assume 1 == ~t3_pc~0; 4978#L352-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4877#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4878#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4884#L769-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4885#L769-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4888#L370-21 assume 1 == ~t4_pc~0; 5065#L371-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5026#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5027#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5007#L777-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5008#L777-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4545#L389-21 assume 1 == ~t5_pc~0; 4546#L390-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 4521#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4568#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4577#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 4578#L785-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4580#L669-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5059#L669-5 assume !(1 == ~T1_E~0); 4854#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4855#L679-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4764#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4765#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4795#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4681#L699-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4682#L704-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4525#L709-3 assume !(1 == ~E_3~0); 4526#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4626#L719-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4627#L724-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4848#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4610#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4775#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 4846#L949 assume !(0 == start_simulation_~tmp~3); 4637#L949-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4830#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4614#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4740#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 4784#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4785#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 4927#L912 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 4557#L962 assume !(0 != start_simulation_~tmp___0~1); 4558#L930-3 [2018-11-18 15:17:50,542 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:50,542 INFO L82 PathProgramCache]: Analyzing trace with hash 739391428, now seen corresponding path program 1 times [2018-11-18 15:17:50,542 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:50,542 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:50,543 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:50,543 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:50,543 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:50,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:50,565 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:17:50,565 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:17:50,565 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:17:50,566 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:17:50,566 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:50,566 INFO L82 PathProgramCache]: Analyzing trace with hash 1619187822, now seen corresponding path program 2 times [2018-11-18 15:17:50,566 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:50,566 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:50,567 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:50,567 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:50,567 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:50,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:50,621 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:17:50,622 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:17:50,622 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:17:50,622 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:17:50,622 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:17:50,622 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:17:50,623 INFO L87 Difference]: Start difference. First operand 559 states and 832 transitions. cyclomatic complexity: 274 Second operand 3 states. [2018-11-18 15:17:50,644 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:17:50,644 INFO L93 Difference]: Finished difference Result 559 states and 831 transitions. [2018-11-18 15:17:50,645 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:17:50,645 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 559 states and 831 transitions. [2018-11-18 15:17:50,648 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 480 [2018-11-18 15:17:50,650 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 559 states to 559 states and 831 transitions. [2018-11-18 15:17:50,650 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 559 [2018-11-18 15:17:50,651 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 559 [2018-11-18 15:17:50,651 INFO L73 IsDeterministic]: Start isDeterministic. Operand 559 states and 831 transitions. [2018-11-18 15:17:50,652 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:17:50,652 INFO L705 BuchiCegarLoop]: Abstraction has 559 states and 831 transitions. [2018-11-18 15:17:50,652 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 559 states and 831 transitions. [2018-11-18 15:17:50,658 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 559 to 559. [2018-11-18 15:17:50,658 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 559 states. [2018-11-18 15:17:50,660 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 559 states to 559 states and 831 transitions. [2018-11-18 15:17:50,660 INFO L728 BuchiCegarLoop]: Abstraction has 559 states and 831 transitions. [2018-11-18 15:17:50,660 INFO L608 BuchiCegarLoop]: Abstraction has 559 states and 831 transitions. [2018-11-18 15:17:50,660 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ [2018-11-18 15:17:50,660 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 559 states and 831 transitions. [2018-11-18 15:17:50,662 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 480 [2018-11-18 15:17:50,663 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:17:50,663 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:17:50,664 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:50,664 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:50,664 INFO L794 eck$LassoCheckResult]: Stem: 6109#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 6014#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 5911#L893 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 5866#L409 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5867#L416 assume 1 == ~m_i~0;~m_st~0 := 0; 6077#L416-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5957#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5958#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5870#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5871#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5918#L441-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5919#L601 assume 0 == ~M_E~0;~M_E~0 := 1; 6175#L601-2 assume !(0 == ~T1_E~0); 5921#L606-1 assume !(0 == ~T2_E~0); 5809#L611-1 assume !(0 == ~T3_E~0); 5810#L616-1 assume !(0 == ~T4_E~0); 5653#L621-1 assume !(0 == ~T5_E~0); 5654#L626-1 assume !(0 == ~E_M~0); 5753#L631-1 assume !(0 == ~E_1~0); 5754#L636-1 assume 0 == ~E_2~0;~E_2~0 := 1; 5977#L641-1 assume !(0 == ~E_3~0); 5978#L646-1 assume !(0 == ~E_4~0); 5907#L651-1 assume !(0 == ~E_5~0); 5908#L656-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6183#L294 assume !(1 == ~m_pc~0); 6069#L294-2 is_master_triggered_~__retres1~0 := 0; 6068#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6084#L306 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 6085#L745 assume !(0 != activate_threads_~tmp~1); 6199#L745-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5849#L313 assume 1 == ~t1_pc~0; 5800#L314 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5801#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5799#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5668#L753 assume !(0 != activate_threads_~tmp___0~0); 5669#L753-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5672#L332 assume 1 == ~t2_pc~0; 5878#L333 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5876#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5877#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5901#L761 assume !(0 != activate_threads_~tmp___1~0); 5902#L761-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5903#L351 assume !(1 == ~t3_pc~0); 6020#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 6021#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6043#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6049#L769 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 6050#L769-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6051#L370 assume 1 == ~t4_pc~0; 6166#L371 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 6161#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6162#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6180#L777 assume !(0 != activate_threads_~tmp___3~0); 6181#L777-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5742#L389 assume !(1 == ~t5_pc~0); 5707#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 5708#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5738#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5764#L785 assume !(0 != activate_threads_~tmp___4~0); 5765#L785-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5767#L669 assume !(1 == ~M_E~0); 6185#L669-2 assume !(1 == ~T1_E~0); 5975#L674-1 assume !(1 == ~T2_E~0); 5976#L679-1 assume !(1 == ~T3_E~0); 5905#L684-1 assume !(1 == ~T4_E~0); 5906#L689-1 assume !(1 == ~T5_E~0); 6101#L694-1 assume !(1 == ~E_M~0); 5830#L699-1 assume 1 == ~E_1~0;~E_1~0 := 2; 5831#L704-1 assume !(1 == ~E_2~0); 5641#L709-1 assume !(1 == ~E_3~0); 5642#L714-1 assume !(1 == ~E_4~0); 5746#L719-1 assume !(1 == ~E_5~0); 5747#L724-1 assume { :end_inline_reset_delta_events } true; 5683#L930-3 [2018-11-18 15:17:50,665 INFO L796 eck$LassoCheckResult]: Loop: 5683#L930-3 assume true; 5836#L930-1 assume !false; 5837#L931 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 5756#L576 assume true; 5757#L496-1 assume !false; 5895#L497 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5896#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5732#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5898#L487 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 5821#L501 assume !(0 != eval_~tmp~0); 5822#L591 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 5872#L409-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 5873#L601-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6156#L601-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5924#L606-3 assume !(0 == ~T2_E~0); 5819#L611-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5820#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5658#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5659#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5725#L631-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5726#L636-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5968#L641-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5969#L646-3 assume !(0 == ~E_4~0); 5893#L651-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5894#L656-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6178#L294-21 assume !(1 == ~m_pc~0); 6080#L294-23 is_master_triggered_~__retres1~0 := 0; 6079#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6070#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 6071#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 6186#L745-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5803#L313-21 assume 1 == ~t1_pc~0; 5804#L314-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5808#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5843#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5844#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5845#L753-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5848#L332-21 assume 1 == ~t2_pc~0; 5947#L333-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5949#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5945#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5946#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5983#L761-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5984#L351-21 assume 1 == ~t3_pc~0; 6104#L352-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 6002#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6003#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6009#L769-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 6010#L769-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6013#L370-21 assume 1 == ~t4_pc~0; 6190#L371-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 6151#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6152#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6132#L777-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 6133#L777-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5670#L389-21 assume 1 == ~t5_pc~0; 5671#L390-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 5646#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5693#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5702#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 5703#L785-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5705#L669-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6184#L669-5 assume !(1 == ~T1_E~0); 5979#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5980#L679-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5889#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5890#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5920#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5806#L699-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5807#L704-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5650#L709-3 assume !(1 == ~E_3~0); 5651#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5751#L719-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5752#L724-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5973#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5735#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5900#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 5972#L949 assume !(0 == start_simulation_~tmp~3); 5762#L949-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5955#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5740#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5865#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 5909#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5910#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 6052#L912 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 5682#L962 assume !(0 != start_simulation_~tmp___0~1); 5683#L930-3 [2018-11-18 15:17:50,665 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:50,665 INFO L82 PathProgramCache]: Analyzing trace with hash 793784326, now seen corresponding path program 1 times [2018-11-18 15:17:50,665 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:50,665 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:50,666 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:50,666 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:17:50,666 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:50,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:50,702 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:17:50,702 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:17:50,702 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 15:17:50,702 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:17:50,703 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:50,703 INFO L82 PathProgramCache]: Analyzing trace with hash -1647247313, now seen corresponding path program 1 times [2018-11-18 15:17:50,703 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:50,703 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:50,704 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:50,704 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:50,704 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:50,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:50,760 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:17:50,761 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:17:50,761 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:17:50,761 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:17:50,761 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:17:50,761 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:17:50,762 INFO L87 Difference]: Start difference. First operand 559 states and 831 transitions. cyclomatic complexity: 273 Second operand 3 states. [2018-11-18 15:17:50,802 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:17:50,803 INFO L93 Difference]: Finished difference Result 995 states and 1473 transitions. [2018-11-18 15:17:50,803 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:17:50,803 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 995 states and 1473 transitions. [2018-11-18 15:17:50,807 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 916 [2018-11-18 15:17:50,810 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 995 states to 995 states and 1473 transitions. [2018-11-18 15:17:50,811 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 995 [2018-11-18 15:17:50,811 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 995 [2018-11-18 15:17:50,811 INFO L73 IsDeterministic]: Start isDeterministic. Operand 995 states and 1473 transitions. [2018-11-18 15:17:50,813 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:17:50,813 INFO L705 BuchiCegarLoop]: Abstraction has 995 states and 1473 transitions. [2018-11-18 15:17:50,814 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 995 states and 1473 transitions. [2018-11-18 15:17:50,823 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 995 to 995. [2018-11-18 15:17:50,824 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 995 states. [2018-11-18 15:17:50,826 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 995 states to 995 states and 1473 transitions. [2018-11-18 15:17:50,826 INFO L728 BuchiCegarLoop]: Abstraction has 995 states and 1473 transitions. [2018-11-18 15:17:50,826 INFO L608 BuchiCegarLoop]: Abstraction has 995 states and 1473 transitions. [2018-11-18 15:17:50,826 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ [2018-11-18 15:17:50,826 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 995 states and 1473 transitions. [2018-11-18 15:17:50,829 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 916 [2018-11-18 15:17:50,829 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:17:50,829 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:17:50,830 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:50,830 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:50,830 INFO L794 eck$LassoCheckResult]: Stem: 7678#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 7582#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 7478#L893 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 7432#L409 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7433#L416 assume 1 == ~m_i~0;~m_st~0 := 0; 7646#L416-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7522#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7523#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7434#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7435#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7484#L441-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7485#L601 assume !(0 == ~M_E~0); 7747#L601-2 assume !(0 == ~T1_E~0); 7488#L606-1 assume !(0 == ~T2_E~0); 7372#L611-1 assume !(0 == ~T3_E~0); 7373#L616-1 assume !(0 == ~T4_E~0); 7213#L621-1 assume !(0 == ~T5_E~0); 7214#L626-1 assume !(0 == ~E_M~0); 7316#L631-1 assume !(0 == ~E_1~0); 7317#L636-1 assume 0 == ~E_2~0;~E_2~0 := 1; 7544#L641-1 assume !(0 == ~E_3~0); 7545#L646-1 assume !(0 == ~E_4~0); 7474#L651-1 assume !(0 == ~E_5~0); 7475#L656-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7756#L294 assume !(1 == ~m_pc~0); 7636#L294-2 is_master_triggered_~__retres1~0 := 0; 7635#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7650#L306 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 7651#L745 assume !(0 != activate_threads_~tmp~1); 7776#L745-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7414#L313 assume 1 == ~t1_pc~0; 7364#L314 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 7365#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7361#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 7228#L753 assume !(0 != activate_threads_~tmp___0~0); 7229#L753-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7233#L332 assume 1 == ~t2_pc~0; 7444#L333 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7442#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7443#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7468#L761 assume !(0 != activate_threads_~tmp___1~0); 7469#L761-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7470#L351 assume !(1 == ~t3_pc~0); 7588#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 7589#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7611#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7618#L769 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 7619#L769-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7620#L370 assume 1 == ~t4_pc~0; 7737#L371 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7732#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7733#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7753#L777 assume !(0 != activate_threads_~tmp___3~0); 7754#L777-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7305#L389 assume !(1 == ~t5_pc~0); 7269#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 7270#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7301#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7328#L785 assume !(0 != activate_threads_~tmp___4~0); 7329#L785-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7331#L669 assume !(1 == ~M_E~0); 7760#L669-2 assume !(1 == ~T1_E~0); 7542#L674-1 assume !(1 == ~T2_E~0); 7543#L679-1 assume !(1 == ~T3_E~0); 7472#L684-1 assume !(1 == ~T4_E~0); 7473#L689-1 assume !(1 == ~T5_E~0); 7670#L694-1 assume !(1 == ~E_M~0); 7394#L699-1 assume 1 == ~E_1~0;~E_1~0 := 2; 7395#L704-1 assume !(1 == ~E_2~0); 7202#L709-1 assume !(1 == ~E_3~0); 7203#L714-1 assume !(1 == ~E_4~0); 7309#L719-1 assume !(1 == ~E_5~0); 7310#L724-1 assume { :end_inline_reset_delta_events } true; 7759#L930-3 [2018-11-18 15:17:50,831 INFO L796 eck$LassoCheckResult]: Loop: 7759#L930-3 assume true; 7400#L930-1 assume !false; 7401#L931 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 7319#L576 assume true; 7320#L496-1 assume !false; 7461#L497 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7462#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 7294#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7464#L487 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 7385#L501 assume !(0 != eval_~tmp~0); 7386#L591 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 7438#L409-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 7439#L601-3 assume !(0 == ~M_E~0); 7751#L601-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8196#L606-3 assume !(0 == ~T2_E~0); 8195#L611-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8194#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8193#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8192#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8191#L631-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8190#L636-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8189#L641-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8188#L646-3 assume !(0 == ~E_4~0); 8187#L651-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8186#L656-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8185#L294-21 assume 1 == ~m_pc~0; 8183#L295-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 8182#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8181#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 8180#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 8179#L745-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8178#L313-21 assume 1 == ~t1_pc~0; 8176#L314-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 8175#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8174#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 8173#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 8172#L753-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8171#L332-21 assume !(1 == ~t2_pc~0); 8169#L332-23 is_transmit2_triggered_~__retres1~2 := 0; 8168#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8167#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 8166#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 8165#L761-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8164#L351-21 assume 1 == ~t3_pc~0; 8162#L352-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 8161#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8160#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 8159#L769-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 8158#L769-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8157#L370-21 assume !(1 == ~t4_pc~0); 8155#L370-23 is_transmit4_triggered_~__retres1~4 := 0; 8154#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8153#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 8152#L777-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 8151#L777-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8150#L389-21 assume 1 == ~t5_pc~0; 8148#L390-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 8147#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8146#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 8145#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 7266#L785-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7267#L669-3 assume !(1 == ~M_E~0); 7761#L669-5 assume !(1 == ~T1_E~0); 8077#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8076#L679-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8075#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8074#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8073#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8072#L699-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8071#L704-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8070#L709-3 assume !(1 == ~E_3~0); 8069#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7314#L719-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7315#L724-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7540#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 7297#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 8009#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 7977#L949 assume !(0 == start_simulation_~tmp~3); 7974#L949-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7829#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 7824#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7822#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 7820#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7818#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 7816#L912 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 7811#L962 assume !(0 != start_simulation_~tmp___0~1); 7759#L930-3 [2018-11-18 15:17:50,831 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:50,831 INFO L82 PathProgramCache]: Analyzing trace with hash 1473056580, now seen corresponding path program 1 times [2018-11-18 15:17:50,831 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:50,831 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:50,832 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:50,832 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:50,832 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:50,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:50,852 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:17:50,852 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:17:50,852 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 15:17:50,853 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:17:50,853 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:50,853 INFO L82 PathProgramCache]: Analyzing trace with hash 945455280, now seen corresponding path program 1 times [2018-11-18 15:17:50,853 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:50,853 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:50,854 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:50,854 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:50,854 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:50,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:50,890 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:17:50,890 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:17:50,890 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:17:50,890 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:17:50,890 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:17:50,890 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:17:50,891 INFO L87 Difference]: Start difference. First operand 995 states and 1473 transitions. cyclomatic complexity: 479 Second operand 3 states. [2018-11-18 15:17:50,928 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:17:50,928 INFO L93 Difference]: Finished difference Result 995 states and 1451 transitions. [2018-11-18 15:17:50,929 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:17:50,929 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 995 states and 1451 transitions. [2018-11-18 15:17:50,933 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 916 [2018-11-18 15:17:50,937 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 995 states to 995 states and 1451 transitions. [2018-11-18 15:17:50,937 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 995 [2018-11-18 15:17:50,938 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 995 [2018-11-18 15:17:50,938 INFO L73 IsDeterministic]: Start isDeterministic. Operand 995 states and 1451 transitions. [2018-11-18 15:17:50,940 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:17:50,940 INFO L705 BuchiCegarLoop]: Abstraction has 995 states and 1451 transitions. [2018-11-18 15:17:50,941 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 995 states and 1451 transitions. [2018-11-18 15:17:50,950 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 995 to 995. [2018-11-18 15:17:50,951 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 995 states. [2018-11-18 15:17:50,953 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 995 states to 995 states and 1451 transitions. [2018-11-18 15:17:50,953 INFO L728 BuchiCegarLoop]: Abstraction has 995 states and 1451 transitions. [2018-11-18 15:17:50,953 INFO L608 BuchiCegarLoop]: Abstraction has 995 states and 1451 transitions. [2018-11-18 15:17:50,953 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ [2018-11-18 15:17:50,953 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 995 states and 1451 transitions. [2018-11-18 15:17:50,956 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 916 [2018-11-18 15:17:50,956 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:17:50,956 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:17:50,957 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:50,957 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:50,957 INFO L794 eck$LassoCheckResult]: Stem: 9675#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 9579#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 9475#L893 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 9429#L409 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9430#L416 assume 1 == ~m_i~0;~m_st~0 := 0; 9643#L416-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9514#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9515#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9431#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9432#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9481#L441-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9482#L601 assume !(0 == ~M_E~0); 9744#L601-2 assume !(0 == ~T1_E~0); 9485#L606-1 assume !(0 == ~T2_E~0); 9369#L611-1 assume !(0 == ~T3_E~0); 9370#L616-1 assume !(0 == ~T4_E~0); 9210#L621-1 assume !(0 == ~T5_E~0); 9211#L626-1 assume !(0 == ~E_M~0); 9313#L631-1 assume !(0 == ~E_1~0); 9314#L636-1 assume !(0 == ~E_2~0); 9537#L641-1 assume !(0 == ~E_3~0); 9538#L646-1 assume !(0 == ~E_4~0); 9471#L651-1 assume !(0 == ~E_5~0); 9472#L656-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9753#L294 assume !(1 == ~m_pc~0); 9633#L294-2 is_master_triggered_~__retres1~0 := 0; 9632#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9647#L306 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 9648#L745 assume !(0 != activate_threads_~tmp~1); 9773#L745-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9411#L313 assume 1 == ~t1_pc~0; 9361#L314 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 9362#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9358#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 9225#L753 assume !(0 != activate_threads_~tmp___0~0); 9226#L753-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9230#L332 assume !(1 == ~t2_pc~0); 9442#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 9439#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9440#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 9465#L761 assume !(0 != activate_threads_~tmp___1~0); 9466#L761-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9467#L351 assume !(1 == ~t3_pc~0); 9585#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 9586#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9608#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 9615#L769 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 9616#L769-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9617#L370 assume 1 == ~t4_pc~0; 9734#L371 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9729#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9730#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9750#L777 assume !(0 != activate_threads_~tmp___3~0); 9751#L777-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9302#L389 assume !(1 == ~t5_pc~0); 9266#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 9267#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9298#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9325#L785 assume !(0 != activate_threads_~tmp___4~0); 9326#L785-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9328#L669 assume !(1 == ~M_E~0); 9757#L669-2 assume !(1 == ~T1_E~0); 9535#L674-1 assume !(1 == ~T2_E~0); 9536#L679-1 assume !(1 == ~T3_E~0); 9469#L684-1 assume !(1 == ~T4_E~0); 9470#L689-1 assume !(1 == ~T5_E~0); 9667#L694-1 assume !(1 == ~E_M~0); 9391#L699-1 assume 1 == ~E_1~0;~E_1~0 := 2; 9392#L704-1 assume !(1 == ~E_2~0); 9199#L709-1 assume !(1 == ~E_3~0); 9200#L714-1 assume !(1 == ~E_4~0); 9306#L719-1 assume !(1 == ~E_5~0); 9307#L724-1 assume { :end_inline_reset_delta_events } true; 9756#L930-3 [2018-11-18 15:17:50,958 INFO L796 eck$LassoCheckResult]: Loop: 9756#L930-3 assume true; 9397#L930-1 assume !false; 9398#L931 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 9316#L576 assume true; 9317#L496-1 assume !false; 9458#L497 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 9459#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 9291#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 9461#L487 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 9382#L501 assume !(0 != eval_~tmp~0); 9383#L591 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 9435#L409-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 9436#L601-3 assume !(0 == ~M_E~0); 9748#L601-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10193#L606-3 assume !(0 == ~T2_E~0); 10192#L611-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10191#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10190#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10189#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10188#L631-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10187#L636-3 assume !(0 == ~E_2~0); 10186#L641-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10185#L646-3 assume !(0 == ~E_4~0); 10184#L651-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10183#L656-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10182#L294-21 assume 1 == ~m_pc~0; 10180#L295-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 10179#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10178#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 10177#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 10176#L745-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10175#L313-21 assume 1 == ~t1_pc~0; 10173#L314-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 10172#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10171#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 10170#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 10169#L753-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10168#L332-21 assume !(1 == ~t2_pc~0); 10166#L332-23 is_transmit2_triggered_~__retres1~2 := 0; 10165#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10164#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 10163#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 10162#L761-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10161#L351-21 assume !(1 == ~t3_pc~0); 10160#L351-23 is_transmit3_triggered_~__retres1~3 := 0; 10158#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10157#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 10156#L769-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 10155#L769-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 10154#L370-21 assume !(1 == ~t4_pc~0); 10152#L370-23 is_transmit4_triggered_~__retres1~4 := 0; 10151#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 10150#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 10149#L777-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 10148#L777-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10147#L389-21 assume 1 == ~t5_pc~0; 10145#L390-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 10144#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 10143#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 10142#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 9263#L785-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9264#L669-3 assume !(1 == ~M_E~0); 9758#L669-5 assume !(1 == ~T1_E~0); 10074#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10073#L679-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10072#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10071#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10070#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10069#L699-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10068#L704-3 assume !(1 == ~E_2~0); 10067#L709-3 assume !(1 == ~E_3~0); 10066#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9311#L719-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9312#L724-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 9532#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 9294#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 10006#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 9974#L949 assume !(0 == start_simulation_~tmp~3); 9971#L949-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 9826#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 9821#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 9819#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 9817#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 9815#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 9813#L912 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 9808#L962 assume !(0 != start_simulation_~tmp___0~1); 9756#L930-3 [2018-11-18 15:17:50,958 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:50,958 INFO L82 PathProgramCache]: Analyzing trace with hash -820631741, now seen corresponding path program 1 times [2018-11-18 15:17:50,958 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:50,958 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:50,959 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:50,959 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:50,959 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:50,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:50,978 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:17:50,979 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:17:50,979 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 15:17:50,979 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:17:50,979 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:50,979 INFO L82 PathProgramCache]: Analyzing trace with hash 523670257, now seen corresponding path program 1 times [2018-11-18 15:17:50,979 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:50,979 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:50,980 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:50,980 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:50,980 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:50,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:51,007 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:17:51,007 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:17:51,007 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:17:51,007 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:17:51,007 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:17:51,008 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:17:51,008 INFO L87 Difference]: Start difference. First operand 995 states and 1451 transitions. cyclomatic complexity: 457 Second operand 3 states. [2018-11-18 15:17:51,104 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:17:51,105 INFO L93 Difference]: Finished difference Result 1807 states and 2615 transitions. [2018-11-18 15:17:51,106 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:17:51,106 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1807 states and 2615 transitions. [2018-11-18 15:17:51,113 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1725 [2018-11-18 15:17:51,119 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1807 states to 1807 states and 2615 transitions. [2018-11-18 15:17:51,120 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1807 [2018-11-18 15:17:51,121 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1807 [2018-11-18 15:17:51,121 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1807 states and 2615 transitions. [2018-11-18 15:17:51,123 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:17:51,124 INFO L705 BuchiCegarLoop]: Abstraction has 1807 states and 2615 transitions. [2018-11-18 15:17:51,125 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1807 states and 2615 transitions. [2018-11-18 15:17:51,144 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1807 to 1801. [2018-11-18 15:17:51,144 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1801 states. [2018-11-18 15:17:51,147 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2609 transitions. [2018-11-18 15:17:51,147 INFO L728 BuchiCegarLoop]: Abstraction has 1801 states and 2609 transitions. [2018-11-18 15:17:51,147 INFO L608 BuchiCegarLoop]: Abstraction has 1801 states and 2609 transitions. [2018-11-18 15:17:51,147 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ [2018-11-18 15:17:51,148 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2609 transitions. [2018-11-18 15:17:51,153 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1719 [2018-11-18 15:17:51,153 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:17:51,153 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:17:51,154 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:51,154 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:51,154 INFO L794 eck$LassoCheckResult]: Stem: 12505#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 12407#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 12295#L893 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 12249#L409 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12250#L416 assume 1 == ~m_i~0;~m_st~0 := 0; 12473#L416-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12337#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12338#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12251#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12252#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12301#L441-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12302#L601 assume !(0 == ~M_E~0); 12578#L601-2 assume !(0 == ~T1_E~0); 12305#L606-1 assume !(0 == ~T2_E~0); 12173#L611-1 assume !(0 == ~T3_E~0); 12174#L616-1 assume !(0 == ~T4_E~0); 12019#L621-1 assume !(0 == ~T5_E~0); 12020#L626-1 assume !(0 == ~E_M~0); 12121#L631-1 assume !(0 == ~E_1~0); 12122#L636-1 assume !(0 == ~E_2~0); 12364#L641-1 assume !(0 == ~E_3~0); 12365#L646-1 assume !(0 == ~E_4~0); 12291#L651-1 assume !(0 == ~E_5~0); 12292#L656-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12586#L294 assume !(1 == ~m_pc~0); 12463#L294-2 is_master_triggered_~__retres1~0 := 0; 12462#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12477#L306 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 12478#L745 assume !(0 != activate_threads_~tmp~1); 12620#L745-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12227#L313 assume !(1 == ~t1_pc~0); 12228#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 12226#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12166#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 12034#L753 assume !(0 != activate_threads_~tmp___0~0); 12035#L753-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12039#L332 assume !(1 == ~t2_pc~0); 12262#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 12259#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12260#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 12285#L761 assume !(0 != activate_threads_~tmp___1~0); 12286#L761-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12287#L351 assume !(1 == ~t3_pc~0); 12413#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 12414#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12437#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 12444#L769 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 12445#L769-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12447#L370 assume 1 == ~t4_pc~0; 12567#L371 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 12562#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12563#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12583#L777 assume !(0 != activate_threads_~tmp___3~0); 12584#L777-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12110#L389 assume !(1 == ~t5_pc~0); 12075#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 12076#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12106#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 12133#L785 assume !(0 != activate_threads_~tmp___4~0); 12134#L785-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12136#L669 assume !(1 == ~M_E~0); 12598#L669-2 assume !(1 == ~T1_E~0); 12362#L674-1 assume !(1 == ~T2_E~0); 12363#L679-1 assume !(1 == ~T3_E~0); 12289#L684-1 assume !(1 == ~T4_E~0); 12290#L689-1 assume !(1 == ~T5_E~0); 12497#L694-1 assume !(1 == ~E_M~0); 12198#L699-1 assume 1 == ~E_1~0;~E_1~0 := 2; 12199#L704-1 assume !(1 == ~E_2~0); 12008#L709-1 assume !(1 == ~E_3~0); 12009#L714-1 assume !(1 == ~E_4~0); 12114#L719-1 assume !(1 == ~E_5~0); 12115#L724-1 assume { :end_inline_reset_delta_events } true; 12050#L930-3 [2018-11-18 15:17:51,154 INFO L796 eck$LassoCheckResult]: Loop: 12050#L930-3 assume true; 12208#L930-1 assume !false; 12209#L931 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 12124#L576 assume true; 12125#L496-1 assume !false; 12820#L497 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 12718#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 12714#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 13374#L487 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 13373#L501 assume !(0 != eval_~tmp~0); 12624#L591 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 12255#L409-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 12256#L601-3 assume !(0 == ~M_E~0); 12558#L601-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12309#L606-3 assume !(0 == ~T2_E~0); 12185#L611-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12186#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12025#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12026#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12093#L631-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12094#L636-3 assume !(0 == ~E_2~0); 12350#L641-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12351#L646-3 assume !(0 == ~E_4~0); 12276#L651-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12277#L656-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12581#L294-21 assume 1 == ~m_pc~0; 12474#L295-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 12475#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12466#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 12467#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 12599#L745-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12169#L313-21 assume !(1 == ~t1_pc~0); 12170#L313-23 is_transmit1_triggered_~__retres1~1 := 0; 13759#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13758#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 13757#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 13756#L753-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13755#L332-21 assume !(1 == ~t2_pc~0); 13753#L332-23 is_transmit2_triggered_~__retres1~2 := 0; 13752#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13751#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 13750#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 13749#L761-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13748#L351-21 assume 1 == ~t3_pc~0; 12500#L352-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 12395#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12396#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 12402#L769-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 12403#L769-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12406#L370-21 assume 1 == ~t4_pc~0; 12605#L371-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 12553#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12554#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12534#L777-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 12535#L777-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12037#L389-21 assume 1 == ~t5_pc~0; 12038#L390-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 12013#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12061#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 12070#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 12071#L785-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12073#L669-3 assume !(1 == ~M_E~0); 12595#L669-5 assume !(1 == ~T1_E~0); 12367#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12368#L679-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12272#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12273#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12304#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12171#L699-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12172#L704-3 assume !(1 == ~E_2~0); 12017#L709-3 assume !(1 == ~E_3~0); 12018#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12119#L719-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12120#L724-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 12358#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 12103#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 12356#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 12357#L949 assume !(0 == start_simulation_~tmp~3); 12130#L949-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 12339#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 12108#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 12248#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 13466#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 13464#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 12448#L912 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 12049#L962 assume !(0 != start_simulation_~tmp___0~1); 12050#L930-3 [2018-11-18 15:17:51,155 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:51,155 INFO L82 PathProgramCache]: Analyzing trace with hash 1077898564, now seen corresponding path program 1 times [2018-11-18 15:17:51,155 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:51,155 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:51,155 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:51,156 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:51,156 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:51,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:51,180 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:17:51,180 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:17:51,180 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 15:17:51,180 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:17:51,180 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:51,180 INFO L82 PathProgramCache]: Analyzing trace with hash 686718640, now seen corresponding path program 1 times [2018-11-18 15:17:51,180 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:51,181 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:51,181 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:51,181 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:51,181 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:51,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:51,204 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:17:51,204 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:17:51,204 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:17:51,204 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:17:51,204 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:17:51,204 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:17:51,204 INFO L87 Difference]: Start difference. First operand 1801 states and 2609 transitions. cyclomatic complexity: 810 Second operand 3 states. [2018-11-18 15:17:51,268 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:17:51,268 INFO L93 Difference]: Finished difference Result 3321 states and 4783 transitions. [2018-11-18 15:17:51,269 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:17:51,269 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3321 states and 4783 transitions. [2018-11-18 15:17:51,281 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3228 [2018-11-18 15:17:51,292 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3321 states to 3321 states and 4783 transitions. [2018-11-18 15:17:51,292 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3321 [2018-11-18 15:17:51,294 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3321 [2018-11-18 15:17:51,294 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3321 states and 4783 transitions. [2018-11-18 15:17:51,298 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:17:51,298 INFO L705 BuchiCegarLoop]: Abstraction has 3321 states and 4783 transitions. [2018-11-18 15:17:51,300 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3321 states and 4783 transitions. [2018-11-18 15:17:51,331 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3321 to 3309. [2018-11-18 15:17:51,331 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3309 states. [2018-11-18 15:17:51,338 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3309 states to 3309 states and 4771 transitions. [2018-11-18 15:17:51,338 INFO L728 BuchiCegarLoop]: Abstraction has 3309 states and 4771 transitions. [2018-11-18 15:17:51,338 INFO L608 BuchiCegarLoop]: Abstraction has 3309 states and 4771 transitions. [2018-11-18 15:17:51,338 INFO L442 BuchiCegarLoop]: ======== Iteration 10============ [2018-11-18 15:17:51,338 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3309 states and 4771 transitions. [2018-11-18 15:17:51,346 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3216 [2018-11-18 15:17:51,346 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:17:51,346 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:17:51,347 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:51,347 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:51,348 INFO L794 eck$LassoCheckResult]: Stem: 17625#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 17527#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 17418#L893 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 17373#L409 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17374#L416 assume 1 == ~m_i~0;~m_st~0 := 0; 17592#L416-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17458#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17459#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17377#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17378#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17424#L441-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17425#L601 assume !(0 == ~M_E~0); 17689#L601-2 assume !(0 == ~T1_E~0); 17428#L606-1 assume !(0 == ~T2_E~0); 17302#L611-1 assume !(0 == ~T3_E~0); 17303#L616-1 assume !(0 == ~T4_E~0); 17149#L621-1 assume !(0 == ~T5_E~0); 17150#L626-1 assume !(0 == ~E_M~0); 17249#L631-1 assume !(0 == ~E_1~0); 17250#L636-1 assume !(0 == ~E_2~0); 17481#L641-1 assume !(0 == ~E_3~0); 17482#L646-1 assume !(0 == ~E_4~0); 17414#L651-1 assume !(0 == ~E_5~0); 17415#L656-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 17698#L294 assume !(1 == ~m_pc~0); 17582#L294-2 is_master_triggered_~__retres1~0 := 0; 17581#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 17596#L306 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 17597#L745 assume !(0 != activate_threads_~tmp~1); 17743#L745-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 17349#L313 assume !(1 == ~t1_pc~0); 17350#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 17348#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17294#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 17164#L753 assume !(0 != activate_threads_~tmp___0~0); 17165#L753-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 17168#L332 assume !(1 == ~t2_pc~0); 17386#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 17383#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 17384#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 17408#L761 assume !(0 != activate_threads_~tmp___1~0); 17409#L761-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 17410#L351 assume !(1 == ~t3_pc~0); 17533#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 17534#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 17556#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 17564#L769 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 17565#L769-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 17566#L370 assume !(1 == ~t4_pc~0); 17681#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 17678#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 17679#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 17694#L777 assume !(0 != activate_threads_~tmp___3~0); 17695#L777-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 17239#L389 assume !(1 == ~t5_pc~0); 17205#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 17206#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 17234#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 17261#L785 assume !(0 != activate_threads_~tmp___4~0); 17262#L785-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17264#L669 assume !(1 == ~M_E~0); 17709#L669-2 assume !(1 == ~T1_E~0); 17479#L674-1 assume !(1 == ~T2_E~0); 17480#L679-1 assume !(1 == ~T3_E~0); 17412#L684-1 assume !(1 == ~T4_E~0); 17413#L689-1 assume !(1 == ~T5_E~0); 17616#L694-1 assume !(1 == ~E_M~0); 17325#L699-1 assume 1 == ~E_1~0;~E_1~0 := 2; 17326#L704-1 assume !(1 == ~E_2~0); 17137#L709-1 assume !(1 == ~E_3~0); 17138#L714-1 assume !(1 == ~E_4~0); 17244#L719-1 assume !(1 == ~E_5~0); 17245#L724-1 assume { :end_inline_reset_delta_events } true; 17708#L930-3 [2018-11-18 15:17:51,348 INFO L796 eck$LassoCheckResult]: Loop: 17708#L930-3 assume true; 18887#L930-1 assume !false; 18885#L931 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 18879#L576 assume true; 18877#L496-1 assume !false; 18875#L497 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 18870#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 18863#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 18861#L487 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 18858#L501 assume !(0 != eval_~tmp~0); 18859#L591 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 20379#L409-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 20376#L601-3 assume !(0 == ~M_E~0); 20374#L601-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20372#L606-3 assume !(0 == ~T2_E~0); 20370#L611-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20368#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20366#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20363#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20361#L631-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20359#L636-3 assume !(0 == ~E_2~0); 20357#L641-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20356#L646-3 assume !(0 == ~E_4~0); 20354#L651-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20352#L656-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 20351#L294-21 assume 1 == ~m_pc~0; 20349#L295-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 20239#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 20238#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 20237#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 20236#L745-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20235#L313-21 assume !(1 == ~t1_pc~0); 20234#L313-23 is_transmit1_triggered_~__retres1~1 := 0; 20233#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 20232#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 20231#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 20229#L753-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 20227#L332-21 assume !(1 == ~t2_pc~0); 20224#L332-23 is_transmit2_triggered_~__retres1~2 := 0; 20221#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 20219#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 20217#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 20215#L761-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 20214#L351-21 assume 1 == ~t3_pc~0; 20212#L352-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 20211#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 20210#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 20209#L769-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 17525#L769-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 17526#L370-21 assume !(1 == ~t4_pc~0); 17744#L370-23 is_transmit4_triggered_~__retres1~4 := 0; 20155#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 20153#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 20151#L777-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 20150#L777-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 20149#L389-21 assume 1 == ~t5_pc~0; 20147#L390-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 20146#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 20145#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 20144#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 20142#L785-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20140#L669-3 assume !(1 == ~M_E~0); 19495#L669-5 assume !(1 == ~T1_E~0); 20137#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20135#L679-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20132#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20130#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20128#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 20126#L699-3 assume 1 == ~E_1~0;~E_1~0 := 2; 20124#L704-3 assume !(1 == ~E_2~0); 18966#L709-3 assume !(1 == ~E_3~0); 18959#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18957#L719-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18955#L724-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 18938#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 18933#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 18930#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 18926#L949 assume !(0 == start_simulation_~tmp~3); 18921#L949-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 18905#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 18901#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 18899#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 18897#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 18893#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 18891#L912 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 18889#L962 assume !(0 != start_simulation_~tmp___0~1); 17708#L930-3 [2018-11-18 15:17:51,348 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:51,348 INFO L82 PathProgramCache]: Analyzing trace with hash -979705467, now seen corresponding path program 1 times [2018-11-18 15:17:51,348 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:51,348 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:51,349 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:51,349 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:51,349 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:51,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:51,378 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:17:51,378 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:17:51,378 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 15:17:51,378 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:17:51,378 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:51,378 INFO L82 PathProgramCache]: Analyzing trace with hash 1811978609, now seen corresponding path program 1 times [2018-11-18 15:17:51,378 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:51,378 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:51,379 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:51,379 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:51,379 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:51,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:51,397 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:17:51,397 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:17:51,397 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:17:51,398 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:17:51,398 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:17:51,398 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:17:51,398 INFO L87 Difference]: Start difference. First operand 3309 states and 4771 transitions. cyclomatic complexity: 1466 Second operand 3 states. [2018-11-18 15:17:51,444 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:17:51,444 INFO L93 Difference]: Finished difference Result 3309 states and 4721 transitions. [2018-11-18 15:17:51,445 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:17:51,445 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3309 states and 4721 transitions. [2018-11-18 15:17:51,455 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3216 [2018-11-18 15:17:51,466 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3309 states to 3309 states and 4721 transitions. [2018-11-18 15:17:51,466 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3309 [2018-11-18 15:17:51,468 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3309 [2018-11-18 15:17:51,468 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3309 states and 4721 transitions. [2018-11-18 15:17:51,472 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:17:51,472 INFO L705 BuchiCegarLoop]: Abstraction has 3309 states and 4721 transitions. [2018-11-18 15:17:51,474 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3309 states and 4721 transitions. [2018-11-18 15:17:51,505 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3309 to 3309. [2018-11-18 15:17:51,505 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3309 states. [2018-11-18 15:17:51,512 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3309 states to 3309 states and 4721 transitions. [2018-11-18 15:17:51,512 INFO L728 BuchiCegarLoop]: Abstraction has 3309 states and 4721 transitions. [2018-11-18 15:17:51,512 INFO L608 BuchiCegarLoop]: Abstraction has 3309 states and 4721 transitions. [2018-11-18 15:17:51,512 INFO L442 BuchiCegarLoop]: ======== Iteration 11============ [2018-11-18 15:17:51,512 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3309 states and 4721 transitions. [2018-11-18 15:17:51,519 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3216 [2018-11-18 15:17:51,519 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:17:51,519 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:17:51,520 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:51,520 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:51,520 INFO L794 eck$LassoCheckResult]: Stem: 24244#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 24146#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 24042#L893 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 23997#L409 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23998#L416 assume 1 == ~m_i~0;~m_st~0 := 0; 24210#L416-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24081#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24082#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23999#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 24000#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 24048#L441-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24049#L601 assume !(0 == ~M_E~0); 24310#L601-2 assume !(0 == ~T1_E~0); 24052#L606-1 assume !(0 == ~T2_E~0); 23924#L611-1 assume !(0 == ~T3_E~0); 23925#L616-1 assume !(0 == ~T4_E~0); 23773#L621-1 assume !(0 == ~T5_E~0); 23774#L626-1 assume !(0 == ~E_M~0); 23875#L631-1 assume !(0 == ~E_1~0); 23876#L636-1 assume !(0 == ~E_2~0); 24104#L641-1 assume !(0 == ~E_3~0); 24105#L646-1 assume !(0 == ~E_4~0); 24038#L651-1 assume !(0 == ~E_5~0); 24039#L656-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 24318#L294 assume !(1 == ~m_pc~0); 24200#L294-2 is_master_triggered_~__retres1~0 := 0; 24199#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 24214#L306 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 24215#L745 assume !(0 != activate_threads_~tmp~1); 24367#L745-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 23975#L313 assume !(1 == ~t1_pc~0); 23976#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 23974#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 23917#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 23788#L753 assume !(0 != activate_threads_~tmp___0~0); 23789#L753-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 23794#L332 assume !(1 == ~t2_pc~0); 24010#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 24007#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 24008#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 24032#L761 assume !(0 != activate_threads_~tmp___1~0); 24033#L761-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 24034#L351 assume !(1 == ~t3_pc~0); 24152#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 24153#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 24175#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 24182#L769 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 24183#L769-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 24184#L370 assume !(1 == ~t4_pc~0); 24303#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 24298#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 24299#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 24315#L777 assume !(0 != activate_threads_~tmp___3~0); 24316#L777-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 23864#L389 assume !(1 == ~t5_pc~0); 23829#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 23830#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 23860#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 23887#L785 assume !(0 != activate_threads_~tmp___4~0); 23888#L785-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23891#L669 assume !(1 == ~M_E~0); 24329#L669-2 assume !(1 == ~T1_E~0); 24102#L674-1 assume !(1 == ~T2_E~0); 24103#L679-1 assume !(1 == ~T3_E~0); 24036#L684-1 assume !(1 == ~T4_E~0); 24037#L689-1 assume !(1 == ~T5_E~0); 24234#L694-1 assume !(1 == ~E_M~0); 23948#L699-1 assume !(1 == ~E_1~0); 23949#L704-1 assume !(1 == ~E_2~0); 23762#L709-1 assume !(1 == ~E_3~0); 23763#L714-1 assume !(1 == ~E_4~0); 23868#L719-1 assume !(1 == ~E_5~0); 23869#L724-1 assume { :end_inline_reset_delta_events } true; 24328#L930-3 [2018-11-18 15:17:51,520 INFO L796 eck$LassoCheckResult]: Loop: 24328#L930-3 assume true; 25525#L930-1 assume !false; 25519#L931 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 25514#L576 assume true; 25512#L496-1 assume !false; 25509#L497 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 25395#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 25389#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 25387#L487 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 25385#L501 assume !(0 != eval_~tmp~0); 25386#L591 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 27070#L409-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 27069#L601-3 assume !(0 == ~M_E~0); 27068#L601-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 27067#L606-3 assume !(0 == ~T2_E~0); 27066#L611-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 27065#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 27064#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 27063#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 27062#L631-3 assume !(0 == ~E_1~0); 27061#L636-3 assume !(0 == ~E_2~0); 27060#L641-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27059#L646-3 assume !(0 == ~E_4~0); 27058#L651-3 assume 0 == ~E_5~0;~E_5~0 := 1; 27057#L656-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 27056#L294-21 assume 1 == ~m_pc~0; 27054#L295-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 27053#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 24203#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 24204#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 24333#L745-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 27051#L313-21 assume !(1 == ~t1_pc~0); 27050#L313-23 is_transmit1_triggered_~__retres1~1 := 0; 27049#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 27048#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 27047#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 27046#L753-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 27045#L332-21 assume !(1 == ~t2_pc~0); 27043#L332-23 is_transmit2_triggered_~__retres1~2 := 0; 27042#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 27007#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 27006#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 27005#L761-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 27004#L351-21 assume 1 == ~t3_pc~0; 27002#L352-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 27001#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 27000#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 26999#L769-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 26998#L769-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 26997#L370-21 assume !(1 == ~t4_pc~0); 26996#L370-23 is_transmit4_triggered_~__retres1~4 := 0; 26995#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 26994#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 26993#L777-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 26991#L777-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 26799#L389-21 assume 1 == ~t5_pc~0; 23984#L390-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 23767#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 23815#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 23824#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 23825#L785-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23827#L669-3 assume !(1 == ~M_E~0); 25809#L669-5 assume !(1 == ~T1_E~0); 25807#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25805#L679-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25803#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25801#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25793#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25737#L699-3 assume !(1 == ~E_1~0); 25736#L704-3 assume !(1 == ~E_2~0); 25735#L709-3 assume !(1 == ~E_3~0); 25734#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25732#L719-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25701#L724-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 25694#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 25679#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 25676#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 25673#L949 assume !(0 == start_simulation_~tmp~3); 25668#L949-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 25582#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 25574#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 25567#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 25561#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 25554#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 25546#L912 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 25538#L962 assume !(0 != start_simulation_~tmp___0~1); 24328#L930-3 [2018-11-18 15:17:51,521 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:51,521 INFO L82 PathProgramCache]: Analyzing trace with hash -922447165, now seen corresponding path program 1 times [2018-11-18 15:17:51,521 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:51,521 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:51,521 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:51,521 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:51,521 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:51,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:51,606 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:17:51,606 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:17:51,607 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:17:51,607 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:17:51,607 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:51,607 INFO L82 PathProgramCache]: Analyzing trace with hash -1398319823, now seen corresponding path program 1 times [2018-11-18 15:17:51,607 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:51,607 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:51,608 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:51,608 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:51,608 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:51,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:51,638 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:17:51,638 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:17:51,638 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:17:51,639 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:17:51,639 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:17:51,639 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:17:51,639 INFO L87 Difference]: Start difference. First operand 3309 states and 4721 transitions. cyclomatic complexity: 1416 Second operand 5 states. [2018-11-18 15:17:51,891 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:17:51,891 INFO L93 Difference]: Finished difference Result 8294 states and 11832 transitions. [2018-11-18 15:17:51,892 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 15:17:51,892 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8294 states and 11832 transitions. [2018-11-18 15:17:51,923 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8112 [2018-11-18 15:17:51,956 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8294 states to 8294 states and 11832 transitions. [2018-11-18 15:17:51,956 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8294 [2018-11-18 15:17:51,963 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8294 [2018-11-18 15:17:51,963 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8294 states and 11832 transitions. [2018-11-18 15:17:51,973 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:17:51,974 INFO L705 BuchiCegarLoop]: Abstraction has 8294 states and 11832 transitions. [2018-11-18 15:17:51,979 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8294 states and 11832 transitions. [2018-11-18 15:17:52,048 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8294 to 3468. [2018-11-18 15:17:52,048 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3468 states. [2018-11-18 15:17:52,055 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3468 states to 3468 states and 4880 transitions. [2018-11-18 15:17:52,056 INFO L728 BuchiCegarLoop]: Abstraction has 3468 states and 4880 transitions. [2018-11-18 15:17:52,056 INFO L608 BuchiCegarLoop]: Abstraction has 3468 states and 4880 transitions. [2018-11-18 15:17:52,056 INFO L442 BuchiCegarLoop]: ======== Iteration 12============ [2018-11-18 15:17:52,056 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3468 states and 4880 transitions. [2018-11-18 15:17:52,065 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3372 [2018-11-18 15:17:52,065 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:17:52,065 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:17:52,066 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:52,066 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:52,066 INFO L794 eck$LassoCheckResult]: Stem: 35985#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 35873#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 35709#L893 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 35659#L409 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 35660#L416 assume 1 == ~m_i~0;~m_st~0 := 0; 35944#L416-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 35754#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35755#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35663#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35664#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35715#L441-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35716#L601 assume !(0 == ~M_E~0); 36096#L601-2 assume !(0 == ~T1_E~0); 35719#L606-1 assume !(0 == ~T2_E~0); 35551#L611-1 assume !(0 == ~T3_E~0); 35552#L616-1 assume !(0 == ~T4_E~0); 35391#L621-1 assume !(0 == ~T5_E~0); 35392#L626-1 assume !(0 == ~E_M~0); 35496#L631-1 assume !(0 == ~E_1~0); 35497#L636-1 assume !(0 == ~E_2~0); 35790#L641-1 assume !(0 == ~E_3~0); 35791#L646-1 assume !(0 == ~E_4~0); 35705#L651-1 assume !(0 == ~E_5~0); 35706#L656-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 36107#L294 assume !(1 == ~m_pc~0); 35936#L294-2 is_master_triggered_~__retres1~0 := 0; 35935#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 35948#L306 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 35949#L745 assume !(0 != activate_threads_~tmp~1); 36203#L745-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 35613#L313 assume !(1 == ~t1_pc~0); 35614#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 35612#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 35541#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 35408#L753 assume !(0 != activate_threads_~tmp___0~0); 35409#L753-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 35412#L332 assume !(1 == ~t2_pc~0); 35672#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 35669#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 35670#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 35698#L761 assume !(0 != activate_threads_~tmp___1~0); 35699#L761-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 35700#L351 assume !(1 == ~t3_pc~0); 35880#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 35881#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 35906#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 35915#L769 assume !(0 != activate_threads_~tmp___2~0); 35916#L769-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 35917#L370 assume !(1 == ~t4_pc~0); 36089#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 36086#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 36087#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 36104#L777 assume !(0 != activate_threads_~tmp___3~0); 36105#L777-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 35486#L389 assume !(1 == ~t5_pc~0); 35449#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 35450#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 35481#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 35509#L785 assume !(0 != activate_threads_~tmp___4~0); 35510#L785-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35513#L669 assume !(1 == ~M_E~0); 36124#L669-2 assume !(1 == ~T1_E~0); 35788#L674-1 assume !(1 == ~T2_E~0); 35789#L679-1 assume !(1 == ~T3_E~0); 35703#L684-1 assume !(1 == ~T4_E~0); 35704#L689-1 assume !(1 == ~T5_E~0); 35968#L694-1 assume !(1 == ~E_M~0); 35575#L699-1 assume !(1 == ~E_1~0); 35576#L704-1 assume !(1 == ~E_2~0); 35378#L709-1 assume !(1 == ~E_3~0); 35379#L714-1 assume !(1 == ~E_4~0); 35491#L719-1 assume !(1 == ~E_5~0); 35492#L724-1 assume { :end_inline_reset_delta_events } true; 36123#L930-3 [2018-11-18 15:17:52,067 INFO L796 eck$LassoCheckResult]: Loop: 36123#L930-3 assume true; 37561#L930-1 assume !false; 37556#L931 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 37549#L576 assume true; 37544#L496-1 assume !false; 37542#L497 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 37530#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 37522#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 37518#L487 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 37511#L501 assume !(0 != eval_~tmp~0); 37512#L591 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 38321#L409-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 38320#L601-3 assume !(0 == ~M_E~0); 38319#L601-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 38318#L606-3 assume !(0 == ~T2_E~0); 38317#L611-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38316#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 38315#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 38314#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 38313#L631-3 assume !(0 == ~E_1~0); 38312#L636-3 assume !(0 == ~E_2~0); 38311#L641-3 assume 0 == ~E_3~0;~E_3~0 := 1; 38310#L646-3 assume !(0 == ~E_4~0); 38309#L651-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38308#L656-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 38307#L294-21 assume 1 == ~m_pc~0; 38305#L295-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 38304#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 38303#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 38302#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 38301#L745-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 38300#L313-21 assume !(1 == ~t1_pc~0); 38299#L313-23 is_transmit1_triggered_~__retres1~1 := 0; 38298#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 38297#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 38296#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 38295#L753-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 38294#L332-21 assume !(1 == ~t2_pc~0); 38292#L332-23 is_transmit2_triggered_~__retres1~2 := 0; 38291#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 38290#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 38289#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 38288#L761-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 38287#L351-21 assume 1 == ~t3_pc~0; 38285#L352-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 38283#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 38281#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 38279#L769-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 38278#L769-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 38277#L370-21 assume !(1 == ~t4_pc~0); 38276#L370-23 is_transmit4_triggered_~__retres1~4 := 0; 38275#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 38274#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 38273#L777-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 38272#L777-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 38271#L389-21 assume 1 == ~t5_pc~0; 38269#L390-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 38268#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 38267#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 38266#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 38265#L785-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38264#L669-3 assume !(1 == ~M_E~0); 37773#L669-5 assume !(1 == ~T1_E~0); 38263#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 38262#L679-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38261#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 38260#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 38259#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 38258#L699-3 assume !(1 == ~E_1~0); 38257#L704-3 assume !(1 == ~E_2~0); 38256#L709-3 assume !(1 == ~E_3~0); 38255#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 38254#L719-3 assume 1 == ~E_5~0;~E_5~0 := 2; 38253#L724-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 35782#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 35478#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 35697#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 35779#L949 assume !(0 == start_simulation_~tmp~3); 37687#L949-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 37681#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 37646#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 37643#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 37640#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 37608#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 37577#L912 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 37570#L962 assume !(0 != start_simulation_~tmp___0~1); 36123#L930-3 [2018-11-18 15:17:52,067 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:52,067 INFO L82 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 1 times [2018-11-18 15:17:52,067 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:52,067 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:52,068 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:52,068 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:52,068 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:52,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:17:52,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:17:52,104 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:52,105 INFO L82 PathProgramCache]: Analyzing trace with hash -1398319823, now seen corresponding path program 2 times [2018-11-18 15:17:52,105 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:52,105 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:52,105 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:52,105 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:52,106 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:52,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:52,153 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:17:52,154 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:17:52,154 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:17:52,154 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:17:52,154 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:17:52,154 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:17:52,154 INFO L87 Difference]: Start difference. First operand 3468 states and 4880 transitions. cyclomatic complexity: 1416 Second operand 3 states. [2018-11-18 15:17:52,180 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:17:52,180 INFO L93 Difference]: Finished difference Result 3980 states and 5597 transitions. [2018-11-18 15:17:52,181 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:17:52,181 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3980 states and 5597 transitions. [2018-11-18 15:17:52,189 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3828 [2018-11-18 15:17:52,198 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3980 states to 3980 states and 5597 transitions. [2018-11-18 15:17:52,198 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3980 [2018-11-18 15:17:52,200 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3980 [2018-11-18 15:17:52,200 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3980 states and 5597 transitions. [2018-11-18 15:17:52,203 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:17:52,203 INFO L705 BuchiCegarLoop]: Abstraction has 3980 states and 5597 transitions. [2018-11-18 15:17:52,205 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3980 states and 5597 transitions. [2018-11-18 15:17:52,231 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3980 to 3980. [2018-11-18 15:17:52,231 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3980 states. [2018-11-18 15:17:52,236 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3980 states to 3980 states and 5597 transitions. [2018-11-18 15:17:52,236 INFO L728 BuchiCegarLoop]: Abstraction has 3980 states and 5597 transitions. [2018-11-18 15:17:52,236 INFO L608 BuchiCegarLoop]: Abstraction has 3980 states and 5597 transitions. [2018-11-18 15:17:52,236 INFO L442 BuchiCegarLoop]: ======== Iteration 13============ [2018-11-18 15:17:52,236 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3980 states and 5597 transitions. [2018-11-18 15:17:52,243 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3828 [2018-11-18 15:17:52,243 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:17:52,243 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:17:52,244 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:52,244 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:52,244 INFO L794 eck$LassoCheckResult]: Stem: 43352#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 43244#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 43118#L893 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 43071#L409 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 43072#L416 assume 1 == ~m_i~0;~m_st~0 := 0; 43316#L416-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43159#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43160#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43075#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43076#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 43125#L441-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 43126#L601 assume !(0 == ~M_E~0); 43435#L601-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 43441#L606-1 assume !(0 == ~T2_E~0); 43555#L611-1 assume !(0 == ~T3_E~0); 43554#L616-1 assume !(0 == ~T4_E~0); 43553#L621-1 assume !(0 == ~T5_E~0); 43283#L626-1 assume !(0 == ~E_M~0); 43284#L631-1 assume !(0 == ~E_1~0); 43552#L636-1 assume !(0 == ~E_2~0); 43551#L641-1 assume !(0 == ~E_3~0); 43505#L646-1 assume !(0 == ~E_4~0); 43114#L651-1 assume !(0 == ~E_5~0); 43115#L656-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 43447#L294 assume !(1 == ~m_pc~0); 43465#L294-2 is_master_triggered_~__retres1~0 := 0; 43489#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 43323#L306 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 43324#L745 assume !(0 != activate_threads_~tmp~1); 43504#L745-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 43046#L313 assume !(1 == ~t1_pc~0); 43047#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 43543#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 43542#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 43541#L753 assume !(0 != activate_threads_~tmp___0~0); 43540#L753-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 43539#L332 assume !(1 == ~t2_pc~0); 43537#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 43536#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 43535#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 43534#L761 assume !(0 != activate_threads_~tmp___1~0); 43533#L761-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 43531#L351 assume !(1 == ~t3_pc~0); 43529#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 43527#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 43525#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 43522#L769 assume !(0 != activate_threads_~tmp___2~0); 43521#L769-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 43520#L370 assume !(1 == ~t4_pc~0); 43519#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 43518#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 43476#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 43444#L777 assume !(0 != activate_threads_~tmp___3~0); 43445#L777-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 42936#L389 assume !(1 == ~t5_pc~0); 42900#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 42901#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 42934#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 42959#L785 assume !(0 != activate_threads_~tmp___4~0); 42960#L785-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42962#L669 assume !(1 == ~M_E~0); 43457#L669-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 43183#L674-1 assume !(1 == ~T2_E~0); 43184#L679-1 assume !(1 == ~T3_E~0); 43112#L684-1 assume !(1 == ~T4_E~0); 43113#L689-1 assume !(1 == ~T5_E~0); 43340#L694-1 assume !(1 == ~E_M~0); 43020#L699-1 assume !(1 == ~E_1~0); 43021#L704-1 assume !(1 == ~E_2~0); 42832#L709-1 assume !(1 == ~E_3~0); 42833#L714-1 assume !(1 == ~E_4~0); 42941#L719-1 assume !(1 == ~E_5~0); 42942#L724-1 assume { :end_inline_reset_delta_events } true; 43456#L930-3 [2018-11-18 15:17:52,244 INFO L796 eck$LassoCheckResult]: Loop: 43456#L930-3 assume true; 44327#L930-1 assume !false; 44287#L931 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 44278#L576 assume true; 44271#L496-1 assume !false; 44270#L497 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 44253#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 44240#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 44236#L487 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 44230#L501 assume !(0 != eval_~tmp~0); 44225#L591 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 44221#L409-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 44217#L601-3 assume !(0 == ~M_E~0); 44210#L601-5 assume !(0 == ~T1_E~0); 44211#L606-3 assume !(0 == ~T2_E~0); 45538#L611-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 45536#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 45534#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 45532#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 45530#L631-3 assume !(0 == ~E_1~0); 45527#L636-3 assume !(0 == ~E_2~0); 45525#L641-3 assume 0 == ~E_3~0;~E_3~0 := 1; 45523#L646-3 assume !(0 == ~E_4~0); 45521#L651-3 assume 0 == ~E_5~0;~E_5~0 := 1; 45519#L656-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 45517#L294-21 assume 1 == ~m_pc~0; 45515#L295-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 45511#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 45509#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 45507#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 45505#L745-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 45502#L313-21 assume !(1 == ~t1_pc~0); 45500#L313-23 is_transmit1_triggered_~__retres1~1 := 0; 45498#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 45496#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 45494#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 45492#L753-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 45490#L332-21 assume !(1 == ~t2_pc~0); 45487#L332-23 is_transmit2_triggered_~__retres1~2 := 0; 45486#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 45485#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 45484#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 45483#L761-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 45481#L351-21 assume !(1 == ~t3_pc~0); 45478#L351-23 is_transmit3_triggered_~__retres1~3 := 0; 45477#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 45475#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 45473#L769-21 assume !(0 != activate_threads_~tmp___2~0); 45470#L769-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 45468#L370-21 assume !(1 == ~t4_pc~0); 45466#L370-23 is_transmit4_triggered_~__retres1~4 := 0; 45463#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 45461#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 45459#L777-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 45457#L777-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 45455#L389-21 assume 1 == ~t5_pc~0; 45451#L390-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 45449#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 45447#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 45445#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 45443#L785-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45306#L669-3 assume !(1 == ~M_E~0); 43919#L669-5 assume !(1 == ~T1_E~0); 43920#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44692#L679-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 44690#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 44688#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44686#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 44684#L699-3 assume !(1 == ~E_1~0); 44682#L704-3 assume !(1 == ~E_2~0); 44680#L709-3 assume !(1 == ~E_3~0); 44678#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 44676#L719-3 assume 1 == ~E_5~0;~E_5~0 := 2; 44674#L724-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 43839#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 43837#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 44663#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 43727#L949 assume !(0 == start_simulation_~tmp~3); 43728#L949-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 44347#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 44343#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 44340#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 44338#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 44336#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 44334#L912 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 44332#L962 assume !(0 != start_simulation_~tmp___0~1); 43456#L930-3 [2018-11-18 15:17:52,245 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:52,245 INFO L82 PathProgramCache]: Analyzing trace with hash -1218959227, now seen corresponding path program 1 times [2018-11-18 15:17:52,245 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:52,245 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:52,245 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:52,246 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:17:52,246 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:52,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:52,267 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:17:52,267 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:17:52,267 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 15:17:52,267 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:17:52,267 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:52,267 INFO L82 PathProgramCache]: Analyzing trace with hash 1038768054, now seen corresponding path program 1 times [2018-11-18 15:17:52,267 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:52,268 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:52,268 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:52,268 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:52,268 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:52,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:52,296 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:17:52,296 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:17:52,296 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:17:52,296 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:17:52,297 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:17:52,297 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:17:52,297 INFO L87 Difference]: Start difference. First operand 3980 states and 5597 transitions. cyclomatic complexity: 1621 Second operand 3 states. [2018-11-18 15:17:52,317 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:17:52,317 INFO L93 Difference]: Finished difference Result 3468 states and 4854 transitions. [2018-11-18 15:17:52,318 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:17:52,318 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3468 states and 4854 transitions. [2018-11-18 15:17:52,325 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3372 [2018-11-18 15:17:52,332 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3468 states to 3468 states and 4854 transitions. [2018-11-18 15:17:52,332 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3468 [2018-11-18 15:17:52,334 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3468 [2018-11-18 15:17:52,334 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3468 states and 4854 transitions. [2018-11-18 15:17:52,337 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:17:52,337 INFO L705 BuchiCegarLoop]: Abstraction has 3468 states and 4854 transitions. [2018-11-18 15:17:52,339 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3468 states and 4854 transitions. [2018-11-18 15:17:52,359 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3468 to 3468. [2018-11-18 15:17:52,359 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3468 states. [2018-11-18 15:17:52,363 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3468 states to 3468 states and 4854 transitions. [2018-11-18 15:17:52,363 INFO L728 BuchiCegarLoop]: Abstraction has 3468 states and 4854 transitions. [2018-11-18 15:17:52,363 INFO L608 BuchiCegarLoop]: Abstraction has 3468 states and 4854 transitions. [2018-11-18 15:17:52,363 INFO L442 BuchiCegarLoop]: ======== Iteration 14============ [2018-11-18 15:17:52,364 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3468 states and 4854 transitions. [2018-11-18 15:17:52,370 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3372 [2018-11-18 15:17:52,370 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:17:52,370 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:17:52,371 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:52,371 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:52,372 INFO L794 eck$LassoCheckResult]: Stem: 50772#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 50670#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 50561#L893 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 50516#L409 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50517#L416 assume 1 == ~m_i~0;~m_st~0 := 0; 50736#L416-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 50600#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50601#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50520#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50521#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 50567#L441-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 50568#L601 assume !(0 == ~M_E~0); 50846#L601-2 assume !(0 == ~T1_E~0); 50571#L606-1 assume !(0 == ~T2_E~0); 50449#L611-1 assume !(0 == ~T3_E~0); 50450#L616-1 assume !(0 == ~T4_E~0); 50299#L621-1 assume !(0 == ~T5_E~0); 50300#L626-1 assume !(0 == ~E_M~0); 50399#L631-1 assume !(0 == ~E_1~0); 50400#L636-1 assume !(0 == ~E_2~0); 50626#L641-1 assume !(0 == ~E_3~0); 50627#L646-1 assume !(0 == ~E_4~0); 50557#L651-1 assume !(0 == ~E_5~0); 50558#L656-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 50854#L294 assume !(1 == ~m_pc~0); 50728#L294-2 is_master_triggered_~__retres1~0 := 0; 50727#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 50740#L306 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 50741#L745 assume !(0 != activate_threads_~tmp~1); 50899#L745-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 50497#L313 assume !(1 == ~t1_pc~0); 50498#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 50496#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 50440#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 50314#L753 assume !(0 != activate_threads_~tmp___0~0); 50315#L753-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 50318#L332 assume !(1 == ~t2_pc~0); 50529#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 50526#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 50527#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 50551#L761 assume !(0 != activate_threads_~tmp___1~0); 50552#L761-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 50553#L351 assume !(1 == ~t3_pc~0); 50677#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 50678#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 50700#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 50707#L769 assume !(0 != activate_threads_~tmp___2~0); 50708#L769-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 50710#L370 assume !(1 == ~t4_pc~0); 50840#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 50837#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 50838#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 50851#L777 assume !(0 != activate_threads_~tmp___3~0); 50852#L777-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 50389#L389 assume !(1 == ~t5_pc~0); 50355#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 50356#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 50384#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 50411#L785 assume !(0 != activate_threads_~tmp___4~0); 50412#L785-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50414#L669 assume !(1 == ~M_E~0); 50860#L669-2 assume !(1 == ~T1_E~0); 50624#L674-1 assume !(1 == ~T2_E~0); 50625#L679-1 assume !(1 == ~T3_E~0); 50555#L684-1 assume !(1 == ~T4_E~0); 50556#L689-1 assume !(1 == ~T5_E~0); 50760#L694-1 assume !(1 == ~E_M~0); 50472#L699-1 assume !(1 == ~E_1~0); 50473#L704-1 assume !(1 == ~E_2~0); 50287#L709-1 assume !(1 == ~E_3~0); 50288#L714-1 assume !(1 == ~E_4~0); 50394#L719-1 assume !(1 == ~E_5~0); 50395#L724-1 assume { :end_inline_reset_delta_events } true; 50329#L930-3 [2018-11-18 15:17:52,372 INFO L796 eck$LassoCheckResult]: Loop: 50329#L930-3 assume true; 50481#L930-1 assume !false; 50482#L931 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 50402#L576 assume true; 50403#L496-1 assume !false; 50546#L497 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 50547#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 50378#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 50548#L487 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 50460#L501 assume !(0 != eval_~tmp~0); 50461#L591 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 53623#L409-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 53622#L601-3 assume !(0 == ~M_E~0); 53621#L601-5 assume !(0 == ~T1_E~0); 53620#L606-3 assume !(0 == ~T2_E~0); 53619#L611-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 53618#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 53617#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 53616#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 53615#L631-3 assume !(0 == ~E_1~0); 53614#L636-3 assume !(0 == ~E_2~0); 53613#L641-3 assume 0 == ~E_3~0;~E_3~0 := 1; 53611#L646-3 assume !(0 == ~E_4~0); 53609#L651-3 assume 0 == ~E_5~0;~E_5~0 := 1; 53607#L656-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 53605#L294-21 assume 1 == ~m_pc~0; 53602#L295-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 53600#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 53598#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 53596#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 53594#L745-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 53592#L313-21 assume !(1 == ~t1_pc~0); 53590#L313-23 is_transmit1_triggered_~__retres1~1 := 0; 53588#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 53586#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 53584#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 53582#L753-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 53579#L332-21 assume !(1 == ~t2_pc~0); 53576#L332-23 is_transmit2_triggered_~__retres1~2 := 0; 53574#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 53572#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 53570#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 53568#L761-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 53567#L351-21 assume !(1 == ~t3_pc~0); 53565#L351-23 is_transmit3_triggered_~__retres1~3 := 0; 53563#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 53561#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 53560#L769-21 assume !(0 != activate_threads_~tmp___2~0); 53558#L769-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 50900#L370-21 assume !(1 == ~t4_pc~0); 50901#L370-23 is_transmit4_triggered_~__retres1~4 := 0; 50823#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 50824#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 50806#L777-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 50807#L777-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 50316#L389-21 assume !(1 == ~t5_pc~0); 50291#L389-23 is_transmit5_triggered_~__retres1~5 := 0; 50292#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 50339#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 50348#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 50349#L785-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50351#L669-3 assume !(1 == ~M_E~0); 50859#L669-5 assume !(1 == ~T1_E~0); 50629#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50630#L679-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50894#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 53505#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 53504#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 53503#L699-3 assume !(1 == ~E_1~0); 53501#L704-3 assume !(1 == ~E_2~0); 53499#L709-3 assume !(1 == ~E_3~0); 53498#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 52752#L719-3 assume 1 == ~E_5~0;~E_5~0 := 2; 52739#L724-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 52712#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 52707#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 52705#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 52703#L949 assume !(0 == start_simulation_~tmp~3); 50408#L949-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 50602#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 50386#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 50515#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 50559#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 50560#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 50711#L912 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 50328#L962 assume !(0 != start_simulation_~tmp___0~1); 50329#L930-3 [2018-11-18 15:17:52,372 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:52,372 INFO L82 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 2 times [2018-11-18 15:17:52,372 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:52,372 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:52,373 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:52,373 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:52,373 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:52,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:17:52,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:17:52,392 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:52,392 INFO L82 PathProgramCache]: Analyzing trace with hash -732702921, now seen corresponding path program 1 times [2018-11-18 15:17:52,392 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:52,392 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:52,393 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:52,393 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:17:52,393 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:52,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:52,416 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:17:52,416 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:17:52,416 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:17:52,416 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:17:52,416 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:17:52,416 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:17:52,417 INFO L87 Difference]: Start difference. First operand 3468 states and 4854 transitions. cyclomatic complexity: 1390 Second operand 3 states. [2018-11-18 15:17:52,469 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:17:52,469 INFO L93 Difference]: Finished difference Result 6059 states and 8409 transitions. [2018-11-18 15:17:52,470 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:17:52,470 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6059 states and 8409 transitions. [2018-11-18 15:17:52,484 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5894 [2018-11-18 15:17:52,495 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6059 states to 6059 states and 8409 transitions. [2018-11-18 15:17:52,495 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6059 [2018-11-18 15:17:52,498 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6059 [2018-11-18 15:17:52,498 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6059 states and 8409 transitions. [2018-11-18 15:17:52,502 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:17:52,502 INFO L705 BuchiCegarLoop]: Abstraction has 6059 states and 8409 transitions. [2018-11-18 15:17:52,505 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6059 states and 8409 transitions. [2018-11-18 15:17:52,533 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6059 to 6051. [2018-11-18 15:17:52,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6051 states. [2018-11-18 15:17:52,539 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6051 states to 6051 states and 8401 transitions. [2018-11-18 15:17:52,539 INFO L728 BuchiCegarLoop]: Abstraction has 6051 states and 8401 transitions. [2018-11-18 15:17:52,540 INFO L608 BuchiCegarLoop]: Abstraction has 6051 states and 8401 transitions. [2018-11-18 15:17:52,540 INFO L442 BuchiCegarLoop]: ======== Iteration 15============ [2018-11-18 15:17:52,540 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6051 states and 8401 transitions. [2018-11-18 15:17:52,551 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5886 [2018-11-18 15:17:52,551 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:17:52,551 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:17:52,552 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:52,552 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:52,553 INFO L794 eck$LassoCheckResult]: Stem: 60323#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 60223#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 60104#L893 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 60058#L409 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 60059#L416 assume 1 == ~m_i~0;~m_st~0 := 0; 60288#L416-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 60145#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 60146#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 60062#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 60063#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 60110#L441-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 60111#L601 assume !(0 == ~M_E~0); 60399#L601-2 assume !(0 == ~T1_E~0); 60115#L606-1 assume !(0 == ~T2_E~0); 59985#L611-1 assume !(0 == ~T3_E~0); 59986#L616-1 assume !(0 == ~T4_E~0); 59832#L621-1 assume !(0 == ~T5_E~0); 59833#L626-1 assume !(0 == ~E_M~0); 59934#L631-1 assume !(0 == ~E_1~0); 59935#L636-1 assume !(0 == ~E_2~0); 60171#L641-1 assume 0 == ~E_3~0;~E_3~0 := 1; 60172#L646-1 assume !(0 == ~E_4~0); 60514#L651-1 assume !(0 == ~E_5~0); 60513#L656-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 60512#L294 assume !(1 == ~m_pc~0); 60510#L294-2 is_master_triggered_~__retres1~0 := 0; 60509#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 60508#L306 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 60507#L745 assume !(0 != activate_threads_~tmp~1); 60506#L745-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 60505#L313 assume !(1 == ~t1_pc~0); 60041#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 60035#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 59978#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 59847#L753 assume !(0 != activate_threads_~tmp___0~0); 59848#L753-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 60495#L332 assume !(1 == ~t2_pc~0); 60492#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 60490#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 60488#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 60487#L761 assume !(0 != activate_threads_~tmp___1~0); 60485#L761-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 60253#L351 assume !(1 == ~t3_pc~0); 60229#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 60230#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 60252#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 60259#L769 assume !(0 != activate_threads_~tmp___2~0); 60260#L769-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 60262#L370 assume !(1 == ~t4_pc~0); 60393#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 60390#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 60391#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 60486#L777 assume !(0 != activate_threads_~tmp___3~0); 60484#L777-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 60483#L389 assume !(1 == ~t5_pc~0); 59889#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 59890#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 59918#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 59946#L785 assume !(0 != activate_threads_~tmp___4~0); 59947#L785-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59950#L669 assume !(1 == ~M_E~0); 60419#L669-2 assume !(1 == ~T1_E~0); 60169#L674-1 assume !(1 == ~T2_E~0); 60170#L679-1 assume !(1 == ~T3_E~0); 60098#L684-1 assume !(1 == ~T4_E~0); 60099#L689-1 assume !(1 == ~T5_E~0); 60312#L694-1 assume !(1 == ~E_M~0); 60007#L699-1 assume !(1 == ~E_1~0); 60008#L704-1 assume !(1 == ~E_2~0); 59820#L709-1 assume 1 == ~E_3~0;~E_3~0 := 2; 59821#L714-1 assume !(1 == ~E_4~0); 59929#L719-1 assume !(1 == ~E_5~0); 59930#L724-1 assume { :end_inline_reset_delta_events } true; 60418#L930-3 [2018-11-18 15:17:52,553 INFO L796 eck$LassoCheckResult]: Loop: 60418#L930-3 assume true; 64633#L930-1 assume !false; 64557#L931 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 64552#L576 assume true; 64550#L496-1 assume !false; 64548#L497 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 64543#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 64537#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 64534#L487 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 64531#L501 assume !(0 != eval_~tmp~0); 64532#L591 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 65534#L409-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 65532#L601-3 assume !(0 == ~M_E~0); 65530#L601-5 assume !(0 == ~T1_E~0); 65528#L606-3 assume !(0 == ~T2_E~0); 65526#L611-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 65525#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 65524#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 65523#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 65522#L631-3 assume !(0 == ~E_1~0); 65521#L636-3 assume !(0 == ~E_2~0); 65495#L641-3 assume 0 == ~E_3~0;~E_3~0 := 1; 65493#L646-3 assume !(0 == ~E_4~0); 65491#L651-3 assume 0 == ~E_5~0;~E_5~0 := 1; 65488#L656-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 65486#L294-21 assume 1 == ~m_pc~0; 65483#L295-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 65481#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 65479#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 65477#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 65474#L745-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 65472#L313-21 assume !(1 == ~t1_pc~0); 65470#L313-23 is_transmit1_triggered_~__retres1~1 := 0; 65468#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 65466#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 65464#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 65462#L753-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 65460#L332-21 assume !(1 == ~t2_pc~0); 65457#L332-23 is_transmit2_triggered_~__retres1~2 := 0; 65456#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 65454#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 65451#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 65449#L761-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 65447#L351-21 assume !(1 == ~t3_pc~0); 65445#L351-23 is_transmit3_triggered_~__retres1~3 := 0; 65443#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 65441#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 64964#L769-21 assume !(0 != activate_threads_~tmp___2~0); 64961#L769-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 64959#L370-21 assume !(1 == ~t4_pc~0); 64957#L370-23 is_transmit4_triggered_~__retres1~4 := 0; 64954#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 64952#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 64950#L777-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 64948#L777-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 64946#L389-21 assume 1 == ~t5_pc~0; 64941#L390-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 64939#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 64937#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 64935#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 64933#L785-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64931#L669-3 assume !(1 == ~M_E~0); 64927#L669-5 assume !(1 == ~T1_E~0); 64925#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 64923#L679-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 64922#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 64921#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 64920#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 64918#L699-3 assume !(1 == ~E_1~0); 64915#L704-3 assume !(1 == ~E_2~0); 64913#L709-3 assume 1 == ~E_3~0;~E_3~0 := 2; 64910#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 64908#L719-3 assume 1 == ~E_5~0;~E_5~0 := 2; 64906#L724-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 64897#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 64893#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 64890#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 64888#L949 assume !(0 == start_simulation_~tmp~3); 64885#L949-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 64692#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 64688#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 64686#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 64684#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 64665#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 64659#L912 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 64650#L962 assume !(0 != start_simulation_~tmp___0~1); 60418#L930-3 [2018-11-18 15:17:52,553 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:52,553 INFO L82 PathProgramCache]: Analyzing trace with hash 556820613, now seen corresponding path program 1 times [2018-11-18 15:17:52,553 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:52,553 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:52,554 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:52,554 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:52,554 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:52,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:52,582 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:17:52,582 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:17:52,582 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 15:17:52,582 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:17:52,582 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:52,583 INFO L82 PathProgramCache]: Analyzing trace with hash 2059836408, now seen corresponding path program 1 times [2018-11-18 15:17:52,583 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:52,583 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:52,583 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:52,583 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:52,583 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:52,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:52,605 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:17:52,606 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:17:52,606 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:17:52,606 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:17:52,606 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:17:52,606 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:17:52,606 INFO L87 Difference]: Start difference. First operand 6051 states and 8401 transitions. cyclomatic complexity: 2354 Second operand 3 states. [2018-11-18 15:17:52,630 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:17:52,631 INFO L93 Difference]: Finished difference Result 3333 states and 4595 transitions. [2018-11-18 15:17:52,632 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:17:52,632 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3333 states and 4595 transitions. [2018-11-18 15:17:52,638 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3240 [2018-11-18 15:17:52,642 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3333 states to 3333 states and 4595 transitions. [2018-11-18 15:17:52,642 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3333 [2018-11-18 15:17:52,644 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3333 [2018-11-18 15:17:52,644 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3333 states and 4595 transitions. [2018-11-18 15:17:52,646 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:17:52,646 INFO L705 BuchiCegarLoop]: Abstraction has 3333 states and 4595 transitions. [2018-11-18 15:17:52,648 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3333 states and 4595 transitions. [2018-11-18 15:17:52,663 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3333 to 3333. [2018-11-18 15:17:52,663 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3333 states. [2018-11-18 15:17:52,667 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3333 states to 3333 states and 4595 transitions. [2018-11-18 15:17:52,667 INFO L728 BuchiCegarLoop]: Abstraction has 3333 states and 4595 transitions. [2018-11-18 15:17:52,667 INFO L608 BuchiCegarLoop]: Abstraction has 3333 states and 4595 transitions. [2018-11-18 15:17:52,667 INFO L442 BuchiCegarLoop]: ======== Iteration 16============ [2018-11-18 15:17:52,667 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3333 states and 4595 transitions. [2018-11-18 15:17:52,673 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3240 [2018-11-18 15:17:52,673 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:17:52,673 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:17:52,674 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:52,674 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:52,674 INFO L794 eck$LassoCheckResult]: Stem: 69702#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 69605#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 69492#L893 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 69447#L409 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 69448#L416 assume 1 == ~m_i~0;~m_st~0 := 0; 69670#L416-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 69531#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 69532#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 69449#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 69450#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 69498#L441-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 69499#L601 assume !(0 == ~M_E~0); 69775#L601-2 assume !(0 == ~T1_E~0); 69502#L606-1 assume !(0 == ~T2_E~0); 69376#L611-1 assume !(0 == ~T3_E~0); 69377#L616-1 assume !(0 == ~T4_E~0); 69224#L621-1 assume !(0 == ~T5_E~0); 69225#L626-1 assume !(0 == ~E_M~0); 69327#L631-1 assume !(0 == ~E_1~0); 69328#L636-1 assume !(0 == ~E_2~0); 69555#L641-1 assume !(0 == ~E_3~0); 69556#L646-1 assume !(0 == ~E_4~0); 69488#L651-1 assume !(0 == ~E_5~0); 69489#L656-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 69785#L294 assume !(1 == ~m_pc~0); 69660#L294-2 is_master_triggered_~__retres1~0 := 0; 69659#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 69674#L306 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 69675#L745 assume !(0 != activate_threads_~tmp~1); 69836#L745-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 69428#L313 assume !(1 == ~t1_pc~0); 69429#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 69427#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 69368#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 69239#L753 assume !(0 != activate_threads_~tmp___0~0); 69240#L753-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 69244#L332 assume !(1 == ~t2_pc~0); 69460#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 69457#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 69458#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 69482#L761 assume !(0 != activate_threads_~tmp___1~0); 69483#L761-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 69484#L351 assume !(1 == ~t3_pc~0); 69611#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 69612#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 69634#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 69641#L769 assume !(0 != activate_threads_~tmp___2~0); 69642#L769-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 69644#L370 assume !(1 == ~t4_pc~0); 69768#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 69763#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 69764#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 69782#L777 assume !(0 != activate_threads_~tmp___3~0); 69783#L777-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 69316#L389 assume !(1 == ~t5_pc~0); 69280#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 69281#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 69312#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 69339#L785 assume !(0 != activate_threads_~tmp___4~0); 69340#L785-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69342#L669 assume !(1 == ~M_E~0); 69792#L669-2 assume !(1 == ~T1_E~0); 69553#L674-1 assume !(1 == ~T2_E~0); 69554#L679-1 assume !(1 == ~T3_E~0); 69486#L684-1 assume !(1 == ~T4_E~0); 69487#L689-1 assume !(1 == ~T5_E~0); 69694#L694-1 assume !(1 == ~E_M~0); 69400#L699-1 assume !(1 == ~E_1~0); 69401#L704-1 assume !(1 == ~E_2~0); 69213#L709-1 assume !(1 == ~E_3~0); 69214#L714-1 assume !(1 == ~E_4~0); 69320#L719-1 assume !(1 == ~E_5~0); 69321#L724-1 assume { :end_inline_reset_delta_events } true; 69791#L930-3 [2018-11-18 15:17:52,674 INFO L796 eck$LassoCheckResult]: Loop: 69791#L930-3 assume true; 70976#L930-1 assume !false; 70969#L931 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 70960#L576 assume true; 70955#L496-1 assume !false; 70951#L497 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 70867#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 70855#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 70848#L487 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 70841#L501 assume !(0 != eval_~tmp~0); 70842#L591 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 71326#L409-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 71316#L601-3 assume !(0 == ~M_E~0); 71312#L601-5 assume !(0 == ~T1_E~0); 71307#L606-3 assume !(0 == ~T2_E~0); 71306#L611-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 71303#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 71294#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 71289#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 71284#L631-3 assume !(0 == ~E_1~0); 71279#L636-3 assume !(0 == ~E_2~0); 71275#L641-3 assume !(0 == ~E_3~0); 71273#L646-3 assume !(0 == ~E_4~0); 71270#L651-3 assume 0 == ~E_5~0;~E_5~0 := 1; 71258#L656-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 71210#L294-21 assume !(1 == ~m_pc~0); 71207#L294-23 is_master_triggered_~__retres1~0 := 0; 71204#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 71202#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 71200#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 71198#L745-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 71196#L313-21 assume !(1 == ~t1_pc~0); 71194#L313-23 is_transmit1_triggered_~__retres1~1 := 0; 71192#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 71190#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 71188#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 71186#L753-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 71183#L332-21 assume !(1 == ~t2_pc~0); 71180#L332-23 is_transmit2_triggered_~__retres1~2 := 0; 71178#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 71176#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 71174#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 71172#L761-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 71169#L351-21 assume !(1 == ~t3_pc~0); 71166#L351-23 is_transmit3_triggered_~__retres1~3 := 0; 71164#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 71162#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 71160#L769-21 assume !(0 != activate_threads_~tmp___2~0); 71158#L769-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 71156#L370-21 assume !(1 == ~t4_pc~0); 71154#L370-23 is_transmit4_triggered_~__retres1~4 := 0; 71152#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 71150#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 71148#L777-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 71146#L777-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 71144#L389-21 assume !(1 == ~t5_pc~0); 71141#L389-23 is_transmit5_triggered_~__retres1~5 := 0; 71138#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 71136#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 71134#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 71132#L785-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 71131#L669-3 assume !(1 == ~M_E~0); 71129#L669-5 assume !(1 == ~T1_E~0); 71127#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 71125#L679-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 71123#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 71121#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 71119#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 71117#L699-3 assume !(1 == ~E_1~0); 71115#L704-3 assume !(1 == ~E_2~0); 71113#L709-3 assume !(1 == ~E_3~0); 71111#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 71109#L719-3 assume 1 == ~E_5~0;~E_5~0 := 2; 71108#L724-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 71101#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 71097#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 71095#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 71093#L949 assume !(0 == start_simulation_~tmp~3); 71090#L949-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 71037#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 71028#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 71021#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 71014#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 71007#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 71000#L912 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 70999#L962 assume !(0 != start_simulation_~tmp___0~1); 69791#L930-3 [2018-11-18 15:17:52,674 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:52,675 INFO L82 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 3 times [2018-11-18 15:17:52,675 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:52,675 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:52,675 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:52,675 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:52,675 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:52,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:17:52,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:17:52,694 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:52,694 INFO L82 PathProgramCache]: Analyzing trace with hash -1390350598, now seen corresponding path program 1 times [2018-11-18 15:17:52,694 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:52,694 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:52,695 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:52,695 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:17:52,695 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:52,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:52,732 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:17:52,732 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:17:52,732 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:17:52,732 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:17:52,732 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:17:52,732 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:17:52,733 INFO L87 Difference]: Start difference. First operand 3333 states and 4595 transitions. cyclomatic complexity: 1266 Second operand 5 states. [2018-11-18 15:17:52,791 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:17:52,791 INFO L93 Difference]: Finished difference Result 5997 states and 8171 transitions. [2018-11-18 15:17:52,793 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-18 15:17:52,793 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5997 states and 8171 transitions. [2018-11-18 15:17:52,804 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5888 [2018-11-18 15:17:52,813 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5997 states to 5997 states and 8171 transitions. [2018-11-18 15:17:52,813 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5997 [2018-11-18 15:17:52,816 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5997 [2018-11-18 15:17:52,816 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5997 states and 8171 transitions. [2018-11-18 15:17:52,819 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:17:52,819 INFO L705 BuchiCegarLoop]: Abstraction has 5997 states and 8171 transitions. [2018-11-18 15:17:52,821 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5997 states and 8171 transitions. [2018-11-18 15:17:52,842 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5997 to 3357. [2018-11-18 15:17:52,842 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3357 states. [2018-11-18 15:17:52,846 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3357 states to 3357 states and 4619 transitions. [2018-11-18 15:17:52,846 INFO L728 BuchiCegarLoop]: Abstraction has 3357 states and 4619 transitions. [2018-11-18 15:17:52,846 INFO L608 BuchiCegarLoop]: Abstraction has 3357 states and 4619 transitions. [2018-11-18 15:17:52,846 INFO L442 BuchiCegarLoop]: ======== Iteration 17============ [2018-11-18 15:17:52,846 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3357 states and 4619 transitions. [2018-11-18 15:17:52,851 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3264 [2018-11-18 15:17:52,851 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:17:52,852 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:17:52,852 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:52,852 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:52,853 INFO L794 eck$LassoCheckResult]: Stem: 79063#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 78962#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 78839#L893 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 78793#L409 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 78794#L416 assume 1 == ~m_i~0;~m_st~0 := 0; 79029#L416-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 78883#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 78884#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 78797#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 78798#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 78846#L441-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 78847#L601 assume !(0 == ~M_E~0); 79137#L601-2 assume !(0 == ~T1_E~0); 78850#L606-1 assume !(0 == ~T2_E~0); 78723#L611-1 assume !(0 == ~T3_E~0); 78724#L616-1 assume !(0 == ~T4_E~0); 78571#L621-1 assume !(0 == ~T5_E~0); 78572#L626-1 assume !(0 == ~E_M~0); 78673#L631-1 assume !(0 == ~E_1~0); 78674#L636-1 assume !(0 == ~E_2~0); 78907#L641-1 assume !(0 == ~E_3~0); 78908#L646-1 assume !(0 == ~E_4~0); 78835#L651-1 assume !(0 == ~E_5~0); 78836#L656-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 79149#L294 assume !(1 == ~m_pc~0); 79021#L294-2 is_master_triggered_~__retres1~0 := 0; 79020#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 79036#L306 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 79037#L745 assume !(0 != activate_threads_~tmp~1); 79217#L745-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 78774#L313 assume !(1 == ~t1_pc~0); 78775#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 78773#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 78717#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 78586#L753 assume !(0 != activate_threads_~tmp___0~0); 78587#L753-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 78590#L332 assume !(1 == ~t2_pc~0); 78806#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 78803#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 78804#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 78829#L761 assume !(0 != activate_threads_~tmp___1~0); 78830#L761-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 78831#L351 assume !(1 == ~t3_pc~0); 78968#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 78969#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 78991#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 79001#L769 assume !(0 != activate_threads_~tmp___2~0); 79002#L769-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 79003#L370 assume !(1 == ~t4_pc~0); 79129#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 79126#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 79127#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 79146#L777 assume !(0 != activate_threads_~tmp___3~0); 79147#L777-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 78663#L389 assume !(1 == ~t5_pc~0); 78628#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 78629#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 78661#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 78685#L785 assume !(0 != activate_threads_~tmp___4~0); 78686#L785-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 78688#L669 assume !(1 == ~M_E~0); 79166#L669-2 assume !(1 == ~T1_E~0); 78905#L674-1 assume !(1 == ~T2_E~0); 78906#L679-1 assume !(1 == ~T3_E~0); 78833#L684-1 assume !(1 == ~T4_E~0); 78834#L689-1 assume !(1 == ~T5_E~0); 79053#L694-1 assume !(1 == ~E_M~0); 78742#L699-1 assume !(1 == ~E_1~0); 78743#L704-1 assume !(1 == ~E_2~0); 78559#L709-1 assume !(1 == ~E_3~0); 78560#L714-1 assume !(1 == ~E_4~0); 78668#L719-1 assume !(1 == ~E_5~0); 78669#L724-1 assume { :end_inline_reset_delta_events } true; 79165#L930-3 [2018-11-18 15:17:52,853 INFO L796 eck$LassoCheckResult]: Loop: 79165#L930-3 assume true; 81668#L930-1 assume !false; 81667#L931 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 81663#L576 assume true; 81519#L496-1 assume !false; 81443#L497 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 81440#L454 assume !(0 == ~m_st~0); 81441#L458 assume !(0 == ~t1_st~0); 81437#L462 assume !(0 == ~t2_st~0); 81438#L466 assume !(0 == ~t3_st~0); 81439#L470 assume !(0 == ~t4_st~0); 81442#L474 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 78825#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 78826#L487 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 80229#L501 assume !(0 != eval_~tmp~0); 81432#L591 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 81479#L409-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 79144#L601-3 assume !(0 == ~M_E~0); 79119#L601-5 assume !(0 == ~T1_E~0); 79120#L606-3 assume !(0 == ~T2_E~0); 78732#L611-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 78733#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 79080#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 78999#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 79000#L631-3 assume !(0 == ~E_1~0); 79157#L636-3 assume !(0 == ~E_2~0); 79158#L641-3 assume !(0 == ~E_3~0); 79214#L646-3 assume !(0 == ~E_4~0); 79215#L651-3 assume 0 == ~E_5~0;~E_5~0 := 1; 79142#L656-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 79143#L294-21 assume 1 == ~m_pc~0; 79030#L295-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 79031#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 79022#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 79023#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 79172#L745-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 79173#L313-21 assume !(1 == ~t1_pc~0); 81608#L313-23 is_transmit1_triggered_~__retres1~1 := 0; 80113#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 80114#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 79381#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 79382#L753-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 79336#L332-21 assume !(1 == ~t2_pc~0); 79335#L332-23 is_transmit2_triggered_~__retres1~2 := 0; 78939#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 78940#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 78918#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 78919#L761-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 79081#L351-21 assume !(1 == ~t3_pc~0); 79059#L351-23 is_transmit3_triggered_~__retres1~3 := 0; 78949#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 78950#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 78956#L769-21 assume !(0 != activate_threads_~tmp___2~0); 78957#L769-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 79218#L370-21 assume !(1 == ~t4_pc~0); 79219#L370-23 is_transmit4_triggered_~__retres1~4 := 0; 79112#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 79113#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 79093#L777-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 79094#L777-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 81526#L389-21 assume !(1 == ~t5_pc~0); 81525#L389-23 is_transmit5_triggered_~__retres1~5 := 0; 81523#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 81522#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 81521#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 81520#L785-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 79168#L669-3 assume !(1 == ~M_E~0); 79169#L669-5 assume !(1 == ~T1_E~0); 78911#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 78912#L679-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 78816#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 78817#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 78848#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 78849#L699-3 assume !(1 == ~E_1~0); 79078#L704-3 assume !(1 == ~E_2~0); 79079#L709-3 assume !(1 == ~E_3~0); 78995#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 78996#L719-3 assume 1 == ~E_5~0;~E_5~0 := 2; 79167#L724-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 78901#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 78655#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 78828#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 78899#L949 assume !(0 == start_simulation_~tmp~3); 78682#L949-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 78914#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 81682#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 81680#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 81678#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 81674#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 81672#L912 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 81670#L962 assume !(0 != start_simulation_~tmp___0~1); 79165#L930-3 [2018-11-18 15:17:52,853 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:52,853 INFO L82 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 4 times [2018-11-18 15:17:52,853 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:52,853 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:52,854 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:52,854 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:52,854 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:52,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:17:52,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:17:52,872 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:52,872 INFO L82 PathProgramCache]: Analyzing trace with hash 1946885686, now seen corresponding path program 1 times [2018-11-18 15:17:52,872 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:52,872 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:52,873 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:52,873 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:17:52,873 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:52,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:52,921 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:17:52,921 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:17:52,922 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:17:52,922 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:17:52,922 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:17:52,922 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:17:52,922 INFO L87 Difference]: Start difference. First operand 3357 states and 4619 transitions. cyclomatic complexity: 1266 Second operand 5 states. [2018-11-18 15:17:53,075 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:17:53,076 INFO L93 Difference]: Finished difference Result 4479 states and 6170 transitions. [2018-11-18 15:17:53,077 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 15:17:53,077 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4479 states and 6170 transitions. [2018-11-18 15:17:53,090 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4378 [2018-11-18 15:17:53,101 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4479 states to 4479 states and 6170 transitions. [2018-11-18 15:17:53,102 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4479 [2018-11-18 15:17:53,104 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4479 [2018-11-18 15:17:53,104 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4479 states and 6170 transitions. [2018-11-18 15:17:53,107 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:17:53,107 INFO L705 BuchiCegarLoop]: Abstraction has 4479 states and 6170 transitions. [2018-11-18 15:17:53,110 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4479 states and 6170 transitions. [2018-11-18 15:17:53,143 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4479 to 3369. [2018-11-18 15:17:53,143 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3369 states. [2018-11-18 15:17:53,149 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3369 states to 3369 states and 4582 transitions. [2018-11-18 15:17:53,149 INFO L728 BuchiCegarLoop]: Abstraction has 3369 states and 4582 transitions. [2018-11-18 15:17:53,149 INFO L608 BuchiCegarLoop]: Abstraction has 3369 states and 4582 transitions. [2018-11-18 15:17:53,150 INFO L442 BuchiCegarLoop]: ======== Iteration 18============ [2018-11-18 15:17:53,150 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3369 states and 4582 transitions. [2018-11-18 15:17:53,158 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3276 [2018-11-18 15:17:53,158 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:17:53,158 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:17:53,159 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:53,159 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:53,160 INFO L794 eck$LassoCheckResult]: Stem: 87004#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 86892#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 86744#L893 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 86695#L409 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 86696#L416 assume 1 == ~m_i~0;~m_st~0 := 0; 86966#L416-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 86786#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 86787#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 86697#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 86698#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 86750#L441-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 86751#L601 assume !(0 == ~M_E~0); 87103#L601-2 assume !(0 == ~T1_E~0); 86754#L606-1 assume !(0 == ~T2_E~0); 86588#L611-1 assume !(0 == ~T3_E~0); 86589#L616-1 assume !(0 == ~T4_E~0); 86420#L621-1 assume !(0 == ~T5_E~0); 86421#L626-1 assume !(0 == ~E_M~0); 86535#L631-1 assume !(0 == ~E_1~0); 86536#L636-1 assume !(0 == ~E_2~0); 86822#L641-1 assume !(0 == ~E_3~0); 86823#L646-1 assume !(0 == ~E_4~0); 86740#L651-1 assume !(0 == ~E_5~0); 86741#L656-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 87115#L294 assume !(1 == ~m_pc~0); 86956#L294-2 is_master_triggered_~__retres1~0 := 0; 86955#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 86970#L306 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 86971#L745 assume !(0 != activate_threads_~tmp~1); 87196#L745-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 86647#L313 assume !(1 == ~t1_pc~0); 86648#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 86645#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 86581#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 86435#L753 assume !(0 != activate_threads_~tmp___0~0); 86436#L753-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 86442#L332 assume !(1 == ~t2_pc~0); 86708#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 86705#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 86706#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 86734#L761 assume !(0 != activate_threads_~tmp___1~0); 86735#L761-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 86736#L351 assume !(1 == ~t3_pc~0); 86899#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 86900#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 86924#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 86933#L769 assume !(0 != activate_threads_~tmp___2~0); 86934#L769-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 86938#L370 assume !(1 == ~t4_pc~0); 87090#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 87085#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 87086#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 87111#L777 assume !(0 != activate_threads_~tmp___3~0); 87112#L777-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 86523#L389 assume !(1 == ~t5_pc~0); 86481#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 86482#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 86519#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 86549#L785 assume !(0 != activate_threads_~tmp___4~0); 86550#L785-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 86553#L669 assume !(1 == ~M_E~0); 87134#L669-2 assume !(1 == ~T1_E~0); 86820#L674-1 assume !(1 == ~T2_E~0); 86821#L679-1 assume !(1 == ~T3_E~0); 86738#L684-1 assume !(1 == ~T4_E~0); 86739#L689-1 assume !(1 == ~T5_E~0); 86990#L694-1 assume !(1 == ~E_M~0); 86612#L699-1 assume !(1 == ~E_1~0); 86613#L704-1 assume !(1 == ~E_2~0); 86409#L709-1 assume !(1 == ~E_3~0); 86410#L714-1 assume !(1 == ~E_4~0); 86528#L719-1 assume !(1 == ~E_5~0); 86529#L724-1 assume { :end_inline_reset_delta_events } true; 87133#L930-3 [2018-11-18 15:17:53,160 INFO L796 eck$LassoCheckResult]: Loop: 87133#L930-3 assume true; 87667#L930-1 assume !false; 87659#L931 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 87650#L576 assume true; 87648#L496-1 assume !false; 87646#L497 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 87644#L454 assume !(0 == ~m_st~0); 87642#L458 assume !(0 == ~t1_st~0); 87640#L462 assume !(0 == ~t2_st~0); 87638#L466 assume !(0 == ~t3_st~0); 87636#L470 assume !(0 == ~t4_st~0); 87633#L474 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 87630#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 87628#L487 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 87625#L501 assume !(0 != eval_~tmp~0); 87622#L591 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 87620#L409-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 87618#L601-3 assume !(0 == ~M_E~0); 87616#L601-5 assume !(0 == ~T1_E~0); 87614#L606-3 assume !(0 == ~T2_E~0); 87612#L611-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 87610#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 87608#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 87606#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 87604#L631-3 assume !(0 == ~E_1~0); 87602#L636-3 assume !(0 == ~E_2~0); 87600#L641-3 assume !(0 == ~E_3~0); 87598#L646-3 assume !(0 == ~E_4~0); 87596#L651-3 assume 0 == ~E_5~0;~E_5~0 := 1; 87594#L656-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 87592#L294-21 assume 1 == ~m_pc~0; 87589#L295-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 87586#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 87584#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 87582#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 87580#L745-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 87578#L313-21 assume !(1 == ~t1_pc~0); 87576#L313-23 is_transmit1_triggered_~__retres1~1 := 0; 87574#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 87572#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 87570#L753-21 assume !(0 != activate_threads_~tmp___0~0); 87568#L753-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 87566#L332-21 assume !(1 == ~t2_pc~0); 87562#L332-23 is_transmit2_triggered_~__retres1~2 := 0; 87560#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 87558#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 87556#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 87554#L761-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 87552#L351-21 assume !(1 == ~t3_pc~0); 87548#L351-23 is_transmit3_triggered_~__retres1~3 := 0; 87546#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 87544#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 87542#L769-21 assume !(0 != activate_threads_~tmp___2~0); 87540#L769-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 87538#L370-21 assume !(1 == ~t4_pc~0); 87536#L370-23 is_transmit4_triggered_~__retres1~4 := 0; 87534#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 87532#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 87530#L777-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 87528#L777-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 87526#L389-21 assume 1 == ~t5_pc~0; 87523#L390-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 87520#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 87518#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 87516#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 87514#L785-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 87512#L669-3 assume !(1 == ~M_E~0); 87511#L669-5 assume !(1 == ~T1_E~0); 87895#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 87894#L679-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 87417#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 87413#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 87409#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 87405#L699-3 assume !(1 == ~E_1~0); 87401#L704-3 assume !(1 == ~E_2~0); 87397#L709-3 assume !(1 == ~E_3~0); 87391#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 87389#L719-3 assume 1 == ~E_5~0;~E_5~0 := 2; 87384#L724-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 87290#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 87288#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 87278#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 87279#L949 assume !(0 == start_simulation_~tmp~3); 87861#L949-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 87710#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 87706#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 87704#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 87700#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 87684#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 87683#L912 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 87682#L962 assume !(0 != start_simulation_~tmp___0~1); 87133#L930-3 [2018-11-18 15:17:53,160 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:53,160 INFO L82 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 5 times [2018-11-18 15:17:53,160 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:53,160 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:53,161 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:53,161 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:53,161 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:53,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:17:53,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:17:53,182 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:53,182 INFO L82 PathProgramCache]: Analyzing trace with hash 1689770551, now seen corresponding path program 1 times [2018-11-18 15:17:53,182 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:53,182 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:53,183 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:53,183 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:17:53,183 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:53,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:53,245 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:17:53,246 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:17:53,246 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:17:53,246 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:17:53,246 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:17:53,246 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:17:53,246 INFO L87 Difference]: Start difference. First operand 3369 states and 4582 transitions. cyclomatic complexity: 1217 Second operand 5 states. [2018-11-18 15:17:53,385 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:17:53,386 INFO L93 Difference]: Finished difference Result 4621 states and 6281 transitions. [2018-11-18 15:17:53,387 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 15:17:53,388 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4621 states and 6281 transitions. [2018-11-18 15:17:53,400 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4520 [2018-11-18 15:17:53,409 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4621 states to 4621 states and 6281 transitions. [2018-11-18 15:17:53,409 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4621 [2018-11-18 15:17:53,411 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4621 [2018-11-18 15:17:53,412 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4621 states and 6281 transitions. [2018-11-18 15:17:53,414 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:17:53,414 INFO L705 BuchiCegarLoop]: Abstraction has 4621 states and 6281 transitions. [2018-11-18 15:17:53,417 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4621 states and 6281 transitions. [2018-11-18 15:17:53,440 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4621 to 3381. [2018-11-18 15:17:53,441 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3381 states. [2018-11-18 15:17:53,445 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3381 states to 3381 states and 4545 transitions. [2018-11-18 15:17:53,445 INFO L728 BuchiCegarLoop]: Abstraction has 3381 states and 4545 transitions. [2018-11-18 15:17:53,446 INFO L608 BuchiCegarLoop]: Abstraction has 3381 states and 4545 transitions. [2018-11-18 15:17:53,446 INFO L442 BuchiCegarLoop]: ======== Iteration 19============ [2018-11-18 15:17:53,446 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3381 states and 4545 transitions. [2018-11-18 15:17:53,453 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3288 [2018-11-18 15:17:53,453 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:17:53,453 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:17:53,454 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:53,454 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:53,454 INFO L794 eck$LassoCheckResult]: Stem: 94929#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 94828#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 94713#L893 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 94667#L409 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 94668#L416 assume 1 == ~m_i~0;~m_st~0 := 0; 94895#L416-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 94755#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 94756#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 94671#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 94672#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 94720#L441-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 94721#L601 assume !(0 == ~M_E~0); 95004#L601-2 assume !(0 == ~T1_E~0); 94723#L606-1 assume !(0 == ~T2_E~0); 94586#L611-1 assume !(0 == ~T3_E~0); 94587#L616-1 assume !(0 == ~T4_E~0); 94426#L621-1 assume !(0 == ~T5_E~0); 94427#L626-1 assume !(0 == ~E_M~0); 94534#L631-1 assume !(0 == ~E_1~0); 94535#L636-1 assume !(0 == ~E_2~0); 94778#L641-1 assume !(0 == ~E_3~0); 94779#L646-1 assume !(0 == ~E_4~0); 94709#L651-1 assume !(0 == ~E_5~0); 94710#L656-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 95012#L294 assume !(1 == ~m_pc~0); 94887#L294-2 is_master_triggered_~__retres1~0 := 0; 94886#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 94902#L306 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 94903#L745 assume !(0 != activate_threads_~tmp~1); 95063#L745-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 94638#L313 assume !(1 == ~t1_pc~0); 94639#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 94637#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 94579#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 94442#L753 assume !(0 != activate_threads_~tmp___0~0); 94443#L753-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 94446#L332 assume !(1 == ~t2_pc~0); 94680#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 94677#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 94678#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 94703#L761 assume !(0 != activate_threads_~tmp___1~0); 94704#L761-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 94705#L351 assume !(1 == ~t3_pc~0); 94834#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 94835#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 94858#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 94865#L769 assume !(0 != activate_threads_~tmp___2~0); 94866#L769-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 94869#L370 assume !(1 == ~t4_pc~0); 94995#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 94992#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 94993#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 95009#L777 assume !(0 != activate_threads_~tmp___3~0); 95010#L777-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 94524#L389 assume !(1 == ~t5_pc~0); 94485#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 94486#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 94521#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 94546#L785 assume !(0 != activate_threads_~tmp___4~0); 94547#L785-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 94549#L669 assume !(1 == ~M_E~0); 95019#L669-2 assume !(1 == ~T1_E~0); 94776#L674-1 assume !(1 == ~T2_E~0); 94777#L679-1 assume !(1 == ~T3_E~0); 94707#L684-1 assume !(1 == ~T4_E~0); 94708#L689-1 assume !(1 == ~T5_E~0); 94919#L694-1 assume !(1 == ~E_M~0); 94608#L699-1 assume !(1 == ~E_1~0); 94609#L704-1 assume !(1 == ~E_2~0); 94413#L709-1 assume !(1 == ~E_3~0); 94414#L714-1 assume !(1 == ~E_4~0); 94529#L719-1 assume !(1 == ~E_5~0); 94530#L724-1 assume { :end_inline_reset_delta_events } true; 95018#L930-3 [2018-11-18 15:17:53,454 INFO L796 eck$LassoCheckResult]: Loop: 95018#L930-3 assume true; 96514#L930-1 assume !false; 96511#L931 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 96506#L576 assume true; 96504#L496-1 assume !false; 96502#L497 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 96500#L454 assume !(0 == ~m_st~0); 96498#L458 assume !(0 == ~t1_st~0); 96496#L462 assume !(0 == ~t2_st~0); 96494#L466 assume !(0 == ~t3_st~0); 96492#L470 assume !(0 == ~t4_st~0); 96489#L474 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 96487#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 96484#L487 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 96482#L501 assume !(0 != eval_~tmp~0); 96480#L591 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 96478#L409-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 96476#L601-3 assume !(0 == ~M_E~0); 96475#L601-5 assume !(0 == ~T1_E~0); 96474#L606-3 assume !(0 == ~T2_E~0); 96473#L611-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 96472#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 96471#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 96470#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 96469#L631-3 assume !(0 == ~E_1~0); 96468#L636-3 assume !(0 == ~E_2~0); 96467#L641-3 assume !(0 == ~E_3~0); 96466#L646-3 assume !(0 == ~E_4~0); 96465#L651-3 assume 0 == ~E_5~0;~E_5~0 := 1; 96463#L656-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 96461#L294-21 assume 1 == ~m_pc~0; 96457#L295-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 96455#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 96453#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 96451#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 96449#L745-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 96446#L313-21 assume !(1 == ~t1_pc~0); 96444#L313-23 is_transmit1_triggered_~__retres1~1 := 0; 96442#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 96440#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 96438#L753-21 assume !(0 != activate_threads_~tmp___0~0); 96436#L753-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 96433#L332-21 assume !(1 == ~t2_pc~0); 96430#L332-23 is_transmit2_triggered_~__retres1~2 := 0; 96428#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 96426#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 96424#L761-21 assume !(0 != activate_threads_~tmp___1~0); 96422#L761-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 96419#L351-21 assume !(1 == ~t3_pc~0); 96416#L351-23 is_transmit3_triggered_~__retres1~3 := 0; 96414#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 96412#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 96410#L769-21 assume !(0 != activate_threads_~tmp___2~0); 96408#L769-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 96406#L370-21 assume !(1 == ~t4_pc~0); 96403#L370-23 is_transmit4_triggered_~__retres1~4 := 0; 96401#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 96399#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 96397#L777-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 96395#L777-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 96393#L389-21 assume 1 == ~t5_pc~0; 96389#L390-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 96387#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 96385#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 96383#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 96381#L785-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 96379#L669-3 assume !(1 == ~M_E~0); 96378#L669-5 assume !(1 == ~T1_E~0); 96688#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 96687#L679-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 96686#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 96685#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 96684#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 96683#L699-3 assume !(1 == ~E_1~0); 96682#L704-3 assume !(1 == ~E_2~0); 96681#L709-3 assume !(1 == ~E_3~0); 96680#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 96679#L719-3 assume 1 == ~E_5~0;~E_5~0 := 2; 96678#L724-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 96553#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 96549#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 96547#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 96545#L949 assume !(0 == start_simulation_~tmp~3); 96542#L949-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 96533#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 96529#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 96526#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 96524#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 96522#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 96520#L912 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 96518#L962 assume !(0 != start_simulation_~tmp___0~1); 95018#L930-3 [2018-11-18 15:17:53,454 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:53,455 INFO L82 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 6 times [2018-11-18 15:17:53,455 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:53,455 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:53,455 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:53,455 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:53,455 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:53,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:17:53,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:17:53,472 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:53,473 INFO L82 PathProgramCache]: Analyzing trace with hash -1711710407, now seen corresponding path program 1 times [2018-11-18 15:17:53,473 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:53,473 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:53,473 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:53,473 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:17:53,473 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:53,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:53,534 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:17:53,535 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:17:53,535 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:17:53,535 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:17:53,535 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:17:53,535 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:17:53,535 INFO L87 Difference]: Start difference. First operand 3381 states and 4545 transitions. cyclomatic complexity: 1168 Second operand 5 states. [2018-11-18 15:17:53,683 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:17:53,684 INFO L93 Difference]: Finished difference Result 5852 states and 7894 transitions. [2018-11-18 15:17:53,685 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 15:17:53,685 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5852 states and 7894 transitions. [2018-11-18 15:17:53,700 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5751 [2018-11-18 15:17:53,712 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5852 states to 5852 states and 7894 transitions. [2018-11-18 15:17:53,712 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5852 [2018-11-18 15:17:53,715 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5852 [2018-11-18 15:17:53,715 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5852 states and 7894 transitions. [2018-11-18 15:17:53,719 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:17:53,719 INFO L705 BuchiCegarLoop]: Abstraction has 5852 states and 7894 transitions. [2018-11-18 15:17:53,722 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5852 states and 7894 transitions. [2018-11-18 15:17:53,748 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5852 to 3465. [2018-11-18 15:17:53,748 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3465 states. [2018-11-18 15:17:53,753 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3465 states to 3465 states and 4604 transitions. [2018-11-18 15:17:53,753 INFO L728 BuchiCegarLoop]: Abstraction has 3465 states and 4604 transitions. [2018-11-18 15:17:53,753 INFO L608 BuchiCegarLoop]: Abstraction has 3465 states and 4604 transitions. [2018-11-18 15:17:53,753 INFO L442 BuchiCegarLoop]: ======== Iteration 20============ [2018-11-18 15:17:53,753 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3465 states and 4604 transitions. [2018-11-18 15:17:53,760 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3372 [2018-11-18 15:17:53,760 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:17:53,760 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:17:53,761 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:53,761 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:53,761 INFO L794 eck$LassoCheckResult]: Stem: 104214#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 104110#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 103964#L893 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 103916#L409 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 103917#L416 assume 1 == ~m_i~0;~m_st~0 := 0; 104179#L416-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 104009#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 104010#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 103920#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 103921#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 103971#L441-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 103972#L601 assume !(0 == ~M_E~0); 104313#L601-2 assume !(0 == ~T1_E~0); 103974#L606-1 assume !(0 == ~T2_E~0); 103822#L611-1 assume !(0 == ~T3_E~0); 103823#L616-1 assume !(0 == ~T4_E~0); 103672#L621-1 assume !(0 == ~T5_E~0); 103673#L626-1 assume !(0 == ~E_M~0); 103773#L631-1 assume !(0 == ~E_1~0); 103774#L636-1 assume !(0 == ~E_2~0); 104039#L641-1 assume !(0 == ~E_3~0); 104040#L646-1 assume !(0 == ~E_4~0); 103960#L651-1 assume !(0 == ~E_5~0); 103961#L656-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 104321#L294 assume !(1 == ~m_pc~0); 104171#L294-2 is_master_triggered_~__retres1~0 := 0; 104170#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 104186#L306 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 104187#L745 assume !(0 != activate_threads_~tmp~1); 104433#L745-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 103882#L313 assume !(1 == ~t1_pc~0); 103883#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 103881#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 103816#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 103688#L753 assume !(0 != activate_threads_~tmp___0~0); 103689#L753-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 103692#L332 assume !(1 == ~t2_pc~0); 103929#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 103926#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 103927#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 103954#L761 assume !(0 != activate_threads_~tmp___1~0); 103955#L761-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 103956#L351 assume !(1 == ~t3_pc~0); 104116#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 104117#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 104143#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 104151#L769 assume !(0 != activate_threads_~tmp___2~0); 104152#L769-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 104153#L370 assume !(1 == ~t4_pc~0); 104303#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 104300#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 104301#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 104318#L777 assume !(0 != activate_threads_~tmp___3~0); 104319#L777-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 103763#L389 assume !(1 == ~t5_pc~0); 103729#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 103730#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 103761#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 103785#L785 assume !(0 != activate_threads_~tmp___4~0); 103786#L785-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 103788#L669 assume !(1 == ~M_E~0); 104341#L669-2 assume !(1 == ~T1_E~0); 104037#L674-1 assume !(1 == ~T2_E~0); 104038#L679-1 assume !(1 == ~T3_E~0); 103958#L684-1 assume !(1 == ~T4_E~0); 103959#L689-1 assume !(1 == ~T5_E~0); 104203#L694-1 assume !(1 == ~E_M~0); 103844#L699-1 assume !(1 == ~E_1~0); 103845#L704-1 assume !(1 == ~E_2~0); 103660#L709-1 assume !(1 == ~E_3~0); 103661#L714-1 assume !(1 == ~E_4~0); 103768#L719-1 assume !(1 == ~E_5~0); 103769#L724-1 assume { :end_inline_reset_delta_events } true; 104340#L930-3 [2018-11-18 15:17:53,761 INFO L796 eck$LassoCheckResult]: Loop: 104340#L930-3 assume true; 104713#L930-1 assume !false; 104705#L931 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 104696#L576 assume true; 104694#L496-1 assume !false; 104692#L497 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 104690#L454 assume !(0 == ~m_st~0); 104688#L458 assume !(0 == ~t1_st~0); 104686#L462 assume !(0 == ~t2_st~0); 104684#L466 assume !(0 == ~t3_st~0); 104682#L470 assume !(0 == ~t4_st~0); 104679#L474 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 104676#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 104674#L487 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 104671#L501 assume !(0 != eval_~tmp~0); 104668#L591 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 104666#L409-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 104664#L601-3 assume !(0 == ~M_E~0); 104662#L601-5 assume !(0 == ~T1_E~0); 104660#L606-3 assume !(0 == ~T2_E~0); 104658#L611-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 104656#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 104654#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 104652#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 104650#L631-3 assume !(0 == ~E_1~0); 104648#L636-3 assume !(0 == ~E_2~0); 104646#L641-3 assume !(0 == ~E_3~0); 104644#L646-3 assume !(0 == ~E_4~0); 104642#L651-3 assume 0 == ~E_5~0;~E_5~0 := 1; 104640#L656-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 104638#L294-21 assume 1 == ~m_pc~0; 104635#L295-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 104632#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 104630#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 104628#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 104626#L745-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 104624#L313-21 assume !(1 == ~t1_pc~0); 104622#L313-23 is_transmit1_triggered_~__retres1~1 := 0; 104620#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 104618#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 104616#L753-21 assume !(0 != activate_threads_~tmp___0~0); 104614#L753-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 104612#L332-21 assume !(1 == ~t2_pc~0); 104608#L332-23 is_transmit2_triggered_~__retres1~2 := 0; 104606#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 104604#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 104602#L761-21 assume !(0 != activate_threads_~tmp___1~0); 104600#L761-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 104598#L351-21 assume !(1 == ~t3_pc~0); 104594#L351-23 is_transmit3_triggered_~__retres1~3 := 0; 104592#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 104590#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 104588#L769-21 assume !(0 != activate_threads_~tmp___2~0); 104586#L769-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 104584#L370-21 assume !(1 == ~t4_pc~0); 104582#L370-23 is_transmit4_triggered_~__retres1~4 := 0; 104580#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 104578#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 104576#L777-21 assume !(0 != activate_threads_~tmp___3~0); 104574#L777-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 104572#L389-21 assume 1 == ~t5_pc~0; 104569#L390-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 104566#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 104564#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 104562#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 104560#L785-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 104558#L669-3 assume !(1 == ~M_E~0); 104557#L669-5 assume !(1 == ~T1_E~0); 104945#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 104944#L679-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 104943#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 104942#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 104941#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 104940#L699-3 assume !(1 == ~E_1~0); 104939#L704-3 assume !(1 == ~E_2~0); 104938#L709-3 assume !(1 == ~E_3~0); 104937#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 104936#L719-3 assume 1 == ~E_5~0;~E_5~0 := 2; 104935#L724-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 104533#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 104528#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 104526#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 104522#L949 assume !(0 == start_simulation_~tmp~3); 104523#L949-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 104864#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 104860#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 104859#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 104858#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 104733#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 104728#L912 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 104724#L962 assume !(0 != start_simulation_~tmp___0~1); 104340#L930-3 [2018-11-18 15:17:53,761 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:53,762 INFO L82 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 7 times [2018-11-18 15:17:53,762 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:53,762 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:53,762 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:53,762 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:53,762 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:53,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:17:53,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:17:53,779 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:53,779 INFO L82 PathProgramCache]: Analyzing trace with hash -1784096965, now seen corresponding path program 1 times [2018-11-18 15:17:53,779 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:53,779 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:53,780 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:53,780 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:53,780 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:53,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:17:53,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:17:53,799 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:53,799 INFO L82 PathProgramCache]: Analyzing trace with hash 1431287927, now seen corresponding path program 1 times [2018-11-18 15:17:53,799 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:53,799 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:53,800 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:53,800 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:53,800 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:53,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:53,856 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:17:53,856 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:17:53,856 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:17:54,290 WARN L180 SmtUtils]: Spent 426.00 ms on a formula simplification. DAG size of input: 190 DAG size of output: 172 [2018-11-18 15:17:54,415 WARN L180 SmtUtils]: Spent 116.00 ms on a formula simplification that was a NOOP. DAG size: 150 [2018-11-18 15:17:54,423 INFO L216 LassoAnalysis]: Preferences: [2018-11-18 15:17:54,424 INFO L124 ssoRankerPreferences]: Compute integeral hull: false [2018-11-18 15:17:54,424 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true [2018-11-18 15:17:54,424 INFO L126 ssoRankerPreferences]: Term annotations enabled: false [2018-11-18 15:17:54,425 INFO L127 ssoRankerPreferences]: Use exernal solver: true [2018-11-18 15:17:54,425 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 15:17:54,425 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false [2018-11-18 15:17:54,425 INFO L130 ssoRankerPreferences]: Path of dumped script: [2018-11-18 15:17:54,425 INFO L131 ssoRankerPreferences]: Filename of dumped script: token_ring.05_false-unreach-call_false-termination.cil.c_Iteration20_Loop [2018-11-18 15:17:54,425 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank [2018-11-18 15:17:54,425 INFO L282 LassoAnalysis]: Starting lasso preprocessing... [2018-11-18 15:17:54,443 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,447 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,453 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,458 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,460 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,461 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,462 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,464 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,467 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,468 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,471 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,472 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,473 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,474 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,476 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,481 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,482 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,484 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,487 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,490 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,492 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,493 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,495 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,496 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,497 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,498 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,501 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,503 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,504 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,506 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,507 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,510 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,511 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,512 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,513 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,516 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,517 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,519 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,523 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,530 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,531 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,532 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,535 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,538 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,539 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,540 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,541 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,542 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,547 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,548 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,554 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,559 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,563 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,575 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,576 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,582 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,590 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,598 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,601 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:54,965 INFO L300 LassoAnalysis]: Preprocessing complete. [2018-11-18 15:17:54,966 INFO L412 LassoAnalysis]: Checking for nontermination... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d6bfc3eb-9043-4962-ad04-a405114524f4/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 15:17:54,978 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 15:17:54,979 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 15:17:54,996 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 15:17:54,996 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret14=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret14=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d6bfc3eb-9043-4962-ad04-a405114524f4/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 15:17:55,031 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 15:17:55,031 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 15:17:55,033 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 15:17:55,034 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_#t~ret16=0} Honda state: {ULTIMATE.start_start_simulation_#t~ret16=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d6bfc3eb-9043-4962-ad04-a405114524f4/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 15:17:55,058 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 15:17:55,059 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 15:17:55,066 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 15:17:55,066 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~__retres2~0=0, ULTIMATE.start_start_simulation_~tmp___0~1=0, ULTIMATE.start_stop_simulation_#res=0} Honda state: {ULTIMATE.start_stop_simulation_~__retres2~0=0, ULTIMATE.start_start_simulation_~tmp___0~1=0, ULTIMATE.start_stop_simulation_#res=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d6bfc3eb-9043-4962-ad04-a405114524f4/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 15:17:55,084 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 15:17:55,084 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 15:17:55,088 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 15:17:55,088 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_st~0=-1} Honda state: {~t4_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d6bfc3eb-9043-4962-ad04-a405114524f4/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 15:17:55,110 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 15:17:55,110 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 15:17:55,125 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 15:17:55,125 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~m_pc~0=1} Honda state: {~m_pc~0=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d6bfc3eb-9043-4962-ad04-a405114524f4/bin-2019/uautomizer/z3 Starting monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 15:17:55,141 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 15:17:55,141 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 15:17:55,143 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 15:17:55,143 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_#t~ret15=0} Honda state: {ULTIMATE.start_stop_simulation_#t~ret15=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d6bfc3eb-9043-4962-ad04-a405114524f4/bin-2019/uautomizer/z3 Starting monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 15:17:55,158 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 15:17:55,158 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 15:17:55,161 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 15:17:55,161 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~E_1~0=-5} Honda state: {~E_1~0=-5} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d6bfc3eb-9043-4962-ad04-a405114524f4/bin-2019/uautomizer/z3 Starting monitored process 9 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 15:17:55,179 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 15:17:55,179 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 15:17:55,190 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 15:17:55,190 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~tmp~2=1, ULTIMATE.start_exists_runnable_thread_#res=1, ULTIMATE.start_exists_runnable_thread_~__retres1~6=1} Honda state: {ULTIMATE.start_stop_simulation_~tmp~2=1, ULTIMATE.start_exists_runnable_thread_#res=1, ULTIMATE.start_exists_runnable_thread_~__retres1~6=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d6bfc3eb-9043-4962-ad04-a405114524f4/bin-2019/uautomizer/z3 Starting monitored process 10 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 15:17:55,210 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 15:17:55,210 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 15:17:55,213 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 15:17:55,213 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret10=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret10=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d6bfc3eb-9043-4962-ad04-a405114524f4/bin-2019/uautomizer/z3 Starting monitored process 11 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 15:17:55,234 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 15:17:55,234 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 15:17:55,237 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 15:17:55,237 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___0~0=0, ULTIMATE.start_is_transmit1_triggered_#res=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___0~0=0, ULTIMATE.start_is_transmit1_triggered_#res=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d6bfc3eb-9043-4962-ad04-a405114524f4/bin-2019/uautomizer/z3 Starting monitored process 12 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 15:17:55,253 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 15:17:55,253 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 15:17:55,255 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 15:17:55,255 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet7=0} Honda state: {ULTIMATE.start_eval_#t~nondet7=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d6bfc3eb-9043-4962-ad04-a405114524f4/bin-2019/uautomizer/z3 Starting monitored process 13 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 15:17:55,271 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 15:17:55,271 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 15:17:55,273 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 15:17:55,273 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t3_pc~0=4} Honda state: {~t3_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d6bfc3eb-9043-4962-ad04-a405114524f4/bin-2019/uautomizer/z3 Starting monitored process 14 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 15:17:55,288 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 15:17:55,288 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 15:17:55,291 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 15:17:55,291 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t1_st~0=-1} Honda state: {~t1_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d6bfc3eb-9043-4962-ad04-a405114524f4/bin-2019/uautomizer/z3 Starting monitored process 15 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 15:17:55,308 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 15:17:55,308 INFO L163 nArgumentSynthesizer]: Using integer mode. No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_d6bfc3eb-9043-4962-ad04-a405114524f4/bin-2019/uautomizer/z3 Starting monitored process 16 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 15:17:55,336 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2018-11-18 15:17:55,336 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 15:17:55,341 INFO L452 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2018-11-18 15:17:55,355 INFO L216 LassoAnalysis]: Preferences: [2018-11-18 15:17:55,355 INFO L124 ssoRankerPreferences]: Compute integeral hull: false [2018-11-18 15:17:55,355 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true [2018-11-18 15:17:55,355 INFO L126 ssoRankerPreferences]: Term annotations enabled: false [2018-11-18 15:17:55,355 INFO L127 ssoRankerPreferences]: Use exernal solver: false [2018-11-18 15:17:55,355 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 15:17:55,355 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false [2018-11-18 15:17:55,355 INFO L130 ssoRankerPreferences]: Path of dumped script: [2018-11-18 15:17:55,355 INFO L131 ssoRankerPreferences]: Filename of dumped script: token_ring.05_false-unreach-call_false-termination.cil.c_Iteration20_Loop [2018-11-18 15:17:55,355 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank [2018-11-18 15:17:55,355 INFO L282 LassoAnalysis]: Starting lasso preprocessing... [2018-11-18 15:17:55,358 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,366 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,367 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,368 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,369 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,371 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,380 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,382 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,383 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,386 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,387 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,389 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,391 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,392 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,398 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,401 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,403 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,407 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,412 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,416 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,425 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,427 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,430 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,431 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,432 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,434 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,439 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,450 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,452 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,462 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,464 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,466 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,468 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,470 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,472 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,475 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,479 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,480 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,481 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,483 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,486 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,490 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,492 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,496 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,498 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,500 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,502 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,506 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,508 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,520 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,523 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,527 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,533 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,536 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,539 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,543 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,544 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,550 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,553 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:17:55,876 INFO L300 LassoAnalysis]: Preprocessing complete. [2018-11-18 15:17:55,881 INFO L497 LassoAnalysis]: Using template 'affine'. [2018-11-18 15:17:55,882 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 15:17:55,882 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 15:17:55,883 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 15:17:55,883 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 15:17:55,883 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-18 15:17:55,883 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 15:17:55,885 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-18 15:17:55,885 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 15:17:55,887 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 15:17:55,887 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 15:17:55,888 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 15:17:55,888 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 15:17:55,888 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 15:17:55,888 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-18 15:17:55,888 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 15:17:55,888 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-18 15:17:55,888 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 15:17:55,889 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 15:17:55,889 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 15:17:55,890 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 15:17:55,890 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 15:17:55,890 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 15:17:55,890 INFO L206 nArgumentSynthesizer]: 2 loop disjuncts [2018-11-18 15:17:55,890 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 15:17:55,891 INFO L402 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2018-11-18 15:17:55,891 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 15:17:55,891 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 15:17:55,892 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 15:17:55,892 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 15:17:55,892 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 15:17:55,892 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 15:17:55,892 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-18 15:17:55,892 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 15:17:55,893 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-18 15:17:55,893 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 15:17:55,894 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 15:17:55,894 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 15:17:55,894 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 15:17:55,894 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 15:17:55,895 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 15:17:55,895 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-18 15:17:55,895 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 15:17:55,895 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-18 15:17:55,895 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 15:17:55,895 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 15:17:55,896 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 15:17:55,896 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 15:17:55,896 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 15:17:55,896 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 15:17:55,896 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-18 15:17:55,896 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 15:17:55,897 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-18 15:17:55,897 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 15:17:55,898 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 15:17:55,899 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 15:17:55,899 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 15:17:55,899 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 15:17:55,899 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 15:17:55,899 INFO L206 nArgumentSynthesizer]: 2 loop disjuncts [2018-11-18 15:17:55,899 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 15:17:55,900 INFO L402 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2018-11-18 15:17:55,900 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 15:17:55,901 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 15:17:55,901 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 15:17:55,901 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 15:17:55,902 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 15:17:55,902 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 15:17:55,902 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-18 15:17:55,902 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 15:17:55,902 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-18 15:17:55,902 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 15:17:55,903 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 15:17:55,903 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 15:17:55,903 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 15:17:55,904 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 15:17:55,904 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 15:17:55,904 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-18 15:17:55,904 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 15:17:55,904 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-18 15:17:55,904 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 15:17:55,905 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 15:17:55,905 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 15:17:55,906 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 15:17:55,906 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 15:17:55,906 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 15:17:55,906 INFO L206 nArgumentSynthesizer]: 2 loop disjuncts [2018-11-18 15:17:55,906 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 15:17:55,906 INFO L402 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2018-11-18 15:17:55,906 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 15:17:55,907 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 15:17:55,907 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 15:17:55,908 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 15:17:55,908 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 15:17:55,908 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 15:17:55,908 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-18 15:17:55,908 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 15:17:55,908 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-18 15:17:55,908 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 15:17:55,909 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 15:17:55,909 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 15:17:55,909 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 15:17:55,910 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 15:17:55,910 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 15:17:55,910 INFO L206 nArgumentSynthesizer]: 2 loop disjuncts [2018-11-18 15:17:55,910 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 15:17:55,910 INFO L402 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2018-11-18 15:17:55,910 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 15:17:55,911 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 15:17:55,911 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 15:17:55,911 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 15:17:55,912 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 15:17:55,912 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 15:17:55,912 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-18 15:17:55,912 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 15:17:55,912 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-18 15:17:55,912 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 15:17:55,913 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 15:17:55,913 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 15:17:55,913 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 15:17:55,913 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 15:17:55,914 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 15:17:55,914 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-18 15:17:55,914 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 15:17:55,914 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-18 15:17:55,914 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 15:17:55,916 INFO L421 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2018-11-18 15:17:55,917 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2018-11-18 15:17:55,917 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2018-11-18 15:17:55,919 INFO L437 nArgumentSynthesizer]: Simplifying supporting invariants... [2018-11-18 15:17:55,919 INFO L440 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2018-11-18 15:17:55,919 INFO L518 LassoAnalysis]: Proved termination. [2018-11-18 15:17:55,919 INFO L520 LassoAnalysis]: Termination argument consisting of: Ranking function f(~E_4~0) = -2*~E_4~0 + 3 Supporting invariants [] [2018-11-18 15:17:55,920 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2018-11-18 15:17:56,004 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:56,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:56,049 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:17:56,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:56,083 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:17:56,145 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:17:56,150 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2018-11-18 15:17:56,151 INFO L72 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 3465 states and 4604 transitions. cyclomatic complexity: 1143 Second operand 4 states. [2018-11-18 15:17:56,292 INFO L76 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 3465 states and 4604 transitions. cyclomatic complexity: 1143. Second operand 4 states. Result 9595 states and 12847 transitions. Complement of second has 5 states. [2018-11-18 15:17:56,293 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2018-11-18 15:17:56,294 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2018-11-18 15:17:56,295 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 705 transitions. [2018-11-18 15:17:56,296 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 705 transitions. Stem has 73 letters. Loop has 91 letters. [2018-11-18 15:17:56,298 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-18 15:17:56,298 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 705 transitions. Stem has 164 letters. Loop has 91 letters. [2018-11-18 15:17:56,300 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-18 15:17:56,300 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 705 transitions. Stem has 73 letters. Loop has 182 letters. [2018-11-18 15:17:56,301 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-18 15:17:56,301 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9595 states and 12847 transitions. [2018-11-18 15:17:56,342 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6388 [2018-11-18 15:17:56,367 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9595 states to 9587 states and 12839 transitions. [2018-11-18 15:17:56,367 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6506 [2018-11-18 15:17:56,373 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6531 [2018-11-18 15:17:56,373 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9587 states and 12839 transitions. [2018-11-18 15:17:56,373 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-18 15:17:56,373 INFO L705 BuchiCegarLoop]: Abstraction has 9587 states and 12839 transitions. [2018-11-18 15:17:56,379 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9587 states and 12839 transitions. [2018-11-18 15:17:56,504 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9587 to 9554. [2018-11-18 15:17:56,505 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9554 states. [2018-11-18 15:17:56,522 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9554 states to 9554 states and 12806 transitions. [2018-11-18 15:17:56,522 INFO L728 BuchiCegarLoop]: Abstraction has 9554 states and 12806 transitions. [2018-11-18 15:17:56,523 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:17:56,523 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:17:56,523 INFO L87 Difference]: Start difference. First operand 9554 states and 12806 transitions. Second operand 3 states. [2018-11-18 15:17:56,682 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:17:56,682 INFO L93 Difference]: Finished difference Result 17630 states and 23122 transitions. [2018-11-18 15:17:56,683 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:17:56,683 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17630 states and 23122 transitions. [2018-11-18 15:17:56,739 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11848 [2018-11-18 15:17:56,773 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17630 states to 17630 states and 23122 transitions. [2018-11-18 15:17:56,773 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11990 [2018-11-18 15:17:56,781 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11990 [2018-11-18 15:17:56,781 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17630 states and 23122 transitions. [2018-11-18 15:17:56,781 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-18 15:17:56,781 INFO L705 BuchiCegarLoop]: Abstraction has 17630 states and 23122 transitions. [2018-11-18 15:17:56,789 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17630 states and 23122 transitions. [2018-11-18 15:17:56,900 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17630 to 16694. [2018-11-18 15:17:56,900 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16694 states. [2018-11-18 15:17:56,923 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16694 states to 16694 states and 21994 transitions. [2018-11-18 15:17:56,923 INFO L728 BuchiCegarLoop]: Abstraction has 16694 states and 21994 transitions. [2018-11-18 15:17:56,923 INFO L608 BuchiCegarLoop]: Abstraction has 16694 states and 21994 transitions. [2018-11-18 15:17:56,923 INFO L442 BuchiCegarLoop]: ======== Iteration 21============ [2018-11-18 15:17:56,923 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16694 states and 21994 transitions. [2018-11-18 15:17:56,963 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11224 [2018-11-18 15:17:56,963 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:17:56,963 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:17:56,965 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:56,965 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:56,965 INFO L794 eck$LassoCheckResult]: Stem: 145344#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 145164#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 144943#L893 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 144866#L409 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 144867#L416 assume 1 == ~m_i~0;~m_st~0 := 0; 145283#L416-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 145020#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 145021#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 144872#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 144873#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 144956#L441-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 144957#L601 assume !(0 == ~M_E~0); 145491#L601-2 assume !(0 == ~T1_E~0); 144960#L606-1 assume !(0 == ~T2_E~0); 144726#L611-1 assume !(0 == ~T3_E~0); 144727#L616-1 assume !(0 == ~T4_E~0); 144440#L621-1 assume !(0 == ~T5_E~0); 144441#L626-1 assume !(0 == ~E_M~0); 144630#L631-1 assume !(0 == ~E_1~0); 144631#L636-1 assume !(0 == ~E_2~0); 145072#L641-1 assume !(0 == ~E_3~0); 145073#L646-1 assume !(0 == ~E_4~0); 144937#L651-1 assume !(0 == ~E_5~0); 144938#L656-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 145513#L294 assume !(1 == ~m_pc~0); 145268#L294-2 is_master_triggered_~__retres1~0 := 0; 145267#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 145296#L306 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 145297#L745 assume !(0 != activate_threads_~tmp~1); 145626#L745-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 144820#L313 assume !(1 == ~t1_pc~0); 144821#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 144819#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 144714#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 144470#L753 assume !(0 != activate_threads_~tmp___0~0); 144471#L753-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 144477#L332 assume !(1 == ~t2_pc~0); 144883#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 144880#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 144881#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 144930#L761 assume !(0 != activate_threads_~tmp___1~0); 144931#L761-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 144932#L351 assume !(1 == ~t3_pc~0); 145173#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 145174#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 145216#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 145232#L769 assume !(0 != activate_threads_~tmp___2~0); 145233#L769-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 145237#L370 assume !(1 == ~t4_pc~0); 145475#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 145471#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 145472#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 145508#L777 assume !(0 != activate_threads_~tmp___3~0); 145509#L777-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 144613#L389 assume !(1 == ~t5_pc~0); 144548#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 144549#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 144610#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 144655#L785 assume !(0 != activate_threads_~tmp___4~0); 144656#L785-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 144661#L669 assume !(1 == ~M_E~0); 145532#L669-2 assume !(1 == ~T1_E~0); 145070#L674-1 assume !(1 == ~T2_E~0); 145071#L679-1 assume !(1 == ~T3_E~0); 144935#L684-1 assume !(1 == ~T4_E~0); 144936#L689-1 assume !(1 == ~T5_E~0); 145325#L694-1 assume !(1 == ~E_M~0); 144768#L699-1 assume !(1 == ~E_1~0); 144769#L704-1 assume !(1 == ~E_2~0); 144418#L709-1 assume !(1 == ~E_3~0); 144419#L714-1 assume !(1 == ~E_4~0); 144621#L719-1 assume !(1 == ~E_5~0); 144622#L724-1 assume { :end_inline_reset_delta_events } true; 145531#L930-3 assume true; 149306#L930-1 [2018-11-18 15:17:56,965 INFO L796 eck$LassoCheckResult]: Loop: 149306#L930-1 assume !false; 154944#L931 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 154938#L576 assume true; 154936#L496-1 assume !false; 154934#L497 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 154932#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 152940#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 154902#L487 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 154897#L501 assume 0 != eval_~tmp~0; 154878#L501-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 152536#L509 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1;assume { :begin_inline_master } true;havoc master_#t~nondet0, master_#t~nondet1, master_~tmp_var~0;master_~tmp_var~0 := master_#t~nondet0;havoc master_#t~nondet0; 154873#L58 assume 0 == ~m_pc~0; 155318#L94 assume true; 155315#L69 assume !false; 155313#L70 ~token~0 := master_#t~nondet1;havoc master_#t~nondet1;~local~0 := ~token~0;~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 155311#L294-3 assume !(1 == ~m_pc~0); 155308#L294-5 is_master_triggered_~__retres1~0 := 0; 155306#L305-1 is_master_triggered_#res := is_master_triggered_~__retres1~0; 155304#L306-1 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 155301#L745-3 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 155299#L745-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 155297#L313-3 assume !(1 == ~t1_pc~0); 155295#L313-5 is_transmit1_triggered_~__retres1~1 := 0; 155292#L324-1 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 155290#L325-1 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 155288#L753-3 assume !(0 != activate_threads_~tmp___0~0); 155286#L753-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 155284#L332-3 assume !(1 == ~t2_pc~0); 155281#L332-5 is_transmit2_triggered_~__retres1~2 := 0; 155279#L343-1 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 155277#L344-1 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 155275#L761-3 assume !(0 != activate_threads_~tmp___1~0); 155272#L761-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 155270#L351-3 assume !(1 == ~t3_pc~0); 155267#L351-5 is_transmit3_triggered_~__retres1~3 := 0; 155265#L362-1 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 155263#L363-1 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 155259#L769-3 assume !(0 != activate_threads_~tmp___2~0); 155257#L769-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 155255#L370-3 assume !(1 == ~t4_pc~0); 155207#L370-5 is_transmit4_triggered_~__retres1~4 := 0; 154800#L381-1 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 154436#L382-1 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 154431#L777-3 assume !(0 != activate_threads_~tmp___3~0); 154430#L777-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 154427#L389-3 assume 1 == ~t5_pc~0; 154183#L390-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 154181#L400-1 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 154179#L401-1 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 154177#L785-3 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 154175#L785-5 assume { :end_inline_activate_threads } true; 152543#L802 assume { :end_inline_immediate_notify } true;~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 152534#L103 assume { :end_inline_master } true; 152530#L506 assume !(0 == ~t1_st~0); 152528#L520 assume !(0 == ~t2_st~0); 152523#L534 assume !(0 == ~t3_st~0); 152521#L548 assume !(0 == ~t4_st~0); 152948#L562 assume !(0 == ~t5_st~0); 152943#L576 assume true; 152942#L496-1 assume !false; 152941#L497 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 152939#L454 assume !(0 == ~m_st~0); 152938#L458 assume !(0 == ~t1_st~0); 152937#L462 assume !(0 == ~t2_st~0); 152936#L466 assume !(0 == ~t3_st~0); 152935#L470 assume !(0 == ~t4_st~0); 152933#L474 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 152932#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 152931#L487 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 152930#L501 assume !(0 != eval_~tmp~0); 152929#L591 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 152928#L409-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 152927#L601-3 assume !(0 == ~M_E~0); 152926#L601-5 assume !(0 == ~T1_E~0); 152925#L606-3 assume !(0 == ~T2_E~0); 152924#L611-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 152923#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 152922#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 152921#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 152920#L631-3 assume !(0 == ~E_1~0); 152919#L636-3 assume !(0 == ~E_2~0); 152918#L641-3 assume !(0 == ~E_3~0); 152917#L646-3 assume !(0 == ~E_4~0); 152916#L651-3 assume 0 == ~E_5~0;~E_5~0 := 1; 152915#L656-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 152914#L294-21 assume 1 == ~m_pc~0; 152912#L295-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 152911#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 152910#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 152908#L745-21 assume !(0 != activate_threads_~tmp~1); 152907#L745-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 152906#L313-21 assume !(1 == ~t1_pc~0); 152905#L313-23 is_transmit1_triggered_~__retres1~1 := 0; 152904#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 152903#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 152902#L753-21 assume !(0 != activate_threads_~tmp___0~0); 152901#L753-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 152900#L332-21 assume !(1 == ~t2_pc~0); 152898#L332-23 is_transmit2_triggered_~__retres1~2 := 0; 152897#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 152896#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 152895#L761-21 assume !(0 != activate_threads_~tmp___1~0); 152894#L761-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 152893#L351-21 assume !(1 == ~t3_pc~0); 152891#L351-23 is_transmit3_triggered_~__retres1~3 := 0; 152890#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 152889#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 152888#L769-21 assume !(0 != activate_threads_~tmp___2~0); 152887#L769-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 152886#L370-21 assume !(1 == ~t4_pc~0); 152885#L370-23 is_transmit4_triggered_~__retres1~4 := 0; 152884#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 152883#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 152882#L777-21 assume !(0 != activate_threads_~tmp___3~0); 152881#L777-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 152880#L389-21 assume 1 == ~t5_pc~0; 152878#L390-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 152877#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 152876#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 152875#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 152874#L785-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 152873#L669-3 assume !(1 == ~M_E~0); 152294#L669-5 assume !(1 == ~T1_E~0); 152872#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 152871#L679-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 152870#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 152869#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 152868#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 152867#L699-3 assume !(1 == ~E_1~0); 152866#L704-3 assume !(1 == ~E_2~0); 152865#L709-3 assume !(1 == ~E_3~0); 152864#L714-3 assume !(1 == ~E_4~0); 152863#L719-3 assume 1 == ~E_5~0;~E_5~0 := 2; 152862#L724-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 152859#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 152860#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 150673#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 150661#L949 assume !(0 == start_simulation_~tmp~3); 150662#L949-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 154975#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 152981#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 154972#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 154970#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 154966#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 154964#L912 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 154962#L962 assume !(0 != start_simulation_~tmp___0~1); 154960#L930-3 assume true; 149306#L930-1 [2018-11-18 15:17:56,966 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:56,966 INFO L82 PathProgramCache]: Analyzing trace with hash 959436202, now seen corresponding path program 1 times [2018-11-18 15:17:56,966 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:56,966 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:56,966 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:56,966 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:56,967 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:56,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:17:56,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:17:56,983 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:56,983 INFO L82 PathProgramCache]: Analyzing trace with hash 492013689, now seen corresponding path program 1 times [2018-11-18 15:17:56,983 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:56,983 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:56,984 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:56,984 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:56,984 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:56,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:57,043 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:17:57,043 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:17:57,044 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:17:57,044 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:17:57,044 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:17:57,044 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:17:57,044 INFO L87 Difference]: Start difference. First operand 16694 states and 21994 transitions. cyclomatic complexity: 5312 Second operand 5 states. [2018-11-18 15:17:57,303 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:17:57,303 INFO L93 Difference]: Finished difference Result 39805 states and 51951 transitions. [2018-11-18 15:17:57,304 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 15:17:57,304 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39805 states and 51951 transitions. [2018-11-18 15:17:57,431 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 26732 [2018-11-18 15:17:57,511 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39805 states to 39805 states and 51951 transitions. [2018-11-18 15:17:57,511 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27101 [2018-11-18 15:17:57,527 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27101 [2018-11-18 15:17:57,527 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39805 states and 51951 transitions. [2018-11-18 15:17:57,528 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-18 15:17:57,528 INFO L705 BuchiCegarLoop]: Abstraction has 39805 states and 51951 transitions. [2018-11-18 15:17:57,546 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39805 states and 51951 transitions. [2018-11-18 15:17:57,674 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39805 to 17393. [2018-11-18 15:17:57,674 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17393 states. [2018-11-18 15:17:57,689 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17393 states to 17393 states and 22693 transitions. [2018-11-18 15:17:57,690 INFO L728 BuchiCegarLoop]: Abstraction has 17393 states and 22693 transitions. [2018-11-18 15:17:57,690 INFO L608 BuchiCegarLoop]: Abstraction has 17393 states and 22693 transitions. [2018-11-18 15:17:57,690 INFO L442 BuchiCegarLoop]: ======== Iteration 22============ [2018-11-18 15:17:57,690 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17393 states and 22693 transitions. [2018-11-18 15:17:57,715 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11704 [2018-11-18 15:17:57,715 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:17:57,715 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:17:57,716 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:57,716 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:57,717 INFO L794 eck$LassoCheckResult]: Stem: 201811#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 201641#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 201433#L893 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 201357#L409 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 201358#L416 assume 1 == ~m_i~0;~m_st~0 := 0; 201752#L416-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 201506#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 201507#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 201363#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 201364#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 201444#L441-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 201445#L601 assume !(0 == ~M_E~0); 201937#L601-2 assume !(0 == ~T1_E~0); 201450#L606-1 assume !(0 == ~T2_E~0); 201225#L611-1 assume !(0 == ~T3_E~0); 201226#L616-1 assume !(0 == ~T4_E~0); 200952#L621-1 assume !(0 == ~T5_E~0); 200953#L626-1 assume !(0 == ~E_M~0); 201134#L631-1 assume !(0 == ~E_1~0); 201135#L636-1 assume !(0 == ~E_2~0); 201553#L641-1 assume !(0 == ~E_3~0); 201554#L646-1 assume !(0 == ~E_4~0); 201427#L651-1 assume !(0 == ~E_5~0); 201428#L656-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 201953#L294 assume !(1 == ~m_pc~0); 201737#L294-2 is_master_triggered_~__retres1~0 := 0; 202088#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 202089#L306 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 202119#L745 assume !(0 != activate_threads_~tmp~1); 202120#L745-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 201314#L313 assume !(1 == ~t1_pc~0); 201315#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 201313#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 201213#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 200981#L753 assume !(0 != activate_threads_~tmp___0~0); 200982#L753-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 200987#L332 assume !(1 == ~t2_pc~0); 201374#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 201371#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 201372#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 201420#L761 assume !(0 != activate_threads_~tmp___1~0); 201421#L761-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 201422#L351 assume !(1 == ~t3_pc~0); 201650#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 201651#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 201692#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 201703#L769 assume !(0 != activate_threads_~tmp___2~0); 201704#L769-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 201705#L370 assume !(1 == ~t4_pc~0); 201924#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 201918#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 201919#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 201949#L777 assume !(0 != activate_threads_~tmp___3~0); 201950#L777-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 201117#L389 assume !(1 == ~t5_pc~0); 201053#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 201054#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 201110#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 201157#L785 assume !(0 != activate_threads_~tmp___4~0); 201158#L785-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 201161#L669 assume !(1 == ~M_E~0); 201983#L669-2 assume !(1 == ~T1_E~0); 201551#L674-1 assume !(1 == ~T2_E~0); 201552#L679-1 assume !(1 == ~T3_E~0); 201425#L684-1 assume !(1 == ~T4_E~0); 201426#L689-1 assume !(1 == ~T5_E~0); 201794#L694-1 assume !(1 == ~E_M~0); 201265#L699-1 assume !(1 == ~E_1~0); 201266#L704-1 assume !(1 == ~E_2~0); 200930#L709-1 assume !(1 == ~E_3~0); 200931#L714-1 assume !(1 == ~E_4~0); 201126#L719-1 assume !(1 == ~E_5~0); 201127#L724-1 assume { :end_inline_reset_delta_events } true; 201982#L930-3 assume true; 204548#L930-1 [2018-11-18 15:17:57,717 INFO L796 eck$LassoCheckResult]: Loop: 204548#L930-1 assume !false; 214721#L931 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 214715#L576 assume true; 214716#L496-1 assume !false; 214711#L497 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 211641#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 211638#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 211636#L487 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 211634#L501 assume 0 != eval_~tmp~0; 211632#L501-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 211006#L509 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1;assume { :begin_inline_master } true;havoc master_#t~nondet0, master_#t~nondet1, master_~tmp_var~0;master_~tmp_var~0 := master_#t~nondet0;havoc master_#t~nondet0; 211623#L58 assume 0 == ~m_pc~0; 211621#L94 assume true; 211619#L69 assume !false; 211618#L70 ~token~0 := master_#t~nondet1;havoc master_#t~nondet1;~local~0 := ~token~0;~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 211617#L294-3 assume !(1 == ~m_pc~0); 211616#L294-5 is_master_triggered_~__retres1~0 := 0; 211614#L305-1 is_master_triggered_#res := is_master_triggered_~__retres1~0; 211612#L306-1 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 211610#L745-3 assume !(0 != activate_threads_~tmp~1); 211605#L745-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 211603#L313-3 assume !(1 == ~t1_pc~0); 211601#L313-5 is_transmit1_triggered_~__retres1~1 := 0; 211599#L324-1 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 211598#L325-1 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 211593#L753-3 assume !(0 != activate_threads_~tmp___0~0); 211532#L753-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 211523#L332-3 assume !(1 == ~t2_pc~0); 211520#L332-5 is_transmit2_triggered_~__retres1~2 := 0; 211410#L343-1 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 211409#L344-1 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 211337#L761-3 assume !(0 != activate_threads_~tmp___1~0); 211334#L761-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 211332#L351-3 assume !(1 == ~t3_pc~0); 211322#L351-5 is_transmit3_triggered_~__retres1~3 := 0; 211263#L362-1 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 211206#L363-1 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 211204#L769-3 assume !(0 != activate_threads_~tmp___2~0); 211202#L769-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 211200#L370-3 assume !(1 == ~t4_pc~0); 211199#L370-5 is_transmit4_triggered_~__retres1~4 := 0; 211193#L381-1 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 211191#L382-1 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 211078#L777-3 assume !(0 != activate_threads_~tmp___3~0); 211076#L777-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 211074#L389-3 assume !(1 == ~t5_pc~0); 211070#L389-5 is_transmit5_triggered_~__retres1~5 := 0; 211067#L400-1 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 211065#L401-1 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 211063#L785-3 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 211060#L785-5 assume { :end_inline_activate_threads } true; 211058#L802 assume { :end_inline_immediate_notify } true;~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 211004#L103 assume { :end_inline_master } true; 210998#L506 assume !(0 == ~t1_st~0); 210931#L520 assume !(0 == ~t2_st~0); 213696#L534 assume !(0 == ~t3_st~0); 213693#L548 assume !(0 == ~t4_st~0); 214768#L562 assume !(0 == ~t5_st~0); 218154#L576 assume true; 214712#L496-1 assume !false; 214713#L497 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 218152#L454 assume !(0 == ~m_st~0); 218151#L458 assume !(0 == ~t1_st~0); 218149#L462 assume !(0 == ~t2_st~0); 218150#L466 assume !(0 == ~t3_st~0); 218148#L470 assume !(0 == ~t4_st~0); 218146#L474 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 218144#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 218143#L487 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 218132#L501 assume !(0 != eval_~tmp~0); 218130#L591 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 218128#L409-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 218127#L601-3 assume !(0 == ~M_E~0); 218126#L601-5 assume !(0 == ~T1_E~0); 218125#L606-3 assume !(0 == ~T2_E~0); 218124#L611-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 218123#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 218122#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 218121#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 218120#L631-3 assume !(0 == ~E_1~0); 201968#L636-3 assume !(0 == ~E_2~0); 201528#L641-3 assume !(0 == ~E_3~0); 201529#L646-3 assume !(0 == ~E_4~0); 202112#L651-3 assume 0 == ~E_5~0;~E_5~0 := 1; 217679#L656-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 201971#L294-21 assume 1 == ~m_pc~0; 201973#L295-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 217678#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 217667#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 217668#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 217803#L745-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 217802#L313-21 assume !(1 == ~t1_pc~0); 217801#L313-23 is_transmit1_triggered_~__retres1~1 := 0; 217800#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 217799#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 217798#L753-21 assume !(0 != activate_threads_~tmp___0~0); 217797#L753-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 217796#L332-21 assume !(1 == ~t2_pc~0); 217794#L332-23 is_transmit2_triggered_~__retres1~2 := 0; 217793#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 217792#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 217791#L761-21 assume !(0 != activate_threads_~tmp___1~0); 217790#L761-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 217789#L351-21 assume !(1 == ~t3_pc~0); 217787#L351-23 is_transmit3_triggered_~__retres1~3 := 0; 217786#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 217785#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 217784#L769-21 assume !(0 != activate_threads_~tmp___2~0); 217783#L769-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 217782#L370-21 assume !(1 == ~t4_pc~0); 217781#L370-23 is_transmit4_triggered_~__retres1~4 := 0; 217780#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 217779#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 217778#L777-21 assume !(0 != activate_threads_~tmp___3~0); 217777#L777-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 200983#L389-21 assume 1 == ~t5_pc~0; 200984#L390-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 200937#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 201024#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 201037#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 201038#L785-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 201047#L669-3 assume !(1 == ~M_E~0); 201994#L669-5 assume !(1 == ~T1_E~0); 217768#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 217767#L679-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 217766#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 217765#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 217764#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 217763#L699-3 assume !(1 == ~E_1~0); 217762#L704-3 assume !(1 == ~E_2~0); 217761#L709-3 assume !(1 == ~E_3~0); 217760#L714-3 assume !(1 == ~E_4~0); 217759#L719-3 assume 1 == ~E_5~0;~E_5~0 := 2; 217758#L724-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 217757#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 217528#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 217755#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 217753#L949 assume !(0 == start_simulation_~tmp~3); 217751#L949-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 217263#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 214764#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 214760#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 214758#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 214756#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 214754#L912 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 214753#L962 assume !(0 != start_simulation_~tmp___0~1); 214748#L930-3 assume true; 204548#L930-1 [2018-11-18 15:17:57,717 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:57,717 INFO L82 PathProgramCache]: Analyzing trace with hash 959436202, now seen corresponding path program 2 times [2018-11-18 15:17:57,717 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:57,717 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:57,718 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:57,718 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:57,718 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:57,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:17:57,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:17:57,733 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:57,733 INFO L82 PathProgramCache]: Analyzing trace with hash 1903507288, now seen corresponding path program 1 times [2018-11-18 15:17:57,733 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:57,733 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:57,734 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:57,734 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:17:57,734 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:57,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:57,772 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:17:57,772 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:17:57,772 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:17:57,772 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:17:57,772 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:17:57,773 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:17:57,773 INFO L87 Difference]: Start difference. First operand 17393 states and 22693 transitions. cyclomatic complexity: 5312 Second operand 5 states. [2018-11-18 15:17:57,985 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:17:57,985 INFO L93 Difference]: Finished difference Result 39794 states and 52238 transitions. [2018-11-18 15:17:57,985 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 15:17:57,986 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39794 states and 52238 transitions. [2018-11-18 15:17:58,064 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 26688 [2018-11-18 15:17:58,113 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39794 states to 39794 states and 52238 transitions. [2018-11-18 15:17:58,113 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 26994 [2018-11-18 15:17:58,123 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26994 [2018-11-18 15:17:58,124 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39794 states and 52238 transitions. [2018-11-18 15:17:58,124 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-18 15:17:58,124 INFO L705 BuchiCegarLoop]: Abstraction has 39794 states and 52238 transitions. [2018-11-18 15:17:58,137 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39794 states and 52238 transitions. [2018-11-18 15:17:58,253 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39794 to 18164. [2018-11-18 15:17:58,253 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18164 states. [2018-11-18 15:17:58,268 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18164 states to 18164 states and 23464 transitions. [2018-11-18 15:17:58,268 INFO L728 BuchiCegarLoop]: Abstraction has 18164 states and 23464 transitions. [2018-11-18 15:17:58,268 INFO L608 BuchiCegarLoop]: Abstraction has 18164 states and 23464 transitions. [2018-11-18 15:17:58,268 INFO L442 BuchiCegarLoop]: ======== Iteration 23============ [2018-11-18 15:17:58,268 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18164 states and 23464 transitions. [2018-11-18 15:17:58,295 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 12232 [2018-11-18 15:17:58,295 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:17:58,295 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:17:58,297 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:58,297 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:58,297 INFO L794 eck$LassoCheckResult]: Stem: 259140#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 258957#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 258726#L893 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 258649#L409 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 258650#L416 assume 1 == ~m_i~0;~m_st~0 := 0; 259075#L416-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 258799#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 258800#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 258651#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 258652#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 258737#L441-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 258738#L601 assume !(0 == ~M_E~0); 259313#L601-2 assume !(0 == ~T1_E~0); 258743#L606-1 assume !(0 == ~T2_E~0); 258451#L611-1 assume !(0 == ~T3_E~0); 258452#L616-1 assume !(0 == ~T4_E~0); 258151#L621-1 assume !(0 == ~T5_E~0); 258152#L626-1 assume !(0 == ~E_M~0); 258362#L631-1 assume !(0 == ~E_1~0); 258363#L636-1 assume !(0 == ~E_2~0); 258855#L641-1 assume !(0 == ~E_3~0); 258856#L646-1 assume !(0 == ~E_4~0); 258720#L651-1 assume !(0 == ~E_5~0); 258721#L656-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 259337#L294 assume !(1 == ~m_pc~0); 259056#L294-2 is_master_triggered_~__retres1~0 := 0; 259486#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 259082#L306 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 259083#L745 assume !(0 != activate_threads_~tmp~1); 259504#L745-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 258559#L313 assume !(1 == ~t1_pc~0); 258560#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 258554#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 258437#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 258182#L753 assume !(0 != activate_threads_~tmp___0~0); 258183#L753-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 258194#L332 assume !(1 == ~t2_pc~0); 258666#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 258663#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 258664#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 258713#L761 assume !(0 != activate_threads_~tmp___1~0); 258714#L761-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 258715#L351 assume !(1 == ~t3_pc~0); 258967#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 258968#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 259012#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 259025#L769 assume !(0 != activate_threads_~tmp___2~0); 259026#L769-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 259029#L370 assume !(1 == ~t4_pc~0); 259293#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 259286#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 259287#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 259332#L777 assume !(0 != activate_threads_~tmp___3~0); 259333#L777-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 258342#L389 assume !(1 == ~t5_pc~0); 258269#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 258270#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 258335#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 258384#L785 assume !(0 != activate_threads_~tmp___4~0); 258385#L785-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 258389#L669 assume !(1 == ~M_E~0); 259365#L669-2 assume !(1 == ~T1_E~0); 258853#L674-1 assume !(1 == ~T2_E~0); 258854#L679-1 assume !(1 == ~T3_E~0); 258718#L684-1 assume !(1 == ~T4_E~0); 258719#L689-1 assume !(1 == ~T5_E~0); 259117#L694-1 assume !(1 == ~E_M~0); 258494#L699-1 assume !(1 == ~E_1~0); 258495#L704-1 assume !(1 == ~E_2~0); 258131#L709-1 assume !(1 == ~E_3~0); 258132#L714-1 assume !(1 == ~E_4~0); 258349#L719-1 assume !(1 == ~E_5~0); 258350#L724-1 assume { :end_inline_reset_delta_events } true; 259364#L930-3 assume true; 264330#L930-1 [2018-11-18 15:17:58,297 INFO L796 eck$LassoCheckResult]: Loop: 264330#L930-1 assume !false; 266848#L931 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 266758#L576 assume true; 266601#L496-1 assume !false; 266596#L497 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 266522#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 266520#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 266516#L487 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 266511#L501 assume 0 != eval_~tmp~0; 266509#L501-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 265819#L509 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1;assume { :begin_inline_master } true;havoc master_#t~nondet0, master_#t~nondet1, master_~tmp_var~0;master_~tmp_var~0 := master_#t~nondet0;havoc master_#t~nondet0; 264918#L58 assume 0 == ~m_pc~0; 264917#L94 assume true; 264900#L69 assume !false; 264744#L70 ~token~0 := master_#t~nondet1;havoc master_#t~nondet1;~local~0 := ~token~0;~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 264745#L294-3 assume 1 == ~m_pc~0; 264737#L295-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 264738#L305-1 is_master_triggered_#res := is_master_triggered_~__retres1~0; 264730#L306-1 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 264731#L745-3 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 259491#L745-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 258582#L313-3 assume !(1 == ~t1_pc~0); 258583#L313-5 is_transmit1_triggered_~__retres1~1 := 0; 266025#L324-1 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 266024#L325-1 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 266023#L753-3 assume !(0 != activate_threads_~tmp___0~0); 266022#L753-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 266021#L332-3 assume !(1 == ~t2_pc~0); 266019#L332-5 is_transmit2_triggered_~__retres1~2 := 0; 266018#L343-1 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 266017#L344-1 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 266016#L761-3 assume !(0 != activate_threads_~tmp___1~0); 266015#L761-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 266014#L351-3 assume !(1 == ~t3_pc~0); 266012#L351-5 is_transmit3_triggered_~__retres1~3 := 0; 266011#L362-1 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 266010#L363-1 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 266009#L769-3 assume !(0 != activate_threads_~tmp___2~0); 266008#L769-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 266007#L370-3 assume !(1 == ~t4_pc~0); 266006#L370-5 is_transmit4_triggered_~__retres1~4 := 0; 266005#L381-1 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 266004#L382-1 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 266003#L777-3 assume !(0 != activate_threads_~tmp___3~0); 266002#L777-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 266001#L389-3 assume !(1 == ~t5_pc~0); 266000#L389-5 is_transmit5_triggered_~__retres1~5 := 0; 265998#L400-1 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 265996#L401-1 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 265994#L785-3 assume !(0 != activate_threads_~tmp___4~0); 265988#L785-5 assume { :end_inline_activate_threads } true; 265984#L802 assume { :end_inline_immediate_notify } true;~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 265817#L103 assume { :end_inline_master } true; 265804#L506 assume !(0 == ~t1_st~0); 265796#L520 assume !(0 == ~t2_st~0); 265740#L534 assume !(0 == ~t3_st~0); 265736#L548 assume !(0 == ~t4_st~0); 266999#L562 assume !(0 == ~t5_st~0); 267152#L576 assume true; 267151#L496-1 assume !false; 267150#L497 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 267149#L454 assume !(0 == ~m_st~0); 267097#L458 assume !(0 == ~t1_st~0); 267092#L462 assume !(0 == ~t2_st~0); 267093#L466 assume !(0 == ~t3_st~0); 267096#L470 assume !(0 == ~t4_st~0); 267094#L474 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 267095#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 267076#L487 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 267077#L501 assume !(0 != eval_~tmp~0); 267361#L591 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 267360#L409-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 267359#L601-3 assume !(0 == ~M_E~0); 267358#L601-5 assume !(0 == ~T1_E~0); 267356#L606-3 assume !(0 == ~T2_E~0); 267354#L611-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 267352#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 267350#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 267348#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 267346#L631-3 assume !(0 == ~E_1~0); 267344#L636-3 assume !(0 == ~E_2~0); 267342#L641-3 assume !(0 == ~E_3~0); 267340#L646-3 assume !(0 == ~E_4~0); 267338#L651-3 assume 0 == ~E_5~0;~E_5~0 := 1; 267147#L656-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 267146#L294-21 assume 1 == ~m_pc~0; 267144#L295-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 267143#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 267142#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 267140#L745-21 assume !(0 != activate_threads_~tmp~1); 267141#L745-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 267411#L313-21 assume !(1 == ~t1_pc~0); 267410#L313-23 is_transmit1_triggered_~__retres1~1 := 0; 267409#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 267408#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 267407#L753-21 assume !(0 != activate_threads_~tmp___0~0); 267406#L753-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 267405#L332-21 assume !(1 == ~t2_pc~0); 267403#L332-23 is_transmit2_triggered_~__retres1~2 := 0; 267402#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 267401#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 267400#L761-21 assume !(0 != activate_threads_~tmp___1~0); 267399#L761-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 267398#L351-21 assume !(1 == ~t3_pc~0); 267396#L351-23 is_transmit3_triggered_~__retres1~3 := 0; 267395#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 267394#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 267393#L769-21 assume !(0 != activate_threads_~tmp___2~0); 267392#L769-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 267391#L370-21 assume !(1 == ~t4_pc~0); 267390#L370-23 is_transmit4_triggered_~__retres1~4 := 0; 267389#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 267388#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 267387#L777-21 assume !(0 != activate_threads_~tmp___3~0); 267386#L777-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 267385#L389-21 assume 1 == ~t5_pc~0; 267383#L390-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 267381#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 267379#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 267377#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 267372#L785-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 267370#L669-3 assume !(1 == ~M_E~0); 266842#L669-5 assume !(1 == ~T1_E~0); 267363#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 267362#L679-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 267148#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 267102#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 267089#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 267086#L699-3 assume !(1 == ~E_1~0); 267084#L704-3 assume !(1 == ~E_2~0); 267081#L709-3 assume !(1 == ~E_3~0); 267079#L714-3 assume !(1 == ~E_4~0); 265118#L719-3 assume 1 == ~E_5~0;~E_5~0 := 2; 265115#L724-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 265103#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 265099#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 266997#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 266995#L949 assume !(0 == start_simulation_~tmp~3); 266996#L949-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 267197#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 267188#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 267180#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 267174#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 267168#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 267162#L912 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 267160#L962 assume !(0 != start_simulation_~tmp___0~1); 267071#L930-3 assume true; 264330#L930-1 [2018-11-18 15:17:58,298 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:58,298 INFO L82 PathProgramCache]: Analyzing trace with hash 959436202, now seen corresponding path program 3 times [2018-11-18 15:17:58,298 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:58,298 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:58,298 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:58,298 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:58,299 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:58,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:17:58,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:17:58,314 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:58,314 INFO L82 PathProgramCache]: Analyzing trace with hash 1639354615, now seen corresponding path program 1 times [2018-11-18 15:17:58,314 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:58,314 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:58,315 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:58,315 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:17:58,315 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:58,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:58,342 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:17:58,342 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:17:58,342 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:17:58,342 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:17:58,343 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:17:58,343 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:17:58,343 INFO L87 Difference]: Start difference. First operand 18164 states and 23464 transitions. cyclomatic complexity: 5312 Second operand 3 states. [2018-11-18 15:17:58,408 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:17:58,408 INFO L93 Difference]: Finished difference Result 21845 states and 27886 transitions. [2018-11-18 15:17:58,410 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:17:58,411 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21845 states and 27886 transitions. [2018-11-18 15:17:58,451 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14724 [2018-11-18 15:17:58,480 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21845 states to 21845 states and 27886 transitions. [2018-11-18 15:17:58,481 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14894 [2018-11-18 15:17:58,486 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14894 [2018-11-18 15:17:58,487 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21845 states and 27886 transitions. [2018-11-18 15:17:58,488 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-18 15:17:58,488 INFO L705 BuchiCegarLoop]: Abstraction has 21845 states and 27886 transitions. [2018-11-18 15:17:58,497 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21845 states and 27886 transitions. [2018-11-18 15:17:58,573 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21845 to 20741. [2018-11-18 15:17:58,573 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20741 states. [2018-11-18 15:17:58,589 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20741 states to 20741 states and 26590 transitions. [2018-11-18 15:17:58,589 INFO L728 BuchiCegarLoop]: Abstraction has 20741 states and 26590 transitions. [2018-11-18 15:17:58,589 INFO L608 BuchiCegarLoop]: Abstraction has 20741 states and 26590 transitions. [2018-11-18 15:17:58,589 INFO L442 BuchiCegarLoop]: ======== Iteration 24============ [2018-11-18 15:17:58,589 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20741 states and 26590 transitions. [2018-11-18 15:17:58,618 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 13988 [2018-11-18 15:17:58,618 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:17:58,618 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:17:58,619 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:58,619 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:58,619 INFO L794 eck$LassoCheckResult]: Stem: 299096#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 298912#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 298690#L893 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 298615#L409 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 298616#L416 assume 1 == ~m_i~0;~m_st~0 := 0; 299033#L416-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 298763#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 298764#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 298621#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 298622#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 298701#L441-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 298702#L601 assume !(0 == ~M_E~0); 299252#L601-2 assume !(0 == ~T1_E~0); 298708#L606-1 assume !(0 == ~T2_E~0); 298450#L611-1 assume !(0 == ~T3_E~0); 298451#L616-1 assume !(0 == ~T4_E~0); 298168#L621-1 assume !(0 == ~T5_E~0); 298169#L626-1 assume !(0 == ~E_M~0); 298357#L631-1 assume !(0 == ~E_1~0); 298358#L636-1 assume !(0 == ~E_2~0); 298813#L641-1 assume !(0 == ~E_3~0); 298814#L646-1 assume !(0 == ~E_4~0); 298684#L651-1 assume !(0 == ~E_5~0); 298685#L656-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 299270#L294 assume !(1 == ~m_pc~0); 299332#L294-2 is_master_triggered_~__retres1~0 := 0; 299377#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 299046#L306 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 299047#L745 assume !(0 != activate_threads_~tmp~1); 299403#L745-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 298544#L313 assume !(1 == ~t1_pc~0); 298545#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 298543#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 298437#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 298198#L753 assume !(0 != activate_threads_~tmp___0~0); 298199#L753-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 298204#L332 assume !(1 == ~t2_pc~0); 298632#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 298629#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 298630#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 298677#L761 assume !(0 != activate_threads_~tmp___1~0); 298678#L761-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 298679#L351 assume !(1 == ~t3_pc~0); 298922#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 298923#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 298965#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 298987#L769 assume !(0 != activate_threads_~tmp___2~0); 298988#L769-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 298990#L370 assume !(1 == ~t4_pc~0); 299235#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 299229#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 299230#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 299266#L777 assume !(0 != activate_threads_~tmp___3~0); 299267#L777-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 298341#L389 assume !(1 == ~t5_pc~0); 298276#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 298277#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 298332#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 298379#L785 assume !(0 != activate_threads_~tmp___4~0); 298380#L785-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 298385#L669 assume !(1 == ~M_E~0); 299291#L669-2 assume !(1 == ~T1_E~0); 298811#L674-1 assume !(1 == ~T2_E~0); 298812#L679-1 assume !(1 == ~T3_E~0); 298682#L684-1 assume !(1 == ~T4_E~0); 298683#L689-1 assume !(1 == ~T5_E~0); 299075#L694-1 assume !(1 == ~E_M~0); 298492#L699-1 assume !(1 == ~E_1~0); 298493#L704-1 assume !(1 == ~E_2~0); 298146#L709-1 assume !(1 == ~E_3~0); 298147#L714-1 assume !(1 == ~E_4~0); 298349#L719-1 assume !(1 == ~E_5~0); 298350#L724-1 assume { :end_inline_reset_delta_events } true; 299290#L930-3 assume true; 303080#L930-1 assume !false; 306624#L931 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 306619#L576 [2018-11-18 15:17:58,619 INFO L796 eck$LassoCheckResult]: Loop: 306619#L576 assume true; 306617#L496-1 assume !false; 306615#L497 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 306613#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 306610#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 306608#L487 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 306606#L501 assume 0 != eval_~tmp~0; 306603#L501-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 306600#L509 assume !(0 != eval_~tmp_ndt_1~0); 306601#L506 assume !(0 == ~t1_st~0); 306641#L520 assume !(0 == ~t2_st~0); 306636#L534 assume !(0 == ~t3_st~0); 306628#L548 assume !(0 == ~t4_st~0); 306625#L562 assume !(0 == ~t5_st~0); 306619#L576 [2018-11-18 15:17:58,619 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:58,619 INFO L82 PathProgramCache]: Analyzing trace with hash -1399767604, now seen corresponding path program 1 times [2018-11-18 15:17:58,619 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:58,619 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:58,620 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:58,620 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:58,620 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:58,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:17:58,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:17:58,637 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:58,637 INFO L82 PathProgramCache]: Analyzing trace with hash 1952412727, now seen corresponding path program 1 times [2018-11-18 15:17:58,637 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:58,637 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:58,638 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:58,638 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:58,638 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:58,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:17:58,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:17:58,642 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:58,642 INFO L82 PathProgramCache]: Analyzing trace with hash -662752574, now seen corresponding path program 1 times [2018-11-18 15:17:58,642 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:58,642 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:58,642 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:58,642 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:58,643 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:58,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:58,685 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:17:58,685 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:17:58,685 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:17:58,762 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:17:58,762 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:17:58,762 INFO L87 Difference]: Start difference. First operand 20741 states and 26590 transitions. cyclomatic complexity: 5873 Second operand 3 states. [2018-11-18 15:17:58,812 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:17:58,813 INFO L93 Difference]: Finished difference Result 35836 states and 45502 transitions. [2018-11-18 15:17:58,813 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:17:58,813 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35836 states and 45502 transitions. [2018-11-18 15:17:58,875 INFO L131 ngComponentsAnalysis]: Automaton has 28 accepting balls. 23512 [2018-11-18 15:17:58,927 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35836 states to 35836 states and 45502 transitions. [2018-11-18 15:17:58,927 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24566 [2018-11-18 15:17:58,937 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24566 [2018-11-18 15:17:58,937 INFO L73 IsDeterministic]: Start isDeterministic. Operand 35836 states and 45502 transitions. [2018-11-18 15:17:58,938 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-18 15:17:58,938 INFO L705 BuchiCegarLoop]: Abstraction has 35836 states and 45502 transitions. [2018-11-18 15:17:58,953 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35836 states and 45502 transitions. [2018-11-18 15:17:59,235 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35836 to 35836. [2018-11-18 15:17:59,235 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 35836 states. [2018-11-18 15:17:59,261 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35836 states to 35836 states and 45502 transitions. [2018-11-18 15:17:59,261 INFO L728 BuchiCegarLoop]: Abstraction has 35836 states and 45502 transitions. [2018-11-18 15:17:59,261 INFO L608 BuchiCegarLoop]: Abstraction has 35836 states and 45502 transitions. [2018-11-18 15:17:59,262 INFO L442 BuchiCegarLoop]: ======== Iteration 25============ [2018-11-18 15:17:59,262 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35836 states and 45502 transitions. [2018-11-18 15:17:59,308 INFO L131 ngComponentsAnalysis]: Automaton has 28 accepting balls. 23512 [2018-11-18 15:17:59,308 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:17:59,309 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:17:59,309 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:59,309 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:59,309 INFO L794 eck$LassoCheckResult]: Stem: 355656#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 355483#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 355271#L893 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 355195#L409 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 355196#L416 assume 1 == ~m_i~0;~m_st~0 := 0; 355595#L416-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 355344#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 355345#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 355201#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 355202#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 355284#L441-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 355285#L601 assume !(0 == ~M_E~0); 355801#L601-2 assume !(0 == ~T1_E~0); 355288#L606-1 assume !(0 == ~T2_E~0); 355033#L611-1 assume !(0 == ~T3_E~0); 355034#L616-1 assume !(0 == ~T4_E~0); 354753#L621-1 assume !(0 == ~T5_E~0); 354754#L626-1 assume !(0 == ~E_M~0); 354940#L631-1 assume !(0 == ~E_1~0); 354941#L636-1 assume !(0 == ~E_2~0); 355390#L641-1 assume !(0 == ~E_3~0); 355391#L646-1 assume !(0 == ~E_4~0); 355265#L651-1 assume !(0 == ~E_5~0); 355266#L656-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 355824#L294 assume !(1 == ~m_pc~0); 355887#L294-2 is_master_triggered_~__retres1~0 := 0; 355932#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 355609#L306 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 355610#L745 assume !(0 != activate_threads_~tmp~1); 355954#L745-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 355132#L313 assume !(1 == ~t1_pc~0); 355133#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 355131#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 355021#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 354783#L753 assume !(0 != activate_threads_~tmp___0~0); 354784#L753-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 354790#L332 assume !(1 == ~t2_pc~0); 355212#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 355209#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 355210#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 355346#L761 assume !(0 != activate_threads_~tmp___1~0); 357023#L761-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 357022#L351 assume !(1 == ~t3_pc~0); 357020#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 357019#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 357018#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 357017#L769 assume !(0 != activate_threads_~tmp___2~0); 357016#L769-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 357015#L370 assume !(1 == ~t4_pc~0); 357014#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 357013#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 357012#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 357011#L777 assume !(0 != activate_threads_~tmp___3~0); 357010#L777-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 357009#L389 assume !(1 == ~t5_pc~0); 357006#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 357005#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 357003#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 357001#L785 assume !(0 != activate_threads_~tmp___4~0); 356998#L785-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 356996#L669 assume !(1 == ~M_E~0); 356994#L669-2 assume !(1 == ~T1_E~0); 356992#L674-1 assume !(1 == ~T2_E~0); 356990#L679-1 assume !(1 == ~T3_E~0); 356988#L684-1 assume !(1 == ~T4_E~0); 355823#L689-1 assume !(1 == ~T5_E~0); 355638#L694-1 assume !(1 == ~E_M~0); 355074#L699-1 assume !(1 == ~E_1~0); 355075#L704-1 assume !(1 == ~E_2~0); 354731#L709-1 assume !(1 == ~E_3~0); 354732#L714-1 assume !(1 == ~E_4~0); 355535#L719-1 assume !(1 == ~E_5~0); 356777#L724-1 assume { :end_inline_reset_delta_events } true; 356744#L930-3 assume true; 356745#L930-1 assume !false; 367801#L931 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 367802#L576 [2018-11-18 15:17:59,309 INFO L796 eck$LassoCheckResult]: Loop: 367802#L576 assume true; 373153#L496-1 assume !false; 373151#L497 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 373149#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 373147#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 367778#L487 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 367779#L501 assume 0 != eval_~tmp~0; 367771#L501-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 367765#L509 assume !(0 != eval_~tmp_ndt_1~0); 367767#L506 assume !(0 == ~t1_st~0); 368131#L520 assume !(0 == ~t2_st~0); 367828#L534 assume !(0 == ~t3_st~0); 367825#L548 assume !(0 == ~t4_st~0); 368145#L562 assume !(0 == ~t5_st~0); 367802#L576 [2018-11-18 15:17:59,310 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:59,310 INFO L82 PathProgramCache]: Analyzing trace with hash 1927849038, now seen corresponding path program 1 times [2018-11-18 15:17:59,310 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:59,310 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:59,310 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:59,310 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:59,310 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:59,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:59,348 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:17:59,348 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:17:59,348 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:17:59,348 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:17:59,348 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:59,348 INFO L82 PathProgramCache]: Analyzing trace with hash 1952412727, now seen corresponding path program 2 times [2018-11-18 15:17:59,348 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:59,348 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:59,349 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:59,349 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:59,349 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:59,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:17:59,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:17:59,392 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:17:59,392 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:17:59,392 INFO L87 Difference]: Start difference. First operand 35836 states and 45502 transitions. cyclomatic complexity: 9708 Second operand 3 states. [2018-11-18 15:17:59,421 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:17:59,421 INFO L93 Difference]: Finished difference Result 22660 states and 28722 transitions. [2018-11-18 15:17:59,422 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:17:59,422 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22660 states and 28722 transitions. [2018-11-18 15:17:59,459 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 15376 [2018-11-18 15:17:59,483 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22660 states to 22660 states and 28722 transitions. [2018-11-18 15:17:59,483 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15546 [2018-11-18 15:17:59,488 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15546 [2018-11-18 15:17:59,488 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22660 states and 28722 transitions. [2018-11-18 15:17:59,491 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-18 15:17:59,491 INFO L705 BuchiCegarLoop]: Abstraction has 22660 states and 28722 transitions. [2018-11-18 15:17:59,501 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22660 states and 28722 transitions. [2018-11-18 15:17:59,594 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22660 to 22660. [2018-11-18 15:17:59,594 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22660 states. [2018-11-18 15:17:59,610 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22660 states to 22660 states and 28722 transitions. [2018-11-18 15:17:59,610 INFO L728 BuchiCegarLoop]: Abstraction has 22660 states and 28722 transitions. [2018-11-18 15:17:59,610 INFO L608 BuchiCegarLoop]: Abstraction has 22660 states and 28722 transitions. [2018-11-18 15:17:59,610 INFO L442 BuchiCegarLoop]: ======== Iteration 26============ [2018-11-18 15:17:59,610 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22660 states and 28722 transitions. [2018-11-18 15:17:59,639 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 15376 [2018-11-18 15:17:59,639 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:17:59,639 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:17:59,640 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:59,640 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:17:59,640 INFO L794 eck$LassoCheckResult]: Stem: 414154#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 413982#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 413765#L893 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 413689#L409 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 413690#L416 assume 1 == ~m_i~0;~m_st~0 := 0; 414095#L416-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 413841#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 413842#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 413695#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 413696#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 413778#L441-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 413779#L601 assume !(0 == ~M_E~0); 414299#L601-2 assume !(0 == ~T1_E~0); 413782#L606-1 assume !(0 == ~T2_E~0); 413536#L611-1 assume !(0 == ~T3_E~0); 413537#L616-1 assume !(0 == ~T4_E~0); 413255#L621-1 assume !(0 == ~T5_E~0); 413256#L626-1 assume !(0 == ~E_M~0); 413444#L631-1 assume !(0 == ~E_1~0); 413445#L636-1 assume !(0 == ~E_2~0); 413887#L641-1 assume !(0 == ~E_3~0); 413888#L646-1 assume !(0 == ~E_4~0); 413759#L651-1 assume !(0 == ~E_5~0); 413760#L656-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 414318#L294 assume !(1 == ~m_pc~0); 414389#L294-2 is_master_triggered_~__retres1~0 := 0; 414430#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 414108#L306 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 414109#L745 assume !(0 != activate_threads_~tmp~1); 414462#L745-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 413636#L313 assume !(1 == ~t1_pc~0); 413637#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 413635#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 413523#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 413284#L753 assume !(0 != activate_threads_~tmp___0~0); 413285#L753-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 413291#L332 assume !(1 == ~t2_pc~0); 413706#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 413703#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 413704#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 413752#L761 assume !(0 != activate_threads_~tmp___1~0); 413753#L761-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 413754#L351 assume !(1 == ~t3_pc~0); 413991#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 413992#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 414033#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 414049#L769 assume !(0 != activate_threads_~tmp___2~0); 414050#L769-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 414051#L370 assume !(1 == ~t4_pc~0); 414284#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 414280#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 414281#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 414314#L777 assume !(0 != activate_threads_~tmp___3~0); 414315#L777-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 413427#L389 assume !(1 == ~t5_pc~0); 413362#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 413363#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 413425#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 413466#L785 assume !(0 != activate_threads_~tmp___4~0); 413467#L785-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 413472#L669 assume !(1 == ~M_E~0); 414344#L669-2 assume !(1 == ~T1_E~0); 413885#L674-1 assume !(1 == ~T2_E~0); 413886#L679-1 assume !(1 == ~T3_E~0); 413757#L684-1 assume !(1 == ~T4_E~0); 413758#L689-1 assume !(1 == ~T5_E~0); 414137#L694-1 assume !(1 == ~E_M~0); 413580#L699-1 assume !(1 == ~E_1~0); 413581#L704-1 assume !(1 == ~E_2~0); 413233#L709-1 assume !(1 == ~E_3~0); 413234#L714-1 assume !(1 == ~E_4~0); 413436#L719-1 assume !(1 == ~E_5~0); 413437#L724-1 assume { :end_inline_reset_delta_events } true; 414343#L930-3 assume true; 419123#L930-1 assume !false; 428851#L931 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 428846#L576 [2018-11-18 15:17:59,640 INFO L796 eck$LassoCheckResult]: Loop: 428846#L576 assume true; 428844#L496-1 assume !false; 428842#L497 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 428839#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 428837#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 428833#L487 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 428831#L501 assume 0 != eval_~tmp~0; 428829#L501-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 428826#L509 assume !(0 != eval_~tmp_ndt_1~0); 428825#L506 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 428823#L523 assume !(0 != eval_~tmp_ndt_2~0); 428822#L520 assume !(0 == ~t2_st~0); 428817#L534 assume !(0 == ~t3_st~0); 428816#L548 assume !(0 == ~t4_st~0); 428852#L562 assume !(0 == ~t5_st~0); 428846#L576 [2018-11-18 15:17:59,640 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:59,641 INFO L82 PathProgramCache]: Analyzing trace with hash -1399767604, now seen corresponding path program 2 times [2018-11-18 15:17:59,641 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:59,641 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:59,641 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:59,641 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:17:59,641 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:59,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:17:59,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:17:59,658 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:59,658 INFO L82 PathProgramCache]: Analyzing trace with hash -582221552, now seen corresponding path program 1 times [2018-11-18 15:17:59,659 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:59,659 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:59,659 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:59,659 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:17:59,659 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:59,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:17:59,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:17:59,663 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:17:59,663 INFO L82 PathProgramCache]: Analyzing trace with hash -47967259, now seen corresponding path program 1 times [2018-11-18 15:17:59,663 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:17:59,663 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:17:59,664 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:59,664 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:17:59,664 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:17:59,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:17:59,705 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:17:59,705 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:17:59,705 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:17:59,746 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:17:59,746 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:17:59,746 INFO L87 Difference]: Start difference. First operand 22660 states and 28722 transitions. cyclomatic complexity: 6086 Second operand 3 states. [2018-11-18 15:17:59,811 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:17:59,811 INFO L93 Difference]: Finished difference Result 37656 states and 47563 transitions. [2018-11-18 15:17:59,812 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:17:59,812 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37656 states and 47563 transitions. [2018-11-18 15:17:59,882 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 25712 [2018-11-18 15:17:59,929 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37656 states to 37656 states and 47563 transitions. [2018-11-18 15:17:59,929 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25970 [2018-11-18 15:17:59,939 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25970 [2018-11-18 15:17:59,939 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37656 states and 47563 transitions. [2018-11-18 15:17:59,940 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-18 15:17:59,940 INFO L705 BuchiCegarLoop]: Abstraction has 37656 states and 47563 transitions. [2018-11-18 15:17:59,953 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37656 states and 47563 transitions. [2018-11-18 15:18:00,076 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37656 to 37656. [2018-11-18 15:18:00,076 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37656 states. [2018-11-18 15:18:00,105 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37656 states to 37656 states and 47563 transitions. [2018-11-18 15:18:00,105 INFO L728 BuchiCegarLoop]: Abstraction has 37656 states and 47563 transitions. [2018-11-18 15:18:00,105 INFO L608 BuchiCegarLoop]: Abstraction has 37656 states and 47563 transitions. [2018-11-18 15:18:00,105 INFO L442 BuchiCegarLoop]: ======== Iteration 27============ [2018-11-18 15:18:00,105 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37656 states and 47563 transitions. [2018-11-18 15:18:00,157 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 25712 [2018-11-18 15:18:00,157 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:18:00,157 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:18:00,158 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:18:00,158 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:18:00,158 INFO L794 eck$LassoCheckResult]: Stem: 474484#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 474308#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 474088#L893 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 474012#L409 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 474013#L416 assume 1 == ~m_i~0;~m_st~0 := 0; 474423#L416-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 474166#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 474167#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 474018#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 474019#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 474101#L441-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 474102#L601 assume !(0 == ~M_E~0); 474633#L601-2 assume !(0 == ~T1_E~0); 474105#L606-1 assume !(0 == ~T2_E~0); 473859#L611-1 assume !(0 == ~T3_E~0); 473860#L616-1 assume !(0 == ~T4_E~0); 473579#L621-1 assume !(0 == ~T5_E~0); 473580#L626-1 assume !(0 == ~E_M~0); 473766#L631-1 assume !(0 == ~E_1~0); 473767#L636-1 assume !(0 == ~E_2~0); 474213#L641-1 assume !(0 == ~E_3~0); 474214#L646-1 assume !(0 == ~E_4~0); 474082#L651-1 assume !(0 == ~E_5~0); 474083#L656-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 474656#L294 assume !(1 == ~m_pc~0); 474735#L294-2 is_master_triggered_~__retres1~0 := 0; 474777#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 474436#L306 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 474437#L745 assume !(0 != activate_threads_~tmp~1); 474800#L745-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 473954#L313 assume !(1 == ~t1_pc~0); 473955#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 473953#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 473846#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 473608#L753 assume !(0 != activate_threads_~tmp___0~0); 473609#L753-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 473615#L332 assume !(1 == ~t2_pc~0); 474029#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 474026#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 474027#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 474075#L761 assume !(0 != activate_threads_~tmp___1~0); 474076#L761-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 474077#L351 assume !(1 == ~t3_pc~0); 474317#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 474318#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 474359#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 474378#L769 assume !(0 != activate_threads_~tmp___2~0); 474379#L769-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 474380#L370 assume !(1 == ~t4_pc~0); 474620#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 474616#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 474617#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 474652#L777 assume !(0 != activate_threads_~tmp___3~0); 474653#L777-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 473750#L389 assume !(1 == ~t5_pc~0); 473684#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 473685#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 473748#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 473789#L785 assume !(0 != activate_threads_~tmp___4~0); 473790#L785-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 473795#L669 assume !(1 == ~M_E~0); 474685#L669-2 assume !(1 == ~T1_E~0); 474211#L674-1 assume !(1 == ~T2_E~0); 474212#L679-1 assume !(1 == ~T3_E~0); 474080#L684-1 assume !(1 == ~T4_E~0); 474081#L689-1 assume !(1 == ~T5_E~0); 474465#L694-1 assume !(1 == ~E_M~0); 473901#L699-1 assume !(1 == ~E_1~0); 473902#L704-1 assume !(1 == ~E_2~0); 473557#L709-1 assume !(1 == ~E_3~0); 473558#L714-1 assume !(1 == ~E_4~0); 473758#L719-1 assume !(1 == ~E_5~0); 473759#L724-1 assume { :end_inline_reset_delta_events } true; 474684#L930-3 assume true; 480751#L930-1 assume !false; 491421#L931 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 491414#L576 [2018-11-18 15:18:00,158 INFO L796 eck$LassoCheckResult]: Loop: 491414#L576 assume true; 491412#L496-1 assume !false; 491410#L497 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 491408#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 491405#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 491403#L487 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 491398#L501 assume 0 != eval_~tmp~0; 491396#L501-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 491393#L509 assume !(0 != eval_~tmp_ndt_1~0); 491394#L506 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 492113#L523 assume !(0 != eval_~tmp_ndt_2~0); 489922#L520 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 489920#L537 assume !(0 != eval_~tmp_ndt_3~0); 489918#L534 assume !(0 == ~t3_st~0); 489912#L548 assume !(0 == ~t4_st~0); 489907#L562 assume !(0 == ~t5_st~0); 491414#L576 [2018-11-18 15:18:00,158 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:18:00,158 INFO L82 PathProgramCache]: Analyzing trace with hash -1399767604, now seen corresponding path program 3 times [2018-11-18 15:18:00,158 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:18:00,159 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:18:00,159 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:18:00,159 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:18:00,159 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:18:00,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:18:00,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:18:00,175 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:18:00,175 INFO L82 PathProgramCache]: Analyzing trace with hash -1039076017, now seen corresponding path program 1 times [2018-11-18 15:18:00,176 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:18:00,176 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:18:00,176 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:18:00,176 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:18:00,176 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:18:00,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:18:00,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:18:00,179 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:18:00,180 INFO L82 PathProgramCache]: Analyzing trace with hash -1657062118, now seen corresponding path program 1 times [2018-11-18 15:18:00,180 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:18:00,180 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:18:00,180 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:18:00,180 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:18:00,180 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:18:00,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:18:00,213 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:18:00,213 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:18:00,213 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:18:00,268 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:18:00,268 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:18:00,268 INFO L87 Difference]: Start difference. First operand 37656 states and 47563 transitions. cyclomatic complexity: 9931 Second operand 3 states. [2018-11-18 15:18:00,552 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:18:00,553 INFO L93 Difference]: Finished difference Result 67484 states and 84808 transitions. [2018-11-18 15:18:00,555 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:18:00,555 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 67484 states and 84808 transitions. [2018-11-18 15:18:00,699 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 45416 [2018-11-18 15:18:00,776 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 67484 states to 67484 states and 84808 transitions. [2018-11-18 15:18:00,776 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 45850 [2018-11-18 15:18:00,791 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 45850 [2018-11-18 15:18:00,792 INFO L73 IsDeterministic]: Start isDeterministic. Operand 67484 states and 84808 transitions. [2018-11-18 15:18:00,795 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-18 15:18:00,795 INFO L705 BuchiCegarLoop]: Abstraction has 67484 states and 84808 transitions. [2018-11-18 15:18:00,815 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67484 states and 84808 transitions. [2018-11-18 15:18:01,047 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67484 to 67484. [2018-11-18 15:18:01,047 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 67484 states. [2018-11-18 15:18:01,097 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67484 states to 67484 states and 84808 transitions. [2018-11-18 15:18:01,097 INFO L728 BuchiCegarLoop]: Abstraction has 67484 states and 84808 transitions. [2018-11-18 15:18:01,098 INFO L608 BuchiCegarLoop]: Abstraction has 67484 states and 84808 transitions. [2018-11-18 15:18:01,098 INFO L442 BuchiCegarLoop]: ======== Iteration 28============ [2018-11-18 15:18:01,098 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 67484 states and 84808 transitions. [2018-11-18 15:18:01,190 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 45416 [2018-11-18 15:18:01,190 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:18:01,190 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:18:01,191 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:18:01,191 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:18:01,191 INFO L794 eck$LassoCheckResult]: Stem: 579649#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 579474#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 579231#L893 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 579155#L409 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 579156#L416 assume 1 == ~m_i~0;~m_st~0 := 0; 579590#L416-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 579316#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 579317#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 579161#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 579162#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 579247#L441-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 579248#L601 assume !(0 == ~M_E~0); 579802#L601-2 assume !(0 == ~T1_E~0); 579251#L606-1 assume !(0 == ~T2_E~0); 579006#L611-1 assume !(0 == ~T3_E~0); 579007#L616-1 assume !(0 == ~T4_E~0); 578728#L621-1 assume !(0 == ~T5_E~0); 578729#L626-1 assume !(0 == ~E_M~0); 578913#L631-1 assume !(0 == ~E_1~0); 578914#L636-1 assume !(0 == ~E_2~0); 579365#L641-1 assume !(0 == ~E_3~0); 579366#L646-1 assume !(0 == ~E_4~0); 579225#L651-1 assume !(0 == ~E_5~0); 579226#L656-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 579823#L294 assume !(1 == ~m_pc~0); 579889#L294-2 is_master_triggered_~__retres1~0 := 0; 579927#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 579603#L306 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 579604#L745 assume !(0 != activate_threads_~tmp~1); 579948#L745-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 579097#L313 assume !(1 == ~t1_pc~0); 579098#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 579096#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 578993#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 578757#L753 assume !(0 != activate_threads_~tmp___0~0); 578758#L753-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 578763#L332 assume !(1 == ~t2_pc~0); 579172#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 579169#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 579170#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 579218#L761 assume !(0 != activate_threads_~tmp___1~0); 579219#L761-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 579220#L351 assume !(1 == ~t3_pc~0); 579483#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 579484#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 579528#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 579545#L769 assume !(0 != activate_threads_~tmp___2~0); 579546#L769-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 579547#L370 assume !(1 == ~t4_pc~0); 579786#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 579782#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 579783#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 579819#L777 assume !(0 != activate_threads_~tmp___3~0); 579820#L777-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 578897#L389 assume !(1 == ~t5_pc~0); 578833#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 578834#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 578895#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 578936#L785 assume !(0 != activate_threads_~tmp___4~0); 578937#L785-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 578942#L669 assume !(1 == ~M_E~0); 579848#L669-2 assume !(1 == ~T1_E~0); 579363#L674-1 assume !(1 == ~T2_E~0); 579364#L679-1 assume !(1 == ~T3_E~0); 579223#L684-1 assume !(1 == ~T4_E~0); 579224#L689-1 assume !(1 == ~T5_E~0); 579632#L694-1 assume !(1 == ~E_M~0); 579048#L699-1 assume !(1 == ~E_1~0); 579049#L704-1 assume !(1 == ~E_2~0); 578705#L709-1 assume !(1 == ~E_3~0); 578706#L714-1 assume !(1 == ~E_4~0); 578905#L719-1 assume !(1 == ~E_5~0); 578906#L724-1 assume { :end_inline_reset_delta_events } true; 579847#L930-3 assume true; 586308#L930-1 assume !false; 610024#L931 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 610017#L576 [2018-11-18 15:18:01,191 INFO L796 eck$LassoCheckResult]: Loop: 610017#L576 assume true; 610015#L496-1 assume !false; 610013#L497 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 610011#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 610008#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 610006#L487 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 610002#L501 assume 0 != eval_~tmp~0; 610000#L501-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 609997#L509 assume !(0 != eval_~tmp_ndt_1~0); 609995#L506 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 609993#L523 assume !(0 != eval_~tmp_ndt_2~0); 609992#L520 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 609865#L537 assume !(0 != eval_~tmp_ndt_3~0); 609991#L534 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 609735#L551 assume !(0 != eval_~tmp_ndt_4~0); 610027#L548 assume !(0 == ~t4_st~0); 610025#L562 assume !(0 == ~t5_st~0); 610017#L576 [2018-11-18 15:18:01,191 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:18:01,191 INFO L82 PathProgramCache]: Analyzing trace with hash -1399767604, now seen corresponding path program 4 times [2018-11-18 15:18:01,191 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:18:01,191 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:18:01,192 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:18:01,192 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:18:01,192 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:18:01,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:18:01,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:18:01,209 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:18:01,209 INFO L82 PathProgramCache]: Analyzing trace with hash 2142897144, now seen corresponding path program 1 times [2018-11-18 15:18:01,209 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:18:01,209 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:18:01,209 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:18:01,210 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:18:01,210 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:18:01,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:18:01,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:18:01,213 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:18:01,213 INFO L82 PathProgramCache]: Analyzing trace with hash 165197197, now seen corresponding path program 1 times [2018-11-18 15:18:01,213 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:18:01,213 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:18:01,214 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:18:01,214 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:18:01,214 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:18:01,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:18:01,240 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:18:01,241 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:18:01,241 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:18:01,320 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:18:01,320 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:18:01,320 INFO L87 Difference]: Start difference. First operand 67484 states and 84808 transitions. cyclomatic complexity: 17348 Second operand 3 states. [2018-11-18 15:18:01,491 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:18:01,491 INFO L93 Difference]: Finished difference Result 87101 states and 109305 transitions. [2018-11-18 15:18:01,491 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:18:01,491 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 87101 states and 109305 transitions. [2018-11-18 15:18:01,668 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 58806 [2018-11-18 15:18:01,797 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 87101 states to 87101 states and 109305 transitions. [2018-11-18 15:18:01,797 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 59248 [2018-11-18 15:18:01,822 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 59248 [2018-11-18 15:18:01,822 INFO L73 IsDeterministic]: Start isDeterministic. Operand 87101 states and 109305 transitions. [2018-11-18 15:18:01,833 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-18 15:18:01,833 INFO L705 BuchiCegarLoop]: Abstraction has 87101 states and 109305 transitions. [2018-11-18 15:18:01,862 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87101 states and 109305 transitions. [2018-11-18 15:18:02,413 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87101 to 84761. [2018-11-18 15:18:02,413 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 84761 states. [2018-11-18 15:18:02,480 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84761 states to 84761 states and 106497 transitions. [2018-11-18 15:18:02,480 INFO L728 BuchiCegarLoop]: Abstraction has 84761 states and 106497 transitions. [2018-11-18 15:18:02,480 INFO L608 BuchiCegarLoop]: Abstraction has 84761 states and 106497 transitions. [2018-11-18 15:18:02,480 INFO L442 BuchiCegarLoop]: ======== Iteration 29============ [2018-11-18 15:18:02,480 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 84761 states and 106497 transitions. [2018-11-18 15:18:02,601 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 57246 [2018-11-18 15:18:02,601 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:18:02,601 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:18:02,601 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:18:02,601 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:18:02,602 INFO L794 eck$LassoCheckResult]: Stem: 734250#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 734063#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 733835#L893 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 733757#L409 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 733758#L416 assume 1 == ~m_i~0;~m_st~0 := 0; 734186#L416-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 733917#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 733918#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 733763#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 733764#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 733852#L441-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 733853#L601 assume !(0 == ~M_E~0); 734415#L601-2 assume !(0 == ~T1_E~0); 733856#L606-1 assume !(0 == ~T2_E~0); 733598#L611-1 assume !(0 == ~T3_E~0); 733599#L616-1 assume !(0 == ~T4_E~0); 733320#L621-1 assume !(0 == ~T5_E~0); 733321#L626-1 assume !(0 == ~E_M~0); 733507#L631-1 assume !(0 == ~E_1~0); 733508#L636-1 assume !(0 == ~E_2~0); 733964#L641-1 assume !(0 == ~E_3~0); 733965#L646-1 assume !(0 == ~E_4~0); 733829#L651-1 assume !(0 == ~E_5~0); 733830#L656-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 734437#L294 assume !(1 == ~m_pc~0); 734505#L294-2 is_master_triggered_~__retres1~0 := 0; 734562#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 734199#L306 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 734200#L745 assume !(0 != activate_threads_~tmp~1); 734590#L745-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 733696#L313 assume !(1 == ~t1_pc~0); 733697#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 733695#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 733585#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 733349#L753 assume !(0 != activate_threads_~tmp___0~0); 733350#L753-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 733355#L332 assume !(1 == ~t2_pc~0); 733774#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 733771#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 733772#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 733821#L761 assume !(0 != activate_threads_~tmp___1~0); 733822#L761-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 733823#L351 assume !(1 == ~t3_pc~0); 734073#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 734074#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 734118#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 734138#L769 assume !(0 != activate_threads_~tmp___2~0); 734139#L769-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 734143#L370 assume !(1 == ~t4_pc~0); 734400#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 734396#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 734397#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 734433#L777 assume !(0 != activate_threads_~tmp___3~0); 734434#L777-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 733491#L389 assume !(1 == ~t5_pc~0); 733426#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 733427#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 734599#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 733529#L785 assume !(0 != activate_threads_~tmp___4~0); 733530#L785-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 733534#L669 assume !(1 == ~M_E~0); 734456#L669-2 assume !(1 == ~T1_E~0); 733962#L674-1 assume !(1 == ~T2_E~0); 733963#L679-1 assume !(1 == ~T3_E~0); 733827#L684-1 assume !(1 == ~T4_E~0); 733828#L689-1 assume !(1 == ~T5_E~0); 734228#L694-1 assume !(1 == ~E_M~0); 733641#L699-1 assume !(1 == ~E_1~0); 733642#L704-1 assume !(1 == ~E_2~0); 733298#L709-1 assume !(1 == ~E_3~0); 733299#L714-1 assume !(1 == ~E_4~0); 733499#L719-1 assume !(1 == ~E_5~0); 733500#L724-1 assume { :end_inline_reset_delta_events } true; 734455#L930-3 assume true; 755080#L930-1 assume !false; 764266#L931 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 764239#L576 [2018-11-18 15:18:02,602 INFO L796 eck$LassoCheckResult]: Loop: 764239#L576 assume true; 764229#L496-1 assume !false; 764223#L497 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 764204#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 764189#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 764183#L487 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 764175#L501 assume 0 != eval_~tmp~0; 764168#L501-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 764160#L509 assume !(0 != eval_~tmp_ndt_1~0); 764153#L506 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 764151#L523 assume !(0 != eval_~tmp_ndt_2~0); 764142#L520 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 764101#L537 assume !(0 != eval_~tmp_ndt_3~0); 764136#L534 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 764221#L551 assume !(0 != eval_~tmp_ndt_4~0); 764258#L548 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 764269#L565 assume !(0 != eval_~tmp_ndt_5~0); 764267#L562 assume !(0 == ~t5_st~0); 764239#L576 [2018-11-18 15:18:02,602 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:18:02,602 INFO L82 PathProgramCache]: Analyzing trace with hash -1399767604, now seen corresponding path program 5 times [2018-11-18 15:18:02,602 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:18:02,602 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:18:02,602 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:18:02,602 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:18:02,602 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:18:02,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:18:02,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:18:02,618 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:18:02,618 INFO L82 PathProgramCache]: Analyzing trace with hash 2005126759, now seen corresponding path program 1 times [2018-11-18 15:18:02,618 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:18:02,618 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:18:02,619 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:18:02,619 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:18:02,619 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:18:02,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:18:02,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:18:02,623 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:18:02,623 INFO L82 PathProgramCache]: Analyzing trace with hash 825970546, now seen corresponding path program 1 times [2018-11-18 15:18:02,623 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:18:02,623 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:18:02,623 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:18:02,624 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:18:02,624 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:18:02,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:18:02,649 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:18:02,649 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:18:02,649 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 15:18:02,737 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:18:02,737 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:18:02,737 INFO L87 Difference]: Start difference. First operand 84761 states and 106497 transitions. cyclomatic complexity: 21760 Second operand 3 states. [2018-11-18 15:18:02,975 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:18:02,975 INFO L93 Difference]: Finished difference Result 146516 states and 183769 transitions. [2018-11-18 15:18:02,977 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:18:02,977 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 146516 states and 183769 transitions. [2018-11-18 15:18:03,265 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 99212 [2018-11-18 15:18:05,195 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 146516 states to 146516 states and 183769 transitions. [2018-11-18 15:18:05,195 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 100014 [2018-11-18 15:18:05,215 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 100014 [2018-11-18 15:18:05,215 INFO L73 IsDeterministic]: Start isDeterministic. Operand 146516 states and 183769 transitions. [2018-11-18 15:18:05,215 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-18 15:18:05,215 INFO L705 BuchiCegarLoop]: Abstraction has 146516 states and 183769 transitions. [2018-11-18 15:18:05,247 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146516 states and 183769 transitions. [2018-11-18 15:18:05,776 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146516 to 144416. [2018-11-18 15:18:05,776 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 144416 states. [2018-11-18 15:18:05,898 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144416 states to 144416 states and 181669 transitions. [2018-11-18 15:18:05,898 INFO L728 BuchiCegarLoop]: Abstraction has 144416 states and 181669 transitions. [2018-11-18 15:18:05,898 INFO L608 BuchiCegarLoop]: Abstraction has 144416 states and 181669 transitions. [2018-11-18 15:18:05,898 INFO L442 BuchiCegarLoop]: ======== Iteration 30============ [2018-11-18 15:18:05,898 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 144416 states and 181669 transitions. [2018-11-18 15:18:06,118 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 97812 [2018-11-18 15:18:06,118 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:18:06,118 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:18:06,118 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:18:06,119 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:18:06,119 INFO L794 eck$LassoCheckResult]: Stem: 965560#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 965372#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 965135#L893 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 965057#L409 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 965058#L416 assume 1 == ~m_i~0;~m_st~0 := 0; 965497#L416-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 965214#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 965215#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 965059#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 965060#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 965148#L441-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 965149#L601 assume !(0 == ~M_E~0); 965733#L601-2 assume !(0 == ~T1_E~0); 965155#L606-1 assume !(0 == ~T2_E~0); 964896#L611-1 assume !(0 == ~T3_E~0); 964897#L616-1 assume !(0 == ~T4_E~0); 964603#L621-1 assume !(0 == ~T5_E~0); 964604#L626-1 assume !(0 == ~E_M~0); 964806#L631-1 assume !(0 == ~E_1~0); 964807#L636-1 assume !(0 == ~E_2~0); 965269#L641-1 assume !(0 == ~E_3~0); 965270#L646-1 assume !(0 == ~E_4~0); 965129#L651-1 assume !(0 == ~E_5~0); 965130#L656-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 965759#L294 assume !(1 == ~m_pc~0); 965829#L294-2 is_master_triggered_~__retres1~0 := 0; 965872#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 965504#L306 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 965505#L745 assume !(0 != activate_threads_~tmp~1); 965905#L745-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 964994#L313 assume !(1 == ~t1_pc~0); 964995#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 964989#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 964881#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 964634#L753 assume !(0 != activate_threads_~tmp___0~0); 964635#L753-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 964645#L332 assume !(1 == ~t2_pc~0); 965074#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 965071#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 965072#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 965122#L761 assume !(0 != activate_threads_~tmp___1~0); 965123#L761-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 965124#L351 assume !(1 == ~t3_pc~0); 965381#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 965382#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 965431#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 965448#L769 assume !(0 != activate_threads_~tmp___2~0); 965449#L769-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 965454#L370 assume !(1 == ~t4_pc~0); 965710#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 965704#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 965705#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 965754#L777 assume !(0 != activate_threads_~tmp___3~0); 965755#L777-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 964789#L389 assume !(1 == ~t5_pc~0); 964719#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 964720#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 965916#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 964829#L785 assume !(0 != activate_threads_~tmp___4~0); 964830#L785-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 964834#L669 assume !(1 == ~M_E~0); 965785#L669-2 assume !(1 == ~T1_E~0); 965267#L674-1 assume !(1 == ~T2_E~0); 965268#L679-1 assume !(1 == ~T3_E~0); 965127#L684-1 assume !(1 == ~T4_E~0); 965128#L689-1 assume !(1 == ~T5_E~0); 965539#L694-1 assume !(1 == ~E_M~0); 964940#L699-1 assume !(1 == ~E_1~0); 964941#L704-1 assume !(1 == ~E_2~0); 964583#L709-1 assume !(1 == ~E_3~0); 964584#L714-1 assume !(1 == ~E_4~0); 964794#L719-1 assume !(1 == ~E_5~0); 964795#L724-1 assume { :end_inline_reset_delta_events } true; 965784#L930-3 assume true; 995221#L930-1 assume !false; 1032630#L931 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 1032626#L576 [2018-11-18 15:18:06,119 INFO L796 eck$LassoCheckResult]: Loop: 1032626#L576 assume true; 1032624#L496-1 assume !false; 1032622#L497 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1032620#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1032619#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1032617#L487 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 1032615#L501 assume 0 != eval_~tmp~0; 1032613#L501-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 1032610#L509 assume !(0 != eval_~tmp_ndt_1~0); 1032611#L506 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 1033605#L523 assume !(0 != eval_~tmp_ndt_2~0); 1033599#L520 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 1033370#L537 assume !(0 != eval_~tmp_ndt_3~0); 1025066#L534 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 1025063#L551 assume !(0 != eval_~tmp_ndt_4~0); 1025064#L548 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 1032691#L565 assume !(0 != eval_~tmp_ndt_5~0); 1032634#L562 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 1032628#L579 assume !(0 != eval_~tmp_ndt_6~0); 1032626#L576 [2018-11-18 15:18:06,119 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:18:06,119 INFO L82 PathProgramCache]: Analyzing trace with hash -1399767604, now seen corresponding path program 6 times [2018-11-18 15:18:06,119 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:18:06,119 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:18:06,120 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:18:06,120 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:18:06,120 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:18:06,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:18:06,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:18:06,136 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:18:06,137 INFO L82 PathProgramCache]: Analyzing trace with hash 2029383392, now seen corresponding path program 1 times [2018-11-18 15:18:06,137 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:18:06,137 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:18:06,137 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:18:06,137 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:18:06,137 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:18:06,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:18:06,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:18:06,141 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:18:06,141 INFO L82 PathProgramCache]: Analyzing trace with hash -164720843, now seen corresponding path program 1 times [2018-11-18 15:18:06,141 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:18:06,142 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:18:06,142 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:18:06,142 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:18:06,142 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:18:06,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:18:06,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:18:06,614 WARN L180 SmtUtils]: Spent 333.00 ms on a formula simplification. DAG size of input: 198 DAG size of output: 132 [2018-11-18 15:18:06,716 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 18.11 03:18:06 BoogieIcfgContainer [2018-11-18 15:18:06,717 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2018-11-18 15:18:06,717 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-18 15:18:06,717 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-18 15:18:06,717 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-18 15:18:06,718 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 03:17:49" (3/4) ... [2018-11-18 15:18:06,724 INFO L141 WitnessPrinter]: Generating witness for non-termination counterexample [2018-11-18 15:18:06,770 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_d6bfc3eb-9043-4962-ad04-a405114524f4/bin-2019/uautomizer/witness.graphml [2018-11-18 15:18:06,771 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-18 15:18:06,771 INFO L168 Benchmark]: Toolchain (without parser) took 18277.68 ms. Allocated memory was 1.0 GB in the beginning and 3.0 GB in the end (delta: 2.0 GB). Free memory was 953.8 MB in the beginning and 1.5 GB in the end (delta: -529.5 MB). Peak memory consumption was 1.4 GB. Max. memory is 11.5 GB. [2018-11-18 15:18:06,772 INFO L168 Benchmark]: CDTParser took 0.17 ms. Allocated memory is still 1.0 GB. Free memory is still 980.1 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 15:18:06,772 INFO L168 Benchmark]: CACSL2BoogieTranslator took 239.62 ms. Allocated memory is still 1.0 GB. Free memory was 953.8 MB in the beginning and 932.3 MB in the end (delta: 21.5 MB). Peak memory consumption was 21.5 MB. Max. memory is 11.5 GB. [2018-11-18 15:18:06,772 INFO L168 Benchmark]: Boogie Procedure Inliner took 87.14 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 129.0 MB). Free memory was 932.3 MB in the beginning and 1.1 GB in the end (delta: -187.6 MB). Peak memory consumption was 14.8 MB. Max. memory is 11.5 GB. [2018-11-18 15:18:06,772 INFO L168 Benchmark]: Boogie Preprocessor took 44.87 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 3.4 MB). Peak memory consumption was 3.4 MB. Max. memory is 11.5 GB. [2018-11-18 15:18:06,773 INFO L168 Benchmark]: RCFGBuilder took 899.60 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 996.8 MB in the end (delta: 119.7 MB). Peak memory consumption was 119.7 MB. Max. memory is 11.5 GB. [2018-11-18 15:18:06,773 INFO L168 Benchmark]: BuchiAutomizer took 16949.74 ms. Allocated memory was 1.2 GB in the beginning and 3.0 GB in the end (delta: 1.8 GB). Free memory was 996.8 MB in the beginning and 1.5 GB in the end (delta: -486.5 MB). Peak memory consumption was 1.3 GB. Max. memory is 11.5 GB. [2018-11-18 15:18:06,773 INFO L168 Benchmark]: Witness Printer took 53.71 ms. Allocated memory is still 3.0 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 15:18:06,775 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.17 ms. Allocated memory is still 1.0 GB. Free memory is still 980.1 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 239.62 ms. Allocated memory is still 1.0 GB. Free memory was 953.8 MB in the beginning and 932.3 MB in the end (delta: 21.5 MB). Peak memory consumption was 21.5 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 87.14 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 129.0 MB). Free memory was 932.3 MB in the beginning and 1.1 GB in the end (delta: -187.6 MB). Peak memory consumption was 14.8 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 44.87 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 3.4 MB). Peak memory consumption was 3.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 899.60 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 996.8 MB in the end (delta: 119.7 MB). Peak memory consumption was 119.7 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 16949.74 ms. Allocated memory was 1.2 GB in the beginning and 3.0 GB in the end (delta: 1.8 GB). Free memory was 996.8 MB in the beginning and 1.5 GB in the end (delta: -486.5 MB). Peak memory consumption was 1.3 GB. Max. memory is 11.5 GB. * Witness Printer took 53.71 ms. Allocated memory is still 3.0 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 30 terminating modules (29 trivial, 1 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function -2 * E_4 + 3 and consists of 3 locations. 29 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 144416 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 16.9s and 30 iterations. TraceHistogramMax:2. Analysis of lassos took 5.1s. Construction of modules took 1.2s. Büchi inclusion checks took 1.9s. Highest rank in rank-based complementation 3. Minimization of det autom 19. Minimization of nondet autom 11. Automata minimization 3.4s AutomataMinimizationTime, 30 MinimizatonAttempts, 62784 StatesRemovedByMinimization, 15 NontrivialMinimizations. Non-live state removal took 3.9s Buchi closure took 0.1s. Biggest automaton had 144416 states and ocurred in iteration 29. Nontrivial modules had stage [1, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 25225 SDtfs, 28401 SDslu, 25107 SDs, 0 SdLazy, 955 SolverSat, 435 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.2s Time LassoAnalysisResults: nont1 unkn0 SFLI9 SFLT0 conc5 concLT1 SILN1 SILU0 SILI13 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital217 mio100 ax100 hnf100 lsp5 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq209 hnf86 smp100 dnf189 smp63 tf108 neg92 sie116 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 2ms VariablesStem: 0 VariablesLoop: 1 DisjunctsStem: 1 DisjunctsLoop: 2 SupportingInvariants: 0 MotzkinApplications: 4 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 13 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 1 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.1s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 496]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {__retres1=0, t3_st=0, token=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@71a5783e=0, tmp=1, t5_i=1, __retres1=0, kernel_st=1, t2_st=0, t4_i=1, E_3=2, t4_pc=0, E_5=2, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@dfdcc7a=0, E_1=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7f554682=0, tmp_ndt_2=0, \result=0, __retres1=0, \result=0, tmp_ndt_4=0, tmp_ndt_6=0, m_st=0, tmp___2=0, tmp___0=0, t3_pc=0, tmp=0, \result=0, __retres1=0, m_pc=0, tmp___4=0, \result=0, __retres1=0, \result=0, __retres1=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@599303b1=0, T2_E=2, tmp___0=0, t1_pc=0, t5_st=0, __retres1=1, E_2=2, E_4=2, T1_E=2, tmp_ndt_1=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, T5_E=2, t2_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7689bb2=0, T4_E=2, t3_i=1, t4_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@291d0e9=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@331f2b76=0, t1_st=0, tmp_ndt_5=0, t5_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@366e9f31=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3af4061e=0, local=0, t2_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@707ad7fc=0, tmp___3=0, E_M=2, tmp___1=0, T3_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@43ea5cb1=0, t1_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2fb69fe8=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7153cf7f=0, \result=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6c2fc18e=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@578166e2=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 496]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int t4_pc = 0; [L19] int t5_pc = 0; [L20] int m_st ; [L21] int t1_st ; [L22] int t2_st ; [L23] int t3_st ; [L24] int t4_st ; [L25] int t5_st ; [L26] int m_i ; [L27] int t1_i ; [L28] int t2_i ; [L29] int t3_i ; [L30] int t4_i ; [L31] int t5_i ; [L32] int M_E = 2; [L33] int T1_E = 2; [L34] int T2_E = 2; [L35] int T3_E = 2; [L36] int T4_E = 2; [L37] int T5_E = 2; [L38] int E_M = 2; [L39] int E_1 = 2; [L40] int E_2 = 2; [L41] int E_3 = 2; [L42] int E_4 = 2; [L43] int E_5 = 2; [L51] int token ; [L53] int local ; [L975] int __retres1 ; [L979] CALL init_model() [L886] m_i = 1 [L887] t1_i = 1 [L888] t2_i = 1 [L889] t3_i = 1 [L890] t4_i = 1 [L891] RET t5_i = 1 [L979] init_model() [L980] CALL start_simulation() [L916] int kernel_st ; [L917] int tmp ; [L918] int tmp___0 ; [L922] kernel_st = 0 [L923] FCALL update_channels() [L924] CALL init_threads() [L416] COND TRUE m_i == 1 [L417] m_st = 0 [L421] COND TRUE t1_i == 1 [L422] t1_st = 0 [L426] COND TRUE t2_i == 1 [L427] t2_st = 0 [L431] COND TRUE t3_i == 1 [L432] t3_st = 0 [L436] COND TRUE t4_i == 1 [L437] t4_st = 0 [L441] COND TRUE t5_i == 1 [L442] RET t5_st = 0 [L924] init_threads() [L925] CALL fire_delta_events() [L601] COND FALSE !(M_E == 0) [L606] COND FALSE !(T1_E == 0) [L611] COND FALSE !(T2_E == 0) [L616] COND FALSE !(T3_E == 0) [L621] COND FALSE !(T4_E == 0) [L626] COND FALSE !(T5_E == 0) [L631] COND FALSE !(E_M == 0) [L636] COND FALSE !(E_1 == 0) [L641] COND FALSE !(E_2 == 0) [L646] COND FALSE !(E_3 == 0) [L651] COND FALSE !(E_4 == 0) [L656] COND FALSE, RET !(E_5 == 0) [L925] fire_delta_events() [L926] CALL activate_threads() [L734] int tmp ; [L735] int tmp___0 ; [L736] int tmp___1 ; [L737] int tmp___2 ; [L738] int tmp___3 ; [L739] int tmp___4 ; [L743] CALL, EXPR is_master_triggered() [L291] int __retres1 ; [L294] COND FALSE !(m_pc == 1) [L304] __retres1 = 0 [L306] RET return (__retres1); [L743] EXPR is_master_triggered() [L743] tmp = is_master_triggered() [L745] COND FALSE !(\read(tmp)) [L751] CALL, EXPR is_transmit1_triggered() [L310] int __retres1 ; [L313] COND FALSE !(t1_pc == 1) [L323] __retres1 = 0 [L325] RET return (__retres1); [L751] EXPR is_transmit1_triggered() [L751] tmp___0 = is_transmit1_triggered() [L753] COND FALSE !(\read(tmp___0)) [L759] CALL, EXPR is_transmit2_triggered() [L329] int __retres1 ; [L332] COND FALSE !(t2_pc == 1) [L342] __retres1 = 0 [L344] RET return (__retres1); [L759] EXPR is_transmit2_triggered() [L759] tmp___1 = is_transmit2_triggered() [L761] COND FALSE !(\read(tmp___1)) [L767] CALL, EXPR is_transmit3_triggered() [L348] int __retres1 ; [L351] COND FALSE !(t3_pc == 1) [L361] __retres1 = 0 [L363] RET return (__retres1); [L767] EXPR is_transmit3_triggered() [L767] tmp___2 = is_transmit3_triggered() [L769] COND FALSE !(\read(tmp___2)) [L775] CALL, EXPR is_transmit4_triggered() [L367] int __retres1 ; [L370] COND FALSE !(t4_pc == 1) [L380] __retres1 = 0 [L382] RET return (__retres1); [L775] EXPR is_transmit4_triggered() [L775] tmp___3 = is_transmit4_triggered() [L777] COND FALSE !(\read(tmp___3)) [L783] CALL, EXPR is_transmit5_triggered() [L386] int __retres1 ; [L389] COND FALSE !(t5_pc == 1) [L399] __retres1 = 0 [L401] RET return (__retres1); [L783] EXPR is_transmit5_triggered() [L783] tmp___4 = is_transmit5_triggered() [L785] COND FALSE, RET !(\read(tmp___4)) [L926] activate_threads() [L927] CALL reset_delta_events() [L669] COND FALSE !(M_E == 1) [L674] COND FALSE !(T1_E == 1) [L679] COND FALSE !(T2_E == 1) [L684] COND FALSE !(T3_E == 1) [L689] COND FALSE !(T4_E == 1) [L694] COND FALSE !(T5_E == 1) [L699] COND FALSE !(E_M == 1) [L704] COND FALSE !(E_1 == 1) [L709] COND FALSE !(E_2 == 1) [L714] COND FALSE !(E_3 == 1) [L719] COND FALSE !(E_4 == 1) [L724] COND FALSE, RET !(E_5 == 1) [L927] reset_delta_events() [L930] COND TRUE 1 [L933] kernel_st = 1 [L934] CALL eval() [L492] int tmp ; Loop: [L496] COND TRUE 1 [L499] CALL, EXPR exists_runnable_thread() [L451] int __retres1 ; [L454] COND TRUE m_st == 0 [L455] __retres1 = 1 [L487] RET return (__retres1); [L499] EXPR exists_runnable_thread() [L499] tmp = exists_runnable_thread() [L501] COND TRUE \read(tmp) [L506] COND TRUE m_st == 0 [L507] int tmp_ndt_1; [L508] tmp_ndt_1 = __VERIFIER_nondet_int() [L509] COND FALSE !(\read(tmp_ndt_1)) [L520] COND TRUE t1_st == 0 [L521] int tmp_ndt_2; [L522] tmp_ndt_2 = __VERIFIER_nondet_int() [L523] COND FALSE !(\read(tmp_ndt_2)) [L534] COND TRUE t2_st == 0 [L535] int tmp_ndt_3; [L536] tmp_ndt_3 = __VERIFIER_nondet_int() [L537] COND FALSE !(\read(tmp_ndt_3)) [L548] COND TRUE t3_st == 0 [L549] int tmp_ndt_4; [L550] tmp_ndt_4 = __VERIFIER_nondet_int() [L551] COND FALSE !(\read(tmp_ndt_4)) [L562] COND TRUE t4_st == 0 [L563] int tmp_ndt_5; [L564] tmp_ndt_5 = __VERIFIER_nondet_int() [L565] COND FALSE !(\read(tmp_ndt_5)) [L576] COND TRUE t5_st == 0 [L577] int tmp_ndt_6; [L578] tmp_ndt_6 = __VERIFIER_nondet_int() [L579] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...