./Ultimate.py --spec ../../sv-benchmarks/c/Termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.06_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 5842f4b8 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_589f8f85-d669-45bb-ac7e-db79ceb26f77/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_589f8f85-d669-45bb-ac7e-db79ceb26f77/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_589f8f85-d669-45bb-ac7e-db79ceb26f77/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_589f8f85-d669-45bb-ac7e-db79ceb26f77/bin-2019/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.06_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_589f8f85-d669-45bb-ac7e-db79ceb26f77/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_589f8f85-d669-45bb-ac7e-db79ceb26f77/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 936bf61b77a625ec3ee8993291aaaab59d0dc18e .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.23-5842f4b [2018-11-18 10:39:52,464 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-18 10:39:52,466 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-18 10:39:52,473 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-18 10:39:52,474 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-18 10:39:52,474 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-18 10:39:52,475 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-18 10:39:52,476 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-18 10:39:52,477 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-18 10:39:52,478 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-18 10:39:52,478 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-18 10:39:52,479 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-18 10:39:52,479 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-18 10:39:52,480 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-18 10:39:52,481 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-18 10:39:52,481 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-18 10:39:52,482 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-18 10:39:52,483 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-18 10:39:52,485 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-18 10:39:52,486 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-18 10:39:52,486 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-18 10:39:52,487 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-18 10:39:52,489 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-18 10:39:52,489 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-18 10:39:52,489 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-18 10:39:52,490 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-18 10:39:52,490 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-18 10:39:52,491 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-18 10:39:52,491 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-18 10:39:52,493 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-18 10:39:52,493 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-18 10:39:52,493 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-18 10:39:52,493 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-18 10:39:52,493 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-18 10:39:52,494 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-18 10:39:52,495 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-18 10:39:52,495 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_589f8f85-d669-45bb-ac7e-db79ceb26f77/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2018-11-18 10:39:52,505 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-18 10:39:52,505 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-18 10:39:52,506 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-18 10:39:52,506 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-18 10:39:52,507 INFO L133 SettingsManager]: * Use SBE=true [2018-11-18 10:39:52,507 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2018-11-18 10:39:52,507 INFO L133 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2018-11-18 10:39:52,507 INFO L133 SettingsManager]: * Use old map elimination=false [2018-11-18 10:39:52,507 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false [2018-11-18 10:39:52,507 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true [2018-11-18 10:39:52,508 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2018-11-18 10:39:52,508 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-18 10:39:52,508 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-18 10:39:52,508 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-18 10:39:52,509 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-18 10:39:52,509 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-18 10:39:52,509 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-18 10:39:52,509 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2018-11-18 10:39:52,509 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2018-11-18 10:39:52,509 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2018-11-18 10:39:52,509 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-18 10:39:52,510 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-18 10:39:52,510 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false [2018-11-18 10:39:52,510 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-18 10:39:52,510 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2018-11-18 10:39:52,510 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-18 10:39:52,510 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-18 10:39:52,510 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2018-11-18 10:39:52,511 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-18 10:39:52,511 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-18 10:39:52,511 INFO L133 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2018-11-18 10:39:52,513 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-11-18 10:39:52,513 INFO L133 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_589f8f85-d669-45bb-ac7e-db79ceb26f77/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 936bf61b77a625ec3ee8993291aaaab59d0dc18e [2018-11-18 10:39:52,537 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-18 10:39:52,545 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-18 10:39:52,547 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-18 10:39:52,548 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-18 10:39:52,548 INFO L276 PluginConnector]: CDTParser initialized [2018-11-18 10:39:52,548 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_589f8f85-d669-45bb-ac7e-db79ceb26f77/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/token_ring.06_false-unreach-call_false-termination.cil.c [2018-11-18 10:39:52,585 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_589f8f85-d669-45bb-ac7e-db79ceb26f77/bin-2019/uautomizer/data/1932308cb/8831342bd53e4448950f41a5b50ca3f3/FLAG32b349a90 [2018-11-18 10:39:52,993 INFO L307 CDTParser]: Found 1 translation units. [2018-11-18 10:39:52,994 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_589f8f85-d669-45bb-ac7e-db79ceb26f77/sv-benchmarks/c/systemc/token_ring.06_false-unreach-call_false-termination.cil.c [2018-11-18 10:39:53,000 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_589f8f85-d669-45bb-ac7e-db79ceb26f77/bin-2019/uautomizer/data/1932308cb/8831342bd53e4448950f41a5b50ca3f3/FLAG32b349a90 [2018-11-18 10:39:53,008 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_589f8f85-d669-45bb-ac7e-db79ceb26f77/bin-2019/uautomizer/data/1932308cb/8831342bd53e4448950f41a5b50ca3f3 [2018-11-18 10:39:53,010 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-18 10:39:53,011 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-18 10:39:53,011 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-18 10:39:53,011 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-18 10:39:53,014 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-18 10:39:53,014 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 10:39:53" (1/1) ... [2018-11-18 10:39:53,016 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@64e3deec and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:39:53, skipping insertion in model container [2018-11-18 10:39:53,016 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 10:39:53" (1/1) ... [2018-11-18 10:39:53,021 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-18 10:39:53,048 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-18 10:39:53,198 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 10:39:53,201 INFO L191 MainTranslator]: Completed pre-run [2018-11-18 10:39:53,234 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 10:39:53,246 INFO L195 MainTranslator]: Completed translation [2018-11-18 10:39:53,246 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:39:53 WrapperNode [2018-11-18 10:39:53,246 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-18 10:39:53,247 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-18 10:39:53,247 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-18 10:39:53,247 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-18 10:39:53,254 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:39:53" (1/1) ... [2018-11-18 10:39:53,299 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:39:53" (1/1) ... [2018-11-18 10:39:53,345 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-18 10:39:53,345 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-18 10:39:53,345 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-18 10:39:53,346 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-18 10:39:53,353 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:39:53" (1/1) ... [2018-11-18 10:39:53,353 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:39:53" (1/1) ... [2018-11-18 10:39:53,357 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:39:53" (1/1) ... [2018-11-18 10:39:53,357 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:39:53" (1/1) ... [2018-11-18 10:39:53,371 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:39:53" (1/1) ... [2018-11-18 10:39:53,388 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:39:53" (1/1) ... [2018-11-18 10:39:53,391 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:39:53" (1/1) ... [2018-11-18 10:39:53,396 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-18 10:39:53,397 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-18 10:39:53,397 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-18 10:39:53,397 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-18 10:39:53,397 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:39:53" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_589f8f85-d669-45bb-ac7e-db79ceb26f77/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 10:39:53,459 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-18 10:39:53,459 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-18 10:39:54,515 INFO L278 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-18 10:39:54,515 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 10:39:54 BoogieIcfgContainer [2018-11-18 10:39:54,515 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-18 10:39:54,516 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2018-11-18 10:39:54,516 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2018-11-18 10:39:54,518 INFO L276 PluginConnector]: BuchiAutomizer initialized [2018-11-18 10:39:54,519 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 10:39:54,519 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 18.11 10:39:53" (1/3) ... [2018-11-18 10:39:54,520 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2b51b893 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 10:39:54, skipping insertion in model container [2018-11-18 10:39:54,520 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 10:39:54,520 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:39:53" (2/3) ... [2018-11-18 10:39:54,520 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2b51b893 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 10:39:54, skipping insertion in model container [2018-11-18 10:39:54,520 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 10:39:54,521 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 10:39:54" (3/3) ... [2018-11-18 10:39:54,522 INFO L375 chiAutomizerObserver]: Analyzing ICFG token_ring.06_false-unreach-call_false-termination.cil.c [2018-11-18 10:39:54,556 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-18 10:39:54,557 INFO L374 BuchiCegarLoop]: Interprodecural is true [2018-11-18 10:39:54,557 INFO L375 BuchiCegarLoop]: Hoare is false [2018-11-18 10:39:54,557 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2018-11-18 10:39:54,557 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-18 10:39:54,557 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-18 10:39:54,557 INFO L379 BuchiCegarLoop]: Difference is false [2018-11-18 10:39:54,557 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-18 10:39:54,558 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2018-11-18 10:39:54,580 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 703 states. [2018-11-18 10:39:54,619 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 608 [2018-11-18 10:39:54,619 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:39:54,619 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:39:54,629 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:39:54,629 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:39:54,629 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ [2018-11-18 10:39:54,629 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 703 states. [2018-11-18 10:39:54,638 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 608 [2018-11-18 10:39:54,639 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:39:54,639 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:39:54,641 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:39:54,641 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:39:54,648 INFO L794 eck$LassoCheckResult]: Stem: 473#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 369#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 160#L1018true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 692#L470true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 52#L477true assume !(1 == ~m_i~0);~m_st~0 := 2; 57#L477-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 618#L482-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 308#L487-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 694#L492-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 188#L497-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 583#L502-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 243#L507-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 61#L686true assume !(0 == ~M_E~0); 68#L686-2true assume !(0 == ~T1_E~0); 627#L691-1true assume !(0 == ~T2_E~0); 321#L696-1true assume !(0 == ~T3_E~0); 701#L701-1true assume !(0 == ~T4_E~0); 193#L706-1true assume !(0 == ~T5_E~0); 590#L711-1true assume !(0 == ~T6_E~0); 440#L716-1true assume 0 == ~E_M~0;~E_M~0 := 1; 144#L721-1true assume !(0 == ~E_1~0); 533#L726-1true assume !(0 == ~E_2~0); 13#L731-1true assume !(0 == ~E_3~0); 396#L736-1true assume !(0 == ~E_4~0); 60#L741-1true assume !(0 == ~E_5~0); 623#L746-1true assume !(0 == ~E_6~0); 315#L751-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 119#L336true assume !(1 == ~m_pc~0); 89#L336-2true is_master_triggered_~__retres1~0 := 0; 117#L347true is_master_triggered_#res := is_master_triggered_~__retres1~0; 566#L348true activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 75#L851true assume !(0 != activate_threads_~tmp~1); 78#L851-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 279#L355true assume 1 == ~t1_pc~0; 30#L356true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 277#L366true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 59#L367true activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 450#L859true assume !(0 != activate_threads_~tmp___0~0); 433#L859-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 503#L374true assume !(1 == ~t2_pc~0); 467#L374-2true is_transmit2_triggered_~__retres1~2 := 0; 501#L385true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 225#L386true activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 639#L867true assume !(0 != activate_threads_~tmp___1~0); 642#L867-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 669#L393true assume 1 == ~t3_pc~0; 621#L394true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 667#L404true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 619#L405true activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 150#L875true assume !(0 != activate_threads_~tmp___2~0); 137#L875-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 176#L412true assume 1 == ~t4_pc~0; 110#L413true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 175#L423true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 109#L424true activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 332#L883true assume !(0 != activate_threads_~tmp___3~0); 336#L883-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 190#L431true assume !(1 == ~t5_pc~0); 182#L431-2true is_transmit5_triggered_~__retres1~5 := 0; 189#L442true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 310#L443true activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 541#L891true assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 525#L891-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 385#L450true assume 1 == ~t6_pc~0; 495#L451true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 384#L461true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 493#L462true activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 544#L899true assume !(0 != activate_threads_~tmp___5~0); 546#L899-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11#L764true assume !(1 == ~M_E~0); 14#L764-2true assume !(1 == ~T1_E~0); 394#L769-1true assume !(1 == ~T2_E~0); 81#L774-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 645#L779-1true assume !(1 == ~T4_E~0); 342#L784-1true assume !(1 == ~T5_E~0); 697#L789-1true assume !(1 == ~T6_E~0); 191#L794-1true assume !(1 == ~E_M~0); 586#L799-1true assume !(1 == ~E_1~0); 434#L804-1true assume !(1 == ~E_2~0); 138#L809-1true assume !(1 == ~E_3~0); 528#L814-1true assume 1 == ~E_4~0;~E_4~0 := 2; 10#L819-1true assume !(1 == ~E_5~0); 393#L824-1true assume !(1 == ~E_6~0); 77#L829-1true assume { :end_inline_reset_delta_events } true; 400#L1055-3true [2018-11-18 10:39:54,650 INFO L796 eck$LassoCheckResult]: Loop: 400#L1055-3true assume true; 398#L1055-1true assume !false; 368#L1056true start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 441#L661true assume !true; 3#L676true assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 695#L470-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 70#L686-3true assume 0 == ~M_E~0;~M_E~0 := 1; 47#L686-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 636#L691-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 327#L696-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 703#L701-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 194#L706-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 573#L711-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 234#L716-3true assume !(0 == ~E_M~0); 128#L721-3true assume 0 == ~E_1~0;~E_1~0 := 1; 511#L726-3true assume 0 == ~E_2~0;~E_2~0 := 1; 5#L731-3true assume 0 == ~E_3~0;~E_3~0 := 1; 392#L736-3true assume 0 == ~E_4~0;~E_4~0 := 1; 67#L741-3true assume 0 == ~E_5~0;~E_5~0 := 1; 630#L746-3true assume 0 == ~E_6~0;~E_6~0 := 1; 323#L751-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 576#L336-24true assume !(1 == ~m_pc~0); 580#L336-26true is_master_triggered_~__retres1~0 := 0; 604#L347-8true is_master_triggered_#res := is_master_triggered_~__retres1~0; 548#L348-8true activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 28#L851-24true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 15#L851-26true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 72#L355-24true assume !(1 == ~t1_pc~0); 48#L355-26true is_transmit1_triggered_~__retres1~1 := 0; 269#L366-8true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 24#L367-8true activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 200#L859-24true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 201#L859-26true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 235#L374-24true assume 1 == ~t2_pc~0; 222#L375-8true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 453#L385-8true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 220#L386-8true activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 413#L867-24true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 397#L867-26true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 633#L393-24true assume 1 == ~t3_pc~0; 409#L394-8true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 660#L404-8true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 408#L405-8true activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 605#L875-24true assume !(0 != activate_threads_~tmp___2~0); 610#L875-26true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 125#L412-24true assume !(1 == ~t4_pc~0); 131#L412-26true is_transmit4_triggered_~__retres1~4 := 0; 169#L423-8true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 103#L424-8true activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 271#L883-24true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 246#L883-26true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 322#L431-24true assume 1 == ~t5_pc~0; 263#L432-8true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 359#L442-8true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 261#L443-8true activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 455#L891-24true assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 460#L891-26true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 536#L450-24true assume !(1 == ~t6_pc~0); 513#L450-26true is_transmit6_triggered_~__retres1~6 := 0; 382#L461-8true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 485#L462-8true activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 663#L899-24true assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 646#L899-26true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4#L764-3true assume 1 == ~M_E~0;~M_E~0 := 2; 6#L764-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 391#L769-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 64#L774-3true assume !(1 == ~T3_E~0); 625#L779-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 320#L784-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 700#L789-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 192#L794-3true assume 1 == ~E_M~0;~E_M~0 := 2; 589#L799-3true assume 1 == ~E_1~0;~E_1~0 := 2; 438#L804-3true assume 1 == ~E_2~0;~E_2~0 := 2; 143#L809-3true assume 1 == ~E_3~0;~E_3~0 := 2; 532#L814-3true assume !(1 == ~E_4~0); 12#L819-3true assume 1 == ~E_5~0;~E_5~0 := 2; 395#L824-3true assume 1 == ~E_6~0;~E_6~0 := 2; 82#L829-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 307#L520-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 579#L557-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 688#L558-1true start_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 609#L1074true assume !(0 == start_simulation_~tmp~3); 613#L1074-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 309#L520-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 582#L557-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 691#L558-2true stop_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 159#L1029true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 202#L1036true stop_simulation_#res := stop_simulation_~__retres2~0; 349#L1037true start_simulation_#t~ret19 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 666#L1087true assume !(0 != start_simulation_~tmp___0~1); 400#L1055-3true [2018-11-18 10:39:54,656 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:39:54,656 INFO L82 PathProgramCache]: Analyzing trace with hash -376834623, now seen corresponding path program 1 times [2018-11-18 10:39:54,658 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:39:54,658 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:39:54,687 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:54,688 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:39:54,688 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:54,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:39:54,770 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:39:54,772 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:39:54,772 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:39:54,776 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 10:39:54,776 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:39:54,776 INFO L82 PathProgramCache]: Analyzing trace with hash -1532897068, now seen corresponding path program 1 times [2018-11-18 10:39:54,776 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:39:54,776 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:39:54,777 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:54,777 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:39:54,777 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:54,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:39:54,798 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:39:54,798 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:39:54,798 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 10:39:54,800 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 10:39:54,810 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:39:54,810 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:39:54,812 INFO L87 Difference]: Start difference. First operand 703 states. Second operand 3 states. [2018-11-18 10:39:54,850 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:39:54,850 INFO L93 Difference]: Finished difference Result 701 states and 1043 transitions. [2018-11-18 10:39:54,850 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:39:54,852 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 701 states and 1043 transitions. [2018-11-18 10:39:54,858 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 604 [2018-11-18 10:39:54,867 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 701 states to 695 states and 1037 transitions. [2018-11-18 10:39:54,868 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 695 [2018-11-18 10:39:54,869 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 695 [2018-11-18 10:39:54,870 INFO L73 IsDeterministic]: Start isDeterministic. Operand 695 states and 1037 transitions. [2018-11-18 10:39:54,873 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:39:54,873 INFO L705 BuchiCegarLoop]: Abstraction has 695 states and 1037 transitions. [2018-11-18 10:39:54,887 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 695 states and 1037 transitions. [2018-11-18 10:39:54,910 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 695 to 695. [2018-11-18 10:39:54,911 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 695 states. [2018-11-18 10:39:54,913 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 695 states to 695 states and 1037 transitions. [2018-11-18 10:39:54,914 INFO L728 BuchiCegarLoop]: Abstraction has 695 states and 1037 transitions. [2018-11-18 10:39:54,914 INFO L608 BuchiCegarLoop]: Abstraction has 695 states and 1037 transitions. [2018-11-18 10:39:54,914 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ [2018-11-18 10:39:54,915 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 695 states and 1037 transitions. [2018-11-18 10:39:54,918 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 604 [2018-11-18 10:39:54,919 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:39:54,919 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:39:54,921 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:39:54,921 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:39:54,921 INFO L794 eck$LassoCheckResult]: Stem: 2018#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1910#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1681#L1018 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 1682#L470 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1511#L477 assume 1 == ~m_i~0;~m_st~0 := 0; 1512#L477-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1520#L482-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1859#L487-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1860#L492-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1704#L497-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1705#L502-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1800#L507-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1526#L686 assume !(0 == ~M_E~0); 1527#L686-2 assume !(0 == ~T1_E~0); 1539#L691-1 assume !(0 == ~T2_E~0); 1870#L696-1 assume !(0 == ~T3_E~0); 1871#L701-1 assume !(0 == ~T4_E~0); 1713#L706-1 assume !(0 == ~T5_E~0); 1714#L711-1 assume !(0 == ~T6_E~0); 2001#L716-1 assume 0 == ~E_M~0;~E_M~0 := 1; 1671#L721-1 assume !(0 == ~E_1~0); 1672#L726-1 assume !(0 == ~E_2~0); 1433#L731-1 assume !(0 == ~E_3~0); 1434#L736-1 assume !(0 == ~E_4~0); 1524#L741-1 assume !(0 == ~E_5~0); 1525#L746-1 assume !(0 == ~E_6~0); 1866#L751-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1631#L336 assume !(1 == ~m_pc~0); 1565#L336-2 is_master_triggered_~__retres1~0 := 0; 1566#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1630#L348 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1543#L851 assume !(0 != activate_threads_~tmp~1); 1544#L851-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1547#L355 assume 1 == ~t1_pc~0; 1467#L356 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1468#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1522#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1523#L859 assume !(0 != activate_threads_~tmp___0~0); 1995#L859-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1996#L374 assume !(1 == ~t2_pc~0); 1777#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 1776#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1773#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1774#L867 assume !(0 != activate_threads_~tmp___1~0); 2097#L867-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2098#L393 assume 1 == ~t3_pc~0; 2089#L394 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2090#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2088#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1676#L875 assume !(0 != activate_threads_~tmp___2~0); 1661#L875-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1662#L412 assume 1 == ~t4_pc~0; 1613#L413 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1614#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1609#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1610#L883 assume !(0 != activate_threads_~tmp___3~0); 1884#L883-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1707#L431 assume !(1 == ~t5_pc~0); 1693#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 1694#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1706#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1861#L891 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 2048#L891-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1933#L450 assume 1 == ~t6_pc~0; 1934#L451 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 1931#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1932#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2033#L899 assume !(0 != activate_threads_~tmp___5~0); 2052#L899-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1429#L764 assume !(1 == ~M_E~0); 1430#L764-2 assume !(1 == ~T1_E~0); 1435#L769-1 assume !(1 == ~T2_E~0); 1549#L774-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1550#L779-1 assume !(1 == ~T4_E~0); 1890#L784-1 assume !(1 == ~T5_E~0); 1891#L789-1 assume !(1 == ~T6_E~0); 1709#L794-1 assume !(1 == ~E_M~0); 1710#L799-1 assume !(1 == ~E_1~0); 1997#L804-1 assume !(1 == ~E_2~0); 1665#L809-1 assume !(1 == ~E_3~0); 1666#L814-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1427#L819-1 assume !(1 == ~E_5~0); 1428#L824-1 assume !(1 == ~E_6~0); 1545#L829-1 assume { :end_inline_reset_delta_events } true; 1546#L1055-3 [2018-11-18 10:39:54,922 INFO L796 eck$LassoCheckResult]: Loop: 1546#L1055-3 assume true; 1943#L1055-1 assume !false; 1909#L1056 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 1534#L661 assume true; 1656#L567-1 assume !false; 1657#L568 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 1851#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 1424#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 2077#L558 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 2043#L572 assume !(0 != eval_~tmp~0); 1413#L676 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 1414#L470-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 1540#L686-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1505#L686-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1506#L691-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1878#L696-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1879#L701-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1715#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1716#L711-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1792#L716-3 assume !(0 == ~E_M~0); 1647#L721-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1648#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1417#L731-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1418#L736-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1537#L741-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1538#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1872#L751-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1873#L336-24 assume 1 == ~m_pc~0; 2055#L337-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2056#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2054#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1463#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1436#L851-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1437#L355-24 assume 1 == ~t1_pc~0; 1457#L356-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1458#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1455#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1456#L859-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1728#L859-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1729#L374-24 assume 1 == ~t2_pc~0; 1767#L375-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1768#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1765#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1766#L867-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1941#L867-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1942#L393-24 assume 1 == ~t3_pc~0; 1958#L394-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1959#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1956#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1957#L875-24 assume !(0 != activate_threads_~tmp___2~0); 2082#L875-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1640#L412-24 assume 1 == ~t4_pc~0; 1597#L413-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1598#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1595#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1596#L883-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1801#L883-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1802#L431-24 assume 1 == ~t5_pc~0; 1818#L432-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1819#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1816#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1817#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 2010#L891-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2013#L450-24 assume 1 == ~t6_pc~0; 2027#L451-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 1928#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1929#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2026#L899-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 2099#L899-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1415#L764-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1416#L764-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1419#L769-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1530#L774-3 assume !(1 == ~T3_E~0); 1531#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1868#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1869#L789-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1711#L794-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1712#L799-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1999#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1669#L809-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1670#L814-3 assume !(1 == ~E_4~0); 1431#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1432#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1551#L829-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 1552#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 1426#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 2078#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 2083#L1074 assume !(0 == start_simulation_~tmp~3); 2080#L1074-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 1857#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 1514#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 2079#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 1679#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1680#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 1730#L1037 start_simulation_#t~ret19 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 1894#L1087 assume !(0 != start_simulation_~tmp___0~1); 1546#L1055-3 [2018-11-18 10:39:54,922 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:39:54,922 INFO L82 PathProgramCache]: Analyzing trace with hash 765667843, now seen corresponding path program 1 times [2018-11-18 10:39:54,923 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:39:54,923 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:39:54,925 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:54,925 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:39:54,926 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:54,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:39:54,972 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:39:54,973 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:39:54,973 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:39:54,973 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 10:39:54,973 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:39:54,973 INFO L82 PathProgramCache]: Analyzing trace with hash 1028803645, now seen corresponding path program 1 times [2018-11-18 10:39:54,974 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:39:54,974 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:39:54,974 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:54,974 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:39:54,974 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:54,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:39:55,038 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:39:55,039 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:39:55,039 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:39:55,039 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 10:39:55,040 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:39:55,040 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:39:55,040 INFO L87 Difference]: Start difference. First operand 695 states and 1037 transitions. cyclomatic complexity: 343 Second operand 3 states. [2018-11-18 10:39:55,062 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:39:55,063 INFO L93 Difference]: Finished difference Result 695 states and 1036 transitions. [2018-11-18 10:39:55,063 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:39:55,064 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 695 states and 1036 transitions. [2018-11-18 10:39:55,068 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 604 [2018-11-18 10:39:55,072 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 695 states to 695 states and 1036 transitions. [2018-11-18 10:39:55,072 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 695 [2018-11-18 10:39:55,073 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 695 [2018-11-18 10:39:55,073 INFO L73 IsDeterministic]: Start isDeterministic. Operand 695 states and 1036 transitions. [2018-11-18 10:39:55,074 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:39:55,075 INFO L705 BuchiCegarLoop]: Abstraction has 695 states and 1036 transitions. [2018-11-18 10:39:55,076 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 695 states and 1036 transitions. [2018-11-18 10:39:55,086 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 695 to 695. [2018-11-18 10:39:55,086 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 695 states. [2018-11-18 10:39:55,088 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 695 states to 695 states and 1036 transitions. [2018-11-18 10:39:55,089 INFO L728 BuchiCegarLoop]: Abstraction has 695 states and 1036 transitions. [2018-11-18 10:39:55,089 INFO L608 BuchiCegarLoop]: Abstraction has 695 states and 1036 transitions. [2018-11-18 10:39:55,089 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ [2018-11-18 10:39:55,089 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 695 states and 1036 transitions. [2018-11-18 10:39:55,092 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 604 [2018-11-18 10:39:55,092 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:39:55,092 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:39:55,094 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:39:55,094 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:39:55,095 INFO L794 eck$LassoCheckResult]: Stem: 3415#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 3307#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 3078#L1018 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 3079#L470 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2908#L477 assume 1 == ~m_i~0;~m_st~0 := 0; 2909#L477-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2917#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3254#L487-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3255#L492-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3101#L497-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3102#L502-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3196#L507-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2923#L686 assume !(0 == ~M_E~0); 2924#L686-2 assume !(0 == ~T1_E~0); 2936#L691-1 assume !(0 == ~T2_E~0); 3267#L696-1 assume !(0 == ~T3_E~0); 3268#L701-1 assume !(0 == ~T4_E~0); 3110#L706-1 assume !(0 == ~T5_E~0); 3111#L711-1 assume !(0 == ~T6_E~0); 3398#L716-1 assume 0 == ~E_M~0;~E_M~0 := 1; 3068#L721-1 assume !(0 == ~E_1~0); 3069#L726-1 assume !(0 == ~E_2~0); 2830#L731-1 assume !(0 == ~E_3~0); 2831#L736-1 assume !(0 == ~E_4~0); 2921#L741-1 assume !(0 == ~E_5~0); 2922#L746-1 assume !(0 == ~E_6~0); 3261#L751-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3028#L336 assume !(1 == ~m_pc~0); 2962#L336-2 is_master_triggered_~__retres1~0 := 0; 2963#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3024#L348 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2940#L851 assume !(0 != activate_threads_~tmp~1); 2941#L851-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2944#L355 assume 1 == ~t1_pc~0; 2864#L356 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2865#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2919#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2920#L859 assume !(0 != activate_threads_~tmp___0~0); 3392#L859-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3393#L374 assume !(1 == ~t2_pc~0); 3174#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 3173#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3170#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3171#L867 assume !(0 != activate_threads_~tmp___1~0); 3494#L867-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3495#L393 assume 1 == ~t3_pc~0; 3486#L394 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3487#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3484#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3073#L875 assume !(0 != activate_threads_~tmp___2~0); 3058#L875-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3059#L412 assume 1 == ~t4_pc~0; 3008#L413 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3009#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3006#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3007#L883 assume !(0 != activate_threads_~tmp___3~0); 3279#L883-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3104#L431 assume !(1 == ~t5_pc~0); 3090#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 3091#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3103#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3258#L891 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 3445#L891-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 3330#L450 assume 1 == ~t6_pc~0; 3331#L451 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 3328#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 3329#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3429#L899 assume !(0 != activate_threads_~tmp___5~0); 3449#L899-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2826#L764 assume !(1 == ~M_E~0); 2827#L764-2 assume !(1 == ~T1_E~0); 2832#L769-1 assume !(1 == ~T2_E~0); 2946#L774-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2947#L779-1 assume !(1 == ~T4_E~0); 3286#L784-1 assume !(1 == ~T5_E~0); 3287#L789-1 assume !(1 == ~T6_E~0); 3106#L794-1 assume !(1 == ~E_M~0); 3107#L799-1 assume !(1 == ~E_1~0); 3394#L804-1 assume !(1 == ~E_2~0); 3060#L809-1 assume !(1 == ~E_3~0); 3061#L814-1 assume 1 == ~E_4~0;~E_4~0 := 2; 2824#L819-1 assume !(1 == ~E_5~0); 2825#L824-1 assume !(1 == ~E_6~0); 2942#L829-1 assume { :end_inline_reset_delta_events } true; 2943#L1055-3 [2018-11-18 10:39:55,095 INFO L796 eck$LassoCheckResult]: Loop: 2943#L1055-3 assume true; 3340#L1055-1 assume !false; 3306#L1056 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 2931#L661 assume true; 3053#L567-1 assume !false; 3054#L568 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 3246#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 2821#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 3474#L558 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 3440#L572 assume !(0 != eval_~tmp~0); 2810#L676 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 2811#L470-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 2937#L686-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2902#L686-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2903#L691-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3275#L696-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3276#L701-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3112#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3113#L711-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3189#L716-3 assume !(0 == ~E_M~0); 3044#L721-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3045#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2814#L731-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2815#L736-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2934#L741-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2935#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3269#L751-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3270#L336-24 assume 1 == ~m_pc~0; 3452#L337-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3453#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3451#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2860#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2833#L851-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2834#L355-24 assume 1 == ~t1_pc~0; 2855#L356-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2856#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2852#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2853#L859-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3125#L859-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3126#L374-24 assume 1 == ~t2_pc~0; 3165#L375-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3166#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3162#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3163#L867-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3338#L867-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3339#L393-24 assume 1 == ~t3_pc~0; 3355#L394-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3356#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3353#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3354#L875-24 assume !(0 != activate_threads_~tmp___2~0); 3479#L875-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3037#L412-24 assume 1 == ~t4_pc~0; 2996#L413-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2997#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2992#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2993#L883-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 3198#L883-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3199#L431-24 assume !(1 == ~t5_pc~0); 3217#L431-26 is_transmit5_triggered_~__retres1~5 := 0; 3216#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3213#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3214#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 3407#L891-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 3410#L450-24 assume 1 == ~t6_pc~0; 3424#L451-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 3325#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 3326#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3423#L899-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 3496#L899-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2812#L764-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2813#L764-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2816#L769-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2927#L774-3 assume !(1 == ~T3_E~0); 2928#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3265#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3266#L789-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3108#L794-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3109#L799-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3396#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3066#L809-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3067#L814-3 assume !(1 == ~E_4~0); 2828#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2829#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2948#L829-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 2949#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 2823#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 3475#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 3480#L1074 assume !(0 == start_simulation_~tmp~3); 3477#L1074-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 3256#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 2911#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 3476#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 3076#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3077#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 3127#L1037 start_simulation_#t~ret19 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 3292#L1087 assume !(0 != start_simulation_~tmp___0~1); 2943#L1055-3 [2018-11-18 10:39:55,095 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:39:55,096 INFO L82 PathProgramCache]: Analyzing trace with hash -73365819, now seen corresponding path program 1 times [2018-11-18 10:39:55,096 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:39:55,096 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:39:55,096 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:55,097 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:39:55,097 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:55,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:39:55,120 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:39:55,120 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:39:55,120 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:39:55,121 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 10:39:55,121 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:39:55,121 INFO L82 PathProgramCache]: Analyzing trace with hash 71875262, now seen corresponding path program 1 times [2018-11-18 10:39:55,121 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:39:55,121 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:39:55,122 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:55,122 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:39:55,122 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:55,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:39:55,170 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:39:55,170 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:39:55,170 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:39:55,170 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 10:39:55,170 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:39:55,171 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:39:55,171 INFO L87 Difference]: Start difference. First operand 695 states and 1036 transitions. cyclomatic complexity: 342 Second operand 3 states. [2018-11-18 10:39:55,186 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:39:55,186 INFO L93 Difference]: Finished difference Result 695 states and 1035 transitions. [2018-11-18 10:39:55,186 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:39:55,187 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 695 states and 1035 transitions. [2018-11-18 10:39:55,189 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 604 [2018-11-18 10:39:55,191 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 695 states to 695 states and 1035 transitions. [2018-11-18 10:39:55,191 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 695 [2018-11-18 10:39:55,192 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 695 [2018-11-18 10:39:55,192 INFO L73 IsDeterministic]: Start isDeterministic. Operand 695 states and 1035 transitions. [2018-11-18 10:39:55,193 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:39:55,193 INFO L705 BuchiCegarLoop]: Abstraction has 695 states and 1035 transitions. [2018-11-18 10:39:55,194 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 695 states and 1035 transitions. [2018-11-18 10:39:55,199 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 695 to 695. [2018-11-18 10:39:55,199 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 695 states. [2018-11-18 10:39:55,200 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 695 states to 695 states and 1035 transitions. [2018-11-18 10:39:55,200 INFO L728 BuchiCegarLoop]: Abstraction has 695 states and 1035 transitions. [2018-11-18 10:39:55,200 INFO L608 BuchiCegarLoop]: Abstraction has 695 states and 1035 transitions. [2018-11-18 10:39:55,200 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ [2018-11-18 10:39:55,201 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 695 states and 1035 transitions. [2018-11-18 10:39:55,202 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 604 [2018-11-18 10:39:55,203 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:39:55,203 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:39:55,204 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:39:55,204 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:39:55,205 INFO L794 eck$LassoCheckResult]: Stem: 4812#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 4704#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 4475#L1018 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 4476#L470 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4305#L477 assume 1 == ~m_i~0;~m_st~0 := 0; 4306#L477-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4314#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4653#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4654#L492-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4498#L497-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4499#L502-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4594#L507-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4320#L686 assume !(0 == ~M_E~0); 4321#L686-2 assume !(0 == ~T1_E~0); 4333#L691-1 assume !(0 == ~T2_E~0); 4664#L696-1 assume !(0 == ~T3_E~0); 4665#L701-1 assume !(0 == ~T4_E~0); 4507#L706-1 assume !(0 == ~T5_E~0); 4508#L711-1 assume !(0 == ~T6_E~0); 4795#L716-1 assume 0 == ~E_M~0;~E_M~0 := 1; 4465#L721-1 assume !(0 == ~E_1~0); 4466#L726-1 assume !(0 == ~E_2~0); 4227#L731-1 assume !(0 == ~E_3~0); 4228#L736-1 assume !(0 == ~E_4~0); 4318#L741-1 assume !(0 == ~E_5~0); 4319#L746-1 assume !(0 == ~E_6~0); 4658#L751-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4425#L336 assume !(1 == ~m_pc~0); 4359#L336-2 is_master_triggered_~__retres1~0 := 0; 4360#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4421#L348 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4337#L851 assume !(0 != activate_threads_~tmp~1); 4338#L851-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4341#L355 assume 1 == ~t1_pc~0; 4261#L356 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4262#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4316#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4317#L859 assume !(0 != activate_threads_~tmp___0~0); 4789#L859-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4790#L374 assume !(1 == ~t2_pc~0); 4571#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 4570#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4567#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4568#L867 assume !(0 != activate_threads_~tmp___1~0); 4891#L867-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4892#L393 assume 1 == ~t3_pc~0; 4883#L394 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4884#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4881#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4470#L875 assume !(0 != activate_threads_~tmp___2~0); 4455#L875-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4456#L412 assume 1 == ~t4_pc~0; 4405#L413 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4406#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4403#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4404#L883 assume !(0 != activate_threads_~tmp___3~0); 4676#L883-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4501#L431 assume !(1 == ~t5_pc~0); 4487#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 4488#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4500#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4655#L891 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 4842#L891-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4727#L450 assume 1 == ~t6_pc~0; 4728#L451 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 4725#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4726#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4827#L899 assume !(0 != activate_threads_~tmp___5~0); 4846#L899-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4223#L764 assume !(1 == ~M_E~0); 4224#L764-2 assume !(1 == ~T1_E~0); 4229#L769-1 assume !(1 == ~T2_E~0); 4343#L774-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4344#L779-1 assume !(1 == ~T4_E~0); 4683#L784-1 assume !(1 == ~T5_E~0); 4684#L789-1 assume !(1 == ~T6_E~0); 4503#L794-1 assume !(1 == ~E_M~0); 4504#L799-1 assume !(1 == ~E_1~0); 4791#L804-1 assume !(1 == ~E_2~0); 4457#L809-1 assume !(1 == ~E_3~0); 4458#L814-1 assume 1 == ~E_4~0;~E_4~0 := 2; 4221#L819-1 assume !(1 == ~E_5~0); 4222#L824-1 assume !(1 == ~E_6~0); 4339#L829-1 assume { :end_inline_reset_delta_events } true; 4340#L1055-3 [2018-11-18 10:39:55,205 INFO L796 eck$LassoCheckResult]: Loop: 4340#L1055-3 assume true; 4737#L1055-1 assume !false; 4703#L1056 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 4328#L661 assume true; 4450#L567-1 assume !false; 4451#L568 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 4643#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 4218#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 4871#L558 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 4837#L572 assume !(0 != eval_~tmp~0); 4207#L676 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 4208#L470-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 4334#L686-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4299#L686-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4300#L691-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4672#L696-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4673#L701-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4509#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4510#L711-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4586#L716-3 assume !(0 == ~E_M~0); 4441#L721-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4442#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4211#L731-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4212#L736-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4331#L741-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4332#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4666#L751-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4667#L336-24 assume 1 == ~m_pc~0; 4849#L337-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4850#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4848#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4260#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4230#L851-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4231#L355-24 assume 1 == ~t1_pc~0; 4252#L356-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4253#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4249#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4250#L859-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4522#L859-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4524#L374-24 assume 1 == ~t2_pc~0; 4562#L375-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4563#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4559#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4560#L867-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4735#L867-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4736#L393-24 assume 1 == ~t3_pc~0; 4752#L394-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4753#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4750#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4751#L875-24 assume !(0 != activate_threads_~tmp___2~0); 4876#L875-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4434#L412-24 assume 1 == ~t4_pc~0; 4393#L413-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4394#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4389#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4390#L883-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 4595#L883-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4596#L431-24 assume 1 == ~t5_pc~0; 4612#L432-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 4613#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4610#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4611#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 4804#L891-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4807#L450-24 assume 1 == ~t6_pc~0; 4821#L451-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 4722#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4723#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4820#L899-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 4893#L899-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4209#L764-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4210#L764-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4213#L769-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4324#L774-3 assume !(1 == ~T3_E~0); 4325#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4661#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4662#L789-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4505#L794-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4506#L799-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4793#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4462#L809-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4463#L814-3 assume !(1 == ~E_4~0); 4225#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4226#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4345#L829-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 4346#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 4220#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 4872#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 4877#L1074 assume !(0 == start_simulation_~tmp~3); 4874#L1074-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 4651#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 4308#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 4873#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 4473#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4474#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 4523#L1037 start_simulation_#t~ret19 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 4688#L1087 assume !(0 != start_simulation_~tmp___0~1); 4340#L1055-3 [2018-11-18 10:39:55,205 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:39:55,206 INFO L82 PathProgramCache]: Analyzing trace with hash -100431421, now seen corresponding path program 1 times [2018-11-18 10:39:55,206 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:39:55,206 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:39:55,206 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:55,207 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:39:55,207 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:55,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:39:55,244 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:39:55,244 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:39:55,244 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:39:55,245 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 10:39:55,245 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:39:55,245 INFO L82 PathProgramCache]: Analyzing trace with hash 1028803645, now seen corresponding path program 2 times [2018-11-18 10:39:55,245 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:39:55,245 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:39:55,246 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:55,246 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:39:55,246 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:55,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:39:55,306 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:39:55,306 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:39:55,306 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:39:55,307 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 10:39:55,307 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:39:55,307 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:39:55,307 INFO L87 Difference]: Start difference. First operand 695 states and 1035 transitions. cyclomatic complexity: 341 Second operand 3 states. [2018-11-18 10:39:55,320 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:39:55,320 INFO L93 Difference]: Finished difference Result 695 states and 1034 transitions. [2018-11-18 10:39:55,324 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:39:55,324 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 695 states and 1034 transitions. [2018-11-18 10:39:55,327 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 604 [2018-11-18 10:39:55,330 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 695 states to 695 states and 1034 transitions. [2018-11-18 10:39:55,330 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 695 [2018-11-18 10:39:55,331 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 695 [2018-11-18 10:39:55,331 INFO L73 IsDeterministic]: Start isDeterministic. Operand 695 states and 1034 transitions. [2018-11-18 10:39:55,332 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:39:55,332 INFO L705 BuchiCegarLoop]: Abstraction has 695 states and 1034 transitions. [2018-11-18 10:39:55,333 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 695 states and 1034 transitions. [2018-11-18 10:39:55,340 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 695 to 695. [2018-11-18 10:39:55,340 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 695 states. [2018-11-18 10:39:55,342 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 695 states to 695 states and 1034 transitions. [2018-11-18 10:39:55,342 INFO L728 BuchiCegarLoop]: Abstraction has 695 states and 1034 transitions. [2018-11-18 10:39:55,342 INFO L608 BuchiCegarLoop]: Abstraction has 695 states and 1034 transitions. [2018-11-18 10:39:55,342 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ [2018-11-18 10:39:55,342 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 695 states and 1034 transitions. [2018-11-18 10:39:55,345 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 604 [2018-11-18 10:39:55,345 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:39:55,345 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:39:55,346 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:39:55,346 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:39:55,346 INFO L794 eck$LassoCheckResult]: Stem: 6209#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 6101#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 5872#L1018 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 5873#L470 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5702#L477 assume 1 == ~m_i~0;~m_st~0 := 0; 5703#L477-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5711#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6050#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6051#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5895#L497-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5896#L502-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5991#L507-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5717#L686 assume !(0 == ~M_E~0); 5718#L686-2 assume !(0 == ~T1_E~0); 5730#L691-1 assume !(0 == ~T2_E~0); 6061#L696-1 assume !(0 == ~T3_E~0); 6062#L701-1 assume !(0 == ~T4_E~0); 5904#L706-1 assume !(0 == ~T5_E~0); 5905#L711-1 assume !(0 == ~T6_E~0); 6192#L716-1 assume 0 == ~E_M~0;~E_M~0 := 1; 5862#L721-1 assume !(0 == ~E_1~0); 5863#L726-1 assume !(0 == ~E_2~0); 5624#L731-1 assume !(0 == ~E_3~0); 5625#L736-1 assume !(0 == ~E_4~0); 5715#L741-1 assume !(0 == ~E_5~0); 5716#L746-1 assume !(0 == ~E_6~0); 6057#L751-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5822#L336 assume !(1 == ~m_pc~0); 5756#L336-2 is_master_triggered_~__retres1~0 := 0; 5757#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5821#L348 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5734#L851 assume !(0 != activate_threads_~tmp~1); 5735#L851-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5738#L355 assume 1 == ~t1_pc~0; 5660#L356 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5661#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5713#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5714#L859 assume !(0 != activate_threads_~tmp___0~0); 6186#L859-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6187#L374 assume !(1 == ~t2_pc~0); 5968#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 5967#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5964#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5965#L867 assume !(0 != activate_threads_~tmp___1~0); 6288#L867-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6289#L393 assume 1 == ~t3_pc~0; 6280#L394 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 6281#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6279#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5867#L875 assume !(0 != activate_threads_~tmp___2~0); 5852#L875-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5853#L412 assume 1 == ~t4_pc~0; 5804#L413 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5805#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5800#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5801#L883 assume !(0 != activate_threads_~tmp___3~0); 6075#L883-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5898#L431 assume !(1 == ~t5_pc~0); 5884#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 5885#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5897#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6052#L891 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 6239#L891-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 6124#L450 assume 1 == ~t6_pc~0; 6125#L451 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 6122#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 6123#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6224#L899 assume !(0 != activate_threads_~tmp___5~0); 6243#L899-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5620#L764 assume !(1 == ~M_E~0); 5621#L764-2 assume !(1 == ~T1_E~0); 5626#L769-1 assume !(1 == ~T2_E~0); 5740#L774-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5741#L779-1 assume !(1 == ~T4_E~0); 6081#L784-1 assume !(1 == ~T5_E~0); 6082#L789-1 assume !(1 == ~T6_E~0); 5900#L794-1 assume !(1 == ~E_M~0); 5901#L799-1 assume !(1 == ~E_1~0); 6188#L804-1 assume !(1 == ~E_2~0); 5856#L809-1 assume !(1 == ~E_3~0); 5857#L814-1 assume 1 == ~E_4~0;~E_4~0 := 2; 5618#L819-1 assume !(1 == ~E_5~0); 5619#L824-1 assume !(1 == ~E_6~0); 5736#L829-1 assume { :end_inline_reset_delta_events } true; 5737#L1055-3 [2018-11-18 10:39:55,347 INFO L796 eck$LassoCheckResult]: Loop: 5737#L1055-3 assume true; 6134#L1055-1 assume !false; 6100#L1056 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 5725#L661 assume true; 5847#L567-1 assume !false; 5848#L568 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 6042#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 5615#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 6268#L558 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 6234#L572 assume !(0 != eval_~tmp~0); 5604#L676 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 5605#L470-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 5732#L686-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5696#L686-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5697#L691-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6069#L696-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6070#L701-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5906#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5907#L711-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5983#L716-3 assume !(0 == ~E_M~0); 5838#L721-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5839#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5608#L731-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5609#L736-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5728#L741-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5729#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6063#L751-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6064#L336-24 assume 1 == ~m_pc~0; 6246#L337-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 6247#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6245#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5654#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5627#L851-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5628#L355-24 assume 1 == ~t1_pc~0; 5649#L356-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5650#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5646#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5647#L859-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5919#L859-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5920#L374-24 assume 1 == ~t2_pc~0; 5958#L375-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5959#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5956#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5957#L867-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6132#L867-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6133#L393-24 assume 1 == ~t3_pc~0; 6149#L394-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 6150#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6147#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6148#L875-24 assume !(0 != activate_threads_~tmp___2~0); 6273#L875-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5831#L412-24 assume !(1 == ~t4_pc~0); 5792#L412-26 is_transmit4_triggered_~__retres1~4 := 0; 5791#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5786#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5787#L883-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5992#L883-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5993#L431-24 assume 1 == ~t5_pc~0; 6009#L432-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 6010#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6007#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6008#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 6201#L891-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 6204#L450-24 assume 1 == ~t6_pc~0; 6218#L451-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 6119#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 6120#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6217#L899-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 6290#L899-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5606#L764-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5607#L764-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5610#L769-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5721#L774-3 assume !(1 == ~T3_E~0); 5722#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6059#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6060#L789-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5902#L794-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5903#L799-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6190#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5860#L809-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5861#L814-3 assume !(1 == ~E_4~0); 5622#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5623#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5742#L829-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 5743#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 5617#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 6269#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 6274#L1074 assume !(0 == start_simulation_~tmp~3); 6271#L1074-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 6048#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 5705#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 6270#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 5870#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5871#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 5921#L1037 start_simulation_#t~ret19 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 6085#L1087 assume !(0 != start_simulation_~tmp___0~1); 5737#L1055-3 [2018-11-18 10:39:55,347 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:39:55,347 INFO L82 PathProgramCache]: Analyzing trace with hash 1976905477, now seen corresponding path program 1 times [2018-11-18 10:39:55,347 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:39:55,347 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:39:55,348 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:55,348 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:39:55,348 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:55,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:39:55,395 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:39:55,395 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:39:55,395 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:39:55,395 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 10:39:55,395 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:39:55,396 INFO L82 PathProgramCache]: Analyzing trace with hash 155325950, now seen corresponding path program 1 times [2018-11-18 10:39:55,396 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:39:55,396 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:39:55,396 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:55,397 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:39:55,397 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:55,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:39:55,450 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:39:55,450 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:39:55,450 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:39:55,451 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 10:39:55,451 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:39:55,451 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:39:55,451 INFO L87 Difference]: Start difference. First operand 695 states and 1034 transitions. cyclomatic complexity: 340 Second operand 3 states. [2018-11-18 10:39:55,461 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:39:55,462 INFO L93 Difference]: Finished difference Result 695 states and 1033 transitions. [2018-11-18 10:39:55,463 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:39:55,463 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 695 states and 1033 transitions. [2018-11-18 10:39:55,466 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 604 [2018-11-18 10:39:55,468 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 695 states to 695 states and 1033 transitions. [2018-11-18 10:39:55,468 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 695 [2018-11-18 10:39:55,469 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 695 [2018-11-18 10:39:55,469 INFO L73 IsDeterministic]: Start isDeterministic. Operand 695 states and 1033 transitions. [2018-11-18 10:39:55,470 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:39:55,470 INFO L705 BuchiCegarLoop]: Abstraction has 695 states and 1033 transitions. [2018-11-18 10:39:55,471 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 695 states and 1033 transitions. [2018-11-18 10:39:55,477 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 695 to 695. [2018-11-18 10:39:55,478 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 695 states. [2018-11-18 10:39:55,479 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 695 states to 695 states and 1033 transitions. [2018-11-18 10:39:55,479 INFO L728 BuchiCegarLoop]: Abstraction has 695 states and 1033 transitions. [2018-11-18 10:39:55,479 INFO L608 BuchiCegarLoop]: Abstraction has 695 states and 1033 transitions. [2018-11-18 10:39:55,479 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ [2018-11-18 10:39:55,479 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 695 states and 1033 transitions. [2018-11-18 10:39:55,482 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 604 [2018-11-18 10:39:55,482 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:39:55,482 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:39:55,483 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:39:55,483 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:39:55,484 INFO L794 eck$LassoCheckResult]: Stem: 7606#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 7498#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 7269#L1018 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 7270#L470 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7099#L477 assume 1 == ~m_i~0;~m_st~0 := 0; 7100#L477-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7108#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7445#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7446#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7292#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7293#L502-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7387#L507-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7114#L686 assume !(0 == ~M_E~0); 7115#L686-2 assume !(0 == ~T1_E~0); 7127#L691-1 assume !(0 == ~T2_E~0); 7458#L696-1 assume !(0 == ~T3_E~0); 7459#L701-1 assume !(0 == ~T4_E~0); 7301#L706-1 assume !(0 == ~T5_E~0); 7302#L711-1 assume !(0 == ~T6_E~0); 7589#L716-1 assume 0 == ~E_M~0;~E_M~0 := 1; 7259#L721-1 assume !(0 == ~E_1~0); 7260#L726-1 assume !(0 == ~E_2~0); 7021#L731-1 assume !(0 == ~E_3~0); 7022#L736-1 assume !(0 == ~E_4~0); 7112#L741-1 assume !(0 == ~E_5~0); 7113#L746-1 assume !(0 == ~E_6~0); 7452#L751-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7219#L336 assume !(1 == ~m_pc~0); 7153#L336-2 is_master_triggered_~__retres1~0 := 0; 7154#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7215#L348 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 7131#L851 assume !(0 != activate_threads_~tmp~1); 7132#L851-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7135#L355 assume 1 == ~t1_pc~0; 7055#L356 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 7056#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7110#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7111#L859 assume !(0 != activate_threads_~tmp___0~0); 7583#L859-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7584#L374 assume !(1 == ~t2_pc~0); 7365#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 7364#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7361#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7362#L867 assume !(0 != activate_threads_~tmp___1~0); 7685#L867-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7686#L393 assume 1 == ~t3_pc~0; 7677#L394 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 7678#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7675#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7264#L875 assume !(0 != activate_threads_~tmp___2~0); 7249#L875-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7250#L412 assume 1 == ~t4_pc~0; 7199#L413 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7200#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7197#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7198#L883 assume !(0 != activate_threads_~tmp___3~0); 7470#L883-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7295#L431 assume !(1 == ~t5_pc~0); 7281#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 7282#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7294#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7449#L891 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 7636#L891-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7521#L450 assume 1 == ~t6_pc~0; 7522#L451 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 7519#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 7520#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7620#L899 assume !(0 != activate_threads_~tmp___5~0); 7640#L899-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7017#L764 assume !(1 == ~M_E~0); 7018#L764-2 assume !(1 == ~T1_E~0); 7023#L769-1 assume !(1 == ~T2_E~0); 7137#L774-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7138#L779-1 assume !(1 == ~T4_E~0); 7477#L784-1 assume !(1 == ~T5_E~0); 7478#L789-1 assume !(1 == ~T6_E~0); 7297#L794-1 assume !(1 == ~E_M~0); 7298#L799-1 assume !(1 == ~E_1~0); 7585#L804-1 assume !(1 == ~E_2~0); 7251#L809-1 assume !(1 == ~E_3~0); 7252#L814-1 assume 1 == ~E_4~0;~E_4~0 := 2; 7015#L819-1 assume !(1 == ~E_5~0); 7016#L824-1 assume !(1 == ~E_6~0); 7133#L829-1 assume { :end_inline_reset_delta_events } true; 7134#L1055-3 [2018-11-18 10:39:55,484 INFO L796 eck$LassoCheckResult]: Loop: 7134#L1055-3 assume true; 7531#L1055-1 assume !false; 7497#L1056 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 7122#L661 assume true; 7244#L567-1 assume !false; 7245#L568 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 7437#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 7012#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 7665#L558 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 7631#L572 assume !(0 != eval_~tmp~0); 7001#L676 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 7002#L470-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 7128#L686-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7093#L686-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7094#L691-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7466#L696-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7467#L701-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7303#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7304#L711-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7380#L716-3 assume !(0 == ~E_M~0); 7235#L721-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7236#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7005#L731-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7006#L736-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7125#L741-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7126#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7460#L751-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7461#L336-24 assume 1 == ~m_pc~0; 7643#L337-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 7644#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7642#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 7051#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 7024#L851-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7025#L355-24 assume 1 == ~t1_pc~0; 7046#L356-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 7047#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7043#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7044#L859-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7316#L859-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7317#L374-24 assume 1 == ~t2_pc~0; 7356#L375-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7357#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7353#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7354#L867-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7529#L867-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7530#L393-24 assume 1 == ~t3_pc~0; 7546#L394-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 7547#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7544#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7545#L875-24 assume !(0 != activate_threads_~tmp___2~0); 7670#L875-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7228#L412-24 assume 1 == ~t4_pc~0; 7187#L413-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7188#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7183#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7184#L883-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 7389#L883-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7390#L431-24 assume !(1 == ~t5_pc~0); 7408#L431-26 is_transmit5_triggered_~__retres1~5 := 0; 7407#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7404#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7405#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 7598#L891-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7601#L450-24 assume !(1 == ~t6_pc~0); 7616#L450-26 is_transmit6_triggered_~__retres1~6 := 0; 7516#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 7517#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7614#L899-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 7687#L899-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7003#L764-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7004#L764-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7007#L769-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7118#L774-3 assume !(1 == ~T3_E~0); 7119#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7456#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7457#L789-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7299#L794-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7300#L799-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7587#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7257#L809-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7258#L814-3 assume !(1 == ~E_4~0); 7019#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7020#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7139#L829-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 7140#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 7014#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 7666#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 7671#L1074 assume !(0 == start_simulation_~tmp~3); 7668#L1074-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 7447#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 7102#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 7667#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 7267#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7268#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 7318#L1037 start_simulation_#t~ret19 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 7483#L1087 assume !(0 != start_simulation_~tmp___0~1); 7134#L1055-3 [2018-11-18 10:39:55,484 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:39:55,484 INFO L82 PathProgramCache]: Analyzing trace with hash 242801027, now seen corresponding path program 1 times [2018-11-18 10:39:55,484 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:39:55,484 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:39:55,485 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:55,485 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:39:55,485 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:55,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:39:55,523 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:39:55,524 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:39:55,524 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:39:55,524 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 10:39:55,524 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:39:55,524 INFO L82 PathProgramCache]: Analyzing trace with hash -1504682497, now seen corresponding path program 1 times [2018-11-18 10:39:55,524 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:39:55,524 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:39:55,525 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:55,525 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:39:55,525 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:55,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:39:55,562 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:39:55,563 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:39:55,563 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:39:55,563 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 10:39:55,563 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:39:55,563 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:39:55,564 INFO L87 Difference]: Start difference. First operand 695 states and 1033 transitions. cyclomatic complexity: 339 Second operand 3 states. [2018-11-18 10:39:55,582 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:39:55,582 INFO L93 Difference]: Finished difference Result 695 states and 1032 transitions. [2018-11-18 10:39:55,583 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:39:55,583 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 695 states and 1032 transitions. [2018-11-18 10:39:55,586 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 604 [2018-11-18 10:39:55,589 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 695 states to 695 states and 1032 transitions. [2018-11-18 10:39:55,589 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 695 [2018-11-18 10:39:55,589 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 695 [2018-11-18 10:39:55,589 INFO L73 IsDeterministic]: Start isDeterministic. Operand 695 states and 1032 transitions. [2018-11-18 10:39:55,590 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:39:55,590 INFO L705 BuchiCegarLoop]: Abstraction has 695 states and 1032 transitions. [2018-11-18 10:39:55,591 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 695 states and 1032 transitions. [2018-11-18 10:39:55,598 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 695 to 695. [2018-11-18 10:39:55,598 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 695 states. [2018-11-18 10:39:55,600 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 695 states to 695 states and 1032 transitions. [2018-11-18 10:39:55,600 INFO L728 BuchiCegarLoop]: Abstraction has 695 states and 1032 transitions. [2018-11-18 10:39:55,600 INFO L608 BuchiCegarLoop]: Abstraction has 695 states and 1032 transitions. [2018-11-18 10:39:55,600 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ [2018-11-18 10:39:55,600 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 695 states and 1032 transitions. [2018-11-18 10:39:55,602 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 604 [2018-11-18 10:39:55,602 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:39:55,602 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:39:55,604 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:39:55,604 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:39:55,604 INFO L794 eck$LassoCheckResult]: Stem: 9003#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 8895#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 8666#L1018 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 8667#L470 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8496#L477 assume 1 == ~m_i~0;~m_st~0 := 0; 8497#L477-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8505#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8844#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8845#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8689#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8690#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 8785#L507-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8511#L686 assume !(0 == ~M_E~0); 8512#L686-2 assume !(0 == ~T1_E~0); 8524#L691-1 assume !(0 == ~T2_E~0); 8855#L696-1 assume !(0 == ~T3_E~0); 8856#L701-1 assume !(0 == ~T4_E~0); 8698#L706-1 assume !(0 == ~T5_E~0); 8699#L711-1 assume !(0 == ~T6_E~0); 8986#L716-1 assume 0 == ~E_M~0;~E_M~0 := 1; 8656#L721-1 assume !(0 == ~E_1~0); 8657#L726-1 assume !(0 == ~E_2~0); 8418#L731-1 assume !(0 == ~E_3~0); 8419#L736-1 assume !(0 == ~E_4~0); 8509#L741-1 assume !(0 == ~E_5~0); 8510#L746-1 assume !(0 == ~E_6~0); 8850#L751-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8616#L336 assume !(1 == ~m_pc~0); 8550#L336-2 is_master_triggered_~__retres1~0 := 0; 8551#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8612#L348 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 8528#L851 assume !(0 != activate_threads_~tmp~1); 8529#L851-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8532#L355 assume 1 == ~t1_pc~0; 8452#L356 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 8453#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8507#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 8508#L859 assume !(0 != activate_threads_~tmp___0~0); 8980#L859-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8981#L374 assume !(1 == ~t2_pc~0); 8762#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 8761#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8758#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 8759#L867 assume !(0 != activate_threads_~tmp___1~0); 9082#L867-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9083#L393 assume 1 == ~t3_pc~0; 9074#L394 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 9075#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9072#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 8661#L875 assume !(0 != activate_threads_~tmp___2~0); 8646#L875-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8647#L412 assume 1 == ~t4_pc~0; 8596#L413 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 8597#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8594#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 8595#L883 assume !(0 != activate_threads_~tmp___3~0); 8869#L883-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8692#L431 assume !(1 == ~t5_pc~0); 8678#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 8679#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8691#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 8846#L891 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 9033#L891-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 8918#L450 assume 1 == ~t6_pc~0; 8919#L451 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 8916#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 8917#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 9018#L899 assume !(0 != activate_threads_~tmp___5~0); 9037#L899-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8414#L764 assume !(1 == ~M_E~0); 8415#L764-2 assume !(1 == ~T1_E~0); 8420#L769-1 assume !(1 == ~T2_E~0); 8534#L774-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8535#L779-1 assume !(1 == ~T4_E~0); 8875#L784-1 assume !(1 == ~T5_E~0); 8876#L789-1 assume !(1 == ~T6_E~0); 8694#L794-1 assume !(1 == ~E_M~0); 8695#L799-1 assume !(1 == ~E_1~0); 8982#L804-1 assume !(1 == ~E_2~0); 8648#L809-1 assume !(1 == ~E_3~0); 8649#L814-1 assume 1 == ~E_4~0;~E_4~0 := 2; 8412#L819-1 assume !(1 == ~E_5~0); 8413#L824-1 assume !(1 == ~E_6~0); 8530#L829-1 assume { :end_inline_reset_delta_events } true; 8531#L1055-3 [2018-11-18 10:39:55,604 INFO L796 eck$LassoCheckResult]: Loop: 8531#L1055-3 assume true; 8928#L1055-1 assume !false; 8894#L1056 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 8519#L661 assume true; 8641#L567-1 assume !false; 8642#L568 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 8834#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 8409#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 9062#L558 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 9028#L572 assume !(0 != eval_~tmp~0); 8398#L676 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 8399#L470-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 8525#L686-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8490#L686-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8491#L691-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8863#L696-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8864#L701-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8700#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8701#L711-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8777#L716-3 assume !(0 == ~E_M~0); 8632#L721-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8633#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8402#L731-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8403#L736-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8522#L741-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8523#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8857#L751-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8858#L336-24 assume 1 == ~m_pc~0; 9040#L337-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 9041#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9039#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 8451#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 8421#L851-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8422#L355-24 assume 1 == ~t1_pc~0; 8443#L356-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 8444#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8440#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 8441#L859-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 8713#L859-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8715#L374-24 assume 1 == ~t2_pc~0; 8753#L375-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 8754#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8750#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 8751#L867-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 8926#L867-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8927#L393-24 assume !(1 == ~t3_pc~0); 8945#L393-26 is_transmit3_triggered_~__retres1~3 := 0; 8944#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8941#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 8942#L875-24 assume !(0 != activate_threads_~tmp___2~0); 9067#L875-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8625#L412-24 assume 1 == ~t4_pc~0; 8582#L413-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 8583#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8580#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 8581#L883-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 8786#L883-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8787#L431-24 assume 1 == ~t5_pc~0; 8803#L432-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 8804#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8801#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 8802#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 8995#L891-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 8998#L450-24 assume 1 == ~t6_pc~0; 9012#L451-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 8913#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 8914#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 9011#L899-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 9084#L899-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8400#L764-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8401#L764-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8404#L769-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8515#L774-3 assume !(1 == ~T3_E~0); 8516#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8852#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8853#L789-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8696#L794-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8697#L799-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8984#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8653#L809-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8654#L814-3 assume !(1 == ~E_4~0); 8416#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8417#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8536#L829-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 8537#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 8411#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 9063#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 9068#L1074 assume !(0 == start_simulation_~tmp~3); 9065#L1074-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 8842#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 8499#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 9064#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 8664#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 8665#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 8714#L1037 start_simulation_#t~ret19 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 8879#L1087 assume !(0 != start_simulation_~tmp___0~1); 8531#L1055-3 [2018-11-18 10:39:55,604 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:39:55,604 INFO L82 PathProgramCache]: Analyzing trace with hash -644421819, now seen corresponding path program 1 times [2018-11-18 10:39:55,605 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:39:55,605 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:39:55,605 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:55,605 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:39:55,606 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:55,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:39:55,643 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:39:55,644 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:39:55,644 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 10:39:55,644 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 10:39:55,644 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:39:55,644 INFO L82 PathProgramCache]: Analyzing trace with hash -1072037570, now seen corresponding path program 1 times [2018-11-18 10:39:55,645 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:39:55,645 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:39:55,645 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:55,645 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:39:55,645 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:55,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:39:55,672 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:39:55,672 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:39:55,672 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:39:55,673 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 10:39:55,673 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:39:55,673 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:39:55,673 INFO L87 Difference]: Start difference. First operand 695 states and 1032 transitions. cyclomatic complexity: 338 Second operand 3 states. [2018-11-18 10:39:55,738 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:39:55,738 INFO L93 Difference]: Finished difference Result 695 states and 1018 transitions. [2018-11-18 10:39:55,738 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:39:55,739 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 695 states and 1018 transitions. [2018-11-18 10:39:55,741 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 604 [2018-11-18 10:39:55,744 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 695 states to 695 states and 1018 transitions. [2018-11-18 10:39:55,744 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 695 [2018-11-18 10:39:55,745 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 695 [2018-11-18 10:39:55,745 INFO L73 IsDeterministic]: Start isDeterministic. Operand 695 states and 1018 transitions. [2018-11-18 10:39:55,746 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:39:55,746 INFO L705 BuchiCegarLoop]: Abstraction has 695 states and 1018 transitions. [2018-11-18 10:39:55,747 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 695 states and 1018 transitions. [2018-11-18 10:39:55,753 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 695 to 695. [2018-11-18 10:39:55,753 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 695 states. [2018-11-18 10:39:55,754 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 695 states to 695 states and 1018 transitions. [2018-11-18 10:39:55,755 INFO L728 BuchiCegarLoop]: Abstraction has 695 states and 1018 transitions. [2018-11-18 10:39:55,755 INFO L608 BuchiCegarLoop]: Abstraction has 695 states and 1018 transitions. [2018-11-18 10:39:55,755 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ [2018-11-18 10:39:55,755 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 695 states and 1018 transitions. [2018-11-18 10:39:55,757 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 604 [2018-11-18 10:39:55,757 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:39:55,757 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:39:55,758 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:39:55,758 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:39:55,759 INFO L794 eck$LassoCheckResult]: Stem: 10400#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 10292#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 10063#L1018 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 10064#L470 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9893#L477 assume 1 == ~m_i~0;~m_st~0 := 0; 9894#L477-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9902#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10241#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10242#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10086#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10087#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10182#L507-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9910#L686 assume !(0 == ~M_E~0); 9911#L686-2 assume !(0 == ~T1_E~0); 9921#L691-1 assume !(0 == ~T2_E~0); 10252#L696-1 assume !(0 == ~T3_E~0); 10253#L701-1 assume !(0 == ~T4_E~0); 10095#L706-1 assume !(0 == ~T5_E~0); 10096#L711-1 assume !(0 == ~T6_E~0); 10383#L716-1 assume !(0 == ~E_M~0); 10053#L721-1 assume !(0 == ~E_1~0); 10054#L726-1 assume !(0 == ~E_2~0); 9815#L731-1 assume !(0 == ~E_3~0); 9816#L736-1 assume !(0 == ~E_4~0); 9906#L741-1 assume !(0 == ~E_5~0); 9907#L746-1 assume !(0 == ~E_6~0); 10248#L751-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10013#L336 assume !(1 == ~m_pc~0); 9947#L336-2 is_master_triggered_~__retres1~0 := 0; 9948#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10012#L348 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 9925#L851 assume !(0 != activate_threads_~tmp~1); 9926#L851-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9929#L355 assume 1 == ~t1_pc~0; 9851#L356 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 9852#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9904#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 9905#L859 assume !(0 != activate_threads_~tmp___0~0); 10377#L859-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10378#L374 assume !(1 == ~t2_pc~0); 10159#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 10158#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10155#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 10156#L867 assume !(0 != activate_threads_~tmp___1~0); 10479#L867-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10480#L393 assume 1 == ~t3_pc~0; 10471#L394 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 10472#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10470#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 10058#L875 assume !(0 != activate_threads_~tmp___2~0); 10043#L875-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 10044#L412 assume 1 == ~t4_pc~0; 9995#L413 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9996#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9991#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9992#L883 assume !(0 != activate_threads_~tmp___3~0); 10266#L883-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10089#L431 assume !(1 == ~t5_pc~0); 10075#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 10076#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 10088#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 10243#L891 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 10430#L891-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 10315#L450 assume 1 == ~t6_pc~0; 10316#L451 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 10313#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 10314#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 10415#L899 assume !(0 != activate_threads_~tmp___5~0); 10434#L899-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9811#L764 assume !(1 == ~M_E~0); 9812#L764-2 assume !(1 == ~T1_E~0); 9817#L769-1 assume !(1 == ~T2_E~0); 9931#L774-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9932#L779-1 assume !(1 == ~T4_E~0); 10272#L784-1 assume !(1 == ~T5_E~0); 10273#L789-1 assume !(1 == ~T6_E~0); 10091#L794-1 assume !(1 == ~E_M~0); 10092#L799-1 assume !(1 == ~E_1~0); 10379#L804-1 assume !(1 == ~E_2~0); 10047#L809-1 assume !(1 == ~E_3~0); 10048#L814-1 assume 1 == ~E_4~0;~E_4~0 := 2; 9809#L819-1 assume !(1 == ~E_5~0); 9810#L824-1 assume !(1 == ~E_6~0); 9927#L829-1 assume { :end_inline_reset_delta_events } true; 9928#L1055-3 [2018-11-18 10:39:55,759 INFO L796 eck$LassoCheckResult]: Loop: 9928#L1055-3 assume true; 10325#L1055-1 assume !false; 10291#L1056 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 9916#L661 assume true; 10038#L567-1 assume !false; 10039#L568 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 10235#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 9806#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 10458#L558 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 10425#L572 assume !(0 != eval_~tmp~0); 9795#L676 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 9796#L470-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 9923#L686-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9887#L686-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9888#L691-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10260#L696-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10261#L701-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10097#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10098#L711-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10174#L716-3 assume !(0 == ~E_M~0); 10029#L721-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10030#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9799#L731-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9800#L736-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9919#L741-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9920#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10254#L751-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10255#L336-24 assume !(1 == ~m_pc~0); 10438#L336-26 is_master_triggered_~__retres1~0 := 0; 10460#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10436#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 9845#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 9818#L851-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9819#L355-24 assume 1 == ~t1_pc~0; 9840#L356-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 9841#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9837#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 9838#L859-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 10110#L859-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10111#L374-24 assume 1 == ~t2_pc~0; 10150#L375-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 10151#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10147#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 10148#L867-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 10323#L867-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10324#L393-24 assume 1 == ~t3_pc~0; 10340#L394-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 10341#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10338#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 10339#L875-24 assume !(0 != activate_threads_~tmp___2~0); 10464#L875-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 10022#L412-24 assume 1 == ~t4_pc~0; 9981#L413-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9982#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9977#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9978#L883-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 10183#L883-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10184#L431-24 assume 1 == ~t5_pc~0; 10200#L432-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 10201#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 10198#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 10199#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 10392#L891-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 10395#L450-24 assume 1 == ~t6_pc~0; 10409#L451-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 10310#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 10311#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 10408#L899-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 10481#L899-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9797#L764-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9798#L764-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9801#L769-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9912#L774-3 assume !(1 == ~T3_E~0); 9913#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10250#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10251#L789-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10093#L794-3 assume !(1 == ~E_M~0); 10094#L799-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10381#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10051#L809-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10052#L814-3 assume !(1 == ~E_4~0); 9813#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9814#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9933#L829-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 9934#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 9808#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 10459#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 10465#L1074 assume !(0 == start_simulation_~tmp~3); 10462#L1074-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 10239#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 9896#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 10461#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 10061#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 10062#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 10112#L1037 start_simulation_#t~ret19 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 10277#L1087 assume !(0 != start_simulation_~tmp___0~1); 9928#L1055-3 [2018-11-18 10:39:55,759 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:39:55,759 INFO L82 PathProgramCache]: Analyzing trace with hash 1964365639, now seen corresponding path program 1 times [2018-11-18 10:39:55,759 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:39:55,759 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:39:55,760 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:55,760 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:39:55,760 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:55,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:39:55,790 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:39:55,790 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:39:55,791 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 10:39:55,791 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 10:39:55,791 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:39:55,791 INFO L82 PathProgramCache]: Analyzing trace with hash 1348784060, now seen corresponding path program 1 times [2018-11-18 10:39:55,791 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:39:55,791 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:39:55,792 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:55,792 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:39:55,792 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:55,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:39:55,814 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:39:55,815 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:39:55,815 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:39:55,815 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 10:39:55,815 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:39:55,815 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:39:55,815 INFO L87 Difference]: Start difference. First operand 695 states and 1018 transitions. cyclomatic complexity: 324 Second operand 3 states. [2018-11-18 10:39:55,885 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:39:55,886 INFO L93 Difference]: Finished difference Result 1238 states and 1798 transitions. [2018-11-18 10:39:55,887 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:39:55,887 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1238 states and 1798 transitions. [2018-11-18 10:39:55,893 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1146 [2018-11-18 10:39:55,897 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1238 states to 1238 states and 1798 transitions. [2018-11-18 10:39:55,897 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1238 [2018-11-18 10:39:55,898 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1238 [2018-11-18 10:39:55,898 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1238 states and 1798 transitions. [2018-11-18 10:39:55,900 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:39:55,900 INFO L705 BuchiCegarLoop]: Abstraction has 1238 states and 1798 transitions. [2018-11-18 10:39:55,901 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1238 states and 1798 transitions. [2018-11-18 10:39:55,913 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1238 to 1235. [2018-11-18 10:39:55,913 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1235 states. [2018-11-18 10:39:55,916 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1235 states to 1235 states and 1795 transitions. [2018-11-18 10:39:55,916 INFO L728 BuchiCegarLoop]: Abstraction has 1235 states and 1795 transitions. [2018-11-18 10:39:55,916 INFO L608 BuchiCegarLoop]: Abstraction has 1235 states and 1795 transitions. [2018-11-18 10:39:55,916 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ [2018-11-18 10:39:55,916 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1235 states and 1795 transitions. [2018-11-18 10:39:55,920 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1143 [2018-11-18 10:39:55,920 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:39:55,920 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:39:55,921 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:39:55,921 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:39:55,921 INFO L794 eck$LassoCheckResult]: Stem: 12357#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 12248#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 12011#L1018 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 12012#L470 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11833#L477 assume 1 == ~m_i~0;~m_st~0 := 0; 11834#L477-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11843#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12194#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12195#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12034#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12035#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12129#L507-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11849#L686 assume !(0 == ~M_E~0); 11850#L686-2 assume !(0 == ~T1_E~0); 11863#L691-1 assume !(0 == ~T2_E~0); 12207#L696-1 assume !(0 == ~T3_E~0); 12208#L701-1 assume !(0 == ~T4_E~0); 12043#L706-1 assume !(0 == ~T5_E~0); 12044#L711-1 assume !(0 == ~T6_E~0); 12340#L716-1 assume !(0 == ~E_M~0); 12000#L721-1 assume !(0 == ~E_1~0); 12001#L726-1 assume !(0 == ~E_2~0); 11755#L731-1 assume !(0 == ~E_3~0); 11756#L736-1 assume !(0 == ~E_4~0); 11847#L741-1 assume !(0 == ~E_5~0); 11848#L746-1 assume !(0 == ~E_6~0); 12201#L751-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11960#L336 assume !(1 == ~m_pc~0); 11894#L336-2 is_master_triggered_~__retres1~0 := 0; 11895#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11956#L348 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 11869#L851 assume !(0 != activate_threads_~tmp~1); 11870#L851-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11874#L355 assume !(1 == ~t1_pc~0); 12167#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 12164#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11845#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 11846#L859 assume !(0 != activate_threads_~tmp___0~0); 12333#L859-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12334#L374 assume !(1 == ~t2_pc~0); 12107#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 12106#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12103#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 12104#L867 assume !(0 != activate_threads_~tmp___1~0); 12438#L867-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12439#L393 assume 1 == ~t3_pc~0; 12430#L394 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 12431#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12428#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12005#L875 assume !(0 != activate_threads_~tmp___2~0); 11990#L875-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11991#L412 assume 1 == ~t4_pc~0; 11940#L413 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 11941#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11938#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 11939#L883 assume !(0 != activate_threads_~tmp___3~0); 12219#L883-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12037#L431 assume !(1 == ~t5_pc~0); 12023#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 12024#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12036#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 12198#L891 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 12387#L891-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 12271#L450 assume 1 == ~t6_pc~0; 12272#L451 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 12269#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 12270#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 12371#L899 assume !(0 != activate_threads_~tmp___5~0); 12391#L899-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11751#L764 assume !(1 == ~M_E~0); 11752#L764-2 assume !(1 == ~T1_E~0); 11757#L769-1 assume !(1 == ~T2_E~0); 11877#L774-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11878#L779-1 assume !(1 == ~T4_E~0); 12226#L784-1 assume !(1 == ~T5_E~0); 12227#L789-1 assume !(1 == ~T6_E~0); 12039#L794-1 assume !(1 == ~E_M~0); 12040#L799-1 assume !(1 == ~E_1~0); 12335#L804-1 assume !(1 == ~E_2~0); 11992#L809-1 assume !(1 == ~E_3~0); 11993#L814-1 assume 1 == ~E_4~0;~E_4~0 := 2; 11749#L819-1 assume !(1 == ~E_5~0); 11750#L824-1 assume !(1 == ~E_6~0); 11872#L829-1 assume { :end_inline_reset_delta_events } true; 11873#L1055-3 [2018-11-18 10:39:55,922 INFO L796 eck$LassoCheckResult]: Loop: 11873#L1055-3 assume true; 12281#L1055-1 assume !false; 12247#L1056 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 11858#L661 assume true; 11985#L567-1 assume !false; 11986#L568 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 12186#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 11746#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 12416#L558 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 12382#L572 assume !(0 != eval_~tmp~0); 11735#L676 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 11736#L470-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 11865#L686-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11824#L686-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11825#L691-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12215#L696-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12216#L701-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12045#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12046#L711-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12122#L716-3 assume !(0 == ~E_M~0); 11976#L721-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11977#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11739#L731-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11740#L736-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11861#L741-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11862#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12209#L751-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12210#L336-24 assume !(1 == ~m_pc~0); 12395#L336-26 is_master_triggered_~__retres1~0 := 0; 12418#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12393#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 11785#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 11758#L851-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11759#L355-24 assume !(1 == ~t1_pc~0); 11826#L355-26 is_transmit1_triggered_~__retres1~1 := 0; 11827#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11777#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 11778#L859-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 12058#L859-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12059#L374-24 assume 1 == ~t2_pc~0; 12098#L375-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 12099#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12095#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 12096#L867-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 12279#L867-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12280#L393-24 assume 1 == ~t3_pc~0; 12296#L394-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 12297#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12294#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12295#L875-24 assume !(0 != activate_threads_~tmp___2~0); 12423#L875-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11969#L412-24 assume 1 == ~t4_pc~0; 11928#L413-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 11929#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11924#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 11925#L883-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 12131#L883-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12132#L431-24 assume 1 == ~t5_pc~0; 12153#L432-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 12154#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12151#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 12152#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 12349#L891-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 12352#L450-24 assume 1 == ~t6_pc~0; 12366#L451-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 12266#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 12267#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 12365#L899-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 12440#L899-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11737#L764-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11738#L764-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11741#L769-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11854#L774-3 assume !(1 == ~T3_E~0); 11855#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12205#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12206#L789-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12041#L794-3 assume !(1 == ~E_M~0); 12042#L799-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12337#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11998#L809-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11999#L814-3 assume !(1 == ~E_4~0); 11753#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11754#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11879#L829-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 11880#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 11748#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 12417#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 12424#L1074 assume !(0 == start_simulation_~tmp~3); 12421#L1074-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 12196#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 11836#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 12419#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 12009#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 12010#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 12060#L1037 start_simulation_#t~ret19 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 12232#L1087 assume !(0 != start_simulation_~tmp___0~1); 11873#L1055-3 [2018-11-18 10:39:55,922 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:39:55,922 INFO L82 PathProgramCache]: Analyzing trace with hash -136475576, now seen corresponding path program 1 times [2018-11-18 10:39:55,922 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:39:55,922 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:39:55,923 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:55,923 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:39:55,923 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:55,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:39:55,952 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:39:55,953 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:39:55,953 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 10:39:55,953 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 10:39:55,953 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:39:55,953 INFO L82 PathProgramCache]: Analyzing trace with hash 1925712701, now seen corresponding path program 1 times [2018-11-18 10:39:55,953 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:39:55,954 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:39:55,954 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:55,954 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:39:55,954 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:55,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:39:55,979 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:39:55,979 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:39:55,979 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:39:55,979 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 10:39:55,979 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:39:55,980 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:39:55,980 INFO L87 Difference]: Start difference. First operand 1235 states and 1795 transitions. cyclomatic complexity: 562 Second operand 3 states. [2018-11-18 10:39:56,041 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:39:56,041 INFO L93 Difference]: Finished difference Result 2261 states and 3264 transitions. [2018-11-18 10:39:56,043 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:39:56,043 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2261 states and 3264 transitions. [2018-11-18 10:39:56,052 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2164 [2018-11-18 10:39:56,060 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2261 states to 2261 states and 3264 transitions. [2018-11-18 10:39:56,060 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2261 [2018-11-18 10:39:56,062 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2261 [2018-11-18 10:39:56,062 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2261 states and 3264 transitions. [2018-11-18 10:39:56,065 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:39:56,065 INFO L705 BuchiCegarLoop]: Abstraction has 2261 states and 3264 transitions. [2018-11-18 10:39:56,067 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2261 states and 3264 transitions. [2018-11-18 10:39:56,090 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2261 to 2255. [2018-11-18 10:39:56,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2255 states. [2018-11-18 10:39:56,094 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2255 states to 2255 states and 3258 transitions. [2018-11-18 10:39:56,095 INFO L728 BuchiCegarLoop]: Abstraction has 2255 states and 3258 transitions. [2018-11-18 10:39:56,095 INFO L608 BuchiCegarLoop]: Abstraction has 2255 states and 3258 transitions. [2018-11-18 10:39:56,095 INFO L442 BuchiCegarLoop]: ======== Iteration 10============ [2018-11-18 10:39:56,095 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2255 states and 3258 transitions. [2018-11-18 10:39:56,102 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2158 [2018-11-18 10:39:56,102 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:39:56,102 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:39:56,103 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:39:56,103 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:39:56,103 INFO L794 eck$LassoCheckResult]: Stem: 15885#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 15765#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 15514#L1018 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 15515#L470 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15337#L477 assume 1 == ~m_i~0;~m_st~0 := 0; 15338#L477-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15346#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15704#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15705#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15539#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15540#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 15636#L507-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15352#L686 assume !(0 == ~M_E~0); 15353#L686-2 assume !(0 == ~T1_E~0); 15365#L691-1 assume !(0 == ~T2_E~0); 15717#L696-1 assume !(0 == ~T3_E~0); 15718#L701-1 assume !(0 == ~T4_E~0); 15548#L706-1 assume !(0 == ~T5_E~0); 15549#L711-1 assume !(0 == ~T6_E~0); 15862#L716-1 assume !(0 == ~E_M~0); 15504#L721-1 assume !(0 == ~E_1~0); 15505#L726-1 assume !(0 == ~E_2~0); 15258#L731-1 assume !(0 == ~E_3~0); 15259#L736-1 assume !(0 == ~E_4~0); 15350#L741-1 assume !(0 == ~E_5~0); 15351#L746-1 assume !(0 == ~E_6~0); 15711#L751-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15463#L336 assume !(1 == ~m_pc~0); 15397#L336-2 is_master_triggered_~__retres1~0 := 0; 15398#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15459#L348 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 15372#L851 assume !(0 != activate_threads_~tmp~1); 15373#L851-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15377#L355 assume !(1 == ~t1_pc~0); 15675#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 15672#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15348#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 15349#L859 assume !(0 != activate_threads_~tmp___0~0); 15856#L859-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15857#L374 assume !(1 == ~t2_pc~0); 15614#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 15613#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15610#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 15611#L867 assume !(0 != activate_threads_~tmp___1~0); 15996#L867-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 16000#L393 assume !(1 == ~t3_pc~0); 16017#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 16015#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15982#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 15509#L875 assume !(0 != activate_threads_~tmp___2~0); 15494#L875-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 15495#L412 assume 1 == ~t4_pc~0; 15443#L413 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 15444#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 15441#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 15442#L883 assume !(0 != activate_threads_~tmp___3~0); 15732#L883-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 15542#L431 assume !(1 == ~t5_pc~0); 15528#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 15529#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 15541#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 15708#L891 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 15926#L891-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 15789#L450 assume 1 == ~t6_pc~0; 15790#L451 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 15787#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 15788#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 15901#L899 assume !(0 != activate_threads_~tmp___5~0); 15936#L899-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15254#L764 assume !(1 == ~M_E~0); 15255#L764-2 assume !(1 == ~T1_E~0); 15260#L769-1 assume !(1 == ~T2_E~0); 15380#L774-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15381#L779-1 assume !(1 == ~T4_E~0); 15740#L784-1 assume !(1 == ~T5_E~0); 15741#L789-1 assume !(1 == ~T6_E~0); 15544#L794-1 assume !(1 == ~E_M~0); 15545#L799-1 assume !(1 == ~E_1~0); 15858#L804-1 assume !(1 == ~E_2~0); 15496#L809-1 assume !(1 == ~E_3~0); 15497#L814-1 assume 1 == ~E_4~0;~E_4~0 := 2; 15252#L819-1 assume !(1 == ~E_5~0); 15253#L824-1 assume !(1 == ~E_6~0); 15375#L829-1 assume { :end_inline_reset_delta_events } true; 15376#L1055-3 [2018-11-18 10:39:56,103 INFO L796 eck$LassoCheckResult]: Loop: 15376#L1055-3 assume true; 15801#L1055-1 assume !false; 15764#L1056 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 15360#L661 assume true; 15489#L567-1 assume !false; 15490#L568 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 15695#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 15249#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 15966#L558 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 16021#L572 assume !(0 != eval_~tmp~0); 15238#L676 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 15239#L470-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 15366#L686-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15329#L686-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15330#L691-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15994#L696-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17373#L701-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17371#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17369#L711-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15629#L716-3 assume !(0 == ~E_M~0); 15480#L721-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15481#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15242#L731-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15243#L736-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15363#L741-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15364#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15721#L751-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15722#L336-24 assume !(1 == ~m_pc~0); 15969#L336-26 is_master_triggered_~__retres1~0 := 0; 15970#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15938#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 15288#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 15289#L851-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15367#L355-24 assume !(1 == ~t1_pc~0); 15331#L355-26 is_transmit1_triggered_~__retres1~1 := 0; 15332#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15280#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 15281#L859-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 15563#L859-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15564#L374-24 assume 1 == ~t2_pc~0; 15605#L375-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 15606#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15601#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 15602#L867-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 15799#L867-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15800#L393-24 assume !(1 == ~t3_pc~0); 15992#L393-26 is_transmit3_triggered_~__retres1~3 := 0; 15995#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15816#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 15817#L875-24 assume !(0 != activate_threads_~tmp___2~0); 15975#L875-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 15473#L412-24 assume 1 == ~t4_pc~0; 15431#L413-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 15432#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 15427#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 15428#L883-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 15638#L883-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 15639#L431-24 assume !(1 == ~t5_pc~0); 15719#L431-26 is_transmit5_triggered_~__retres1~5 := 0; 17457#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 17456#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 17455#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 17454#L891-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 17453#L450-24 assume 1 == ~t6_pc~0; 17451#L451-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 17450#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 17449#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 17448#L899-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 16002#L899-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15240#L764-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15241#L764-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15244#L769-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15356#L774-3 assume !(1 == ~T3_E~0); 15357#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15715#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15716#L789-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15546#L794-3 assume !(1 == ~E_M~0); 15547#L799-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15860#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15502#L809-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15503#L814-3 assume !(1 == ~E_4~0); 15256#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15257#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15382#L829-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 15383#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 15967#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 15968#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 16023#L1074 assume !(0 == start_simulation_~tmp~3); 17197#L1074-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 17151#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 17144#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 17143#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 17138#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 15565#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 15566#L1037 start_simulation_#t~ret19 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 15747#L1087 assume !(0 != start_simulation_~tmp___0~1); 15376#L1055-3 [2018-11-18 10:39:56,104 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:39:56,104 INFO L82 PathProgramCache]: Analyzing trace with hash -1093403959, now seen corresponding path program 1 times [2018-11-18 10:39:56,104 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:39:56,104 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:39:56,104 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:56,105 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:39:56,105 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:56,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:39:56,133 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:39:56,133 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:39:56,134 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 10:39:56,134 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 10:39:56,134 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:39:56,134 INFO L82 PathProgramCache]: Analyzing trace with hash -1132056897, now seen corresponding path program 1 times [2018-11-18 10:39:56,134 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:39:56,134 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:39:56,135 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:56,135 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:39:56,135 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:56,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:39:56,162 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:39:56,162 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:39:56,163 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:39:56,163 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 10:39:56,163 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:39:56,166 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:39:56,166 INFO L87 Difference]: Start difference. First operand 2255 states and 3258 transitions. cyclomatic complexity: 1007 Second operand 3 states. [2018-11-18 10:39:56,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:39:56,226 INFO L93 Difference]: Finished difference Result 4188 states and 6017 transitions. [2018-11-18 10:39:56,228 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:39:56,228 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4188 states and 6017 transitions. [2018-11-18 10:39:56,245 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4076 [2018-11-18 10:39:56,262 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4188 states to 4188 states and 6017 transitions. [2018-11-18 10:39:56,262 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4188 [2018-11-18 10:39:56,266 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4188 [2018-11-18 10:39:56,266 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4188 states and 6017 transitions. [2018-11-18 10:39:56,273 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:39:56,273 INFO L705 BuchiCegarLoop]: Abstraction has 4188 states and 6017 transitions. [2018-11-18 10:39:56,277 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4188 states and 6017 transitions. [2018-11-18 10:39:56,327 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4188 to 4176. [2018-11-18 10:39:56,328 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4176 states. [2018-11-18 10:39:56,338 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4176 states to 4176 states and 6005 transitions. [2018-11-18 10:39:56,338 INFO L728 BuchiCegarLoop]: Abstraction has 4176 states and 6005 transitions. [2018-11-18 10:39:56,339 INFO L608 BuchiCegarLoop]: Abstraction has 4176 states and 6005 transitions. [2018-11-18 10:39:56,339 INFO L442 BuchiCegarLoop]: ======== Iteration 11============ [2018-11-18 10:39:56,339 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4176 states and 6005 transitions. [2018-11-18 10:39:56,354 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4064 [2018-11-18 10:39:56,354 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:39:56,354 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:39:56,355 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:39:56,355 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:39:56,358 INFO L794 eck$LassoCheckResult]: Stem: 22354#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 22231#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 21965#L1018 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 21966#L470 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21786#L477 assume 1 == ~m_i~0;~m_st~0 := 0; 21787#L477-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21795#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22171#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22172#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21995#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 21996#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 22096#L507-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21801#L686 assume !(0 == ~M_E~0); 21802#L686-2 assume !(0 == ~T1_E~0); 21815#L691-1 assume !(0 == ~T2_E~0); 22185#L696-1 assume !(0 == ~T3_E~0); 22186#L701-1 assume !(0 == ~T4_E~0); 22004#L706-1 assume !(0 == ~T5_E~0); 22005#L711-1 assume !(0 == ~T6_E~0); 22330#L716-1 assume !(0 == ~E_M~0); 21952#L721-1 assume !(0 == ~E_1~0); 21953#L726-1 assume !(0 == ~E_2~0); 21708#L731-1 assume !(0 == ~E_3~0); 21709#L736-1 assume !(0 == ~E_4~0); 21799#L741-1 assume !(0 == ~E_5~0); 21800#L746-1 assume !(0 == ~E_6~0); 22179#L751-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 21908#L336 assume !(1 == ~m_pc~0); 21845#L336-2 is_master_triggered_~__retres1~0 := 0; 21846#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 21904#L348 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 21820#L851 assume !(0 != activate_threads_~tmp~1); 21821#L851-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 21825#L355 assume !(1 == ~t1_pc~0); 22139#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 22136#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 21797#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 21798#L859 assume !(0 != activate_threads_~tmp___0~0); 22322#L859-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22323#L374 assume !(1 == ~t2_pc~0); 22068#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 22067#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22064#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 22065#L867 assume !(0 != activate_threads_~tmp___1~0); 22459#L867-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22461#L393 assume !(1 == ~t3_pc~0); 22478#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 22476#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 22448#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 21957#L875 assume !(0 != activate_threads_~tmp___2~0); 21940#L875-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 21941#L412 assume !(1 == ~t4_pc~0); 21978#L412-2 is_transmit4_triggered_~__retres1~4 := 0; 21977#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 21889#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 21890#L883 assume !(0 != activate_threads_~tmp___3~0); 22199#L883-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 21998#L431 assume !(1 == ~t5_pc~0); 21983#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 21984#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 21997#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 22175#L891 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 22389#L891-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 22254#L450 assume 1 == ~t6_pc~0; 22255#L451 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 22252#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 22253#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 22369#L899 assume !(0 != activate_threads_~tmp___5~0); 22396#L899-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21704#L764 assume !(1 == ~M_E~0); 21705#L764-2 assume !(1 == ~T1_E~0); 21710#L769-1 assume !(1 == ~T2_E~0); 21828#L774-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21829#L779-1 assume !(1 == ~T4_E~0); 22207#L784-1 assume !(1 == ~T5_E~0); 22208#L789-1 assume !(1 == ~T6_E~0); 22000#L794-1 assume !(1 == ~E_M~0); 22001#L799-1 assume !(1 == ~E_1~0); 22324#L804-1 assume !(1 == ~E_2~0); 21942#L809-1 assume !(1 == ~E_3~0); 21943#L814-1 assume 1 == ~E_4~0;~E_4~0 := 2; 21702#L819-1 assume !(1 == ~E_5~0); 21703#L824-1 assume !(1 == ~E_6~0); 21823#L829-1 assume { :end_inline_reset_delta_events } true; 21824#L1055-3 [2018-11-18 10:39:56,359 INFO L796 eck$LassoCheckResult]: Loop: 21824#L1055-3 assume true; 25262#L1055-1 assume !false; 22230#L1056 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 21810#L661 assume true; 21935#L567-1 assume !false; 21936#L568 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 22161#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 21699#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 22421#L558 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 22383#L572 assume !(0 != eval_~tmp~0); 22385#L676 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 25597#L470-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 25595#L686-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25593#L686-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25591#L691-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25588#L696-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25586#L701-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25584#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25582#L711-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25578#L716-3 assume !(0 == ~E_M~0); 25575#L721-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25571#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25568#L731-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25565#L736-3 assume 0 == ~E_4~0;~E_4~0 := 1; 25562#L741-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25559#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25556#L751-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 25551#L336-24 assume !(1 == ~m_pc~0); 25548#L336-26 is_master_triggered_~__retres1~0 := 0; 25545#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 25542#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 25539#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 25535#L851-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 25532#L355-24 assume !(1 == ~t1_pc~0); 25529#L355-26 is_transmit1_triggered_~__retres1~1 := 0; 25526#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 25523#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 25520#L859-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 25517#L859-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 25513#L374-24 assume !(1 == ~t2_pc~0); 25509#L374-26 is_transmit2_triggered_~__retres1~2 := 0; 25506#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 25503#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 25500#L867-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 25497#L867-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 25493#L393-24 assume !(1 == ~t3_pc~0); 25491#L393-26 is_transmit3_triggered_~__retres1~3 := 0; 25489#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 25394#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 25393#L875-24 assume !(0 != activate_threads_~tmp___2~0); 25392#L875-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 25390#L412-24 assume !(1 == ~t4_pc~0); 25386#L412-26 is_transmit4_triggered_~__retres1~4 := 0; 25382#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 25378#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 25374#L883-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 25369#L883-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 25365#L431-24 assume 1 == ~t5_pc~0; 25360#L432-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 25356#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 25352#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 25348#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 25343#L891-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 25339#L450-24 assume 1 == ~t6_pc~0; 25334#L451-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 25331#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 25317#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 25308#L899-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 25307#L899-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25306#L764-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25305#L764-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25304#L769-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25303#L774-3 assume !(1 == ~T3_E~0); 25302#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25301#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25300#L789-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 25298#L794-3 assume !(1 == ~E_M~0); 25297#L799-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25296#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25295#L809-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25294#L814-3 assume !(1 == ~E_4~0); 25293#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25292#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25291#L829-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 25284#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 25247#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 25248#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 25243#L1074 assume !(0 == start_simulation_~tmp~3); 25242#L1074-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 25274#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 25268#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 25267#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 25266#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 25265#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 25264#L1037 start_simulation_#t~ret19 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 25263#L1087 assume !(0 != start_simulation_~tmp___0~1); 21824#L1055-3 [2018-11-18 10:39:56,359 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:39:56,359 INFO L82 PathProgramCache]: Analyzing trace with hash 1625005578, now seen corresponding path program 1 times [2018-11-18 10:39:56,359 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:39:56,359 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:39:56,360 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:56,360 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:39:56,360 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:56,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:39:56,405 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:39:56,405 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:39:56,405 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 10:39:56,405 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 10:39:56,405 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:39:56,406 INFO L82 PathProgramCache]: Analyzing trace with hash -808338880, now seen corresponding path program 1 times [2018-11-18 10:39:56,406 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:39:56,406 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:39:56,406 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:56,407 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:39:56,407 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:56,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:39:56,471 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:39:56,471 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:39:56,471 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:39:56,472 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 10:39:56,472 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:39:56,472 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:39:56,472 INFO L87 Difference]: Start difference. First operand 4176 states and 6005 transitions. cyclomatic complexity: 1837 Second operand 3 states. [2018-11-18 10:39:56,586 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:39:56,586 INFO L93 Difference]: Finished difference Result 7807 states and 11166 transitions. [2018-11-18 10:39:56,587 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:39:56,587 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7807 states and 11166 transitions. [2018-11-18 10:39:56,614 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7656 [2018-11-18 10:39:56,642 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7807 states to 7807 states and 11166 transitions. [2018-11-18 10:39:56,642 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7807 [2018-11-18 10:39:56,648 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7807 [2018-11-18 10:39:56,648 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7807 states and 11166 transitions. [2018-11-18 10:39:56,657 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:39:56,657 INFO L705 BuchiCegarLoop]: Abstraction has 7807 states and 11166 transitions. [2018-11-18 10:39:56,663 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7807 states and 11166 transitions. [2018-11-18 10:39:56,740 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7807 to 7783. [2018-11-18 10:39:56,740 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7783 states. [2018-11-18 10:39:56,753 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7783 states to 7783 states and 11142 transitions. [2018-11-18 10:39:56,753 INFO L728 BuchiCegarLoop]: Abstraction has 7783 states and 11142 transitions. [2018-11-18 10:39:56,753 INFO L608 BuchiCegarLoop]: Abstraction has 7783 states and 11142 transitions. [2018-11-18 10:39:56,753 INFO L442 BuchiCegarLoop]: ======== Iteration 12============ [2018-11-18 10:39:56,753 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7783 states and 11142 transitions. [2018-11-18 10:39:56,774 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7632 [2018-11-18 10:39:56,774 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:39:56,774 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:39:56,775 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:39:56,775 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:39:56,775 INFO L794 eck$LassoCheckResult]: Stem: 34320#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 34205#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 33957#L1018 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 33958#L470 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33773#L477 assume 1 == ~m_i~0;~m_st~0 := 0; 33774#L477-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33782#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34154#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34155#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 33987#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33988#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 34083#L507-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33788#L686 assume !(0 == ~M_E~0); 33789#L686-2 assume !(0 == ~T1_E~0); 33802#L691-1 assume !(0 == ~T2_E~0); 34165#L696-1 assume !(0 == ~T3_E~0); 34166#L701-1 assume !(0 == ~T4_E~0); 33996#L706-1 assume !(0 == ~T5_E~0); 33997#L711-1 assume !(0 == ~T6_E~0); 34301#L716-1 assume !(0 == ~E_M~0); 33940#L721-1 assume !(0 == ~E_1~0); 33941#L726-1 assume !(0 == ~E_2~0); 33698#L731-1 assume !(0 == ~E_3~0); 33699#L736-1 assume !(0 == ~E_4~0); 33786#L741-1 assume !(0 == ~E_5~0); 33787#L746-1 assume !(0 == ~E_6~0); 34159#L751-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 33893#L336 assume !(1 == ~m_pc~0); 33829#L336-2 is_master_triggered_~__retres1~0 := 0; 33830#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 33889#L348 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 33807#L851 assume !(0 != activate_threads_~tmp~1); 33808#L851-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 33811#L355 assume !(1 == ~t1_pc~0); 34117#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 34114#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 33784#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 33785#L859 assume !(0 != activate_threads_~tmp___0~0); 34291#L859-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 34292#L374 assume !(1 == ~t2_pc~0); 34060#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 34059#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 34056#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 34057#L867 assume !(0 != activate_threads_~tmp___1~0); 34440#L867-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 34442#L393 assume !(1 == ~t3_pc~0); 34461#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 34459#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 34429#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 33948#L875 assume !(0 != activate_threads_~tmp___2~0); 33927#L875-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 33928#L412 assume !(1 == ~t4_pc~0); 33971#L412-2 is_transmit4_triggered_~__retres1~4 := 0; 33970#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 33874#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 33875#L883 assume !(0 != activate_threads_~tmp___3~0); 34177#L883-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 33990#L431 assume !(1 == ~t5_pc~0); 33976#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 33977#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 33989#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 34156#L891 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 34368#L891-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 34229#L450 assume !(1 == ~t6_pc~0); 34230#L450-2 is_transmit6_triggered_~__retres1~6 := 0; 34227#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 34228#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 34342#L899 assume !(0 != activate_threads_~tmp___5~0); 34375#L899-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33694#L764 assume !(1 == ~M_E~0); 33695#L764-2 assume !(1 == ~T1_E~0); 33700#L769-1 assume !(1 == ~T2_E~0); 33814#L774-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33815#L779-1 assume !(1 == ~T4_E~0); 34184#L784-1 assume !(1 == ~T5_E~0); 34185#L789-1 assume !(1 == ~T6_E~0); 33992#L794-1 assume !(1 == ~E_M~0); 33993#L799-1 assume !(1 == ~E_1~0); 34293#L804-1 assume !(1 == ~E_2~0); 33929#L809-1 assume !(1 == ~E_3~0); 33930#L814-1 assume 1 == ~E_4~0;~E_4~0 := 2; 33692#L819-1 assume !(1 == ~E_5~0); 33693#L824-1 assume !(1 == ~E_6~0); 33809#L829-1 assume { :end_inline_reset_delta_events } true; 33810#L1055-3 [2018-11-18 10:39:56,776 INFO L796 eck$LassoCheckResult]: Loop: 33810#L1055-3 assume true; 36657#L1055-1 assume !false; 36647#L1056 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 36639#L661 assume true; 36636#L567-1 assume !false; 36635#L568 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 36577#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 36564#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 36557#L558 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 36548#L572 assume !(0 != eval_~tmp~0); 36549#L676 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 37087#L470-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 37086#L686-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37085#L686-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37084#L691-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 37083#L696-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 37082#L701-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 37081#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 37080#L711-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 37079#L716-3 assume !(0 == ~E_M~0); 37078#L721-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37077#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37076#L731-3 assume 0 == ~E_3~0;~E_3~0 := 1; 37075#L736-3 assume 0 == ~E_4~0;~E_4~0 := 1; 37074#L741-3 assume 0 == ~E_5~0;~E_5~0 := 1; 37073#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 37072#L751-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 37070#L336-24 assume !(1 == ~m_pc~0); 37069#L336-26 is_master_triggered_~__retres1~0 := 0; 37068#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 37067#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 37066#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 37065#L851-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 37064#L355-24 assume !(1 == ~t1_pc~0); 37063#L355-26 is_transmit1_triggered_~__retres1~1 := 0; 37062#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 37061#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 37060#L859-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 37059#L859-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 37058#L374-24 assume !(1 == ~t2_pc~0); 37056#L374-26 is_transmit2_triggered_~__retres1~2 := 0; 37055#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 37054#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 37053#L867-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 37052#L867-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 37051#L393-24 assume !(1 == ~t3_pc~0); 37050#L393-26 is_transmit3_triggered_~__retres1~3 := 0; 37049#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 37048#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 37046#L875-24 assume !(0 != activate_threads_~tmp___2~0); 37042#L875-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 37039#L412-24 assume !(1 == ~t4_pc~0); 37036#L412-26 is_transmit4_triggered_~__retres1~4 := 0; 37033#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 37030#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 37027#L883-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 37024#L883-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 37021#L431-24 assume 1 == ~t5_pc~0; 37015#L432-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 37009#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 37000#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 36995#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 36990#L891-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 36984#L450-24 assume !(1 == ~t6_pc~0); 36978#L450-26 is_transmit6_triggered_~__retres1~6 := 0; 36972#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 36967#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 36962#L899-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 36957#L899-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36952#L764-3 assume 1 == ~M_E~0;~M_E~0 := 2; 36947#L764-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36941#L769-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36936#L774-3 assume !(1 == ~T3_E~0); 36931#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36926#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36921#L789-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36916#L794-3 assume !(1 == ~E_M~0); 36910#L799-3 assume 1 == ~E_1~0;~E_1~0 := 2; 36904#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 36899#L809-3 assume 1 == ~E_3~0;~E_3~0 := 2; 36894#L814-3 assume !(1 == ~E_4~0); 36888#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36884#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 36881#L829-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 36811#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 36802#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 36796#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 36789#L1074 assume !(0 == start_simulation_~tmp~3); 36785#L1074-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 36730#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 36718#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 36712#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 36706#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 36700#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 36696#L1037 start_simulation_#t~ret19 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 36692#L1087 assume !(0 != start_simulation_~tmp___0~1); 33810#L1055-3 [2018-11-18 10:39:56,776 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:39:56,776 INFO L82 PathProgramCache]: Analyzing trace with hash 651516619, now seen corresponding path program 1 times [2018-11-18 10:39:56,776 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:39:56,776 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:39:56,777 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:56,777 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:39:56,777 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:56,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:39:56,802 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:39:56,802 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:39:56,802 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 10:39:56,803 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 10:39:56,803 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:39:56,803 INFO L82 PathProgramCache]: Analyzing trace with hash 1910070657, now seen corresponding path program 1 times [2018-11-18 10:39:56,803 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:39:56,803 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:39:56,804 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:56,804 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:39:56,804 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:56,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:39:56,850 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:39:56,850 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:39:56,850 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:39:56,850 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 10:39:56,850 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:39:56,850 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:39:56,851 INFO L87 Difference]: Start difference. First operand 7783 states and 11142 transitions. cyclomatic complexity: 3375 Second operand 3 states. [2018-11-18 10:39:56,887 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:39:56,888 INFO L93 Difference]: Finished difference Result 7783 states and 11092 transitions. [2018-11-18 10:39:56,889 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:39:56,889 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7783 states and 11092 transitions. [2018-11-18 10:39:56,918 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7632 [2018-11-18 10:39:56,946 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7783 states to 7783 states and 11092 transitions. [2018-11-18 10:39:56,946 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7783 [2018-11-18 10:39:56,952 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7783 [2018-11-18 10:39:56,952 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7783 states and 11092 transitions. [2018-11-18 10:39:56,962 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:39:56,962 INFO L705 BuchiCegarLoop]: Abstraction has 7783 states and 11092 transitions. [2018-11-18 10:39:56,967 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7783 states and 11092 transitions. [2018-11-18 10:39:57,045 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7783 to 7783. [2018-11-18 10:39:57,045 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7783 states. [2018-11-18 10:39:57,058 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7783 states to 7783 states and 11092 transitions. [2018-11-18 10:39:57,058 INFO L728 BuchiCegarLoop]: Abstraction has 7783 states and 11092 transitions. [2018-11-18 10:39:57,058 INFO L608 BuchiCegarLoop]: Abstraction has 7783 states and 11092 transitions. [2018-11-18 10:39:57,059 INFO L442 BuchiCegarLoop]: ======== Iteration 13============ [2018-11-18 10:39:57,059 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7783 states and 11092 transitions. [2018-11-18 10:39:57,078 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7632 [2018-11-18 10:39:57,079 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:39:57,079 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:39:57,079 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:39:57,080 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:39:57,080 INFO L794 eck$LassoCheckResult]: Stem: 49896#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 49778#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 49530#L1018 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 49531#L470 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49347#L477 assume 1 == ~m_i~0;~m_st~0 := 0; 49348#L477-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49357#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49724#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49725#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 49560#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 49561#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 49656#L507-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49363#L686 assume !(0 == ~M_E~0); 49364#L686-2 assume !(0 == ~T1_E~0); 49377#L691-1 assume !(0 == ~T2_E~0); 49737#L696-1 assume !(0 == ~T3_E~0); 49738#L701-1 assume !(0 == ~T4_E~0); 49569#L706-1 assume !(0 == ~T5_E~0); 49570#L711-1 assume !(0 == ~T6_E~0); 49874#L716-1 assume !(0 == ~E_M~0); 49515#L721-1 assume !(0 == ~E_1~0); 49516#L726-1 assume !(0 == ~E_2~0); 49271#L731-1 assume !(0 == ~E_3~0); 49272#L736-1 assume !(0 == ~E_4~0); 49361#L741-1 assume !(0 == ~E_5~0); 49362#L746-1 assume !(0 == ~E_6~0); 49731#L751-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 49471#L336 assume !(1 == ~m_pc~0); 49408#L336-2 is_master_triggered_~__retres1~0 := 0; 49409#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 49467#L348 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 49384#L851 assume !(0 != activate_threads_~tmp~1); 49385#L851-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 49389#L355 assume !(1 == ~t1_pc~0); 49696#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 49693#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 49359#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 49360#L859 assume !(0 != activate_threads_~tmp___0~0); 49868#L859-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 49869#L374 assume !(1 == ~t2_pc~0); 49634#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 49633#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 49630#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 49631#L867 assume !(0 != activate_threads_~tmp___1~0); 50001#L867-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 50002#L393 assume !(1 == ~t3_pc~0); 50018#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 50016#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 49988#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 49522#L875 assume !(0 != activate_threads_~tmp___2~0); 49502#L875-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 49503#L412 assume !(1 == ~t4_pc~0); 49544#L412-2 is_transmit4_triggered_~__retres1~4 := 0; 49543#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 49452#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 49453#L883 assume !(0 != activate_threads_~tmp___3~0); 49749#L883-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 49563#L431 assume !(1 == ~t5_pc~0); 49549#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 49550#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 49562#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 49728#L891 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 49936#L891-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 49801#L450 assume !(1 == ~t6_pc~0); 49802#L450-2 is_transmit6_triggered_~__retres1~6 := 0; 49799#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 49800#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 49912#L899 assume !(0 != activate_threads_~tmp___5~0); 49940#L899-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49267#L764 assume !(1 == ~M_E~0); 49268#L764-2 assume !(1 == ~T1_E~0); 49273#L769-1 assume !(1 == ~T2_E~0); 49392#L774-1 assume !(1 == ~T3_E~0); 49393#L779-1 assume !(1 == ~T4_E~0); 49756#L784-1 assume !(1 == ~T5_E~0); 49757#L789-1 assume !(1 == ~T6_E~0); 49565#L794-1 assume !(1 == ~E_M~0); 49566#L799-1 assume !(1 == ~E_1~0); 49870#L804-1 assume !(1 == ~E_2~0); 49504#L809-1 assume !(1 == ~E_3~0); 49505#L814-1 assume 1 == ~E_4~0;~E_4~0 := 2; 49265#L819-1 assume !(1 == ~E_5~0); 49266#L824-1 assume !(1 == ~E_6~0); 49387#L829-1 assume { :end_inline_reset_delta_events } true; 49388#L1055-3 [2018-11-18 10:39:57,080 INFO L796 eck$LassoCheckResult]: Loop: 49388#L1055-3 assume true; 52715#L1055-1 assume !false; 52713#L1056 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 52708#L661 assume true; 52706#L567-1 assume !false; 52704#L568 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 52701#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 52693#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 52689#L558 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 52686#L572 assume !(0 != eval_~tmp~0); 52687#L676 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 52909#L470-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 52907#L686-3 assume 0 == ~M_E~0;~M_E~0 := 1; 52905#L686-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 52903#L691-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 52901#L696-3 assume !(0 == ~T3_E~0); 52899#L701-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 52897#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 52895#L711-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 52893#L716-3 assume !(0 == ~E_M~0); 52890#L721-3 assume 0 == ~E_1~0;~E_1~0 := 1; 52888#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 52886#L731-3 assume 0 == ~E_3~0;~E_3~0 := 1; 52884#L736-3 assume 0 == ~E_4~0;~E_4~0 := 1; 52882#L741-3 assume 0 == ~E_5~0;~E_5~0 := 1; 52880#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 52878#L751-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 52874#L336-24 assume !(1 == ~m_pc~0); 52872#L336-26 is_master_triggered_~__retres1~0 := 0; 52870#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 52868#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 52866#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 52864#L851-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 52862#L355-24 assume !(1 == ~t1_pc~0); 52860#L355-26 is_transmit1_triggered_~__retres1~1 := 0; 52858#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 52856#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 52853#L859-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 52851#L859-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 52849#L374-24 assume !(1 == ~t2_pc~0); 52846#L374-26 is_transmit2_triggered_~__retres1~2 := 0; 52844#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 52842#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 52840#L867-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 52838#L867-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 52836#L393-24 assume !(1 == ~t3_pc~0); 52834#L393-26 is_transmit3_triggered_~__retres1~3 := 0; 52832#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 52830#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 52828#L875-24 assume !(0 != activate_threads_~tmp___2~0); 52826#L875-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 52824#L412-24 assume !(1 == ~t4_pc~0); 52822#L412-26 is_transmit4_triggered_~__retres1~4 := 0; 52820#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 52818#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 52816#L883-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 52814#L883-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 52812#L431-24 assume 1 == ~t5_pc~0; 52809#L432-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 52807#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 52805#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 52803#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 52802#L891-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 52801#L450-24 assume !(1 == ~t6_pc~0); 52800#L450-26 is_transmit6_triggered_~__retres1~6 := 0; 52799#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 52798#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 52797#L899-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 52796#L899-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52793#L764-3 assume 1 == ~M_E~0;~M_E~0 := 2; 52791#L764-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 52789#L769-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 52787#L774-3 assume !(1 == ~T3_E~0); 52785#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 52783#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 52781#L789-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 52778#L794-3 assume !(1 == ~E_M~0); 52776#L799-3 assume 1 == ~E_1~0;~E_1~0 := 2; 52774#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 52772#L809-3 assume 1 == ~E_3~0;~E_3~0 := 2; 52770#L814-3 assume !(1 == ~E_4~0); 52768#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 52765#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 52763#L829-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 52754#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 52749#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 52747#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 52744#L1074 assume !(0 == start_simulation_~tmp~3); 52741#L1074-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 52736#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 52729#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 52727#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 52725#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 52723#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 52720#L1037 start_simulation_#t~ret19 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 52718#L1087 assume !(0 != start_simulation_~tmp___0~1); 49388#L1055-3 [2018-11-18 10:39:57,080 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:39:57,080 INFO L82 PathProgramCache]: Analyzing trace with hash 909682057, now seen corresponding path program 1 times [2018-11-18 10:39:57,080 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:39:57,081 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:39:57,081 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:57,081 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:39:57,081 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:57,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:39:57,114 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:39:57,114 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:39:57,114 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 10:39:57,114 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 10:39:57,114 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:39:57,115 INFO L82 PathProgramCache]: Analyzing trace with hash 852232579, now seen corresponding path program 1 times [2018-11-18 10:39:57,115 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:39:57,115 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:39:57,115 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:57,115 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:39:57,116 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:57,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:39:57,146 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:39:57,147 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:39:57,147 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:39:57,149 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 10:39:57,149 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:39:57,149 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:39:57,149 INFO L87 Difference]: Start difference. First operand 7783 states and 11092 transitions. cyclomatic complexity: 3325 Second operand 3 states. [2018-11-18 10:39:57,203 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:39:57,203 INFO L93 Difference]: Finished difference Result 7783 states and 10986 transitions. [2018-11-18 10:39:57,205 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:39:57,205 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7783 states and 10986 transitions. [2018-11-18 10:39:57,230 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7632 [2018-11-18 10:39:57,251 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7783 states to 7783 states and 10986 transitions. [2018-11-18 10:39:57,251 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7783 [2018-11-18 10:39:57,255 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7783 [2018-11-18 10:39:57,255 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7783 states and 10986 transitions. [2018-11-18 10:39:57,263 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:39:57,263 INFO L705 BuchiCegarLoop]: Abstraction has 7783 states and 10986 transitions. [2018-11-18 10:39:57,269 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7783 states and 10986 transitions. [2018-11-18 10:39:57,342 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7783 to 7783. [2018-11-18 10:39:57,342 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7783 states. [2018-11-18 10:39:57,356 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7783 states to 7783 states and 10986 transitions. [2018-11-18 10:39:57,356 INFO L728 BuchiCegarLoop]: Abstraction has 7783 states and 10986 transitions. [2018-11-18 10:39:57,356 INFO L608 BuchiCegarLoop]: Abstraction has 7783 states and 10986 transitions. [2018-11-18 10:39:57,356 INFO L442 BuchiCegarLoop]: ======== Iteration 14============ [2018-11-18 10:39:57,356 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7783 states and 10986 transitions. [2018-11-18 10:39:57,376 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7632 [2018-11-18 10:39:57,376 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:39:57,376 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:39:57,377 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:39:57,377 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:39:57,377 INFO L794 eck$LassoCheckResult]: Stem: 65472#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 65354#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 65099#L1018 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 65100#L470 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 64919#L477 assume 1 == ~m_i~0;~m_st~0 := 0; 64920#L477-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 64928#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 65297#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 65298#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 65128#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 65129#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 65225#L507-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 64934#L686 assume !(0 == ~M_E~0); 64935#L686-2 assume !(0 == ~T1_E~0); 64949#L691-1 assume !(0 == ~T2_E~0); 65310#L696-1 assume !(0 == ~T3_E~0); 65311#L701-1 assume !(0 == ~T4_E~0); 65137#L706-1 assume !(0 == ~T5_E~0); 65138#L711-1 assume !(0 == ~T6_E~0); 65450#L716-1 assume !(0 == ~E_M~0); 65082#L721-1 assume !(0 == ~E_1~0); 65083#L726-1 assume !(0 == ~E_2~0); 64844#L731-1 assume !(0 == ~E_3~0); 64845#L736-1 assume !(0 == ~E_4~0); 64932#L741-1 assume !(0 == ~E_5~0); 64933#L746-1 assume !(0 == ~E_6~0); 65304#L751-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 65037#L336 assume !(1 == ~m_pc~0); 64980#L336-2 is_master_triggered_~__retres1~0 := 0; 64981#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 65034#L348 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 64956#L851 assume !(0 != activate_threads_~tmp~1); 64957#L851-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 64961#L355 assume !(1 == ~t1_pc~0); 65265#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 65262#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 64930#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 64931#L859 assume !(0 != activate_threads_~tmp___0~0); 65444#L859-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 65445#L374 assume !(1 == ~t2_pc~0); 65203#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 65202#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 65199#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 65200#L867 assume !(0 != activate_threads_~tmp___1~0); 65588#L867-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 65591#L393 assume !(1 == ~t3_pc~0); 65603#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 65601#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 65577#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 65090#L875 assume !(0 != activate_threads_~tmp___2~0); 65069#L875-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 65070#L412 assume !(1 == ~t4_pc~0); 65112#L412-2 is_transmit4_triggered_~__retres1~4 := 0; 65111#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 65020#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 65021#L883 assume !(0 != activate_threads_~tmp___3~0); 65322#L883-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 65131#L431 assume !(1 == ~t5_pc~0); 65117#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 65118#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 65130#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 65301#L891 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 65523#L891-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 65376#L450 assume !(1 == ~t6_pc~0); 65377#L450-2 is_transmit6_triggered_~__retres1~6 := 0; 65374#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 65375#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 65490#L899 assume !(0 != activate_threads_~tmp___5~0); 65529#L899-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64840#L764 assume !(1 == ~M_E~0); 64841#L764-2 assume !(1 == ~T1_E~0); 64846#L769-1 assume !(1 == ~T2_E~0); 64964#L774-1 assume !(1 == ~T3_E~0); 64965#L779-1 assume !(1 == ~T4_E~0); 65329#L784-1 assume !(1 == ~T5_E~0); 65330#L789-1 assume !(1 == ~T6_E~0); 65133#L794-1 assume !(1 == ~E_M~0); 65134#L799-1 assume !(1 == ~E_1~0); 65446#L804-1 assume !(1 == ~E_2~0); 65071#L809-1 assume !(1 == ~E_3~0); 65072#L814-1 assume !(1 == ~E_4~0); 64838#L819-1 assume !(1 == ~E_5~0); 64839#L824-1 assume !(1 == ~E_6~0); 64959#L829-1 assume { :end_inline_reset_delta_events } true; 64960#L1055-3 [2018-11-18 10:39:57,378 INFO L796 eck$LassoCheckResult]: Loop: 64960#L1055-3 assume true; 66990#L1055-1 assume !false; 66988#L1056 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 66984#L661 assume true; 66982#L567-1 assume !false; 66980#L568 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 66977#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 66969#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 66965#L558 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 66962#L572 assume !(0 != eval_~tmp~0); 66963#L676 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 67184#L470-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 67182#L686-3 assume 0 == ~M_E~0;~M_E~0 := 1; 67180#L686-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 67178#L691-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 67176#L696-3 assume !(0 == ~T3_E~0); 67174#L701-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 67172#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 67170#L711-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 67168#L716-3 assume !(0 == ~E_M~0); 67165#L721-3 assume 0 == ~E_1~0;~E_1~0 := 1; 67163#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 67161#L731-3 assume 0 == ~E_3~0;~E_3~0 := 1; 67159#L736-3 assume !(0 == ~E_4~0); 67157#L741-3 assume 0 == ~E_5~0;~E_5~0 := 1; 67155#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 67153#L751-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 67149#L336-24 assume !(1 == ~m_pc~0); 67147#L336-26 is_master_triggered_~__retres1~0 := 0; 67145#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 67143#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 67141#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 67139#L851-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 67137#L355-24 assume !(1 == ~t1_pc~0); 67135#L355-26 is_transmit1_triggered_~__retres1~1 := 0; 67133#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 67131#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 67128#L859-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 67126#L859-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 67124#L374-24 assume !(1 == ~t2_pc~0); 67121#L374-26 is_transmit2_triggered_~__retres1~2 := 0; 67119#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 67117#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 67115#L867-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 67113#L867-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 67111#L393-24 assume !(1 == ~t3_pc~0); 67109#L393-26 is_transmit3_triggered_~__retres1~3 := 0; 67107#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 67105#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 67103#L875-24 assume !(0 != activate_threads_~tmp___2~0); 67101#L875-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 67099#L412-24 assume !(1 == ~t4_pc~0); 67097#L412-26 is_transmit4_triggered_~__retres1~4 := 0; 67095#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 67093#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 67091#L883-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 67089#L883-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 67087#L431-24 assume !(1 == ~t5_pc~0); 67085#L431-26 is_transmit5_triggered_~__retres1~5 := 0; 67082#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 67080#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 67078#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 67077#L891-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 67076#L450-24 assume !(1 == ~t6_pc~0); 67075#L450-26 is_transmit6_triggered_~__retres1~6 := 0; 67074#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 67073#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 67072#L899-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 67071#L899-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 67068#L764-3 assume 1 == ~M_E~0;~M_E~0 := 2; 67066#L764-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 67064#L769-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 67062#L774-3 assume !(1 == ~T3_E~0); 67060#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 67058#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 67056#L789-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 67053#L794-3 assume !(1 == ~E_M~0); 67051#L799-3 assume 1 == ~E_1~0;~E_1~0 := 2; 67049#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 67047#L809-3 assume 1 == ~E_3~0;~E_3~0 := 2; 67045#L814-3 assume !(1 == ~E_4~0); 67043#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 67040#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 67038#L829-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 67029#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 67024#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 67022#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 67019#L1074 assume !(0 == start_simulation_~tmp~3); 67016#L1074-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 67011#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 67004#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 67002#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 67000#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 66998#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 66995#L1037 start_simulation_#t~ret19 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 66993#L1087 assume !(0 != start_simulation_~tmp___0~1); 64960#L1055-3 [2018-11-18 10:39:57,378 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:39:57,378 INFO L82 PathProgramCache]: Analyzing trace with hash 909741639, now seen corresponding path program 1 times [2018-11-18 10:39:57,378 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:39:57,378 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:39:57,379 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:57,379 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:39:57,379 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:57,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:39:57,448 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:39:57,448 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:39:57,448 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 10:39:57,449 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 10:39:57,449 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:39:57,449 INFO L82 PathProgramCache]: Analyzing trace with hash -2015738362, now seen corresponding path program 1 times [2018-11-18 10:39:57,449 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:39:57,449 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:39:57,450 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:57,450 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:39:57,450 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:57,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:39:57,474 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:39:57,474 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:39:57,474 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 10:39:57,474 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 10:39:57,475 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 10:39:57,475 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 10:39:57,475 INFO L87 Difference]: Start difference. First operand 7783 states and 10986 transitions. cyclomatic complexity: 3219 Second operand 5 states. [2018-11-18 10:39:57,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:39:57,724 INFO L93 Difference]: Finished difference Result 18450 states and 26133 transitions. [2018-11-18 10:39:57,725 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 10:39:57,725 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18450 states and 26133 transitions. [2018-11-18 10:39:57,798 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18124 [2018-11-18 10:39:57,854 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18450 states to 18450 states and 26133 transitions. [2018-11-18 10:39:57,854 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18450 [2018-11-18 10:39:57,866 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18450 [2018-11-18 10:39:57,866 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18450 states and 26133 transitions. [2018-11-18 10:39:57,886 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:39:57,886 INFO L705 BuchiCegarLoop]: Abstraction has 18450 states and 26133 transitions. [2018-11-18 10:39:57,900 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18450 states and 26133 transitions. [2018-11-18 10:39:58,071 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18450 to 8122. [2018-11-18 10:39:58,071 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8122 states. [2018-11-18 10:39:58,085 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8122 states to 8122 states and 11325 transitions. [2018-11-18 10:39:58,086 INFO L728 BuchiCegarLoop]: Abstraction has 8122 states and 11325 transitions. [2018-11-18 10:39:58,086 INFO L608 BuchiCegarLoop]: Abstraction has 8122 states and 11325 transitions. [2018-11-18 10:39:58,086 INFO L442 BuchiCegarLoop]: ======== Iteration 15============ [2018-11-18 10:39:58,086 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8122 states and 11325 transitions. [2018-11-18 10:39:58,104 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7968 [2018-11-18 10:39:58,104 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:39:58,105 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:39:58,106 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:39:58,106 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:39:58,106 INFO L794 eck$LassoCheckResult]: Stem: 91756#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 91641#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 91347#L1018 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 91348#L470 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 91172#L477 assume 1 == ~m_i~0;~m_st~0 := 0; 91173#L477-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 91181#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 91557#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 91558#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 91377#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 91378#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 91473#L507-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 91187#L686 assume !(0 == ~M_E~0); 91188#L686-2 assume !(0 == ~T1_E~0); 91201#L691-1 assume !(0 == ~T2_E~0); 91577#L696-1 assume !(0 == ~T3_E~0); 91578#L701-1 assume !(0 == ~T4_E~0); 91386#L706-1 assume !(0 == ~T5_E~0); 91387#L711-1 assume !(0 == ~T6_E~0); 91734#L716-1 assume !(0 == ~E_M~0); 91332#L721-1 assume !(0 == ~E_1~0); 91333#L726-1 assume !(0 == ~E_2~0); 91092#L731-1 assume !(0 == ~E_3~0); 91093#L736-1 assume !(0 == ~E_4~0); 91185#L741-1 assume !(0 == ~E_5~0); 91186#L746-1 assume !(0 == ~E_6~0); 91569#L751-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 91289#L336 assume !(1 == ~m_pc~0); 91231#L336-2 is_master_triggered_~__retres1~0 := 0; 91232#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 91286#L348 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 91207#L851 assume !(0 != activate_threads_~tmp~1); 91208#L851-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 91212#L355 assume !(1 == ~t1_pc~0); 91516#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 91513#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 91183#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 91184#L859 assume !(0 != activate_threads_~tmp___0~0); 91728#L859-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 91729#L374 assume !(1 == ~t2_pc~0); 91450#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 91449#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 91446#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 91447#L867 assume !(0 != activate_threads_~tmp___1~0); 91885#L867-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 91889#L393 assume !(1 == ~t3_pc~0); 91903#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 91901#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 91873#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 91338#L875 assume !(0 != activate_threads_~tmp___2~0); 91320#L875-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 91321#L412 assume !(1 == ~t4_pc~0); 91360#L412-2 is_transmit4_triggered_~__retres1~4 := 0; 91359#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 91272#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 91273#L883 assume !(0 != activate_threads_~tmp___3~0); 91594#L883-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 91380#L431 assume !(1 == ~t5_pc~0); 91365#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 91366#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 91379#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 91819#L891 assume !(0 != activate_threads_~tmp___4~0); 91811#L891-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 91663#L450 assume !(1 == ~t6_pc~0); 91664#L450-2 is_transmit6_triggered_~__retres1~6 := 0; 91661#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 91662#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 91774#L899 assume !(0 != activate_threads_~tmp___5~0); 91822#L899-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 91088#L764 assume !(1 == ~M_E~0); 91089#L764-2 assume !(1 == ~T1_E~0); 91094#L769-1 assume !(1 == ~T2_E~0); 91215#L774-1 assume !(1 == ~T3_E~0); 91216#L779-1 assume !(1 == ~T4_E~0); 91608#L784-1 assume !(1 == ~T5_E~0); 91609#L789-1 assume !(1 == ~T6_E~0); 91382#L794-1 assume !(1 == ~E_M~0); 91383#L799-1 assume !(1 == ~E_1~0); 91730#L804-1 assume !(1 == ~E_2~0); 91322#L809-1 assume !(1 == ~E_3~0); 91323#L814-1 assume !(1 == ~E_4~0); 91086#L819-1 assume !(1 == ~E_5~0); 91087#L824-1 assume !(1 == ~E_6~0); 91210#L829-1 assume { :end_inline_reset_delta_events } true; 91211#L1055-3 [2018-11-18 10:39:58,106 INFO L796 eck$LassoCheckResult]: Loop: 91211#L1055-3 assume true; 94489#L1055-1 assume !false; 94486#L1056 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 93992#L661 assume true; 94481#L567-1 assume !false; 94342#L568 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 94295#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 94283#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 94278#L558 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 94227#L572 assume !(0 != eval_~tmp~0); 94228#L676 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 94883#L470-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 94882#L686-3 assume 0 == ~M_E~0;~M_E~0 := 1; 94881#L686-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 94880#L691-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 94879#L696-3 assume !(0 == ~T3_E~0); 94878#L701-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 94877#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 94876#L711-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 94875#L716-3 assume !(0 == ~E_M~0); 94874#L721-3 assume 0 == ~E_1~0;~E_1~0 := 1; 94873#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 94872#L731-3 assume 0 == ~E_3~0;~E_3~0 := 1; 94871#L736-3 assume !(0 == ~E_4~0); 94870#L741-3 assume 0 == ~E_5~0;~E_5~0 := 1; 94869#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 94868#L751-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 94866#L336-24 assume !(1 == ~m_pc~0); 94865#L336-26 is_master_triggered_~__retres1~0 := 0; 94864#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 94863#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 94862#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 94861#L851-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 94860#L355-24 assume !(1 == ~t1_pc~0); 94859#L355-26 is_transmit1_triggered_~__retres1~1 := 0; 94858#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 94857#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 94856#L859-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 94855#L859-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 94854#L374-24 assume 1 == ~t2_pc~0; 94853#L375-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 94851#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 94850#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 94849#L867-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 94848#L867-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 94847#L393-24 assume !(1 == ~t3_pc~0); 94846#L393-26 is_transmit3_triggered_~__retres1~3 := 0; 94845#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 94844#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 94843#L875-24 assume !(0 != activate_threads_~tmp___2~0); 94842#L875-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 94841#L412-24 assume !(1 == ~t4_pc~0); 94840#L412-26 is_transmit4_triggered_~__retres1~4 := 0; 94839#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 94838#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 94837#L883-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 94836#L883-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 94835#L431-24 assume 1 == ~t5_pc~0; 94833#L432-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 94831#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 94829#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 94827#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 94826#L891-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 94783#L450-24 assume !(1 == ~t6_pc~0); 94781#L450-26 is_transmit6_triggered_~__retres1~6 := 0; 94779#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 94737#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 94735#L899-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 94732#L899-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 94729#L764-3 assume 1 == ~M_E~0;~M_E~0 := 2; 94725#L764-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 94721#L769-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 94717#L774-3 assume !(1 == ~T3_E~0); 94713#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 94709#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 94705#L789-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 94701#L794-3 assume !(1 == ~E_M~0); 94697#L799-3 assume 1 == ~E_1~0;~E_1~0 := 2; 94693#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 94689#L809-3 assume 1 == ~E_3~0;~E_3~0 := 2; 94685#L814-3 assume !(1 == ~E_4~0); 94681#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 94677#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 94632#L829-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 94624#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 94574#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 94570#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 94565#L1074 assume !(0 == start_simulation_~tmp~3); 94562#L1074-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 94517#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 94509#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 94506#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 94503#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 94500#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 94497#L1037 start_simulation_#t~ret19 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 94494#L1087 assume !(0 != start_simulation_~tmp___0~1); 91211#L1055-3 [2018-11-18 10:39:58,106 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:39:58,106 INFO L82 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 1 times [2018-11-18 10:39:58,107 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:39:58,107 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:39:58,107 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:58,107 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:39:58,107 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:58,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:39:58,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:39:58,147 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:39:58,147 INFO L82 PathProgramCache]: Analyzing trace with hash -1299077308, now seen corresponding path program 1 times [2018-11-18 10:39:58,147 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:39:58,147 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:39:58,148 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:58,148 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:39:58,148 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:58,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:39:58,169 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:39:58,169 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:39:58,169 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 10:39:58,170 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 10:39:58,170 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 10:39:58,170 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 10:39:58,170 INFO L87 Difference]: Start difference. First operand 8122 states and 11325 transitions. cyclomatic complexity: 3219 Second operand 5 states. [2018-11-18 10:39:58,329 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:39:58,330 INFO L93 Difference]: Finished difference Result 14730 states and 20261 transitions. [2018-11-18 10:39:58,332 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-18 10:39:58,332 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14730 states and 20261 transitions. [2018-11-18 10:39:58,377 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14512 [2018-11-18 10:39:58,415 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14730 states to 14730 states and 20261 transitions. [2018-11-18 10:39:58,415 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14730 [2018-11-18 10:39:58,423 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14730 [2018-11-18 10:39:58,423 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14730 states and 20261 transitions. [2018-11-18 10:39:58,436 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:39:58,436 INFO L705 BuchiCegarLoop]: Abstraction has 14730 states and 20261 transitions. [2018-11-18 10:39:58,446 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14730 states and 20261 transitions. [2018-11-18 10:39:58,528 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14730 to 8170. [2018-11-18 10:39:58,529 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8170 states. [2018-11-18 10:39:58,542 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8170 states to 8170 states and 11373 transitions. [2018-11-18 10:39:58,542 INFO L728 BuchiCegarLoop]: Abstraction has 8170 states and 11373 transitions. [2018-11-18 10:39:58,542 INFO L608 BuchiCegarLoop]: Abstraction has 8170 states and 11373 transitions. [2018-11-18 10:39:58,542 INFO L442 BuchiCegarLoop]: ======== Iteration 16============ [2018-11-18 10:39:58,542 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8170 states and 11373 transitions. [2018-11-18 10:39:58,562 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8016 [2018-11-18 10:39:58,562 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:39:58,562 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:39:58,563 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:39:58,563 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:39:58,564 INFO L794 eck$LassoCheckResult]: Stem: 114608#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 114485#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 114219#L1018 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 114220#L470 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 114039#L477 assume 1 == ~m_i~0;~m_st~0 := 0; 114040#L477-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 114048#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 114422#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 114423#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 114250#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 114251#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 114348#L507-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 114054#L686 assume !(0 == ~M_E~0); 114055#L686-2 assume !(0 == ~T1_E~0); 114068#L691-1 assume !(0 == ~T2_E~0); 114439#L696-1 assume !(0 == ~T3_E~0); 114440#L701-1 assume !(0 == ~T4_E~0); 114259#L706-1 assume !(0 == ~T5_E~0); 114260#L711-1 assume !(0 == ~T6_E~0); 114585#L716-1 assume !(0 == ~E_M~0); 114200#L721-1 assume !(0 == ~E_1~0); 114201#L726-1 assume !(0 == ~E_2~0); 113962#L731-1 assume !(0 == ~E_3~0); 113963#L736-1 assume !(0 == ~E_4~0); 114052#L741-1 assume !(0 == ~E_5~0); 114053#L746-1 assume !(0 == ~E_6~0); 114432#L751-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 114155#L336 assume !(1 == ~m_pc~0); 114097#L336-2 is_master_triggered_~__retres1~0 := 0; 114098#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 114152#L348 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 114076#L851 assume !(0 != activate_threads_~tmp~1); 114077#L851-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 114080#L355 assume !(1 == ~t1_pc~0); 114386#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 114382#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 114050#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 114051#L859 assume !(0 != activate_threads_~tmp___0~0); 114578#L859-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 114579#L374 assume !(1 == ~t2_pc~0); 114325#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 114324#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 114321#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 114322#L867 assume !(0 != activate_threads_~tmp___1~0); 114733#L867-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 114737#L393 assume !(1 == ~t3_pc~0); 114751#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 114749#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 114721#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 114209#L875 assume !(0 != activate_threads_~tmp___2~0); 114187#L875-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 114188#L412 assume !(1 == ~t4_pc~0); 114233#L412-2 is_transmit4_triggered_~__retres1~4 := 0; 114232#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 114138#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 114139#L883 assume !(0 != activate_threads_~tmp___3~0); 114455#L883-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 114253#L431 assume !(1 == ~t5_pc~0); 114239#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 114240#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 114252#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 114665#L891 assume !(0 != activate_threads_~tmp___4~0); 114657#L891-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 114507#L450 assume !(1 == ~t6_pc~0); 114508#L450-2 is_transmit6_triggered_~__retres1~6 := 0; 114505#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 114506#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 114624#L899 assume !(0 != activate_threads_~tmp___5~0); 114668#L899-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 113958#L764 assume !(1 == ~M_E~0); 113959#L764-2 assume !(1 == ~T1_E~0); 113964#L769-1 assume !(1 == ~T2_E~0); 114082#L774-1 assume !(1 == ~T3_E~0); 114083#L779-1 assume !(1 == ~T4_E~0); 114463#L784-1 assume !(1 == ~T5_E~0); 114464#L789-1 assume !(1 == ~T6_E~0); 114255#L794-1 assume !(1 == ~E_M~0); 114256#L799-1 assume !(1 == ~E_1~0); 114580#L804-1 assume !(1 == ~E_2~0); 114189#L809-1 assume !(1 == ~E_3~0); 114190#L814-1 assume !(1 == ~E_4~0); 113956#L819-1 assume !(1 == ~E_5~0); 113957#L824-1 assume !(1 == ~E_6~0); 114078#L829-1 assume { :end_inline_reset_delta_events } true; 114079#L1055-3 [2018-11-18 10:39:58,564 INFO L796 eck$LassoCheckResult]: Loop: 114079#L1055-3 assume true; 121191#L1055-1 assume !false; 121189#L1056 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 121184#L661 assume true; 121182#L567-1 assume !false; 120741#L568 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 120736#L520 assume !(0 == ~m_st~0); 120729#L524 assume !(0 == ~t1_st~0); 120730#L528 assume !(0 == ~t2_st~0); 120733#L532 assume !(0 == ~t3_st~0); 120735#L536 assume !(0 == ~t4_st~0); 120731#L540 assume !(0 == ~t5_st~0); 120732#L544 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7 := 0; 120734#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 118903#L558 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 118904#L572 assume !(0 != eval_~tmp~0); 120697#L676 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 120698#L470-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 120690#L686-3 assume 0 == ~M_E~0;~M_E~0 := 1; 120691#L686-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 120684#L691-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 120685#L696-3 assume !(0 == ~T3_E~0); 120680#L701-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 120681#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 120674#L711-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 120675#L716-3 assume !(0 == ~E_M~0); 120668#L721-3 assume 0 == ~E_1~0;~E_1~0 := 1; 120669#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 120662#L731-3 assume 0 == ~E_3~0;~E_3~0 := 1; 120663#L736-3 assume !(0 == ~E_4~0); 120656#L741-3 assume 0 == ~E_5~0;~E_5~0 := 1; 120657#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 120644#L751-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 120645#L336-24 assume !(1 == ~m_pc~0); 114699#L336-26 is_master_triggered_~__retres1~0 := 0; 114700#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 114671#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 113992#L851-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 113965#L851-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 113966#L355-24 assume !(1 == ~t1_pc~0); 121144#L355-26 is_transmit1_triggered_~__retres1~1 := 0; 121142#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 121140#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 121138#L859-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 121135#L859-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 121133#L374-24 assume 1 == ~t2_pc~0; 121131#L375-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 121128#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 121126#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 121124#L867-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 121121#L867-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 121119#L393-24 assume !(1 == ~t3_pc~0); 121117#L393-26 is_transmit3_triggered_~__retres1~3 := 0; 121115#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 121113#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 114710#L875-24 assume !(0 != activate_threads_~tmp___2~0); 114711#L875-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 114164#L412-24 assume !(1 == ~t4_pc~0); 114165#L412-26 is_transmit4_triggered_~__retres1~4 := 0; 114178#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 114223#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 121409#L883-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 121408#L883-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 121407#L431-24 assume 1 == ~t5_pc~0; 114369#L432-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 114370#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 121284#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 121285#L891-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 114599#L891-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 114600#L450-24 assume !(1 == ~t6_pc~0); 121403#L450-26 is_transmit6_triggered_~__retres1~6 := 0; 121402#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 121401#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 121400#L899-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 121395#L899-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 121394#L764-3 assume 1 == ~M_E~0;~M_E~0 := 2; 121393#L764-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 121392#L769-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 121391#L774-3 assume !(1 == ~T3_E~0); 121390#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 121389#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 121388#L789-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 121387#L794-3 assume !(1 == ~E_M~0); 121386#L799-3 assume 1 == ~E_1~0;~E_1~0 := 2; 121385#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 121384#L809-3 assume 1 == ~E_3~0;~E_3~0 := 2; 121383#L814-3 assume !(1 == ~E_4~0); 121382#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 121381#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 121380#L829-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 121376#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 121367#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 121360#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 121352#L1074 assume !(0 == start_simulation_~tmp~3); 121345#L1074-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 121343#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 121336#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 121326#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 121200#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 121198#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 121196#L1037 start_simulation_#t~ret19 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 121194#L1087 assume !(0 != start_simulation_~tmp___0~1); 114079#L1055-3 [2018-11-18 10:39:58,564 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:39:58,564 INFO L82 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 2 times [2018-11-18 10:39:58,564 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:39:58,564 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:39:58,565 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:58,565 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:39:58,565 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:58,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:39:58,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:39:58,591 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:39:58,591 INFO L82 PathProgramCache]: Analyzing trace with hash -915437677, now seen corresponding path program 1 times [2018-11-18 10:39:58,591 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:39:58,592 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:39:58,592 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:58,592 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:39:58,592 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:58,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:39:58,641 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:39:58,641 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:39:58,641 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 10:39:58,641 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 10:39:58,641 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 10:39:58,641 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 10:39:58,642 INFO L87 Difference]: Start difference. First operand 8170 states and 11373 transitions. cyclomatic complexity: 3219 Second operand 5 states. [2018-11-18 10:39:58,780 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:39:58,780 INFO L93 Difference]: Finished difference Result 10402 states and 14524 transitions. [2018-11-18 10:39:58,782 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 10:39:58,782 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10402 states and 14524 transitions. [2018-11-18 10:39:58,813 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 10200 [2018-11-18 10:39:58,840 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10402 states to 10402 states and 14524 transitions. [2018-11-18 10:39:58,840 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10402 [2018-11-18 10:39:58,845 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10402 [2018-11-18 10:39:58,846 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10402 states and 14524 transitions. [2018-11-18 10:39:58,854 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:39:58,854 INFO L705 BuchiCegarLoop]: Abstraction has 10402 states and 14524 transitions. [2018-11-18 10:39:58,860 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10402 states and 14524 transitions. [2018-11-18 10:39:58,924 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10402 to 8194. [2018-11-18 10:39:58,924 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8194 states. [2018-11-18 10:39:58,937 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8194 states to 8194 states and 11292 transitions. [2018-11-18 10:39:58,937 INFO L728 BuchiCegarLoop]: Abstraction has 8194 states and 11292 transitions. [2018-11-18 10:39:58,937 INFO L608 BuchiCegarLoop]: Abstraction has 8194 states and 11292 transitions. [2018-11-18 10:39:58,937 INFO L442 BuchiCegarLoop]: ======== Iteration 17============ [2018-11-18 10:39:58,937 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8194 states and 11292 transitions. [2018-11-18 10:39:58,956 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8040 [2018-11-18 10:39:58,956 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:39:58,956 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:39:58,957 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:39:58,957 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:39:58,957 INFO L794 eck$LassoCheckResult]: Stem: 133211#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 133087#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 132802#L1018 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 132803#L470 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 132623#L477 assume 1 == ~m_i~0;~m_st~0 := 0; 132624#L477-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 132632#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 133020#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 133021#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 132837#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 132838#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 132935#L507-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 132638#L686 assume !(0 == ~M_E~0); 132639#L686-2 assume !(0 == ~T1_E~0); 132652#L691-1 assume !(0 == ~T2_E~0); 133036#L696-1 assume !(0 == ~T3_E~0); 133037#L701-1 assume !(0 == ~T4_E~0); 132846#L706-1 assume !(0 == ~T5_E~0); 132847#L711-1 assume !(0 == ~T6_E~0); 133183#L716-1 assume !(0 == ~E_M~0); 132783#L721-1 assume !(0 == ~E_1~0); 132784#L726-1 assume !(0 == ~E_2~0); 132546#L731-1 assume !(0 == ~E_3~0); 132547#L736-1 assume !(0 == ~E_4~0); 132636#L741-1 assume !(0 == ~E_5~0); 132637#L746-1 assume !(0 == ~E_6~0); 133029#L751-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 132740#L336 assume !(1 == ~m_pc~0); 132683#L336-2 is_master_triggered_~__retres1~0 := 0; 132684#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 132737#L348 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 132660#L851 assume !(0 != activate_threads_~tmp~1); 132661#L851-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 132664#L355 assume !(1 == ~t1_pc~0); 132980#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 132976#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 132634#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 132635#L859 assume !(0 != activate_threads_~tmp___0~0); 133177#L859-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 133178#L374 assume !(1 == ~t2_pc~0); 132910#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 132909#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 132906#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 132907#L867 assume !(0 != activate_threads_~tmp___1~0); 133334#L867-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 133338#L393 assume !(1 == ~t3_pc~0); 133353#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 133351#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 133319#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 132792#L875 assume !(0 != activate_threads_~tmp___2~0); 132771#L875-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 132772#L412 assume !(1 == ~t4_pc~0); 132819#L412-2 is_transmit4_triggered_~__retres1~4 := 0; 132818#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 132723#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 132724#L883 assume !(0 != activate_threads_~tmp___3~0); 133053#L883-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 132840#L431 assume !(1 == ~t5_pc~0); 132825#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 132826#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 132839#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 133256#L891 assume !(0 != activate_threads_~tmp___4~0); 133251#L891-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 133109#L450 assume !(1 == ~t6_pc~0); 133110#L450-2 is_transmit6_triggered_~__retres1~6 := 0; 133107#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 133108#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 133229#L899 assume !(0 != activate_threads_~tmp___5~0); 133259#L899-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 132542#L764 assume !(1 == ~M_E~0); 132543#L764-2 assume !(1 == ~T1_E~0); 132548#L769-1 assume !(1 == ~T2_E~0); 132667#L774-1 assume !(1 == ~T3_E~0); 132668#L779-1 assume !(1 == ~T4_E~0); 133062#L784-1 assume !(1 == ~T5_E~0); 133063#L789-1 assume !(1 == ~T6_E~0); 132842#L794-1 assume !(1 == ~E_M~0); 132843#L799-1 assume !(1 == ~E_1~0); 133179#L804-1 assume !(1 == ~E_2~0); 132773#L809-1 assume !(1 == ~E_3~0); 132774#L814-1 assume !(1 == ~E_4~0); 132540#L819-1 assume !(1 == ~E_5~0); 132541#L824-1 assume !(1 == ~E_6~0); 132662#L829-1 assume { :end_inline_reset_delta_events } true; 132663#L1055-3 [2018-11-18 10:39:58,957 INFO L796 eck$LassoCheckResult]: Loop: 132663#L1055-3 assume true; 134685#L1055-1 assume !false; 134680#L1056 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 134676#L661 assume true; 134675#L567-1 assume !false; 134674#L568 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 134673#L520 assume !(0 == ~m_st~0); 134666#L524 assume !(0 == ~t1_st~0); 134667#L528 assume !(0 == ~t2_st~0); 134670#L532 assume !(0 == ~t3_st~0); 134672#L536 assume !(0 == ~t4_st~0); 134668#L540 assume !(0 == ~t5_st~0); 134669#L544 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7 := 0; 134671#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 134415#L558 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 134416#L572 assume !(0 != eval_~tmp~0); 134970#L676 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 134969#L470-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 134968#L686-3 assume 0 == ~M_E~0;~M_E~0 := 1; 134967#L686-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 134966#L691-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 134965#L696-3 assume !(0 == ~T3_E~0); 134964#L701-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 134963#L706-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 134962#L711-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 134961#L716-3 assume !(0 == ~E_M~0); 134960#L721-3 assume 0 == ~E_1~0;~E_1~0 := 1; 134959#L726-3 assume 0 == ~E_2~0;~E_2~0 := 1; 134958#L731-3 assume 0 == ~E_3~0;~E_3~0 := 1; 134957#L736-3 assume !(0 == ~E_4~0); 134956#L741-3 assume 0 == ~E_5~0;~E_5~0 := 1; 134955#L746-3 assume 0 == ~E_6~0;~E_6~0 := 1; 134954#L751-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 134952#L336-24 assume !(1 == ~m_pc~0); 134951#L336-26 is_master_triggered_~__retres1~0 := 0; 134950#L347-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 134949#L348-8 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 134948#L851-24 assume !(0 != activate_threads_~tmp~1); 134947#L851-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 134946#L355-24 assume !(1 == ~t1_pc~0); 134945#L355-26 is_transmit1_triggered_~__retres1~1 := 0; 134944#L366-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 134943#L367-8 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 134942#L859-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 134941#L859-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 134940#L374-24 assume !(1 == ~t2_pc~0); 134938#L374-26 is_transmit2_triggered_~__retres1~2 := 0; 134937#L385-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 134934#L386-8 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 134932#L867-24 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 134930#L867-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 134928#L393-24 assume !(1 == ~t3_pc~0); 134926#L393-26 is_transmit3_triggered_~__retres1~3 := 0; 134924#L404-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 134922#L405-8 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 134920#L875-24 assume !(0 != activate_threads_~tmp___2~0); 134918#L875-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 134916#L412-24 assume !(1 == ~t4_pc~0); 134912#L412-26 is_transmit4_triggered_~__retres1~4 := 0; 134907#L423-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 134903#L424-8 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 134898#L883-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 134894#L883-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 134890#L431-24 assume !(1 == ~t5_pc~0); 134886#L431-26 is_transmit5_triggered_~__retres1~5 := 0; 134881#L442-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 134876#L443-8 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 134871#L891-24 assume !(0 != activate_threads_~tmp___4~0); 134866#L891-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 134862#L450-24 assume !(1 == ~t6_pc~0); 134858#L450-26 is_transmit6_triggered_~__retres1~6 := 0; 134853#L461-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 134848#L462-8 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 134844#L899-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 134840#L899-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 134836#L764-3 assume 1 == ~M_E~0;~M_E~0 := 2; 134832#L764-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 134828#L769-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 134824#L774-3 assume !(1 == ~T3_E~0); 134819#L779-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 134814#L784-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 134809#L789-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 134804#L794-3 assume !(1 == ~E_M~0); 134800#L799-3 assume 1 == ~E_1~0;~E_1~0 := 2; 134796#L804-3 assume 1 == ~E_2~0;~E_2~0 := 2; 134792#L809-3 assume 1 == ~E_3~0;~E_3~0 := 2; 134788#L814-3 assume !(1 == ~E_4~0); 134784#L819-3 assume 1 == ~E_5~0;~E_5~0 := 2; 134780#L824-3 assume 1 == ~E_6~0;~E_6~0 := 2; 134776#L829-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 134749#L520-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 134741#L557-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 134736#L558-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 134731#L1074 assume !(0 == start_simulation_~tmp~3); 134727#L1074-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 134723#L520-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 134715#L557-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 134710#L558-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 134707#L1029 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 134704#L1036 stop_simulation_#res := stop_simulation_~__retres2~0; 134699#L1037 start_simulation_#t~ret19 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 134694#L1087 assume !(0 != start_simulation_~tmp___0~1); 132663#L1055-3 [2018-11-18 10:39:58,957 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:39:58,958 INFO L82 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 3 times [2018-11-18 10:39:58,958 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:39:58,958 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:39:58,958 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:58,958 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:39:58,958 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:58,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:39:58,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:39:58,981 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:39:58,982 INFO L82 PathProgramCache]: Analyzing trace with hash 132683225, now seen corresponding path program 1 times [2018-11-18 10:39:58,982 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:39:58,982 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:39:58,982 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:58,983 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:39:58,983 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:58,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:39:59,033 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:39:59,034 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:39:59,034 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:39:59,034 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 10:39:59,034 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:39:59,034 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:39:59,034 INFO L87 Difference]: Start difference. First operand 8194 states and 11292 transitions. cyclomatic complexity: 3114 Second operand 3 states. [2018-11-18 10:39:59,105 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:39:59,105 INFO L93 Difference]: Finished difference Result 12333 states and 16727 transitions. [2018-11-18 10:39:59,107 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:39:59,107 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12333 states and 16727 transitions. [2018-11-18 10:39:59,145 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 11612 [2018-11-18 10:39:59,178 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12333 states to 12333 states and 16727 transitions. [2018-11-18 10:39:59,178 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12333 [2018-11-18 10:39:59,184 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12333 [2018-11-18 10:39:59,184 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12333 states and 16727 transitions. [2018-11-18 10:39:59,194 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:39:59,194 INFO L705 BuchiCegarLoop]: Abstraction has 12333 states and 16727 transitions. [2018-11-18 10:39:59,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12333 states and 16727 transitions. [2018-11-18 10:39:59,346 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12333 to 12333. [2018-11-18 10:39:59,346 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12333 states. [2018-11-18 10:39:59,367 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12333 states to 12333 states and 16727 transitions. [2018-11-18 10:39:59,367 INFO L728 BuchiCegarLoop]: Abstraction has 12333 states and 16727 transitions. [2018-11-18 10:39:59,367 INFO L608 BuchiCegarLoop]: Abstraction has 12333 states and 16727 transitions. [2018-11-18 10:39:59,367 INFO L442 BuchiCegarLoop]: ======== Iteration 18============ [2018-11-18 10:39:59,367 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12333 states and 16727 transitions. [2018-11-18 10:39:59,396 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 11612 [2018-11-18 10:39:59,396 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:39:59,396 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:39:59,397 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:39:59,397 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:39:59,397 INFO L794 eck$LassoCheckResult]: Stem: 153718#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 153605#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 153339#L1018 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 153340#L470 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 153159#L477 assume 1 == ~m_i~0;~m_st~0 := 0; 153160#L477-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 153168#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 153540#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 153541#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 153366#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 153367#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 153464#L507-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 153174#L686 assume !(0 == ~M_E~0); 153175#L686-2 assume !(0 == ~T1_E~0); 153188#L691-1 assume !(0 == ~T2_E~0); 153557#L696-1 assume !(0 == ~T3_E~0); 153558#L701-1 assume !(0 == ~T4_E~0); 153375#L706-1 assume !(0 == ~T5_E~0); 153376#L711-1 assume !(0 == ~T6_E~0); 153697#L716-1 assume !(0 == ~E_M~0); 153319#L721-1 assume !(0 == ~E_1~0); 153320#L726-1 assume !(0 == ~E_2~0); 153079#L731-1 assume !(0 == ~E_3~0); 153080#L736-1 assume !(0 == ~E_4~0); 153172#L741-1 assume !(0 == ~E_5~0); 153173#L746-1 assume !(0 == ~E_6~0); 153550#L751-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 153275#L336 assume !(1 == ~m_pc~0); 153218#L336-2 is_master_triggered_~__retres1~0 := 0; 153219#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 153272#L348 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 153194#L851 assume !(0 != activate_threads_~tmp~1); 153195#L851-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 153198#L355 assume !(1 == ~t1_pc~0); 153505#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 153501#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 153170#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 153171#L859 assume !(0 != activate_threads_~tmp___0~0); 153691#L859-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 153692#L374 assume !(1 == ~t2_pc~0); 153442#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 153441#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 153438#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 153439#L867 assume !(0 != activate_threads_~tmp___1~0); 153829#L867-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 153833#L393 assume !(1 == ~t3_pc~0); 153843#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 153841#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 153821#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 153328#L875 assume !(0 != activate_threads_~tmp___2~0); 153306#L875-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 153307#L412 assume !(1 == ~t4_pc~0); 153350#L412-2 is_transmit4_triggered_~__retres1~4 := 0; 153349#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 153258#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 153259#L883 assume !(0 != activate_threads_~tmp___3~0); 153572#L883-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 153369#L431 assume !(1 == ~t5_pc~0); 153355#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 153356#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 153368#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 153763#L891 assume !(0 != activate_threads_~tmp___4~0); 153759#L891-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 153628#L450 assume !(1 == ~t6_pc~0); 153629#L450-2 is_transmit6_triggered_~__retres1~6 := 0; 153626#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 153627#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 153736#L899 assume !(0 != activate_threads_~tmp___5~0); 153766#L899-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 153075#L764 assume !(1 == ~M_E~0); 153076#L764-2 assume !(1 == ~T1_E~0); 153081#L769-1 assume !(1 == ~T2_E~0); 153202#L774-1 assume !(1 == ~T3_E~0); 153203#L779-1 assume !(1 == ~T4_E~0); 153580#L784-1 assume !(1 == ~T5_E~0); 153581#L789-1 assume !(1 == ~T6_E~0); 153371#L794-1 assume !(1 == ~E_M~0); 153372#L799-1 assume !(1 == ~E_1~0); 153693#L804-1 assume !(1 == ~E_2~0); 153308#L809-1 assume !(1 == ~E_3~0); 153309#L814-1 assume !(1 == ~E_4~0); 153073#L819-1 assume !(1 == ~E_5~0); 153074#L824-1 assume !(1 == ~E_6~0); 153196#L829-1 assume { :end_inline_reset_delta_events } true; 153197#L1055-3 assume true; 155699#L1055-1 assume !false; 155698#L1056 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 155694#L661 [2018-11-18 10:39:59,397 INFO L796 eck$LassoCheckResult]: Loop: 155694#L661 assume true; 155693#L567-1 assume !false; 155692#L568 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 155690#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 155689#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 155688#L558 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 155686#L572 assume 0 != eval_~tmp~0; 155683#L572-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 155680#L580 assume !(0 != eval_~tmp_ndt_1~0); 155216#L577 assume !(0 == ~t1_st~0); 154870#L591 assume !(0 == ~t2_st~0); 154862#L605 assume !(0 == ~t3_st~0); 154858#L619 assume !(0 == ~t4_st~0); 154856#L633 assume !(0 == ~t5_st~0); 155697#L647 assume !(0 == ~t6_st~0); 155694#L661 [2018-11-18 10:39:59,398 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:39:59,398 INFO L82 PathProgramCache]: Analyzing trace with hash 931954781, now seen corresponding path program 1 times [2018-11-18 10:39:59,398 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:39:59,398 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:39:59,399 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:59,399 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:39:59,399 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:59,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:39:59,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:39:59,424 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:39:59,424 INFO L82 PathProgramCache]: Analyzing trace with hash 408754285, now seen corresponding path program 1 times [2018-11-18 10:39:59,424 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:39:59,424 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:39:59,425 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:59,425 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:39:59,425 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:59,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:39:59,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:39:59,430 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:39:59,430 INFO L82 PathProgramCache]: Analyzing trace with hash 1454134417, now seen corresponding path program 1 times [2018-11-18 10:39:59,430 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:39:59,430 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:39:59,431 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:59,431 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:39:59,431 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:39:59,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:39:59,472 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:39:59,473 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:39:59,473 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:39:59,539 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:39:59,539 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:39:59,540 INFO L87 Difference]: Start difference. First operand 12333 states and 16727 transitions. cyclomatic complexity: 4418 Second operand 3 states. [2018-11-18 10:39:59,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:39:59,724 INFO L93 Difference]: Finished difference Result 23564 states and 31647 transitions. [2018-11-18 10:39:59,724 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:39:59,724 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23564 states and 31647 transitions. [2018-11-18 10:39:59,775 INFO L131 ngComponentsAnalysis]: Automaton has 36 accepting balls. 21080 [2018-11-18 10:39:59,816 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23564 states to 23564 states and 31647 transitions. [2018-11-18 10:39:59,816 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23564 [2018-11-18 10:39:59,826 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23564 [2018-11-18 10:39:59,826 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23564 states and 31647 transitions. [2018-11-18 10:39:59,837 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:39:59,837 INFO L705 BuchiCegarLoop]: Abstraction has 23564 states and 31647 transitions. [2018-11-18 10:39:59,846 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23564 states and 31647 transitions. [2018-11-18 10:39:59,942 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23564 to 22900. [2018-11-18 10:39:59,942 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22900 states. [2018-11-18 10:39:59,962 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22900 states to 22900 states and 30799 transitions. [2018-11-18 10:39:59,962 INFO L728 BuchiCegarLoop]: Abstraction has 22900 states and 30799 transitions. [2018-11-18 10:39:59,962 INFO L608 BuchiCegarLoop]: Abstraction has 22900 states and 30799 transitions. [2018-11-18 10:39:59,962 INFO L442 BuchiCegarLoop]: ======== Iteration 19============ [2018-11-18 10:39:59,962 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22900 states and 30799 transitions. [2018-11-18 10:40:00,001 INFO L131 ngComponentsAnalysis]: Automaton has 36 accepting balls. 20416 [2018-11-18 10:40:00,002 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:40:00,002 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:40:00,002 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:40:00,002 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:40:00,003 INFO L794 eck$LassoCheckResult]: Stem: 189665#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 189536#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 189240#L1018 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 189241#L470 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 189062#L477 assume 1 == ~m_i~0;~m_st~0 := 0; 189063#L477-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 189072#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 202492#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 202491#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 202490#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 202489#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 202488#L507-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 202487#L686 assume !(0 == ~M_E~0); 202486#L686-2 assume !(0 == ~T1_E~0); 202485#L691-1 assume !(0 == ~T2_E~0); 202484#L696-1 assume !(0 == ~T3_E~0); 202483#L701-1 assume !(0 == ~T4_E~0); 202482#L706-1 assume !(0 == ~T5_E~0); 202481#L711-1 assume !(0 == ~T6_E~0); 202480#L716-1 assume !(0 == ~E_M~0); 202479#L721-1 assume !(0 == ~E_1~0); 202478#L726-1 assume !(0 == ~E_2~0); 202477#L731-1 assume !(0 == ~E_3~0); 202476#L736-1 assume !(0 == ~E_4~0); 202475#L741-1 assume !(0 == ~E_5~0); 202474#L746-1 assume !(0 == ~E_6~0); 189477#L751-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 189478#L336 assume !(1 == ~m_pc~0); 202471#L336-2 is_master_triggered_~__retres1~0 := 0; 202470#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 202469#L348 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 202468#L851 assume !(0 != activate_threads_~tmp~1); 202467#L851-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 202466#L355 assume !(1 == ~t1_pc~0); 202465#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 202464#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 202463#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 202462#L859 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 189635#L859-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 189636#L374 assume !(1 == ~t2_pc~0); 189356#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 189355#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 189352#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 189353#L867 assume !(0 != activate_threads_~tmp___1~0); 189812#L867-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 189817#L393 assume !(1 == ~t3_pc~0); 189833#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 189837#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 189795#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 189796#L875 assume !(0 != activate_threads_~tmp___2~0); 189212#L875-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 189213#L412 assume !(1 == ~t4_pc~0); 189260#L412-2 is_transmit4_triggered_~__retres1~4 := 0; 189261#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 189163#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 189164#L883 assume !(0 != activate_threads_~tmp___3~0); 189505#L883-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 189506#L431 assume !(1 == ~t5_pc~0); 189266#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 189267#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 189858#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 189859#L891 assume !(0 != activate_threads_~tmp___4~0); 189721#L891-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 189722#L450 assume !(1 == ~t6_pc~0); 189567#L450-2 is_transmit6_triggered_~__retres1~6 := 0; 189568#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 189684#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 189685#L899 assume !(0 != activate_threads_~tmp___5~0); 189735#L899-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 189736#L764 assume !(1 == ~M_E~0); 188985#L764-2 assume !(1 == ~T1_E~0); 188986#L769-1 assume !(1 == ~T2_E~0); 189107#L774-1 assume !(1 == ~T3_E~0); 189108#L779-1 assume !(1 == ~T4_E~0); 189511#L784-1 assume !(1 == ~T5_E~0); 189512#L789-1 assume !(1 == ~T6_E~0); 189284#L794-1 assume !(1 == ~E_M~0); 189285#L799-1 assume !(1 == ~E_1~0); 189776#L804-1 assume !(1 == ~E_2~0); 189214#L809-1 assume !(1 == ~E_3~0); 189215#L814-1 assume !(1 == ~E_4~0); 188977#L819-1 assume !(1 == ~E_5~0); 188978#L824-1 assume !(1 == ~E_6~0); 189102#L829-1 assume { :end_inline_reset_delta_events } true; 189103#L1055-3 assume true; 202812#L1055-1 assume !false; 202806#L1056 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 202800#L661 [2018-11-18 10:40:00,003 INFO L796 eck$LassoCheckResult]: Loop: 202800#L661 assume true; 202799#L567-1 assume !false; 202798#L568 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 202796#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 202795#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 202794#L558 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 202793#L572 assume 0 != eval_~tmp~0; 202715#L572-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 202708#L580 assume !(0 != eval_~tmp_ndt_1~0); 202709#L577 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 202348#L594 assume !(0 != eval_~tmp_ndt_2~0); 202883#L591 assume !(0 == ~t2_st~0); 202874#L605 assume !(0 == ~t3_st~0); 202817#L619 assume !(0 == ~t4_st~0); 202811#L633 assume !(0 == ~t5_st~0); 202805#L647 assume !(0 == ~t6_st~0); 202800#L661 [2018-11-18 10:40:00,003 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:40:00,003 INFO L82 PathProgramCache]: Analyzing trace with hash -1315174307, now seen corresponding path program 1 times [2018-11-18 10:40:00,003 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:40:00,003 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:40:00,004 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:40:00,004 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:40:00,004 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:40:00,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:40:00,029 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:40:00,030 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:40:00,030 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:40:00,030 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 10:40:00,030 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:40:00,030 INFO L82 PathProgramCache]: Analyzing trace with hash -68659005, now seen corresponding path program 1 times [2018-11-18 10:40:00,030 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:40:00,030 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:40:00,031 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:40:00,031 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:40:00,031 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:40:00,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:40:00,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:40:00,093 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:40:00,094 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:40:00,094 INFO L87 Difference]: Start difference. First operand 22900 states and 30799 transitions. cyclomatic complexity: 7935 Second operand 3 states. [2018-11-18 10:40:00,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:40:00,121 INFO L93 Difference]: Finished difference Result 16153 states and 21690 transitions. [2018-11-18 10:40:00,121 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:40:00,121 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16153 states and 21690 transitions. [2018-11-18 10:40:00,158 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 15132 [2018-11-18 10:40:00,187 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16153 states to 16153 states and 21690 transitions. [2018-11-18 10:40:00,187 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16153 [2018-11-18 10:40:00,194 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16153 [2018-11-18 10:40:00,194 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16153 states and 21690 transitions. [2018-11-18 10:40:00,201 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:40:00,201 INFO L705 BuchiCegarLoop]: Abstraction has 16153 states and 21690 transitions. [2018-11-18 10:40:00,208 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16153 states and 21690 transitions. [2018-11-18 10:40:00,273 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16153 to 16153. [2018-11-18 10:40:00,274 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16153 states. [2018-11-18 10:40:00,287 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16153 states to 16153 states and 21690 transitions. [2018-11-18 10:40:00,287 INFO L728 BuchiCegarLoop]: Abstraction has 16153 states and 21690 transitions. [2018-11-18 10:40:00,287 INFO L608 BuchiCegarLoop]: Abstraction has 16153 states and 21690 transitions. [2018-11-18 10:40:00,287 INFO L442 BuchiCegarLoop]: ======== Iteration 20============ [2018-11-18 10:40:00,287 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16153 states and 21690 transitions. [2018-11-18 10:40:00,313 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 15132 [2018-11-18 10:40:00,313 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:40:00,313 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:40:00,314 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:40:00,314 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:40:00,315 INFO L794 eck$LassoCheckResult]: Stem: 228682#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 228562#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 228291#L1018 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 228292#L470 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 228117#L477 assume 1 == ~m_i~0;~m_st~0 := 0; 228118#L477-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 228126#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 228494#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 228495#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 228320#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 228321#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 228418#L507-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 228132#L686 assume !(0 == ~M_E~0); 228133#L686-2 assume !(0 == ~T1_E~0); 228146#L691-1 assume !(0 == ~T2_E~0); 228510#L696-1 assume !(0 == ~T3_E~0); 228511#L701-1 assume !(0 == ~T4_E~0); 228329#L706-1 assume !(0 == ~T5_E~0); 228330#L711-1 assume !(0 == ~T6_E~0); 228659#L716-1 assume !(0 == ~E_M~0); 228275#L721-1 assume !(0 == ~E_1~0); 228276#L726-1 assume !(0 == ~E_2~0); 228042#L731-1 assume !(0 == ~E_3~0); 228043#L736-1 assume !(0 == ~E_4~0); 228130#L741-1 assume !(0 == ~E_5~0); 228131#L746-1 assume !(0 == ~E_6~0); 228503#L751-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 228234#L336 assume !(1 == ~m_pc~0); 228177#L336-2 is_master_triggered_~__retres1~0 := 0; 228178#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 228231#L348 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 228153#L851 assume !(0 != activate_threads_~tmp~1); 228154#L851-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 228158#L355 assume !(1 == ~t1_pc~0); 228460#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 228456#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 228128#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 228129#L859 assume !(0 != activate_threads_~tmp___0~0); 228653#L859-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 228654#L374 assume !(1 == ~t2_pc~0); 228396#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 228395#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 228392#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 228393#L867 assume !(0 != activate_threads_~tmp___1~0); 228792#L867-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 228793#L393 assume !(1 == ~t3_pc~0); 228804#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 228802#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 228783#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 228281#L875 assume !(0 != activate_threads_~tmp___2~0); 228264#L875-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 228265#L412 assume !(1 == ~t4_pc~0); 228303#L412-2 is_transmit4_triggered_~__retres1~4 := 0; 228302#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 228217#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 228218#L883 assume !(0 != activate_threads_~tmp___3~0); 228525#L883-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 228323#L431 assume !(1 == ~t5_pc~0); 228308#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 228309#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 228322#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 228720#L891 assume !(0 != activate_threads_~tmp___4~0); 228716#L891-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 228586#L450 assume !(1 == ~t6_pc~0); 228587#L450-2 is_transmit6_triggered_~__retres1~6 := 0; 228584#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 228585#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 228696#L899 assume !(0 != activate_threads_~tmp___5~0); 228723#L899-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 228038#L764 assume !(1 == ~M_E~0); 228039#L764-2 assume !(1 == ~T1_E~0); 228044#L769-1 assume !(1 == ~T2_E~0); 228161#L774-1 assume !(1 == ~T3_E~0); 228162#L779-1 assume !(1 == ~T4_E~0); 228534#L784-1 assume !(1 == ~T5_E~0); 228535#L789-1 assume !(1 == ~T6_E~0); 228325#L794-1 assume !(1 == ~E_M~0); 228326#L799-1 assume !(1 == ~E_1~0); 228655#L804-1 assume !(1 == ~E_2~0); 228266#L809-1 assume !(1 == ~E_3~0); 228267#L814-1 assume !(1 == ~E_4~0); 228036#L819-1 assume !(1 == ~E_5~0); 228037#L824-1 assume !(1 == ~E_6~0); 228156#L829-1 assume { :end_inline_reset_delta_events } true; 228157#L1055-3 assume true; 242007#L1055-1 assume !false; 242004#L1056 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 237942#L661 [2018-11-18 10:40:00,315 INFO L796 eck$LassoCheckResult]: Loop: 237942#L661 assume true; 242001#L567-1 assume !false; 241999#L568 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 241996#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 241994#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 241992#L558 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 241990#L572 assume 0 != eval_~tmp~0; 241989#L572-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 241987#L580 assume !(0 != eval_~tmp_ndt_1~0); 241985#L577 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 233356#L594 assume !(0 != eval_~tmp_ndt_2~0); 233353#L591 assume !(0 == ~t2_st~0); 233345#L605 assume !(0 == ~t3_st~0); 233343#L619 assume !(0 == ~t4_st~0); 233341#L633 assume !(0 == ~t5_st~0); 237944#L647 assume !(0 == ~t6_st~0); 237942#L661 [2018-11-18 10:40:00,315 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:40:00,315 INFO L82 PathProgramCache]: Analyzing trace with hash 931954781, now seen corresponding path program 2 times [2018-11-18 10:40:00,315 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:40:00,315 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:40:00,316 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:40:00,316 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:40:00,316 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:40:00,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:40:00,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:40:00,339 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:40:00,339 INFO L82 PathProgramCache]: Analyzing trace with hash -68659005, now seen corresponding path program 2 times [2018-11-18 10:40:00,339 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:40:00,339 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:40:00,343 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:40:00,343 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:40:00,343 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:40:00,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:40:00,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:40:00,347 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:40:00,347 INFO L82 PathProgramCache]: Analyzing trace with hash -2021613281, now seen corresponding path program 1 times [2018-11-18 10:40:00,348 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:40:00,348 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:40:00,348 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:40:00,348 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:40:00,348 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:40:00,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:40:00,389 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:40:00,389 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:40:00,389 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:40:00,472 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:40:00,472 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:40:00,472 INFO L87 Difference]: Start difference. First operand 16153 states and 21690 transitions. cyclomatic complexity: 5561 Second operand 3 states. [2018-11-18 10:40:00,561 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:40:00,561 INFO L93 Difference]: Finished difference Result 30557 states and 40806 transitions. [2018-11-18 10:40:00,561 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:40:00,562 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30557 states and 40806 transitions. [2018-11-18 10:40:00,642 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 28608 [2018-11-18 10:40:00,834 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30557 states to 30557 states and 40806 transitions. [2018-11-18 10:40:00,834 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30557 [2018-11-18 10:40:00,845 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30557 [2018-11-18 10:40:00,845 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30557 states and 40806 transitions. [2018-11-18 10:40:00,859 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:40:00,859 INFO L705 BuchiCegarLoop]: Abstraction has 30557 states and 40806 transitions. [2018-11-18 10:40:00,869 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30557 states and 40806 transitions. [2018-11-18 10:40:01,015 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30557 to 28901. [2018-11-18 10:40:01,015 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28901 states. [2018-11-18 10:40:01,039 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28901 states to 28901 states and 38742 transitions. [2018-11-18 10:40:01,040 INFO L728 BuchiCegarLoop]: Abstraction has 28901 states and 38742 transitions. [2018-11-18 10:40:01,040 INFO L608 BuchiCegarLoop]: Abstraction has 28901 states and 38742 transitions. [2018-11-18 10:40:01,040 INFO L442 BuchiCegarLoop]: ======== Iteration 21============ [2018-11-18 10:40:01,040 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28901 states and 38742 transitions. [2018-11-18 10:40:01,087 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 26952 [2018-11-18 10:40:01,087 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:40:01,087 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:40:01,088 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:40:01,088 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:40:01,088 INFO L794 eck$LassoCheckResult]: Stem: 275430#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 275305#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 275014#L1018 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 275015#L470 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 274836#L477 assume 1 == ~m_i~0;~m_st~0 := 0; 274837#L477-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 274845#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 275235#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 275236#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 275046#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 275047#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 275151#L507-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 274853#L686 assume !(0 == ~M_E~0); 274854#L686-2 assume !(0 == ~T1_E~0); 274864#L691-1 assume !(0 == ~T2_E~0); 275250#L696-1 assume !(0 == ~T3_E~0); 275251#L701-1 assume !(0 == ~T4_E~0); 275055#L706-1 assume !(0 == ~T5_E~0); 275056#L711-1 assume !(0 == ~T6_E~0); 275405#L716-1 assume !(0 == ~E_M~0); 274996#L721-1 assume !(0 == ~E_1~0); 274997#L726-1 assume !(0 == ~E_2~0); 274760#L731-1 assume !(0 == ~E_3~0); 274761#L736-1 assume !(0 == ~E_4~0); 274849#L741-1 assume !(0 == ~E_5~0); 274850#L746-1 assume !(0 == ~E_6~0); 275245#L751-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 274951#L336 assume !(1 == ~m_pc~0); 274894#L336-2 is_master_triggered_~__retres1~0 := 0; 274895#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 274950#L348 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 274870#L851 assume !(0 != activate_threads_~tmp~1); 274871#L851-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 274875#L355 assume !(1 == ~t1_pc~0); 275195#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 275194#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 274847#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 274848#L859 assume !(0 != activate_threads_~tmp___0~0); 275398#L859-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 275399#L374 assume !(1 == ~t2_pc~0); 275122#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 275121#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 275118#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 275119#L867 assume !(0 != activate_threads_~tmp___1~0); 275573#L867-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 275575#L393 assume !(1 == ~t3_pc~0); 275588#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 275587#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 275563#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 275004#L875 assume !(0 != activate_threads_~tmp___2~0); 274983#L875-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 274984#L412 assume !(1 == ~t4_pc~0); 275029#L412-2 is_transmit4_triggered_~__retres1~4 := 0; 275028#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 274934#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 274935#L883 assume !(0 != activate_threads_~tmp___3~0); 275267#L883-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 275049#L431 assume !(1 == ~t5_pc~0); 275034#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 275035#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 275048#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 275489#L891 assume !(0 != activate_threads_~tmp___4~0); 275484#L891-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 275329#L450 assume !(1 == ~t6_pc~0); 275330#L450-2 is_transmit6_triggered_~__retres1~6 := 0; 275327#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 275328#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 275453#L899 assume !(0 != activate_threads_~tmp___5~0); 275493#L899-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 274756#L764 assume !(1 == ~M_E~0); 274757#L764-2 assume !(1 == ~T1_E~0); 274762#L769-1 assume !(1 == ~T2_E~0); 274879#L774-1 assume !(1 == ~T3_E~0); 274880#L779-1 assume !(1 == ~T4_E~0); 275276#L784-1 assume !(1 == ~T5_E~0); 275277#L789-1 assume !(1 == ~T6_E~0); 275051#L794-1 assume !(1 == ~E_M~0); 275052#L799-1 assume !(1 == ~E_1~0); 275400#L804-1 assume !(1 == ~E_2~0); 274989#L809-1 assume !(1 == ~E_3~0); 274990#L814-1 assume !(1 == ~E_4~0); 274754#L819-1 assume !(1 == ~E_5~0); 274755#L824-1 assume !(1 == ~E_6~0); 274873#L829-1 assume { :end_inline_reset_delta_events } true; 274874#L1055-3 assume true; 302567#L1055-1 assume !false; 302565#L1056 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 293937#L661 [2018-11-18 10:40:01,088 INFO L796 eck$LassoCheckResult]: Loop: 293937#L661 assume true; 302562#L567-1 assume !false; 302560#L568 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 285730#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 285731#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 290614#L558 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 290612#L572 assume 0 != eval_~tmp~0; 290610#L572-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 290607#L580 assume !(0 != eval_~tmp_ndt_1~0); 290604#L577 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 290602#L594 assume !(0 != eval_~tmp_ndt_2~0); 290600#L591 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 280227#L608 assume !(0 != eval_~tmp_ndt_3~0); 290596#L605 assume !(0 == ~t3_st~0); 290594#L619 assume !(0 == ~t4_st~0); 293943#L633 assume !(0 == ~t5_st~0); 293938#L647 assume !(0 == ~t6_st~0); 293937#L661 [2018-11-18 10:40:01,088 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:40:01,088 INFO L82 PathProgramCache]: Analyzing trace with hash 931954781, now seen corresponding path program 3 times [2018-11-18 10:40:01,089 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:40:01,089 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:40:01,089 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:40:01,089 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:40:01,089 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:40:01,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:40:01,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:40:01,113 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:40:01,113 INFO L82 PathProgramCache]: Analyzing trace with hash 508645132, now seen corresponding path program 1 times [2018-11-18 10:40:01,113 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:40:01,113 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:40:01,114 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:40:01,114 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:40:01,114 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:40:01,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:40:01,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:40:01,118 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:40:01,118 INFO L82 PathProgramCache]: Analyzing trace with hash 96604720, now seen corresponding path program 1 times [2018-11-18 10:40:01,118 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:40:01,118 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:40:01,119 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:40:01,119 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:40:01,119 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:40:01,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:40:01,156 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:40:01,157 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:40:01,157 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:40:01,244 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:40:01,244 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:40:01,244 INFO L87 Difference]: Start difference. First operand 28901 states and 38742 transitions. cyclomatic complexity: 9865 Second operand 3 states. [2018-11-18 10:40:01,397 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:40:01,397 INFO L93 Difference]: Finished difference Result 40609 states and 54194 transitions. [2018-11-18 10:40:01,397 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:40:01,397 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40609 states and 54194 transitions. [2018-11-18 10:40:01,479 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 37774 [2018-11-18 10:40:01,547 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40609 states to 40609 states and 54194 transitions. [2018-11-18 10:40:01,547 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 40609 [2018-11-18 10:40:01,563 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 40609 [2018-11-18 10:40:01,563 INFO L73 IsDeterministic]: Start isDeterministic. Operand 40609 states and 54194 transitions. [2018-11-18 10:40:01,579 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:40:01,579 INFO L705 BuchiCegarLoop]: Abstraction has 40609 states and 54194 transitions. [2018-11-18 10:40:01,594 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40609 states and 54194 transitions. [2018-11-18 10:40:01,741 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40609 to 39265. [2018-11-18 10:40:01,741 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39265 states. [2018-11-18 10:40:01,774 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39265 states to 39265 states and 52514 transitions. [2018-11-18 10:40:01,775 INFO L728 BuchiCegarLoop]: Abstraction has 39265 states and 52514 transitions. [2018-11-18 10:40:01,775 INFO L608 BuchiCegarLoop]: Abstraction has 39265 states and 52514 transitions. [2018-11-18 10:40:01,775 INFO L442 BuchiCegarLoop]: ======== Iteration 22============ [2018-11-18 10:40:01,775 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39265 states and 52514 transitions. [2018-11-18 10:40:01,842 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 36430 [2018-11-18 10:40:01,842 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:40:01,842 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:40:01,843 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:40:01,843 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:40:01,844 INFO L794 eck$LassoCheckResult]: Stem: 344936#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 344811#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 344530#L1018 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 344531#L470 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 344353#L477 assume 1 == ~m_i~0;~m_st~0 := 0; 344354#L477-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 344361#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 344743#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 344744#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 344562#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 344563#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 344662#L507-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 344370#L686 assume !(0 == ~M_E~0); 344371#L686-2 assume !(0 == ~T1_E~0); 344382#L691-1 assume !(0 == ~T2_E~0); 344760#L696-1 assume !(0 == ~T3_E~0); 344761#L701-1 assume !(0 == ~T4_E~0); 344571#L706-1 assume !(0 == ~T5_E~0); 344572#L711-1 assume !(0 == ~T6_E~0); 344911#L716-1 assume !(0 == ~E_M~0); 344511#L721-1 assume !(0 == ~E_1~0); 344512#L726-1 assume !(0 == ~E_2~0); 344278#L731-1 assume !(0 == ~E_3~0); 344279#L736-1 assume !(0 == ~E_4~0); 344366#L741-1 assume !(0 == ~E_5~0); 344367#L746-1 assume !(0 == ~E_6~0); 344753#L751-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 344468#L336 assume !(1 == ~m_pc~0); 344410#L336-2 is_master_triggered_~__retres1~0 := 0; 344411#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 344467#L348 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 344388#L851 assume !(0 != activate_threads_~tmp~1); 344389#L851-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 344392#L355 assume !(1 == ~t1_pc~0); 344705#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 344704#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 344364#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 344365#L859 assume !(0 != activate_threads_~tmp___0~0); 344901#L859-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 344902#L374 assume !(1 == ~t2_pc~0); 344638#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 344637#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 344634#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 344635#L867 assume !(0 != activate_threads_~tmp___1~0); 345071#L867-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 345073#L393 assume !(1 == ~t3_pc~0); 345089#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 345088#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 345061#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 344519#L875 assume !(0 != activate_threads_~tmp___2~0); 344499#L875-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 344500#L412 assume !(1 == ~t4_pc~0); 344545#L412-2 is_transmit4_triggered_~__retres1~4 := 0; 344544#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 344451#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 344452#L883 assume !(0 != activate_threads_~tmp___3~0); 344779#L883-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 344565#L431 assume !(1 == ~t5_pc~0); 344551#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 344552#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 344564#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 345002#L891 assume !(0 != activate_threads_~tmp___4~0); 344998#L891-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 344834#L450 assume !(1 == ~t6_pc~0); 344835#L450-2 is_transmit6_triggered_~__retres1~6 := 0; 344832#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 344833#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 344964#L899 assume !(0 != activate_threads_~tmp___5~0); 345005#L899-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 344274#L764 assume !(1 == ~M_E~0); 344275#L764-2 assume !(1 == ~T1_E~0); 344280#L769-1 assume !(1 == ~T2_E~0); 344395#L774-1 assume !(1 == ~T3_E~0); 344396#L779-1 assume !(1 == ~T4_E~0); 344788#L784-1 assume !(1 == ~T5_E~0); 344789#L789-1 assume !(1 == ~T6_E~0); 344567#L794-1 assume !(1 == ~E_M~0); 344568#L799-1 assume !(1 == ~E_1~0); 344903#L804-1 assume !(1 == ~E_2~0); 344504#L809-1 assume !(1 == ~E_3~0); 344505#L814-1 assume !(1 == ~E_4~0); 344272#L819-1 assume !(1 == ~E_5~0); 344273#L824-1 assume !(1 == ~E_6~0); 344390#L829-1 assume { :end_inline_reset_delta_events } true; 344391#L1055-3 assume true; 361221#L1055-1 assume !false; 361219#L1056 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 361214#L661 [2018-11-18 10:40:01,844 INFO L796 eck$LassoCheckResult]: Loop: 361214#L661 assume true; 361212#L567-1 assume !false; 361210#L568 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 361207#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 361205#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 361202#L558 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 361200#L572 assume 0 != eval_~tmp~0; 361197#L572-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 361194#L580 assume !(0 != eval_~tmp_ndt_1~0); 361192#L577 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 361189#L594 assume !(0 != eval_~tmp_ndt_2~0); 361187#L591 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 361182#L608 assume !(0 != eval_~tmp_ndt_3~0); 361177#L605 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 361171#L622 assume !(0 != eval_~tmp_ndt_4~0); 361166#L619 assume !(0 == ~t4_st~0); 361163#L633 assume !(0 == ~t5_st~0); 361218#L647 assume !(0 == ~t6_st~0); 361214#L661 [2018-11-18 10:40:01,844 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:40:01,844 INFO L82 PathProgramCache]: Analyzing trace with hash 931954781, now seen corresponding path program 4 times [2018-11-18 10:40:01,844 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:40:01,844 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:40:01,845 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:40:01,845 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:40:01,845 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:40:01,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:40:01,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:40:01,865 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:40:01,866 INFO L82 PathProgramCache]: Analyzing trace with hash -1603895772, now seen corresponding path program 1 times [2018-11-18 10:40:01,866 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:40:01,866 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:40:01,866 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:40:01,866 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:40:01,867 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:40:01,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:40:01,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:40:01,870 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:40:01,871 INFO L82 PathProgramCache]: Analyzing trace with hash -1492246656, now seen corresponding path program 1 times [2018-11-18 10:40:01,871 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:40:01,871 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:40:01,871 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:40:01,871 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:40:01,872 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:40:01,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:40:02,029 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:40:02,029 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:40:02,029 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:40:02,147 WARN L180 SmtUtils]: Spent 116.00 ms on a formula simplification. DAG size of input: 44 DAG size of output: 42 [2018-11-18 10:40:02,198 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:40:02,198 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:40:02,199 INFO L87 Difference]: Start difference. First operand 39265 states and 52514 transitions. cyclomatic complexity: 13273 Second operand 3 states. [2018-11-18 10:40:02,365 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:40:02,365 INFO L93 Difference]: Finished difference Result 55851 states and 74354 transitions. [2018-11-18 10:40:02,365 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:40:02,365 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55851 states and 74354 transitions. [2018-11-18 10:40:02,522 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 51708 [2018-11-18 10:40:02,606 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55851 states to 55851 states and 74354 transitions. [2018-11-18 10:40:02,606 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 55851 [2018-11-18 10:40:02,630 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 55851 [2018-11-18 10:40:02,630 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55851 states and 74354 transitions. [2018-11-18 10:40:02,651 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:40:02,651 INFO L705 BuchiCegarLoop]: Abstraction has 55851 states and 74354 transitions. [2018-11-18 10:40:02,671 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55851 states and 74354 transitions. [2018-11-18 10:40:02,895 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55851 to 54303. [2018-11-18 10:40:02,895 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54303 states. [2018-11-18 10:40:02,950 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54303 states to 54303 states and 72446 transitions. [2018-11-18 10:40:02,950 INFO L728 BuchiCegarLoop]: Abstraction has 54303 states and 72446 transitions. [2018-11-18 10:40:02,950 INFO L608 BuchiCegarLoop]: Abstraction has 54303 states and 72446 transitions. [2018-11-18 10:40:02,950 INFO L442 BuchiCegarLoop]: ======== Iteration 23============ [2018-11-18 10:40:02,950 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54303 states and 72446 transitions. [2018-11-18 10:40:03,048 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 50160 [2018-11-18 10:40:03,048 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:40:03,048 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:40:03,048 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:40:03,049 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:40:03,049 INFO L794 eck$LassoCheckResult]: Stem: 440103#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 439970#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 439666#L1018 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 439667#L470 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 439480#L477 assume 1 == ~m_i~0;~m_st~0 := 0; 439481#L477-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 439488#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 439895#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 439896#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 439704#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 439705#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 439807#L507-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 439498#L686 assume !(0 == ~M_E~0); 439499#L686-2 assume !(0 == ~T1_E~0); 439510#L691-1 assume !(0 == ~T2_E~0); 439912#L696-1 assume !(0 == ~T3_E~0); 439913#L701-1 assume !(0 == ~T4_E~0); 439713#L706-1 assume !(0 == ~T5_E~0); 439714#L711-1 assume !(0 == ~T6_E~0); 440078#L716-1 assume !(0 == ~E_M~0); 439647#L721-1 assume !(0 == ~E_1~0); 439648#L726-1 assume !(0 == ~E_2~0); 439402#L731-1 assume !(0 == ~E_3~0); 439403#L736-1 assume !(0 == ~E_4~0); 439492#L741-1 assume !(0 == ~E_5~0); 439493#L746-1 assume !(0 == ~E_6~0); 439907#L751-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 439602#L336 assume !(1 == ~m_pc~0); 439544#L336-2 is_master_triggered_~__retres1~0 := 0; 439545#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 439601#L348 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 439519#L851 assume !(0 != activate_threads_~tmp~1); 439520#L851-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 439525#L355 assume !(1 == ~t1_pc~0); 439851#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 439850#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 439490#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 439491#L859 assume !(0 != activate_threads_~tmp___0~0); 440070#L859-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 440071#L374 assume !(1 == ~t2_pc~0); 439781#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 439780#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 439777#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 439778#L867 assume !(0 != activate_threads_~tmp___1~0); 440248#L867-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 440251#L393 assume !(1 == ~t3_pc~0); 440269#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 440268#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 440232#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 439658#L875 assume !(0 != activate_threads_~tmp___2~0); 439635#L875-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 439636#L412 assume !(1 == ~t4_pc~0); 439687#L412-2 is_transmit4_triggered_~__retres1~4 := 0; 439686#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 439585#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 439586#L883 assume !(0 != activate_threads_~tmp___3~0); 439931#L883-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 439707#L431 assume !(1 == ~t5_pc~0); 439692#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 439693#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 439706#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 439897#L891 assume !(0 != activate_threads_~tmp___4~0); 440147#L891-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 439996#L450 assume !(1 == ~t6_pc~0); 439997#L450-2 is_transmit6_triggered_~__retres1~6 := 0; 439994#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 439995#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 440123#L899 assume !(0 != activate_threads_~tmp___5~0); 440157#L899-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 439398#L764 assume !(1 == ~M_E~0); 439399#L764-2 assume !(1 == ~T1_E~0); 439404#L769-1 assume !(1 == ~T2_E~0); 439528#L774-1 assume !(1 == ~T3_E~0); 439529#L779-1 assume !(1 == ~T4_E~0); 439942#L784-1 assume !(1 == ~T5_E~0); 439943#L789-1 assume !(1 == ~T6_E~0); 439709#L794-1 assume !(1 == ~E_M~0); 439710#L799-1 assume !(1 == ~E_1~0); 440072#L804-1 assume !(1 == ~E_2~0); 439640#L809-1 assume !(1 == ~E_3~0); 439641#L814-1 assume !(1 == ~E_4~0); 439396#L819-1 assume !(1 == ~E_5~0); 439397#L824-1 assume !(1 == ~E_6~0); 439522#L829-1 assume { :end_inline_reset_delta_events } true; 439523#L1055-3 assume true; 450312#L1055-1 assume !false; 450303#L1056 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 450295#L661 [2018-11-18 10:40:03,049 INFO L796 eck$LassoCheckResult]: Loop: 450295#L661 assume true; 450290#L567-1 assume !false; 450285#L568 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 450279#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 450273#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 450269#L558 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 450265#L572 assume 0 != eval_~tmp~0; 450260#L572-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 450252#L580 assume !(0 != eval_~tmp_ndt_1~0); 450247#L577 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 450245#L594 assume !(0 != eval_~tmp_ndt_2~0); 450244#L591 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 450133#L608 assume !(0 != eval_~tmp_ndt_3~0); 446064#L605 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 446065#L622 assume !(0 != eval_~tmp_ndt_4~0); 446056#L619 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 446057#L636 assume !(0 != eval_~tmp_ndt_5~0); 450311#L633 assume !(0 == ~t5_st~0); 450302#L647 assume !(0 == ~t6_st~0); 450295#L661 [2018-11-18 10:40:03,049 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:40:03,049 INFO L82 PathProgramCache]: Analyzing trace with hash 931954781, now seen corresponding path program 5 times [2018-11-18 10:40:03,049 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:40:03,050 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:40:03,050 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:40:03,050 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:40:03,050 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:40:03,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:40:03,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:40:03,074 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:40:03,074 INFO L82 PathProgramCache]: Analyzing trace with hash 1812646315, now seen corresponding path program 1 times [2018-11-18 10:40:03,074 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:40:03,074 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:40:03,075 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:40:03,075 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:40:03,075 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:40:03,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:40:03,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:40:03,080 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:40:03,080 INFO L82 PathProgramCache]: Analyzing trace with hash 978801615, now seen corresponding path program 1 times [2018-11-18 10:40:03,080 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:40:03,080 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:40:03,080 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:40:03,081 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:40:03,081 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:40:03,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:40:03,113 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:40:03,113 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:40:03,113 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:40:03,227 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:40:03,228 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:40:03,228 INFO L87 Difference]: Start difference. First operand 54303 states and 72446 transitions. cyclomatic complexity: 18167 Second operand 3 states. [2018-11-18 10:40:03,453 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:40:03,453 INFO L93 Difference]: Finished difference Result 97557 states and 129858 transitions. [2018-11-18 10:40:03,454 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:40:03,454 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 97557 states and 129858 transitions. [2018-11-18 10:40:03,712 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 89364 [2018-11-18 10:40:04,142 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 97557 states to 97557 states and 129858 transitions. [2018-11-18 10:40:04,142 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 97557 [2018-11-18 10:40:04,161 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 97557 [2018-11-18 10:40:04,161 INFO L73 IsDeterministic]: Start isDeterministic. Operand 97557 states and 129858 transitions. [2018-11-18 10:40:04,181 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:40:04,181 INFO L705 BuchiCegarLoop]: Abstraction has 97557 states and 129858 transitions. [2018-11-18 10:40:04,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97557 states and 129858 transitions. [2018-11-18 10:40:04,573 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97557 to 95073. [2018-11-18 10:40:04,573 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 95073 states. [2018-11-18 10:40:04,662 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95073 states to 95073 states and 126942 transitions. [2018-11-18 10:40:04,662 INFO L728 BuchiCegarLoop]: Abstraction has 95073 states and 126942 transitions. [2018-11-18 10:40:04,662 INFO L608 BuchiCegarLoop]: Abstraction has 95073 states and 126942 transitions. [2018-11-18 10:40:04,662 INFO L442 BuchiCegarLoop]: ======== Iteration 24============ [2018-11-18 10:40:04,662 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 95073 states and 126942 transitions. [2018-11-18 10:40:04,832 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 86880 [2018-11-18 10:40:04,832 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:40:04,833 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:40:04,833 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:40:04,833 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:40:04,834 INFO L794 eck$LassoCheckResult]: Stem: 591956#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 591827#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 591531#L1018 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 591532#L470 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 591347#L477 assume 1 == ~m_i~0;~m_st~0 := 0; 591348#L477-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 591355#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 591752#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 591753#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 591563#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 591564#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 591667#L507-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 591365#L686 assume !(0 == ~M_E~0); 591366#L686-2 assume !(0 == ~T1_E~0); 591376#L691-1 assume !(0 == ~T2_E~0); 591768#L696-1 assume !(0 == ~T3_E~0); 591769#L701-1 assume !(0 == ~T4_E~0); 591572#L706-1 assume !(0 == ~T5_E~0); 591573#L711-1 assume !(0 == ~T6_E~0); 591929#L716-1 assume !(0 == ~E_M~0); 591511#L721-1 assume !(0 == ~E_1~0); 591512#L726-1 assume !(0 == ~E_2~0); 591270#L731-1 assume !(0 == ~E_3~0); 591271#L736-1 assume !(0 == ~E_4~0); 591359#L741-1 assume !(0 == ~E_5~0); 591360#L746-1 assume !(0 == ~E_6~0); 591762#L751-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 591467#L336 assume !(1 == ~m_pc~0); 591409#L336-2 is_master_triggered_~__retres1~0 := 0; 591410#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 591466#L348 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 591385#L851 assume !(0 != activate_threads_~tmp~1); 591386#L851-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 591390#L355 assume !(1 == ~t1_pc~0); 591713#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 591712#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 591357#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 591358#L859 assume !(0 != activate_threads_~tmp___0~0); 591921#L859-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 591922#L374 assume !(1 == ~t2_pc~0); 591640#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 591639#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 591636#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 591637#L867 assume !(0 != activate_threads_~tmp___1~0); 592092#L867-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 592094#L393 assume !(1 == ~t3_pc~0); 592106#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 592105#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 592074#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 591521#L875 assume !(0 != activate_threads_~tmp___2~0); 591498#L875-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 591499#L412 assume !(1 == ~t4_pc~0); 591547#L412-2 is_transmit4_triggered_~__retres1~4 := 0; 591546#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 591450#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 591451#L883 assume !(0 != activate_threads_~tmp___3~0); 591789#L883-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 591566#L431 assume !(1 == ~t5_pc~0); 591552#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 591553#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 591565#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 591754#L891 assume !(0 != activate_threads_~tmp___4~0); 592009#L891-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 591850#L450 assume !(1 == ~t6_pc~0); 591851#L450-2 is_transmit6_triggered_~__retres1~6 := 0; 591848#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 591849#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 591975#L899 assume !(0 != activate_threads_~tmp___5~0); 592018#L899-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 591266#L764 assume !(1 == ~M_E~0); 591267#L764-2 assume !(1 == ~T1_E~0); 591272#L769-1 assume !(1 == ~T2_E~0); 591392#L774-1 assume !(1 == ~T3_E~0); 591393#L779-1 assume !(1 == ~T4_E~0); 591798#L784-1 assume !(1 == ~T5_E~0); 591799#L789-1 assume !(1 == ~T6_E~0); 591568#L794-1 assume !(1 == ~E_M~0); 591569#L799-1 assume !(1 == ~E_1~0); 591923#L804-1 assume !(1 == ~E_2~0); 591504#L809-1 assume !(1 == ~E_3~0); 591505#L814-1 assume !(1 == ~E_4~0); 591264#L819-1 assume !(1 == ~E_5~0); 591265#L824-1 assume !(1 == ~E_6~0); 591387#L829-1 assume { :end_inline_reset_delta_events } true; 591388#L1055-3 assume true; 623048#L1055-1 assume !false; 623047#L1056 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 623044#L661 [2018-11-18 10:40:04,834 INFO L796 eck$LassoCheckResult]: Loop: 623044#L661 assume true; 623043#L567-1 assume !false; 623041#L568 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 623038#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 623033#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 623030#L558 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 623026#L572 assume 0 != eval_~tmp~0; 623023#L572-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 623020#L580 assume !(0 != eval_~tmp_ndt_1~0); 623018#L577 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 623015#L594 assume !(0 != eval_~tmp_ndt_2~0); 623011#L591 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 622742#L608 assume !(0 != eval_~tmp_ndt_3~0); 623007#L605 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 623053#L622 assume !(0 != eval_~tmp_ndt_4~0); 623052#L619 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 623050#L636 assume !(0 != eval_~tmp_ndt_5~0); 623049#L633 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 622791#L650 assume !(0 != eval_~tmp_ndt_6~0); 623046#L647 assume !(0 == ~t6_st~0); 623044#L661 [2018-11-18 10:40:04,834 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:40:04,834 INFO L82 PathProgramCache]: Analyzing trace with hash 931954781, now seen corresponding path program 6 times [2018-11-18 10:40:04,834 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:40:04,834 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:40:04,835 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:40:04,835 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:40:04,835 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:40:04,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:40:04,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:40:04,856 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:40:04,856 INFO L82 PathProgramCache]: Analyzing trace with hash 357263237, now seen corresponding path program 1 times [2018-11-18 10:40:04,856 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:40:04,856 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:40:04,857 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:40:04,857 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:40:04,857 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:40:04,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:40:04,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:40:04,861 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:40:04,861 INFO L82 PathProgramCache]: Analyzing trace with hash 277881313, now seen corresponding path program 1 times [2018-11-18 10:40:04,861 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:40:04,861 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:40:04,862 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:40:04,862 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:40:04,862 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:40:04,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:40:04,896 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:40:04,896 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:40:04,897 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 10:40:04,980 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:40:04,980 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:40:04,980 INFO L87 Difference]: Start difference. First operand 95073 states and 126942 transitions. cyclomatic complexity: 31893 Second operand 3 states. [2018-11-18 10:40:05,254 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:40:05,254 INFO L93 Difference]: Finished difference Result 132554 states and 176321 transitions. [2018-11-18 10:40:05,256 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:40:05,256 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 132554 states and 176321 transitions. [2018-11-18 10:40:05,931 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 123929 [2018-11-18 10:40:06,077 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 132554 states to 132554 states and 176321 transitions. [2018-11-18 10:40:06,077 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 132554 [2018-11-18 10:40:06,117 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 132554 [2018-11-18 10:40:06,117 INFO L73 IsDeterministic]: Start isDeterministic. Operand 132554 states and 176321 transitions. [2018-11-18 10:40:06,153 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:40:06,154 INFO L705 BuchiCegarLoop]: Abstraction has 132554 states and 176321 transitions. [2018-11-18 10:40:06,192 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132554 states and 176321 transitions. [2018-11-18 10:40:06,749 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132554 to 131474. [2018-11-18 10:40:06,749 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 131474 states. [2018-11-18 10:40:06,887 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 131474 states to 131474 states and 175241 transitions. [2018-11-18 10:40:06,888 INFO L728 BuchiCegarLoop]: Abstraction has 131474 states and 175241 transitions. [2018-11-18 10:40:06,888 INFO L608 BuchiCegarLoop]: Abstraction has 131474 states and 175241 transitions. [2018-11-18 10:40:06,888 INFO L442 BuchiCegarLoop]: ======== Iteration 25============ [2018-11-18 10:40:06,888 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 131474 states and 175241 transitions. [2018-11-18 10:40:07,137 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 122849 [2018-11-18 10:40:07,137 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:40:07,137 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:40:07,138 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:40:07,138 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:40:07,138 INFO L794 eck$LassoCheckResult]: Stem: 819574#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 819448#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 819151#L1018 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 819152#L470 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 818980#L477 assume 1 == ~m_i~0;~m_st~0 := 0; 818981#L477-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 818988#L482-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 819377#L487-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 819378#L492-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 819187#L497-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 819188#L502-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 819291#L507-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 818994#L686 assume !(0 == ~M_E~0); 818995#L686-2 assume !(0 == ~T1_E~0); 819010#L691-1 assume !(0 == ~T2_E~0); 819393#L696-1 assume !(0 == ~T3_E~0); 819394#L701-1 assume !(0 == ~T4_E~0); 819196#L706-1 assume !(0 == ~T5_E~0); 819197#L711-1 assume !(0 == ~T6_E~0); 819549#L716-1 assume !(0 == ~E_M~0); 819133#L721-1 assume !(0 == ~E_1~0); 819134#L726-1 assume !(0 == ~E_2~0); 818904#L731-1 assume !(0 == ~E_3~0); 818905#L736-1 assume !(0 == ~E_4~0); 818992#L741-1 assume !(0 == ~E_5~0); 818993#L746-1 assume !(0 == ~E_6~0); 819388#L751-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 819092#L336 assume !(1 == ~m_pc~0); 819035#L336-2 is_master_triggered_~__retres1~0 := 0; 819036#L347 is_master_triggered_#res := is_master_triggered_~__retres1~0; 819091#L348 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 819014#L851 assume !(0 != activate_threads_~tmp~1); 819015#L851-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 819018#L355 assume !(1 == ~t1_pc~0); 819331#L355-2 is_transmit1_triggered_~__retres1~1 := 0; 819330#L366 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 818990#L367 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 818991#L859 assume !(0 != activate_threads_~tmp___0~0); 819539#L859-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 819540#L374 assume !(1 == ~t2_pc~0); 819264#L374-2 is_transmit2_triggered_~__retres1~2 := 0; 819263#L385 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 819260#L386 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 819261#L867 assume !(0 != activate_threads_~tmp___1~0); 819700#L867-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 819703#L393 assume !(1 == ~t3_pc~0); 819725#L393-2 is_transmit3_triggered_~__retres1~3 := 0; 819724#L404 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 819687#L405 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 819141#L875 assume !(0 != activate_threads_~tmp___2~0); 819122#L875-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 819123#L412 assume !(1 == ~t4_pc~0); 819167#L412-2 is_transmit4_triggered_~__retres1~4 := 0; 819166#L423 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 819075#L424 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 819076#L883 assume !(0 != activate_threads_~tmp___3~0); 819412#L883-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 819190#L431 assume !(1 == ~t5_pc~0); 819174#L431-2 is_transmit5_triggered_~__retres1~5 := 0; 819175#L442 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 819189#L443 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 819632#L891 assume !(0 != activate_threads_~tmp___4~0); 819625#L891-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 819472#L450 assume !(1 == ~t6_pc~0); 819473#L450-2 is_transmit6_triggered_~__retres1~6 := 0; 819470#L461 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 819471#L462 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 819596#L899 assume !(0 != activate_threads_~tmp___5~0); 819636#L899-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 818900#L764 assume !(1 == ~M_E~0); 818901#L764-2 assume !(1 == ~T1_E~0); 818906#L769-1 assume !(1 == ~T2_E~0); 819020#L774-1 assume !(1 == ~T3_E~0); 819021#L779-1 assume !(1 == ~T4_E~0); 819423#L784-1 assume !(1 == ~T5_E~0); 819424#L789-1 assume !(1 == ~T6_E~0); 819192#L794-1 assume !(1 == ~E_M~0); 819193#L799-1 assume !(1 == ~E_1~0); 819541#L804-1 assume !(1 == ~E_2~0); 819127#L809-1 assume !(1 == ~E_3~0); 819128#L814-1 assume !(1 == ~E_4~0); 818898#L819-1 assume !(1 == ~E_5~0); 818899#L824-1 assume !(1 == ~E_6~0); 819016#L829-1 assume { :end_inline_reset_delta_events } true; 819017#L1055-3 assume true; 878168#L1055-1 assume !false; 878166#L1056 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 878162#L661 [2018-11-18 10:40:07,138 INFO L796 eck$LassoCheckResult]: Loop: 878162#L661 assume true; 878160#L567-1 assume !false; 878158#L568 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 878155#L520 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 878153#L557 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 878151#L558 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 878147#L572 assume 0 != eval_~tmp~0; 878144#L572-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 878141#L580 assume !(0 != eval_~tmp_ndt_1~0); 878139#L577 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 878136#L594 assume !(0 != eval_~tmp_ndt_2~0); 878137#L591 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 878298#L608 assume !(0 != eval_~tmp_ndt_3~0); 878295#L605 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 878292#L622 assume !(0 != eval_~tmp_ndt_4~0); 878291#L619 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 878289#L636 assume !(0 != eval_~tmp_ndt_5~0); 878187#L633 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 878185#L650 assume !(0 != eval_~tmp_ndt_6~0); 878184#L647 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 878164#L664 assume !(0 != eval_~tmp_ndt_7~0); 878162#L661 [2018-11-18 10:40:07,139 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:40:07,139 INFO L82 PathProgramCache]: Analyzing trace with hash 931954781, now seen corresponding path program 7 times [2018-11-18 10:40:07,139 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:40:07,139 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:40:07,140 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:40:07,140 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:40:07,140 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:40:07,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:40:07,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:40:07,164 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:40:07,164 INFO L82 PathProgramCache]: Analyzing trace with hash -1809745846, now seen corresponding path program 1 times [2018-11-18 10:40:07,164 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:40:07,164 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:40:07,165 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:40:07,165 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:40:07,165 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:40:07,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:40:07,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:40:07,169 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:40:07,170 INFO L82 PathProgramCache]: Analyzing trace with hash 24381806, now seen corresponding path program 1 times [2018-11-18 10:40:07,170 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:40:07,170 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:40:07,170 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:40:07,170 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:40:07,170 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:40:07,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:40:07,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:40:07,858 WARN L180 SmtUtils]: Spent 527.00 ms on a formula simplification. DAG size of input: 229 DAG size of output: 152 [2018-11-18 10:40:09,258 WARN L180 SmtUtils]: Spent 1.39 s on a formula simplification that was a NOOP. DAG size: 122 [2018-11-18 10:40:09,287 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 18.11 10:40:09 BoogieIcfgContainer [2018-11-18 10:40:09,287 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2018-11-18 10:40:09,290 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-18 10:40:09,290 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-18 10:40:09,290 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-18 10:40:09,290 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 10:39:54" (3/4) ... [2018-11-18 10:40:09,293 INFO L141 WitnessPrinter]: Generating witness for non-termination counterexample [2018-11-18 10:40:09,343 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_589f8f85-d669-45bb-ac7e-db79ceb26f77/bin-2019/uautomizer/witness.graphml [2018-11-18 10:40:09,343 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-18 10:40:09,344 INFO L168 Benchmark]: Toolchain (without parser) took 16333.80 ms. Allocated memory was 1.0 GB in the beginning and 3.1 GB in the end (delta: 2.1 GB). Free memory was 952.7 MB in the beginning and 2.8 GB in the end (delta: -1.9 GB). Peak memory consumption was 239.6 MB. Max. memory is 11.5 GB. [2018-11-18 10:40:09,345 INFO L168 Benchmark]: CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 980.1 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 10:40:09,345 INFO L168 Benchmark]: CACSL2BoogieTranslator took 235.26 ms. Allocated memory is still 1.0 GB. Free memory was 952.7 MB in the beginning and 931.1 MB in the end (delta: 21.6 MB). Peak memory consumption was 21.6 MB. Max. memory is 11.5 GB. [2018-11-18 10:40:09,345 INFO L168 Benchmark]: Boogie Procedure Inliner took 98.31 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 165.7 MB). Free memory was 931.1 MB in the beginning and 1.2 GB in the end (delta: -226.1 MB). Peak memory consumption was 15.1 MB. Max. memory is 11.5 GB. [2018-11-18 10:40:09,345 INFO L168 Benchmark]: Boogie Preprocessor took 50.95 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 6.5 MB). Peak memory consumption was 6.5 MB. Max. memory is 11.5 GB. [2018-11-18 10:40:09,346 INFO L168 Benchmark]: RCFGBuilder took 1119.03 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.0 GB in the end (delta: 143.1 MB). Peak memory consumption was 143.1 MB. Max. memory is 11.5 GB. [2018-11-18 10:40:09,346 INFO L168 Benchmark]: BuchiAutomizer took 14773.44 ms. Allocated memory was 1.2 GB in the beginning and 3.1 GB in the end (delta: 1.9 GB). Free memory was 1.0 GB in the beginning and 2.8 GB in the end (delta: -1.8 GB). Peak memory consumption was 2.2 GB. Max. memory is 11.5 GB. [2018-11-18 10:40:09,346 INFO L168 Benchmark]: Witness Printer took 53.79 ms. Allocated memory is still 3.1 GB. Free memory was 2.8 GB in the beginning and 2.8 GB in the end (delta: 409.6 kB). Peak memory consumption was 409.6 kB. Max. memory is 11.5 GB. [2018-11-18 10:40:09,348 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 980.1 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 235.26 ms. Allocated memory is still 1.0 GB. Free memory was 952.7 MB in the beginning and 931.1 MB in the end (delta: 21.6 MB). Peak memory consumption was 21.6 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 98.31 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 165.7 MB). Free memory was 931.1 MB in the beginning and 1.2 GB in the end (delta: -226.1 MB). Peak memory consumption was 15.1 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 50.95 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 6.5 MB). Peak memory consumption was 6.5 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1119.03 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.0 GB in the end (delta: 143.1 MB). Peak memory consumption was 143.1 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 14773.44 ms. Allocated memory was 1.2 GB in the beginning and 3.1 GB in the end (delta: 1.9 GB). Free memory was 1.0 GB in the beginning and 2.8 GB in the end (delta: -1.8 GB). Peak memory consumption was 2.2 GB. Max. memory is 11.5 GB. * Witness Printer took 53.79 ms. Allocated memory is still 3.1 GB. Free memory was 2.8 GB in the beginning and 2.8 GB in the end (delta: 409.6 kB). Peak memory consumption was 409.6 kB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 24 terminating modules (24 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.24 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 131474 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 14.7s and 25 iterations. TraceHistogramMax:1. Analysis of lassos took 4.8s. Construction of modules took 0.8s. Büchi inclusion checks took 1.5s. Highest rank in rank-based complementation 0. Minimization of det autom 24. Minimization of nondet autom 0. Automata minimization 3.1s AutomataMinimizationTime, 24 MinimizatonAttempts, 27917 StatesRemovedByMinimization, 13 NontrivialMinimizations. Non-live state removal took 2.9s Buchi closure took 0.1s. Biggest automaton had 131474 states and ocurred in iteration 24. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 24650 SDtfs, 25628 SDslu, 16335 SDs, 0 SdLazy, 514 SolverSat, 325 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.8s Time LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc6 concLT0 SILN1 SILU0 SILI14 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 567]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {__retres1=0, t3_st=0, token=0, tmp=1, t5_i=1, __retres1=0, kernel_st=1, \result=0, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@47c0b789=0, t4_i=1, E_3=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2af5af8b=0, t4_pc=0, E_5=2, T6_E=2, \result=0, E_1=2, tmp_ndt_2=0, \result=0, __retres1=0, \result=0, tmp_ndt_4=0, tmp_ndt_6=0, m_st=0, t6_pc=0, tmp___2=0, tmp___0=0, t3_pc=0, tmp=0, __retres1=0, \result=0, t6_i=1, m_pc=0, tmp___4=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7ea3b7cc=0, \result=0, __retres1=0, t6_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7a4aa7a7=0, E_6=2, \result=0, __retres1=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7a226354=0, T2_E=2, tmp___0=0, t1_pc=0, __retres1=1, t5_st=0, E_2=2, E_4=2, T1_E=2, tmp_ndt_1=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, T5_E=2, t2_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@203bd324=0, T4_E=2, t3_i=1, t4_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@454b0553=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@706d12ba=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@54837911=0, t1_st=0, tmp_ndt_5=0, t5_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2adf3d9d=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@37a3d7a7=0, local=0, t2_pc=0, tmp_ndt_7=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2f43f837=0, tmp___3=0, E_M=2, tmp___1=0, T3_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4a1650b5=0, t1_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@20fb5caf=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@e3d023c=0, \result=1, tmp___5=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5bc103f9=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3e70f505=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 567]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int t4_pc = 0; [L19] int t5_pc = 0; [L20] int t6_pc = 0; [L21] int m_st ; [L22] int t1_st ; [L23] int t2_st ; [L24] int t3_st ; [L25] int t4_st ; [L26] int t5_st ; [L27] int t6_st ; [L28] int m_i ; [L29] int t1_i ; [L30] int t2_i ; [L31] int t3_i ; [L32] int t4_i ; [L33] int t5_i ; [L34] int t6_i ; [L35] int M_E = 2; [L36] int T1_E = 2; [L37] int T2_E = 2; [L38] int T3_E = 2; [L39] int T4_E = 2; [L40] int T5_E = 2; [L41] int T6_E = 2; [L42] int E_M = 2; [L43] int E_1 = 2; [L44] int E_2 = 2; [L45] int E_3 = 2; [L46] int E_4 = 2; [L47] int E_5 = 2; [L48] int E_6 = 2; [L57] int token ; [L59] int local ; [L1100] int __retres1 ; [L1104] CALL init_model() [L1010] m_i = 1 [L1011] t1_i = 1 [L1012] t2_i = 1 [L1013] t3_i = 1 [L1014] t4_i = 1 [L1015] t5_i = 1 [L1016] RET t6_i = 1 [L1104] init_model() [L1105] CALL start_simulation() [L1041] int kernel_st ; [L1042] int tmp ; [L1043] int tmp___0 ; [L1047] kernel_st = 0 [L1048] FCALL update_channels() [L1049] CALL init_threads() [L477] COND TRUE m_i == 1 [L478] m_st = 0 [L482] COND TRUE t1_i == 1 [L483] t1_st = 0 [L487] COND TRUE t2_i == 1 [L488] t2_st = 0 [L492] COND TRUE t3_i == 1 [L493] t3_st = 0 [L497] COND TRUE t4_i == 1 [L498] t4_st = 0 [L502] COND TRUE t5_i == 1 [L503] t5_st = 0 [L507] COND TRUE t6_i == 1 [L508] RET t6_st = 0 [L1049] init_threads() [L1050] CALL fire_delta_events() [L686] COND FALSE !(M_E == 0) [L691] COND FALSE !(T1_E == 0) [L696] COND FALSE !(T2_E == 0) [L701] COND FALSE !(T3_E == 0) [L706] COND FALSE !(T4_E == 0) [L711] COND FALSE !(T5_E == 0) [L716] COND FALSE !(T6_E == 0) [L721] COND FALSE !(E_M == 0) [L726] COND FALSE !(E_1 == 0) [L731] COND FALSE !(E_2 == 0) [L736] COND FALSE !(E_3 == 0) [L741] COND FALSE !(E_4 == 0) [L746] COND FALSE !(E_5 == 0) [L751] COND FALSE, RET !(E_6 == 0) [L1050] fire_delta_events() [L1051] CALL activate_threads() [L839] int tmp ; [L840] int tmp___0 ; [L841] int tmp___1 ; [L842] int tmp___2 ; [L843] int tmp___3 ; [L844] int tmp___4 ; [L845] int tmp___5 ; [L849] CALL, EXPR is_master_triggered() [L333] int __retres1 ; [L336] COND FALSE !(m_pc == 1) [L346] __retres1 = 0 [L348] RET return (__retres1); [L849] EXPR is_master_triggered() [L849] tmp = is_master_triggered() [L851] COND FALSE !(\read(tmp)) [L857] CALL, EXPR is_transmit1_triggered() [L352] int __retres1 ; [L355] COND FALSE !(t1_pc == 1) [L365] __retres1 = 0 [L367] RET return (__retres1); [L857] EXPR is_transmit1_triggered() [L857] tmp___0 = is_transmit1_triggered() [L859] COND FALSE !(\read(tmp___0)) [L865] CALL, EXPR is_transmit2_triggered() [L371] int __retres1 ; [L374] COND FALSE !(t2_pc == 1) [L384] __retres1 = 0 [L386] RET return (__retres1); [L865] EXPR is_transmit2_triggered() [L865] tmp___1 = is_transmit2_triggered() [L867] COND FALSE !(\read(tmp___1)) [L873] CALL, EXPR is_transmit3_triggered() [L390] int __retres1 ; [L393] COND FALSE !(t3_pc == 1) [L403] __retres1 = 0 [L405] RET return (__retres1); [L873] EXPR is_transmit3_triggered() [L873] tmp___2 = is_transmit3_triggered() [L875] COND FALSE !(\read(tmp___2)) [L881] CALL, EXPR is_transmit4_triggered() [L409] int __retres1 ; [L412] COND FALSE !(t4_pc == 1) [L422] __retres1 = 0 [L424] RET return (__retres1); [L881] EXPR is_transmit4_triggered() [L881] tmp___3 = is_transmit4_triggered() [L883] COND FALSE !(\read(tmp___3)) [L889] CALL, EXPR is_transmit5_triggered() [L428] int __retres1 ; [L431] COND FALSE !(t5_pc == 1) [L441] __retres1 = 0 [L443] RET return (__retres1); [L889] EXPR is_transmit5_triggered() [L889] tmp___4 = is_transmit5_triggered() [L891] COND FALSE !(\read(tmp___4)) [L897] CALL, EXPR is_transmit6_triggered() [L447] int __retres1 ; [L450] COND FALSE !(t6_pc == 1) [L460] __retres1 = 0 [L462] RET return (__retres1); [L897] EXPR is_transmit6_triggered() [L897] tmp___5 = is_transmit6_triggered() [L899] COND FALSE, RET !(\read(tmp___5)) [L1051] activate_threads() [L1052] CALL reset_delta_events() [L764] COND FALSE !(M_E == 1) [L769] COND FALSE !(T1_E == 1) [L774] COND FALSE !(T2_E == 1) [L779] COND FALSE !(T3_E == 1) [L784] COND FALSE !(T4_E == 1) [L789] COND FALSE !(T5_E == 1) [L794] COND FALSE !(T6_E == 1) [L799] COND FALSE !(E_M == 1) [L804] COND FALSE !(E_1 == 1) [L809] COND FALSE !(E_2 == 1) [L814] COND FALSE !(E_3 == 1) [L819] COND FALSE !(E_4 == 1) [L824] COND FALSE !(E_5 == 1) [L829] COND FALSE, RET !(E_6 == 1) [L1052] reset_delta_events() [L1055] COND TRUE 1 [L1058] kernel_st = 1 [L1059] CALL eval() [L563] int tmp ; Loop: [L567] COND TRUE 1 [L570] CALL, EXPR exists_runnable_thread() [L517] int __retres1 ; [L520] COND TRUE m_st == 0 [L521] __retres1 = 1 [L558] RET return (__retres1); [L570] EXPR exists_runnable_thread() [L570] tmp = exists_runnable_thread() [L572] COND TRUE \read(tmp) [L577] COND TRUE m_st == 0 [L578] int tmp_ndt_1; [L579] tmp_ndt_1 = __VERIFIER_nondet_int() [L580] COND FALSE !(\read(tmp_ndt_1)) [L591] COND TRUE t1_st == 0 [L592] int tmp_ndt_2; [L593] tmp_ndt_2 = __VERIFIER_nondet_int() [L594] COND FALSE !(\read(tmp_ndt_2)) [L605] COND TRUE t2_st == 0 [L606] int tmp_ndt_3; [L607] tmp_ndt_3 = __VERIFIER_nondet_int() [L608] COND FALSE !(\read(tmp_ndt_3)) [L619] COND TRUE t3_st == 0 [L620] int tmp_ndt_4; [L621] tmp_ndt_4 = __VERIFIER_nondet_int() [L622] COND FALSE !(\read(tmp_ndt_4)) [L633] COND TRUE t4_st == 0 [L634] int tmp_ndt_5; [L635] tmp_ndt_5 = __VERIFIER_nondet_int() [L636] COND FALSE !(\read(tmp_ndt_5)) [L647] COND TRUE t5_st == 0 [L648] int tmp_ndt_6; [L649] tmp_ndt_6 = __VERIFIER_nondet_int() [L650] COND FALSE !(\read(tmp_ndt_6)) [L661] COND TRUE t6_st == 0 [L662] int tmp_ndt_7; [L663] tmp_ndt_7 = __VERIFIER_nondet_int() [L664] COND FALSE !(\read(tmp_ndt_7)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...