./Ultimate.py --spec ../../sv-benchmarks/c/Termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.07_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 5842f4b8 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_b625e2b8-c366-4210-a7ec-394d99235a33/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_b625e2b8-c366-4210-a7ec-394d99235a33/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_b625e2b8-c366-4210-a7ec-394d99235a33/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_b625e2b8-c366-4210-a7ec-394d99235a33/bin-2019/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.07_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_b625e2b8-c366-4210-a7ec-394d99235a33/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_b625e2b8-c366-4210-a7ec-394d99235a33/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 7fd2d1a9f96a95d1ad5fce6dcab48c9b2b66f4e4 ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.23-5842f4b [2018-11-18 09:04:47,875 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-18 09:04:47,876 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-18 09:04:47,884 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-18 09:04:47,884 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-18 09:04:47,884 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-18 09:04:47,885 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-18 09:04:47,886 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-18 09:04:47,887 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-18 09:04:47,888 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-18 09:04:47,888 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-18 09:04:47,888 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-18 09:04:47,889 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-18 09:04:47,890 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-18 09:04:47,890 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-18 09:04:47,891 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-18 09:04:47,892 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-18 09:04:47,893 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-18 09:04:47,894 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-18 09:04:47,895 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-18 09:04:47,896 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-18 09:04:47,896 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-18 09:04:47,898 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-18 09:04:47,898 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-18 09:04:47,898 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-18 09:04:47,899 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-18 09:04:47,900 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-18 09:04:47,900 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-18 09:04:47,901 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-18 09:04:47,902 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-18 09:04:47,902 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-18 09:04:47,902 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-18 09:04:47,902 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-18 09:04:47,903 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-18 09:04:47,903 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-18 09:04:47,904 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-18 09:04:47,904 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_b625e2b8-c366-4210-a7ec-394d99235a33/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2018-11-18 09:04:47,915 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-18 09:04:47,915 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-18 09:04:47,916 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-18 09:04:47,916 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-18 09:04:47,916 INFO L133 SettingsManager]: * Use SBE=true [2018-11-18 09:04:47,916 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2018-11-18 09:04:47,916 INFO L133 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2018-11-18 09:04:47,916 INFO L133 SettingsManager]: * Use old map elimination=false [2018-11-18 09:04:47,916 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false [2018-11-18 09:04:47,917 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true [2018-11-18 09:04:47,917 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2018-11-18 09:04:47,917 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-18 09:04:47,917 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-18 09:04:47,917 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-18 09:04:47,917 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-18 09:04:47,917 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-18 09:04:47,917 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-18 09:04:47,917 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2018-11-18 09:04:47,918 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2018-11-18 09:04:47,918 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2018-11-18 09:04:47,918 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-18 09:04:47,918 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-18 09:04:47,918 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false [2018-11-18 09:04:47,918 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-18 09:04:47,918 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2018-11-18 09:04:47,918 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-18 09:04:47,918 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-18 09:04:47,918 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2018-11-18 09:04:47,919 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-18 09:04:47,919 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-18 09:04:47,919 INFO L133 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2018-11-18 09:04:47,919 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-11-18 09:04:47,919 INFO L133 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_b625e2b8-c366-4210-a7ec-394d99235a33/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 7fd2d1a9f96a95d1ad5fce6dcab48c9b2b66f4e4 [2018-11-18 09:04:47,941 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-18 09:04:47,949 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-18 09:04:47,951 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-18 09:04:47,952 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-18 09:04:47,952 INFO L276 PluginConnector]: CDTParser initialized [2018-11-18 09:04:47,952 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_b625e2b8-c366-4210-a7ec-394d99235a33/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/token_ring.07_false-unreach-call_false-termination.cil.c [2018-11-18 09:04:47,988 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_b625e2b8-c366-4210-a7ec-394d99235a33/bin-2019/uautomizer/data/e2292af76/50ca879a54df4aef922728a5f90c9682/FLAGf68ab795f [2018-11-18 09:04:48,318 INFO L307 CDTParser]: Found 1 translation units. [2018-11-18 09:04:48,318 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_b625e2b8-c366-4210-a7ec-394d99235a33/sv-benchmarks/c/systemc/token_ring.07_false-unreach-call_false-termination.cil.c [2018-11-18 09:04:48,327 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_b625e2b8-c366-4210-a7ec-394d99235a33/bin-2019/uautomizer/data/e2292af76/50ca879a54df4aef922728a5f90c9682/FLAGf68ab795f [2018-11-18 09:04:48,337 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_b625e2b8-c366-4210-a7ec-394d99235a33/bin-2019/uautomizer/data/e2292af76/50ca879a54df4aef922728a5f90c9682 [2018-11-18 09:04:48,339 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-18 09:04:48,340 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-18 09:04:48,341 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-18 09:04:48,341 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-18 09:04:48,343 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-18 09:04:48,343 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 09:04:48" (1/1) ... [2018-11-18 09:04:48,345 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@58ae4871 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:04:48, skipping insertion in model container [2018-11-18 09:04:48,345 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 09:04:48" (1/1) ... [2018-11-18 09:04:48,351 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-18 09:04:48,381 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-18 09:04:48,549 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 09:04:48,552 INFO L191 MainTranslator]: Completed pre-run [2018-11-18 09:04:48,588 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 09:04:48,605 INFO L195 MainTranslator]: Completed translation [2018-11-18 09:04:48,605 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:04:48 WrapperNode [2018-11-18 09:04:48,605 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-18 09:04:48,606 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-18 09:04:48,606 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-18 09:04:48,606 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-18 09:04:48,652 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:04:48" (1/1) ... [2018-11-18 09:04:48,660 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:04:48" (1/1) ... [2018-11-18 09:04:48,703 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-18 09:04:48,703 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-18 09:04:48,703 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-18 09:04:48,703 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-18 09:04:48,712 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:04:48" (1/1) ... [2018-11-18 09:04:48,712 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:04:48" (1/1) ... [2018-11-18 09:04:48,716 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:04:48" (1/1) ... [2018-11-18 09:04:48,716 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:04:48" (1/1) ... [2018-11-18 09:04:48,731 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:04:48" (1/1) ... [2018-11-18 09:04:48,750 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:04:48" (1/1) ... [2018-11-18 09:04:48,753 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:04:48" (1/1) ... [2018-11-18 09:04:48,760 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-18 09:04:48,760 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-18 09:04:48,760 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-18 09:04:48,760 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-18 09:04:48,761 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:04:48" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_b625e2b8-c366-4210-a7ec-394d99235a33/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 09:04:48,818 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-18 09:04:48,819 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-18 09:04:49,881 INFO L278 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-18 09:04:49,881 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 09:04:49 BoogieIcfgContainer [2018-11-18 09:04:49,881 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-18 09:04:49,882 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2018-11-18 09:04:49,882 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2018-11-18 09:04:49,884 INFO L276 PluginConnector]: BuchiAutomizer initialized [2018-11-18 09:04:49,885 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 09:04:49,885 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 18.11 09:04:48" (1/3) ... [2018-11-18 09:04:49,886 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@12d51c1e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 09:04:49, skipping insertion in model container [2018-11-18 09:04:49,886 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 09:04:49,886 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:04:48" (2/3) ... [2018-11-18 09:04:49,886 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@12d51c1e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 09:04:49, skipping insertion in model container [2018-11-18 09:04:49,886 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 09:04:49,886 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 09:04:49" (3/3) ... [2018-11-18 09:04:49,888 INFO L375 chiAutomizerObserver]: Analyzing ICFG token_ring.07_false-unreach-call_false-termination.cil.c [2018-11-18 09:04:49,923 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-18 09:04:49,923 INFO L374 BuchiCegarLoop]: Interprodecural is true [2018-11-18 09:04:49,923 INFO L375 BuchiCegarLoop]: Hoare is false [2018-11-18 09:04:49,923 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2018-11-18 09:04:49,924 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-18 09:04:49,924 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-18 09:04:49,924 INFO L379 BuchiCegarLoop]: Difference is false [2018-11-18 09:04:49,924 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-18 09:04:49,924 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2018-11-18 09:04:49,949 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 853 states. [2018-11-18 09:04:49,992 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 746 [2018-11-18 09:04:49,992 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:04:49,992 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:04:50,002 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:50,002 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:50,002 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ [2018-11-18 09:04:50,002 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 853 states. [2018-11-18 09:04:50,010 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 746 [2018-11-18 09:04:50,011 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:04:50,011 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:04:50,013 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:50,014 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:50,020 INFO L794 eck$LassoCheckResult]: Stem: 326#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 242#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 288#L1143true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 220#L531true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 689#L538true assume !(1 == ~m_i~0);~m_st~0 := 2; 684#L538-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 485#L543-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 399#L548-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 221#L553-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 851#L558-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 576#L563-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 375#L568-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 205#L573-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 307#L771true assume !(0 == ~M_E~0); 311#L771-2true assume !(0 == ~T1_E~0); 92#L776-1true assume !(0 == ~T2_E~0); 766#L781-1true assume !(0 == ~T3_E~0); 452#L786-1true assume !(0 == ~T4_E~0); 276#L791-1true assume !(0 == ~T5_E~0); 62#L796-1true assume 0 == ~T6_E~0;~T6_E~0 := 1; 833#L801-1true assume !(0 == ~T7_E~0); 653#L806-1true assume !(0 == ~E_M~0); 353#L811-1true assume !(0 == ~E_1~0); 165#L816-1true assume !(0 == ~E_2~0); 802#L821-1true assume !(0 == ~E_3~0); 717#L826-1true assume !(0 == ~E_4~0); 534#L831-1true assume !(0 == ~E_5~0); 343#L836-1true assume 0 == ~E_6~0;~E_6~0 := 1; 17#L841-1true assume !(0 == ~E_7~0); 691#L846-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 55#L378true assume !(1 == ~m_pc~0); 42#L378-2true is_master_triggered_~__retres1~0 := 0; 493#L389true is_master_triggered_#res := is_master_triggered_~__retres1~0; 559#L390true activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 771#L957true assume !(0 != activate_threads_~tmp~1); 772#L957-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 189#L397true assume 1 == ~t1_pc~0; 142#L398true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 609#L408true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 565#L409true activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 355#L965true assume !(0 != activate_threads_~tmp___0~0); 348#L965-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 403#L416true assume !(1 == ~t2_pc~0); 293#L416-2true is_transmit2_triggered_~__retres1~2 := 0; 819#L427true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 685#L428true activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 27#L973true assume !(0 != activate_threads_~tmp___1~0); 30#L973-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 520#L435true assume 1 == ~t3_pc~0; 362#L436true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 73#L446true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 801#L447true activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 593#L981true assume !(0 != activate_threads_~tmp___2~0); 585#L981-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 647#L454true assume !(1 == ~t4_pc~0); 640#L454-2true is_transmit4_triggered_~__retres1~4 := 0; 223#L465true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 52#L466true activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 280#L989true assume !(0 != activate_threads_~tmp___3~0); 283#L989-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 752#L473true assume 1 == ~t5_pc~0; 627#L474true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 332#L484true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 207#L485true activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 814#L997true assume !(0 != activate_threads_~tmp___4~0); 807#L997-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 852#L492true assume 1 == ~t6_pc~0; 816#L493true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 435#L503true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 400#L504true activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 630#L1005true assume !(0 != activate_threads_~tmp___5~0); 632#L1005-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 12#L511true assume !(1 == ~t7_pc~0); 132#L511-2true is_transmit7_triggered_~__retres1~7 := 0; 449#L522true is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 531#L523true activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 324#L1013true assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 317#L1013-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 319#L859true assume !(1 == ~M_E~0); 306#L859-2true assume !(1 == ~T1_E~0); 105#L864-1true assume !(1 == ~T2_E~0); 762#L869-1true assume !(1 == ~T3_E~0); 450#L874-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 270#L879-1true assume !(1 == ~T5_E~0); 60#L884-1true assume !(1 == ~T6_E~0); 829#L889-1true assume !(1 == ~T7_E~0); 651#L894-1true assume !(1 == ~E_M~0); 349#L899-1true assume !(1 == ~E_1~0); 161#L904-1true assume !(1 == ~E_2~0); 809#L909-1true assume !(1 == ~E_3~0); 726#L914-1true assume 1 == ~E_4~0;~E_4~0 := 2; 538#L919-1true assume !(1 == ~E_5~0); 347#L924-1true assume !(1 == ~E_6~0); 32#L929-1true assume !(1 == ~E_7~0); 694#L934-1true assume { :end_inline_reset_delta_events } true; 654#L1180-3true [2018-11-18 09:04:50,022 INFO L796 eck$LassoCheckResult]: Loop: 654#L1180-3true assume true; 665#L1180-1true assume !false; 636#L1181true start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 408#L746true assume !true; 579#L761true assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 222#L531-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 314#L771-3true assume 0 == ~M_E~0;~M_E~0 := 1; 203#L771-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 95#L776-3true assume !(0 == ~T2_E~0); 769#L781-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 453#L786-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 261#L791-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 57#L796-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 824#L801-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 649#L806-3true assume 0 == ~E_M~0;~E_M~0 := 1; 440#L811-3true assume 0 == ~E_1~0;~E_1~0 := 1; 156#L816-3true assume !(0 == ~E_2~0); 804#L821-3true assume 0 == ~E_3~0;~E_3~0 := 1; 719#L826-3true assume 0 == ~E_4~0;~E_4~0 := 1; 535#L831-3true assume 0 == ~E_5~0;~E_5~0 := 1; 344#L836-3true assume 0 == ~E_6~0;~E_6~0 := 1; 22#L841-3true assume 0 == ~E_7~0;~E_7~0 := 1; 692#L846-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13#L378-27true assume !(1 == ~m_pc~0); 133#L378-29true is_master_triggered_~__retres1~0 := 0; 462#L389-9true is_master_triggered_#res := is_master_triggered_~__retres1~0; 542#L390-9true activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 736#L957-27true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 739#L957-29true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 151#L397-27true assume !(1 == ~t1_pc~0); 152#L397-29true is_transmit1_triggered_~__retres1~1 := 0; 606#L408-9true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 667#L409-9true activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 418#L965-27true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 410#L965-29true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 268#L416-27true assume 1 == ~t2_pc~0; 236#L417-9true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 700#L427-9true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 671#L428-9true activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 112#L973-27true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 116#L973-29true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 373#L435-27true assume 1 == ~t3_pc~0; 360#L436-9true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 71#L446-9true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 785#L447-9true activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 668#L981-27true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 656#L981-29true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 501#L454-27true assume !(1 == ~t4_pc~0); 484#L454-29true is_transmit4_triggered_~__retres1~4 := 0; 211#L465-9true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 35#L466-9true activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 237#L989-27true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 239#L989-29true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 620#L473-27true assume !(1 == ~t5_pc~0); 624#L473-29true is_transmit5_triggered_~__retres1~5 := 0; 330#L484-9true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 179#L485-9true activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 788#L997-27true assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 775#L997-29true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 826#L492-27true assume 1 == ~t6_pc~0; 696#L493-9true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 414#L503-9true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 305#L504-9true activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 461#L1005-27true assume !(0 != activate_threads_~tmp___5~0); 465#L1005-29true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 84#L511-27true assume 1 == ~t7_pc~0; 68#L512-9true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 552#L522-9true is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 514#L523-9true activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 184#L1013-27true assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 167#L1013-29true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 309#L859-3true assume !(1 == ~M_E~0); 313#L859-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 91#L864-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 764#L869-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 451#L874-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 275#L879-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 61#L884-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 832#L889-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 652#L894-3true assume !(1 == ~E_M~0); 352#L899-3true assume 1 == ~E_1~0;~E_1~0 := 2; 164#L904-3true assume 1 == ~E_2~0;~E_2~0 := 2; 811#L909-3true assume 1 == ~E_3~0;~E_3~0 := 2; 728#L914-3true assume 1 == ~E_4~0;~E_4~0 := 2; 533#L919-3true assume 1 == ~E_5~0;~E_5~0 := 2; 342#L924-3true assume 1 == ~E_6~0;~E_6~0 := 2; 16#L929-3true assume 1 == ~E_7~0;~E_7~0 := 2; 690#L934-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 645#L586-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 621#L628-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 573#L629-1true start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 683#L1199true assume !(0 == start_simulation_~tmp~3); 672#L1199-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 646#L586-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 623#L628-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 575#L629-2true stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 701#L1154true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 540#L1161true stop_simulation_#res := stop_simulation_~__retres2~0; 518#L1162true start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 180#L1212true assume !(0 != start_simulation_~tmp___0~1); 654#L1180-3true [2018-11-18 09:04:50,027 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:50,027 INFO L82 PathProgramCache]: Analyzing trace with hash 1617538625, now seen corresponding path program 1 times [2018-11-18 09:04:50,029 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:50,029 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:50,059 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:50,059 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:50,059 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:50,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:50,146 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:50,147 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:50,148 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:04:50,151 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 09:04:50,151 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:50,152 INFO L82 PathProgramCache]: Analyzing trace with hash -1409086590, now seen corresponding path program 1 times [2018-11-18 09:04:50,152 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:50,152 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:50,153 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:50,153 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:50,153 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:50,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:50,177 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:50,177 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:50,178 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 09:04:50,180 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:04:50,189 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:04:50,190 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:04:50,191 INFO L87 Difference]: Start difference. First operand 853 states. Second operand 3 states. [2018-11-18 09:04:50,233 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:04:50,233 INFO L93 Difference]: Finished difference Result 851 states and 1265 transitions. [2018-11-18 09:04:50,234 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:04:50,235 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 851 states and 1265 transitions. [2018-11-18 09:04:50,240 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 742 [2018-11-18 09:04:50,248 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 851 states to 845 states and 1259 transitions. [2018-11-18 09:04:50,249 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 845 [2018-11-18 09:04:50,250 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 845 [2018-11-18 09:04:50,250 INFO L73 IsDeterministic]: Start isDeterministic. Operand 845 states and 1259 transitions. [2018-11-18 09:04:50,255 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:04:50,255 INFO L705 BuchiCegarLoop]: Abstraction has 845 states and 1259 transitions. [2018-11-18 09:04:50,268 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 845 states and 1259 transitions. [2018-11-18 09:04:50,299 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 845 to 845. [2018-11-18 09:04:50,300 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 845 states. [2018-11-18 09:04:50,302 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 845 states to 845 states and 1259 transitions. [2018-11-18 09:04:50,303 INFO L728 BuchiCegarLoop]: Abstraction has 845 states and 1259 transitions. [2018-11-18 09:04:50,303 INFO L608 BuchiCegarLoop]: Abstraction has 845 states and 1259 transitions. [2018-11-18 09:04:50,303 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ [2018-11-18 09:04:50,303 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 845 states and 1259 transitions. [2018-11-18 09:04:50,306 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 742 [2018-11-18 09:04:50,306 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:04:50,306 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:04:50,308 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:50,308 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:50,309 INFO L794 eck$LassoCheckResult]: Stem: 2190#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 2092#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2093#L1143 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 2063#L531 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2064#L538 assume 1 == ~m_i~0;~m_st~0 := 0; 2489#L538-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2344#L543-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2256#L548-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2065#L553-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2066#L558-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2409#L563-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2251#L568-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2044#L573-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2045#L771 assume !(0 == ~M_E~0); 2170#L771-2 assume !(0 == ~T1_E~0); 1895#L776-1 assume !(0 == ~T2_E~0); 1896#L781-1 assume !(0 == ~T3_E~0); 2307#L786-1 assume !(0 == ~T4_E~0); 2138#L791-1 assume !(0 == ~T5_E~0); 1833#L796-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1834#L801-1 assume !(0 == ~T7_E~0); 2471#L806-1 assume !(0 == ~E_M~0); 2218#L811-1 assume !(0 == ~E_1~0); 1989#L816-1 assume !(0 == ~E_2~0); 1990#L821-1 assume !(0 == ~E_3~0); 2508#L826-1 assume !(0 == ~E_4~0); 2376#L831-1 assume !(0 == ~E_5~0); 2206#L836-1 assume 0 == ~E_6~0;~E_6~0 := 1; 1743#L841-1 assume !(0 == ~E_7~0); 1744#L846-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1817#L378 assume !(1 == ~m_pc~0); 1791#L378-2 is_master_triggered_~__retres1~0 := 0; 1792#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2351#L390 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2390#L957 assume !(0 != activate_threads_~tmp~1); 2525#L957-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2023#L397 assume 1 == ~t1_pc~0; 1939#L398 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1940#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2394#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2221#L965 assume !(0 != activate_threads_~tmp___0~0); 2212#L965-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2213#L416 assume !(1 == ~t2_pc~0); 2117#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 2118#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2490#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1763#L973 assume !(0 != activate_threads_~tmp___1~0); 1764#L973-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1769#L435 assume 1 == ~t3_pc~0; 2235#L436 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1859#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1860#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2428#L981 assume !(0 != activate_threads_~tmp___2~0); 2418#L981-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2419#L454 assume !(1 == ~t4_pc~0); 2348#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 2069#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1811#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1812#L989 assume !(0 != activate_threads_~tmp___3~0); 2142#L989-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2144#L473 assume 1 == ~t5_pc~0; 2460#L474 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 2195#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2047#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2048#L997 assume !(0 != activate_threads_~tmp___4~0); 2546#L997-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2547#L492 assume 1 == ~t6_pc~0; 2550#L493 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 2292#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2257#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2258#L1005 assume !(0 != activate_threads_~tmp___5~0); 2463#L1005-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1732#L511 assume !(1 == ~t7_pc~0); 1733#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 1889#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2304#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2188#L1013 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 2180#L1013-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2181#L859 assume !(1 == ~M_E~0); 2169#L859-2 assume !(1 == ~T1_E~0); 1910#L864-1 assume !(1 == ~T2_E~0); 1911#L869-1 assume !(1 == ~T3_E~0); 2305#L874-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2132#L879-1 assume !(1 == ~T5_E~0); 1829#L884-1 assume !(1 == ~T6_E~0); 1830#L889-1 assume !(1 == ~T7_E~0); 2469#L894-1 assume !(1 == ~E_M~0); 2214#L899-1 assume !(1 == ~E_1~0); 1982#L904-1 assume !(1 == ~E_2~0); 1983#L909-1 assume !(1 == ~E_3~0); 2512#L914-1 assume 1 == ~E_4~0;~E_4~0 := 2; 2378#L919-1 assume !(1 == ~E_5~0); 2211#L924-1 assume !(1 == ~E_6~0); 1772#L929-1 assume !(1 == ~E_7~0); 1773#L934-1 assume { :end_inline_reset_delta_events } true; 2010#L1180-3 [2018-11-18 09:04:50,310 INFO L796 eck$LassoCheckResult]: Loop: 2010#L1180-3 assume true; 2472#L1180-1 assume !false; 2464#L1181 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 1900#L746 assume true; 2201#L638-1 assume !false; 2177#L639 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 2178#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 1825#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 2416#L629 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 1718#L643 assume !(0 != eval_~tmp~0); 1720#L761 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 2067#L531-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 2068#L771-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2042#L771-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1901#L776-3 assume !(0 == ~T2_E~0); 1902#L781-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2308#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2125#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1821#L796-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1822#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2468#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2296#L811-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1972#L816-3 assume !(0 == ~E_2~0); 1973#L821-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2509#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2377#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2207#L836-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1753#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1754#L846-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1735#L378-27 assume 1 == ~m_pc~0; 1736#L379-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1915#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2319#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2381#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2517#L957-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1961#L397-27 assume !(1 == ~t1_pc~0); 1962#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 1964#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2446#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2276#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2268#L965-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2130#L416-27 assume 1 == ~t2_pc~0; 2082#L417-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2083#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2480#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1916#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1917#L973-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1923#L435-27 assume 1 == ~t3_pc~0; 2230#L436-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1855#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1856#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2478#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2473#L981-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2357#L454-27 assume 1 == ~t4_pc~0; 2312#L455-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2054#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1778#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1779#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2085#L989-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2089#L473-27 assume 1 == ~t5_pc~0; 2438#L474-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 2193#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2007#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2008#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 2527#L997-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2528#L492-27 assume 1 == ~t6_pc~0; 2493#L493-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 2272#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2167#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2168#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 2318#L1005-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1887#L511-27 assume 1 == ~t7_pc~0; 1847#L512-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 1848#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2364#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2014#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 1992#L1013-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1993#L859-3 assume !(1 == ~M_E~0); 2173#L859-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1893#L864-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1894#L869-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2306#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2137#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1831#L884-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1832#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2470#L894-3 assume !(1 == ~E_M~0); 2217#L899-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1987#L904-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1988#L909-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2513#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2375#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2205#L924-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1741#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1742#L934-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 2465#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 1828#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 2403#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 2404#L1199 assume !(0 == start_simulation_~tmp~3); 2149#L1199-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 2466#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 1807#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 2407#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 2408#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2379#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 2366#L1162 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 2009#L1212 assume !(0 != start_simulation_~tmp___0~1); 2010#L1180-3 [2018-11-18 09:04:50,310 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:50,310 INFO L82 PathProgramCache]: Analyzing trace with hash -736846657, now seen corresponding path program 1 times [2018-11-18 09:04:50,310 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:50,310 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:50,311 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:50,311 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:50,311 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:50,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:50,357 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:50,357 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:50,357 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:04:50,358 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 09:04:50,358 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:50,358 INFO L82 PathProgramCache]: Analyzing trace with hash 744138663, now seen corresponding path program 1 times [2018-11-18 09:04:50,358 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:50,358 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:50,359 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:50,359 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:50,359 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:50,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:50,441 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:50,441 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:50,441 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:04:50,441 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:04:50,442 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:04:50,442 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:04:50,442 INFO L87 Difference]: Start difference. First operand 845 states and 1259 transitions. cyclomatic complexity: 415 Second operand 3 states. [2018-11-18 09:04:50,453 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:04:50,454 INFO L93 Difference]: Finished difference Result 845 states and 1258 transitions. [2018-11-18 09:04:50,454 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:04:50,455 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 845 states and 1258 transitions. [2018-11-18 09:04:50,459 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 742 [2018-11-18 09:04:50,462 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 845 states to 845 states and 1258 transitions. [2018-11-18 09:04:50,462 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 845 [2018-11-18 09:04:50,463 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 845 [2018-11-18 09:04:50,463 INFO L73 IsDeterministic]: Start isDeterministic. Operand 845 states and 1258 transitions. [2018-11-18 09:04:50,464 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:04:50,465 INFO L705 BuchiCegarLoop]: Abstraction has 845 states and 1258 transitions. [2018-11-18 09:04:50,466 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 845 states and 1258 transitions. [2018-11-18 09:04:50,478 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 845 to 845. [2018-11-18 09:04:50,478 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 845 states. [2018-11-18 09:04:50,480 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 845 states to 845 states and 1258 transitions. [2018-11-18 09:04:50,480 INFO L728 BuchiCegarLoop]: Abstraction has 845 states and 1258 transitions. [2018-11-18 09:04:50,480 INFO L608 BuchiCegarLoop]: Abstraction has 845 states and 1258 transitions. [2018-11-18 09:04:50,480 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ [2018-11-18 09:04:50,480 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 845 states and 1258 transitions. [2018-11-18 09:04:50,483 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 742 [2018-11-18 09:04:50,483 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:04:50,483 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:04:50,485 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:50,485 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:50,485 INFO L794 eck$LassoCheckResult]: Stem: 3887#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 3789#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 3790#L1143 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 3760#L531 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3761#L538 assume 1 == ~m_i~0;~m_st~0 := 0; 4186#L538-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4041#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3953#L548-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3762#L553-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3763#L558-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4106#L563-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3948#L568-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3741#L573-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3742#L771 assume !(0 == ~M_E~0); 3867#L771-2 assume !(0 == ~T1_E~0); 3592#L776-1 assume !(0 == ~T2_E~0); 3593#L781-1 assume !(0 == ~T3_E~0); 4004#L786-1 assume !(0 == ~T4_E~0); 3835#L791-1 assume !(0 == ~T5_E~0); 3530#L796-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3531#L801-1 assume !(0 == ~T7_E~0); 4168#L806-1 assume !(0 == ~E_M~0); 3915#L811-1 assume !(0 == ~E_1~0); 3686#L816-1 assume !(0 == ~E_2~0); 3687#L821-1 assume !(0 == ~E_3~0); 4205#L826-1 assume !(0 == ~E_4~0); 4073#L831-1 assume !(0 == ~E_5~0); 3903#L836-1 assume 0 == ~E_6~0;~E_6~0 := 1; 3440#L841-1 assume !(0 == ~E_7~0); 3441#L846-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3514#L378 assume !(1 == ~m_pc~0); 3488#L378-2 is_master_triggered_~__retres1~0 := 0; 3489#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4048#L390 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4087#L957 assume !(0 != activate_threads_~tmp~1); 4222#L957-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3720#L397 assume 1 == ~t1_pc~0; 3636#L398 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3637#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4091#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3918#L965 assume !(0 != activate_threads_~tmp___0~0); 3909#L965-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3910#L416 assume !(1 == ~t2_pc~0); 3814#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 3815#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4187#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3460#L973 assume !(0 != activate_threads_~tmp___1~0); 3461#L973-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3466#L435 assume 1 == ~t3_pc~0; 3932#L436 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3556#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3557#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4125#L981 assume !(0 != activate_threads_~tmp___2~0); 4115#L981-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4116#L454 assume !(1 == ~t4_pc~0); 4045#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 3766#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3508#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3509#L989 assume !(0 != activate_threads_~tmp___3~0); 3839#L989-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3841#L473 assume 1 == ~t5_pc~0; 4157#L474 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 3892#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3744#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3745#L997 assume !(0 != activate_threads_~tmp___4~0); 4243#L997-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4244#L492 assume 1 == ~t6_pc~0; 4247#L493 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 3989#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 3954#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3955#L1005 assume !(0 != activate_threads_~tmp___5~0); 4160#L1005-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 3429#L511 assume !(1 == ~t7_pc~0); 3430#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 3586#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 4001#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3885#L1013 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 3877#L1013-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3878#L859 assume !(1 == ~M_E~0); 3866#L859-2 assume !(1 == ~T1_E~0); 3607#L864-1 assume !(1 == ~T2_E~0); 3608#L869-1 assume !(1 == ~T3_E~0); 4002#L874-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3829#L879-1 assume !(1 == ~T5_E~0); 3526#L884-1 assume !(1 == ~T6_E~0); 3527#L889-1 assume !(1 == ~T7_E~0); 4166#L894-1 assume !(1 == ~E_M~0); 3911#L899-1 assume !(1 == ~E_1~0); 3679#L904-1 assume !(1 == ~E_2~0); 3680#L909-1 assume !(1 == ~E_3~0); 4209#L914-1 assume 1 == ~E_4~0;~E_4~0 := 2; 4075#L919-1 assume !(1 == ~E_5~0); 3908#L924-1 assume !(1 == ~E_6~0); 3469#L929-1 assume !(1 == ~E_7~0); 3470#L934-1 assume { :end_inline_reset_delta_events } true; 3707#L1180-3 [2018-11-18 09:04:50,486 INFO L796 eck$LassoCheckResult]: Loop: 3707#L1180-3 assume true; 4169#L1180-1 assume !false; 4161#L1181 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 3597#L746 assume true; 3898#L638-1 assume !false; 3874#L639 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 3875#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 3522#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 4113#L629 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 3415#L643 assume !(0 != eval_~tmp~0); 3417#L761 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 3764#L531-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 3765#L771-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3739#L771-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3598#L776-3 assume !(0 == ~T2_E~0); 3599#L781-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4005#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3822#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3518#L796-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3519#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4165#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3993#L811-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3669#L816-3 assume !(0 == ~E_2~0); 3670#L821-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4206#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4074#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3904#L836-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3450#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3451#L846-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3432#L378-27 assume 1 == ~m_pc~0; 3433#L379-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3612#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4016#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4078#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4214#L957-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3658#L397-27 assume !(1 == ~t1_pc~0); 3659#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 3661#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4143#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3973#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3965#L965-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3827#L416-27 assume 1 == ~t2_pc~0; 3779#L417-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3780#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4177#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3613#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3614#L973-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3620#L435-27 assume 1 == ~t3_pc~0; 3927#L436-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3552#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3553#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4175#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4170#L981-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4054#L454-27 assume 1 == ~t4_pc~0; 4009#L455-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3751#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3475#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3476#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 3782#L989-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3786#L473-27 assume 1 == ~t5_pc~0; 4135#L474-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 3890#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3704#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3705#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 4224#L997-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4225#L492-27 assume 1 == ~t6_pc~0; 4190#L493-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 3969#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 3864#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3865#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 4015#L1005-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 3584#L511-27 assume 1 == ~t7_pc~0; 3544#L512-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 3545#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 4061#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3711#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 3689#L1013-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3690#L859-3 assume !(1 == ~M_E~0); 3870#L859-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3590#L864-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3591#L869-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4003#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3834#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3528#L884-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3529#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4167#L894-3 assume !(1 == ~E_M~0); 3914#L899-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3684#L904-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3685#L909-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4210#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4072#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3902#L924-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3438#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3439#L934-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 4162#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 3525#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 4100#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 4101#L1199 assume !(0 == start_simulation_~tmp~3); 3846#L1199-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 4163#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 3504#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 4104#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 4105#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4076#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 4063#L1162 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 3706#L1212 assume !(0 != start_simulation_~tmp___0~1); 3707#L1180-3 [2018-11-18 09:04:50,486 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:50,486 INFO L82 PathProgramCache]: Analyzing trace with hash 33886909, now seen corresponding path program 1 times [2018-11-18 09:04:50,486 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:50,486 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:50,487 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:50,487 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:50,487 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:50,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:50,519 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:50,519 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:50,519 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:04:50,520 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 09:04:50,520 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:50,520 INFO L82 PathProgramCache]: Analyzing trace with hash 744138663, now seen corresponding path program 2 times [2018-11-18 09:04:50,520 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:50,520 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:50,521 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:50,521 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:50,521 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:50,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:50,586 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:50,587 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:50,587 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:04:50,587 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:04:50,587 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:04:50,587 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:04:50,588 INFO L87 Difference]: Start difference. First operand 845 states and 1258 transitions. cyclomatic complexity: 414 Second operand 3 states. [2018-11-18 09:04:50,602 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:04:50,602 INFO L93 Difference]: Finished difference Result 845 states and 1257 transitions. [2018-11-18 09:04:50,603 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:04:50,603 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 845 states and 1257 transitions. [2018-11-18 09:04:50,605 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 742 [2018-11-18 09:04:50,607 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 845 states to 845 states and 1257 transitions. [2018-11-18 09:04:50,607 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 845 [2018-11-18 09:04:50,608 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 845 [2018-11-18 09:04:50,608 INFO L73 IsDeterministic]: Start isDeterministic. Operand 845 states and 1257 transitions. [2018-11-18 09:04:50,609 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:04:50,609 INFO L705 BuchiCegarLoop]: Abstraction has 845 states and 1257 transitions. [2018-11-18 09:04:50,610 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 845 states and 1257 transitions. [2018-11-18 09:04:50,615 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 845 to 845. [2018-11-18 09:04:50,615 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 845 states. [2018-11-18 09:04:50,617 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 845 states to 845 states and 1257 transitions. [2018-11-18 09:04:50,617 INFO L728 BuchiCegarLoop]: Abstraction has 845 states and 1257 transitions. [2018-11-18 09:04:50,617 INFO L608 BuchiCegarLoop]: Abstraction has 845 states and 1257 transitions. [2018-11-18 09:04:50,617 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ [2018-11-18 09:04:50,617 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 845 states and 1257 transitions. [2018-11-18 09:04:50,619 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 742 [2018-11-18 09:04:50,619 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:04:50,619 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:04:50,621 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:50,621 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:50,621 INFO L794 eck$LassoCheckResult]: Stem: 5584#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 5486#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 5487#L1143 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 5457#L531 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5458#L538 assume 1 == ~m_i~0;~m_st~0 := 0; 5883#L538-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5738#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5650#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5459#L553-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5460#L558-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5803#L563-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5645#L568-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5438#L573-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5439#L771 assume !(0 == ~M_E~0); 5564#L771-2 assume !(0 == ~T1_E~0); 5289#L776-1 assume !(0 == ~T2_E~0); 5290#L781-1 assume !(0 == ~T3_E~0); 5701#L786-1 assume !(0 == ~T4_E~0); 5532#L791-1 assume !(0 == ~T5_E~0); 5227#L796-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5228#L801-1 assume !(0 == ~T7_E~0); 5865#L806-1 assume !(0 == ~E_M~0); 5612#L811-1 assume !(0 == ~E_1~0); 5383#L816-1 assume !(0 == ~E_2~0); 5384#L821-1 assume !(0 == ~E_3~0); 5902#L826-1 assume !(0 == ~E_4~0); 5770#L831-1 assume !(0 == ~E_5~0); 5600#L836-1 assume 0 == ~E_6~0;~E_6~0 := 1; 5137#L841-1 assume !(0 == ~E_7~0); 5138#L846-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5211#L378 assume !(1 == ~m_pc~0); 5185#L378-2 is_master_triggered_~__retres1~0 := 0; 5186#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5745#L390 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5784#L957 assume !(0 != activate_threads_~tmp~1); 5919#L957-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5417#L397 assume 1 == ~t1_pc~0; 5333#L398 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5334#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5788#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5615#L965 assume !(0 != activate_threads_~tmp___0~0); 5606#L965-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5607#L416 assume !(1 == ~t2_pc~0); 5511#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 5512#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5884#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5157#L973 assume !(0 != activate_threads_~tmp___1~0); 5158#L973-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5163#L435 assume 1 == ~t3_pc~0; 5629#L436 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5253#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5254#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5822#L981 assume !(0 != activate_threads_~tmp___2~0); 5812#L981-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5813#L454 assume !(1 == ~t4_pc~0); 5742#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 5463#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5205#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5206#L989 assume !(0 != activate_threads_~tmp___3~0); 5536#L989-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5538#L473 assume 1 == ~t5_pc~0; 5854#L474 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 5589#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5441#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5442#L997 assume !(0 != activate_threads_~tmp___4~0); 5940#L997-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 5941#L492 assume 1 == ~t6_pc~0; 5944#L493 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 5686#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 5651#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5652#L1005 assume !(0 != activate_threads_~tmp___5~0); 5857#L1005-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 5126#L511 assume !(1 == ~t7_pc~0); 5127#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 5283#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 5698#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5582#L1013 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 5574#L1013-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5575#L859 assume !(1 == ~M_E~0); 5563#L859-2 assume !(1 == ~T1_E~0); 5304#L864-1 assume !(1 == ~T2_E~0); 5305#L869-1 assume !(1 == ~T3_E~0); 5699#L874-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5526#L879-1 assume !(1 == ~T5_E~0); 5223#L884-1 assume !(1 == ~T6_E~0); 5224#L889-1 assume !(1 == ~T7_E~0); 5863#L894-1 assume !(1 == ~E_M~0); 5608#L899-1 assume !(1 == ~E_1~0); 5376#L904-1 assume !(1 == ~E_2~0); 5377#L909-1 assume !(1 == ~E_3~0); 5906#L914-1 assume 1 == ~E_4~0;~E_4~0 := 2; 5772#L919-1 assume !(1 == ~E_5~0); 5605#L924-1 assume !(1 == ~E_6~0); 5166#L929-1 assume !(1 == ~E_7~0); 5167#L934-1 assume { :end_inline_reset_delta_events } true; 5404#L1180-3 [2018-11-18 09:04:50,621 INFO L796 eck$LassoCheckResult]: Loop: 5404#L1180-3 assume true; 5866#L1180-1 assume !false; 5858#L1181 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 5294#L746 assume true; 5595#L638-1 assume !false; 5571#L639 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 5572#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 5219#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 5810#L629 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 5112#L643 assume !(0 != eval_~tmp~0); 5114#L761 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 5461#L531-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 5462#L771-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5436#L771-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5295#L776-3 assume !(0 == ~T2_E~0); 5296#L781-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5702#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5519#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5215#L796-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5216#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5862#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5690#L811-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5366#L816-3 assume !(0 == ~E_2~0); 5367#L821-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5903#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5771#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5601#L836-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5147#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5148#L846-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5129#L378-27 assume 1 == ~m_pc~0; 5130#L379-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 5309#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5713#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5775#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5911#L957-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5355#L397-27 assume !(1 == ~t1_pc~0); 5356#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 5358#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5840#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5670#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5662#L965-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5524#L416-27 assume 1 == ~t2_pc~0; 5476#L417-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5477#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5874#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5310#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5311#L973-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5317#L435-27 assume 1 == ~t3_pc~0; 5624#L436-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5249#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5250#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5872#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5867#L981-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5751#L454-27 assume 1 == ~t4_pc~0; 5706#L455-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5448#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5172#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5173#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5479#L989-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5483#L473-27 assume 1 == ~t5_pc~0; 5832#L474-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 5587#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5401#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5402#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 5921#L997-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 5922#L492-27 assume !(1 == ~t6_pc~0); 5888#L492-29 is_transmit6_triggered_~__retres1~6 := 0; 5666#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 5561#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5562#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 5712#L1005-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 5281#L511-27 assume 1 == ~t7_pc~0; 5241#L512-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 5242#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 5758#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5408#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 5386#L1013-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5387#L859-3 assume !(1 == ~M_E~0); 5567#L859-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5287#L864-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5288#L869-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5700#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5531#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5225#L884-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5226#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5864#L894-3 assume !(1 == ~E_M~0); 5611#L899-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5381#L904-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5382#L909-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5907#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5769#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5599#L924-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5135#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5136#L934-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 5859#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 5222#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 5797#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 5798#L1199 assume !(0 == start_simulation_~tmp~3); 5543#L1199-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 5860#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 5201#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 5801#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 5802#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5773#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 5760#L1162 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 5403#L1212 assume !(0 != start_simulation_~tmp___0~1); 5404#L1180-3 [2018-11-18 09:04:50,622 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:50,622 INFO L82 PathProgramCache]: Analyzing trace with hash 1028580607, now seen corresponding path program 1 times [2018-11-18 09:04:50,622 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:50,622 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:50,623 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:50,623 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 09:04:50,623 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:50,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:50,659 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:50,659 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:50,660 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:04:50,660 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 09:04:50,660 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:50,660 INFO L82 PathProgramCache]: Analyzing trace with hash 258963944, now seen corresponding path program 1 times [2018-11-18 09:04:50,660 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:50,660 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:50,661 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:50,661 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:50,661 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:50,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:50,705 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:50,705 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:50,705 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:04:50,706 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:04:50,706 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:04:50,706 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:04:50,706 INFO L87 Difference]: Start difference. First operand 845 states and 1257 transitions. cyclomatic complexity: 413 Second operand 3 states. [2018-11-18 09:04:50,718 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:04:50,718 INFO L93 Difference]: Finished difference Result 845 states and 1256 transitions. [2018-11-18 09:04:50,719 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:04:50,719 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 845 states and 1256 transitions. [2018-11-18 09:04:50,721 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 742 [2018-11-18 09:04:50,723 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 845 states to 845 states and 1256 transitions. [2018-11-18 09:04:50,723 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 845 [2018-11-18 09:04:50,724 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 845 [2018-11-18 09:04:50,724 INFO L73 IsDeterministic]: Start isDeterministic. Operand 845 states and 1256 transitions. [2018-11-18 09:04:50,725 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:04:50,725 INFO L705 BuchiCegarLoop]: Abstraction has 845 states and 1256 transitions. [2018-11-18 09:04:50,726 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 845 states and 1256 transitions. [2018-11-18 09:04:50,731 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 845 to 845. [2018-11-18 09:04:50,731 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 845 states. [2018-11-18 09:04:50,732 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 845 states to 845 states and 1256 transitions. [2018-11-18 09:04:50,732 INFO L728 BuchiCegarLoop]: Abstraction has 845 states and 1256 transitions. [2018-11-18 09:04:50,732 INFO L608 BuchiCegarLoop]: Abstraction has 845 states and 1256 transitions. [2018-11-18 09:04:50,732 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ [2018-11-18 09:04:50,733 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 845 states and 1256 transitions. [2018-11-18 09:04:50,735 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 742 [2018-11-18 09:04:50,735 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:04:50,735 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:04:50,736 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:50,736 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:50,736 INFO L794 eck$LassoCheckResult]: Stem: 7281#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 7183#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 7184#L1143 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 7154#L531 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7155#L538 assume 1 == ~m_i~0;~m_st~0 := 0; 7580#L538-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7436#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7347#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7156#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7157#L558-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7500#L563-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7342#L568-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7135#L573-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7136#L771 assume !(0 == ~M_E~0); 7261#L771-2 assume !(0 == ~T1_E~0); 6987#L776-1 assume !(0 == ~T2_E~0); 6988#L781-1 assume !(0 == ~T3_E~0); 7398#L786-1 assume !(0 == ~T4_E~0); 7229#L791-1 assume !(0 == ~T5_E~0); 6924#L796-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6925#L801-1 assume !(0 == ~T7_E~0); 7562#L806-1 assume !(0 == ~E_M~0); 7309#L811-1 assume !(0 == ~E_1~0); 7080#L816-1 assume !(0 == ~E_2~0); 7081#L821-1 assume !(0 == ~E_3~0); 7599#L826-1 assume !(0 == ~E_4~0); 7467#L831-1 assume !(0 == ~E_5~0); 7297#L836-1 assume 0 == ~E_6~0;~E_6~0 := 1; 6839#L841-1 assume !(0 == ~E_7~0); 6840#L846-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6908#L378 assume !(1 == ~m_pc~0); 6882#L378-2 is_master_triggered_~__retres1~0 := 0; 6883#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7444#L390 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7481#L957 assume !(0 != activate_threads_~tmp~1); 7616#L957-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7114#L397 assume 1 == ~t1_pc~0; 7030#L398 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 7031#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7485#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7312#L965 assume !(0 != activate_threads_~tmp___0~0); 7303#L965-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7304#L416 assume !(1 == ~t2_pc~0); 7208#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 7209#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7581#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6854#L973 assume !(0 != activate_threads_~tmp___1~0); 6855#L973-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6862#L435 assume 1 == ~t3_pc~0; 7326#L436 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 6953#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6954#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7519#L981 assume !(0 != activate_threads_~tmp___2~0); 7509#L981-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7510#L454 assume !(1 == ~t4_pc~0); 7439#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 7160#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6902#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6903#L989 assume !(0 != activate_threads_~tmp___3~0); 7233#L989-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7235#L473 assume 1 == ~t5_pc~0; 7551#L474 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 7286#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7138#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7139#L997 assume !(0 != activate_threads_~tmp___4~0); 7637#L997-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7638#L492 assume 1 == ~t6_pc~0; 7641#L493 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 7383#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 7348#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 7349#L1005 assume !(0 != activate_threads_~tmp___5~0); 7554#L1005-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 6827#L511 assume !(1 == ~t7_pc~0); 6828#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 6980#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 7395#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 7279#L1013 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 7271#L1013-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7272#L859 assume !(1 == ~M_E~0); 7260#L859-2 assume !(1 == ~T1_E~0); 7001#L864-1 assume !(1 == ~T2_E~0); 7002#L869-1 assume !(1 == ~T3_E~0); 7396#L874-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7224#L879-1 assume !(1 == ~T5_E~0); 6920#L884-1 assume !(1 == ~T6_E~0); 6921#L889-1 assume !(1 == ~T7_E~0); 7560#L894-1 assume !(1 == ~E_M~0); 7307#L899-1 assume !(1 == ~E_1~0); 7073#L904-1 assume !(1 == ~E_2~0); 7074#L909-1 assume !(1 == ~E_3~0); 7603#L914-1 assume 1 == ~E_4~0;~E_4~0 := 2; 7469#L919-1 assume !(1 == ~E_5~0); 7302#L924-1 assume !(1 == ~E_6~0); 6863#L929-1 assume !(1 == ~E_7~0); 6864#L934-1 assume { :end_inline_reset_delta_events } true; 7101#L1180-3 [2018-11-18 09:04:50,736 INFO L796 eck$LassoCheckResult]: Loop: 7101#L1180-3 assume true; 7563#L1180-1 assume !false; 7555#L1181 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 6991#L746 assume true; 7292#L638-1 assume !false; 7269#L639 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 7270#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 6916#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 7507#L629 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 6811#L643 assume !(0 != eval_~tmp~0); 6813#L761 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 7158#L531-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 7159#L771-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7133#L771-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6992#L776-3 assume !(0 == ~T2_E~0); 6993#L781-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7399#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7217#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6912#L796-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6913#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7559#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7387#L811-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7063#L816-3 assume !(0 == ~E_2~0); 7064#L821-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7600#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7468#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7298#L836-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6844#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6845#L846-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6823#L378-27 assume 1 == ~m_pc~0; 6824#L379-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 7006#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7410#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7472#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 7608#L957-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7052#L397-27 assume !(1 == ~t1_pc~0); 7053#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 7055#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7535#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7367#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7359#L965-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7221#L416-27 assume 1 == ~t2_pc~0; 7173#L417-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7174#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7571#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7007#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7008#L973-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7014#L435-27 assume 1 == ~t3_pc~0; 7321#L436-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 6946#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6947#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7569#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 7564#L981-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7448#L454-27 assume 1 == ~t4_pc~0; 7403#L455-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7145#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6869#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6870#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 7176#L989-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7180#L473-27 assume 1 == ~t5_pc~0; 7529#L474-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 7284#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7098#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7099#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 7618#L997-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7619#L492-27 assume 1 == ~t6_pc~0; 7584#L493-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 7363#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 7258#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 7259#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 7409#L1005-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 6978#L511-27 assume 1 == ~t7_pc~0; 6938#L512-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 6939#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 7455#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 7105#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 7083#L1013-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7084#L859-3 assume !(1 == ~M_E~0); 7264#L859-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6984#L864-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6985#L869-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7397#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7228#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6922#L884-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6923#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7561#L894-3 assume !(1 == ~E_M~0); 7308#L899-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7078#L904-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7079#L909-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7604#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7466#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7296#L924-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6832#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6833#L934-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 7556#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 6919#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 7494#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 7495#L1199 assume !(0 == start_simulation_~tmp~3); 7240#L1199-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 7557#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 6898#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 7498#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 7499#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7470#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 7457#L1162 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 7100#L1212 assume !(0 != start_simulation_~tmp___0~1); 7101#L1180-3 [2018-11-18 09:04:50,737 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:50,737 INFO L82 PathProgramCache]: Analyzing trace with hash 1614856829, now seen corresponding path program 1 times [2018-11-18 09:04:50,737 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:50,737 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:50,738 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:50,738 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:50,738 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:50,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:50,767 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:50,767 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:50,768 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:04:50,768 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 09:04:50,768 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:50,768 INFO L82 PathProgramCache]: Analyzing trace with hash 744138663, now seen corresponding path program 3 times [2018-11-18 09:04:50,769 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:50,769 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:50,770 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:50,770 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:50,770 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:50,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:50,813 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:50,813 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:50,813 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:04:50,814 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:04:50,814 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:04:50,814 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:04:50,814 INFO L87 Difference]: Start difference. First operand 845 states and 1256 transitions. cyclomatic complexity: 412 Second operand 3 states. [2018-11-18 09:04:50,823 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:04:50,823 INFO L93 Difference]: Finished difference Result 845 states and 1255 transitions. [2018-11-18 09:04:50,823 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:04:50,824 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 845 states and 1255 transitions. [2018-11-18 09:04:50,826 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 742 [2018-11-18 09:04:50,828 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 845 states to 845 states and 1255 transitions. [2018-11-18 09:04:50,828 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 845 [2018-11-18 09:04:50,828 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 845 [2018-11-18 09:04:50,828 INFO L73 IsDeterministic]: Start isDeterministic. Operand 845 states and 1255 transitions. [2018-11-18 09:04:50,829 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:04:50,829 INFO L705 BuchiCegarLoop]: Abstraction has 845 states and 1255 transitions. [2018-11-18 09:04:50,830 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 845 states and 1255 transitions. [2018-11-18 09:04:50,835 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 845 to 845. [2018-11-18 09:04:50,836 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 845 states. [2018-11-18 09:04:50,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 845 states to 845 states and 1255 transitions. [2018-11-18 09:04:50,837 INFO L728 BuchiCegarLoop]: Abstraction has 845 states and 1255 transitions. [2018-11-18 09:04:50,837 INFO L608 BuchiCegarLoop]: Abstraction has 845 states and 1255 transitions. [2018-11-18 09:04:50,837 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ [2018-11-18 09:04:50,837 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 845 states and 1255 transitions. [2018-11-18 09:04:50,839 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 742 [2018-11-18 09:04:50,839 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:04:50,839 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:04:50,841 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:50,841 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:50,841 INFO L794 eck$LassoCheckResult]: Stem: 8978#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 8880#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 8881#L1143 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 8851#L531 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8852#L538 assume 1 == ~m_i~0;~m_st~0 := 0; 9277#L538-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9133#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9044#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8853#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8854#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9197#L563-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9039#L568-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8832#L573-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8833#L771 assume !(0 == ~M_E~0); 8958#L771-2 assume !(0 == ~T1_E~0); 8684#L776-1 assume !(0 == ~T2_E~0); 8685#L781-1 assume !(0 == ~T3_E~0); 9095#L786-1 assume !(0 == ~T4_E~0); 8926#L791-1 assume !(0 == ~T5_E~0); 8621#L796-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8622#L801-1 assume !(0 == ~T7_E~0); 9259#L806-1 assume !(0 == ~E_M~0); 9006#L811-1 assume !(0 == ~E_1~0); 8777#L816-1 assume !(0 == ~E_2~0); 8778#L821-1 assume !(0 == ~E_3~0); 9296#L826-1 assume !(0 == ~E_4~0); 9164#L831-1 assume !(0 == ~E_5~0); 8994#L836-1 assume 0 == ~E_6~0;~E_6~0 := 1; 8531#L841-1 assume !(0 == ~E_7~0); 8532#L846-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8605#L378 assume !(1 == ~m_pc~0); 8579#L378-2 is_master_triggered_~__retres1~0 := 0; 8580#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9139#L390 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 9178#L957 assume !(0 != activate_threads_~tmp~1); 9313#L957-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8811#L397 assume 1 == ~t1_pc~0; 8727#L398 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 8728#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9182#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 9009#L965 assume !(0 != activate_threads_~tmp___0~0); 9000#L965-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9001#L416 assume !(1 == ~t2_pc~0); 8905#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 8906#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9278#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 8551#L973 assume !(0 != activate_threads_~tmp___1~0); 8552#L973-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8557#L435 assume 1 == ~t3_pc~0; 9023#L436 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 8650#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8651#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9216#L981 assume !(0 != activate_threads_~tmp___2~0); 9206#L981-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9207#L454 assume !(1 == ~t4_pc~0); 9136#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 8857#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8599#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 8600#L989 assume !(0 != activate_threads_~tmp___3~0); 8930#L989-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8932#L473 assume 1 == ~t5_pc~0; 9248#L474 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 8983#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8835#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 8836#L997 assume !(0 != activate_threads_~tmp___4~0); 9334#L997-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 9335#L492 assume 1 == ~t6_pc~0; 9338#L493 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 9080#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 9045#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 9046#L1005 assume !(0 != activate_threads_~tmp___5~0); 9251#L1005-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 8520#L511 assume !(1 == ~t7_pc~0); 8521#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 8677#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 9092#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 8976#L1013 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 8968#L1013-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8969#L859 assume !(1 == ~M_E~0); 8957#L859-2 assume !(1 == ~T1_E~0); 8698#L864-1 assume !(1 == ~T2_E~0); 8699#L869-1 assume !(1 == ~T3_E~0); 9093#L874-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8920#L879-1 assume !(1 == ~T5_E~0); 8617#L884-1 assume !(1 == ~T6_E~0); 8618#L889-1 assume !(1 == ~T7_E~0); 9257#L894-1 assume !(1 == ~E_M~0); 9002#L899-1 assume !(1 == ~E_1~0); 8770#L904-1 assume !(1 == ~E_2~0); 8771#L909-1 assume !(1 == ~E_3~0); 9300#L914-1 assume 1 == ~E_4~0;~E_4~0 := 2; 9166#L919-1 assume !(1 == ~E_5~0); 8999#L924-1 assume !(1 == ~E_6~0); 8560#L929-1 assume !(1 == ~E_7~0); 8561#L934-1 assume { :end_inline_reset_delta_events } true; 8798#L1180-3 [2018-11-18 09:04:50,841 INFO L796 eck$LassoCheckResult]: Loop: 8798#L1180-3 assume true; 9260#L1180-1 assume !false; 9252#L1181 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 8688#L746 assume true; 8989#L638-1 assume !false; 8966#L639 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 8967#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 8613#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 9204#L629 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 8506#L643 assume !(0 != eval_~tmp~0); 8508#L761 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 8855#L531-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 8856#L771-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8830#L771-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8689#L776-3 assume !(0 == ~T2_E~0); 8690#L781-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9096#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8913#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8609#L796-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8610#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9256#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9084#L811-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8760#L816-3 assume !(0 == ~E_2~0); 8761#L821-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9297#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9165#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8995#L836-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8541#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8542#L846-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8523#L378-27 assume 1 == ~m_pc~0; 8524#L379-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 8703#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9107#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 9169#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 9305#L957-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8749#L397-27 assume !(1 == ~t1_pc~0); 8750#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 8752#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9234#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 9064#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9056#L965-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8918#L416-27 assume 1 == ~t2_pc~0; 8870#L417-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 8871#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9268#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 8704#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 8705#L973-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8712#L435-27 assume 1 == ~t3_pc~0; 9018#L436-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 8643#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8644#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9266#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 9261#L981-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9145#L454-27 assume 1 == ~t4_pc~0; 9099#L455-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 8842#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8566#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 8567#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 8873#L989-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8877#L473-27 assume 1 == ~t5_pc~0; 9225#L474-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 8981#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8795#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 8796#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 9315#L997-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 9316#L492-27 assume 1 == ~t6_pc~0; 9281#L493-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 9059#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 8955#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 8956#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 9106#L1005-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 8675#L511-27 assume 1 == ~t7_pc~0; 8633#L512-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 8634#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 9152#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 8802#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 8780#L1013-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8781#L859-3 assume !(1 == ~M_E~0); 8961#L859-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8681#L864-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8682#L869-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9094#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8925#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8619#L884-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8620#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9258#L894-3 assume !(1 == ~E_M~0); 9005#L899-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8775#L904-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8776#L909-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9301#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9163#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8993#L924-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8529#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8530#L934-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 9253#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 8616#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 9191#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 9192#L1199 assume !(0 == start_simulation_~tmp~3); 8937#L1199-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 9254#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 8595#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 9195#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 9196#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 9167#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 9154#L1162 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 8797#L1212 assume !(0 != start_simulation_~tmp___0~1); 8798#L1180-3 [2018-11-18 09:04:50,841 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:50,841 INFO L82 PathProgramCache]: Analyzing trace with hash -721535681, now seen corresponding path program 1 times [2018-11-18 09:04:50,842 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:50,842 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:50,842 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:50,842 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 09:04:50,842 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:50,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:50,872 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:50,873 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:50,873 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:04:50,873 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 09:04:50,873 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:50,873 INFO L82 PathProgramCache]: Analyzing trace with hash 744138663, now seen corresponding path program 4 times [2018-11-18 09:04:50,873 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:50,874 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:50,874 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:50,874 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:50,874 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:50,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:50,913 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:50,913 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:50,913 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:04:50,914 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:04:50,914 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:04:50,914 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:04:50,914 INFO L87 Difference]: Start difference. First operand 845 states and 1255 transitions. cyclomatic complexity: 411 Second operand 3 states. [2018-11-18 09:04:50,927 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:04:50,927 INFO L93 Difference]: Finished difference Result 845 states and 1254 transitions. [2018-11-18 09:04:50,928 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:04:50,928 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 845 states and 1254 transitions. [2018-11-18 09:04:50,930 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 742 [2018-11-18 09:04:50,932 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 845 states to 845 states and 1254 transitions. [2018-11-18 09:04:50,932 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 845 [2018-11-18 09:04:50,933 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 845 [2018-11-18 09:04:50,933 INFO L73 IsDeterministic]: Start isDeterministic. Operand 845 states and 1254 transitions. [2018-11-18 09:04:50,934 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:04:50,934 INFO L705 BuchiCegarLoop]: Abstraction has 845 states and 1254 transitions. [2018-11-18 09:04:50,935 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 845 states and 1254 transitions. [2018-11-18 09:04:50,940 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 845 to 845. [2018-11-18 09:04:50,940 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 845 states. [2018-11-18 09:04:50,941 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 845 states to 845 states and 1254 transitions. [2018-11-18 09:04:50,941 INFO L728 BuchiCegarLoop]: Abstraction has 845 states and 1254 transitions. [2018-11-18 09:04:50,942 INFO L608 BuchiCegarLoop]: Abstraction has 845 states and 1254 transitions. [2018-11-18 09:04:50,942 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ [2018-11-18 09:04:50,942 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 845 states and 1254 transitions. [2018-11-18 09:04:50,944 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 742 [2018-11-18 09:04:50,944 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:04:50,944 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:04:50,945 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:50,945 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:50,945 INFO L794 eck$LassoCheckResult]: Stem: 10675#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 10577#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 10578#L1143 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 10548#L531 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10549#L538 assume 1 == ~m_i~0;~m_st~0 := 0; 10974#L538-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10829#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10741#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10550#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10551#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10894#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10736#L568-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10529#L573-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10530#L771 assume !(0 == ~M_E~0); 10655#L771-2 assume !(0 == ~T1_E~0); 10380#L776-1 assume !(0 == ~T2_E~0); 10381#L781-1 assume !(0 == ~T3_E~0); 10792#L786-1 assume !(0 == ~T4_E~0); 10623#L791-1 assume !(0 == ~T5_E~0); 10318#L796-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10319#L801-1 assume !(0 == ~T7_E~0); 10956#L806-1 assume !(0 == ~E_M~0); 10703#L811-1 assume !(0 == ~E_1~0); 10474#L816-1 assume !(0 == ~E_2~0); 10475#L821-1 assume !(0 == ~E_3~0); 10993#L826-1 assume !(0 == ~E_4~0); 10861#L831-1 assume !(0 == ~E_5~0); 10691#L836-1 assume 0 == ~E_6~0;~E_6~0 := 1; 10228#L841-1 assume !(0 == ~E_7~0); 10229#L846-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10302#L378 assume !(1 == ~m_pc~0); 10276#L378-2 is_master_triggered_~__retres1~0 := 0; 10277#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10836#L390 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 10875#L957 assume !(0 != activate_threads_~tmp~1); 11010#L957-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10508#L397 assume 1 == ~t1_pc~0; 10424#L398 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 10425#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10879#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 10706#L965 assume !(0 != activate_threads_~tmp___0~0); 10697#L965-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10698#L416 assume !(1 == ~t2_pc~0); 10602#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 10603#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10975#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 10248#L973 assume !(0 != activate_threads_~tmp___1~0); 10249#L973-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10254#L435 assume 1 == ~t3_pc~0; 10720#L436 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 10344#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10345#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 10913#L981 assume !(0 != activate_threads_~tmp___2~0); 10903#L981-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 10904#L454 assume !(1 == ~t4_pc~0); 10833#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 10554#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 10296#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 10297#L989 assume !(0 != activate_threads_~tmp___3~0); 10627#L989-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10629#L473 assume 1 == ~t5_pc~0; 10945#L474 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 10680#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 10532#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 10533#L997 assume !(0 != activate_threads_~tmp___4~0); 11031#L997-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 11032#L492 assume 1 == ~t6_pc~0; 11035#L493 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 10777#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 10742#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 10743#L1005 assume !(0 != activate_threads_~tmp___5~0); 10948#L1005-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 10217#L511 assume !(1 == ~t7_pc~0); 10218#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 10374#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 10789#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 10673#L1013 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 10665#L1013-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10666#L859 assume !(1 == ~M_E~0); 10654#L859-2 assume !(1 == ~T1_E~0); 10395#L864-1 assume !(1 == ~T2_E~0); 10396#L869-1 assume !(1 == ~T3_E~0); 10790#L874-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10617#L879-1 assume !(1 == ~T5_E~0); 10314#L884-1 assume !(1 == ~T6_E~0); 10315#L889-1 assume !(1 == ~T7_E~0); 10954#L894-1 assume !(1 == ~E_M~0); 10699#L899-1 assume !(1 == ~E_1~0); 10467#L904-1 assume !(1 == ~E_2~0); 10468#L909-1 assume !(1 == ~E_3~0); 10997#L914-1 assume 1 == ~E_4~0;~E_4~0 := 2; 10863#L919-1 assume !(1 == ~E_5~0); 10696#L924-1 assume !(1 == ~E_6~0); 10257#L929-1 assume !(1 == ~E_7~0); 10258#L934-1 assume { :end_inline_reset_delta_events } true; 10495#L1180-3 [2018-11-18 09:04:50,946 INFO L796 eck$LassoCheckResult]: Loop: 10495#L1180-3 assume true; 10957#L1180-1 assume !false; 10949#L1181 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 10385#L746 assume true; 10686#L638-1 assume !false; 10662#L639 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 10663#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 10310#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 10901#L629 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 10203#L643 assume !(0 != eval_~tmp~0); 10205#L761 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 10552#L531-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 10553#L771-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10527#L771-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10386#L776-3 assume !(0 == ~T2_E~0); 10387#L781-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10793#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10610#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10306#L796-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10307#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10953#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10781#L811-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10457#L816-3 assume !(0 == ~E_2~0); 10458#L821-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10994#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10862#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10692#L836-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10238#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10239#L846-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10220#L378-27 assume 1 == ~m_pc~0; 10221#L379-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 10400#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10804#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 10866#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 11002#L957-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10446#L397-27 assume 1 == ~t1_pc~0; 10448#L398-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 10449#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10931#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 10761#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 10753#L965-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10615#L416-27 assume 1 == ~t2_pc~0; 10567#L417-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 10568#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10965#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 10401#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 10402#L973-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10408#L435-27 assume 1 == ~t3_pc~0; 10715#L436-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 10340#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10341#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 10963#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 10958#L981-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 10842#L454-27 assume 1 == ~t4_pc~0; 10797#L455-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 10539#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 10263#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 10264#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 10570#L989-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10574#L473-27 assume 1 == ~t5_pc~0; 10923#L474-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 10678#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 10492#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 10493#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 11012#L997-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 11013#L492-27 assume 1 == ~t6_pc~0; 10978#L493-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 10757#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 10652#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 10653#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 10803#L1005-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 10372#L511-27 assume 1 == ~t7_pc~0; 10332#L512-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 10333#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 10849#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 10499#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 10477#L1013-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10478#L859-3 assume !(1 == ~M_E~0); 10658#L859-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10378#L864-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10379#L869-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10791#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10622#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10316#L884-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10317#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10955#L894-3 assume !(1 == ~E_M~0); 10702#L899-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10472#L904-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10473#L909-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10998#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10860#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10690#L924-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10226#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10227#L934-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 10950#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 10313#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 10888#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 10889#L1199 assume !(0 == start_simulation_~tmp~3); 10634#L1199-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 10951#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 10292#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 10892#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 10893#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 10864#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 10851#L1162 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 10494#L1212 assume !(0 != start_simulation_~tmp___0~1); 10495#L1180-3 [2018-11-18 09:04:50,946 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:50,946 INFO L82 PathProgramCache]: Analyzing trace with hash 1696948797, now seen corresponding path program 1 times [2018-11-18 09:04:50,946 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:50,946 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:50,947 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:50,947 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 09:04:50,947 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:50,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:50,977 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:50,977 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:50,977 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:04:50,978 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 09:04:50,978 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:50,978 INFO L82 PathProgramCache]: Analyzing trace with hash -1595507418, now seen corresponding path program 1 times [2018-11-18 09:04:50,978 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:50,978 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:50,979 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:50,979 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:50,979 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:50,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:51,017 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:51,017 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:51,018 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:04:51,018 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:04:51,018 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:04:51,018 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:04:51,018 INFO L87 Difference]: Start difference. First operand 845 states and 1254 transitions. cyclomatic complexity: 410 Second operand 3 states. [2018-11-18 09:04:51,029 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:04:51,029 INFO L93 Difference]: Finished difference Result 845 states and 1253 transitions. [2018-11-18 09:04:51,030 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:04:51,030 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 845 states and 1253 transitions. [2018-11-18 09:04:51,033 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 742 [2018-11-18 09:04:51,034 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 845 states to 845 states and 1253 transitions. [2018-11-18 09:04:51,035 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 845 [2018-11-18 09:04:51,035 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 845 [2018-11-18 09:04:51,035 INFO L73 IsDeterministic]: Start isDeterministic. Operand 845 states and 1253 transitions. [2018-11-18 09:04:51,036 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:04:51,036 INFO L705 BuchiCegarLoop]: Abstraction has 845 states and 1253 transitions. [2018-11-18 09:04:51,038 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 845 states and 1253 transitions. [2018-11-18 09:04:51,043 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 845 to 845. [2018-11-18 09:04:51,043 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 845 states. [2018-11-18 09:04:51,045 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 845 states to 845 states and 1253 transitions. [2018-11-18 09:04:51,045 INFO L728 BuchiCegarLoop]: Abstraction has 845 states and 1253 transitions. [2018-11-18 09:04:51,045 INFO L608 BuchiCegarLoop]: Abstraction has 845 states and 1253 transitions. [2018-11-18 09:04:51,045 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ [2018-11-18 09:04:51,045 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 845 states and 1253 transitions. [2018-11-18 09:04:51,047 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 742 [2018-11-18 09:04:51,047 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:04:51,047 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:04:51,048 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:51,048 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:51,049 INFO L794 eck$LassoCheckResult]: Stem: 12372#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 12274#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 12275#L1143 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 12245#L531 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12246#L538 assume 1 == ~m_i~0;~m_st~0 := 0; 12671#L538-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12526#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12438#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12247#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12248#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12591#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12433#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 12226#L573-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12227#L771 assume !(0 == ~M_E~0); 12352#L771-2 assume !(0 == ~T1_E~0); 12077#L776-1 assume !(0 == ~T2_E~0); 12078#L781-1 assume !(0 == ~T3_E~0); 12489#L786-1 assume !(0 == ~T4_E~0); 12320#L791-1 assume !(0 == ~T5_E~0); 12015#L796-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12016#L801-1 assume !(0 == ~T7_E~0); 12653#L806-1 assume !(0 == ~E_M~0); 12400#L811-1 assume !(0 == ~E_1~0); 12171#L816-1 assume !(0 == ~E_2~0); 12172#L821-1 assume !(0 == ~E_3~0); 12690#L826-1 assume !(0 == ~E_4~0); 12558#L831-1 assume !(0 == ~E_5~0); 12388#L836-1 assume 0 == ~E_6~0;~E_6~0 := 1; 11925#L841-1 assume !(0 == ~E_7~0); 11926#L846-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11999#L378 assume !(1 == ~m_pc~0); 11973#L378-2 is_master_triggered_~__retres1~0 := 0; 11974#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12533#L390 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 12572#L957 assume !(0 != activate_threads_~tmp~1); 12707#L957-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12205#L397 assume 1 == ~t1_pc~0; 12121#L398 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 12122#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12576#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 12403#L965 assume !(0 != activate_threads_~tmp___0~0); 12394#L965-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12395#L416 assume !(1 == ~t2_pc~0); 12299#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 12300#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12672#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 11945#L973 assume !(0 != activate_threads_~tmp___1~0); 11946#L973-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11951#L435 assume 1 == ~t3_pc~0; 12417#L436 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 12041#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12042#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 12610#L981 assume !(0 != activate_threads_~tmp___2~0); 12600#L981-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12601#L454 assume !(1 == ~t4_pc~0); 12530#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 12251#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11993#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 11994#L989 assume !(0 != activate_threads_~tmp___3~0); 12324#L989-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12326#L473 assume 1 == ~t5_pc~0; 12642#L474 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 12377#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12229#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 12230#L997 assume !(0 != activate_threads_~tmp___4~0); 12728#L997-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 12729#L492 assume 1 == ~t6_pc~0; 12732#L493 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 12474#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 12439#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 12440#L1005 assume !(0 != activate_threads_~tmp___5~0); 12645#L1005-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 11914#L511 assume !(1 == ~t7_pc~0); 11915#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 12071#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 12486#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 12370#L1013 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 12362#L1013-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12363#L859 assume !(1 == ~M_E~0); 12351#L859-2 assume !(1 == ~T1_E~0); 12092#L864-1 assume !(1 == ~T2_E~0); 12093#L869-1 assume !(1 == ~T3_E~0); 12487#L874-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12314#L879-1 assume !(1 == ~T5_E~0); 12011#L884-1 assume !(1 == ~T6_E~0); 12012#L889-1 assume !(1 == ~T7_E~0); 12651#L894-1 assume !(1 == ~E_M~0); 12396#L899-1 assume !(1 == ~E_1~0); 12164#L904-1 assume !(1 == ~E_2~0); 12165#L909-1 assume !(1 == ~E_3~0); 12694#L914-1 assume 1 == ~E_4~0;~E_4~0 := 2; 12560#L919-1 assume !(1 == ~E_5~0); 12393#L924-1 assume !(1 == ~E_6~0); 11954#L929-1 assume !(1 == ~E_7~0); 11955#L934-1 assume { :end_inline_reset_delta_events } true; 12192#L1180-3 [2018-11-18 09:04:51,049 INFO L796 eck$LassoCheckResult]: Loop: 12192#L1180-3 assume true; 12654#L1180-1 assume !false; 12646#L1181 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 12082#L746 assume true; 12383#L638-1 assume !false; 12359#L639 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 12360#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 12007#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 12598#L629 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 11900#L643 assume !(0 != eval_~tmp~0); 11902#L761 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 12249#L531-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 12250#L771-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12224#L771-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12083#L776-3 assume !(0 == ~T2_E~0); 12084#L781-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12490#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12307#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12003#L796-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12004#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12650#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12478#L811-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12154#L816-3 assume !(0 == ~E_2~0); 12155#L821-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12691#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12559#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12389#L836-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11935#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11936#L846-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11917#L378-27 assume 1 == ~m_pc~0; 11918#L379-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 12097#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12501#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 12563#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 12699#L957-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12143#L397-27 assume !(1 == ~t1_pc~0); 12144#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 12146#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12628#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 12458#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 12450#L965-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12312#L416-27 assume 1 == ~t2_pc~0; 12264#L417-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 12265#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12662#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12098#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 12099#L973-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12105#L435-27 assume 1 == ~t3_pc~0; 12412#L436-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 12037#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12038#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 12660#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 12655#L981-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12539#L454-27 assume 1 == ~t4_pc~0; 12494#L455-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 12236#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11960#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 11961#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 12267#L989-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12271#L473-27 assume 1 == ~t5_pc~0; 12620#L474-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 12375#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12189#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 12190#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 12709#L997-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 12710#L492-27 assume 1 == ~t6_pc~0; 12675#L493-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 12454#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 12349#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 12350#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 12500#L1005-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 12069#L511-27 assume 1 == ~t7_pc~0; 12029#L512-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 12030#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 12546#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 12196#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 12174#L1013-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12175#L859-3 assume !(1 == ~M_E~0); 12355#L859-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12075#L864-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12076#L869-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12488#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12319#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12013#L884-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12014#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12652#L894-3 assume !(1 == ~E_M~0); 12399#L899-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12169#L904-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12170#L909-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12695#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12557#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12387#L924-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11923#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11924#L934-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 12647#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 12010#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 12585#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 12586#L1199 assume !(0 == start_simulation_~tmp~3); 12331#L1199-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 12648#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 11989#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 12589#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 12590#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 12561#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 12548#L1162 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 12191#L1212 assume !(0 != start_simulation_~tmp___0~1); 12192#L1180-3 [2018-11-18 09:04:51,049 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:51,049 INFO L82 PathProgramCache]: Analyzing trace with hash -718887553, now seen corresponding path program 1 times [2018-11-18 09:04:51,049 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:51,049 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:51,050 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:51,050 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:51,050 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:51,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:51,073 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:51,074 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:51,074 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 09:04:51,074 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 09:04:51,074 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:51,074 INFO L82 PathProgramCache]: Analyzing trace with hash 744138663, now seen corresponding path program 5 times [2018-11-18 09:04:51,074 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:51,074 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:51,075 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:51,075 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:51,075 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:51,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:51,113 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:51,113 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:51,113 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:04:51,114 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:04:51,114 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:04:51,114 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:04:51,114 INFO L87 Difference]: Start difference. First operand 845 states and 1253 transitions. cyclomatic complexity: 409 Second operand 3 states. [2018-11-18 09:04:51,133 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:04:51,133 INFO L93 Difference]: Finished difference Result 845 states and 1248 transitions. [2018-11-18 09:04:51,134 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:04:51,134 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 845 states and 1248 transitions. [2018-11-18 09:04:51,136 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 742 [2018-11-18 09:04:51,138 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 845 states to 845 states and 1248 transitions. [2018-11-18 09:04:51,138 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 845 [2018-11-18 09:04:51,139 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 845 [2018-11-18 09:04:51,139 INFO L73 IsDeterministic]: Start isDeterministic. Operand 845 states and 1248 transitions. [2018-11-18 09:04:51,140 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:04:51,140 INFO L705 BuchiCegarLoop]: Abstraction has 845 states and 1248 transitions. [2018-11-18 09:04:51,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 845 states and 1248 transitions. [2018-11-18 09:04:51,147 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 845 to 845. [2018-11-18 09:04:51,147 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 845 states. [2018-11-18 09:04:51,148 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 845 states to 845 states and 1248 transitions. [2018-11-18 09:04:51,148 INFO L728 BuchiCegarLoop]: Abstraction has 845 states and 1248 transitions. [2018-11-18 09:04:51,148 INFO L608 BuchiCegarLoop]: Abstraction has 845 states and 1248 transitions. [2018-11-18 09:04:51,148 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ [2018-11-18 09:04:51,148 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 845 states and 1248 transitions. [2018-11-18 09:04:51,151 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 742 [2018-11-18 09:04:51,151 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:04:51,151 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:04:51,152 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:51,152 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:51,152 INFO L794 eck$LassoCheckResult]: Stem: 14069#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 13971#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 13972#L1143 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 13942#L531 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13943#L538 assume 1 == ~m_i~0;~m_st~0 := 0; 14368#L538-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14223#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14135#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13944#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13945#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14288#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14130#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 13923#L573-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13924#L771 assume !(0 == ~M_E~0); 14049#L771-2 assume !(0 == ~T1_E~0); 13774#L776-1 assume !(0 == ~T2_E~0); 13775#L781-1 assume !(0 == ~T3_E~0); 14186#L786-1 assume !(0 == ~T4_E~0); 14017#L791-1 assume !(0 == ~T5_E~0); 13712#L796-1 assume !(0 == ~T6_E~0); 13713#L801-1 assume !(0 == ~T7_E~0); 14350#L806-1 assume !(0 == ~E_M~0); 14097#L811-1 assume !(0 == ~E_1~0); 13868#L816-1 assume !(0 == ~E_2~0); 13869#L821-1 assume !(0 == ~E_3~0); 14387#L826-1 assume !(0 == ~E_4~0); 14255#L831-1 assume !(0 == ~E_5~0); 14085#L836-1 assume 0 == ~E_6~0;~E_6~0 := 1; 13622#L841-1 assume !(0 == ~E_7~0); 13623#L846-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13696#L378 assume !(1 == ~m_pc~0); 13670#L378-2 is_master_triggered_~__retres1~0 := 0; 13671#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14230#L390 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 14269#L957 assume !(0 != activate_threads_~tmp~1); 14404#L957-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13902#L397 assume 1 == ~t1_pc~0; 13818#L398 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 13819#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14273#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 14100#L965 assume !(0 != activate_threads_~tmp___0~0); 14091#L965-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14092#L416 assume !(1 == ~t2_pc~0); 13996#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 13997#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14369#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 13642#L973 assume !(0 != activate_threads_~tmp___1~0); 13643#L973-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13648#L435 assume 1 == ~t3_pc~0; 14114#L436 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 13738#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 13739#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 14307#L981 assume !(0 != activate_threads_~tmp___2~0); 14297#L981-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 14298#L454 assume !(1 == ~t4_pc~0); 14227#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 13948#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 13690#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 13691#L989 assume !(0 != activate_threads_~tmp___3~0); 14021#L989-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 14023#L473 assume 1 == ~t5_pc~0; 14339#L474 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 14074#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 13926#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 13927#L997 assume !(0 != activate_threads_~tmp___4~0); 14425#L997-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 14426#L492 assume 1 == ~t6_pc~0; 14429#L493 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 14171#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 14136#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 14137#L1005 assume !(0 != activate_threads_~tmp___5~0); 14342#L1005-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 13611#L511 assume !(1 == ~t7_pc~0); 13612#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 13768#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 14183#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 14067#L1013 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 14059#L1013-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14060#L859 assume !(1 == ~M_E~0); 14048#L859-2 assume !(1 == ~T1_E~0); 13789#L864-1 assume !(1 == ~T2_E~0); 13790#L869-1 assume !(1 == ~T3_E~0); 14184#L874-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14011#L879-1 assume !(1 == ~T5_E~0); 13708#L884-1 assume !(1 == ~T6_E~0); 13709#L889-1 assume !(1 == ~T7_E~0); 14348#L894-1 assume !(1 == ~E_M~0); 14093#L899-1 assume !(1 == ~E_1~0); 13861#L904-1 assume !(1 == ~E_2~0); 13862#L909-1 assume !(1 == ~E_3~0); 14391#L914-1 assume 1 == ~E_4~0;~E_4~0 := 2; 14257#L919-1 assume !(1 == ~E_5~0); 14090#L924-1 assume !(1 == ~E_6~0); 13651#L929-1 assume !(1 == ~E_7~0); 13652#L934-1 assume { :end_inline_reset_delta_events } true; 13889#L1180-3 [2018-11-18 09:04:51,152 INFO L796 eck$LassoCheckResult]: Loop: 13889#L1180-3 assume true; 14351#L1180-1 assume !false; 14343#L1181 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 13779#L746 assume true; 14080#L638-1 assume !false; 14056#L639 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 14057#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 13704#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 14295#L629 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 13597#L643 assume !(0 != eval_~tmp~0); 13599#L761 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 13946#L531-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 13947#L771-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13921#L771-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13780#L776-3 assume !(0 == ~T2_E~0); 13781#L781-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14187#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14004#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13700#L796-3 assume !(0 == ~T6_E~0); 13701#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14347#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14175#L811-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13851#L816-3 assume !(0 == ~E_2~0); 13852#L821-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14388#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14256#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14086#L836-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13632#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13633#L846-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13614#L378-27 assume !(1 == ~m_pc~0); 13616#L378-29 is_master_triggered_~__retres1~0 := 0; 13794#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14198#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 14260#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 14396#L957-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13840#L397-27 assume !(1 == ~t1_pc~0); 13841#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 13843#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14325#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 14155#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 14147#L965-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14009#L416-27 assume 1 == ~t2_pc~0; 13961#L417-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 13962#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14359#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 13795#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 13796#L973-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13802#L435-27 assume 1 == ~t3_pc~0; 14109#L436-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 13734#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 13735#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 14357#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 14352#L981-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 14236#L454-27 assume !(1 == ~t4_pc~0); 14192#L454-29 is_transmit4_triggered_~__retres1~4 := 0; 13933#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 13657#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 13658#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 13964#L989-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 13968#L473-27 assume 1 == ~t5_pc~0; 14317#L474-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 14072#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 13886#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 13887#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 14406#L997-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 14407#L492-27 assume 1 == ~t6_pc~0; 14372#L493-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 14151#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 14046#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 14047#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 14197#L1005-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 13766#L511-27 assume !(1 == ~t7_pc~0); 13728#L511-29 is_transmit7_triggered_~__retres1~7 := 0; 13727#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 14243#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 13893#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 13871#L1013-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13872#L859-3 assume !(1 == ~M_E~0); 14052#L859-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13772#L864-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13773#L869-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14185#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14016#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13710#L884-3 assume !(1 == ~T6_E~0); 13711#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14349#L894-3 assume !(1 == ~E_M~0); 14096#L899-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13866#L904-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13867#L909-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14392#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14254#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14084#L924-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13620#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13621#L934-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 14344#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 13707#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 14282#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 14283#L1199 assume !(0 == start_simulation_~tmp~3); 14028#L1199-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 14345#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 13686#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 14286#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 14287#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 14258#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 14245#L1162 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 13888#L1212 assume !(0 != start_simulation_~tmp___0~1); 13889#L1180-3 [2018-11-18 09:04:51,153 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:51,153 INFO L82 PathProgramCache]: Analyzing trace with hash 1498742845, now seen corresponding path program 1 times [2018-11-18 09:04:51,153 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:51,153 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:51,153 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:51,154 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 09:04:51,154 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:51,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:51,185 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:51,186 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:51,186 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 09:04:51,186 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 09:04:51,186 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:51,186 INFO L82 PathProgramCache]: Analyzing trace with hash 1174330730, now seen corresponding path program 1 times [2018-11-18 09:04:51,186 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:51,187 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:51,187 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:51,187 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:51,187 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:51,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:51,214 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:51,214 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:51,214 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:04:51,215 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:04:51,215 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:04:51,215 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:04:51,215 INFO L87 Difference]: Start difference. First operand 845 states and 1248 transitions. cyclomatic complexity: 404 Second operand 3 states. [2018-11-18 09:04:51,270 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:04:51,270 INFO L93 Difference]: Finished difference Result 845 states and 1233 transitions. [2018-11-18 09:04:51,271 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:04:51,272 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 845 states and 1233 transitions. [2018-11-18 09:04:51,275 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 742 [2018-11-18 09:04:51,279 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 845 states to 845 states and 1233 transitions. [2018-11-18 09:04:51,279 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 845 [2018-11-18 09:04:51,280 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 845 [2018-11-18 09:04:51,280 INFO L73 IsDeterministic]: Start isDeterministic. Operand 845 states and 1233 transitions. [2018-11-18 09:04:51,281 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:04:51,281 INFO L705 BuchiCegarLoop]: Abstraction has 845 states and 1233 transitions. [2018-11-18 09:04:51,283 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 845 states and 1233 transitions. [2018-11-18 09:04:51,292 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 845 to 845. [2018-11-18 09:04:51,292 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 845 states. [2018-11-18 09:04:51,294 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 845 states to 845 states and 1233 transitions. [2018-11-18 09:04:51,294 INFO L728 BuchiCegarLoop]: Abstraction has 845 states and 1233 transitions. [2018-11-18 09:04:51,295 INFO L608 BuchiCegarLoop]: Abstraction has 845 states and 1233 transitions. [2018-11-18 09:04:51,295 INFO L442 BuchiCegarLoop]: ======== Iteration 10============ [2018-11-18 09:04:51,295 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 845 states and 1233 transitions. [2018-11-18 09:04:51,298 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 742 [2018-11-18 09:04:51,298 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:04:51,298 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:04:51,299 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:51,299 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:51,300 INFO L794 eck$LassoCheckResult]: Stem: 15766#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 15668#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 15669#L1143 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 15639#L531 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15640#L538 assume 1 == ~m_i~0;~m_st~0 := 0; 16065#L538-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15920#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15832#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15641#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15642#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15985#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 15827#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 15620#L573-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15621#L771 assume !(0 == ~M_E~0); 15746#L771-2 assume !(0 == ~T1_E~0); 15471#L776-1 assume !(0 == ~T2_E~0); 15472#L781-1 assume !(0 == ~T3_E~0); 15883#L786-1 assume !(0 == ~T4_E~0); 15714#L791-1 assume !(0 == ~T5_E~0); 15409#L796-1 assume !(0 == ~T6_E~0); 15410#L801-1 assume !(0 == ~T7_E~0); 16047#L806-1 assume !(0 == ~E_M~0); 15794#L811-1 assume !(0 == ~E_1~0); 15565#L816-1 assume !(0 == ~E_2~0); 15566#L821-1 assume !(0 == ~E_3~0); 16084#L826-1 assume !(0 == ~E_4~0); 15952#L831-1 assume !(0 == ~E_5~0); 15782#L836-1 assume !(0 == ~E_6~0); 15319#L841-1 assume !(0 == ~E_7~0); 15320#L846-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15393#L378 assume !(1 == ~m_pc~0); 15367#L378-2 is_master_triggered_~__retres1~0 := 0; 15368#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15927#L390 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 15966#L957 assume !(0 != activate_threads_~tmp~1); 16101#L957-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15599#L397 assume 1 == ~t1_pc~0; 15515#L398 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 15516#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15970#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 15797#L965 assume !(0 != activate_threads_~tmp___0~0); 15788#L965-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15789#L416 assume !(1 == ~t2_pc~0); 15693#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 15694#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16066#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 15339#L973 assume !(0 != activate_threads_~tmp___1~0); 15340#L973-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15345#L435 assume 1 == ~t3_pc~0; 15811#L436 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 15435#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15436#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 16004#L981 assume !(0 != activate_threads_~tmp___2~0); 15994#L981-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 15995#L454 assume !(1 == ~t4_pc~0); 15924#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 15645#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 15387#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 15388#L989 assume !(0 != activate_threads_~tmp___3~0); 15718#L989-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 15720#L473 assume 1 == ~t5_pc~0; 16036#L474 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 15771#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 15623#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 15624#L997 assume !(0 != activate_threads_~tmp___4~0); 16122#L997-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 16123#L492 assume !(1 == ~t6_pc~0); 16127#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 15868#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 15833#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 15834#L1005 assume !(0 != activate_threads_~tmp___5~0); 16039#L1005-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 15308#L511 assume !(1 == ~t7_pc~0); 15309#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 15465#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 15880#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 15764#L1013 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 15756#L1013-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15757#L859 assume !(1 == ~M_E~0); 15745#L859-2 assume !(1 == ~T1_E~0); 15486#L864-1 assume !(1 == ~T2_E~0); 15487#L869-1 assume !(1 == ~T3_E~0); 15881#L874-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15708#L879-1 assume !(1 == ~T5_E~0); 15405#L884-1 assume !(1 == ~T6_E~0); 15406#L889-1 assume !(1 == ~T7_E~0); 16045#L894-1 assume !(1 == ~E_M~0); 15790#L899-1 assume !(1 == ~E_1~0); 15558#L904-1 assume !(1 == ~E_2~0); 15559#L909-1 assume !(1 == ~E_3~0); 16088#L914-1 assume 1 == ~E_4~0;~E_4~0 := 2; 15954#L919-1 assume !(1 == ~E_5~0); 15787#L924-1 assume !(1 == ~E_6~0); 15348#L929-1 assume !(1 == ~E_7~0); 15349#L934-1 assume { :end_inline_reset_delta_events } true; 15586#L1180-3 [2018-11-18 09:04:51,300 INFO L796 eck$LassoCheckResult]: Loop: 15586#L1180-3 assume true; 16048#L1180-1 assume !false; 16040#L1181 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 15476#L746 assume true; 15777#L638-1 assume !false; 15753#L639 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 15754#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 15401#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 15992#L629 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 15294#L643 assume !(0 != eval_~tmp~0); 15296#L761 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 15643#L531-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 15644#L771-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15618#L771-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15477#L776-3 assume !(0 == ~T2_E~0); 15478#L781-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15884#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15701#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15397#L796-3 assume !(0 == ~T6_E~0); 15398#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16044#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 15872#L811-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15548#L816-3 assume !(0 == ~E_2~0); 15549#L821-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16085#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15953#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15783#L836-3 assume !(0 == ~E_6~0); 15329#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15330#L846-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15311#L378-27 assume 1 == ~m_pc~0; 15312#L379-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 15491#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15895#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 15957#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 16093#L957-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15537#L397-27 assume !(1 == ~t1_pc~0); 15538#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 15540#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16022#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 15852#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 15844#L965-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15706#L416-27 assume 1 == ~t2_pc~0; 15658#L417-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 15659#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16056#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 15492#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 15493#L973-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15499#L435-27 assume 1 == ~t3_pc~0; 15806#L436-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 15431#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15432#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 16054#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 16049#L981-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 15933#L454-27 assume 1 == ~t4_pc~0; 15888#L455-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 15630#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 15354#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 15355#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 15661#L989-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 15665#L473-27 assume 1 == ~t5_pc~0; 16014#L474-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 15769#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 15583#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 15584#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 16103#L997-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 16104#L492-27 assume !(1 == ~t6_pc~0); 16070#L492-29 is_transmit6_triggered_~__retres1~6 := 0; 15848#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 15743#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 15744#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 15894#L1005-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 15463#L511-27 assume !(1 == ~t7_pc~0); 15425#L511-29 is_transmit7_triggered_~__retres1~7 := 0; 15424#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 15940#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 15590#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 15568#L1013-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15569#L859-3 assume !(1 == ~M_E~0); 15749#L859-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15469#L864-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15470#L869-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15882#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15713#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15407#L884-3 assume !(1 == ~T6_E~0); 15408#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16046#L894-3 assume !(1 == ~E_M~0); 15793#L899-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15563#L904-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15564#L909-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16089#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15951#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15781#L924-3 assume !(1 == ~E_6~0); 15317#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15318#L934-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 16041#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 15404#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 15979#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 15980#L1199 assume !(0 == start_simulation_~tmp~3); 15725#L1199-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 16042#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 15383#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 15983#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 15984#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 15955#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 15942#L1162 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 15585#L1212 assume !(0 != start_simulation_~tmp___0~1); 15586#L1180-3 [2018-11-18 09:04:51,300 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:51,300 INFO L82 PathProgramCache]: Analyzing trace with hash 1481008316, now seen corresponding path program 1 times [2018-11-18 09:04:51,301 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:51,301 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:51,301 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:51,301 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:51,302 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:51,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:51,331 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:51,332 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:51,332 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 09:04:51,332 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 09:04:51,332 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:51,332 INFO L82 PathProgramCache]: Analyzing trace with hash 382882153, now seen corresponding path program 1 times [2018-11-18 09:04:51,332 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:51,333 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:51,333 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:51,333 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:51,333 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:51,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:51,365 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:51,366 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:51,366 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:04:51,366 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:04:51,366 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:04:51,366 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:04:51,366 INFO L87 Difference]: Start difference. First operand 845 states and 1233 transitions. cyclomatic complexity: 389 Second operand 3 states. [2018-11-18 09:04:51,457 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:04:51,457 INFO L93 Difference]: Finished difference Result 1518 states and 2198 transitions. [2018-11-18 09:04:51,458 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:04:51,458 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1518 states and 2198 transitions. [2018-11-18 09:04:51,466 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1414 [2018-11-18 09:04:51,474 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1518 states to 1518 states and 2198 transitions. [2018-11-18 09:04:51,474 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1518 [2018-11-18 09:04:51,475 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1518 [2018-11-18 09:04:51,475 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1518 states and 2198 transitions. [2018-11-18 09:04:51,477 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:04:51,478 INFO L705 BuchiCegarLoop]: Abstraction has 1518 states and 2198 transitions. [2018-11-18 09:04:51,479 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1518 states and 2198 transitions. [2018-11-18 09:04:51,519 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1518 to 1515. [2018-11-18 09:04:51,519 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1515 states. [2018-11-18 09:04:51,523 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1515 states to 1515 states and 2195 transitions. [2018-11-18 09:04:51,523 INFO L728 BuchiCegarLoop]: Abstraction has 1515 states and 2195 transitions. [2018-11-18 09:04:51,523 INFO L608 BuchiCegarLoop]: Abstraction has 1515 states and 2195 transitions. [2018-11-18 09:04:51,523 INFO L442 BuchiCegarLoop]: ======== Iteration 11============ [2018-11-18 09:04:51,523 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1515 states and 2195 transitions. [2018-11-18 09:04:51,527 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1411 [2018-11-18 09:04:51,528 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:04:51,528 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:04:51,529 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:51,529 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:51,529 INFO L794 eck$LassoCheckResult]: Stem: 18155#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 18057#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 18058#L1143 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 18012#L531 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18013#L538 assume 1 == ~m_i~0;~m_st~0 := 0; 18463#L538-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18314#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18224#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18014#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18015#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 18380#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 18216#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 17993#L573-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17994#L771 assume !(0 == ~M_E~0); 18135#L771-2 assume !(0 == ~T1_E~0); 17843#L776-1 assume !(0 == ~T2_E~0); 17844#L781-1 assume !(0 == ~T3_E~0); 18276#L786-1 assume !(0 == ~T4_E~0); 18103#L791-1 assume !(0 == ~T5_E~0); 17780#L796-1 assume !(0 == ~T6_E~0); 17781#L801-1 assume !(0 == ~T7_E~0); 18445#L806-1 assume !(0 == ~E_M~0); 18183#L811-1 assume !(0 == ~E_1~0); 17929#L816-1 assume !(0 == ~E_2~0); 17930#L821-1 assume !(0 == ~E_3~0); 18482#L826-1 assume !(0 == ~E_4~0); 18346#L831-1 assume !(0 == ~E_5~0); 18171#L836-1 assume !(0 == ~E_6~0); 17694#L841-1 assume !(0 == ~E_7~0); 17695#L846-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 17764#L378 assume !(1 == ~m_pc~0); 17737#L378-2 is_master_triggered_~__retres1~0 := 0; 17738#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 18322#L390 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 18361#L957 assume !(0 != activate_threads_~tmp~1); 18505#L957-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 17969#L397 assume !(1 == ~t1_pc~0); 17970#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 17978#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 18365#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 18186#L965 assume !(0 != activate_threads_~tmp___0~0); 18177#L965-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 18178#L416 assume !(1 == ~t2_pc~0); 18082#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 18083#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 18464#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 17712#L973 assume !(0 != activate_threads_~tmp___1~0); 17713#L973-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 17717#L435 assume 1 == ~t3_pc~0; 18200#L436 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 17809#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 17810#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 18400#L981 assume !(0 != activate_threads_~tmp___2~0); 18390#L981-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 18391#L454 assume !(1 == ~t4_pc~0); 18317#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 18018#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 17758#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 17759#L989 assume !(0 != activate_threads_~tmp___3~0); 18107#L989-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 18109#L473 assume 1 == ~t5_pc~0; 18433#L474 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 18160#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 17996#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 17997#L997 assume !(0 != activate_threads_~tmp___4~0); 18527#L997-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 18528#L492 assume !(1 == ~t6_pc~0); 18532#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 18261#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 18225#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 18226#L1005 assume !(0 != activate_threads_~tmp___5~0); 18436#L1005-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 17682#L511 assume !(1 == ~t7_pc~0); 17683#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 17836#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 18273#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 18153#L1013 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 18145#L1013-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18146#L859 assume !(1 == ~M_E~0); 18134#L859-2 assume !(1 == ~T1_E~0); 17857#L864-1 assume !(1 == ~T2_E~0); 17858#L869-1 assume !(1 == ~T3_E~0); 18274#L874-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18098#L879-1 assume !(1 == ~T5_E~0); 17776#L884-1 assume !(1 == ~T6_E~0); 17777#L889-1 assume !(1 == ~T7_E~0); 18443#L894-1 assume !(1 == ~E_M~0); 18181#L899-1 assume !(1 == ~E_1~0); 17923#L904-1 assume !(1 == ~E_2~0); 17924#L909-1 assume !(1 == ~E_3~0); 18486#L914-1 assume 1 == ~E_4~0;~E_4~0 := 2; 18348#L919-1 assume !(1 == ~E_5~0); 18176#L924-1 assume !(1 == ~E_6~0); 17718#L929-1 assume !(1 == ~E_7~0); 17719#L934-1 assume { :end_inline_reset_delta_events } true; 17956#L1180-3 [2018-11-18 09:04:51,529 INFO L796 eck$LassoCheckResult]: Loop: 17956#L1180-3 assume true; 18446#L1180-1 assume !false; 18438#L1181 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 17847#L746 assume true; 18166#L638-1 assume !false; 18142#L639 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 18143#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 17772#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 18388#L629 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 17666#L643 assume !(0 != eval_~tmp~0); 17668#L761 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 18016#L531-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 18017#L771-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17991#L771-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17848#L776-3 assume !(0 == ~T2_E~0); 17849#L781-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18277#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18090#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17768#L796-3 assume !(0 == ~T6_E~0); 17769#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18442#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 18265#L811-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17914#L816-3 assume !(0 == ~E_2~0); 17915#L821-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18483#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18347#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18172#L836-3 assume !(0 == ~E_6~0); 17699#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17700#L846-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 17678#L378-27 assume !(1 == ~m_pc~0); 17680#L378-29 is_master_triggered_~__retres1~0 := 0; 17862#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 18288#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 18351#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 18492#L957-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 17906#L397-27 assume !(1 == ~t1_pc~0); 17907#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 17908#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 18418#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 18244#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 18236#L965-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 18095#L416-27 assume !(1 == ~t2_pc~0); 18049#L416-29 is_transmit2_triggered_~__retres1~2 := 0; 18048#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 18454#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 17863#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 17864#L973-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 17870#L435-27 assume 1 == ~t3_pc~0; 18195#L436-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 17802#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 17803#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 18452#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 18447#L981-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 18326#L454-27 assume 1 == ~t4_pc~0; 18281#L455-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 18003#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 17724#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 17725#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 18050#L989-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 18054#L473-27 assume 1 == ~t5_pc~0; 18410#L474-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 18158#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 17953#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 17954#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 19054#L997-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 19052#L492-27 assume !(1 == ~t6_pc~0); 19050#L492-29 is_transmit6_triggered_~__retres1~6 := 0; 19049#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 19048#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 19047#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 19046#L1005-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 19045#L511-27 assume 1 == ~t7_pc~0; 19043#L512-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 19042#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 19040#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 19038#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 19037#L1013-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19036#L859-3 assume !(1 == ~M_E~0); 19035#L859-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19034#L864-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19033#L869-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19032#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19031#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19030#L884-3 assume !(1 == ~T6_E~0); 19029#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19028#L894-3 assume !(1 == ~E_M~0); 19027#L899-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19026#L904-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19025#L909-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19024#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18996#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18170#L924-3 assume !(1 == ~E_6~0); 17687#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 17688#L934-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 18439#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 17775#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 18374#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 18375#L1199 assume !(0 == start_simulation_~tmp~3); 18114#L1199-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 18440#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 17754#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 18378#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 18379#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 18349#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 18335#L1162 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 17955#L1212 assume !(0 != start_simulation_~tmp___0~1); 17956#L1180-3 [2018-11-18 09:04:51,530 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:51,530 INFO L82 PathProgramCache]: Analyzing trace with hash 449677501, now seen corresponding path program 1 times [2018-11-18 09:04:51,530 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:51,530 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:51,530 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:51,530 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:51,531 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:51,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:51,559 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:51,559 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:51,559 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 09:04:51,559 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 09:04:51,559 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:51,560 INFO L82 PathProgramCache]: Analyzing trace with hash -2133237910, now seen corresponding path program 1 times [2018-11-18 09:04:51,560 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:51,560 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:51,561 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:51,561 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:51,561 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:51,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:51,589 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:51,589 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:51,589 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:04:51,590 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:04:51,590 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:04:51,590 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:04:51,590 INFO L87 Difference]: Start difference. First operand 1515 states and 2195 transitions. cyclomatic complexity: 682 Second operand 3 states. [2018-11-18 09:04:51,653 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:04:51,653 INFO L93 Difference]: Finished difference Result 2793 states and 4021 transitions. [2018-11-18 09:04:51,654 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:04:51,654 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2793 states and 4021 transitions. [2018-11-18 09:04:51,663 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2684 [2018-11-18 09:04:51,674 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2793 states to 2793 states and 4021 transitions. [2018-11-18 09:04:51,674 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2793 [2018-11-18 09:04:51,676 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2793 [2018-11-18 09:04:51,676 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2793 states and 4021 transitions. [2018-11-18 09:04:51,680 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:04:51,680 INFO L705 BuchiCegarLoop]: Abstraction has 2793 states and 4021 transitions. [2018-11-18 09:04:51,682 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2793 states and 4021 transitions. [2018-11-18 09:04:51,707 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2793 to 2787. [2018-11-18 09:04:51,707 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2787 states. [2018-11-18 09:04:51,712 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2787 states to 2787 states and 4015 transitions. [2018-11-18 09:04:51,712 INFO L728 BuchiCegarLoop]: Abstraction has 2787 states and 4015 transitions. [2018-11-18 09:04:51,712 INFO L608 BuchiCegarLoop]: Abstraction has 2787 states and 4015 transitions. [2018-11-18 09:04:51,712 INFO L442 BuchiCegarLoop]: ======== Iteration 12============ [2018-11-18 09:04:51,713 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2787 states and 4015 transitions. [2018-11-18 09:04:51,719 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2678 [2018-11-18 09:04:51,719 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:04:51,719 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:04:51,720 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:51,720 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:51,720 INFO L794 eck$LassoCheckResult]: Stem: 22469#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 22369#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 22370#L1143 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 22322#L531 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22323#L538 assume 1 == ~m_i~0;~m_st~0 := 0; 22788#L538-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22639#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22548#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22324#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22325#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22707#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 22537#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 22303#L573-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22304#L771 assume !(0 == ~M_E~0); 22449#L771-2 assume !(0 == ~T1_E~0); 22157#L776-1 assume !(0 == ~T2_E~0); 22158#L781-1 assume !(0 == ~T3_E~0); 22601#L786-1 assume !(0 == ~T4_E~0); 22416#L791-1 assume !(0 == ~T5_E~0); 22094#L796-1 assume !(0 == ~T6_E~0); 22095#L801-1 assume !(0 == ~T7_E~0); 22770#L806-1 assume !(0 == ~E_M~0); 22497#L811-1 assume !(0 == ~E_1~0); 22241#L816-1 assume !(0 == ~E_2~0); 22242#L821-1 assume !(0 == ~E_3~0); 22807#L826-1 assume !(0 == ~E_4~0); 22673#L831-1 assume !(0 == ~E_5~0); 22485#L836-1 assume !(0 == ~E_6~0); 22006#L841-1 assume !(0 == ~E_7~0); 22007#L846-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 22078#L378 assume !(1 == ~m_pc~0); 22052#L378-2 is_master_triggered_~__retres1~0 := 0; 22053#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 22647#L390 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 22688#L957 assume !(0 != activate_threads_~tmp~1); 22827#L957-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22279#L397 assume !(1 == ~t1_pc~0); 22280#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 22287#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22692#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 22500#L965 assume !(0 != activate_threads_~tmp___0~0); 22491#L965-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22492#L416 assume !(1 == ~t2_pc~0); 22395#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 22396#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22789#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 22024#L973 assume !(0 != activate_threads_~tmp___1~0); 22025#L973-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22030#L435 assume !(1 == ~t3_pc~0); 22664#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 22123#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 22124#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 22726#L981 assume !(0 != activate_threads_~tmp___2~0); 22716#L981-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 22717#L454 assume !(1 == ~t4_pc~0); 22642#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 22328#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 22072#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 22073#L989 assume !(0 != activate_threads_~tmp___3~0); 22420#L989-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 22422#L473 assume 1 == ~t5_pc~0; 22759#L474 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 22474#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 22306#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 22307#L997 assume !(0 != activate_threads_~tmp___4~0); 22849#L997-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 22850#L492 assume !(1 == ~t6_pc~0); 22854#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 22585#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 22549#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 22550#L1005 assume !(0 != activate_threads_~tmp___5~0); 22762#L1005-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 21997#L511 assume !(1 == ~t7_pc~0); 21998#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 22150#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 22598#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 22467#L1013 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 22459#L1013-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22460#L859 assume !(1 == ~M_E~0); 22448#L859-2 assume !(1 == ~T1_E~0); 22171#L864-1 assume !(1 == ~T2_E~0); 22172#L869-1 assume !(1 == ~T3_E~0); 22599#L874-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22410#L879-1 assume !(1 == ~T5_E~0); 22090#L884-1 assume !(1 == ~T6_E~0); 22091#L889-1 assume !(1 == ~T7_E~0); 22768#L894-1 assume !(1 == ~E_M~0); 22493#L899-1 assume !(1 == ~E_1~0); 22235#L904-1 assume !(1 == ~E_2~0); 22236#L909-1 assume !(1 == ~E_3~0); 22811#L914-1 assume 1 == ~E_4~0;~E_4~0 := 2; 22675#L919-1 assume !(1 == ~E_5~0); 22490#L924-1 assume !(1 == ~E_6~0); 22033#L929-1 assume !(1 == ~E_7~0); 22034#L934-1 assume { :end_inline_reset_delta_events } true; 22266#L1180-3 [2018-11-18 09:04:51,721 INFO L796 eck$LassoCheckResult]: Loop: 22266#L1180-3 assume true; 22771#L1180-1 assume !false; 22763#L1181 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 22161#L746 assume true; 22480#L638-1 assume !false; 22457#L639 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 22458#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 22086#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 22714#L629 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 21979#L643 assume !(0 != eval_~tmp~0); 21981#L761 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 22326#L531-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 22327#L771-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22301#L771-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22162#L776-3 assume !(0 == ~T2_E~0); 22163#L781-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22602#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22404#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22082#L796-3 assume !(0 == ~T6_E~0); 22083#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22767#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22589#L811-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22227#L816-3 assume !(0 == ~E_2~0); 22228#L821-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22808#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22674#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22486#L836-3 assume !(0 == ~E_6~0); 22013#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 22014#L846-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 21993#L378-27 assume 1 == ~m_pc~0; 21994#L379-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 22176#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 22613#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 22678#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 22816#L957-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22219#L397-27 assume !(1 == ~t1_pc~0); 22220#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 22221#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22742#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 22568#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 22560#L965-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22408#L416-27 assume 1 == ~t2_pc~0; 22359#L417-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 22360#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22779#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 22177#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 22178#L973-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22185#L435-27 assume !(1 == ~t3_pc~0); 22535#L435-29 is_transmit3_triggered_~__retres1~3 := 0; 22116#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 22117#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 22777#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 22772#L981-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 22651#L454-27 assume 1 == ~t4_pc~0; 22605#L455-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 22313#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 22039#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 22040#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 22362#L989-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 22366#L473-27 assume !(1 == ~t5_pc~0); 22736#L473-29 is_transmit5_triggered_~__retres1~5 := 0; 22472#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 22263#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 22264#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 22829#L997-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 22830#L492-27 assume !(1 == ~t6_pc~0); 22793#L492-29 is_transmit6_triggered_~__retres1~6 := 0; 22563#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 22446#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 22447#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 22612#L1005-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 22148#L511-27 assume 1 == ~t7_pc~0; 22106#L512-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 22107#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 22660#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 22270#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 22245#L1013-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22246#L859-3 assume !(1 == ~M_E~0); 22450#L859-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22154#L864-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22155#L869-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22600#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22415#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22092#L884-3 assume !(1 == ~T6_E~0); 22093#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22769#L894-3 assume !(1 == ~E_M~0); 22496#L899-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22239#L904-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22240#L909-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22812#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22672#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22484#L924-3 assume !(1 == ~E_6~0); 22002#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22003#L934-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 22764#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 22089#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 22701#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 22702#L1199 assume !(0 == start_simulation_~tmp~3); 22427#L1199-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 22765#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 22068#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 22705#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 22706#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 22676#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 22662#L1162 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 22265#L1212 assume !(0 != start_simulation_~tmp___0~1); 22266#L1180-3 [2018-11-18 09:04:51,721 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:51,721 INFO L82 PathProgramCache]: Analyzing trace with hash -1443764674, now seen corresponding path program 1 times [2018-11-18 09:04:51,721 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:51,721 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:51,722 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:51,722 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:51,722 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:51,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:51,767 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:51,767 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:51,767 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 09:04:51,767 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 09:04:51,768 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:51,768 INFO L82 PathProgramCache]: Analyzing trace with hash 701627370, now seen corresponding path program 1 times [2018-11-18 09:04:51,768 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:51,768 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:51,768 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:51,768 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:51,769 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:51,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:51,793 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:51,793 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:51,793 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:04:51,793 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:04:51,793 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:04:51,794 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:04:51,794 INFO L87 Difference]: Start difference. First operand 2787 states and 4015 transitions. cyclomatic complexity: 1232 Second operand 3 states. [2018-11-18 09:04:51,887 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:04:51,887 INFO L93 Difference]: Finished difference Result 5208 states and 7458 transitions. [2018-11-18 09:04:51,889 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:04:51,889 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5208 states and 7458 transitions. [2018-11-18 09:04:51,907 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5084 [2018-11-18 09:04:51,929 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5208 states to 5208 states and 7458 transitions. [2018-11-18 09:04:51,933 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5208 [2018-11-18 09:04:51,938 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5208 [2018-11-18 09:04:51,938 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5208 states and 7458 transitions. [2018-11-18 09:04:51,945 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:04:51,945 INFO L705 BuchiCegarLoop]: Abstraction has 5208 states and 7458 transitions. [2018-11-18 09:04:51,949 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5208 states and 7458 transitions. [2018-11-18 09:04:52,002 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5208 to 5196. [2018-11-18 09:04:52,002 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5196 states. [2018-11-18 09:04:52,011 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5196 states to 5196 states and 7446 transitions. [2018-11-18 09:04:52,011 INFO L728 BuchiCegarLoop]: Abstraction has 5196 states and 7446 transitions. [2018-11-18 09:04:52,012 INFO L608 BuchiCegarLoop]: Abstraction has 5196 states and 7446 transitions. [2018-11-18 09:04:52,012 INFO L442 BuchiCegarLoop]: ======== Iteration 13============ [2018-11-18 09:04:52,012 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5196 states and 7446 transitions. [2018-11-18 09:04:52,025 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5072 [2018-11-18 09:04:52,025 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:04:52,025 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:04:52,026 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:52,026 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:52,026 INFO L794 eck$LassoCheckResult]: Stem: 30479#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 30378#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 30379#L1143 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 30343#L531 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30344#L538 assume 1 == ~m_i~0;~m_st~0 := 0; 30827#L538-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30659#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30564#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30345#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30346#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30732#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30552#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 30323#L573-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30324#L771 assume !(0 == ~M_E~0); 30458#L771-2 assume !(0 == ~T1_E~0); 30162#L776-1 assume !(0 == ~T2_E~0); 30163#L781-1 assume !(0 == ~T3_E~0); 30622#L786-1 assume !(0 == ~T4_E~0); 30425#L791-1 assume !(0 == ~T5_E~0); 30098#L796-1 assume !(0 == ~T6_E~0); 30099#L801-1 assume !(0 == ~T7_E~0); 30804#L806-1 assume !(0 == ~E_M~0); 30510#L811-1 assume !(0 == ~E_1~0); 30260#L816-1 assume !(0 == ~E_2~0); 30261#L821-1 assume !(0 == ~E_3~0); 30851#L826-1 assume !(0 == ~E_4~0); 30695#L831-1 assume !(0 == ~E_5~0); 30496#L836-1 assume !(0 == ~E_6~0); 30007#L841-1 assume !(0 == ~E_7~0); 30008#L846-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 30082#L378 assume !(1 == ~m_pc~0); 30056#L378-2 is_master_triggered_~__retres1~0 := 0; 30057#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 30666#L390 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 30712#L957 assume !(0 != activate_threads_~tmp~1); 30883#L957-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 30298#L397 assume !(1 == ~t1_pc~0); 30299#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 30307#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 30716#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 30513#L965 assume !(0 != activate_threads_~tmp___0~0); 30504#L965-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 30505#L416 assume !(1 == ~t2_pc~0); 30403#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 30404#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 30828#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 30028#L973 assume !(0 != activate_threads_~tmp___1~0); 30029#L973-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 30034#L435 assume !(1 == ~t3_pc~0); 30685#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 30124#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 30125#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 30752#L981 assume !(0 != activate_threads_~tmp___2~0); 30741#L981-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 30742#L454 assume !(1 == ~t4_pc~0); 30663#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 30349#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 30076#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 30077#L989 assume !(0 != activate_threads_~tmp___3~0); 30430#L989-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 30432#L473 assume !(1 == ~t5_pc~0); 30872#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 30484#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 30326#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 30327#L997 assume !(0 != activate_threads_~tmp___4~0); 30904#L997-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 30905#L492 assume !(1 == ~t6_pc~0); 30909#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 30605#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 30565#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 30566#L1005 assume !(0 != activate_threads_~tmp___5~0); 30796#L1005-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 29996#L511 assume !(1 == ~t7_pc~0); 29997#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 30156#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 30619#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 30477#L1013 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 30468#L1013-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30469#L859 assume !(1 == ~M_E~0); 30457#L859-2 assume !(1 == ~T1_E~0); 30180#L864-1 assume !(1 == ~T2_E~0); 30181#L869-1 assume !(1 == ~T3_E~0); 30620#L874-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30419#L879-1 assume !(1 == ~T5_E~0); 30094#L884-1 assume !(1 == ~T6_E~0); 30095#L889-1 assume !(1 == ~T7_E~0); 30802#L894-1 assume !(1 == ~E_M~0); 30506#L899-1 assume !(1 == ~E_1~0); 30252#L904-1 assume !(1 == ~E_2~0); 30253#L909-1 assume !(1 == ~E_3~0); 30856#L914-1 assume 1 == ~E_4~0;~E_4~0 := 2; 30698#L919-1 assume !(1 == ~E_5~0); 30503#L924-1 assume !(1 == ~E_6~0); 30037#L929-1 assume !(1 == ~E_7~0); 30038#L934-1 assume { :end_inline_reset_delta_events } true; 30831#L1180-3 [2018-11-18 09:04:52,027 INFO L796 eck$LassoCheckResult]: Loop: 30831#L1180-3 assume true; 34713#L1180-1 assume !false; 34601#L1181 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 34600#L746 assume true; 34599#L638-1 assume !false; 34177#L639 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 34169#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 34168#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 34167#L629 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 34165#L643 assume !(0 != eval_~tmp~0); 34166#L761 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 34892#L531-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 34891#L771-3 assume 0 == ~M_E~0;~M_E~0 := 1; 34890#L771-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 34889#L776-3 assume !(0 == ~T2_E~0); 34888#L781-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 34887#L786-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 34886#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 34885#L796-3 assume !(0 == ~T6_E~0); 34884#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 34883#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 34882#L811-3 assume 0 == ~E_1~0;~E_1~0 := 1; 34881#L816-3 assume !(0 == ~E_2~0); 34880#L821-3 assume 0 == ~E_3~0;~E_3~0 := 1; 34879#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 34878#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 34877#L836-3 assume !(0 == ~E_6~0); 34876#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 34875#L846-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 34874#L378-27 assume 1 == ~m_pc~0; 34872#L379-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 34871#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 34870#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 34869#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 34868#L957-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 34867#L397-27 assume !(1 == ~t1_pc~0); 34866#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 34865#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 34864#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 34863#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 34862#L965-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 34861#L416-27 assume 1 == ~t2_pc~0; 34859#L417-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 34858#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 34857#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 34856#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 34855#L973-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 34854#L435-27 assume !(1 == ~t3_pc~0); 34853#L435-29 is_transmit3_triggered_~__retres1~3 := 0; 34852#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 34851#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 34850#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 34849#L981-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 34848#L454-27 assume 1 == ~t4_pc~0; 34846#L455-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 34845#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 34844#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 34843#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 34842#L989-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 34841#L473-27 assume !(1 == ~t5_pc~0); 34840#L473-29 is_transmit5_triggered_~__retres1~5 := 0; 34839#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 34838#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 34837#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 34836#L997-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 34835#L492-27 assume !(1 == ~t6_pc~0); 34833#L492-29 is_transmit6_triggered_~__retres1~6 := 0; 34832#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 30455#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 30456#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 30633#L1005-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 30152#L511-27 assume 1 == ~t7_pc~0; 30112#L512-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 30113#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 30681#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 30289#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 30264#L1013-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30265#L859-3 assume !(1 == ~M_E~0); 30459#L859-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30160#L864-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30161#L869-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30621#L874-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30424#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30096#L884-3 assume !(1 == ~T6_E~0); 30097#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30803#L894-3 assume !(1 == ~E_M~0); 30509#L899-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30258#L904-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30259#L909-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30857#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30694#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30495#L924-3 assume !(1 == ~E_6~0); 30005#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 30006#L934-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 30798#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 30093#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 30726#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 30727#L1199 assume !(0 == start_simulation_~tmp~3); 30826#L1199-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 34901#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 34900#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 34898#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 34896#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 34716#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 34715#L1162 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 34714#L1212 assume !(0 != start_simulation_~tmp___0~1); 30831#L1180-3 [2018-11-18 09:04:52,027 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:52,027 INFO L82 PathProgramCache]: Analyzing trace with hash -392315585, now seen corresponding path program 1 times [2018-11-18 09:04:52,027 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:52,027 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:52,028 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:52,028 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:52,028 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:52,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:52,064 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:52,064 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:52,064 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 09:04:52,064 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 09:04:52,064 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:52,065 INFO L82 PathProgramCache]: Analyzing trace with hash 701627370, now seen corresponding path program 2 times [2018-11-18 09:04:52,065 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:52,065 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:52,065 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:52,065 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:52,066 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:52,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:52,090 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:52,090 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:52,090 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:04:52,090 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:04:52,090 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:04:52,090 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:04:52,091 INFO L87 Difference]: Start difference. First operand 5196 states and 7446 transitions. cyclomatic complexity: 2258 Second operand 3 states. [2018-11-18 09:04:52,142 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:04:52,142 INFO L93 Difference]: Finished difference Result 5196 states and 7420 transitions. [2018-11-18 09:04:52,143 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:04:52,143 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5196 states and 7420 transitions. [2018-11-18 09:04:52,159 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5072 [2018-11-18 09:04:52,177 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5196 states to 5196 states and 7420 transitions. [2018-11-18 09:04:52,177 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5196 [2018-11-18 09:04:52,181 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5196 [2018-11-18 09:04:52,181 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5196 states and 7420 transitions. [2018-11-18 09:04:52,186 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:04:52,186 INFO L705 BuchiCegarLoop]: Abstraction has 5196 states and 7420 transitions. [2018-11-18 09:04:52,190 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5196 states and 7420 transitions. [2018-11-18 09:04:52,242 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5196 to 5196. [2018-11-18 09:04:52,242 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5196 states. [2018-11-18 09:04:52,251 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5196 states to 5196 states and 7420 transitions. [2018-11-18 09:04:52,251 INFO L728 BuchiCegarLoop]: Abstraction has 5196 states and 7420 transitions. [2018-11-18 09:04:52,251 INFO L608 BuchiCegarLoop]: Abstraction has 5196 states and 7420 transitions. [2018-11-18 09:04:52,251 INFO L442 BuchiCegarLoop]: ======== Iteration 14============ [2018-11-18 09:04:52,251 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5196 states and 7420 transitions. [2018-11-18 09:04:52,264 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5072 [2018-11-18 09:04:52,264 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:04:52,264 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:04:52,266 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:52,266 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:52,266 INFO L794 eck$LassoCheckResult]: Stem: 40868#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 40767#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 40768#L1143 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 40728#L531 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 40729#L538 assume 1 == ~m_i~0;~m_st~0 := 0; 41218#L538-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41048#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40950#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40730#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40731#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 41123#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 40938#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 40709#L573-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40710#L771 assume !(0 == ~M_E~0); 40848#L771-2 assume !(0 == ~T1_E~0); 40557#L776-1 assume !(0 == ~T2_E~0); 40558#L781-1 assume !(0 == ~T3_E~0); 41008#L786-1 assume !(0 == ~T4_E~0); 40815#L791-1 assume !(0 == ~T5_E~0); 40495#L796-1 assume !(0 == ~T6_E~0); 40496#L801-1 assume !(0 == ~T7_E~0); 41197#L806-1 assume !(0 == ~E_M~0); 40897#L811-1 assume !(0 == ~E_1~0); 40646#L816-1 assume !(0 == ~E_2~0); 40647#L821-1 assume !(0 == ~E_3~0); 41241#L826-1 assume !(0 == ~E_4~0); 41088#L831-1 assume !(0 == ~E_5~0); 40885#L836-1 assume !(0 == ~E_6~0); 40405#L841-1 assume !(0 == ~E_7~0); 40406#L846-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 40479#L378 assume !(1 == ~m_pc~0); 40453#L378-2 is_master_triggered_~__retres1~0 := 0; 40454#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 41056#L390 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 41104#L957 assume !(0 != activate_threads_~tmp~1); 41278#L957-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 40684#L397 assume !(1 == ~t1_pc~0); 40685#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 40692#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 41108#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 40900#L965 assume !(0 != activate_threads_~tmp___0~0); 40891#L965-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 40892#L416 assume !(1 == ~t2_pc~0); 40792#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 40793#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 41219#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 40425#L973 assume !(0 != activate_threads_~tmp___1~0); 40426#L973-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 40431#L435 assume !(1 == ~t3_pc~0); 41078#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 40521#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 40522#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 41144#L981 assume !(0 != activate_threads_~tmp___2~0); 41134#L981-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 41135#L454 assume !(1 == ~t4_pc~0); 41052#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 40734#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 40473#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 40474#L989 assume !(0 != activate_threads_~tmp___3~0); 40819#L989-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 40821#L473 assume !(1 == ~t5_pc~0); 41263#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 40874#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 40712#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 40713#L997 assume !(0 != activate_threads_~tmp___4~0); 41302#L997-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 41303#L492 assume !(1 == ~t6_pc~0); 41308#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 40991#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 40951#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 40952#L1005 assume !(0 != activate_threads_~tmp___5~0); 41187#L1005-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 40394#L511 assume !(1 == ~t7_pc~0); 40395#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 40551#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 41005#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 40866#L1013 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 40858#L1013-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40859#L859 assume !(1 == ~M_E~0); 40847#L859-2 assume !(1 == ~T1_E~0); 40572#L864-1 assume !(1 == ~T2_E~0); 40573#L869-1 assume !(1 == ~T3_E~0); 41006#L874-1 assume !(1 == ~T4_E~0); 40807#L879-1 assume !(1 == ~T5_E~0); 40491#L884-1 assume !(1 == ~T6_E~0); 40492#L889-1 assume !(1 == ~T7_E~0); 41195#L894-1 assume !(1 == ~E_M~0); 40893#L899-1 assume !(1 == ~E_1~0); 40640#L904-1 assume !(1 == ~E_2~0); 40641#L909-1 assume !(1 == ~E_3~0); 41246#L914-1 assume 1 == ~E_4~0;~E_4~0 := 2; 41092#L919-1 assume !(1 == ~E_5~0); 40890#L924-1 assume !(1 == ~E_6~0); 40434#L929-1 assume !(1 == ~E_7~0); 40435#L934-1 assume { :end_inline_reset_delta_events } true; 40671#L1180-3 [2018-11-18 09:04:52,266 INFO L796 eck$LassoCheckResult]: Loop: 40671#L1180-3 assume true; 41198#L1180-1 assume !false; 41188#L1181 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 40961#L746 assume true; 40880#L638-1 assume !false; 40855#L639 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 40856#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 40487#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 41132#L629 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 40380#L643 assume !(0 != eval_~tmp~0); 40382#L761 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 45545#L531-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 45543#L771-3 assume 0 == ~M_E~0;~M_E~0 := 1; 45541#L771-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 45539#L776-3 assume !(0 == ~T2_E~0); 45537#L781-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 45536#L786-3 assume !(0 == ~T4_E~0); 45535#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 45533#L796-3 assume !(0 == ~T6_E~0); 45530#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 45528#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 45527#L811-3 assume 0 == ~E_1~0;~E_1~0 := 1; 45526#L816-3 assume !(0 == ~E_2~0); 45525#L821-3 assume 0 == ~E_3~0;~E_3~0 := 1; 45524#L826-3 assume 0 == ~E_4~0;~E_4~0 := 1; 45523#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 45522#L836-3 assume !(0 == ~E_6~0); 45521#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 45520#L846-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 45519#L378-27 assume 1 == ~m_pc~0; 45517#L379-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 45516#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 45515#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 45514#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 45513#L957-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 45512#L397-27 assume !(1 == ~t1_pc~0); 45511#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 45510#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 45509#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 45508#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 45507#L965-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 45505#L416-27 assume 1 == ~t2_pc~0; 45502#L417-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 45500#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 45498#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 45497#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 45496#L973-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 45495#L435-27 assume !(1 == ~t3_pc~0); 45494#L435-29 is_transmit3_triggered_~__retres1~3 := 0; 45493#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 45492#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 45491#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 45490#L981-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 45489#L454-27 assume 1 == ~t4_pc~0; 41013#L455-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 40719#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 40440#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 40441#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 40760#L989-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 40764#L473-27 assume !(1 == ~t5_pc~0); 41183#L473-29 is_transmit5_triggered_~__retres1~5 := 0; 40871#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 40872#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 45429#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 45427#L997-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 45425#L492-27 assume !(1 == ~t6_pc~0); 45422#L492-29 is_transmit6_triggered_~__retres1~6 := 0; 45420#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 45418#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 45416#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 45414#L1005-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 45412#L511-27 assume 1 == ~t7_pc~0; 45409#L512-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 45407#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 45405#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 45402#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 45400#L1013-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45398#L859-3 assume !(1 == ~M_E~0); 45396#L859-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 45394#L864-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 45392#L869-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45390#L874-3 assume !(1 == ~T4_E~0); 45388#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 45386#L884-3 assume !(1 == ~T6_E~0); 45279#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41196#L894-3 assume !(1 == ~E_M~0); 40896#L899-3 assume 1 == ~E_1~0;~E_1~0 := 2; 40644#L904-3 assume 1 == ~E_2~0;~E_2~0 := 2; 40645#L909-3 assume 1 == ~E_3~0;~E_3~0 := 2; 41247#L914-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41087#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 40884#L924-3 assume !(1 == ~E_6~0); 40403#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 40404#L934-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 41222#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 45250#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 45248#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 41217#L1199 assume !(0 == start_simulation_~tmp~3); 40827#L1199-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 41192#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 40469#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 41121#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 41122#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 41093#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 41076#L1162 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 40670#L1212 assume !(0 != start_simulation_~tmp___0~1); 40671#L1180-3 [2018-11-18 09:04:52,266 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:52,267 INFO L82 PathProgramCache]: Analyzing trace with hash -979121599, now seen corresponding path program 1 times [2018-11-18 09:04:52,267 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:52,267 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:52,267 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:52,267 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 09:04:52,267 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:52,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:52,311 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:52,311 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:52,312 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 09:04:52,312 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 09:04:52,312 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:52,312 INFO L82 PathProgramCache]: Analyzing trace with hash -1575728086, now seen corresponding path program 1 times [2018-11-18 09:04:52,312 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:52,312 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:52,313 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:52,313 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:52,313 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:52,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:52,348 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:52,348 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:52,349 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:04:52,349 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:04:52,349 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:04:52,349 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:04:52,349 INFO L87 Difference]: Start difference. First operand 5196 states and 7420 transitions. cyclomatic complexity: 2232 Second operand 3 states. [2018-11-18 09:04:52,417 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:04:52,417 INFO L93 Difference]: Finished difference Result 5196 states and 7329 transitions. [2018-11-18 09:04:52,419 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:04:52,419 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5196 states and 7329 transitions. [2018-11-18 09:04:52,437 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5072 [2018-11-18 09:04:52,454 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5196 states to 5196 states and 7329 transitions. [2018-11-18 09:04:52,454 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5196 [2018-11-18 09:04:52,458 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5196 [2018-11-18 09:04:52,458 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5196 states and 7329 transitions. [2018-11-18 09:04:52,462 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:04:52,463 INFO L705 BuchiCegarLoop]: Abstraction has 5196 states and 7329 transitions. [2018-11-18 09:04:52,466 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5196 states and 7329 transitions. [2018-11-18 09:04:52,512 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5196 to 5196. [2018-11-18 09:04:52,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5196 states. [2018-11-18 09:04:52,519 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5196 states to 5196 states and 7329 transitions. [2018-11-18 09:04:52,519 INFO L728 BuchiCegarLoop]: Abstraction has 5196 states and 7329 transitions. [2018-11-18 09:04:52,519 INFO L608 BuchiCegarLoop]: Abstraction has 5196 states and 7329 transitions. [2018-11-18 09:04:52,519 INFO L442 BuchiCegarLoop]: ======== Iteration 15============ [2018-11-18 09:04:52,519 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5196 states and 7329 transitions. [2018-11-18 09:04:52,533 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5072 [2018-11-18 09:04:52,533 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:04:52,533 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:04:52,534 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:52,534 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:52,534 INFO L794 eck$LassoCheckResult]: Stem: 51261#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 51160#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 51161#L1143 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 51130#L531 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 51131#L538 assume 1 == ~m_i~0;~m_st~0 := 0; 51593#L538-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 51432#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 51340#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 51132#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 51133#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 51502#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 51330#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 51111#L573-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 51112#L771 assume !(0 == ~M_E~0); 51241#L771-2 assume !(0 == ~T1_E~0); 50957#L776-1 assume !(0 == ~T2_E~0); 50958#L781-1 assume !(0 == ~T3_E~0); 51394#L786-1 assume !(0 == ~T4_E~0); 51207#L791-1 assume !(0 == ~T5_E~0); 50894#L796-1 assume !(0 == ~T6_E~0); 50895#L801-1 assume !(0 == ~T7_E~0); 51573#L806-1 assume !(0 == ~E_M~0); 51289#L811-1 assume !(0 == ~E_1~0); 51047#L816-1 assume !(0 == ~E_2~0); 51048#L821-1 assume !(0 == ~E_3~0); 51617#L826-1 assume !(0 == ~E_4~0); 51467#L831-1 assume !(0 == ~E_5~0); 51277#L836-1 assume !(0 == ~E_6~0); 50804#L841-1 assume !(0 == ~E_7~0); 50805#L846-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 50878#L378 assume !(1 == ~m_pc~0); 50852#L378-2 is_master_triggered_~__retres1~0 := 0; 50853#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 51438#L390 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 51483#L957 assume !(0 != activate_threads_~tmp~1); 51646#L957-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 51084#L397 assume !(1 == ~t1_pc~0); 51085#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 51093#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 51487#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 51292#L965 assume !(0 != activate_threads_~tmp___0~0); 51283#L965-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 51284#L416 assume !(1 == ~t2_pc~0); 51185#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 51186#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 51594#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 50824#L973 assume !(0 != activate_threads_~tmp___1~0); 50825#L973-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 50830#L435 assume !(1 == ~t3_pc~0); 51457#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 50923#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 50924#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 51523#L981 assume !(0 != activate_threads_~tmp___2~0); 51513#L981-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 51514#L454 assume !(1 == ~t4_pc~0); 51435#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 51136#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 50872#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 50873#L989 assume !(0 != activate_threads_~tmp___3~0); 51213#L989-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 51215#L473 assume !(1 == ~t5_pc~0); 51638#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 51266#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 51114#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 51115#L997 assume !(0 != activate_threads_~tmp___4~0); 51668#L997-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 51669#L492 assume !(1 == ~t6_pc~0); 51673#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 51378#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 51341#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 51342#L1005 assume !(0 != activate_threads_~tmp___5~0); 51565#L1005-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 50793#L511 assume !(1 == ~t7_pc~0); 50794#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 50950#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 51391#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 51259#L1013 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 51251#L1013-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51252#L859 assume !(1 == ~M_E~0); 51240#L859-2 assume !(1 == ~T1_E~0); 50971#L864-1 assume !(1 == ~T2_E~0); 50972#L869-1 assume !(1 == ~T3_E~0); 51392#L874-1 assume !(1 == ~T4_E~0); 51201#L879-1 assume !(1 == ~T5_E~0); 50890#L884-1 assume !(1 == ~T6_E~0); 50891#L889-1 assume !(1 == ~T7_E~0); 51571#L894-1 assume !(1 == ~E_M~0); 51285#L899-1 assume !(1 == ~E_1~0); 51040#L904-1 assume !(1 == ~E_2~0); 51041#L909-1 assume !(1 == ~E_3~0); 51623#L914-1 assume !(1 == ~E_4~0); 51470#L919-1 assume !(1 == ~E_5~0); 51282#L924-1 assume !(1 == ~E_6~0); 50833#L929-1 assume !(1 == ~E_7~0); 50834#L934-1 assume { :end_inline_reset_delta_events } true; 51598#L1180-3 [2018-11-18 09:04:52,535 INFO L796 eck$LassoCheckResult]: Loop: 51598#L1180-3 assume true; 54208#L1180-1 assume !false; 53329#L1181 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 53327#L746 assume true; 53325#L638-1 assume !false; 53323#L639 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 53271#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 53265#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 53257#L629 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 53239#L643 assume !(0 != eval_~tmp~0); 53240#L761 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 55899#L531-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 55898#L771-3 assume 0 == ~M_E~0;~M_E~0 := 1; 55897#L771-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 55896#L776-3 assume !(0 == ~T2_E~0); 55893#L781-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 55891#L786-3 assume !(0 == ~T4_E~0); 55889#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 55887#L796-3 assume !(0 == ~T6_E~0); 55885#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 55883#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 55881#L811-3 assume 0 == ~E_1~0;~E_1~0 := 1; 55879#L816-3 assume !(0 == ~E_2~0); 55877#L821-3 assume 0 == ~E_3~0;~E_3~0 := 1; 55875#L826-3 assume !(0 == ~E_4~0); 55873#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 55871#L836-3 assume !(0 == ~E_6~0); 55868#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 55866#L846-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 55864#L378-27 assume 1 == ~m_pc~0; 55861#L379-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 55859#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 55857#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 55855#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 55852#L957-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 55850#L397-27 assume !(1 == ~t1_pc~0); 55848#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 55846#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 55844#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 55842#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 55841#L965-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 55840#L416-27 assume 1 == ~t2_pc~0; 55838#L417-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 55836#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 55834#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 55832#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 55768#L973-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 55767#L435-27 assume !(1 == ~t3_pc~0); 55766#L435-29 is_transmit3_triggered_~__retres1~3 := 0; 54392#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 54391#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 54389#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 54387#L981-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 54385#L454-27 assume !(1 == ~t4_pc~0); 54383#L454-29 is_transmit4_triggered_~__retres1~4 := 0; 54382#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 54381#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 54378#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 54376#L989-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 54374#L473-27 assume !(1 == ~t5_pc~0); 54372#L473-29 is_transmit5_triggered_~__retres1~5 := 0; 54371#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 54369#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 54366#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 54364#L997-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 54362#L492-27 assume !(1 == ~t6_pc~0); 54359#L492-29 is_transmit6_triggered_~__retres1~6 := 0; 54357#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 54355#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 54352#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 54350#L1005-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 54348#L511-27 assume 1 == ~t7_pc~0; 54345#L512-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 54343#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 54340#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 54338#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 54336#L1013-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54334#L859-3 assume !(1 == ~M_E~0); 54332#L859-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 54330#L864-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 54328#L869-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54326#L874-3 assume !(1 == ~T4_E~0); 54324#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 54322#L884-3 assume !(1 == ~T6_E~0); 54320#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 54318#L894-3 assume !(1 == ~E_M~0); 54315#L899-3 assume 1 == ~E_1~0;~E_1~0 := 2; 54313#L904-3 assume 1 == ~E_2~0;~E_2~0 := 2; 54311#L909-3 assume 1 == ~E_3~0;~E_3~0 := 2; 54309#L914-3 assume !(1 == ~E_4~0); 54307#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 54305#L924-3 assume !(1 == ~E_6~0); 54303#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 54300#L934-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 54284#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 54282#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 54280#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 54277#L1199 assume !(0 == start_simulation_~tmp~3); 54274#L1199-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 54224#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 54222#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 54220#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 54217#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 54215#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 54213#L1162 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 54211#L1212 assume !(0 != start_simulation_~tmp___0~1); 51598#L1180-3 [2018-11-18 09:04:52,535 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:52,535 INFO L82 PathProgramCache]: Analyzing trace with hash -977274557, now seen corresponding path program 1 times [2018-11-18 09:04:52,535 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:52,535 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:52,536 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:52,536 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:52,536 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:52,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:52,623 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:52,623 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:52,623 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 09:04:52,624 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 09:04:52,624 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:52,624 INFO L82 PathProgramCache]: Analyzing trace with hash -1871096533, now seen corresponding path program 1 times [2018-11-18 09:04:52,624 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:52,624 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:52,625 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:52,625 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:52,625 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:52,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:52,664 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:52,665 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:52,665 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:04:52,665 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:04:52,665 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 09:04:52,665 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 09:04:52,666 INFO L87 Difference]: Start difference. First operand 5196 states and 7329 transitions. cyclomatic complexity: 2141 Second operand 5 states. [2018-11-18 09:04:53,034 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:04:53,034 INFO L93 Difference]: Finished difference Result 11579 states and 16404 transitions. [2018-11-18 09:04:53,035 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 09:04:53,035 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11579 states and 16404 transitions. [2018-11-18 09:04:53,057 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11368 [2018-11-18 09:04:53,077 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11579 states to 11579 states and 16404 transitions. [2018-11-18 09:04:53,077 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11579 [2018-11-18 09:04:53,082 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11579 [2018-11-18 09:04:53,082 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11579 states and 16404 transitions. [2018-11-18 09:04:53,089 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:04:53,089 INFO L705 BuchiCegarLoop]: Abstraction has 11579 states and 16404 transitions. [2018-11-18 09:04:53,094 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11579 states and 16404 transitions. [2018-11-18 09:04:53,135 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11579 to 5403. [2018-11-18 09:04:53,135 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5403 states. [2018-11-18 09:04:53,140 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5403 states to 5403 states and 7536 transitions. [2018-11-18 09:04:53,140 INFO L728 BuchiCegarLoop]: Abstraction has 5403 states and 7536 transitions. [2018-11-18 09:04:53,140 INFO L608 BuchiCegarLoop]: Abstraction has 5403 states and 7536 transitions. [2018-11-18 09:04:53,140 INFO L442 BuchiCegarLoop]: ======== Iteration 16============ [2018-11-18 09:04:53,140 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5403 states and 7536 transitions. [2018-11-18 09:04:53,149 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5276 [2018-11-18 09:04:53,149 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:04:53,149 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:04:53,150 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:53,150 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:53,150 INFO L794 eck$LassoCheckResult]: Stem: 68083#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 67983#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 67984#L1143 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 67936#L531 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 67937#L538 assume 1 == ~m_i~0;~m_st~0 := 0; 68444#L538-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 68260#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 68163#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 67938#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 67939#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 68351#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 68153#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 67916#L573-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 67917#L771 assume !(0 == ~M_E~0); 68063#L771-2 assume !(0 == ~T1_E~0); 67751#L776-1 assume !(0 == ~T2_E~0); 67752#L781-1 assume !(0 == ~T3_E~0); 68218#L786-1 assume !(0 == ~T4_E~0); 68031#L791-1 assume !(0 == ~T5_E~0); 67682#L796-1 assume !(0 == ~T6_E~0); 67683#L801-1 assume !(0 == ~T7_E~0); 68423#L806-1 assume !(0 == ~E_M~0); 68112#L811-1 assume !(0 == ~E_1~0); 67854#L816-1 assume !(0 == ~E_2~0); 67855#L821-1 assume !(0 == ~E_3~0); 68467#L826-1 assume !(0 == ~E_4~0); 68308#L831-1 assume !(0 == ~E_5~0); 68100#L836-1 assume !(0 == ~E_6~0); 67592#L841-1 assume !(0 == ~E_7~0); 67593#L846-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 67666#L378 assume !(1 == ~m_pc~0); 67640#L378-2 is_master_triggered_~__retres1~0 := 0; 67641#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 68269#L390 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 68328#L957 assume !(0 != activate_threads_~tmp~1); 68499#L957-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 67893#L397 assume !(1 == ~t1_pc~0); 67894#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 67901#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 68335#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 68115#L965 assume !(0 != activate_threads_~tmp___0~0); 68106#L965-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 68107#L416 assume !(1 == ~t2_pc~0); 68009#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 68010#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 68445#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 67612#L973 assume !(0 != activate_threads_~tmp___1~0); 67613#L973-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 67618#L435 assume !(1 == ~t3_pc~0); 68293#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 67708#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 67709#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 68372#L981 assume !(0 != activate_threads_~tmp___2~0); 68362#L981-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 68363#L454 assume !(1 == ~t4_pc~0); 68264#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 67942#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 67660#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 67661#L989 assume !(0 != activate_threads_~tmp___3~0); 68035#L989-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 68037#L473 assume !(1 == ~t5_pc~0); 68492#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 68088#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 67919#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 67920#L997 assume !(0 != activate_threads_~tmp___4~0); 68521#L997-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 68522#L492 assume !(1 == ~t6_pc~0); 68527#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 68202#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 68164#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 68165#L1005 assume !(0 != activate_threads_~tmp___5~0); 68414#L1005-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 67581#L511 assume !(1 == ~t7_pc~0); 67582#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 67808#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 68215#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 68081#L1013 assume !(0 != activate_threads_~tmp___6~0); 68073#L1013-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68074#L859 assume !(1 == ~M_E~0); 68062#L859-2 assume !(1 == ~T1_E~0); 67771#L864-1 assume !(1 == ~T2_E~0); 67772#L869-1 assume !(1 == ~T3_E~0); 68216#L874-1 assume !(1 == ~T4_E~0); 68025#L879-1 assume !(1 == ~T5_E~0); 67678#L884-1 assume !(1 == ~T6_E~0); 67679#L889-1 assume !(1 == ~T7_E~0); 68421#L894-1 assume !(1 == ~E_M~0); 68108#L899-1 assume !(1 == ~E_1~0); 67848#L904-1 assume !(1 == ~E_2~0); 67849#L909-1 assume !(1 == ~E_3~0); 68475#L914-1 assume !(1 == ~E_4~0); 68311#L919-1 assume !(1 == ~E_5~0); 68105#L924-1 assume !(1 == ~E_6~0); 67621#L929-1 assume !(1 == ~E_7~0); 67622#L934-1 assume { :end_inline_reset_delta_events } true; 67880#L1180-3 [2018-11-18 09:04:53,151 INFO L796 eck$LassoCheckResult]: Loop: 67880#L1180-3 assume true; 68424#L1180-1 assume !false; 68415#L1181 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 67756#L746 assume true; 68095#L638-1 assume !false; 68070#L639 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 68071#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 67674#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 68360#L629 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 67567#L643 assume !(0 != eval_~tmp~0); 67569#L761 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 72867#L531-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 72865#L771-3 assume 0 == ~M_E~0;~M_E~0 := 1; 72863#L771-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 72860#L776-3 assume !(0 == ~T2_E~0); 72858#L781-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 72856#L786-3 assume !(0 == ~T4_E~0); 72849#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 72835#L796-3 assume !(0 == ~T6_E~0); 72834#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 72833#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 72832#L811-3 assume 0 == ~E_1~0;~E_1~0 := 1; 72831#L816-3 assume !(0 == ~E_2~0); 72830#L821-3 assume 0 == ~E_3~0;~E_3~0 := 1; 72829#L826-3 assume !(0 == ~E_4~0); 72828#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 72826#L836-3 assume !(0 == ~E_6~0); 72818#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 72799#L846-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 72795#L378-27 assume 1 == ~m_pc~0; 72789#L379-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 72773#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 68314#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 68315#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 68484#L957-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 67832#L397-27 assume !(1 == ~t1_pc~0); 67833#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 67834#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 68392#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 68183#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 68175#L965-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 68023#L416-27 assume 1 == ~t2_pc~0; 67973#L417-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 67974#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 68452#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 72733#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 72731#L973-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 72730#L435-27 assume !(1 == ~t3_pc~0); 68155#L435-29 is_transmit3_triggered_~__retres1~3 := 0; 67704#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 67705#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 68432#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 68425#L981-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 68276#L454-27 assume !(1 == ~t4_pc~0); 68225#L454-29 is_transmit4_triggered_~__retres1~4 := 0; 67926#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 67627#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 67628#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 67976#L989-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 67980#L473-27 assume !(1 == ~t5_pc~0); 68408#L473-29 is_transmit5_triggered_~__retres1~5 := 0; 72955#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 72954#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 72953#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 72952#L997-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 72951#L492-27 assume !(1 == ~t6_pc~0); 68534#L492-29 is_transmit6_triggered_~__retres1~6 := 0; 68179#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 68060#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 68061#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 72947#L1005-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 67736#L511-27 assume 1 == ~t7_pc~0; 67737#L512-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 72945#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 72943#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 72941#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 72940#L1013-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 72939#L859-3 assume !(1 == ~M_E~0); 72938#L859-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 72937#L864-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 72936#L869-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 72935#L874-3 assume !(1 == ~T4_E~0); 72934#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 72933#L884-3 assume !(1 == ~T6_E~0); 72932#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 72931#L894-3 assume !(1 == ~E_M~0); 72930#L899-3 assume 1 == ~E_1~0;~E_1~0 := 2; 72929#L904-3 assume 1 == ~E_2~0;~E_2~0 := 2; 72928#L909-3 assume 1 == ~E_3~0;~E_3~0 := 2; 72927#L914-3 assume !(1 == ~E_4~0); 72926#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 72925#L924-3 assume !(1 == ~E_6~0); 72924#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 72923#L934-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 72898#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 72897#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 72850#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 72847#L1199 assume !(0 == start_simulation_~tmp~3); 72845#L1199-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 72837#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 72647#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 68349#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 68350#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 68312#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 68291#L1162 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 67879#L1212 assume !(0 != start_simulation_~tmp___0~1); 67880#L1180-3 [2018-11-18 09:04:53,151 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:53,151 INFO L82 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 1 times [2018-11-18 09:04:53,151 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:53,151 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:53,152 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:53,152 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:53,152 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:53,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:04:53,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:04:53,190 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:53,191 INFO L82 PathProgramCache]: Analyzing trace with hash -1871096533, now seen corresponding path program 2 times [2018-11-18 09:04:53,191 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:53,191 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:53,191 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:53,192 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:53,192 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:53,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:53,221 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:53,221 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:53,221 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:04:53,221 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:04:53,222 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:04:53,222 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:04:53,222 INFO L87 Difference]: Start difference. First operand 5403 states and 7536 transitions. cyclomatic complexity: 2141 Second operand 3 states. [2018-11-18 09:04:53,258 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:04:53,259 INFO L93 Difference]: Finished difference Result 6072 states and 8464 transitions. [2018-11-18 09:04:53,260 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:04:53,260 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6072 states and 8464 transitions. [2018-11-18 09:04:53,272 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5872 [2018-11-18 09:04:53,280 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6072 states to 6072 states and 8464 transitions. [2018-11-18 09:04:53,281 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6072 [2018-11-18 09:04:53,284 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6072 [2018-11-18 09:04:53,284 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6072 states and 8464 transitions. [2018-11-18 09:04:53,287 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:04:53,287 INFO L705 BuchiCegarLoop]: Abstraction has 6072 states and 8464 transitions. [2018-11-18 09:04:53,291 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6072 states and 8464 transitions. [2018-11-18 09:04:53,321 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6072 to 6072. [2018-11-18 09:04:53,321 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6072 states. [2018-11-18 09:04:53,326 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6072 states to 6072 states and 8464 transitions. [2018-11-18 09:04:53,326 INFO L728 BuchiCegarLoop]: Abstraction has 6072 states and 8464 transitions. [2018-11-18 09:04:53,326 INFO L608 BuchiCegarLoop]: Abstraction has 6072 states and 8464 transitions. [2018-11-18 09:04:53,326 INFO L442 BuchiCegarLoop]: ======== Iteration 17============ [2018-11-18 09:04:53,327 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6072 states and 8464 transitions. [2018-11-18 09:04:53,336 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5872 [2018-11-18 09:04:53,336 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:04:53,336 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:04:53,337 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:53,337 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:53,338 INFO L794 eck$LassoCheckResult]: Stem: 79561#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 79453#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 79454#L1143 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 79411#L531 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 79412#L538 assume 1 == ~m_i~0;~m_st~0 := 0; 79924#L538-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 79743#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 79642#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 79413#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 79414#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 79826#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 79628#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 79392#L573-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 79393#L771 assume 0 == ~M_E~0;~M_E~0 := 1; 79536#L771-2 assume !(0 == ~T1_E~0); 79544#L776-1 assume !(0 == ~T2_E~0); 79979#L781-1 assume !(0 == ~T3_E~0); 79701#L786-1 assume !(0 == ~T4_E~0); 79702#L791-1 assume !(0 == ~T5_E~0); 80067#L796-1 assume !(0 == ~T6_E~0); 80066#L801-1 assume !(0 == ~T7_E~0); 79904#L806-1 assume !(0 == ~E_M~0); 79905#L811-1 assume !(0 == ~E_1~0); 79330#L816-1 assume !(0 == ~E_2~0); 79331#L821-1 assume !(0 == ~E_3~0); 80003#L826-1 assume !(0 == ~E_4~0); 79786#L831-1 assume !(0 == ~E_5~0); 79787#L836-1 assume !(0 == ~E_6~0); 79078#L841-1 assume !(0 == ~E_7~0); 79079#L846-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 80064#L378 assume !(1 == ~m_pc~0); 79121#L378-2 is_master_triggered_~__retres1~0 := 0; 79122#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 79751#L390 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 79980#L957 assume !(0 != activate_threads_~tmp~1); 79981#L957-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 79368#L397 assume !(1 == ~t1_pc~0); 79369#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 79377#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 79810#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 79811#L965 assume !(0 != activate_threads_~tmp___0~0); 79586#L965-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 79587#L416 assume !(1 == ~t2_pc~0); 79478#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 79479#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 80020#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 80060#L973 assume !(0 != activate_threads_~tmp___1~0); 80059#L973-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 79771#L435 assume !(1 == ~t3_pc~0); 79772#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 79193#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 79194#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 80002#L981 assume !(0 != activate_threads_~tmp___2~0); 79836#L981-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 79837#L454 assume !(1 == ~t4_pc~0); 79895#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 79417#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 79141#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 79142#L989 assume !(0 != activate_threads_~tmp___3~0); 79509#L989-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 79510#L473 assume !(1 == ~t5_pc~0); 79968#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 79970#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 80050#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 80049#L997 assume !(0 != activate_threads_~tmp___4~0); 80009#L997-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 80010#L492 assume !(1 == ~t6_pc~0); 80015#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 79684#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 79643#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 79644#L1005 assume !(0 != activate_threads_~tmp___5~0); 80033#L1005-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 80032#L511 assume !(1 == ~t7_pc~0); 80031#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 80055#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 80053#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 79559#L1013 assume !(0 != activate_threads_~tmp___6~0); 79550#L1013-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 79551#L859 assume 1 == ~M_E~0;~M_E~0 := 2; 79535#L859-2 assume !(1 == ~T1_E~0); 79249#L864-1 assume !(1 == ~T2_E~0); 79250#L869-1 assume !(1 == ~T3_E~0); 79699#L874-1 assume !(1 == ~T4_E~0); 79496#L879-1 assume !(1 == ~T5_E~0); 79160#L884-1 assume !(1 == ~T6_E~0); 79161#L889-1 assume !(1 == ~T7_E~0); 79901#L894-1 assume !(1 == ~E_M~0); 79590#L899-1 assume !(1 == ~E_1~0); 79323#L904-1 assume !(1 == ~E_2~0); 79324#L909-1 assume !(1 == ~E_3~0); 79954#L914-1 assume !(1 == ~E_4~0); 79790#L919-1 assume !(1 == ~E_5~0); 79585#L924-1 assume !(1 == ~E_6~0); 79102#L929-1 assume !(1 == ~E_7~0); 79103#L934-1 assume { :end_inline_reset_delta_events } true; 79929#L1180-3 [2018-11-18 09:04:53,338 INFO L796 eck$LassoCheckResult]: Loop: 79929#L1180-3 assume true; 81251#L1180-1 assume !false; 81238#L1181 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 81236#L746 assume true; 81234#L638-1 assume !false; 81232#L639 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 81094#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 79885#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 79834#L629 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 79050#L643 assume !(0 != eval_~tmp~0); 79052#L761 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 83590#L531-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 83588#L771-3 assume 0 == ~M_E~0;~M_E~0 := 1; 83587#L771-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 83585#L776-3 assume !(0 == ~T2_E~0); 83583#L781-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 83581#L786-3 assume !(0 == ~T4_E~0); 83579#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 83577#L796-3 assume !(0 == ~T6_E~0); 83575#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 83573#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 83571#L811-3 assume 0 == ~E_1~0;~E_1~0 := 1; 82715#L816-3 assume !(0 == ~E_2~0); 82714#L821-3 assume 0 == ~E_3~0;~E_3~0 := 1; 82712#L826-3 assume !(0 == ~E_4~0); 82709#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 82707#L836-3 assume !(0 == ~E_6~0); 82705#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 82703#L846-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 82701#L378-27 assume 1 == ~m_pc~0; 82697#L379-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 82695#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 82693#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 82691#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 82689#L957-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 82687#L397-27 assume !(1 == ~t1_pc~0); 82684#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 82682#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 82680#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 82678#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 82676#L965-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 82674#L416-27 assume !(1 == ~t2_pc~0); 82673#L416-29 is_transmit2_triggered_~__retres1~2 := 0; 82670#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 82668#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 82666#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 82664#L973-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 82662#L435-27 assume !(1 == ~t3_pc~0); 82661#L435-29 is_transmit3_triggered_~__retres1~3 := 0; 82658#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 82656#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 82654#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 82652#L981-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 82650#L454-27 assume !(1 == ~t4_pc~0); 82647#L454-29 is_transmit4_triggered_~__retres1~4 := 0; 82645#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 82407#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 82405#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 82403#L989-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 82401#L473-27 assume !(1 == ~t5_pc~0); 82399#L473-29 is_transmit5_triggered_~__retres1~5 := 0; 82398#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 82397#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 82394#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 82392#L997-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 81933#L492-27 assume !(1 == ~t6_pc~0); 81930#L492-29 is_transmit6_triggered_~__retres1~6 := 0; 81928#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 81926#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 81924#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 81922#L1005-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 81918#L511-27 assume !(1 == ~t7_pc~0); 81914#L511-29 is_transmit7_triggered_~__retres1~7 := 0; 81912#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 81910#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 81907#L1013-27 assume !(0 != activate_threads_~tmp___6~0); 81904#L1013-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 81903#L859-3 assume 1 == ~M_E~0;~M_E~0 := 2; 81901#L859-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 81900#L864-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 81898#L869-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 81896#L874-3 assume !(1 == ~T4_E~0); 81895#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 81894#L884-3 assume !(1 == ~T6_E~0); 81893#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 81891#L894-3 assume !(1 == ~E_M~0); 81889#L899-3 assume 1 == ~E_1~0;~E_1~0 := 2; 81888#L904-3 assume 1 == ~E_2~0;~E_2~0 := 2; 81705#L909-3 assume 1 == ~E_3~0;~E_3~0 := 2; 81703#L914-3 assume !(1 == ~E_4~0); 81701#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 81700#L924-3 assume !(1 == ~E_6~0); 81577#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 81575#L934-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 81407#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 81406#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 81405#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 81403#L1199 assume !(0 == start_simulation_~tmp~3); 81401#L1199-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 81268#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 81266#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 81264#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 81262#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 81259#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 81257#L1162 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 81254#L1212 assume !(0 != start_simulation_~tmp___0~1); 79929#L1180-3 [2018-11-18 09:04:53,338 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:53,338 INFO L82 PathProgramCache]: Analyzing trace with hash 1650338949, now seen corresponding path program 1 times [2018-11-18 09:04:53,338 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:53,338 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:53,339 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:53,339 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 09:04:53,339 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:53,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:53,367 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:53,367 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:53,368 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 09:04:53,368 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 09:04:53,368 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:53,368 INFO L82 PathProgramCache]: Analyzing trace with hash -1126608147, now seen corresponding path program 1 times [2018-11-18 09:04:53,368 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:53,368 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:53,369 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:53,369 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:53,369 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:53,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:53,403 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:53,403 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:53,403 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:04:53,403 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:04:53,403 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:04:53,403 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:04:53,404 INFO L87 Difference]: Start difference. First operand 6072 states and 8464 transitions. cyclomatic complexity: 2400 Second operand 3 states. [2018-11-18 09:04:53,435 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:04:53,435 INFO L93 Difference]: Finished difference Result 5403 states and 7510 transitions. [2018-11-18 09:04:53,436 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:04:53,436 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5403 states and 7510 transitions. [2018-11-18 09:04:53,446 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5276 [2018-11-18 09:04:53,454 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5403 states to 5403 states and 7510 transitions. [2018-11-18 09:04:53,454 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5403 [2018-11-18 09:04:53,457 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5403 [2018-11-18 09:04:53,457 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5403 states and 7510 transitions. [2018-11-18 09:04:53,460 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:04:53,460 INFO L705 BuchiCegarLoop]: Abstraction has 5403 states and 7510 transitions. [2018-11-18 09:04:53,464 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5403 states and 7510 transitions. [2018-11-18 09:04:53,489 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5403 to 5403. [2018-11-18 09:04:53,489 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5403 states. [2018-11-18 09:04:53,494 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5403 states to 5403 states and 7510 transitions. [2018-11-18 09:04:53,494 INFO L728 BuchiCegarLoop]: Abstraction has 5403 states and 7510 transitions. [2018-11-18 09:04:53,494 INFO L608 BuchiCegarLoop]: Abstraction has 5403 states and 7510 transitions. [2018-11-18 09:04:53,494 INFO L442 BuchiCegarLoop]: ======== Iteration 18============ [2018-11-18 09:04:53,494 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5403 states and 7510 transitions. [2018-11-18 09:04:53,503 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5276 [2018-11-18 09:04:53,503 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:04:53,503 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:04:53,504 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:53,504 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:53,504 INFO L794 eck$LassoCheckResult]: Stem: 91027#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 90927#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 90928#L1143 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 90885#L531 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 90886#L538 assume 1 == ~m_i~0;~m_st~0 := 0; 91361#L538-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 91196#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 91105#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 90887#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 90888#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 91269#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 91097#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 90866#L573-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 90867#L771 assume !(0 == ~M_E~0); 91007#L771-2 assume !(0 == ~T1_E~0); 90710#L776-1 assume !(0 == ~T2_E~0); 90711#L781-1 assume !(0 == ~T3_E~0); 91158#L786-1 assume !(0 == ~T4_E~0); 90975#L791-1 assume !(0 == ~T5_E~0); 90645#L796-1 assume !(0 == ~T6_E~0); 90646#L801-1 assume !(0 == ~T7_E~0); 91342#L806-1 assume !(0 == ~E_M~0); 91056#L811-1 assume !(0 == ~E_1~0); 90806#L816-1 assume !(0 == ~E_2~0); 90807#L821-1 assume !(0 == ~E_3~0); 91384#L826-1 assume !(0 == ~E_4~0); 91234#L831-1 assume !(0 == ~E_5~0); 91044#L836-1 assume !(0 == ~E_6~0); 90555#L841-1 assume !(0 == ~E_7~0); 90556#L846-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 90629#L378 assume !(1 == ~m_pc~0); 90603#L378-2 is_master_triggered_~__retres1~0 := 0; 90604#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 91203#L390 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 91250#L957 assume !(0 != activate_threads_~tmp~1); 91416#L957-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 90843#L397 assume !(1 == ~t1_pc~0); 90844#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 90851#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 91254#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 91059#L965 assume !(0 != activate_threads_~tmp___0~0); 91050#L965-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 91051#L416 assume !(1 == ~t2_pc~0); 90952#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 90953#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 91362#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 90575#L973 assume !(0 != activate_threads_~tmp___1~0); 90576#L973-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 90581#L435 assume !(1 == ~t3_pc~0); 91223#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 90671#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 90672#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 91290#L981 assume !(0 != activate_threads_~tmp___2~0); 91280#L981-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 91281#L454 assume !(1 == ~t4_pc~0); 91200#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 90891#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 90623#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 90624#L989 assume !(0 != activate_threads_~tmp___3~0); 90979#L989-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 90981#L473 assume !(1 == ~t5_pc~0); 91408#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 91032#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 90869#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 90870#L997 assume !(0 != activate_threads_~tmp___4~0); 91439#L997-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 91440#L492 assume !(1 == ~t6_pc~0); 91444#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 91142#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 91106#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 91107#L1005 assume !(0 != activate_threads_~tmp___5~0); 91333#L1005-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 90544#L511 assume !(1 == ~t7_pc~0); 90545#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 90757#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 91454#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 91025#L1013 assume !(0 != activate_threads_~tmp___6~0); 91017#L1013-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 91018#L859 assume !(1 == ~M_E~0); 91006#L859-2 assume !(1 == ~T1_E~0); 90728#L864-1 assume !(1 == ~T2_E~0); 90729#L869-1 assume !(1 == ~T3_E~0); 91156#L874-1 assume !(1 == ~T4_E~0); 90969#L879-1 assume !(1 == ~T5_E~0); 90641#L884-1 assume !(1 == ~T6_E~0); 90642#L889-1 assume !(1 == ~T7_E~0); 91340#L894-1 assume !(1 == ~E_M~0); 91052#L899-1 assume !(1 == ~E_1~0); 90799#L904-1 assume !(1 == ~E_2~0); 90800#L909-1 assume !(1 == ~E_3~0); 91390#L914-1 assume !(1 == ~E_4~0); 91237#L919-1 assume !(1 == ~E_5~0); 91049#L924-1 assume !(1 == ~E_6~0); 90584#L929-1 assume !(1 == ~E_7~0); 90585#L934-1 assume { :end_inline_reset_delta_events } true; 91366#L1180-3 [2018-11-18 09:04:53,505 INFO L796 eck$LassoCheckResult]: Loop: 91366#L1180-3 assume true; 95575#L1180-1 assume !false; 95543#L1181 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 95541#L746 assume true; 95539#L638-1 assume !false; 95530#L639 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 95471#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 95423#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 91278#L629 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 90530#L643 assume !(0 != eval_~tmp~0); 90532#L761 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 95927#L531-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 95926#L771-3 assume !(0 == ~M_E~0); 95925#L771-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 95924#L776-3 assume !(0 == ~T2_E~0); 95923#L781-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 95922#L786-3 assume !(0 == ~T4_E~0); 95921#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 95920#L796-3 assume !(0 == ~T6_E~0); 95913#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 95912#L806-3 assume 0 == ~E_M~0;~E_M~0 := 1; 95911#L811-3 assume 0 == ~E_1~0;~E_1~0 := 1; 95910#L816-3 assume !(0 == ~E_2~0); 95908#L821-3 assume 0 == ~E_3~0;~E_3~0 := 1; 95905#L826-3 assume !(0 == ~E_4~0); 91235#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 91045#L836-3 assume !(0 == ~E_6~0); 90564#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 90565#L846-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 91365#L378-27 assume !(1 == ~m_pc~0); 95856#L378-29 is_master_triggered_~__retres1~0 := 0; 95854#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 95853#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 91398#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 91399#L957-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 90781#L397-27 assume !(1 == ~t1_pc~0); 90782#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 90783#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 91312#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 91126#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 91118#L965-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 90967#L416-27 assume 1 == ~t2_pc~0; 90917#L417-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 90918#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 91351#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 90735#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 90736#L973-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 90743#L435-27 assume !(1 == ~t3_pc~0); 91095#L435-29 is_transmit3_triggered_~__retres1~3 := 0; 90667#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 90668#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 91349#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 91344#L981-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 91210#L454-27 assume !(1 == ~t4_pc~0); 91164#L454-29 is_transmit4_triggered_~__retres1~4 := 0; 90876#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 90590#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 90591#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 90920#L989-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 90924#L473-27 assume !(1 == ~t5_pc~0); 91329#L473-29 is_transmit5_triggered_~__retres1~5 := 0; 91030#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 90827#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 90828#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 91418#L997-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 91419#L492-27 assume !(1 == ~t6_pc~0); 91368#L492-29 is_transmit6_triggered_~__retres1~6 := 0; 91122#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 91004#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 91005#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 91169#L1005-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 90699#L511-27 assume 1 == ~t7_pc~0; 90659#L512-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 90660#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 95890#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 95888#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 90809#L1013-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 90810#L859-3 assume !(1 == ~M_E~0); 91008#L859-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 90708#L864-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 90709#L869-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 91157#L874-3 assume !(1 == ~T4_E~0); 90974#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 90643#L884-3 assume !(1 == ~T6_E~0); 90644#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 91341#L894-3 assume !(1 == ~E_M~0); 91055#L899-3 assume 1 == ~E_1~0;~E_1~0 := 2; 90804#L904-3 assume 1 == ~E_2~0;~E_2~0 := 2; 90805#L909-3 assume 1 == ~E_3~0;~E_3~0 := 2; 91391#L914-3 assume !(1 == ~E_4~0); 91233#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 91043#L924-3 assume !(1 == ~E_6~0); 90553#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 90554#L934-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 91335#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 90640#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 91263#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 91264#L1199 assume !(0 == start_simulation_~tmp~3); 91360#L1199-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 95620#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 95618#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 95607#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 95599#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 95591#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 95583#L1162 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 95580#L1212 assume !(0 != start_simulation_~tmp___0~1); 91366#L1180-3 [2018-11-18 09:04:53,505 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:53,505 INFO L82 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 2 times [2018-11-18 09:04:53,505 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:53,505 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:53,506 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:53,506 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:53,506 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:53,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:04:53,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:04:53,536 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:53,536 INFO L82 PathProgramCache]: Analyzing trace with hash -1037417942, now seen corresponding path program 1 times [2018-11-18 09:04:53,536 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:53,536 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:53,536 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:53,537 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 09:04:53,537 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:53,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:53,577 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:53,577 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:53,577 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:04:53,578 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:04:53,578 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:04:53,578 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:04:53,578 INFO L87 Difference]: Start difference. First operand 5403 states and 7510 transitions. cyclomatic complexity: 2115 Second operand 3 states. [2018-11-18 09:04:53,650 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:04:53,650 INFO L93 Difference]: Finished difference Result 9916 states and 13640 transitions. [2018-11-18 09:04:53,652 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:04:53,652 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9916 states and 13640 transitions. [2018-11-18 09:04:53,673 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9692 [2018-11-18 09:04:53,690 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9916 states to 9916 states and 13640 transitions. [2018-11-18 09:04:53,690 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9916 [2018-11-18 09:04:53,695 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9916 [2018-11-18 09:04:53,695 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9916 states and 13640 transitions. [2018-11-18 09:04:53,702 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:04:53,702 INFO L705 BuchiCegarLoop]: Abstraction has 9916 states and 13640 transitions. [2018-11-18 09:04:53,707 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9916 states and 13640 transitions. [2018-11-18 09:04:53,756 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9916 to 9908. [2018-11-18 09:04:53,756 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9908 states. [2018-11-18 09:04:53,765 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9908 states to 9908 states and 13632 transitions. [2018-11-18 09:04:53,765 INFO L728 BuchiCegarLoop]: Abstraction has 9908 states and 13632 transitions. [2018-11-18 09:04:53,765 INFO L608 BuchiCegarLoop]: Abstraction has 9908 states and 13632 transitions. [2018-11-18 09:04:53,765 INFO L442 BuchiCegarLoop]: ======== Iteration 19============ [2018-11-18 09:04:53,765 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9908 states and 13632 transitions. [2018-11-18 09:04:53,783 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9684 [2018-11-18 09:04:53,784 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:04:53,784 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:04:53,785 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:53,785 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:53,785 INFO L794 eck$LassoCheckResult]: Stem: 106380#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 106273#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 106274#L1143 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 106239#L531 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 106240#L538 assume 1 == ~m_i~0;~m_st~0 := 0; 106754#L538-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 106566#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 106464#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 106241#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 106242#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 106654#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 106452#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 106220#L573-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 106221#L771 assume !(0 == ~M_E~0); 106357#L771-2 assume !(0 == ~T1_E~0); 106042#L776-1 assume !(0 == ~T2_E~0); 106043#L781-1 assume !(0 == ~T3_E~0); 106524#L786-1 assume !(0 == ~T4_E~0); 106320#L791-1 assume !(0 == ~T5_E~0); 105974#L796-1 assume !(0 == ~T6_E~0); 105975#L801-1 assume !(0 == ~T7_E~0); 106731#L806-1 assume 0 == ~E_M~0;~E_M~0 := 1; 106411#L811-1 assume !(0 == ~E_1~0); 106412#L816-1 assume !(0 == ~E_2~0); 106839#L821-1 assume !(0 == ~E_3~0); 106840#L826-1 assume !(0 == ~E_4~0); 106612#L831-1 assume !(0 == ~E_5~0); 106613#L836-1 assume !(0 == ~E_6~0); 105886#L841-1 assume !(0 == ~E_7~0); 105887#L846-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 106872#L378 assume !(1 == ~m_pc~0); 106873#L378-2 is_master_triggered_~__retres1~0 := 0; 106103#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 106632#L390 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 106633#L957 assume !(0 != activate_threads_~tmp~1); 106814#L957-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 106815#L397 assume !(1 == ~t1_pc~0); 106204#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 106205#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 106638#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 106639#L965 assume !(0 != activate_threads_~tmp___0~0); 106405#L965-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 106406#L416 assume !(1 == ~t2_pc~0); 106299#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 106300#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 106755#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 105904#L973 assume !(0 != activate_threads_~tmp___1~0); 105905#L973-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 105910#L435 assume !(1 == ~t3_pc~0); 106599#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 106600#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 106837#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 106838#L981 assume !(0 != activate_threads_~tmp___2~0); 106665#L981-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 106666#L454 assume !(1 == ~t4_pc~0); 106721#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 106245#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 106246#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 106324#L989 assume !(0 != activate_threads_~tmp___3~0); 106325#L989-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 106801#L473 assume !(1 == ~t5_pc~0); 106802#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 106386#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 106387#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 106850#L997 assume !(0 != activate_threads_~tmp___4~0); 106851#L997-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 106880#L492 assume !(1 == ~t6_pc~0); 106878#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 106506#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 106507#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 106717#L1005 assume !(0 != activate_threads_~tmp___5~0); 106718#L1005-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 106877#L511 assume !(1 == ~t7_pc~0); 106033#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 106876#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 106868#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 106869#L1013 assume !(0 != activate_threads_~tmp___6~0); 106367#L1013-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 106368#L859 assume !(1 == ~M_E~0); 106355#L859-2 assume !(1 == ~T1_E~0); 106356#L864-1 assume !(1 == ~T2_E~0); 106808#L869-1 assume !(1 == ~T3_E~0); 106521#L874-1 assume !(1 == ~T4_E~0); 106522#L879-1 assume !(1 == ~T5_E~0); 106874#L884-1 assume !(1 == ~T6_E~0); 106862#L889-1 assume !(1 == ~T7_E~0); 106729#L894-1 assume 1 == ~E_M~0;~E_M~0 := 2; 106409#L899-1 assume !(1 == ~E_1~0); 106147#L904-1 assume !(1 == ~E_2~0); 106148#L909-1 assume !(1 == ~E_3~0); 106785#L914-1 assume !(1 == ~E_4~0); 106617#L919-1 assume !(1 == ~E_5~0); 106404#L924-1 assume !(1 == ~E_6~0); 105911#L929-1 assume !(1 == ~E_7~0); 105912#L934-1 assume { :end_inline_reset_delta_events } true; 106761#L1180-3 [2018-11-18 09:04:53,785 INFO L796 eck$LassoCheckResult]: Loop: 106761#L1180-3 assume true; 109588#L1180-1 assume !false; 109454#L1181 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 109452#L746 assume true; 109450#L638-1 assume !false; 109448#L639 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 109380#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 109378#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 109376#L629 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 109374#L643 assume !(0 != eval_~tmp~0); 109375#L761 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 110366#L531-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 110363#L771-3 assume !(0 == ~M_E~0); 110361#L771-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 110359#L776-3 assume !(0 == ~T2_E~0); 110357#L781-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 110355#L786-3 assume !(0 == ~T4_E~0); 110352#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 110350#L796-3 assume !(0 == ~T6_E~0); 110348#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 110345#L806-3 assume !(0 == ~E_M~0); 110343#L811-3 assume 0 == ~E_1~0;~E_1~0 := 1; 110341#L816-3 assume !(0 == ~E_2~0); 110339#L821-3 assume 0 == ~E_3~0;~E_3~0 := 1; 110336#L826-3 assume !(0 == ~E_4~0); 110334#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 110332#L836-3 assume !(0 == ~E_6~0); 110329#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 110328#L846-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 110327#L378-27 assume 1 == ~m_pc~0; 110325#L379-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 110326#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 111453#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 111451#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 111449#L957-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 111448#L397-27 assume !(1 == ~t1_pc~0); 111447#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 111445#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 111444#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 111443#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 111442#L965-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 111441#L416-27 assume !(1 == ~t2_pc~0); 111440#L416-29 is_transmit2_triggered_~__retres1~2 := 0; 111438#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 111437#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 111436#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 111434#L973-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 111432#L435-27 assume !(1 == ~t3_pc~0); 111430#L435-29 is_transmit3_triggered_~__retres1~3 := 0; 111428#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 111425#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 111423#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 111421#L981-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 111419#L454-27 assume !(1 == ~t4_pc~0); 111416#L454-29 is_transmit4_triggered_~__retres1~4 := 0; 110844#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 110843#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 110842#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 110841#L989-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 110840#L473-27 assume !(1 == ~t5_pc~0); 110837#L473-29 is_transmit5_triggered_~__retres1~5 := 0; 110836#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 110835#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 110834#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 110833#L997-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 110832#L492-27 assume !(1 == ~t6_pc~0); 110830#L492-29 is_transmit6_triggered_~__retres1~6 := 0; 110829#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 110828#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 110826#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 110825#L1005-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 110824#L511-27 assume !(1 == ~t7_pc~0); 110821#L511-29 is_transmit7_triggered_~__retres1~7 := 0; 110820#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 110818#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 110815#L1013-27 assume !(0 != activate_threads_~tmp___6~0); 110812#L1013-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 110810#L859-3 assume !(1 == ~M_E~0); 110808#L859-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 110806#L864-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 110804#L869-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 110802#L874-3 assume !(1 == ~T4_E~0); 110800#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 110798#L884-3 assume !(1 == ~T6_E~0); 110796#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 109673#L894-3 assume 1 == ~E_M~0;~E_M~0 := 2; 109670#L899-3 assume 1 == ~E_1~0;~E_1~0 := 2; 109667#L904-3 assume 1 == ~E_2~0;~E_2~0 := 2; 109665#L909-3 assume 1 == ~E_3~0;~E_3~0 := 2; 109663#L914-3 assume !(1 == ~E_4~0); 109661#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 109659#L924-3 assume !(1 == ~E_6~0); 109657#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 109655#L934-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 109637#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 109635#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 109633#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 109630#L1199 assume !(0 == start_simulation_~tmp~3); 109627#L1199-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 109606#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 109604#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 109602#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 109600#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 109597#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 109595#L1162 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 109591#L1212 assume !(0 != start_simulation_~tmp___0~1); 106761#L1180-3 [2018-11-18 09:04:53,785 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:53,785 INFO L82 PathProgramCache]: Analyzing trace with hash 61467781, now seen corresponding path program 1 times [2018-11-18 09:04:53,786 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:53,786 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:53,786 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:53,786 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:53,786 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:53,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:53,816 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:53,816 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:53,816 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 09:04:53,816 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 09:04:53,816 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:53,817 INFO L82 PathProgramCache]: Analyzing trace with hash 554311017, now seen corresponding path program 1 times [2018-11-18 09:04:53,817 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:53,817 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:53,817 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:53,817 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:53,817 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:53,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:53,844 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:53,844 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:53,844 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 09:04:53,844 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:04:53,844 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:04:53,844 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:04:53,845 INFO L87 Difference]: Start difference. First operand 9908 states and 13632 transitions. cyclomatic complexity: 3732 Second operand 3 states. [2018-11-18 09:04:53,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:04:53,880 INFO L93 Difference]: Finished difference Result 5403 states and 7415 transitions. [2018-11-18 09:04:53,881 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:04:53,882 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5403 states and 7415 transitions. [2018-11-18 09:04:53,893 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5276 [2018-11-18 09:04:53,901 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5403 states to 5403 states and 7415 transitions. [2018-11-18 09:04:53,902 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5403 [2018-11-18 09:04:53,905 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5403 [2018-11-18 09:04:53,905 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5403 states and 7415 transitions. [2018-11-18 09:04:53,909 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:04:53,909 INFO L705 BuchiCegarLoop]: Abstraction has 5403 states and 7415 transitions. [2018-11-18 09:04:53,912 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5403 states and 7415 transitions. [2018-11-18 09:04:53,991 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5403 to 5403. [2018-11-18 09:04:53,992 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5403 states. [2018-11-18 09:04:53,997 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5403 states to 5403 states and 7415 transitions. [2018-11-18 09:04:53,997 INFO L728 BuchiCegarLoop]: Abstraction has 5403 states and 7415 transitions. [2018-11-18 09:04:53,997 INFO L608 BuchiCegarLoop]: Abstraction has 5403 states and 7415 transitions. [2018-11-18 09:04:53,997 INFO L442 BuchiCegarLoop]: ======== Iteration 20============ [2018-11-18 09:04:53,997 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5403 states and 7415 transitions. [2018-11-18 09:04:54,006 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5276 [2018-11-18 09:04:54,006 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:04:54,006 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:04:54,007 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:54,007 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:54,008 INFO L794 eck$LassoCheckResult]: Stem: 121672#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 121574#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 121575#L1143 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 121530#L531 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 121531#L538 assume 1 == ~m_i~0;~m_st~0 := 0; 122015#L538-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 121843#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 121752#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 121532#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 121533#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 121918#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 121740#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 121511#L573-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 121512#L771 assume !(0 == ~M_E~0); 121652#L771-2 assume !(0 == ~T1_E~0); 121356#L776-1 assume !(0 == ~T2_E~0); 121357#L781-1 assume !(0 == ~T3_E~0); 121806#L786-1 assume !(0 == ~T4_E~0); 121620#L791-1 assume !(0 == ~T5_E~0); 121291#L796-1 assume !(0 == ~T6_E~0); 121292#L801-1 assume !(0 == ~T7_E~0); 121991#L806-1 assume !(0 == ~E_M~0); 121701#L811-1 assume !(0 == ~E_1~0); 121450#L816-1 assume !(0 == ~E_2~0); 121451#L821-1 assume !(0 == ~E_3~0); 122037#L826-1 assume !(0 == ~E_4~0); 121880#L831-1 assume !(0 == ~E_5~0); 121688#L836-1 assume !(0 == ~E_6~0); 121200#L841-1 assume !(0 == ~E_7~0); 121201#L846-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 121275#L378 assume !(1 == ~m_pc~0); 121248#L378-2 is_master_triggered_~__retres1~0 := 0; 121249#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 121850#L390 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 121897#L957 assume !(0 != activate_threads_~tmp~1); 122064#L957-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 121487#L397 assume !(1 == ~t1_pc~0); 121488#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 121495#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 121902#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 121704#L965 assume !(0 != activate_threads_~tmp___0~0); 121694#L965-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 121695#L416 assume !(1 == ~t2_pc~0); 121599#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 121600#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 122016#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 121220#L973 assume !(0 != activate_threads_~tmp___1~0); 121221#L973-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 121226#L435 assume !(1 == ~t3_pc~0); 121868#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 121317#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 121318#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 121939#L981 assume !(0 != activate_threads_~tmp___2~0); 121929#L981-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 121930#L454 assume !(1 == ~t4_pc~0); 121847#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 121536#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 121269#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 121270#L989 assume !(0 != activate_threads_~tmp___3~0); 121624#L989-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 121626#L473 assume !(1 == ~t5_pc~0); 122056#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 121677#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 121514#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 121515#L997 assume !(0 != activate_threads_~tmp___4~0); 122088#L997-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 122089#L492 assume !(1 == ~t6_pc~0); 122093#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 121790#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 121753#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 121754#L1005 assume !(0 != activate_threads_~tmp___5~0); 121982#L1005-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 121189#L511 assume !(1 == ~t7_pc~0); 121190#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 121401#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 122102#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 121670#L1013 assume !(0 != activate_threads_~tmp___6~0); 121662#L1013-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 121663#L859 assume !(1 == ~M_E~0); 121651#L859-2 assume !(1 == ~T1_E~0); 121374#L864-1 assume !(1 == ~T2_E~0); 121375#L869-1 assume !(1 == ~T3_E~0); 121804#L874-1 assume !(1 == ~T4_E~0); 121614#L879-1 assume !(1 == ~T5_E~0); 121287#L884-1 assume !(1 == ~T6_E~0); 121288#L889-1 assume !(1 == ~T7_E~0); 121989#L894-1 assume !(1 == ~E_M~0); 121696#L899-1 assume !(1 == ~E_1~0); 121444#L904-1 assume !(1 == ~E_2~0); 121445#L909-1 assume !(1 == ~E_3~0); 122042#L914-1 assume !(1 == ~E_4~0); 121884#L919-1 assume !(1 == ~E_5~0); 121693#L924-1 assume !(1 == ~E_6~0); 121229#L929-1 assume !(1 == ~E_7~0); 121230#L934-1 assume { :end_inline_reset_delta_events } true; 122019#L1180-3 [2018-11-18 09:04:54,008 INFO L796 eck$LassoCheckResult]: Loop: 122019#L1180-3 assume true; 126202#L1180-1 assume !false; 121983#L1181 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 121361#L746 assume true; 121683#L638-1 assume !false; 121659#L639 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 121660#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 121283#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 121927#L629 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 121175#L643 assume !(0 != eval_~tmp~0); 121177#L761 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 126404#L531-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 126403#L771-3 assume !(0 == ~M_E~0); 126402#L771-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 126401#L776-3 assume !(0 == ~T2_E~0); 126400#L781-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 126398#L786-3 assume !(0 == ~T4_E~0); 126396#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 126394#L796-3 assume !(0 == ~T6_E~0); 126393#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 126390#L806-3 assume !(0 == ~E_M~0); 126388#L811-3 assume 0 == ~E_1~0;~E_1~0 := 1; 126386#L816-3 assume !(0 == ~E_2~0); 126384#L821-3 assume 0 == ~E_3~0;~E_3~0 := 1; 126382#L826-3 assume !(0 == ~E_4~0); 126380#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 126378#L836-3 assume !(0 == ~E_6~0); 126375#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 126373#L846-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 126371#L378-27 assume !(1 == ~m_pc~0); 126369#L378-29 is_master_triggered_~__retres1~0 := 0; 126368#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 126367#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 126353#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 122051#L957-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 121427#L397-27 assume !(1 == ~t1_pc~0); 121428#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 121429#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 121962#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 121772#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 121764#L965-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 121612#L416-27 assume 1 == ~t2_pc~0; 121564#L417-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 121565#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 122002#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 121380#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 121381#L973-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 121387#L435-27 assume !(1 == ~t3_pc~0); 121738#L435-29 is_transmit3_triggered_~__retres1~3 := 0; 121313#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 121314#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 122000#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 121993#L981-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 121856#L454-27 assume !(1 == ~t4_pc~0); 121812#L454-29 is_transmit4_triggered_~__retres1~4 := 0; 121521#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 121235#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 121236#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 121567#L989-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 121571#L473-27 assume !(1 == ~t5_pc~0); 121978#L473-29 is_transmit5_triggered_~__retres1~5 := 0; 121675#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 121471#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 121472#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 122068#L997-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 122069#L492-27 assume !(1 == ~t6_pc~0); 122021#L492-29 is_transmit6_triggered_~__retres1~6 := 0; 121768#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 121649#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 121650#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 121817#L1005-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 121345#L511-27 assume 1 == ~t7_pc~0; 121305#L512-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 121306#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 126429#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 126428#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 121453#L1013-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 121454#L859-3 assume !(1 == ~M_E~0); 121653#L859-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 121354#L864-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 121355#L869-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 121805#L874-3 assume !(1 == ~T4_E~0); 121619#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 121289#L884-3 assume !(1 == ~T6_E~0); 121290#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 121990#L894-3 assume !(1 == ~E_M~0); 121700#L899-3 assume 1 == ~E_1~0;~E_1~0 := 2; 121448#L904-3 assume 1 == ~E_2~0;~E_2~0 := 2; 121449#L909-3 assume 1 == ~E_3~0;~E_3~0 := 2; 122043#L914-3 assume !(1 == ~E_4~0); 121879#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 121687#L924-3 assume !(1 == ~E_6~0); 121198#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 121199#L934-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 121985#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 121286#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 121912#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 121913#L1199 assume !(0 == start_simulation_~tmp~3); 121631#L1199-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 126211#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 126209#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 126207#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 126206#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 126205#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 126204#L1162 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 126203#L1212 assume !(0 != start_simulation_~tmp___0~1); 122019#L1180-3 [2018-11-18 09:04:54,008 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:54,008 INFO L82 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 3 times [2018-11-18 09:04:54,008 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:54,008 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:54,009 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:54,009 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:54,009 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:54,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:04:54,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:04:54,037 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:54,037 INFO L82 PathProgramCache]: Analyzing trace with hash 1298974568, now seen corresponding path program 1 times [2018-11-18 09:04:54,038 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:54,038 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:54,038 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:54,038 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 09:04:54,038 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:54,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:54,097 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:54,097 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:54,098 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 09:04:54,098 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:04:54,098 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 09:04:54,098 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 09:04:54,098 INFO L87 Difference]: Start difference. First operand 5403 states and 7415 transitions. cyclomatic complexity: 2020 Second operand 5 states. [2018-11-18 09:04:54,172 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:04:54,172 INFO L93 Difference]: Finished difference Result 9883 states and 13431 transitions. [2018-11-18 09:04:54,174 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-18 09:04:54,174 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9883 states and 13431 transitions. [2018-11-18 09:04:54,195 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9732 [2018-11-18 09:04:54,212 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9883 states to 9883 states and 13431 transitions. [2018-11-18 09:04:54,212 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9883 [2018-11-18 09:04:54,217 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9883 [2018-11-18 09:04:54,217 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9883 states and 13431 transitions. [2018-11-18 09:04:54,223 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:04:54,223 INFO L705 BuchiCegarLoop]: Abstraction has 9883 states and 13431 transitions. [2018-11-18 09:04:54,228 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9883 states and 13431 transitions. [2018-11-18 09:04:54,262 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9883 to 5427. [2018-11-18 09:04:54,263 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5427 states. [2018-11-18 09:04:54,268 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5427 states to 5427 states and 7439 transitions. [2018-11-18 09:04:54,268 INFO L728 BuchiCegarLoop]: Abstraction has 5427 states and 7439 transitions. [2018-11-18 09:04:54,268 INFO L608 BuchiCegarLoop]: Abstraction has 5427 states and 7439 transitions. [2018-11-18 09:04:54,268 INFO L442 BuchiCegarLoop]: ======== Iteration 21============ [2018-11-18 09:04:54,268 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5427 states and 7439 transitions. [2018-11-18 09:04:54,278 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5300 [2018-11-18 09:04:54,278 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:04:54,278 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:04:54,279 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:54,280 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:54,280 INFO L794 eck$LassoCheckResult]: Stem: 136979#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 136880#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 136881#L1143 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 136833#L531 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 136834#L538 assume 1 == ~m_i~0;~m_st~0 := 0; 137328#L538-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 137157#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 137060#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 136835#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 136836#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 137234#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 137049#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 136814#L573-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 136815#L771 assume !(0 == ~M_E~0); 136958#L771-2 assume !(0 == ~T1_E~0); 136659#L776-1 assume !(0 == ~T2_E~0); 136660#L781-1 assume !(0 == ~T3_E~0); 137115#L786-1 assume !(0 == ~T4_E~0); 136926#L791-1 assume !(0 == ~T5_E~0); 136591#L796-1 assume !(0 == ~T6_E~0); 136592#L801-1 assume !(0 == ~T7_E~0); 137305#L806-1 assume !(0 == ~E_M~0); 137008#L811-1 assume !(0 == ~E_1~0); 136751#L816-1 assume !(0 == ~E_2~0); 136752#L821-1 assume !(0 == ~E_3~0); 137351#L826-1 assume !(0 == ~E_4~0); 137196#L831-1 assume !(0 == ~E_5~0); 136996#L836-1 assume !(0 == ~E_6~0); 136503#L841-1 assume !(0 == ~E_7~0); 136504#L846-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 136575#L378 assume !(1 == ~m_pc~0); 136549#L378-2 is_master_triggered_~__retres1~0 := 0; 136550#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 137165#L390 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 137214#L957 assume !(0 != activate_threads_~tmp~1); 137377#L957-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 136790#L397 assume !(1 == ~t1_pc~0); 136791#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 136798#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 137219#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 137011#L965 assume !(0 != activate_threads_~tmp___0~0); 137002#L965-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 137003#L416 assume !(1 == ~t2_pc~0); 136905#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 136906#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 137329#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 136521#L973 assume !(0 != activate_threads_~tmp___1~0); 136522#L973-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 136527#L435 assume !(1 == ~t3_pc~0); 137184#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 136620#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 136621#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 137255#L981 assume !(0 != activate_threads_~tmp___2~0); 137245#L981-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 137246#L454 assume !(1 == ~t4_pc~0); 137160#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 136839#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 136569#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 136570#L989 assume !(0 != activate_threads_~tmp___3~0); 136930#L989-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 136932#L473 assume !(1 == ~t5_pc~0); 137370#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 136985#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 136817#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 136818#L997 assume !(0 != activate_threads_~tmp___4~0); 137402#L997-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 137403#L492 assume !(1 == ~t6_pc~0); 137407#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 137099#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 137061#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 137062#L1005 assume !(0 != activate_threads_~tmp___5~0); 137297#L1005-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 136494#L511 assume !(1 == ~t7_pc~0); 136495#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 136704#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 137112#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 136977#L1013 assume !(0 != activate_threads_~tmp___6~0); 136969#L1013-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 136970#L859 assume !(1 == ~M_E~0); 136957#L859-2 assume !(1 == ~T1_E~0); 136676#L864-1 assume !(1 == ~T2_E~0); 136677#L869-1 assume !(1 == ~T3_E~0); 137113#L874-1 assume !(1 == ~T4_E~0); 136921#L879-1 assume !(1 == ~T5_E~0); 136587#L884-1 assume !(1 == ~T6_E~0); 136588#L889-1 assume !(1 == ~T7_E~0); 137303#L894-1 assume !(1 == ~E_M~0); 137006#L899-1 assume !(1 == ~E_1~0); 136745#L904-1 assume !(1 == ~E_2~0); 136746#L909-1 assume !(1 == ~E_3~0); 137357#L914-1 assume !(1 == ~E_4~0); 137199#L919-1 assume !(1 == ~E_5~0); 137001#L924-1 assume !(1 == ~E_6~0); 136530#L929-1 assume !(1 == ~E_7~0); 136531#L934-1 assume { :end_inline_reset_delta_events } true; 137333#L1180-3 [2018-11-18 09:04:54,280 INFO L796 eck$LassoCheckResult]: Loop: 137333#L1180-3 assume true; 137313#L1180-1 assume !false; 137298#L1181 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 136663#L746 assume true; 136991#L638-1 assume !false; 136967#L639 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 136968#L586 assume !(0 == ~m_st~0); 137045#L590 assume !(0 == ~t1_st~0); 136992#L594 assume !(0 == ~t2_st~0); 136581#L598 assume !(0 == ~t3_st~0); 136582#L602 assume !(0 == ~t4_st~0); 137293#L606 assume !(0 == ~t5_st~0); 137109#L610 assume !(0 == ~t6_st~0); 137069#L614 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8 := 0; 137070#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 137242#L629 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 137243#L643 assume !(0 != eval_~tmp~0); 137237#L761 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 136837#L531-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 136838#L771-3 assume !(0 == ~M_E~0); 136811#L771-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 136812#L776-3 assume !(0 == ~T2_E~0); 140647#L781-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 140646#L786-3 assume !(0 == ~T4_E~0); 140645#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 140644#L796-3 assume !(0 == ~T6_E~0); 140643#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 140642#L806-3 assume !(0 == ~E_M~0); 140641#L811-3 assume 0 == ~E_1~0;~E_1~0 := 1; 140640#L816-3 assume !(0 == ~E_2~0); 140639#L821-3 assume 0 == ~E_3~0;~E_3~0 := 1; 140638#L826-3 assume !(0 == ~E_4~0); 140637#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 140636#L836-3 assume !(0 == ~E_6~0); 140635#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 140634#L846-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 140633#L378-27 assume !(1 == ~m_pc~0); 140631#L378-29 is_master_triggered_~__retres1~0 := 0; 140630#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 140629#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 140627#L957-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 140626#L957-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 140623#L397-27 assume !(1 == ~t1_pc~0); 140624#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 140628#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 137481#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 137477#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 137474#L965-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 137468#L416-27 assume !(1 == ~t2_pc~0); 137470#L416-29 is_transmit2_triggered_~__retres1~2 := 0; 137459#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 137460#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 137451#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 137452#L973-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 137046#L435-27 assume !(1 == ~t3_pc~0); 137047#L435-29 is_transmit3_triggered_~__retres1~3 := 0; 141188#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 141187#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 137314#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 137315#L981-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 141186#L454-27 assume !(1 == ~t4_pc~0); 141184#L454-29 is_transmit4_triggered_~__retres1~4 := 0; 136824#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 136536#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 136537#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 136873#L989-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 136877#L473-27 assume !(1 == ~t5_pc~0); 137292#L473-29 is_transmit5_triggered_~__retres1~5 := 0; 136982#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 136983#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 137390#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 137391#L997-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 141749#L492-27 assume !(1 == ~t6_pc~0); 137414#L492-29 is_transmit6_triggered_~__retres1~6 := 0; 137415#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 136955#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 136956#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 137132#L1005-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 136645#L511-27 assume 1 == ~t7_pc~0; 136646#L512-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 141249#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 141250#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 141243#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 136755#L1013-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 136756#L859-3 assume !(1 == ~M_E~0); 141745#L859-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 141744#L864-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 141743#L869-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 141742#L874-3 assume !(1 == ~T4_E~0); 141741#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 141740#L884-3 assume !(1 == ~T6_E~0); 141739#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 141738#L894-3 assume !(1 == ~E_M~0); 141737#L899-3 assume 1 == ~E_1~0;~E_1~0 := 2; 141736#L904-3 assume 1 == ~E_2~0;~E_2~0 := 2; 141735#L909-3 assume 1 == ~E_3~0;~E_3~0 := 2; 141734#L914-3 assume !(1 == ~E_4~0); 141733#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 141732#L924-3 assume !(1 == ~E_6~0); 141731#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 141730#L934-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 137299#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 136586#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 137228#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 137229#L1199 assume !(0 == start_simulation_~tmp~3); 136937#L1199-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 137318#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 141622#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 141621#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 141620#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 141619#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 141618#L1162 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 141617#L1212 assume !(0 != start_simulation_~tmp___0~1); 137333#L1180-3 [2018-11-18 09:04:54,280 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:54,280 INFO L82 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 4 times [2018-11-18 09:04:54,280 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:54,281 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:54,281 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:54,281 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:54,281 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:54,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:04:54,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:04:54,309 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:54,309 INFO L82 PathProgramCache]: Analyzing trace with hash -182468245, now seen corresponding path program 1 times [2018-11-18 09:04:54,309 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:54,309 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:54,310 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:54,310 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 09:04:54,310 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:54,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:54,368 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:54,368 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:54,368 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 09:04:54,368 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:04:54,368 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 09:04:54,369 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 09:04:54,369 INFO L87 Difference]: Start difference. First operand 5427 states and 7439 transitions. cyclomatic complexity: 2020 Second operand 5 states. [2018-11-18 09:04:54,465 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:04:54,465 INFO L93 Difference]: Finished difference Result 7963 states and 11026 transitions. [2018-11-18 09:04:54,465 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 09:04:54,465 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7963 states and 11026 transitions. [2018-11-18 09:04:54,483 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7788 [2018-11-18 09:04:54,496 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7963 states to 7963 states and 11026 transitions. [2018-11-18 09:04:54,496 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7963 [2018-11-18 09:04:54,500 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7963 [2018-11-18 09:04:54,501 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7963 states and 11026 transitions. [2018-11-18 09:04:54,505 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:04:54,505 INFO L705 BuchiCegarLoop]: Abstraction has 7963 states and 11026 transitions. [2018-11-18 09:04:54,509 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7963 states and 11026 transitions. [2018-11-18 09:04:54,536 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7963 to 5451. [2018-11-18 09:04:54,536 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5451 states. [2018-11-18 09:04:54,542 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5451 states to 5451 states and 7402 transitions. [2018-11-18 09:04:54,542 INFO L728 BuchiCegarLoop]: Abstraction has 5451 states and 7402 transitions. [2018-11-18 09:04:54,542 INFO L608 BuchiCegarLoop]: Abstraction has 5451 states and 7402 transitions. [2018-11-18 09:04:54,542 INFO L442 BuchiCegarLoop]: ======== Iteration 22============ [2018-11-18 09:04:54,542 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5451 states and 7402 transitions. [2018-11-18 09:04:54,552 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5324 [2018-11-18 09:04:54,552 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:04:54,552 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:04:54,553 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:54,553 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:54,553 INFO L794 eck$LassoCheckResult]: Stem: 150409#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 150296#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 150297#L1143 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 150254#L531 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 150255#L538 assume 1 == ~m_i~0;~m_st~0 := 0; 150801#L538-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 150596#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 150498#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 150256#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 150257#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 150682#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 150479#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 150232#L573-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 150233#L771 assume !(0 == ~M_E~0); 150388#L771-2 assume !(0 == ~T1_E~0); 150063#L776-1 assume !(0 == ~T2_E~0); 150064#L781-1 assume !(0 == ~T3_E~0); 150558#L786-1 assume !(0 == ~T4_E~0); 150352#L791-1 assume !(0 == ~T5_E~0); 149998#L796-1 assume !(0 == ~T6_E~0); 149999#L801-1 assume !(0 == ~T7_E~0); 150770#L806-1 assume !(0 == ~E_M~0); 150440#L811-1 assume !(0 == ~E_1~0); 150167#L816-1 assume !(0 == ~E_2~0); 150168#L821-1 assume !(0 == ~E_3~0); 150841#L826-1 assume !(0 == ~E_4~0); 150639#L831-1 assume !(0 == ~E_5~0); 150427#L836-1 assume !(0 == ~E_6~0); 149906#L841-1 assume !(0 == ~E_7~0); 149907#L846-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 149982#L378 assume !(1 == ~m_pc~0); 149956#L378-2 is_master_triggered_~__retres1~0 := 0; 149957#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 150604#L390 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 150660#L957 assume !(0 != activate_threads_~tmp~1); 150879#L957-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 150206#L397 assume !(1 == ~t1_pc~0); 150207#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 150215#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 150664#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 150443#L965 assume !(0 != activate_threads_~tmp___0~0); 150434#L965-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 150435#L416 assume !(1 == ~t2_pc~0); 150326#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 150327#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 150802#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 149930#L973 assume !(0 != activate_threads_~tmp___1~0); 149931#L973-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 149933#L435 assume !(1 == ~t3_pc~0); 150627#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 150024#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 150025#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 150707#L981 assume !(0 != activate_threads_~tmp___2~0); 150695#L981-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 150696#L454 assume !(1 == ~t4_pc~0); 150600#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 150260#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 149976#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 149977#L989 assume !(0 != activate_threads_~tmp___3~0); 150357#L989-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 150359#L473 assume !(1 == ~t5_pc~0); 150867#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 150415#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 150235#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 150236#L997 assume !(0 != activate_threads_~tmp___4~0); 150911#L997-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 150912#L492 assume !(1 == ~t6_pc~0); 150917#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 150540#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 150499#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 150500#L1005 assume !(0 != activate_threads_~tmp___5~0); 150755#L1005-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 149895#L511 assume !(1 == ~t7_pc~0); 149896#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 150114#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 150929#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 150407#L1013 assume !(0 != activate_threads_~tmp___6~0); 150398#L1013-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 150399#L859 assume !(1 == ~M_E~0); 150387#L859-2 assume !(1 == ~T1_E~0); 150081#L864-1 assume !(1 == ~T2_E~0); 150082#L869-1 assume !(1 == ~T3_E~0); 150556#L874-1 assume !(1 == ~T4_E~0); 150343#L879-1 assume !(1 == ~T5_E~0); 149994#L884-1 assume !(1 == ~T6_E~0); 149995#L889-1 assume !(1 == ~T7_E~0); 150768#L894-1 assume !(1 == ~E_M~0); 150436#L899-1 assume !(1 == ~E_1~0); 150160#L904-1 assume !(1 == ~E_2~0); 150161#L909-1 assume !(1 == ~E_3~0); 150850#L914-1 assume !(1 == ~E_4~0); 150642#L919-1 assume !(1 == ~E_5~0); 150433#L924-1 assume !(1 == ~E_6~0); 149936#L929-1 assume !(1 == ~E_7~0); 149937#L934-1 assume { :end_inline_reset_delta_events } true; 150807#L1180-3 [2018-11-18 09:04:54,553 INFO L796 eck$LassoCheckResult]: Loop: 150807#L1180-3 assume true; 154252#L1180-1 assume !false; 154253#L1181 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 155146#L746 assume true; 155140#L638-1 assume !false; 155079#L639 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 155078#L586 assume !(0 == ~m_st~0); 155077#L590 assume !(0 == ~t1_st~0); 155076#L594 assume !(0 == ~t2_st~0); 155075#L598 assume !(0 == ~t3_st~0); 155074#L602 assume !(0 == ~t4_st~0); 155073#L606 assume !(0 == ~t5_st~0); 155072#L610 assume !(0 == ~t6_st~0); 155070#L614 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8 := 0; 155069#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 155068#L629 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 155067#L643 assume !(0 != eval_~tmp~0); 155066#L761 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 155065#L531-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 155064#L771-3 assume !(0 == ~M_E~0); 155063#L771-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 155061#L776-3 assume !(0 == ~T2_E~0); 155059#L781-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 155058#L786-3 assume !(0 == ~T4_E~0); 155057#L791-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 155056#L796-3 assume !(0 == ~T6_E~0); 155055#L801-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 155054#L806-3 assume !(0 == ~E_M~0); 155053#L811-3 assume 0 == ~E_1~0;~E_1~0 := 1; 155052#L816-3 assume !(0 == ~E_2~0); 150907#L821-3 assume 0 == ~E_3~0;~E_3~0 := 1; 150908#L826-3 assume !(0 == ~E_4~0); 155005#L831-3 assume 0 == ~E_5~0;~E_5~0 := 1; 155002#L836-3 assume !(0 == ~E_6~0); 154998#L841-3 assume 0 == ~E_7~0;~E_7~0 := 1; 150806#L846-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 149898#L378-27 assume !(1 == ~m_pc~0); 149900#L378-29 is_master_triggered_~__retres1~0 := 0; 150115#L389-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 150570#L390-9 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 150646#L957-27 assume !(0 != activate_threads_~tmp~1); 150858#L957-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 150142#L397-27 assume !(1 == ~t1_pc~0); 150143#L397-29 is_transmit1_triggered_~__retres1~1 := 0; 150144#L408-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 150732#L409-9 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 150521#L965-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 150511#L965-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 150341#L416-27 assume !(1 == ~t2_pc~0); 150288#L416-29 is_transmit2_triggered_~__retres1~2 := 0; 150287#L427-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 150785#L428-9 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 150089#L973-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 150090#L973-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 150097#L435-27 assume !(1 == ~t3_pc~0); 150477#L435-29 is_transmit3_triggered_~__retres1~3 := 0; 150020#L446-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 150021#L447-9 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 150781#L981-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 150772#L981-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 150610#L454-27 assume !(1 == ~t4_pc~0); 150563#L454-29 is_transmit4_triggered_~__retres1~4 := 0; 150242#L465-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 149942#L466-9 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 149943#L989-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 150289#L989-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 150293#L473-27 assume !(1 == ~t5_pc~0); 150750#L473-29 is_transmit5_triggered_~__retres1~5 := 0; 150413#L484-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 150190#L485-9 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 150191#L997-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 150881#L997-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 150882#L492-27 assume !(1 == ~t6_pc~0); 150809#L492-29 is_transmit6_triggered_~__retres1~6 := 0; 150516#L503-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 150385#L504-9 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 150386#L1005-27 assume !(0 != activate_threads_~tmp___5~0); 150569#L1005-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 150052#L511-27 assume 1 == ~t7_pc~0; 150010#L512-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 150011#L522-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 153717#L523-9 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 153716#L1013-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 150171#L1013-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 150172#L859-3 assume !(1 == ~M_E~0); 150391#L859-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 150061#L864-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 150062#L869-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 150557#L874-3 assume !(1 == ~T4_E~0); 150351#L879-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 149996#L884-3 assume !(1 == ~T6_E~0); 149997#L889-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 150769#L894-3 assume !(1 == ~E_M~0); 150439#L899-3 assume 1 == ~E_1~0;~E_1~0 := 2; 150165#L904-3 assume 1 == ~E_2~0;~E_2~0 := 2; 150166#L909-3 assume 1 == ~E_3~0;~E_3~0 := 2; 150851#L914-3 assume !(1 == ~E_4~0); 150638#L919-3 assume 1 == ~E_5~0;~E_5~0 := 2; 150426#L924-3 assume !(1 == ~E_6~0); 149904#L929-3 assume 1 == ~E_7~0;~E_7~0 := 2; 149905#L934-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 150763#L586-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 149993#L628-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 150676#L629-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 150677#L1199 assume !(0 == start_simulation_~tmp~3); 150800#L1199-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 154657#L586-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 154655#L628-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 154653#L629-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 154335#L1154 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 154260#L1161 stop_simulation_#res := stop_simulation_~__retres2~0; 154261#L1162 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 154647#L1212 assume !(0 != start_simulation_~tmp___0~1); 150807#L1180-3 [2018-11-18 09:04:54,554 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:54,554 INFO L82 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 5 times [2018-11-18 09:04:54,554 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:54,554 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:54,555 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:54,555 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:54,555 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:54,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:04:54,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:04:54,581 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:54,581 INFO L82 PathProgramCache]: Analyzing trace with hash -2093510803, now seen corresponding path program 1 times [2018-11-18 09:04:54,582 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:54,582 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:54,582 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:54,582 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 09:04:54,582 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:54,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:54,612 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:54,612 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:54,612 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:04:54,612 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:04:54,612 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:04:54,613 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:04:54,613 INFO L87 Difference]: Start difference. First operand 5451 states and 7402 transitions. cyclomatic complexity: 1959 Second operand 3 states. [2018-11-18 09:04:54,653 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:04:54,653 INFO L93 Difference]: Finished difference Result 8566 states and 11489 transitions. [2018-11-18 09:04:54,653 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:04:54,654 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8566 states and 11489 transitions. [2018-11-18 09:04:54,672 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8412 [2018-11-18 09:04:54,686 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8566 states to 8566 states and 11489 transitions. [2018-11-18 09:04:54,686 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8566 [2018-11-18 09:04:54,690 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8566 [2018-11-18 09:04:54,690 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8566 states and 11489 transitions. [2018-11-18 09:04:54,695 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:04:54,695 INFO L705 BuchiCegarLoop]: Abstraction has 8566 states and 11489 transitions. [2018-11-18 09:04:54,699 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8566 states and 11489 transitions. [2018-11-18 09:04:54,734 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8566 to 8566. [2018-11-18 09:04:54,734 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8566 states. [2018-11-18 09:04:54,742 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8566 states to 8566 states and 11489 transitions. [2018-11-18 09:04:54,743 INFO L728 BuchiCegarLoop]: Abstraction has 8566 states and 11489 transitions. [2018-11-18 09:04:54,743 INFO L608 BuchiCegarLoop]: Abstraction has 8566 states and 11489 transitions. [2018-11-18 09:04:54,743 INFO L442 BuchiCegarLoop]: ======== Iteration 23============ [2018-11-18 09:04:54,743 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8566 states and 11489 transitions. [2018-11-18 09:04:54,757 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8412 [2018-11-18 09:04:54,757 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:04:54,758 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:04:54,758 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:54,758 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:54,759 INFO L794 eck$LassoCheckResult]: Stem: 164402#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 164303#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 164304#L1143 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 164264#L531 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 164265#L538 assume 1 == ~m_i~0;~m_st~0 := 0; 164761#L538-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 164580#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 164482#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 164266#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 164267#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 164659#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 164472#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 164244#L573-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 164245#L771 assume !(0 == ~M_E~0); 164381#L771-2 assume !(0 == ~T1_E~0); 164083#L776-1 assume !(0 == ~T2_E~0); 164084#L781-1 assume !(0 == ~T3_E~0); 164539#L786-1 assume !(0 == ~T4_E~0); 164349#L791-1 assume !(0 == ~T5_E~0); 164016#L796-1 assume !(0 == ~T6_E~0); 164017#L801-1 assume !(0 == ~T7_E~0); 164738#L806-1 assume !(0 == ~E_M~0); 164432#L811-1 assume !(0 == ~E_1~0); 164183#L816-1 assume !(0 == ~E_2~0); 164184#L821-1 assume !(0 == ~E_3~0); 164784#L826-1 assume !(0 == ~E_4~0); 164621#L831-1 assume !(0 == ~E_5~0); 164420#L836-1 assume !(0 == ~E_6~0); 163926#L841-1 assume !(0 == ~E_7~0); 163927#L846-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 164000#L378 assume !(1 == ~m_pc~0); 163974#L378-2 is_master_triggered_~__retres1~0 := 0; 163975#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 164587#L390 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 164640#L957 assume !(0 != activate_threads_~tmp~1); 164816#L957-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 164220#L397 assume !(1 == ~t1_pc~0); 164221#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 164228#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 164644#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 164435#L965 assume !(0 != activate_threads_~tmp___0~0); 164426#L965-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 164427#L416 assume !(1 == ~t2_pc~0); 164328#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 164329#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 164762#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 163946#L973 assume !(0 != activate_threads_~tmp___1~0); 163947#L973-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 163952#L435 assume !(1 == ~t3_pc~0); 164609#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 164042#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 164043#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 164682#L981 assume !(0 != activate_threads_~tmp___2~0); 164672#L981-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 164673#L454 assume !(1 == ~t4_pc~0); 164584#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 164270#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 163994#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 163995#L989 assume !(0 != activate_threads_~tmp___3~0); 164353#L989-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 164355#L473 assume !(1 == ~t5_pc~0); 164805#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 164407#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 164247#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 164248#L997 assume !(0 != activate_threads_~tmp___4~0); 164837#L997-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 164838#L492 assume !(1 == ~t6_pc~0); 164842#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 164523#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 164483#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 164484#L1005 assume !(0 != activate_threads_~tmp___5~0); 164727#L1005-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 163915#L511 assume !(1 == ~t7_pc~0); 163916#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 164130#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 164855#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 164400#L1013 assume !(0 != activate_threads_~tmp___6~0); 164392#L1013-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 164393#L859 assume !(1 == ~M_E~0); 164380#L859-2 assume !(1 == ~T1_E~0); 164101#L864-1 assume !(1 == ~T2_E~0); 164102#L869-1 assume !(1 == ~T3_E~0); 164537#L874-1 assume !(1 == ~T4_E~0); 164343#L879-1 assume !(1 == ~T5_E~0); 164012#L884-1 assume !(1 == ~T6_E~0); 164013#L889-1 assume !(1 == ~T7_E~0); 164736#L894-1 assume !(1 == ~E_M~0); 164428#L899-1 assume !(1 == ~E_1~0); 164176#L904-1 assume !(1 == ~E_2~0); 164177#L909-1 assume !(1 == ~E_3~0); 164790#L914-1 assume !(1 == ~E_4~0); 164625#L919-1 assume !(1 == ~E_5~0); 164425#L924-1 assume !(1 == ~E_6~0); 163955#L929-1 assume !(1 == ~E_7~0); 163956#L934-1 assume { :end_inline_reset_delta_events } true; 164766#L1180-3 assume true; 169127#L1180-1 assume !false; 168697#L1181 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 168695#L746 [2018-11-18 09:04:54,759 INFO L796 eck$LassoCheckResult]: Loop: 168695#L746 assume true; 168693#L638-1 assume !false; 168691#L639 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 168687#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 168685#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 168684#L629 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 168683#L643 assume 0 != eval_~tmp~0; 168682#L643-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 168678#L651 assume !(0 != eval_~tmp_ndt_1~0); 168679#L648 assume !(0 == ~t1_st~0); 168758#L662 assume !(0 == ~t2_st~0); 168754#L676 assume !(0 == ~t3_st~0); 168750#L690 assume !(0 == ~t4_st~0); 168743#L704 assume !(0 == ~t5_st~0); 168705#L718 assume !(0 == ~t6_st~0); 168701#L732 assume !(0 == ~t7_st~0); 168695#L746 [2018-11-18 09:04:54,759 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:54,759 INFO L82 PathProgramCache]: Analyzing trace with hash 1816264822, now seen corresponding path program 1 times [2018-11-18 09:04:54,759 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:54,759 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:54,760 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:54,760 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:54,760 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:54,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:04:54,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:04:54,786 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:54,786 INFO L82 PathProgramCache]: Analyzing trace with hash 204988965, now seen corresponding path program 1 times [2018-11-18 09:04:54,786 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:54,786 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:54,787 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:54,787 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:54,787 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:54,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:04:54,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:04:54,791 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:54,791 INFO L82 PathProgramCache]: Analyzing trace with hash -1843636070, now seen corresponding path program 1 times [2018-11-18 09:04:54,791 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:54,791 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:54,792 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:54,792 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:54,792 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:54,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:54,826 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:54,827 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:54,827 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:04:54,891 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:04:54,891 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:04:54,891 INFO L87 Difference]: Start difference. First operand 8566 states and 11489 transitions. cyclomatic complexity: 2931 Second operand 3 states. [2018-11-18 09:04:55,035 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:04:55,036 INFO L93 Difference]: Finished difference Result 16538 states and 22015 transitions. [2018-11-18 09:04:55,036 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:04:55,036 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16538 states and 22015 transitions. [2018-11-18 09:04:55,071 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 15636 [2018-11-18 09:04:55,096 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16538 states to 16538 states and 22015 transitions. [2018-11-18 09:04:55,096 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16538 [2018-11-18 09:04:55,103 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16538 [2018-11-18 09:04:55,103 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16538 states and 22015 transitions. [2018-11-18 09:04:55,110 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:04:55,110 INFO L705 BuchiCegarLoop]: Abstraction has 16538 states and 22015 transitions. [2018-11-18 09:04:55,117 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16538 states and 22015 transitions. [2018-11-18 09:04:55,201 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16538 to 16146. [2018-11-18 09:04:55,201 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16146 states. [2018-11-18 09:04:55,219 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16146 states to 16146 states and 21511 transitions. [2018-11-18 09:04:55,219 INFO L728 BuchiCegarLoop]: Abstraction has 16146 states and 21511 transitions. [2018-11-18 09:04:55,219 INFO L608 BuchiCegarLoop]: Abstraction has 16146 states and 21511 transitions. [2018-11-18 09:04:55,219 INFO L442 BuchiCegarLoop]: ======== Iteration 24============ [2018-11-18 09:04:55,219 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16146 states and 21511 transitions. [2018-11-18 09:04:55,252 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 15244 [2018-11-18 09:04:55,252 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:04:55,252 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:04:55,253 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:55,253 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:55,253 INFO L794 eck$LassoCheckResult]: Stem: 189523#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 189421#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 189422#L1143 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 189382#L531 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 189383#L538 assume 1 == ~m_i~0;~m_st~0 := 0; 189883#L538-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 189695#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 189598#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 189384#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 189385#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 189782#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 189588#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 189363#L573-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 189364#L771 assume !(0 == ~M_E~0); 189501#L771-2 assume !(0 == ~T1_E~0); 189195#L776-1 assume !(0 == ~T2_E~0); 189196#L781-1 assume !(0 == ~T3_E~0); 189655#L786-1 assume !(0 == ~T4_E~0); 189469#L791-1 assume !(0 == ~T5_E~0); 189130#L796-1 assume !(0 == ~T6_E~0); 189131#L801-1 assume !(0 == ~T7_E~0); 189859#L806-1 assume !(0 == ~E_M~0); 189552#L811-1 assume !(0 == ~E_1~0); 189303#L816-1 assume !(0 == ~E_2~0); 189304#L821-1 assume !(0 == ~E_3~0); 189907#L826-1 assume !(0 == ~E_4~0); 189740#L831-1 assume !(0 == ~E_5~0); 189540#L836-1 assume !(0 == ~E_6~0); 189040#L841-1 assume !(0 == ~E_7~0); 189041#L846-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 189114#L378 assume !(1 == ~m_pc~0); 189088#L378-2 is_master_triggered_~__retres1~0 := 0; 189089#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 189702#L390 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 189760#L957 assume !(0 != activate_threads_~tmp~1); 189940#L957-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 189339#L397 assume !(1 == ~t1_pc~0); 189340#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 189347#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 189766#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 189555#L965 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 189556#L965-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 192843#L416 assume !(1 == ~t2_pc~0); 192841#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 192840#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 192839#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 192838#L973 assume !(0 != activate_threads_~tmp___1~0); 192837#L973-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 192836#L435 assume !(1 == ~t3_pc~0); 192835#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 192834#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 192833#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 192832#L981 assume !(0 != activate_threads_~tmp___2~0); 192831#L981-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 192829#L454 assume !(1 == ~t4_pc~0); 192828#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 192827#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 192826#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 192825#L989 assume !(0 != activate_threads_~tmp___3~0); 192824#L989-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 192823#L473 assume !(1 == ~t5_pc~0); 192822#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 192821#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 192820#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 192819#L997 assume !(0 != activate_threads_~tmp___4~0); 192818#L997-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 192817#L492 assume !(1 == ~t6_pc~0); 192815#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 192814#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 192813#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 192812#L1005 assume !(0 != activate_threads_~tmp___5~0); 192811#L1005-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 192810#L511 assume !(1 == ~t7_pc~0); 189249#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 189250#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 189652#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 189520#L1013 assume !(0 != activate_threads_~tmp___6~0); 189511#L1013-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 189512#L859 assume !(1 == ~M_E~0); 189500#L859-2 assume !(1 == ~T1_E~0); 189215#L864-1 assume !(1 == ~T2_E~0); 189216#L869-1 assume !(1 == ~T3_E~0); 189653#L874-1 assume !(1 == ~T4_E~0); 189463#L879-1 assume !(1 == ~T5_E~0); 189126#L884-1 assume !(1 == ~T6_E~0); 189127#L889-1 assume !(1 == ~T7_E~0); 189857#L894-1 assume !(1 == ~E_M~0); 189548#L899-1 assume !(1 == ~E_1~0); 189296#L904-1 assume !(1 == ~E_2~0); 189297#L909-1 assume !(1 == ~E_3~0); 189917#L914-1 assume !(1 == ~E_4~0); 189743#L919-1 assume !(1 == ~E_5~0); 189545#L924-1 assume !(1 == ~E_6~0); 189069#L929-1 assume !(1 == ~E_7~0); 189070#L934-1 assume { :end_inline_reset_delta_events } true; 189888#L1180-3 assume true; 199207#L1180-1 assume !false; 199069#L1181 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 199067#L746 [2018-11-18 09:04:55,254 INFO L796 eck$LassoCheckResult]: Loop: 199067#L746 assume true; 199064#L638-1 assume !false; 199062#L639 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 199060#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 199056#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 199054#L629 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 199052#L643 assume 0 != eval_~tmp~0; 199050#L643-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 199049#L651 assume !(0 != eval_~tmp_ndt_1~0); 199048#L648 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 192505#L665 assume !(0 != eval_~tmp_ndt_2~0); 199023#L662 assume !(0 == ~t2_st~0); 199019#L676 assume !(0 == ~t3_st~0); 199015#L690 assume !(0 == ~t4_st~0); 199009#L704 assume !(0 == ~t5_st~0); 198967#L718 assume !(0 == ~t6_st~0); 199073#L732 assume !(0 == ~t7_st~0); 199067#L746 [2018-11-18 09:04:55,254 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:55,254 INFO L82 PathProgramCache]: Analyzing trace with hash 499026746, now seen corresponding path program 1 times [2018-11-18 09:04:55,254 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:55,254 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:55,255 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:55,255 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:55,255 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:55,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:55,322 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:55,322 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:55,322 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:04:55,322 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 09:04:55,322 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:55,322 INFO L82 PathProgramCache]: Analyzing trace with hash 1207221344, now seen corresponding path program 1 times [2018-11-18 09:04:55,322 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:55,322 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:55,323 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:55,323 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:55,323 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:55,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:04:55,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:04:55,423 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:04:55,423 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:04:55,424 INFO L87 Difference]: Start difference. First operand 16146 states and 21511 transitions. cyclomatic complexity: 5377 Second operand 3 states. [2018-11-18 09:04:55,445 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:04:55,445 INFO L93 Difference]: Finished difference Result 11506 states and 15328 transitions. [2018-11-18 09:04:55,445 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:04:55,446 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11506 states and 15328 transitions. [2018-11-18 09:04:55,470 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11336 [2018-11-18 09:04:55,486 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11506 states to 11506 states and 15328 transitions. [2018-11-18 09:04:55,486 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11506 [2018-11-18 09:04:55,492 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11506 [2018-11-18 09:04:55,492 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11506 states and 15328 transitions. [2018-11-18 09:04:55,497 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:04:55,497 INFO L705 BuchiCegarLoop]: Abstraction has 11506 states and 15328 transitions. [2018-11-18 09:04:55,502 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11506 states and 15328 transitions. [2018-11-18 09:04:55,547 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11506 to 11506. [2018-11-18 09:04:55,547 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11506 states. [2018-11-18 09:04:55,556 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11506 states to 11506 states and 15328 transitions. [2018-11-18 09:04:55,556 INFO L728 BuchiCegarLoop]: Abstraction has 11506 states and 15328 transitions. [2018-11-18 09:04:55,556 INFO L608 BuchiCegarLoop]: Abstraction has 11506 states and 15328 transitions. [2018-11-18 09:04:55,556 INFO L442 BuchiCegarLoop]: ======== Iteration 25============ [2018-11-18 09:04:55,556 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11506 states and 15328 transitions. [2018-11-18 09:04:55,576 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11336 [2018-11-18 09:04:55,576 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:04:55,576 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:04:55,577 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:55,577 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:55,577 INFO L794 eck$LassoCheckResult]: Stem: 217181#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 217079#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 217080#L1143 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 217036#L531 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 217037#L538 assume 1 == ~m_i~0;~m_st~0 := 0; 217539#L538-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 217364#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 217266#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 217038#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 217039#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 217441#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 217253#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 217017#L573-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 217018#L771 assume !(0 == ~M_E~0); 217159#L771-2 assume !(0 == ~T1_E~0); 216853#L776-1 assume !(0 == ~T2_E~0); 216854#L781-1 assume !(0 == ~T3_E~0); 217325#L786-1 assume !(0 == ~T4_E~0); 217127#L791-1 assume !(0 == ~T5_E~0); 216787#L796-1 assume !(0 == ~T6_E~0); 216788#L801-1 assume !(0 == ~T7_E~0); 217517#L806-1 assume !(0 == ~E_M~0); 217214#L811-1 assume !(0 == ~E_1~0); 216952#L816-1 assume !(0 == ~E_2~0); 216953#L821-1 assume !(0 == ~E_3~0); 217562#L826-1 assume !(0 == ~E_4~0); 217404#L831-1 assume !(0 == ~E_5~0); 217198#L836-1 assume !(0 == ~E_6~0); 216697#L841-1 assume !(0 == ~E_7~0); 216698#L846-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 216771#L378 assume !(1 == ~m_pc~0); 216745#L378-2 is_master_triggered_~__retres1~0 := 0; 216746#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 217372#L390 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 217421#L957 assume !(0 != activate_threads_~tmp~1); 217586#L957-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 216993#L397 assume !(1 == ~t1_pc~0); 216994#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 217001#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 217425#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 217217#L965 assume !(0 != activate_threads_~tmp___0~0); 217206#L965-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 217207#L416 assume !(1 == ~t2_pc~0); 217105#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 217106#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 217540#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 216717#L973 assume !(0 != activate_threads_~tmp___1~0); 216718#L973-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 216723#L435 assume !(1 == ~t3_pc~0); 217393#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 216816#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 216817#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 217465#L981 assume !(0 != activate_threads_~tmp___2~0); 217455#L981-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 217456#L454 assume !(1 == ~t4_pc~0); 217367#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 217042#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 216765#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 216766#L989 assume !(0 != activate_threads_~tmp___3~0); 217131#L989-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 217133#L473 assume !(1 == ~t5_pc~0); 217579#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 217186#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 217020#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 217021#L997 assume !(0 != activate_threads_~tmp___4~0); 217608#L997-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 217609#L492 assume !(1 == ~t6_pc~0); 217615#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 217307#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 217267#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 217268#L1005 assume !(0 != activate_threads_~tmp___5~0); 217506#L1005-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 216686#L511 assume !(1 == ~t7_pc~0); 216687#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 216899#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 217322#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 217179#L1013 assume !(0 != activate_threads_~tmp___6~0); 217171#L1013-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 217172#L859 assume !(1 == ~M_E~0); 217158#L859-2 assume !(1 == ~T1_E~0); 216870#L864-1 assume !(1 == ~T2_E~0); 216871#L869-1 assume !(1 == ~T3_E~0); 217323#L874-1 assume !(1 == ~T4_E~0); 217121#L879-1 assume !(1 == ~T5_E~0); 216783#L884-1 assume !(1 == ~T6_E~0); 216784#L889-1 assume !(1 == ~T7_E~0); 217515#L894-1 assume !(1 == ~E_M~0); 217210#L899-1 assume !(1 == ~E_1~0); 216946#L904-1 assume !(1 == ~E_2~0); 216947#L909-1 assume !(1 == ~E_3~0); 217566#L914-1 assume !(1 == ~E_4~0); 217407#L919-1 assume !(1 == ~E_5~0); 217205#L924-1 assume !(1 == ~E_6~0); 216726#L929-1 assume !(1 == ~E_7~0); 216727#L934-1 assume { :end_inline_reset_delta_events } true; 217544#L1180-3 assume true; 219574#L1180-1 assume !false; 219375#L1181 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 219373#L746 [2018-11-18 09:04:55,578 INFO L796 eck$LassoCheckResult]: Loop: 219373#L746 assume true; 219371#L638-1 assume !false; 219369#L639 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 219366#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 219364#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 219361#L629 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 219359#L643 assume 0 != eval_~tmp~0; 219356#L643-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 219354#L651 assume !(0 != eval_~tmp_ndt_1~0); 219353#L648 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 219351#L665 assume !(0 != eval_~tmp_ndt_2~0); 219352#L662 assume !(0 == ~t2_st~0); 219406#L676 assume !(0 == ~t3_st~0); 219402#L690 assume !(0 == ~t4_st~0); 219393#L704 assume !(0 == ~t5_st~0); 219383#L718 assume !(0 == ~t6_st~0); 219379#L732 assume !(0 == ~t7_st~0); 219373#L746 [2018-11-18 09:04:55,578 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:55,578 INFO L82 PathProgramCache]: Analyzing trace with hash 1816264822, now seen corresponding path program 2 times [2018-11-18 09:04:55,578 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:55,578 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:55,579 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:55,579 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:55,579 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:55,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:04:55,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:04:55,606 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:55,607 INFO L82 PathProgramCache]: Analyzing trace with hash 1207221344, now seen corresponding path program 2 times [2018-11-18 09:04:55,607 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:55,607 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:55,607 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:55,607 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 09:04:55,608 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:55,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:04:55,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:04:55,612 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:55,612 INFO L82 PathProgramCache]: Analyzing trace with hash 2124354699, now seen corresponding path program 1 times [2018-11-18 09:04:55,612 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:55,612 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:55,612 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:55,613 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 09:04:55,613 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:55,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:55,659 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:55,659 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:55,659 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:04:55,716 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:04:55,716 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:04:55,716 INFO L87 Difference]: Start difference. First operand 11506 states and 15328 transitions. cyclomatic complexity: 3830 Second operand 3 states. [2018-11-18 09:04:55,773 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:04:55,774 INFO L93 Difference]: Finished difference Result 22058 states and 29264 transitions. [2018-11-18 09:04:55,774 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:04:55,774 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22058 states and 29264 transitions. [2018-11-18 09:04:55,821 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 21824 [2018-11-18 09:04:55,850 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22058 states to 22058 states and 29264 transitions. [2018-11-18 09:04:55,850 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22058 [2018-11-18 09:04:55,859 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22058 [2018-11-18 09:04:55,859 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22058 states and 29264 transitions. [2018-11-18 09:04:55,868 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:04:55,869 INFO L705 BuchiCegarLoop]: Abstraction has 22058 states and 29264 transitions. [2018-11-18 09:04:55,877 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22058 states and 29264 transitions. [2018-11-18 09:04:55,960 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22058 to 21050. [2018-11-18 09:04:55,961 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21050 states. [2018-11-18 09:04:55,978 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21050 states to 21050 states and 27992 transitions. [2018-11-18 09:04:55,978 INFO L728 BuchiCegarLoop]: Abstraction has 21050 states and 27992 transitions. [2018-11-18 09:04:55,978 INFO L608 BuchiCegarLoop]: Abstraction has 21050 states and 27992 transitions. [2018-11-18 09:04:55,978 INFO L442 BuchiCegarLoop]: ======== Iteration 26============ [2018-11-18 09:04:55,978 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21050 states and 27992 transitions. [2018-11-18 09:04:56,015 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 20816 [2018-11-18 09:04:56,015 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:04:56,015 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:04:56,016 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:56,016 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:56,016 INFO L794 eck$LassoCheckResult]: Stem: 250758#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 250656#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 250657#L1143 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 250618#L531 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 250619#L538 assume 1 == ~m_i~0;~m_st~0 := 0; 251155#L538-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 250953#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 250846#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 250620#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 250621#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 251044#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 250832#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 250598#L573-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 250599#L771 assume !(0 == ~M_E~0); 250738#L771-2 assume !(0 == ~T1_E~0); 250429#L776-1 assume !(0 == ~T2_E~0); 250430#L781-1 assume !(0 == ~T3_E~0); 250911#L786-1 assume !(0 == ~T4_E~0); 250704#L791-1 assume !(0 == ~T5_E~0); 250362#L796-1 assume !(0 == ~T6_E~0); 250363#L801-1 assume !(0 == ~T7_E~0); 251122#L806-1 assume !(0 == ~E_M~0); 250793#L811-1 assume !(0 == ~E_1~0); 250537#L816-1 assume !(0 == ~E_2~0); 250538#L821-1 assume !(0 == ~E_3~0); 251186#L826-1 assume !(0 == ~E_4~0); 251002#L831-1 assume !(0 == ~E_5~0); 250779#L836-1 assume !(0 == ~E_6~0); 250275#L841-1 assume !(0 == ~E_7~0); 250276#L846-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 250346#L378 assume !(1 == ~m_pc~0); 250320#L378-2 is_master_triggered_~__retres1~0 := 0; 250321#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 250963#L390 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 251023#L957 assume !(0 != activate_threads_~tmp~1); 251220#L957-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 250574#L397 assume !(1 == ~t1_pc~0); 250575#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 250583#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 251028#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 250796#L965 assume !(0 != activate_threads_~tmp___0~0); 250786#L965-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 250787#L416 assume !(1 == ~t2_pc~0); 250683#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 250684#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 251156#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 250293#L973 assume !(0 != activate_threads_~tmp___1~0); 250294#L973-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 250298#L435 assume !(1 == ~t3_pc~0); 250986#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 250391#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 250392#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 251069#L981 assume !(0 != activate_threads_~tmp___2~0); 251058#L981-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 251059#L454 assume !(1 == ~t4_pc~0); 250956#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 250624#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 250340#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 250341#L989 assume !(0 != activate_threads_~tmp___3~0); 250708#L989-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 250712#L473 assume !(1 == ~t5_pc~0); 251208#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 250765#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 250601#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 250602#L997 assume !(0 != activate_threads_~tmp___4~0); 251249#L997-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 251250#L492 assume !(1 == ~t6_pc~0); 251255#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 250891#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 250847#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 250848#L1005 assume !(0 != activate_threads_~tmp___5~0); 251111#L1005-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 250263#L511 assume !(1 == ~t7_pc~0); 250264#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 250480#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 250908#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 250756#L1013 assume !(0 != activate_threads_~tmp___6~0); 250748#L1013-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 250749#L859 assume !(1 == ~M_E~0); 250737#L859-2 assume !(1 == ~T1_E~0); 250446#L864-1 assume !(1 == ~T2_E~0); 250447#L869-1 assume !(1 == ~T3_E~0); 250909#L874-1 assume !(1 == ~T4_E~0); 250699#L879-1 assume !(1 == ~T5_E~0); 250358#L884-1 assume !(1 == ~T6_E~0); 250359#L889-1 assume !(1 == ~T7_E~0); 251120#L894-1 assume !(1 == ~E_M~0); 250790#L899-1 assume !(1 == ~E_1~0); 250529#L904-1 assume !(1 == ~E_2~0); 250530#L909-1 assume !(1 == ~E_3~0); 251194#L914-1 assume !(1 == ~E_4~0); 251006#L919-1 assume !(1 == ~E_5~0); 250785#L924-1 assume !(1 == ~E_6~0); 250299#L929-1 assume !(1 == ~E_7~0); 250300#L934-1 assume { :end_inline_reset_delta_events } true; 251161#L1180-3 assume true; 259859#L1180-1 assume !false; 259334#L1181 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 259332#L746 [2018-11-18 09:04:56,016 INFO L796 eck$LassoCheckResult]: Loop: 259332#L746 assume true; 259330#L638-1 assume !false; 259328#L639 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 259323#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 259321#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 259319#L629 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 259317#L643 assume 0 != eval_~tmp~0; 259313#L643-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 259310#L651 assume !(0 != eval_~tmp_ndt_1~0); 259306#L648 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 259304#L665 assume !(0 != eval_~tmp_ndt_2~0); 259302#L662 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 256342#L679 assume !(0 != eval_~tmp_ndt_3~0); 259299#L676 assume !(0 == ~t3_st~0); 259298#L690 assume !(0 == ~t4_st~0); 259730#L704 assume !(0 == ~t5_st~0); 259342#L718 assume !(0 == ~t6_st~0); 259338#L732 assume !(0 == ~t7_st~0); 259332#L746 [2018-11-18 09:04:56,016 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:56,016 INFO L82 PathProgramCache]: Analyzing trace with hash 1816264822, now seen corresponding path program 3 times [2018-11-18 09:04:56,016 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:56,017 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:56,017 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:56,017 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:56,017 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:56,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:04:56,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:04:56,044 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:56,044 INFO L82 PathProgramCache]: Analyzing trace with hash -704151153, now seen corresponding path program 1 times [2018-11-18 09:04:56,044 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:56,044 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:56,045 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:56,045 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 09:04:56,045 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:56,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:04:56,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:04:56,049 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:56,049 INFO L82 PathProgramCache]: Analyzing trace with hash 1957179076, now seen corresponding path program 1 times [2018-11-18 09:04:56,049 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:56,049 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:56,050 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:56,050 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:56,050 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:56,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:56,083 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:56,083 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:56,083 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:04:56,162 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:04:56,162 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:04:56,162 INFO L87 Difference]: Start difference. First operand 21050 states and 27992 transitions. cyclomatic complexity: 6950 Second operand 3 states. [2018-11-18 09:04:56,246 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:04:56,246 INFO L93 Difference]: Finished difference Result 30110 states and 39966 transitions. [2018-11-18 09:04:56,247 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:04:56,247 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30110 states and 39966 transitions. [2018-11-18 09:04:56,313 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 29836 [2018-11-18 09:04:56,356 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30110 states to 30110 states and 39966 transitions. [2018-11-18 09:04:56,356 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30110 [2018-11-18 09:04:56,369 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30110 [2018-11-18 09:04:56,369 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30110 states and 39966 transitions. [2018-11-18 09:04:56,381 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:04:56,381 INFO L705 BuchiCegarLoop]: Abstraction has 30110 states and 39966 transitions. [2018-11-18 09:04:56,392 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30110 states and 39966 transitions. [2018-11-18 09:04:56,619 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30110 to 29258. [2018-11-18 09:04:56,619 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29258 states. [2018-11-18 09:04:56,645 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29258 states to 29258 states and 38874 transitions. [2018-11-18 09:04:56,645 INFO L728 BuchiCegarLoop]: Abstraction has 29258 states and 38874 transitions. [2018-11-18 09:04:56,645 INFO L608 BuchiCegarLoop]: Abstraction has 29258 states and 38874 transitions. [2018-11-18 09:04:56,646 INFO L442 BuchiCegarLoop]: ======== Iteration 27============ [2018-11-18 09:04:56,646 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29258 states and 38874 transitions. [2018-11-18 09:04:56,696 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 28984 [2018-11-18 09:04:56,696 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:04:56,697 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:04:56,697 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:56,697 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:56,698 INFO L794 eck$LassoCheckResult]: Stem: 301935#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 301826#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 301827#L1143 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 301784#L531 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 301785#L538 assume 1 == ~m_i~0;~m_st~0 := 0; 302328#L538-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 302136#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 302026#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 301786#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 301787#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 302221#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 302011#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 301764#L573-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 301765#L771 assume !(0 == ~M_E~0); 301912#L771-2 assume !(0 == ~T1_E~0); 301594#L776-1 assume !(0 == ~T2_E~0); 301595#L781-1 assume !(0 == ~T3_E~0); 302096#L786-1 assume !(0 == ~T4_E~0); 301876#L791-1 assume !(0 == ~T5_E~0); 301529#L796-1 assume !(0 == ~T6_E~0); 301530#L801-1 assume !(0 == ~T7_E~0); 302299#L806-1 assume !(0 == ~E_M~0); 301969#L811-1 assume !(0 == ~E_1~0); 301699#L816-1 assume !(0 == ~E_2~0); 301700#L821-1 assume !(0 == ~E_3~0); 302355#L826-1 assume !(0 == ~E_4~0); 302176#L831-1 assume !(0 == ~E_5~0); 301955#L836-1 assume !(0 == ~E_6~0); 301439#L841-1 assume !(0 == ~E_7~0); 301440#L846-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 301515#L378 assume !(1 == ~m_pc~0); 301490#L378-2 is_master_triggered_~__retres1~0 := 0; 301491#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 302143#L390 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 302200#L957 assume !(0 != activate_threads_~tmp~1); 302389#L957-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 301739#L397 assume !(1 == ~t1_pc~0); 301740#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 301747#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 302206#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 301972#L965 assume !(0 != activate_threads_~tmp___0~0); 301962#L965-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 301963#L416 assume !(1 == ~t2_pc~0); 301852#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 301853#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 302329#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 301460#L973 assume !(0 != activate_threads_~tmp___1~0); 301461#L973-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 301466#L435 assume !(1 == ~t3_pc~0); 302165#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 301555#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 301556#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 302247#L981 assume !(0 != activate_threads_~tmp___2~0); 302236#L981-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 302237#L454 assume !(1 == ~t4_pc~0); 302140#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 301790#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 301509#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 301510#L989 assume !(0 != activate_threads_~tmp___3~0); 301884#L989-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 301886#L473 assume !(1 == ~t5_pc~0); 302378#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 301940#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 301767#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 301768#L997 assume !(0 != activate_threads_~tmp___4~0); 302412#L997-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 302413#L492 assume !(1 == ~t6_pc~0); 302417#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 302075#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 302027#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 302028#L1005 assume !(0 != activate_threads_~tmp___5~0); 302286#L1005-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 301428#L511 assume !(1 == ~t7_pc~0); 301429#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 301645#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 302433#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 301933#L1013 assume !(0 != activate_threads_~tmp___6~0); 301924#L1013-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 301925#L859 assume !(1 == ~M_E~0); 301911#L859-2 assume !(1 == ~T1_E~0); 301612#L864-1 assume !(1 == ~T2_E~0); 301613#L869-1 assume !(1 == ~T3_E~0); 302094#L874-1 assume !(1 == ~T4_E~0); 301870#L879-1 assume !(1 == ~T5_E~0); 301525#L884-1 assume !(1 == ~T6_E~0); 301526#L889-1 assume !(1 == ~T7_E~0); 302297#L894-1 assume !(1 == ~E_M~0); 301964#L899-1 assume !(1 == ~E_1~0); 301692#L904-1 assume !(1 == ~E_2~0); 301693#L909-1 assume !(1 == ~E_3~0); 302360#L914-1 assume !(1 == ~E_4~0); 302180#L919-1 assume !(1 == ~E_5~0); 301961#L924-1 assume !(1 == ~E_6~0); 301469#L929-1 assume !(1 == ~E_7~0); 301470#L934-1 assume { :end_inline_reset_delta_events } true; 302335#L1180-3 assume true; 314092#L1180-1 assume !false; 313602#L1181 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 313600#L746 [2018-11-18 09:04:56,698 INFO L796 eck$LassoCheckResult]: Loop: 313600#L746 assume true; 313598#L638-1 assume !false; 313594#L639 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 313591#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 313589#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 313586#L629 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 313584#L643 assume 0 != eval_~tmp~0; 313581#L643-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 313578#L651 assume !(0 != eval_~tmp_ndt_1~0); 313576#L648 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 313573#L665 assume !(0 != eval_~tmp_ndt_2~0); 313574#L662 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 313728#L679 assume !(0 != eval_~tmp_ndt_3~0); 313726#L676 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 313723#L693 assume !(0 != eval_~tmp_ndt_4~0); 313721#L690 assume !(0 == ~t4_st~0); 313714#L704 assume !(0 == ~t5_st~0); 313611#L718 assume !(0 == ~t6_st~0); 313606#L732 assume !(0 == ~t7_st~0); 313600#L746 [2018-11-18 09:04:56,698 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:56,698 INFO L82 PathProgramCache]: Analyzing trace with hash 1816264822, now seen corresponding path program 4 times [2018-11-18 09:04:56,698 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:56,698 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:56,699 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:56,699 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:56,699 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:56,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:04:56,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:04:56,725 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:56,725 INFO L82 PathProgramCache]: Analyzing trace with hash 1602806006, now seen corresponding path program 1 times [2018-11-18 09:04:56,725 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:56,725 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:56,726 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:56,726 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 09:04:56,726 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:56,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:04:56,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:04:56,730 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:56,730 INFO L82 PathProgramCache]: Analyzing trace with hash -1795302815, now seen corresponding path program 1 times [2018-11-18 09:04:56,730 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:56,730 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:56,731 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:56,731 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:56,731 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:56,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:56,767 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:56,767 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:56,767 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:04:56,846 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:04:56,847 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:04:56,847 INFO L87 Difference]: Start difference. First operand 29258 states and 38874 transitions. cyclomatic complexity: 9624 Second operand 3 states. [2018-11-18 09:04:56,988 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:04:56,988 INFO L93 Difference]: Finished difference Result 55366 states and 73386 transitions. [2018-11-18 09:04:56,988 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:04:56,989 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55366 states and 73386 transitions. [2018-11-18 09:04:57,115 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 54924 [2018-11-18 09:04:57,196 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55366 states to 55366 states and 73386 transitions. [2018-11-18 09:04:57,196 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 55366 [2018-11-18 09:04:57,218 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 55366 [2018-11-18 09:04:57,219 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55366 states and 73386 transitions. [2018-11-18 09:04:57,240 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:04:57,240 INFO L705 BuchiCegarLoop]: Abstraction has 55366 states and 73386 transitions. [2018-11-18 09:04:57,260 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55366 states and 73386 transitions. [2018-11-18 09:04:57,488 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55366 to 53314. [2018-11-18 09:04:57,488 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 53314 states. [2018-11-18 09:04:57,542 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53314 states to 53314 states and 70830 transitions. [2018-11-18 09:04:57,542 INFO L728 BuchiCegarLoop]: Abstraction has 53314 states and 70830 transitions. [2018-11-18 09:04:57,542 INFO L608 BuchiCegarLoop]: Abstraction has 53314 states and 70830 transitions. [2018-11-18 09:04:57,542 INFO L442 BuchiCegarLoop]: ======== Iteration 28============ [2018-11-18 09:04:57,542 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 53314 states and 70830 transitions. [2018-11-18 09:04:57,651 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 52872 [2018-11-18 09:04:57,651 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:04:57,651 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:04:57,652 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:57,652 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:57,652 INFO L794 eck$LassoCheckResult]: Stem: 386550#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 386447#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 386448#L1143 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 386415#L531 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 386416#L538 assume 1 == ~m_i~0;~m_st~0 := 0; 386950#L538-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 386744#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 386633#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 386417#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 386418#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 386838#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 386620#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 386395#L573-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 386396#L771 assume !(0 == ~M_E~0); 386529#L771-2 assume !(0 == ~T1_E~0); 386224#L776-1 assume !(0 == ~T2_E~0); 386225#L781-1 assume !(0 == ~T3_E~0); 386703#L786-1 assume !(0 == ~T4_E~0); 386495#L791-1 assume !(0 == ~T5_E~0); 386158#L796-1 assume !(0 == ~T6_E~0); 386159#L801-1 assume !(0 == ~T7_E~0); 386920#L806-1 assume !(0 == ~E_M~0); 386586#L811-1 assume !(0 == ~E_1~0); 386333#L816-1 assume !(0 == ~E_2~0); 386334#L821-1 assume !(0 == ~E_3~0); 386978#L826-1 assume !(0 == ~E_4~0); 386793#L831-1 assume !(0 == ~E_5~0); 386572#L836-1 assume !(0 == ~E_6~0); 386069#L841-1 assume !(0 == ~E_7~0); 386070#L846-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 386144#L378 assume !(1 == ~m_pc~0); 386118#L378-2 is_master_triggered_~__retres1~0 := 0; 386119#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 386753#L390 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 386817#L957 assume !(0 != activate_threads_~tmp~1); 387015#L957-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 386370#L397 assume !(1 == ~t1_pc~0); 386371#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 386378#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 386822#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 386589#L965 assume !(0 != activate_threads_~tmp___0~0); 386580#L965-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 386581#L416 assume !(1 == ~t2_pc~0); 386472#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 386473#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 386951#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 386089#L973 assume !(0 != activate_threads_~tmp___1~0); 386090#L973-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 386095#L435 assume !(1 == ~t3_pc~0); 386777#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 386184#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 386185#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 386863#L981 assume !(0 != activate_threads_~tmp___2~0); 386851#L981-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 386852#L454 assume !(1 == ~t4_pc~0); 386748#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 386421#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 386138#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 386139#L989 assume !(0 != activate_threads_~tmp___3~0); 386500#L989-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 386502#L473 assume !(1 == ~t5_pc~0); 387005#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 386556#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 386398#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 386399#L997 assume !(0 != activate_threads_~tmp___4~0); 387040#L997-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 387041#L492 assume !(1 == ~t6_pc~0); 387047#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 386680#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 386634#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 386635#L1005 assume !(0 != activate_threads_~tmp___5~0); 386905#L1005-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 386058#L511 assume !(1 == ~t7_pc~0); 386059#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 386276#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 387066#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 386548#L1013 assume !(0 != activate_threads_~tmp___6~0); 386540#L1013-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 386541#L859 assume !(1 == ~M_E~0); 386528#L859-2 assume !(1 == ~T1_E~0); 386244#L864-1 assume !(1 == ~T2_E~0); 386245#L869-1 assume !(1 == ~T3_E~0); 386701#L874-1 assume !(1 == ~T4_E~0); 386487#L879-1 assume !(1 == ~T5_E~0); 386154#L884-1 assume !(1 == ~T6_E~0); 386155#L889-1 assume !(1 == ~T7_E~0); 386917#L894-1 assume !(1 == ~E_M~0); 386582#L899-1 assume !(1 == ~E_1~0); 386326#L904-1 assume !(1 == ~E_2~0); 386327#L909-1 assume !(1 == ~E_3~0); 386984#L914-1 assume !(1 == ~E_4~0); 386799#L919-1 assume !(1 == ~E_5~0); 386579#L924-1 assume !(1 == ~E_6~0); 386098#L929-1 assume !(1 == ~E_7~0); 386099#L934-1 assume { :end_inline_reset_delta_events } true; 386957#L1180-3 assume true; 410198#L1180-1 assume !false; 410179#L1181 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 410171#L746 [2018-11-18 09:04:57,653 INFO L796 eck$LassoCheckResult]: Loop: 410171#L746 assume true; 410162#L638-1 assume !false; 410154#L639 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 410144#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 410135#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 410129#L629 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 410087#L643 assume 0 != eval_~tmp~0; 410079#L643-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 410069#L651 assume !(0 != eval_~tmp_ndt_1~0); 410062#L648 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 410056#L665 assume !(0 != eval_~tmp_ndt_2~0); 408269#L662 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 408267#L679 assume !(0 != eval_~tmp_ndt_3~0); 408264#L676 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 408261#L693 assume !(0 != eval_~tmp_ndt_4~0); 408262#L690 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 399079#L707 assume !(0 != eval_~tmp_ndt_5~0); 410335#L704 assume !(0 == ~t5_st~0); 410203#L718 assume !(0 == ~t6_st~0); 410183#L732 assume !(0 == ~t7_st~0); 410171#L746 [2018-11-18 09:04:57,653 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:57,653 INFO L82 PathProgramCache]: Analyzing trace with hash 1816264822, now seen corresponding path program 5 times [2018-11-18 09:04:57,653 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:57,653 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:57,654 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:57,654 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:57,654 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:57,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:04:57,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:04:57,683 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:57,683 INFO L82 PathProgramCache]: Analyzing trace with hash -2066595591, now seen corresponding path program 1 times [2018-11-18 09:04:57,683 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:57,683 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:57,684 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:57,684 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 09:04:57,684 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:57,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:04:57,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:04:57,689 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:57,689 INFO L82 PathProgramCache]: Analyzing trace with hash -33786642, now seen corresponding path program 1 times [2018-11-18 09:04:57,689 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:57,689 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:57,690 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:57,690 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:57,690 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:57,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:57,745 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:57,745 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:57,745 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:04:57,833 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:04:57,834 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:04:57,834 INFO L87 Difference]: Start difference. First operand 53314 states and 70830 transitions. cyclomatic complexity: 17524 Second operand 3 states. [2018-11-18 09:04:58,213 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:04:58,213 INFO L93 Difference]: Finished difference Result 76572 states and 101631 transitions. [2018-11-18 09:04:58,214 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:04:58,214 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 76572 states and 101631 transitions. [2018-11-18 09:04:58,394 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 76034 [2018-11-18 09:04:58,493 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 76572 states to 76572 states and 101631 transitions. [2018-11-18 09:04:58,493 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 76572 [2018-11-18 09:04:58,517 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 76572 [2018-11-18 09:04:58,517 INFO L73 IsDeterministic]: Start isDeterministic. Operand 76572 states and 101631 transitions. [2018-11-18 09:04:58,540 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:04:58,540 INFO L705 BuchiCegarLoop]: Abstraction has 76572 states and 101631 transitions. [2018-11-18 09:04:58,563 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76572 states and 101631 transitions. [2018-11-18 09:04:58,857 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76572 to 74988. [2018-11-18 09:04:58,857 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74988 states. [2018-11-18 09:04:58,931 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74988 states to 74988 states and 99615 transitions. [2018-11-18 09:04:58,931 INFO L728 BuchiCegarLoop]: Abstraction has 74988 states and 99615 transitions. [2018-11-18 09:04:58,931 INFO L608 BuchiCegarLoop]: Abstraction has 74988 states and 99615 transitions. [2018-11-18 09:04:58,931 INFO L442 BuchiCegarLoop]: ======== Iteration 29============ [2018-11-18 09:04:58,931 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 74988 states and 99615 transitions. [2018-11-18 09:04:59,068 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 74450 [2018-11-18 09:04:59,068 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:04:59,068 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:04:59,069 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:59,069 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:04:59,069 INFO L794 eck$LassoCheckResult]: Stem: 516437#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 516336#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 516337#L1143 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 516303#L531 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 516304#L538 assume 1 == ~m_i~0;~m_st~0 := 0; 516814#L538-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 516617#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 516516#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 516305#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 516306#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 516704#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 516504#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 516283#L573-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 516284#L771 assume !(0 == ~M_E~0); 516417#L771-2 assume !(0 == ~T1_E~0); 516118#L776-1 assume !(0 == ~T2_E~0); 516119#L781-1 assume !(0 == ~T3_E~0); 516577#L786-1 assume !(0 == ~T4_E~0); 516384#L791-1 assume !(0 == ~T5_E~0); 516052#L796-1 assume !(0 == ~T6_E~0); 516053#L801-1 assume !(0 == ~T7_E~0); 516789#L806-1 assume !(0 == ~E_M~0); 516469#L811-1 assume !(0 == ~E_1~0); 516225#L816-1 assume !(0 == ~E_2~0); 516226#L821-1 assume !(0 == ~E_3~0); 516840#L826-1 assume !(0 == ~E_4~0); 516662#L831-1 assume !(0 == ~E_5~0); 516456#L836-1 assume !(0 == ~E_6~0); 515965#L841-1 assume !(0 == ~E_7~0); 515966#L846-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 516038#L378 assume !(1 == ~m_pc~0); 516013#L378-2 is_master_triggered_~__retres1~0 := 0; 516014#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 516624#L390 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 516684#L957 assume !(0 != activate_threads_~tmp~1); 516871#L957-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 516259#L397 assume !(1 == ~t1_pc~0); 516260#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 516267#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 516688#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 516472#L965 assume !(0 != activate_threads_~tmp___0~0); 516462#L965-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 516463#L416 assume !(1 == ~t2_pc~0); 516361#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 516362#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 516815#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 515985#L973 assume !(0 != activate_threads_~tmp___1~0); 515986#L973-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 515991#L435 assume !(1 == ~t3_pc~0); 516646#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 516078#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 516079#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 516730#L981 assume !(0 != activate_threads_~tmp___2~0); 516718#L981-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 516719#L454 assume !(1 == ~t4_pc~0); 516621#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 516309#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 516032#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 516033#L989 assume !(0 != activate_threads_~tmp___3~0); 516389#L989-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 516391#L473 assume !(1 == ~t5_pc~0); 516861#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 516442#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 516286#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 516287#L997 assume !(0 != activate_threads_~tmp___4~0); 516896#L997-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 516897#L492 assume !(1 == ~t6_pc~0); 516904#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 516560#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 516517#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 516518#L1005 assume !(0 != activate_threads_~tmp___5~0); 516775#L1005-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 515953#L511 assume !(1 == ~t7_pc~0); 515954#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 516169#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 516574#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 516435#L1013 assume !(0 != activate_threads_~tmp___6~0); 516427#L1013-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 516428#L859 assume !(1 == ~M_E~0); 516416#L859-2 assume !(1 == ~T1_E~0); 516137#L864-1 assume !(1 == ~T2_E~0); 516138#L869-1 assume !(1 == ~T3_E~0); 516575#L874-1 assume !(1 == ~T4_E~0); 516377#L879-1 assume !(1 == ~T5_E~0); 516048#L884-1 assume !(1 == ~T6_E~0); 516049#L889-1 assume !(1 == ~T7_E~0); 516787#L894-1 assume !(1 == ~E_M~0); 516464#L899-1 assume !(1 == ~E_1~0); 516218#L904-1 assume !(1 == ~E_2~0); 516219#L909-1 assume !(1 == ~E_3~0); 516845#L914-1 assume !(1 == ~E_4~0); 516666#L919-1 assume !(1 == ~E_5~0); 516461#L924-1 assume !(1 == ~E_6~0); 515994#L929-1 assume !(1 == ~E_7~0); 515995#L934-1 assume { :end_inline_reset_delta_events } true; 516821#L1180-3 assume true; 555115#L1180-1 assume !false; 555036#L1181 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 555033#L746 [2018-11-18 09:04:59,069 INFO L796 eck$LassoCheckResult]: Loop: 555033#L746 assume true; 555031#L638-1 assume !false; 555029#L639 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 555026#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 555024#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 555022#L629 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 555020#L643 assume 0 != eval_~tmp~0; 555018#L643-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 555015#L651 assume !(0 != eval_~tmp_ndt_1~0); 555016#L648 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 555561#L665 assume !(0 != eval_~tmp_ndt_2~0); 555559#L662 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 554000#L679 assume !(0 != eval_~tmp_ndt_3~0); 555059#L676 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 555055#L693 assume !(0 != eval_~tmp_ndt_4~0); 555053#L690 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 554145#L707 assume !(0 != eval_~tmp_ndt_5~0); 555048#L704 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 555046#L721 assume !(0 != eval_~tmp_ndt_6~0); 555043#L718 assume !(0 == ~t6_st~0); 555040#L732 assume !(0 == ~t7_st~0); 555033#L746 [2018-11-18 09:04:59,069 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:59,069 INFO L82 PathProgramCache]: Analyzing trace with hash 1816264822, now seen corresponding path program 6 times [2018-11-18 09:04:59,069 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:59,069 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:59,070 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:59,070 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:59,070 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:59,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:04:59,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:04:59,099 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:59,099 INFO L82 PathProgramCache]: Analyzing trace with hash 353146252, now seen corresponding path program 1 times [2018-11-18 09:04:59,099 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:59,099 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:59,100 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:59,100 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 09:04:59,100 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:59,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:04:59,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:04:59,104 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:04:59,105 INFO L82 PathProgramCache]: Analyzing trace with hash -1054285769, now seen corresponding path program 1 times [2018-11-18 09:04:59,105 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:04:59,105 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:04:59,105 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:59,105 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:04:59,106 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:04:59,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:04:59,148 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:04:59,148 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:04:59,148 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:04:59,268 WARN L180 SmtUtils]: Spent 117.00 ms on a formula simplification. DAG size of input: 53 DAG size of output: 51 [2018-11-18 09:04:59,328 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:04:59,328 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:04:59,328 INFO L87 Difference]: Start difference. First operand 74988 states and 99615 transitions. cyclomatic complexity: 24635 Second operand 3 states. [2018-11-18 09:04:59,908 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:04:59,908 INFO L93 Difference]: Finished difference Result 138166 states and 183115 transitions. [2018-11-18 09:04:59,908 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:04:59,908 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 138166 states and 183115 transitions. [2018-11-18 09:05:00,241 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 137196 [2018-11-18 09:05:00,453 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 138166 states to 138166 states and 183115 transitions. [2018-11-18 09:05:00,453 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 138166 [2018-11-18 09:05:00,509 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 138166 [2018-11-18 09:05:00,509 INFO L73 IsDeterministic]: Start isDeterministic. Operand 138166 states and 183115 transitions. [2018-11-18 09:05:00,555 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:05:00,555 INFO L705 BuchiCegarLoop]: Abstraction has 138166 states and 183115 transitions. [2018-11-18 09:05:00,605 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 138166 states and 183115 transitions. [2018-11-18 09:05:01,159 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 138166 to 134926. [2018-11-18 09:05:01,159 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 134926 states. [2018-11-18 09:05:01,295 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134926 states to 134926 states and 179227 transitions. [2018-11-18 09:05:01,295 INFO L728 BuchiCegarLoop]: Abstraction has 134926 states and 179227 transitions. [2018-11-18 09:05:01,296 INFO L608 BuchiCegarLoop]: Abstraction has 134926 states and 179227 transitions. [2018-11-18 09:05:01,296 INFO L442 BuchiCegarLoop]: ======== Iteration 30============ [2018-11-18 09:05:01,296 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 134926 states and 179227 transitions. [2018-11-18 09:05:01,873 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 133956 [2018-11-18 09:05:01,873 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:05:01,874 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:05:01,874 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:05:01,874 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:05:01,875 INFO L794 eck$LassoCheckResult]: Stem: 729620#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 729512#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 729513#L1143 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 729474#L531 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 729475#L538 assume 1 == ~m_i~0;~m_st~0 := 0; 730028#L538-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 729824#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 729710#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 729476#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 729477#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 729913#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 729690#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 729454#L573-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 729455#L771 assume !(0 == ~M_E~0); 729600#L771-2 assume !(0 == ~T1_E~0); 729281#L776-1 assume !(0 == ~T2_E~0); 729282#L781-1 assume !(0 == ~T3_E~0); 729781#L786-1 assume !(0 == ~T4_E~0); 729566#L791-1 assume !(0 == ~T5_E~0); 729216#L796-1 assume !(0 == ~T6_E~0); 729217#L801-1 assume !(0 == ~T7_E~0); 729997#L806-1 assume !(0 == ~E_M~0); 729652#L811-1 assume !(0 == ~E_1~0); 729388#L816-1 assume !(0 == ~E_2~0); 729389#L821-1 assume !(0 == ~E_3~0); 730060#L826-1 assume !(0 == ~E_4~0); 729869#L831-1 assume !(0 == ~E_5~0); 729640#L836-1 assume !(0 == ~E_6~0); 729127#L841-1 assume !(0 == ~E_7~0); 729128#L846-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 729202#L378 assume !(1 == ~m_pc~0); 729176#L378-2 is_master_triggered_~__retres1~0 := 0; 729177#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 729832#L390 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 729890#L957 assume !(0 != activate_threads_~tmp~1); 730098#L957-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 729426#L397 assume !(1 == ~t1_pc~0); 729427#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 729435#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 729895#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 729655#L965 assume !(0 != activate_threads_~tmp___0~0); 729646#L965-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 729647#L416 assume !(1 == ~t2_pc~0); 729542#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 729543#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 730029#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 729147#L973 assume !(0 != activate_threads_~tmp___1~0); 729148#L973-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 729154#L435 assume !(1 == ~t3_pc~0); 729857#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 729242#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 729243#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 729938#L981 assume !(0 != activate_threads_~tmp___2~0); 729927#L981-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 729928#L454 assume !(1 == ~t4_pc~0); 729828#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 729480#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 729196#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 729197#L989 assume !(0 != activate_threads_~tmp___3~0); 729571#L989-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 729573#L473 assume !(1 == ~t5_pc~0); 730087#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 729626#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 729457#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 729458#L997 assume !(0 != activate_threads_~tmp___4~0); 730128#L997-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 730129#L492 assume !(1 == ~t6_pc~0); 730134#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 729758#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 729711#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 729712#L1005 assume !(0 != activate_threads_~tmp___5~0); 729982#L1005-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 729115#L511 assume !(1 == ~t7_pc~0); 729116#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 729335#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 729778#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 729618#L1013 assume !(0 != activate_threads_~tmp___6~0); 729610#L1013-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 729611#L859 assume !(1 == ~M_E~0); 729599#L859-2 assume !(1 == ~T1_E~0); 729301#L864-1 assume !(1 == ~T2_E~0); 729302#L869-1 assume !(1 == ~T3_E~0); 729779#L874-1 assume !(1 == ~T4_E~0); 729560#L879-1 assume !(1 == ~T5_E~0); 729212#L884-1 assume !(1 == ~T6_E~0); 729213#L889-1 assume !(1 == ~T7_E~0); 729995#L894-1 assume !(1 == ~E_M~0); 729648#L899-1 assume !(1 == ~E_1~0); 729381#L904-1 assume !(1 == ~E_2~0); 729382#L909-1 assume !(1 == ~E_3~0); 730067#L914-1 assume !(1 == ~E_4~0); 729874#L919-1 assume !(1 == ~E_5~0); 729645#L924-1 assume !(1 == ~E_6~0); 729157#L929-1 assume !(1 == ~E_7~0); 729158#L934-1 assume { :end_inline_reset_delta_events } true; 730036#L1180-3 assume true; 849551#L1180-1 assume !false; 777880#L1181 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 777878#L746 [2018-11-18 09:05:01,875 INFO L796 eck$LassoCheckResult]: Loop: 777878#L746 assume true; 777876#L638-1 assume !false; 777874#L639 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 777870#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 777868#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 777866#L629 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 777864#L643 assume 0 != eval_~tmp~0; 777861#L643-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 777859#L651 assume !(0 != eval_~tmp_ndt_1~0); 777855#L648 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 777853#L665 assume !(0 != eval_~tmp_ndt_2~0); 777851#L662 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 777833#L679 assume !(0 != eval_~tmp_ndt_3~0); 777849#L676 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 797491#L693 assume !(0 != eval_~tmp_ndt_4~0); 777897#L690 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 777894#L707 assume !(0 != eval_~tmp_ndt_5~0); 777892#L704 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 777890#L721 assume !(0 != eval_~tmp_ndt_6~0); 777888#L718 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 754067#L735 assume !(0 != eval_~tmp_ndt_7~0); 777884#L732 assume !(0 == ~t7_st~0); 777878#L746 [2018-11-18 09:05:01,875 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:05:01,875 INFO L82 PathProgramCache]: Analyzing trace with hash 1816264822, now seen corresponding path program 7 times [2018-11-18 09:05:01,875 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:05:01,875 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:05:01,876 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:05:01,876 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:05:01,876 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:05:01,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:05:01,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:05:01,905 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:05:01,905 INFO L82 PathProgramCache]: Analyzing trace with hash -1937588125, now seen corresponding path program 1 times [2018-11-18 09:05:01,905 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:05:01,905 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:05:01,906 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:05:01,906 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:05:01,906 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:05:01,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:05:01,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:05:01,911 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:05:01,911 INFO L82 PathProgramCache]: Analyzing trace with hash 1676659480, now seen corresponding path program 1 times [2018-11-18 09:05:01,911 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:05:01,911 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:05:01,912 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:05:01,912 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:05:01,912 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:05:01,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:05:01,967 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:05:01,967 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:05:01,967 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 09:05:02,129 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:05:02,129 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:05:02,129 INFO L87 Difference]: Start difference. First operand 134926 states and 179227 transitions. cyclomatic complexity: 44309 Second operand 3 states. [2018-11-18 09:05:02,623 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:05:02,624 INFO L93 Difference]: Finished difference Result 240554 states and 318830 transitions. [2018-11-18 09:05:02,625 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:05:02,625 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 240554 states and 318830 transitions. [2018-11-18 09:05:03,275 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 238720 [2018-11-18 09:05:03,661 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 240554 states to 240554 states and 318830 transitions. [2018-11-18 09:05:03,662 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 240554 [2018-11-18 09:05:03,760 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 240554 [2018-11-18 09:05:03,760 INFO L73 IsDeterministic]: Start isDeterministic. Operand 240554 states and 318830 transitions. [2018-11-18 09:05:03,838 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:05:03,838 INFO L705 BuchiCegarLoop]: Abstraction has 240554 states and 318830 transitions. [2018-11-18 09:05:03,930 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 240554 states and 318830 transitions. [2018-11-18 09:05:08,349 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 240554 to 238394. [2018-11-18 09:05:08,349 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 238394 states. [2018-11-18 09:05:08,622 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 238394 states to 238394 states and 316670 transitions. [2018-11-18 09:05:08,622 INFO L728 BuchiCegarLoop]: Abstraction has 238394 states and 316670 transitions. [2018-11-18 09:05:08,622 INFO L608 BuchiCegarLoop]: Abstraction has 238394 states and 316670 transitions. [2018-11-18 09:05:08,622 INFO L442 BuchiCegarLoop]: ======== Iteration 31============ [2018-11-18 09:05:08,622 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 238394 states and 316670 transitions. [2018-11-18 09:05:09,115 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 236560 [2018-11-18 09:05:09,115 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:05:09,115 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:05:09,116 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:05:09,116 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:05:09,116 INFO L794 eck$LassoCheckResult]: Stem: 1105114#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1105006#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1105007#L1143 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 1104968#L531 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1104969#L538 assume 1 == ~m_i~0;~m_st~0 := 0; 1105519#L538-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1105316#L543-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1105198#L548-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1104970#L553-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1104971#L558-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1105412#L563-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1105184#L568-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1104946#L573-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1104947#L771 assume !(0 == ~M_E~0); 1105093#L771-2 assume !(0 == ~T1_E~0); 1104769#L776-1 assume !(0 == ~T2_E~0); 1104770#L781-1 assume !(0 == ~T3_E~0); 1105267#L786-1 assume !(0 == ~T4_E~0); 1105058#L791-1 assume !(0 == ~T5_E~0); 1104701#L796-1 assume !(0 == ~T6_E~0); 1104702#L801-1 assume !(0 == ~T7_E~0); 1105492#L806-1 assume !(0 == ~E_M~0); 1105147#L811-1 assume !(0 == ~E_1~0); 1104881#L816-1 assume !(0 == ~E_2~0); 1104882#L821-1 assume !(0 == ~E_3~0); 1105547#L826-1 assume !(0 == ~E_4~0); 1105370#L831-1 assume !(0 == ~E_5~0); 1105134#L836-1 assume !(0 == ~E_6~0); 1104615#L841-1 assume !(0 == ~E_7~0); 1104616#L846-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1104687#L378 assume !(1 == ~m_pc~0); 1104661#L378-2 is_master_triggered_~__retres1~0 := 0; 1104662#L389 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1105324#L390 activate_threads_#t~ret11 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1105390#L957 assume !(0 != activate_threads_~tmp~1); 1105579#L957-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1104920#L397 assume !(1 == ~t1_pc~0); 1104921#L397-2 is_transmit1_triggered_~__retres1~1 := 0; 1104929#L408 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1105396#L409 activate_threads_#t~ret12 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1105150#L965 assume !(0 != activate_threads_~tmp___0~0); 1105140#L965-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1105141#L416 assume !(1 == ~t2_pc~0); 1105033#L416-2 is_transmit2_triggered_~__retres1~2 := 0; 1105034#L427 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1105520#L428 activate_threads_#t~ret13 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1104633#L973 assume !(0 != activate_threads_~tmp___1~0); 1104634#L973-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1104639#L435 assume !(1 == ~t3_pc~0); 1105352#L435-2 is_transmit3_triggered_~__retres1~3 := 0; 1104730#L446 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1104731#L447 activate_threads_#t~ret14 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1105439#L981 assume !(0 != activate_threads_~tmp___2~0); 1105427#L981-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1105428#L454 assume !(1 == ~t4_pc~0); 1105319#L454-2 is_transmit4_triggered_~__retres1~4 := 0; 1104974#L465 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1104681#L466 activate_threads_#t~ret15 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1104682#L989 assume !(0 != activate_threads_~tmp___3~0); 1105064#L989-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1105066#L473 assume !(1 == ~t5_pc~0); 1105570#L473-2 is_transmit5_triggered_~__retres1~5 := 0; 1105120#L484 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1104949#L485 activate_threads_#t~ret16 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1104950#L997 assume !(0 != activate_threads_~tmp___4~0); 1105608#L997-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1105609#L492 assume !(1 == ~t6_pc~0); 1105617#L492-2 is_transmit6_triggered_~__retres1~6 := 0; 1105245#L503 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1105199#L504 activate_threads_#t~ret17 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1105200#L1005 assume !(0 != activate_threads_~tmp___5~0); 1105480#L1005-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1104603#L511 assume !(1 == ~t7_pc~0); 1104604#L511-2 is_transmit7_triggered_~__retres1~7 := 0; 1104827#L522 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1105264#L523 activate_threads_#t~ret18 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1105112#L1013 assume !(0 != activate_threads_~tmp___6~0); 1105104#L1013-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1105105#L859 assume !(1 == ~M_E~0); 1105092#L859-2 assume !(1 == ~T1_E~0); 1104790#L864-1 assume !(1 == ~T2_E~0); 1104791#L869-1 assume !(1 == ~T3_E~0); 1105265#L874-1 assume !(1 == ~T4_E~0); 1105052#L879-1 assume !(1 == ~T5_E~0); 1104697#L884-1 assume !(1 == ~T6_E~0); 1104698#L889-1 assume !(1 == ~T7_E~0); 1105490#L894-1 assume !(1 == ~E_M~0); 1105144#L899-1 assume !(1 == ~E_1~0); 1104874#L904-1 assume !(1 == ~E_2~0); 1104875#L909-1 assume !(1 == ~E_3~0); 1105555#L914-1 assume !(1 == ~E_4~0); 1105375#L919-1 assume !(1 == ~E_5~0); 1105139#L924-1 assume !(1 == ~E_6~0); 1104642#L929-1 assume !(1 == ~E_7~0); 1104643#L934-1 assume { :end_inline_reset_delta_events } true; 1105523#L1180-3 assume true; 1172420#L1180-1 assume !false; 1172415#L1181 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 1172414#L746 [2018-11-18 09:05:09,116 INFO L796 eck$LassoCheckResult]: Loop: 1172414#L746 assume true; 1172413#L638-1 assume !false; 1172412#L639 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 1172410#L586 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 1172409#L628 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 1172406#L629 eval_#t~ret2 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 1172403#L643 assume 0 != eval_~tmp~0; 1172400#L643-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 1172397#L651 assume !(0 != eval_~tmp_ndt_1~0); 1172394#L648 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 1156690#L665 assume !(0 != eval_~tmp_ndt_2~0); 1135660#L662 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 1135656#L679 assume !(0 != eval_~tmp_ndt_3~0); 1135654#L676 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 1135651#L693 assume !(0 != eval_~tmp_ndt_4~0); 1135574#L690 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 1135486#L707 assume !(0 != eval_~tmp_ndt_5~0); 1135559#L704 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 1137038#L721 assume !(0 != eval_~tmp_ndt_6~0); 1137033#L718 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 1136964#L735 assume !(0 != eval_~tmp_ndt_7~0); 1137031#L732 assume 0 == ~t7_st~0;havoc eval_~tmp_ndt_8~0;eval_~tmp_ndt_8~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 1158653#L749 assume !(0 != eval_~tmp_ndt_8~0); 1172414#L746 [2018-11-18 09:05:09,117 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:05:09,117 INFO L82 PathProgramCache]: Analyzing trace with hash 1816264822, now seen corresponding path program 8 times [2018-11-18 09:05:09,117 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:05:09,117 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:05:09,118 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:05:09,118 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:05:09,118 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:05:09,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:05:09,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:05:09,146 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:05:09,146 INFO L82 PathProgramCache]: Analyzing trace with hash 64305698, now seen corresponding path program 1 times [2018-11-18 09:05:09,146 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:05:09,147 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:05:09,147 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:05:09,147 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 09:05:09,147 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:05:09,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:05:09,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:05:09,152 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:05:09,152 INFO L82 PathProgramCache]: Analyzing trace with hash 436831757, now seen corresponding path program 1 times [2018-11-18 09:05:09,152 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:05:09,152 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:05:09,153 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:05:09,153 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:05:09,153 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:05:09,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:05:09,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:05:10,254 WARN L180 SmtUtils]: Spent 938.00 ms on a formula simplification. DAG size of input: 260 DAG size of output: 172 [2018-11-18 09:05:10,378 WARN L180 SmtUtils]: Spent 115.00 ms on a formula simplification that was a NOOP. DAG size: 138 [2018-11-18 09:05:10,409 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 18.11 09:05:10 BoogieIcfgContainer [2018-11-18 09:05:10,409 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2018-11-18 09:05:10,409 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-18 09:05:10,409 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-18 09:05:10,410 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-18 09:05:10,410 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 09:04:49" (3/4) ... [2018-11-18 09:05:10,412 INFO L141 WitnessPrinter]: Generating witness for non-termination counterexample [2018-11-18 09:05:10,466 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_b625e2b8-c366-4210-a7ec-394d99235a33/bin-2019/uautomizer/witness.graphml [2018-11-18 09:05:10,466 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-18 09:05:10,467 INFO L168 Benchmark]: Toolchain (without parser) took 22127.38 ms. Allocated memory was 1.0 GB in the beginning and 3.9 GB in the end (delta: 2.8 GB). Free memory was 959.2 MB in the beginning and 2.4 GB in the end (delta: -1.4 GB). Peak memory consumption was 1.4 GB. Max. memory is 11.5 GB. [2018-11-18 09:05:10,467 INFO L168 Benchmark]: CDTParser took 0.12 ms. Allocated memory is still 1.0 GB. Free memory is still 985.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 09:05:10,468 INFO L168 Benchmark]: CACSL2BoogieTranslator took 264.87 ms. Allocated memory is still 1.0 GB. Free memory was 959.2 MB in the beginning and 935.1 MB in the end (delta: 24.2 MB). Peak memory consumption was 24.2 MB. Max. memory is 11.5 GB. [2018-11-18 09:05:10,468 INFO L168 Benchmark]: Boogie Procedure Inliner took 97.20 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 177.2 MB). Free memory was 935.1 MB in the beginning and 1.2 GB in the end (delta: -230.2 MB). Peak memory consumption was 15.2 MB. Max. memory is 11.5 GB. [2018-11-18 09:05:10,468 INFO L168 Benchmark]: Boogie Preprocessor took 56.60 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 3.3 MB). Peak memory consumption was 3.3 MB. Max. memory is 11.5 GB. [2018-11-18 09:05:10,468 INFO L168 Benchmark]: RCFGBuilder took 1121.36 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 990.2 MB in the end (delta: 171.7 MB). Peak memory consumption was 171.7 MB. Max. memory is 11.5 GB. [2018-11-18 09:05:10,468 INFO L168 Benchmark]: BuchiAutomizer took 20527.30 ms. Allocated memory was 1.2 GB in the beginning and 3.9 GB in the end (delta: 2.7 GB). Free memory was 990.2 MB in the beginning and 2.4 GB in the end (delta: -1.4 GB). Peak memory consumption was 2.4 GB. Max. memory is 11.5 GB. [2018-11-18 09:05:10,468 INFO L168 Benchmark]: Witness Printer took 57.11 ms. Allocated memory is still 3.9 GB. Free memory was 2.4 GB in the beginning and 2.4 GB in the end (delta: 24 B). Peak memory consumption was 24 B. Max. memory is 11.5 GB. [2018-11-18 09:05:10,469 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.12 ms. Allocated memory is still 1.0 GB. Free memory is still 985.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 264.87 ms. Allocated memory is still 1.0 GB. Free memory was 959.2 MB in the beginning and 935.1 MB in the end (delta: 24.2 MB). Peak memory consumption was 24.2 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 97.20 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 177.2 MB). Free memory was 935.1 MB in the beginning and 1.2 GB in the end (delta: -230.2 MB). Peak memory consumption was 15.2 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 56.60 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 3.3 MB). Peak memory consumption was 3.3 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1121.36 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 990.2 MB in the end (delta: 171.7 MB). Peak memory consumption was 171.7 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 20527.30 ms. Allocated memory was 1.2 GB in the beginning and 3.9 GB in the end (delta: 2.7 GB). Free memory was 990.2 MB in the beginning and 2.4 GB in the end (delta: -1.4 GB). Peak memory consumption was 2.4 GB. Max. memory is 11.5 GB. * Witness Printer took 57.11 ms. Allocated memory is still 3.9 GB. Free memory was 2.4 GB in the beginning and 2.4 GB in the end (delta: 24 B). Peak memory consumption was 24 B. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 30 terminating modules (30 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.30 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 238394 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 20.4s and 31 iterations. TraceHistogramMax:1. Analysis of lassos took 4.5s. Construction of modules took 1.0s. Büchi inclusion checks took 2.2s. Highest rank in rank-based complementation 0. Minimization of det autom 30. Minimization of nondet autom 0. Automata minimization 7.5s AutomataMinimizationTime, 30 MinimizatonAttempts, 24461 StatesRemovedByMinimization, 14 NontrivialMinimizations. Non-live state removal took 2.7s Buchi closure took 0.2s. Biggest automaton had 238394 states and ocurred in iteration 30. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 37498 SDtfs, 36673 SDslu, 22359 SDs, 0 SdLazy, 601 SolverSat, 424 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.0s Time LassoAnalysisResults: nont1 unkn0 SFLI5 SFLT0 conc7 concLT0 SILN1 SILU0 SILI17 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 638]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {E_7=2, t3_st=0, __retres1=0, t5_i=1, __retres1=0, kernel_st=1, \result=0, E_3=2, T6_E=2, t7_i=1, tmp_ndt_8=0, tmp_ndt_4=0, \result=0, m_st=0, t6_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@52e13665=0, tmp___2=0, __retres1=0, t3_pc=0, \result=0, m_pc=0, tmp___6=0, t6_st=0, E_6=2, __retres1=0, \result=0, T2_E=2, t5_st=0, __retres1=1, E_2=2, t7_pc=0, tmp=0, M_E=2, tmp_ndt_3=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@62b5917=0, T4_E=2, t4_st=0, t3_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@71542739=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4545b58b=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@12e554d3=0, t5_pc=0, t7_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4e5a5fee=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1ee7cee4=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7666d44e=0, tmp_ndt_7=0, tmp___3=0, t1_i=1, __retres1=0, token=0, T7_E=2, tmp=1, t2_st=0, t4_i=1, t4_pc=0, E_5=2, \result=0, E_1=2, tmp_ndt_2=0, \result=0, __retres1=0, tmp_ndt_6=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@34848bec=0, tmp___0=0, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3db8657e=0, t6_i=1, tmp___4=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@248f6908=0, \result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@25613846=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@76c6b4e2=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@467cc222=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2a6fc873=0, tmp___0=0, t1_pc=0, E_4=2, T1_E=2, tmp_ndt_1=0, T5_E=2, t2_i=1, m_i=1, t1_st=0, tmp_ndt_5=0, local=0, __retres1=0, t2_pc=0, E_M=2, tmp___1=0, T3_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4df57b1b=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@82f27e8=0, \result=1, tmp___5=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@38bf20cf=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2e671b3f=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 638]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int t4_pc = 0; [L19] int t5_pc = 0; [L20] int t6_pc = 0; [L21] int t7_pc = 0; [L22] int m_st ; [L23] int t1_st ; [L24] int t2_st ; [L25] int t3_st ; [L26] int t4_st ; [L27] int t5_st ; [L28] int t6_st ; [L29] int t7_st ; [L30] int m_i ; [L31] int t1_i ; [L32] int t2_i ; [L33] int t3_i ; [L34] int t4_i ; [L35] int t5_i ; [L36] int t6_i ; [L37] int t7_i ; [L38] int M_E = 2; [L39] int T1_E = 2; [L40] int T2_E = 2; [L41] int T3_E = 2; [L42] int T4_E = 2; [L43] int T5_E = 2; [L44] int T6_E = 2; [L45] int T7_E = 2; [L46] int E_M = 2; [L47] int E_1 = 2; [L48] int E_2 = 2; [L49] int E_3 = 2; [L50] int E_4 = 2; [L51] int E_5 = 2; [L52] int E_6 = 2; [L53] int E_7 = 2; [L63] int token ; [L65] int local ; [L1225] int __retres1 ; [L1229] CALL init_model() [L1134] m_i = 1 [L1135] t1_i = 1 [L1136] t2_i = 1 [L1137] t3_i = 1 [L1138] t4_i = 1 [L1139] t5_i = 1 [L1140] t6_i = 1 [L1141] RET t7_i = 1 [L1229] init_model() [L1230] CALL start_simulation() [L1166] int kernel_st ; [L1167] int tmp ; [L1168] int tmp___0 ; [L1172] kernel_st = 0 [L1173] FCALL update_channels() [L1174] CALL init_threads() [L538] COND TRUE m_i == 1 [L539] m_st = 0 [L543] COND TRUE t1_i == 1 [L544] t1_st = 0 [L548] COND TRUE t2_i == 1 [L549] t2_st = 0 [L553] COND TRUE t3_i == 1 [L554] t3_st = 0 [L558] COND TRUE t4_i == 1 [L559] t4_st = 0 [L563] COND TRUE t5_i == 1 [L564] t5_st = 0 [L568] COND TRUE t6_i == 1 [L569] t6_st = 0 [L573] COND TRUE t7_i == 1 [L574] RET t7_st = 0 [L1174] init_threads() [L1175] CALL fire_delta_events() [L771] COND FALSE !(M_E == 0) [L776] COND FALSE !(T1_E == 0) [L781] COND FALSE !(T2_E == 0) [L786] COND FALSE !(T3_E == 0) [L791] COND FALSE !(T4_E == 0) [L796] COND FALSE !(T5_E == 0) [L801] COND FALSE !(T6_E == 0) [L806] COND FALSE !(T7_E == 0) [L811] COND FALSE !(E_M == 0) [L816] COND FALSE !(E_1 == 0) [L821] COND FALSE !(E_2 == 0) [L826] COND FALSE !(E_3 == 0) [L831] COND FALSE !(E_4 == 0) [L836] COND FALSE !(E_5 == 0) [L841] COND FALSE !(E_6 == 0) [L846] COND FALSE, RET !(E_7 == 0) [L1175] fire_delta_events() [L1176] CALL activate_threads() [L944] int tmp ; [L945] int tmp___0 ; [L946] int tmp___1 ; [L947] int tmp___2 ; [L948] int tmp___3 ; [L949] int tmp___4 ; [L950] int tmp___5 ; [L951] int tmp___6 ; [L955] CALL, EXPR is_master_triggered() [L375] int __retres1 ; [L378] COND FALSE !(m_pc == 1) [L388] __retres1 = 0 [L390] RET return (__retres1); [L955] EXPR is_master_triggered() [L955] tmp = is_master_triggered() [L957] COND FALSE !(\read(tmp)) [L963] CALL, EXPR is_transmit1_triggered() [L394] int __retres1 ; [L397] COND FALSE !(t1_pc == 1) [L407] __retres1 = 0 [L409] RET return (__retres1); [L963] EXPR is_transmit1_triggered() [L963] tmp___0 = is_transmit1_triggered() [L965] COND FALSE !(\read(tmp___0)) [L971] CALL, EXPR is_transmit2_triggered() [L413] int __retres1 ; [L416] COND FALSE !(t2_pc == 1) [L426] __retres1 = 0 [L428] RET return (__retres1); [L971] EXPR is_transmit2_triggered() [L971] tmp___1 = is_transmit2_triggered() [L973] COND FALSE !(\read(tmp___1)) [L979] CALL, EXPR is_transmit3_triggered() [L432] int __retres1 ; [L435] COND FALSE !(t3_pc == 1) [L445] __retres1 = 0 [L447] RET return (__retres1); [L979] EXPR is_transmit3_triggered() [L979] tmp___2 = is_transmit3_triggered() [L981] COND FALSE !(\read(tmp___2)) [L987] CALL, EXPR is_transmit4_triggered() [L451] int __retres1 ; [L454] COND FALSE !(t4_pc == 1) [L464] __retres1 = 0 [L466] RET return (__retres1); [L987] EXPR is_transmit4_triggered() [L987] tmp___3 = is_transmit4_triggered() [L989] COND FALSE !(\read(tmp___3)) [L995] CALL, EXPR is_transmit5_triggered() [L470] int __retres1 ; [L473] COND FALSE !(t5_pc == 1) [L483] __retres1 = 0 [L485] RET return (__retres1); [L995] EXPR is_transmit5_triggered() [L995] tmp___4 = is_transmit5_triggered() [L997] COND FALSE !(\read(tmp___4)) [L1003] CALL, EXPR is_transmit6_triggered() [L489] int __retres1 ; [L492] COND FALSE !(t6_pc == 1) [L502] __retres1 = 0 [L504] RET return (__retres1); [L1003] EXPR is_transmit6_triggered() [L1003] tmp___5 = is_transmit6_triggered() [L1005] COND FALSE !(\read(tmp___5)) [L1011] CALL, EXPR is_transmit7_triggered() [L508] int __retres1 ; [L511] COND FALSE !(t7_pc == 1) [L521] __retres1 = 0 [L523] RET return (__retres1); [L1011] EXPR is_transmit7_triggered() [L1011] tmp___6 = is_transmit7_triggered() [L1013] COND FALSE, RET !(\read(tmp___6)) [L1176] activate_threads() [L1177] CALL reset_delta_events() [L859] COND FALSE !(M_E == 1) [L864] COND FALSE !(T1_E == 1) [L869] COND FALSE !(T2_E == 1) [L874] COND FALSE !(T3_E == 1) [L879] COND FALSE !(T4_E == 1) [L884] COND FALSE !(T5_E == 1) [L889] COND FALSE !(T6_E == 1) [L894] COND FALSE !(T7_E == 1) [L899] COND FALSE !(E_M == 1) [L904] COND FALSE !(E_1 == 1) [L909] COND FALSE !(E_2 == 1) [L914] COND FALSE !(E_3 == 1) [L919] COND FALSE !(E_4 == 1) [L924] COND FALSE !(E_5 == 1) [L929] COND FALSE !(E_6 == 1) [L934] COND FALSE, RET !(E_7 == 1) [L1177] reset_delta_events() [L1180] COND TRUE 1 [L1183] kernel_st = 1 [L1184] CALL eval() [L634] int tmp ; Loop: [L638] COND TRUE 1 [L641] CALL, EXPR exists_runnable_thread() [L583] int __retres1 ; [L586] COND TRUE m_st == 0 [L587] __retres1 = 1 [L629] RET return (__retres1); [L641] EXPR exists_runnable_thread() [L641] tmp = exists_runnable_thread() [L643] COND TRUE \read(tmp) [L648] COND TRUE m_st == 0 [L649] int tmp_ndt_1; [L650] tmp_ndt_1 = __VERIFIER_nondet_int() [L651] COND FALSE !(\read(tmp_ndt_1)) [L662] COND TRUE t1_st == 0 [L663] int tmp_ndt_2; [L664] tmp_ndt_2 = __VERIFIER_nondet_int() [L665] COND FALSE !(\read(tmp_ndt_2)) [L676] COND TRUE t2_st == 0 [L677] int tmp_ndt_3; [L678] tmp_ndt_3 = __VERIFIER_nondet_int() [L679] COND FALSE !(\read(tmp_ndt_3)) [L690] COND TRUE t3_st == 0 [L691] int tmp_ndt_4; [L692] tmp_ndt_4 = __VERIFIER_nondet_int() [L693] COND FALSE !(\read(tmp_ndt_4)) [L704] COND TRUE t4_st == 0 [L705] int tmp_ndt_5; [L706] tmp_ndt_5 = __VERIFIER_nondet_int() [L707] COND FALSE !(\read(tmp_ndt_5)) [L718] COND TRUE t5_st == 0 [L719] int tmp_ndt_6; [L720] tmp_ndt_6 = __VERIFIER_nondet_int() [L721] COND FALSE !(\read(tmp_ndt_6)) [L732] COND TRUE t6_st == 0 [L733] int tmp_ndt_7; [L734] tmp_ndt_7 = __VERIFIER_nondet_int() [L735] COND FALSE !(\read(tmp_ndt_7)) [L746] COND TRUE t7_st == 0 [L747] int tmp_ndt_8; [L748] tmp_ndt_8 = __VERIFIER_nondet_int() [L749] COND FALSE !(\read(tmp_ndt_8)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...